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85208be0 ED |
1 | /* |
2 | * Copyright © 2012 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS | |
21 | * IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: | |
24 | * Eugeni Dodonov <eugeni.dodonov@intel.com> | |
25 | * | |
26 | */ | |
27 | ||
2b4e57bd | 28 | #include <linux/cpufreq.h> |
85208be0 ED |
29 | #include "i915_drv.h" |
30 | #include "intel_drv.h" | |
eb48eb00 DV |
31 | #include "../../../platform/x86/intel_ips.h" |
32 | #include <linux/module.h> | |
85208be0 | 33 | |
dc39fff7 BW |
34 | /** |
35 | * RC6 is a special power stage which allows the GPU to enter an very | |
36 | * low-voltage mode when idle, using down to 0V while at this stage. This | |
37 | * stage is entered automatically when the GPU is idle when RC6 support is | |
38 | * enabled, and as soon as new workload arises GPU wakes up automatically as well. | |
39 | * | |
40 | * There are different RC6 modes available in Intel GPU, which differentiate | |
41 | * among each other with the latency required to enter and leave RC6 and | |
42 | * voltage consumed by the GPU in different states. | |
43 | * | |
44 | * The combination of the following flags define which states GPU is allowed | |
45 | * to enter, while RC6 is the normal RC6 state, RC6p is the deep RC6, and | |
46 | * RC6pp is deepest RC6. Their support by hardware varies according to the | |
47 | * GPU, BIOS, chipset and platform. RC6 is usually the safest one and the one | |
48 | * which brings the most power savings; deeper states save more power, but | |
49 | * require higher latency to switch to and wake up. | |
50 | */ | |
51 | #define INTEL_RC6_ENABLE (1<<0) | |
52 | #define INTEL_RC6p_ENABLE (1<<1) | |
53 | #define INTEL_RC6pp_ENABLE (1<<2) | |
54 | ||
da2078cd DL |
55 | static void gen9_init_clock_gating(struct drm_device *dev) |
56 | { | |
acd5c346 DL |
57 | struct drm_i915_private *dev_priv = dev->dev_private; |
58 | ||
77719d28 DL |
59 | /* WaEnableLbsSlaRetryTimerDecrement:skl */ |
60 | I915_WRITE(BDW_SCRATCH1, I915_READ(BDW_SCRATCH1) | | |
61 | GEN9_LBS_SLA_RETRY_TIMER_DECREMENT_ENABLE); | |
62 | } | |
91e41d16 | 63 | |
45db2194 | 64 | static void skl_init_clock_gating(struct drm_device *dev) |
da2078cd | 65 | { |
acd5c346 | 66 | struct drm_i915_private *dev_priv = dev->dev_private; |
3ca5da43 | 67 | |
77719d28 DL |
68 | gen9_init_clock_gating(dev); |
69 | ||
669506e7 | 70 | if (INTEL_REVID(dev) <= SKL_REVID_B0) { |
3dcd020a HN |
71 | /* |
72 | * WaDisableSDEUnitClockGating:skl | |
9253c2e5 | 73 | * WaSetGAPSunitClckGateDisable:skl |
3dcd020a HN |
74 | */ |
75 | I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) | | |
9253c2e5 | 76 | GEN8_GAPSUNIT_CLOCK_GATE_DISABLE | |
3dcd020a | 77 | GEN8_SDEUNIT_CLOCK_GATE_DISABLE); |
f9fc42f4 DL |
78 | |
79 | /* WaDisableVFUnitClockGating:skl */ | |
80 | I915_WRITE(GEN6_UCGCTL2, I915_READ(GEN6_UCGCTL2) | | |
81 | GEN6_VFUNIT_CLOCK_GATE_DISABLE); | |
3dcd020a | 82 | } |
8bc0ccf6 | 83 | |
2caa3b26 | 84 | if (INTEL_REVID(dev) <= SKL_REVID_D0) { |
81e231af DL |
85 | /* WaDisableHDCInvalidation:skl */ |
86 | I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | | |
87 | BDW_DISABLE_HDC_INVALIDATION); | |
88 | ||
2caa3b26 DL |
89 | /* WaDisableChickenBitTSGBarrierAckForFFSliceCS:skl */ |
90 | I915_WRITE(FF_SLICE_CS_CHICKEN2, | |
f1d3d34d | 91 | _MASKED_BIT_ENABLE(GEN9_TSG_BARRIER_ACK_DISABLE)); |
2caa3b26 | 92 | } |
81e231af | 93 | |
8bc0ccf6 DL |
94 | if (INTEL_REVID(dev) <= SKL_REVID_E0) |
95 | /* WaDisableLSQCROPERFforOCL:skl */ | |
96 | I915_WRITE(GEN8_L3SQCREG4, I915_READ(GEN8_L3SQCREG4) | | |
97 | GEN8_LQSC_RO_PERF_DIS); | |
da2078cd DL |
98 | } |
99 | ||
a82abe43 ID |
100 | static void bxt_init_clock_gating(struct drm_device *dev) |
101 | { | |
32608ca2 ID |
102 | struct drm_i915_private *dev_priv = dev->dev_private; |
103 | ||
a82abe43 | 104 | gen9_init_clock_gating(dev); |
32608ca2 ID |
105 | |
106 | /* | |
107 | * FIXME: | |
108 | * GEN8_SDEUNIT_CLOCK_GATE_DISABLE applies on A0 only. | |
868434c5 | 109 | * GEN8_HDCUNIT_CLOCK_GATE_DISABLE_HDCREQ applies on 3x6 GT SKUs only. |
32608ca2 ID |
110 | */ |
111 | /* WaDisableSDEUnitClockGating:bxt */ | |
112 | I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) | | |
868434c5 BW |
113 | GEN8_SDEUNIT_CLOCK_GATE_DISABLE | |
114 | GEN8_HDCUNIT_CLOCK_GATE_DISABLE_HDCREQ); | |
32608ca2 | 115 | |
e3a29055 RB |
116 | /* FIXME: apply on A0 only */ |
117 | I915_WRITE(TILECTL, I915_READ(TILECTL) | TILECTL_TLBPF); | |
a82abe43 ID |
118 | } |
119 | ||
c921aba8 DV |
120 | static void i915_pineview_get_mem_freq(struct drm_device *dev) |
121 | { | |
50227e1c | 122 | struct drm_i915_private *dev_priv = dev->dev_private; |
c921aba8 DV |
123 | u32 tmp; |
124 | ||
125 | tmp = I915_READ(CLKCFG); | |
126 | ||
127 | switch (tmp & CLKCFG_FSB_MASK) { | |
128 | case CLKCFG_FSB_533: | |
129 | dev_priv->fsb_freq = 533; /* 133*4 */ | |
130 | break; | |
131 | case CLKCFG_FSB_800: | |
132 | dev_priv->fsb_freq = 800; /* 200*4 */ | |
133 | break; | |
134 | case CLKCFG_FSB_667: | |
135 | dev_priv->fsb_freq = 667; /* 167*4 */ | |
136 | break; | |
137 | case CLKCFG_FSB_400: | |
138 | dev_priv->fsb_freq = 400; /* 100*4 */ | |
139 | break; | |
140 | } | |
141 | ||
142 | switch (tmp & CLKCFG_MEM_MASK) { | |
143 | case CLKCFG_MEM_533: | |
144 | dev_priv->mem_freq = 533; | |
145 | break; | |
146 | case CLKCFG_MEM_667: | |
147 | dev_priv->mem_freq = 667; | |
148 | break; | |
149 | case CLKCFG_MEM_800: | |
150 | dev_priv->mem_freq = 800; | |
151 | break; | |
152 | } | |
153 | ||
154 | /* detect pineview DDR3 setting */ | |
155 | tmp = I915_READ(CSHRDDR3CTL); | |
156 | dev_priv->is_ddr3 = (tmp & CSHRDDR3CTL_DDR3) ? 1 : 0; | |
157 | } | |
158 | ||
159 | static void i915_ironlake_get_mem_freq(struct drm_device *dev) | |
160 | { | |
50227e1c | 161 | struct drm_i915_private *dev_priv = dev->dev_private; |
c921aba8 DV |
162 | u16 ddrpll, csipll; |
163 | ||
164 | ddrpll = I915_READ16(DDRMPLL1); | |
165 | csipll = I915_READ16(CSIPLL0); | |
166 | ||
167 | switch (ddrpll & 0xff) { | |
168 | case 0xc: | |
169 | dev_priv->mem_freq = 800; | |
170 | break; | |
171 | case 0x10: | |
172 | dev_priv->mem_freq = 1066; | |
173 | break; | |
174 | case 0x14: | |
175 | dev_priv->mem_freq = 1333; | |
176 | break; | |
177 | case 0x18: | |
178 | dev_priv->mem_freq = 1600; | |
179 | break; | |
180 | default: | |
181 | DRM_DEBUG_DRIVER("unknown memory frequency 0x%02x\n", | |
182 | ddrpll & 0xff); | |
183 | dev_priv->mem_freq = 0; | |
184 | break; | |
185 | } | |
186 | ||
20e4d407 | 187 | dev_priv->ips.r_t = dev_priv->mem_freq; |
c921aba8 DV |
188 | |
189 | switch (csipll & 0x3ff) { | |
190 | case 0x00c: | |
191 | dev_priv->fsb_freq = 3200; | |
192 | break; | |
193 | case 0x00e: | |
194 | dev_priv->fsb_freq = 3733; | |
195 | break; | |
196 | case 0x010: | |
197 | dev_priv->fsb_freq = 4266; | |
198 | break; | |
199 | case 0x012: | |
200 | dev_priv->fsb_freq = 4800; | |
201 | break; | |
202 | case 0x014: | |
203 | dev_priv->fsb_freq = 5333; | |
204 | break; | |
205 | case 0x016: | |
206 | dev_priv->fsb_freq = 5866; | |
207 | break; | |
208 | case 0x018: | |
209 | dev_priv->fsb_freq = 6400; | |
210 | break; | |
211 | default: | |
212 | DRM_DEBUG_DRIVER("unknown fsb frequency 0x%04x\n", | |
213 | csipll & 0x3ff); | |
214 | dev_priv->fsb_freq = 0; | |
215 | break; | |
216 | } | |
217 | ||
218 | if (dev_priv->fsb_freq == 3200) { | |
20e4d407 | 219 | dev_priv->ips.c_m = 0; |
c921aba8 | 220 | } else if (dev_priv->fsb_freq > 3200 && dev_priv->fsb_freq <= 4800) { |
20e4d407 | 221 | dev_priv->ips.c_m = 1; |
c921aba8 | 222 | } else { |
20e4d407 | 223 | dev_priv->ips.c_m = 2; |
c921aba8 DV |
224 | } |
225 | } | |
226 | ||
b445e3b0 ED |
227 | static const struct cxsr_latency cxsr_latency_table[] = { |
228 | {1, 0, 800, 400, 3382, 33382, 3983, 33983}, /* DDR2-400 SC */ | |
229 | {1, 0, 800, 667, 3354, 33354, 3807, 33807}, /* DDR2-667 SC */ | |
230 | {1, 0, 800, 800, 3347, 33347, 3763, 33763}, /* DDR2-800 SC */ | |
231 | {1, 1, 800, 667, 6420, 36420, 6873, 36873}, /* DDR3-667 SC */ | |
232 | {1, 1, 800, 800, 5902, 35902, 6318, 36318}, /* DDR3-800 SC */ | |
233 | ||
234 | {1, 0, 667, 400, 3400, 33400, 4021, 34021}, /* DDR2-400 SC */ | |
235 | {1, 0, 667, 667, 3372, 33372, 3845, 33845}, /* DDR2-667 SC */ | |
236 | {1, 0, 667, 800, 3386, 33386, 3822, 33822}, /* DDR2-800 SC */ | |
237 | {1, 1, 667, 667, 6438, 36438, 6911, 36911}, /* DDR3-667 SC */ | |
238 | {1, 1, 667, 800, 5941, 35941, 6377, 36377}, /* DDR3-800 SC */ | |
239 | ||
240 | {1, 0, 400, 400, 3472, 33472, 4173, 34173}, /* DDR2-400 SC */ | |
241 | {1, 0, 400, 667, 3443, 33443, 3996, 33996}, /* DDR2-667 SC */ | |
242 | {1, 0, 400, 800, 3430, 33430, 3946, 33946}, /* DDR2-800 SC */ | |
243 | {1, 1, 400, 667, 6509, 36509, 7062, 37062}, /* DDR3-667 SC */ | |
244 | {1, 1, 400, 800, 5985, 35985, 6501, 36501}, /* DDR3-800 SC */ | |
245 | ||
246 | {0, 0, 800, 400, 3438, 33438, 4065, 34065}, /* DDR2-400 SC */ | |
247 | {0, 0, 800, 667, 3410, 33410, 3889, 33889}, /* DDR2-667 SC */ | |
248 | {0, 0, 800, 800, 3403, 33403, 3845, 33845}, /* DDR2-800 SC */ | |
249 | {0, 1, 800, 667, 6476, 36476, 6955, 36955}, /* DDR3-667 SC */ | |
250 | {0, 1, 800, 800, 5958, 35958, 6400, 36400}, /* DDR3-800 SC */ | |
251 | ||
252 | {0, 0, 667, 400, 3456, 33456, 4103, 34106}, /* DDR2-400 SC */ | |
253 | {0, 0, 667, 667, 3428, 33428, 3927, 33927}, /* DDR2-667 SC */ | |
254 | {0, 0, 667, 800, 3443, 33443, 3905, 33905}, /* DDR2-800 SC */ | |
255 | {0, 1, 667, 667, 6494, 36494, 6993, 36993}, /* DDR3-667 SC */ | |
256 | {0, 1, 667, 800, 5998, 35998, 6460, 36460}, /* DDR3-800 SC */ | |
257 | ||
258 | {0, 0, 400, 400, 3528, 33528, 4255, 34255}, /* DDR2-400 SC */ | |
259 | {0, 0, 400, 667, 3500, 33500, 4079, 34079}, /* DDR2-667 SC */ | |
260 | {0, 0, 400, 800, 3487, 33487, 4029, 34029}, /* DDR2-800 SC */ | |
261 | {0, 1, 400, 667, 6566, 36566, 7145, 37145}, /* DDR3-667 SC */ | |
262 | {0, 1, 400, 800, 6042, 36042, 6584, 36584}, /* DDR3-800 SC */ | |
263 | }; | |
264 | ||
63c62275 | 265 | static const struct cxsr_latency *intel_get_cxsr_latency(int is_desktop, |
b445e3b0 ED |
266 | int is_ddr3, |
267 | int fsb, | |
268 | int mem) | |
269 | { | |
270 | const struct cxsr_latency *latency; | |
271 | int i; | |
272 | ||
273 | if (fsb == 0 || mem == 0) | |
274 | return NULL; | |
275 | ||
276 | for (i = 0; i < ARRAY_SIZE(cxsr_latency_table); i++) { | |
277 | latency = &cxsr_latency_table[i]; | |
278 | if (is_desktop == latency->is_desktop && | |
279 | is_ddr3 == latency->is_ddr3 && | |
280 | fsb == latency->fsb_freq && mem == latency->mem_freq) | |
281 | return latency; | |
282 | } | |
283 | ||
284 | DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n"); | |
285 | ||
286 | return NULL; | |
287 | } | |
288 | ||
fc1ac8de VS |
289 | static void chv_set_memory_dvfs(struct drm_i915_private *dev_priv, bool enable) |
290 | { | |
291 | u32 val; | |
292 | ||
293 | mutex_lock(&dev_priv->rps.hw_lock); | |
294 | ||
295 | val = vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2); | |
296 | if (enable) | |
297 | val &= ~FORCE_DDR_HIGH_FREQ; | |
298 | else | |
299 | val |= FORCE_DDR_HIGH_FREQ; | |
300 | val &= ~FORCE_DDR_LOW_FREQ; | |
301 | val |= FORCE_DDR_FREQ_REQ_ACK; | |
302 | vlv_punit_write(dev_priv, PUNIT_REG_DDR_SETUP2, val); | |
303 | ||
304 | if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2) & | |
305 | FORCE_DDR_FREQ_REQ_ACK) == 0, 3)) | |
306 | DRM_ERROR("timed out waiting for Punit DDR DVFS request\n"); | |
307 | ||
308 | mutex_unlock(&dev_priv->rps.hw_lock); | |
309 | } | |
310 | ||
cfb41411 VS |
311 | static void chv_set_memory_pm5(struct drm_i915_private *dev_priv, bool enable) |
312 | { | |
313 | u32 val; | |
314 | ||
315 | mutex_lock(&dev_priv->rps.hw_lock); | |
316 | ||
317 | val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ); | |
318 | if (enable) | |
319 | val |= DSP_MAXFIFO_PM5_ENABLE; | |
320 | else | |
321 | val &= ~DSP_MAXFIFO_PM5_ENABLE; | |
322 | vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val); | |
323 | ||
324 | mutex_unlock(&dev_priv->rps.hw_lock); | |
325 | } | |
326 | ||
f4998963 VS |
327 | #define FW_WM(value, plane) \ |
328 | (((value) << DSPFW_ ## plane ## _SHIFT) & DSPFW_ ## plane ## _MASK) | |
329 | ||
5209b1f4 | 330 | void intel_set_memory_cxsr(struct drm_i915_private *dev_priv, bool enable) |
b445e3b0 | 331 | { |
5209b1f4 ID |
332 | struct drm_device *dev = dev_priv->dev; |
333 | u32 val; | |
b445e3b0 | 334 | |
5209b1f4 ID |
335 | if (IS_VALLEYVIEW(dev)) { |
336 | I915_WRITE(FW_BLC_SELF_VLV, enable ? FW_CSPWRDWNEN : 0); | |
a7a6c498 | 337 | POSTING_READ(FW_BLC_SELF_VLV); |
cfb41411 VS |
338 | if (IS_CHERRYVIEW(dev)) |
339 | chv_set_memory_pm5(dev_priv, enable); | |
5209b1f4 ID |
340 | } else if (IS_G4X(dev) || IS_CRESTLINE(dev)) { |
341 | I915_WRITE(FW_BLC_SELF, enable ? FW_BLC_SELF_EN : 0); | |
a7a6c498 | 342 | POSTING_READ(FW_BLC_SELF); |
5209b1f4 ID |
343 | } else if (IS_PINEVIEW(dev)) { |
344 | val = I915_READ(DSPFW3) & ~PINEVIEW_SELF_REFRESH_EN; | |
345 | val |= enable ? PINEVIEW_SELF_REFRESH_EN : 0; | |
346 | I915_WRITE(DSPFW3, val); | |
a7a6c498 | 347 | POSTING_READ(DSPFW3); |
5209b1f4 ID |
348 | } else if (IS_I945G(dev) || IS_I945GM(dev)) { |
349 | val = enable ? _MASKED_BIT_ENABLE(FW_BLC_SELF_EN) : | |
350 | _MASKED_BIT_DISABLE(FW_BLC_SELF_EN); | |
351 | I915_WRITE(FW_BLC_SELF, val); | |
a7a6c498 | 352 | POSTING_READ(FW_BLC_SELF); |
5209b1f4 ID |
353 | } else if (IS_I915GM(dev)) { |
354 | val = enable ? _MASKED_BIT_ENABLE(INSTPM_SELF_EN) : | |
355 | _MASKED_BIT_DISABLE(INSTPM_SELF_EN); | |
356 | I915_WRITE(INSTPM, val); | |
a7a6c498 | 357 | POSTING_READ(INSTPM); |
5209b1f4 ID |
358 | } else { |
359 | return; | |
360 | } | |
b445e3b0 | 361 | |
5209b1f4 ID |
362 | DRM_DEBUG_KMS("memory self-refresh is %s\n", |
363 | enable ? "enabled" : "disabled"); | |
b445e3b0 ED |
364 | } |
365 | ||
fc1ac8de | 366 | |
b445e3b0 ED |
367 | /* |
368 | * Latency for FIFO fetches is dependent on several factors: | |
369 | * - memory configuration (speed, channels) | |
370 | * - chipset | |
371 | * - current MCH state | |
372 | * It can be fairly high in some situations, so here we assume a fairly | |
373 | * pessimal value. It's a tradeoff between extra memory fetches (if we | |
374 | * set this value too high, the FIFO will fetch frequently to stay full) | |
375 | * and power consumption (set it too low to save power and we might see | |
376 | * FIFO underruns and display "flicker"). | |
377 | * | |
378 | * A value of 5us seems to be a good balance; safe for very low end | |
379 | * platforms but not overly aggressive on lower latency configs. | |
380 | */ | |
5aef6003 | 381 | static const int pessimal_latency_ns = 5000; |
b445e3b0 | 382 | |
b5004720 VS |
383 | #define VLV_FIFO_START(dsparb, dsparb2, lo_shift, hi_shift) \ |
384 | ((((dsparb) >> (lo_shift)) & 0xff) | ((((dsparb2) >> (hi_shift)) & 0x1) << 8)) | |
385 | ||
386 | static int vlv_get_fifo_size(struct drm_device *dev, | |
387 | enum pipe pipe, int plane) | |
388 | { | |
389 | struct drm_i915_private *dev_priv = dev->dev_private; | |
390 | int sprite0_start, sprite1_start, size; | |
391 | ||
392 | switch (pipe) { | |
393 | uint32_t dsparb, dsparb2, dsparb3; | |
394 | case PIPE_A: | |
395 | dsparb = I915_READ(DSPARB); | |
396 | dsparb2 = I915_READ(DSPARB2); | |
397 | sprite0_start = VLV_FIFO_START(dsparb, dsparb2, 0, 0); | |
398 | sprite1_start = VLV_FIFO_START(dsparb, dsparb2, 8, 4); | |
399 | break; | |
400 | case PIPE_B: | |
401 | dsparb = I915_READ(DSPARB); | |
402 | dsparb2 = I915_READ(DSPARB2); | |
403 | sprite0_start = VLV_FIFO_START(dsparb, dsparb2, 16, 8); | |
404 | sprite1_start = VLV_FIFO_START(dsparb, dsparb2, 24, 12); | |
405 | break; | |
406 | case PIPE_C: | |
407 | dsparb2 = I915_READ(DSPARB2); | |
408 | dsparb3 = I915_READ(DSPARB3); | |
409 | sprite0_start = VLV_FIFO_START(dsparb3, dsparb2, 0, 16); | |
410 | sprite1_start = VLV_FIFO_START(dsparb3, dsparb2, 8, 20); | |
411 | break; | |
412 | default: | |
413 | return 0; | |
414 | } | |
415 | ||
416 | switch (plane) { | |
417 | case 0: | |
418 | size = sprite0_start; | |
419 | break; | |
420 | case 1: | |
421 | size = sprite1_start - sprite0_start; | |
422 | break; | |
423 | case 2: | |
424 | size = 512 - 1 - sprite1_start; | |
425 | break; | |
426 | default: | |
427 | return 0; | |
428 | } | |
429 | ||
430 | DRM_DEBUG_KMS("Pipe %c %s %c FIFO size: %d\n", | |
431 | pipe_name(pipe), plane == 0 ? "primary" : "sprite", | |
432 | plane == 0 ? plane_name(pipe) : sprite_name(pipe, plane - 1), | |
433 | size); | |
434 | ||
435 | return size; | |
436 | } | |
437 | ||
1fa61106 | 438 | static int i9xx_get_fifo_size(struct drm_device *dev, int plane) |
b445e3b0 ED |
439 | { |
440 | struct drm_i915_private *dev_priv = dev->dev_private; | |
441 | uint32_t dsparb = I915_READ(DSPARB); | |
442 | int size; | |
443 | ||
444 | size = dsparb & 0x7f; | |
445 | if (plane) | |
446 | size = ((dsparb >> DSPARB_CSTART_SHIFT) & 0x7f) - size; | |
447 | ||
448 | DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb, | |
449 | plane ? "B" : "A", size); | |
450 | ||
451 | return size; | |
452 | } | |
453 | ||
feb56b93 | 454 | static int i830_get_fifo_size(struct drm_device *dev, int plane) |
b445e3b0 ED |
455 | { |
456 | struct drm_i915_private *dev_priv = dev->dev_private; | |
457 | uint32_t dsparb = I915_READ(DSPARB); | |
458 | int size; | |
459 | ||
460 | size = dsparb & 0x1ff; | |
461 | if (plane) | |
462 | size = ((dsparb >> DSPARB_BEND_SHIFT) & 0x1ff) - size; | |
463 | size >>= 1; /* Convert to cachelines */ | |
464 | ||
465 | DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb, | |
466 | plane ? "B" : "A", size); | |
467 | ||
468 | return size; | |
469 | } | |
470 | ||
1fa61106 | 471 | static int i845_get_fifo_size(struct drm_device *dev, int plane) |
b445e3b0 ED |
472 | { |
473 | struct drm_i915_private *dev_priv = dev->dev_private; | |
474 | uint32_t dsparb = I915_READ(DSPARB); | |
475 | int size; | |
476 | ||
477 | size = dsparb & 0x7f; | |
478 | size >>= 2; /* Convert to cachelines */ | |
479 | ||
480 | DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb, | |
481 | plane ? "B" : "A", | |
482 | size); | |
483 | ||
484 | return size; | |
485 | } | |
486 | ||
b445e3b0 ED |
487 | /* Pineview has different values for various configs */ |
488 | static const struct intel_watermark_params pineview_display_wm = { | |
e0f0273e VS |
489 | .fifo_size = PINEVIEW_DISPLAY_FIFO, |
490 | .max_wm = PINEVIEW_MAX_WM, | |
491 | .default_wm = PINEVIEW_DFT_WM, | |
492 | .guard_size = PINEVIEW_GUARD_WM, | |
493 | .cacheline_size = PINEVIEW_FIFO_LINE_SIZE, | |
b445e3b0 ED |
494 | }; |
495 | static const struct intel_watermark_params pineview_display_hplloff_wm = { | |
e0f0273e VS |
496 | .fifo_size = PINEVIEW_DISPLAY_FIFO, |
497 | .max_wm = PINEVIEW_MAX_WM, | |
498 | .default_wm = PINEVIEW_DFT_HPLLOFF_WM, | |
499 | .guard_size = PINEVIEW_GUARD_WM, | |
500 | .cacheline_size = PINEVIEW_FIFO_LINE_SIZE, | |
b445e3b0 ED |
501 | }; |
502 | static const struct intel_watermark_params pineview_cursor_wm = { | |
e0f0273e VS |
503 | .fifo_size = PINEVIEW_CURSOR_FIFO, |
504 | .max_wm = PINEVIEW_CURSOR_MAX_WM, | |
505 | .default_wm = PINEVIEW_CURSOR_DFT_WM, | |
506 | .guard_size = PINEVIEW_CURSOR_GUARD_WM, | |
507 | .cacheline_size = PINEVIEW_FIFO_LINE_SIZE, | |
b445e3b0 ED |
508 | }; |
509 | static const struct intel_watermark_params pineview_cursor_hplloff_wm = { | |
e0f0273e VS |
510 | .fifo_size = PINEVIEW_CURSOR_FIFO, |
511 | .max_wm = PINEVIEW_CURSOR_MAX_WM, | |
512 | .default_wm = PINEVIEW_CURSOR_DFT_WM, | |
513 | .guard_size = PINEVIEW_CURSOR_GUARD_WM, | |
514 | .cacheline_size = PINEVIEW_FIFO_LINE_SIZE, | |
b445e3b0 ED |
515 | }; |
516 | static const struct intel_watermark_params g4x_wm_info = { | |
e0f0273e VS |
517 | .fifo_size = G4X_FIFO_SIZE, |
518 | .max_wm = G4X_MAX_WM, | |
519 | .default_wm = G4X_MAX_WM, | |
520 | .guard_size = 2, | |
521 | .cacheline_size = G4X_FIFO_LINE_SIZE, | |
b445e3b0 ED |
522 | }; |
523 | static const struct intel_watermark_params g4x_cursor_wm_info = { | |
e0f0273e VS |
524 | .fifo_size = I965_CURSOR_FIFO, |
525 | .max_wm = I965_CURSOR_MAX_WM, | |
526 | .default_wm = I965_CURSOR_DFT_WM, | |
527 | .guard_size = 2, | |
528 | .cacheline_size = G4X_FIFO_LINE_SIZE, | |
b445e3b0 ED |
529 | }; |
530 | static const struct intel_watermark_params valleyview_wm_info = { | |
e0f0273e VS |
531 | .fifo_size = VALLEYVIEW_FIFO_SIZE, |
532 | .max_wm = VALLEYVIEW_MAX_WM, | |
533 | .default_wm = VALLEYVIEW_MAX_WM, | |
534 | .guard_size = 2, | |
535 | .cacheline_size = G4X_FIFO_LINE_SIZE, | |
b445e3b0 ED |
536 | }; |
537 | static const struct intel_watermark_params valleyview_cursor_wm_info = { | |
e0f0273e VS |
538 | .fifo_size = I965_CURSOR_FIFO, |
539 | .max_wm = VALLEYVIEW_CURSOR_MAX_WM, | |
540 | .default_wm = I965_CURSOR_DFT_WM, | |
541 | .guard_size = 2, | |
542 | .cacheline_size = G4X_FIFO_LINE_SIZE, | |
b445e3b0 ED |
543 | }; |
544 | static const struct intel_watermark_params i965_cursor_wm_info = { | |
e0f0273e VS |
545 | .fifo_size = I965_CURSOR_FIFO, |
546 | .max_wm = I965_CURSOR_MAX_WM, | |
547 | .default_wm = I965_CURSOR_DFT_WM, | |
548 | .guard_size = 2, | |
549 | .cacheline_size = I915_FIFO_LINE_SIZE, | |
b445e3b0 ED |
550 | }; |
551 | static const struct intel_watermark_params i945_wm_info = { | |
e0f0273e VS |
552 | .fifo_size = I945_FIFO_SIZE, |
553 | .max_wm = I915_MAX_WM, | |
554 | .default_wm = 1, | |
555 | .guard_size = 2, | |
556 | .cacheline_size = I915_FIFO_LINE_SIZE, | |
b445e3b0 ED |
557 | }; |
558 | static const struct intel_watermark_params i915_wm_info = { | |
e0f0273e VS |
559 | .fifo_size = I915_FIFO_SIZE, |
560 | .max_wm = I915_MAX_WM, | |
561 | .default_wm = 1, | |
562 | .guard_size = 2, | |
563 | .cacheline_size = I915_FIFO_LINE_SIZE, | |
b445e3b0 | 564 | }; |
9d539105 | 565 | static const struct intel_watermark_params i830_a_wm_info = { |
e0f0273e VS |
566 | .fifo_size = I855GM_FIFO_SIZE, |
567 | .max_wm = I915_MAX_WM, | |
568 | .default_wm = 1, | |
569 | .guard_size = 2, | |
570 | .cacheline_size = I830_FIFO_LINE_SIZE, | |
b445e3b0 | 571 | }; |
9d539105 VS |
572 | static const struct intel_watermark_params i830_bc_wm_info = { |
573 | .fifo_size = I855GM_FIFO_SIZE, | |
574 | .max_wm = I915_MAX_WM/2, | |
575 | .default_wm = 1, | |
576 | .guard_size = 2, | |
577 | .cacheline_size = I830_FIFO_LINE_SIZE, | |
578 | }; | |
feb56b93 | 579 | static const struct intel_watermark_params i845_wm_info = { |
e0f0273e VS |
580 | .fifo_size = I830_FIFO_SIZE, |
581 | .max_wm = I915_MAX_WM, | |
582 | .default_wm = 1, | |
583 | .guard_size = 2, | |
584 | .cacheline_size = I830_FIFO_LINE_SIZE, | |
b445e3b0 ED |
585 | }; |
586 | ||
b445e3b0 ED |
587 | /** |
588 | * intel_calculate_wm - calculate watermark level | |
589 | * @clock_in_khz: pixel clock | |
590 | * @wm: chip FIFO params | |
591 | * @pixel_size: display pixel size | |
592 | * @latency_ns: memory latency for the platform | |
593 | * | |
594 | * Calculate the watermark level (the level at which the display plane will | |
595 | * start fetching from memory again). Each chip has a different display | |
596 | * FIFO size and allocation, so the caller needs to figure that out and pass | |
597 | * in the correct intel_watermark_params structure. | |
598 | * | |
599 | * As the pixel clock runs, the FIFO will be drained at a rate that depends | |
600 | * on the pixel size. When it reaches the watermark level, it'll start | |
601 | * fetching FIFO line sized based chunks from memory until the FIFO fills | |
602 | * past the watermark point. If the FIFO drains completely, a FIFO underrun | |
603 | * will occur, and a display engine hang could result. | |
604 | */ | |
605 | static unsigned long intel_calculate_wm(unsigned long clock_in_khz, | |
606 | const struct intel_watermark_params *wm, | |
607 | int fifo_size, | |
608 | int pixel_size, | |
609 | unsigned long latency_ns) | |
610 | { | |
611 | long entries_required, wm_size; | |
612 | ||
613 | /* | |
614 | * Note: we need to make sure we don't overflow for various clock & | |
615 | * latency values. | |
616 | * clocks go from a few thousand to several hundred thousand. | |
617 | * latency is usually a few thousand | |
618 | */ | |
619 | entries_required = ((clock_in_khz / 1000) * pixel_size * latency_ns) / | |
620 | 1000; | |
621 | entries_required = DIV_ROUND_UP(entries_required, wm->cacheline_size); | |
622 | ||
623 | DRM_DEBUG_KMS("FIFO entries required for mode: %ld\n", entries_required); | |
624 | ||
625 | wm_size = fifo_size - (entries_required + wm->guard_size); | |
626 | ||
627 | DRM_DEBUG_KMS("FIFO watermark level: %ld\n", wm_size); | |
628 | ||
629 | /* Don't promote wm_size to unsigned... */ | |
630 | if (wm_size > (long)wm->max_wm) | |
631 | wm_size = wm->max_wm; | |
632 | if (wm_size <= 0) | |
633 | wm_size = wm->default_wm; | |
d6feb196 VS |
634 | |
635 | /* | |
636 | * Bspec seems to indicate that the value shouldn't be lower than | |
637 | * 'burst size + 1'. Certainly 830 is quite unhappy with low values. | |
638 | * Lets go for 8 which is the burst size since certain platforms | |
639 | * already use a hardcoded 8 (which is what the spec says should be | |
640 | * done). | |
641 | */ | |
642 | if (wm_size <= 8) | |
643 | wm_size = 8; | |
644 | ||
b445e3b0 ED |
645 | return wm_size; |
646 | } | |
647 | ||
648 | static struct drm_crtc *single_enabled_crtc(struct drm_device *dev) | |
649 | { | |
650 | struct drm_crtc *crtc, *enabled = NULL; | |
651 | ||
70e1e0ec | 652 | for_each_crtc(dev, crtc) { |
3490ea5d | 653 | if (intel_crtc_active(crtc)) { |
b445e3b0 ED |
654 | if (enabled) |
655 | return NULL; | |
656 | enabled = crtc; | |
657 | } | |
658 | } | |
659 | ||
660 | return enabled; | |
661 | } | |
662 | ||
46ba614c | 663 | static void pineview_update_wm(struct drm_crtc *unused_crtc) |
b445e3b0 | 664 | { |
46ba614c | 665 | struct drm_device *dev = unused_crtc->dev; |
b445e3b0 ED |
666 | struct drm_i915_private *dev_priv = dev->dev_private; |
667 | struct drm_crtc *crtc; | |
668 | const struct cxsr_latency *latency; | |
669 | u32 reg; | |
670 | unsigned long wm; | |
671 | ||
672 | latency = intel_get_cxsr_latency(IS_PINEVIEW_G(dev), dev_priv->is_ddr3, | |
673 | dev_priv->fsb_freq, dev_priv->mem_freq); | |
674 | if (!latency) { | |
675 | DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n"); | |
5209b1f4 | 676 | intel_set_memory_cxsr(dev_priv, false); |
b445e3b0 ED |
677 | return; |
678 | } | |
679 | ||
680 | crtc = single_enabled_crtc(dev); | |
681 | if (crtc) { | |
241bfc38 | 682 | const struct drm_display_mode *adjusted_mode; |
59bea882 | 683 | int pixel_size = crtc->primary->state->fb->bits_per_pixel / 8; |
241bfc38 DL |
684 | int clock; |
685 | ||
6e3c9717 | 686 | adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode; |
241bfc38 | 687 | clock = adjusted_mode->crtc_clock; |
b445e3b0 ED |
688 | |
689 | /* Display SR */ | |
690 | wm = intel_calculate_wm(clock, &pineview_display_wm, | |
691 | pineview_display_wm.fifo_size, | |
692 | pixel_size, latency->display_sr); | |
693 | reg = I915_READ(DSPFW1); | |
694 | reg &= ~DSPFW_SR_MASK; | |
f4998963 | 695 | reg |= FW_WM(wm, SR); |
b445e3b0 ED |
696 | I915_WRITE(DSPFW1, reg); |
697 | DRM_DEBUG_KMS("DSPFW1 register is %x\n", reg); | |
698 | ||
699 | /* cursor SR */ | |
700 | wm = intel_calculate_wm(clock, &pineview_cursor_wm, | |
701 | pineview_display_wm.fifo_size, | |
702 | pixel_size, latency->cursor_sr); | |
703 | reg = I915_READ(DSPFW3); | |
704 | reg &= ~DSPFW_CURSOR_SR_MASK; | |
f4998963 | 705 | reg |= FW_WM(wm, CURSOR_SR); |
b445e3b0 ED |
706 | I915_WRITE(DSPFW3, reg); |
707 | ||
708 | /* Display HPLL off SR */ | |
709 | wm = intel_calculate_wm(clock, &pineview_display_hplloff_wm, | |
710 | pineview_display_hplloff_wm.fifo_size, | |
711 | pixel_size, latency->display_hpll_disable); | |
712 | reg = I915_READ(DSPFW3); | |
713 | reg &= ~DSPFW_HPLL_SR_MASK; | |
f4998963 | 714 | reg |= FW_WM(wm, HPLL_SR); |
b445e3b0 ED |
715 | I915_WRITE(DSPFW3, reg); |
716 | ||
717 | /* cursor HPLL off SR */ | |
718 | wm = intel_calculate_wm(clock, &pineview_cursor_hplloff_wm, | |
719 | pineview_display_hplloff_wm.fifo_size, | |
720 | pixel_size, latency->cursor_hpll_disable); | |
721 | reg = I915_READ(DSPFW3); | |
722 | reg &= ~DSPFW_HPLL_CURSOR_MASK; | |
f4998963 | 723 | reg |= FW_WM(wm, HPLL_CURSOR); |
b445e3b0 ED |
724 | I915_WRITE(DSPFW3, reg); |
725 | DRM_DEBUG_KMS("DSPFW3 register is %x\n", reg); | |
726 | ||
5209b1f4 | 727 | intel_set_memory_cxsr(dev_priv, true); |
b445e3b0 | 728 | } else { |
5209b1f4 | 729 | intel_set_memory_cxsr(dev_priv, false); |
b445e3b0 ED |
730 | } |
731 | } | |
732 | ||
733 | static bool g4x_compute_wm0(struct drm_device *dev, | |
734 | int plane, | |
735 | const struct intel_watermark_params *display, | |
736 | int display_latency_ns, | |
737 | const struct intel_watermark_params *cursor, | |
738 | int cursor_latency_ns, | |
739 | int *plane_wm, | |
740 | int *cursor_wm) | |
741 | { | |
742 | struct drm_crtc *crtc; | |
4fe8590a | 743 | const struct drm_display_mode *adjusted_mode; |
b445e3b0 ED |
744 | int htotal, hdisplay, clock, pixel_size; |
745 | int line_time_us, line_count; | |
746 | int entries, tlb_miss; | |
747 | ||
748 | crtc = intel_get_crtc_for_plane(dev, plane); | |
3490ea5d | 749 | if (!intel_crtc_active(crtc)) { |
b445e3b0 ED |
750 | *cursor_wm = cursor->guard_size; |
751 | *plane_wm = display->guard_size; | |
752 | return false; | |
753 | } | |
754 | ||
6e3c9717 | 755 | adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode; |
241bfc38 | 756 | clock = adjusted_mode->crtc_clock; |
fec8cba3 | 757 | htotal = adjusted_mode->crtc_htotal; |
6e3c9717 | 758 | hdisplay = to_intel_crtc(crtc)->config->pipe_src_w; |
59bea882 | 759 | pixel_size = crtc->primary->state->fb->bits_per_pixel / 8; |
b445e3b0 ED |
760 | |
761 | /* Use the small buffer method to calculate plane watermark */ | |
762 | entries = ((clock * pixel_size / 1000) * display_latency_ns) / 1000; | |
763 | tlb_miss = display->fifo_size*display->cacheline_size - hdisplay * 8; | |
764 | if (tlb_miss > 0) | |
765 | entries += tlb_miss; | |
766 | entries = DIV_ROUND_UP(entries, display->cacheline_size); | |
767 | *plane_wm = entries + display->guard_size; | |
768 | if (*plane_wm > (int)display->max_wm) | |
769 | *plane_wm = display->max_wm; | |
770 | ||
771 | /* Use the large buffer method to calculate cursor watermark */ | |
922044c9 | 772 | line_time_us = max(htotal * 1000 / clock, 1); |
b445e3b0 | 773 | line_count = (cursor_latency_ns / line_time_us + 1000) / 1000; |
3dd512fb | 774 | entries = line_count * crtc->cursor->state->crtc_w * pixel_size; |
b445e3b0 ED |
775 | tlb_miss = cursor->fifo_size*cursor->cacheline_size - hdisplay * 8; |
776 | if (tlb_miss > 0) | |
777 | entries += tlb_miss; | |
778 | entries = DIV_ROUND_UP(entries, cursor->cacheline_size); | |
779 | *cursor_wm = entries + cursor->guard_size; | |
780 | if (*cursor_wm > (int)cursor->max_wm) | |
781 | *cursor_wm = (int)cursor->max_wm; | |
782 | ||
783 | return true; | |
784 | } | |
785 | ||
786 | /* | |
787 | * Check the wm result. | |
788 | * | |
789 | * If any calculated watermark values is larger than the maximum value that | |
790 | * can be programmed into the associated watermark register, that watermark | |
791 | * must be disabled. | |
792 | */ | |
793 | static bool g4x_check_srwm(struct drm_device *dev, | |
794 | int display_wm, int cursor_wm, | |
795 | const struct intel_watermark_params *display, | |
796 | const struct intel_watermark_params *cursor) | |
797 | { | |
798 | DRM_DEBUG_KMS("SR watermark: display plane %d, cursor %d\n", | |
799 | display_wm, cursor_wm); | |
800 | ||
801 | if (display_wm > display->max_wm) { | |
802 | DRM_DEBUG_KMS("display watermark is too large(%d/%ld), disabling\n", | |
803 | display_wm, display->max_wm); | |
804 | return false; | |
805 | } | |
806 | ||
807 | if (cursor_wm > cursor->max_wm) { | |
808 | DRM_DEBUG_KMS("cursor watermark is too large(%d/%ld), disabling\n", | |
809 | cursor_wm, cursor->max_wm); | |
810 | return false; | |
811 | } | |
812 | ||
813 | if (!(display_wm || cursor_wm)) { | |
814 | DRM_DEBUG_KMS("SR latency is 0, disabling\n"); | |
815 | return false; | |
816 | } | |
817 | ||
818 | return true; | |
819 | } | |
820 | ||
821 | static bool g4x_compute_srwm(struct drm_device *dev, | |
822 | int plane, | |
823 | int latency_ns, | |
824 | const struct intel_watermark_params *display, | |
825 | const struct intel_watermark_params *cursor, | |
826 | int *display_wm, int *cursor_wm) | |
827 | { | |
828 | struct drm_crtc *crtc; | |
4fe8590a | 829 | const struct drm_display_mode *adjusted_mode; |
b445e3b0 ED |
830 | int hdisplay, htotal, pixel_size, clock; |
831 | unsigned long line_time_us; | |
832 | int line_count, line_size; | |
833 | int small, large; | |
834 | int entries; | |
835 | ||
836 | if (!latency_ns) { | |
837 | *display_wm = *cursor_wm = 0; | |
838 | return false; | |
839 | } | |
840 | ||
841 | crtc = intel_get_crtc_for_plane(dev, plane); | |
6e3c9717 | 842 | adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode; |
241bfc38 | 843 | clock = adjusted_mode->crtc_clock; |
fec8cba3 | 844 | htotal = adjusted_mode->crtc_htotal; |
6e3c9717 | 845 | hdisplay = to_intel_crtc(crtc)->config->pipe_src_w; |
59bea882 | 846 | pixel_size = crtc->primary->state->fb->bits_per_pixel / 8; |
b445e3b0 | 847 | |
922044c9 | 848 | line_time_us = max(htotal * 1000 / clock, 1); |
b445e3b0 ED |
849 | line_count = (latency_ns / line_time_us + 1000) / 1000; |
850 | line_size = hdisplay * pixel_size; | |
851 | ||
852 | /* Use the minimum of the small and large buffer method for primary */ | |
853 | small = ((clock * pixel_size / 1000) * latency_ns) / 1000; | |
854 | large = line_count * line_size; | |
855 | ||
856 | entries = DIV_ROUND_UP(min(small, large), display->cacheline_size); | |
857 | *display_wm = entries + display->guard_size; | |
858 | ||
859 | /* calculate the self-refresh watermark for display cursor */ | |
3dd512fb | 860 | entries = line_count * pixel_size * crtc->cursor->state->crtc_w; |
b445e3b0 ED |
861 | entries = DIV_ROUND_UP(entries, cursor->cacheline_size); |
862 | *cursor_wm = entries + cursor->guard_size; | |
863 | ||
864 | return g4x_check_srwm(dev, | |
865 | *display_wm, *cursor_wm, | |
866 | display, cursor); | |
867 | } | |
868 | ||
15665979 VS |
869 | #define FW_WM_VLV(value, plane) \ |
870 | (((value) << DSPFW_ ## plane ## _SHIFT) & DSPFW_ ## plane ## _MASK_VLV) | |
871 | ||
0018fda1 VS |
872 | static void vlv_write_wm_values(struct intel_crtc *crtc, |
873 | const struct vlv_wm_values *wm) | |
874 | { | |
875 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); | |
876 | enum pipe pipe = crtc->pipe; | |
877 | ||
878 | I915_WRITE(VLV_DDL(pipe), | |
879 | (wm->ddl[pipe].cursor << DDL_CURSOR_SHIFT) | | |
880 | (wm->ddl[pipe].sprite[1] << DDL_SPRITE_SHIFT(1)) | | |
881 | (wm->ddl[pipe].sprite[0] << DDL_SPRITE_SHIFT(0)) | | |
882 | (wm->ddl[pipe].primary << DDL_PLANE_SHIFT)); | |
883 | ||
ae80152d | 884 | I915_WRITE(DSPFW1, |
15665979 VS |
885 | FW_WM(wm->sr.plane, SR) | |
886 | FW_WM(wm->pipe[PIPE_B].cursor, CURSORB) | | |
887 | FW_WM_VLV(wm->pipe[PIPE_B].primary, PLANEB) | | |
888 | FW_WM_VLV(wm->pipe[PIPE_A].primary, PLANEA)); | |
ae80152d | 889 | I915_WRITE(DSPFW2, |
15665979 VS |
890 | FW_WM_VLV(wm->pipe[PIPE_A].sprite[1], SPRITEB) | |
891 | FW_WM(wm->pipe[PIPE_A].cursor, CURSORA) | | |
892 | FW_WM_VLV(wm->pipe[PIPE_A].sprite[0], SPRITEA)); | |
ae80152d | 893 | I915_WRITE(DSPFW3, |
15665979 | 894 | FW_WM(wm->sr.cursor, CURSOR_SR)); |
ae80152d VS |
895 | |
896 | if (IS_CHERRYVIEW(dev_priv)) { | |
897 | I915_WRITE(DSPFW7_CHV, | |
15665979 VS |
898 | FW_WM_VLV(wm->pipe[PIPE_B].sprite[1], SPRITED) | |
899 | FW_WM_VLV(wm->pipe[PIPE_B].sprite[0], SPRITEC)); | |
ae80152d | 900 | I915_WRITE(DSPFW8_CHV, |
15665979 VS |
901 | FW_WM_VLV(wm->pipe[PIPE_C].sprite[1], SPRITEF) | |
902 | FW_WM_VLV(wm->pipe[PIPE_C].sprite[0], SPRITEE)); | |
ae80152d | 903 | I915_WRITE(DSPFW9_CHV, |
15665979 VS |
904 | FW_WM_VLV(wm->pipe[PIPE_C].primary, PLANEC) | |
905 | FW_WM(wm->pipe[PIPE_C].cursor, CURSORC)); | |
ae80152d | 906 | I915_WRITE(DSPHOWM, |
15665979 VS |
907 | FW_WM(wm->sr.plane >> 9, SR_HI) | |
908 | FW_WM(wm->pipe[PIPE_C].sprite[1] >> 8, SPRITEF_HI) | | |
909 | FW_WM(wm->pipe[PIPE_C].sprite[0] >> 8, SPRITEE_HI) | | |
910 | FW_WM(wm->pipe[PIPE_C].primary >> 8, PLANEC_HI) | | |
911 | FW_WM(wm->pipe[PIPE_B].sprite[1] >> 8, SPRITED_HI) | | |
912 | FW_WM(wm->pipe[PIPE_B].sprite[0] >> 8, SPRITEC_HI) | | |
913 | FW_WM(wm->pipe[PIPE_B].primary >> 8, PLANEB_HI) | | |
914 | FW_WM(wm->pipe[PIPE_A].sprite[1] >> 8, SPRITEB_HI) | | |
915 | FW_WM(wm->pipe[PIPE_A].sprite[0] >> 8, SPRITEA_HI) | | |
916 | FW_WM(wm->pipe[PIPE_A].primary >> 8, PLANEA_HI)); | |
ae80152d VS |
917 | } else { |
918 | I915_WRITE(DSPFW7, | |
15665979 VS |
919 | FW_WM_VLV(wm->pipe[PIPE_B].sprite[1], SPRITED) | |
920 | FW_WM_VLV(wm->pipe[PIPE_B].sprite[0], SPRITEC)); | |
ae80152d | 921 | I915_WRITE(DSPHOWM, |
15665979 VS |
922 | FW_WM(wm->sr.plane >> 9, SR_HI) | |
923 | FW_WM(wm->pipe[PIPE_B].sprite[1] >> 8, SPRITED_HI) | | |
924 | FW_WM(wm->pipe[PIPE_B].sprite[0] >> 8, SPRITEC_HI) | | |
925 | FW_WM(wm->pipe[PIPE_B].primary >> 8, PLANEB_HI) | | |
926 | FW_WM(wm->pipe[PIPE_A].sprite[1] >> 8, SPRITEB_HI) | | |
927 | FW_WM(wm->pipe[PIPE_A].sprite[0] >> 8, SPRITEA_HI) | | |
928 | FW_WM(wm->pipe[PIPE_A].primary >> 8, PLANEA_HI)); | |
ae80152d VS |
929 | } |
930 | ||
931 | POSTING_READ(DSPFW1); | |
932 | ||
0018fda1 VS |
933 | dev_priv->wm.vlv = *wm; |
934 | } | |
935 | ||
15665979 VS |
936 | #undef FW_WM_VLV |
937 | ||
341c526f | 938 | static uint8_t vlv_compute_drain_latency(struct drm_crtc *crtc, |
883a3d2f | 939 | struct drm_plane *plane) |
b445e3b0 | 940 | { |
5e56ba45 | 941 | struct drm_device *dev = crtc->dev; |
883a3d2f VS |
942 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
943 | int entries, prec_mult, drain_latency, pixel_size; | |
944 | int clock = intel_crtc->config->base.adjusted_mode.crtc_clock; | |
341c526f | 945 | const int high_precision = IS_CHERRYVIEW(dev) ? 16 : 64; |
b445e3b0 | 946 | |
883a3d2f VS |
947 | /* |
948 | * FIXME the plane might have an fb | |
949 | * but be invisible (eg. due to clipping) | |
950 | */ | |
951 | if (!intel_crtc->active || !plane->state->fb) | |
952 | return 0; | |
953 | ||
0948c265 | 954 | if (WARN(clock == 0, "Pixel clock is zero!\n")) |
341c526f | 955 | return 0; |
b445e3b0 | 956 | |
883a3d2f VS |
957 | pixel_size = drm_format_plane_cpp(plane->state->fb->pixel_format, 0); |
958 | ||
0948c265 | 959 | if (WARN(pixel_size == 0, "Pixel size is zero!\n")) |
341c526f | 960 | return 0; |
b445e3b0 | 961 | |
a398e9c7 | 962 | entries = DIV_ROUND_UP(clock, 1000) * pixel_size; |
abfc00b5 | 963 | |
341c526f VS |
964 | prec_mult = high_precision; |
965 | drain_latency = 64 * prec_mult * 4 / entries; | |
b445e3b0 | 966 | |
341c526f VS |
967 | if (drain_latency > DRAIN_LATENCY_MASK) { |
968 | prec_mult /= 2; | |
969 | drain_latency = 64 * prec_mult * 4 / entries; | |
abfc00b5 VS |
970 | } |
971 | ||
341c526f VS |
972 | if (drain_latency > DRAIN_LATENCY_MASK) |
973 | drain_latency = DRAIN_LATENCY_MASK; | |
b445e3b0 | 974 | |
341c526f VS |
975 | return drain_latency | (prec_mult == high_precision ? |
976 | DDL_PRECISION_HIGH : DDL_PRECISION_LOW); | |
b445e3b0 ED |
977 | } |
978 | ||
ae80152d VS |
979 | static int vlv_compute_wm(struct intel_crtc *crtc, |
980 | struct intel_plane *plane, | |
981 | int fifo_size) | |
b445e3b0 | 982 | { |
ae80152d | 983 | int clock, entries, pixel_size; |
b445e3b0 | 984 | |
ae80152d VS |
985 | /* |
986 | * FIXME the plane might have an fb | |
987 | * but be invisible (eg. due to clipping) | |
988 | */ | |
989 | if (!crtc->active || !plane->base.state->fb) | |
990 | return 0; | |
0948c265 | 991 | |
ae80152d VS |
992 | pixel_size = drm_format_plane_cpp(plane->base.state->fb->pixel_format, 0); |
993 | clock = crtc->config->base.adjusted_mode.crtc_clock; | |
b445e3b0 | 994 | |
ae80152d | 995 | entries = DIV_ROUND_UP(clock, 1000) * pixel_size; |
b445e3b0 | 996 | |
ae80152d VS |
997 | /* |
998 | * Set up the watermark such that we don't start issuing memory | |
999 | * requests until we are within PND's max deadline value (256us). | |
1000 | * Idea being to be idle as long as possible while still taking | |
1001 | * advatange of PND's deadline scheduling. The limit of 8 | |
1002 | * cachelines (used when the FIFO will anyway drain in less time | |
1003 | * than 256us) should match what we would be done if trickle | |
1004 | * feed were enabled. | |
1005 | */ | |
1006 | return fifo_size - clamp(DIV_ROUND_UP(256 * entries, 64), 0, fifo_size - 8); | |
1007 | } | |
1008 | ||
1009 | static bool vlv_compute_sr_wm(struct drm_device *dev, | |
1010 | struct vlv_wm_values *wm) | |
b445e3b0 | 1011 | { |
ae80152d VS |
1012 | struct drm_i915_private *dev_priv = to_i915(dev); |
1013 | struct drm_crtc *crtc; | |
1014 | enum pipe pipe = INVALID_PIPE; | |
1015 | int num_planes = 0; | |
1016 | int fifo_size = 0; | |
1017 | struct intel_plane *plane; | |
b445e3b0 | 1018 | |
ae80152d | 1019 | wm->sr.cursor = wm->sr.plane = 0; |
b445e3b0 | 1020 | |
ae80152d VS |
1021 | crtc = single_enabled_crtc(dev); |
1022 | /* maxfifo not supported on pipe C */ | |
1023 | if (crtc && to_intel_crtc(crtc)->pipe != PIPE_C) { | |
1024 | pipe = to_intel_crtc(crtc)->pipe; | |
1025 | num_planes = !!wm->pipe[pipe].primary + | |
1026 | !!wm->pipe[pipe].sprite[0] + | |
1027 | !!wm->pipe[pipe].sprite[1]; | |
1028 | fifo_size = INTEL_INFO(dev_priv)->num_pipes * 512 - 1; | |
1029 | } | |
b445e3b0 | 1030 | |
ae80152d VS |
1031 | if (fifo_size == 0 || num_planes > 1) |
1032 | return false; | |
b445e3b0 | 1033 | |
ae80152d VS |
1034 | wm->sr.cursor = vlv_compute_wm(to_intel_crtc(crtc), |
1035 | to_intel_plane(crtc->cursor), 0x3f); | |
b445e3b0 | 1036 | |
ae80152d VS |
1037 | list_for_each_entry(plane, &dev->mode_config.plane_list, base.head) { |
1038 | if (plane->base.type == DRM_PLANE_TYPE_CURSOR) | |
1039 | continue; | |
b445e3b0 | 1040 | |
ae80152d VS |
1041 | if (plane->pipe != pipe) |
1042 | continue; | |
9858425c | 1043 | |
ae80152d VS |
1044 | wm->sr.plane = vlv_compute_wm(to_intel_crtc(crtc), |
1045 | plane, fifo_size); | |
1046 | if (wm->sr.plane != 0) | |
1047 | break; | |
1048 | } | |
1049 | ||
1050 | return true; | |
b445e3b0 ED |
1051 | } |
1052 | ||
ae80152d | 1053 | static void valleyview_update_wm(struct drm_crtc *crtc) |
3c2777fd VS |
1054 | { |
1055 | struct drm_device *dev = crtc->dev; | |
3c2777fd | 1056 | struct drm_i915_private *dev_priv = dev->dev_private; |
ae80152d VS |
1057 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
1058 | enum pipe pipe = intel_crtc->pipe; | |
3c2777fd | 1059 | bool cxsr_enabled; |
ae80152d | 1060 | struct vlv_wm_values wm = dev_priv->wm.vlv; |
3c2777fd | 1061 | |
ae80152d VS |
1062 | wm.ddl[pipe].primary = vlv_compute_drain_latency(crtc, crtc->primary); |
1063 | wm.pipe[pipe].primary = vlv_compute_wm(intel_crtc, | |
1064 | to_intel_plane(crtc->primary), | |
1065 | vlv_get_fifo_size(dev, pipe, 0)); | |
3c2777fd | 1066 | |
ae80152d VS |
1067 | wm.ddl[pipe].cursor = vlv_compute_drain_latency(crtc, crtc->cursor); |
1068 | wm.pipe[pipe].cursor = vlv_compute_wm(intel_crtc, | |
1069 | to_intel_plane(crtc->cursor), | |
1070 | 0x3f); | |
3c2777fd | 1071 | |
ae80152d | 1072 | cxsr_enabled = vlv_compute_sr_wm(dev, &wm); |
3c2777fd | 1073 | |
ae80152d VS |
1074 | if (memcmp(&wm, &dev_priv->wm.vlv, sizeof(wm)) == 0) |
1075 | return; | |
3c2777fd | 1076 | |
ae80152d VS |
1077 | DRM_DEBUG_KMS("Setting FIFO watermarks - %c: plane=%d, cursor=%d, " |
1078 | "SR: plane=%d, cursor=%d\n", pipe_name(pipe), | |
1079 | wm.pipe[pipe].primary, wm.pipe[pipe].cursor, | |
1080 | wm.sr.plane, wm.sr.cursor); | |
3c2777fd | 1081 | |
fc1ac8de VS |
1082 | /* |
1083 | * FIXME DDR DVFS introduces massive memory latencies which | |
1084 | * are not known to system agent so any deadline specified | |
1085 | * by the display may not be respected. To support DDR DVFS | |
1086 | * the watermark code needs to be rewritten to essentially | |
1087 | * bypass deadline mechanism and rely solely on the | |
1088 | * watermarks. For now disable DDR DVFS. | |
1089 | */ | |
1090 | if (IS_CHERRYVIEW(dev_priv)) | |
1091 | chv_set_memory_dvfs(dev_priv, false); | |
1092 | ||
ae80152d VS |
1093 | if (!cxsr_enabled) |
1094 | intel_set_memory_cxsr(dev_priv, false); | |
3c2777fd | 1095 | |
ae80152d | 1096 | vlv_write_wm_values(intel_crtc, &wm); |
3c2777fd VS |
1097 | |
1098 | if (cxsr_enabled) | |
1099 | intel_set_memory_cxsr(dev_priv, true); | |
1100 | } | |
1101 | ||
01e184cc GB |
1102 | static void valleyview_update_sprite_wm(struct drm_plane *plane, |
1103 | struct drm_crtc *crtc, | |
1104 | uint32_t sprite_width, | |
1105 | uint32_t sprite_height, | |
1106 | int pixel_size, | |
1107 | bool enabled, bool scaled) | |
1108 | { | |
1109 | struct drm_device *dev = crtc->dev; | |
1110 | struct drm_i915_private *dev_priv = dev->dev_private; | |
0018fda1 VS |
1111 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
1112 | enum pipe pipe = intel_crtc->pipe; | |
01e184cc | 1113 | int sprite = to_intel_plane(plane)->plane; |
ae80152d | 1114 | bool cxsr_enabled; |
0018fda1 | 1115 | struct vlv_wm_values wm = dev_priv->wm.vlv; |
01e184cc | 1116 | |
ae80152d | 1117 | if (enabled) { |
0018fda1 | 1118 | wm.ddl[pipe].sprite[sprite] = |
883a3d2f | 1119 | vlv_compute_drain_latency(crtc, plane); |
ae80152d VS |
1120 | |
1121 | wm.pipe[pipe].sprite[sprite] = | |
1122 | vlv_compute_wm(intel_crtc, | |
1123 | to_intel_plane(plane), | |
1124 | vlv_get_fifo_size(dev, pipe, sprite+1)); | |
1125 | } else { | |
0018fda1 | 1126 | wm.ddl[pipe].sprite[sprite] = 0; |
ae80152d VS |
1127 | wm.pipe[pipe].sprite[sprite] = 0; |
1128 | } | |
1129 | ||
1130 | cxsr_enabled = vlv_compute_sr_wm(dev, &wm); | |
1131 | ||
1132 | if (memcmp(&wm, &dev_priv->wm.vlv, sizeof(wm)) == 0) | |
1133 | return; | |
1134 | ||
1135 | DRM_DEBUG_KMS("Setting FIFO watermarks - %c: sprite %c=%d, " | |
1136 | "SR: plane=%d, cursor=%d\n", pipe_name(pipe), | |
1137 | sprite_name(pipe, sprite), | |
1138 | wm.pipe[pipe].sprite[sprite], | |
1139 | wm.sr.plane, wm.sr.cursor); | |
1140 | ||
1141 | if (!cxsr_enabled) | |
1142 | intel_set_memory_cxsr(dev_priv, false); | |
01e184cc | 1143 | |
0018fda1 | 1144 | vlv_write_wm_values(intel_crtc, &wm); |
ae80152d VS |
1145 | |
1146 | if (cxsr_enabled) | |
1147 | intel_set_memory_cxsr(dev_priv, true); | |
01e184cc GB |
1148 | } |
1149 | ||
ae80152d VS |
1150 | #define single_plane_enabled(mask) is_power_of_2(mask) |
1151 | ||
46ba614c | 1152 | static void g4x_update_wm(struct drm_crtc *crtc) |
b445e3b0 | 1153 | { |
46ba614c | 1154 | struct drm_device *dev = crtc->dev; |
b445e3b0 ED |
1155 | static const int sr_latency_ns = 12000; |
1156 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1157 | int planea_wm, planeb_wm, cursora_wm, cursorb_wm; | |
1158 | int plane_sr, cursor_sr; | |
1159 | unsigned int enabled = 0; | |
9858425c | 1160 | bool cxsr_enabled; |
b445e3b0 | 1161 | |
51cea1f4 | 1162 | if (g4x_compute_wm0(dev, PIPE_A, |
5aef6003 CW |
1163 | &g4x_wm_info, pessimal_latency_ns, |
1164 | &g4x_cursor_wm_info, pessimal_latency_ns, | |
b445e3b0 | 1165 | &planea_wm, &cursora_wm)) |
51cea1f4 | 1166 | enabled |= 1 << PIPE_A; |
b445e3b0 | 1167 | |
51cea1f4 | 1168 | if (g4x_compute_wm0(dev, PIPE_B, |
5aef6003 CW |
1169 | &g4x_wm_info, pessimal_latency_ns, |
1170 | &g4x_cursor_wm_info, pessimal_latency_ns, | |
b445e3b0 | 1171 | &planeb_wm, &cursorb_wm)) |
51cea1f4 | 1172 | enabled |= 1 << PIPE_B; |
b445e3b0 | 1173 | |
b445e3b0 ED |
1174 | if (single_plane_enabled(enabled) && |
1175 | g4x_compute_srwm(dev, ffs(enabled) - 1, | |
1176 | sr_latency_ns, | |
1177 | &g4x_wm_info, | |
1178 | &g4x_cursor_wm_info, | |
52bd02d8 | 1179 | &plane_sr, &cursor_sr)) { |
9858425c | 1180 | cxsr_enabled = true; |
52bd02d8 | 1181 | } else { |
9858425c | 1182 | cxsr_enabled = false; |
5209b1f4 | 1183 | intel_set_memory_cxsr(dev_priv, false); |
52bd02d8 CW |
1184 | plane_sr = cursor_sr = 0; |
1185 | } | |
b445e3b0 | 1186 | |
a5043453 VS |
1187 | DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, " |
1188 | "B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n", | |
b445e3b0 ED |
1189 | planea_wm, cursora_wm, |
1190 | planeb_wm, cursorb_wm, | |
1191 | plane_sr, cursor_sr); | |
1192 | ||
1193 | I915_WRITE(DSPFW1, | |
f4998963 VS |
1194 | FW_WM(plane_sr, SR) | |
1195 | FW_WM(cursorb_wm, CURSORB) | | |
1196 | FW_WM(planeb_wm, PLANEB) | | |
1197 | FW_WM(planea_wm, PLANEA)); | |
b445e3b0 | 1198 | I915_WRITE(DSPFW2, |
8c919b28 | 1199 | (I915_READ(DSPFW2) & ~DSPFW_CURSORA_MASK) | |
f4998963 | 1200 | FW_WM(cursora_wm, CURSORA)); |
b445e3b0 ED |
1201 | /* HPLL off in SR has some issues on G4x... disable it */ |
1202 | I915_WRITE(DSPFW3, | |
8c919b28 | 1203 | (I915_READ(DSPFW3) & ~(DSPFW_HPLL_SR_EN | DSPFW_CURSOR_SR_MASK)) | |
f4998963 | 1204 | FW_WM(cursor_sr, CURSOR_SR)); |
9858425c ID |
1205 | |
1206 | if (cxsr_enabled) | |
1207 | intel_set_memory_cxsr(dev_priv, true); | |
b445e3b0 ED |
1208 | } |
1209 | ||
46ba614c | 1210 | static void i965_update_wm(struct drm_crtc *unused_crtc) |
b445e3b0 | 1211 | { |
46ba614c | 1212 | struct drm_device *dev = unused_crtc->dev; |
b445e3b0 ED |
1213 | struct drm_i915_private *dev_priv = dev->dev_private; |
1214 | struct drm_crtc *crtc; | |
1215 | int srwm = 1; | |
1216 | int cursor_sr = 16; | |
9858425c | 1217 | bool cxsr_enabled; |
b445e3b0 ED |
1218 | |
1219 | /* Calc sr entries for one plane configs */ | |
1220 | crtc = single_enabled_crtc(dev); | |
1221 | if (crtc) { | |
1222 | /* self-refresh has much higher latency */ | |
1223 | static const int sr_latency_ns = 12000; | |
4fe8590a | 1224 | const struct drm_display_mode *adjusted_mode = |
6e3c9717 | 1225 | &to_intel_crtc(crtc)->config->base.adjusted_mode; |
241bfc38 | 1226 | int clock = adjusted_mode->crtc_clock; |
fec8cba3 | 1227 | int htotal = adjusted_mode->crtc_htotal; |
6e3c9717 | 1228 | int hdisplay = to_intel_crtc(crtc)->config->pipe_src_w; |
59bea882 | 1229 | int pixel_size = crtc->primary->state->fb->bits_per_pixel / 8; |
b445e3b0 ED |
1230 | unsigned long line_time_us; |
1231 | int entries; | |
1232 | ||
922044c9 | 1233 | line_time_us = max(htotal * 1000 / clock, 1); |
b445e3b0 ED |
1234 | |
1235 | /* Use ns/us then divide to preserve precision */ | |
1236 | entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) * | |
1237 | pixel_size * hdisplay; | |
1238 | entries = DIV_ROUND_UP(entries, I915_FIFO_LINE_SIZE); | |
1239 | srwm = I965_FIFO_SIZE - entries; | |
1240 | if (srwm < 0) | |
1241 | srwm = 1; | |
1242 | srwm &= 0x1ff; | |
1243 | DRM_DEBUG_KMS("self-refresh entries: %d, wm: %d\n", | |
1244 | entries, srwm); | |
1245 | ||
1246 | entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) * | |
3dd512fb | 1247 | pixel_size * crtc->cursor->state->crtc_w; |
b445e3b0 ED |
1248 | entries = DIV_ROUND_UP(entries, |
1249 | i965_cursor_wm_info.cacheline_size); | |
1250 | cursor_sr = i965_cursor_wm_info.fifo_size - | |
1251 | (entries + i965_cursor_wm_info.guard_size); | |
1252 | ||
1253 | if (cursor_sr > i965_cursor_wm_info.max_wm) | |
1254 | cursor_sr = i965_cursor_wm_info.max_wm; | |
1255 | ||
1256 | DRM_DEBUG_KMS("self-refresh watermark: display plane %d " | |
1257 | "cursor %d\n", srwm, cursor_sr); | |
1258 | ||
9858425c | 1259 | cxsr_enabled = true; |
b445e3b0 | 1260 | } else { |
9858425c | 1261 | cxsr_enabled = false; |
b445e3b0 | 1262 | /* Turn off self refresh if both pipes are enabled */ |
5209b1f4 | 1263 | intel_set_memory_cxsr(dev_priv, false); |
b445e3b0 ED |
1264 | } |
1265 | ||
1266 | DRM_DEBUG_KMS("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR %d\n", | |
1267 | srwm); | |
1268 | ||
1269 | /* 965 has limitations... */ | |
f4998963 VS |
1270 | I915_WRITE(DSPFW1, FW_WM(srwm, SR) | |
1271 | FW_WM(8, CURSORB) | | |
1272 | FW_WM(8, PLANEB) | | |
1273 | FW_WM(8, PLANEA)); | |
1274 | I915_WRITE(DSPFW2, FW_WM(8, CURSORA) | | |
1275 | FW_WM(8, PLANEC_OLD)); | |
b445e3b0 | 1276 | /* update cursor SR watermark */ |
f4998963 | 1277 | I915_WRITE(DSPFW3, FW_WM(cursor_sr, CURSOR_SR)); |
9858425c ID |
1278 | |
1279 | if (cxsr_enabled) | |
1280 | intel_set_memory_cxsr(dev_priv, true); | |
b445e3b0 ED |
1281 | } |
1282 | ||
f4998963 VS |
1283 | #undef FW_WM |
1284 | ||
46ba614c | 1285 | static void i9xx_update_wm(struct drm_crtc *unused_crtc) |
b445e3b0 | 1286 | { |
46ba614c | 1287 | struct drm_device *dev = unused_crtc->dev; |
b445e3b0 ED |
1288 | struct drm_i915_private *dev_priv = dev->dev_private; |
1289 | const struct intel_watermark_params *wm_info; | |
1290 | uint32_t fwater_lo; | |
1291 | uint32_t fwater_hi; | |
1292 | int cwm, srwm = 1; | |
1293 | int fifo_size; | |
1294 | int planea_wm, planeb_wm; | |
1295 | struct drm_crtc *crtc, *enabled = NULL; | |
1296 | ||
1297 | if (IS_I945GM(dev)) | |
1298 | wm_info = &i945_wm_info; | |
1299 | else if (!IS_GEN2(dev)) | |
1300 | wm_info = &i915_wm_info; | |
1301 | else | |
9d539105 | 1302 | wm_info = &i830_a_wm_info; |
b445e3b0 ED |
1303 | |
1304 | fifo_size = dev_priv->display.get_fifo_size(dev, 0); | |
1305 | crtc = intel_get_crtc_for_plane(dev, 0); | |
3490ea5d | 1306 | if (intel_crtc_active(crtc)) { |
241bfc38 | 1307 | const struct drm_display_mode *adjusted_mode; |
59bea882 | 1308 | int cpp = crtc->primary->state->fb->bits_per_pixel / 8; |
b9e0bda3 CW |
1309 | if (IS_GEN2(dev)) |
1310 | cpp = 4; | |
1311 | ||
6e3c9717 | 1312 | adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode; |
241bfc38 | 1313 | planea_wm = intel_calculate_wm(adjusted_mode->crtc_clock, |
b9e0bda3 | 1314 | wm_info, fifo_size, cpp, |
5aef6003 | 1315 | pessimal_latency_ns); |
b445e3b0 | 1316 | enabled = crtc; |
9d539105 | 1317 | } else { |
b445e3b0 | 1318 | planea_wm = fifo_size - wm_info->guard_size; |
9d539105 VS |
1319 | if (planea_wm > (long)wm_info->max_wm) |
1320 | planea_wm = wm_info->max_wm; | |
1321 | } | |
1322 | ||
1323 | if (IS_GEN2(dev)) | |
1324 | wm_info = &i830_bc_wm_info; | |
b445e3b0 ED |
1325 | |
1326 | fifo_size = dev_priv->display.get_fifo_size(dev, 1); | |
1327 | crtc = intel_get_crtc_for_plane(dev, 1); | |
3490ea5d | 1328 | if (intel_crtc_active(crtc)) { |
241bfc38 | 1329 | const struct drm_display_mode *adjusted_mode; |
59bea882 | 1330 | int cpp = crtc->primary->state->fb->bits_per_pixel / 8; |
b9e0bda3 CW |
1331 | if (IS_GEN2(dev)) |
1332 | cpp = 4; | |
1333 | ||
6e3c9717 | 1334 | adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode; |
241bfc38 | 1335 | planeb_wm = intel_calculate_wm(adjusted_mode->crtc_clock, |
b9e0bda3 | 1336 | wm_info, fifo_size, cpp, |
5aef6003 | 1337 | pessimal_latency_ns); |
b445e3b0 ED |
1338 | if (enabled == NULL) |
1339 | enabled = crtc; | |
1340 | else | |
1341 | enabled = NULL; | |
9d539105 | 1342 | } else { |
b445e3b0 | 1343 | planeb_wm = fifo_size - wm_info->guard_size; |
9d539105 VS |
1344 | if (planeb_wm > (long)wm_info->max_wm) |
1345 | planeb_wm = wm_info->max_wm; | |
1346 | } | |
b445e3b0 ED |
1347 | |
1348 | DRM_DEBUG_KMS("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm); | |
1349 | ||
2ab1bc9d | 1350 | if (IS_I915GM(dev) && enabled) { |
2ff8fde1 | 1351 | struct drm_i915_gem_object *obj; |
2ab1bc9d | 1352 | |
59bea882 | 1353 | obj = intel_fb_obj(enabled->primary->state->fb); |
2ab1bc9d DV |
1354 | |
1355 | /* self-refresh seems busted with untiled */ | |
2ff8fde1 | 1356 | if (obj->tiling_mode == I915_TILING_NONE) |
2ab1bc9d DV |
1357 | enabled = NULL; |
1358 | } | |
1359 | ||
b445e3b0 ED |
1360 | /* |
1361 | * Overlay gets an aggressive default since video jitter is bad. | |
1362 | */ | |
1363 | cwm = 2; | |
1364 | ||
1365 | /* Play safe and disable self-refresh before adjusting watermarks. */ | |
5209b1f4 | 1366 | intel_set_memory_cxsr(dev_priv, false); |
b445e3b0 ED |
1367 | |
1368 | /* Calc sr entries for one plane configs */ | |
1369 | if (HAS_FW_BLC(dev) && enabled) { | |
1370 | /* self-refresh has much higher latency */ | |
1371 | static const int sr_latency_ns = 6000; | |
4fe8590a | 1372 | const struct drm_display_mode *adjusted_mode = |
6e3c9717 | 1373 | &to_intel_crtc(enabled)->config->base.adjusted_mode; |
241bfc38 | 1374 | int clock = adjusted_mode->crtc_clock; |
fec8cba3 | 1375 | int htotal = adjusted_mode->crtc_htotal; |
6e3c9717 | 1376 | int hdisplay = to_intel_crtc(enabled)->config->pipe_src_w; |
59bea882 | 1377 | int pixel_size = enabled->primary->state->fb->bits_per_pixel / 8; |
b445e3b0 ED |
1378 | unsigned long line_time_us; |
1379 | int entries; | |
1380 | ||
922044c9 | 1381 | line_time_us = max(htotal * 1000 / clock, 1); |
b445e3b0 ED |
1382 | |
1383 | /* Use ns/us then divide to preserve precision */ | |
1384 | entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) * | |
1385 | pixel_size * hdisplay; | |
1386 | entries = DIV_ROUND_UP(entries, wm_info->cacheline_size); | |
1387 | DRM_DEBUG_KMS("self-refresh entries: %d\n", entries); | |
1388 | srwm = wm_info->fifo_size - entries; | |
1389 | if (srwm < 0) | |
1390 | srwm = 1; | |
1391 | ||
1392 | if (IS_I945G(dev) || IS_I945GM(dev)) | |
1393 | I915_WRITE(FW_BLC_SELF, | |
1394 | FW_BLC_SELF_FIFO_MASK | (srwm & 0xff)); | |
1395 | else if (IS_I915GM(dev)) | |
1396 | I915_WRITE(FW_BLC_SELF, srwm & 0x3f); | |
1397 | } | |
1398 | ||
1399 | DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n", | |
1400 | planea_wm, planeb_wm, cwm, srwm); | |
1401 | ||
1402 | fwater_lo = ((planeb_wm & 0x3f) << 16) | (planea_wm & 0x3f); | |
1403 | fwater_hi = (cwm & 0x1f); | |
1404 | ||
1405 | /* Set request length to 8 cachelines per fetch */ | |
1406 | fwater_lo = fwater_lo | (1 << 24) | (1 << 8); | |
1407 | fwater_hi = fwater_hi | (1 << 8); | |
1408 | ||
1409 | I915_WRITE(FW_BLC, fwater_lo); | |
1410 | I915_WRITE(FW_BLC2, fwater_hi); | |
1411 | ||
5209b1f4 ID |
1412 | if (enabled) |
1413 | intel_set_memory_cxsr(dev_priv, true); | |
b445e3b0 ED |
1414 | } |
1415 | ||
feb56b93 | 1416 | static void i845_update_wm(struct drm_crtc *unused_crtc) |
b445e3b0 | 1417 | { |
46ba614c | 1418 | struct drm_device *dev = unused_crtc->dev; |
b445e3b0 ED |
1419 | struct drm_i915_private *dev_priv = dev->dev_private; |
1420 | struct drm_crtc *crtc; | |
241bfc38 | 1421 | const struct drm_display_mode *adjusted_mode; |
b445e3b0 ED |
1422 | uint32_t fwater_lo; |
1423 | int planea_wm; | |
1424 | ||
1425 | crtc = single_enabled_crtc(dev); | |
1426 | if (crtc == NULL) | |
1427 | return; | |
1428 | ||
6e3c9717 | 1429 | adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode; |
241bfc38 | 1430 | planea_wm = intel_calculate_wm(adjusted_mode->crtc_clock, |
feb56b93 | 1431 | &i845_wm_info, |
b445e3b0 | 1432 | dev_priv->display.get_fifo_size(dev, 0), |
5aef6003 | 1433 | 4, pessimal_latency_ns); |
b445e3b0 ED |
1434 | fwater_lo = I915_READ(FW_BLC) & ~0xfff; |
1435 | fwater_lo |= (3<<8) | planea_wm; | |
1436 | ||
1437 | DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d\n", planea_wm); | |
1438 | ||
1439 | I915_WRITE(FW_BLC, fwater_lo); | |
1440 | } | |
1441 | ||
8cfb3407 | 1442 | uint32_t ilk_pipe_pixel_rate(const struct intel_crtc_state *pipe_config) |
801bcfff | 1443 | { |
fd4daa9c | 1444 | uint32_t pixel_rate; |
801bcfff | 1445 | |
8cfb3407 | 1446 | pixel_rate = pipe_config->base.adjusted_mode.crtc_clock; |
801bcfff PZ |
1447 | |
1448 | /* We only use IF-ID interlacing. If we ever use PF-ID we'll need to | |
1449 | * adjust the pixel_rate here. */ | |
1450 | ||
8cfb3407 | 1451 | if (pipe_config->pch_pfit.enabled) { |
801bcfff | 1452 | uint64_t pipe_w, pipe_h, pfit_w, pfit_h; |
8cfb3407 VS |
1453 | uint32_t pfit_size = pipe_config->pch_pfit.size; |
1454 | ||
1455 | pipe_w = pipe_config->pipe_src_w; | |
1456 | pipe_h = pipe_config->pipe_src_h; | |
801bcfff | 1457 | |
801bcfff PZ |
1458 | pfit_w = (pfit_size >> 16) & 0xFFFF; |
1459 | pfit_h = pfit_size & 0xFFFF; | |
1460 | if (pipe_w < pfit_w) | |
1461 | pipe_w = pfit_w; | |
1462 | if (pipe_h < pfit_h) | |
1463 | pipe_h = pfit_h; | |
1464 | ||
1465 | pixel_rate = div_u64((uint64_t) pixel_rate * pipe_w * pipe_h, | |
1466 | pfit_w * pfit_h); | |
1467 | } | |
1468 | ||
1469 | return pixel_rate; | |
1470 | } | |
1471 | ||
37126462 | 1472 | /* latency must be in 0.1us units. */ |
23297044 | 1473 | static uint32_t ilk_wm_method1(uint32_t pixel_rate, uint8_t bytes_per_pixel, |
801bcfff PZ |
1474 | uint32_t latency) |
1475 | { | |
1476 | uint64_t ret; | |
1477 | ||
3312ba65 VS |
1478 | if (WARN(latency == 0, "Latency value missing\n")) |
1479 | return UINT_MAX; | |
1480 | ||
801bcfff PZ |
1481 | ret = (uint64_t) pixel_rate * bytes_per_pixel * latency; |
1482 | ret = DIV_ROUND_UP_ULL(ret, 64 * 10000) + 2; | |
1483 | ||
1484 | return ret; | |
1485 | } | |
1486 | ||
37126462 | 1487 | /* latency must be in 0.1us units. */ |
23297044 | 1488 | static uint32_t ilk_wm_method2(uint32_t pixel_rate, uint32_t pipe_htotal, |
801bcfff PZ |
1489 | uint32_t horiz_pixels, uint8_t bytes_per_pixel, |
1490 | uint32_t latency) | |
1491 | { | |
1492 | uint32_t ret; | |
1493 | ||
3312ba65 VS |
1494 | if (WARN(latency == 0, "Latency value missing\n")) |
1495 | return UINT_MAX; | |
1496 | ||
801bcfff PZ |
1497 | ret = (latency * pixel_rate) / (pipe_htotal * 10000); |
1498 | ret = (ret + 1) * horiz_pixels * bytes_per_pixel; | |
1499 | ret = DIV_ROUND_UP(ret, 64) + 2; | |
1500 | return ret; | |
1501 | } | |
1502 | ||
23297044 | 1503 | static uint32_t ilk_wm_fbc(uint32_t pri_val, uint32_t horiz_pixels, |
cca32e9a PZ |
1504 | uint8_t bytes_per_pixel) |
1505 | { | |
1506 | return DIV_ROUND_UP(pri_val * 64, horiz_pixels * bytes_per_pixel) + 2; | |
1507 | } | |
1508 | ||
2ac96d2a PB |
1509 | struct skl_pipe_wm_parameters { |
1510 | bool active; | |
1511 | uint32_t pipe_htotal; | |
1512 | uint32_t pixel_rate; /* in KHz */ | |
1513 | struct intel_plane_wm_parameters plane[I915_MAX_PLANES]; | |
1514 | struct intel_plane_wm_parameters cursor; | |
1515 | }; | |
1516 | ||
820c1980 | 1517 | struct ilk_pipe_wm_parameters { |
801bcfff | 1518 | bool active; |
801bcfff PZ |
1519 | uint32_t pipe_htotal; |
1520 | uint32_t pixel_rate; | |
c35426d2 VS |
1521 | struct intel_plane_wm_parameters pri; |
1522 | struct intel_plane_wm_parameters spr; | |
1523 | struct intel_plane_wm_parameters cur; | |
801bcfff PZ |
1524 | }; |
1525 | ||
820c1980 | 1526 | struct ilk_wm_maximums { |
cca32e9a PZ |
1527 | uint16_t pri; |
1528 | uint16_t spr; | |
1529 | uint16_t cur; | |
1530 | uint16_t fbc; | |
1531 | }; | |
1532 | ||
240264f4 VS |
1533 | /* used in computing the new watermarks state */ |
1534 | struct intel_wm_config { | |
1535 | unsigned int num_pipes_active; | |
1536 | bool sprites_enabled; | |
1537 | bool sprites_scaled; | |
240264f4 VS |
1538 | }; |
1539 | ||
37126462 VS |
1540 | /* |
1541 | * For both WM_PIPE and WM_LP. | |
1542 | * mem_value must be in 0.1us units. | |
1543 | */ | |
820c1980 | 1544 | static uint32_t ilk_compute_pri_wm(const struct ilk_pipe_wm_parameters *params, |
cca32e9a PZ |
1545 | uint32_t mem_value, |
1546 | bool is_lp) | |
801bcfff | 1547 | { |
cca32e9a PZ |
1548 | uint32_t method1, method2; |
1549 | ||
c35426d2 | 1550 | if (!params->active || !params->pri.enabled) |
801bcfff PZ |
1551 | return 0; |
1552 | ||
23297044 | 1553 | method1 = ilk_wm_method1(params->pixel_rate, |
c35426d2 | 1554 | params->pri.bytes_per_pixel, |
cca32e9a PZ |
1555 | mem_value); |
1556 | ||
1557 | if (!is_lp) | |
1558 | return method1; | |
1559 | ||
23297044 | 1560 | method2 = ilk_wm_method2(params->pixel_rate, |
cca32e9a | 1561 | params->pipe_htotal, |
c35426d2 VS |
1562 | params->pri.horiz_pixels, |
1563 | params->pri.bytes_per_pixel, | |
cca32e9a PZ |
1564 | mem_value); |
1565 | ||
1566 | return min(method1, method2); | |
801bcfff PZ |
1567 | } |
1568 | ||
37126462 VS |
1569 | /* |
1570 | * For both WM_PIPE and WM_LP. | |
1571 | * mem_value must be in 0.1us units. | |
1572 | */ | |
820c1980 | 1573 | static uint32_t ilk_compute_spr_wm(const struct ilk_pipe_wm_parameters *params, |
801bcfff PZ |
1574 | uint32_t mem_value) |
1575 | { | |
1576 | uint32_t method1, method2; | |
1577 | ||
c35426d2 | 1578 | if (!params->active || !params->spr.enabled) |
801bcfff PZ |
1579 | return 0; |
1580 | ||
23297044 | 1581 | method1 = ilk_wm_method1(params->pixel_rate, |
c35426d2 | 1582 | params->spr.bytes_per_pixel, |
801bcfff | 1583 | mem_value); |
23297044 | 1584 | method2 = ilk_wm_method2(params->pixel_rate, |
801bcfff | 1585 | params->pipe_htotal, |
c35426d2 VS |
1586 | params->spr.horiz_pixels, |
1587 | params->spr.bytes_per_pixel, | |
801bcfff PZ |
1588 | mem_value); |
1589 | return min(method1, method2); | |
1590 | } | |
1591 | ||
37126462 VS |
1592 | /* |
1593 | * For both WM_PIPE and WM_LP. | |
1594 | * mem_value must be in 0.1us units. | |
1595 | */ | |
820c1980 | 1596 | static uint32_t ilk_compute_cur_wm(const struct ilk_pipe_wm_parameters *params, |
801bcfff PZ |
1597 | uint32_t mem_value) |
1598 | { | |
c35426d2 | 1599 | if (!params->active || !params->cur.enabled) |
801bcfff PZ |
1600 | return 0; |
1601 | ||
23297044 | 1602 | return ilk_wm_method2(params->pixel_rate, |
801bcfff | 1603 | params->pipe_htotal, |
c35426d2 VS |
1604 | params->cur.horiz_pixels, |
1605 | params->cur.bytes_per_pixel, | |
801bcfff PZ |
1606 | mem_value); |
1607 | } | |
1608 | ||
cca32e9a | 1609 | /* Only for WM_LP. */ |
820c1980 | 1610 | static uint32_t ilk_compute_fbc_wm(const struct ilk_pipe_wm_parameters *params, |
1fda9882 | 1611 | uint32_t pri_val) |
cca32e9a | 1612 | { |
c35426d2 | 1613 | if (!params->active || !params->pri.enabled) |
cca32e9a PZ |
1614 | return 0; |
1615 | ||
23297044 | 1616 | return ilk_wm_fbc(pri_val, |
c35426d2 VS |
1617 | params->pri.horiz_pixels, |
1618 | params->pri.bytes_per_pixel); | |
cca32e9a PZ |
1619 | } |
1620 | ||
158ae64f VS |
1621 | static unsigned int ilk_display_fifo_size(const struct drm_device *dev) |
1622 | { | |
416f4727 VS |
1623 | if (INTEL_INFO(dev)->gen >= 8) |
1624 | return 3072; | |
1625 | else if (INTEL_INFO(dev)->gen >= 7) | |
158ae64f VS |
1626 | return 768; |
1627 | else | |
1628 | return 512; | |
1629 | } | |
1630 | ||
4e975081 VS |
1631 | static unsigned int ilk_plane_wm_reg_max(const struct drm_device *dev, |
1632 | int level, bool is_sprite) | |
1633 | { | |
1634 | if (INTEL_INFO(dev)->gen >= 8) | |
1635 | /* BDW primary/sprite plane watermarks */ | |
1636 | return level == 0 ? 255 : 2047; | |
1637 | else if (INTEL_INFO(dev)->gen >= 7) | |
1638 | /* IVB/HSW primary/sprite plane watermarks */ | |
1639 | return level == 0 ? 127 : 1023; | |
1640 | else if (!is_sprite) | |
1641 | /* ILK/SNB primary plane watermarks */ | |
1642 | return level == 0 ? 127 : 511; | |
1643 | else | |
1644 | /* ILK/SNB sprite plane watermarks */ | |
1645 | return level == 0 ? 63 : 255; | |
1646 | } | |
1647 | ||
1648 | static unsigned int ilk_cursor_wm_reg_max(const struct drm_device *dev, | |
1649 | int level) | |
1650 | { | |
1651 | if (INTEL_INFO(dev)->gen >= 7) | |
1652 | return level == 0 ? 63 : 255; | |
1653 | else | |
1654 | return level == 0 ? 31 : 63; | |
1655 | } | |
1656 | ||
1657 | static unsigned int ilk_fbc_wm_reg_max(const struct drm_device *dev) | |
1658 | { | |
1659 | if (INTEL_INFO(dev)->gen >= 8) | |
1660 | return 31; | |
1661 | else | |
1662 | return 15; | |
1663 | } | |
1664 | ||
158ae64f VS |
1665 | /* Calculate the maximum primary/sprite plane watermark */ |
1666 | static unsigned int ilk_plane_wm_max(const struct drm_device *dev, | |
1667 | int level, | |
240264f4 | 1668 | const struct intel_wm_config *config, |
158ae64f VS |
1669 | enum intel_ddb_partitioning ddb_partitioning, |
1670 | bool is_sprite) | |
1671 | { | |
1672 | unsigned int fifo_size = ilk_display_fifo_size(dev); | |
158ae64f VS |
1673 | |
1674 | /* if sprites aren't enabled, sprites get nothing */ | |
240264f4 | 1675 | if (is_sprite && !config->sprites_enabled) |
158ae64f VS |
1676 | return 0; |
1677 | ||
1678 | /* HSW allows LP1+ watermarks even with multiple pipes */ | |
240264f4 | 1679 | if (level == 0 || config->num_pipes_active > 1) { |
158ae64f VS |
1680 | fifo_size /= INTEL_INFO(dev)->num_pipes; |
1681 | ||
1682 | /* | |
1683 | * For some reason the non self refresh | |
1684 | * FIFO size is only half of the self | |
1685 | * refresh FIFO size on ILK/SNB. | |
1686 | */ | |
1687 | if (INTEL_INFO(dev)->gen <= 6) | |
1688 | fifo_size /= 2; | |
1689 | } | |
1690 | ||
240264f4 | 1691 | if (config->sprites_enabled) { |
158ae64f VS |
1692 | /* level 0 is always calculated with 1:1 split */ |
1693 | if (level > 0 && ddb_partitioning == INTEL_DDB_PART_5_6) { | |
1694 | if (is_sprite) | |
1695 | fifo_size *= 5; | |
1696 | fifo_size /= 6; | |
1697 | } else { | |
1698 | fifo_size /= 2; | |
1699 | } | |
1700 | } | |
1701 | ||
1702 | /* clamp to max that the registers can hold */ | |
4e975081 | 1703 | return min(fifo_size, ilk_plane_wm_reg_max(dev, level, is_sprite)); |
158ae64f VS |
1704 | } |
1705 | ||
1706 | /* Calculate the maximum cursor plane watermark */ | |
1707 | static unsigned int ilk_cursor_wm_max(const struct drm_device *dev, | |
240264f4 VS |
1708 | int level, |
1709 | const struct intel_wm_config *config) | |
158ae64f VS |
1710 | { |
1711 | /* HSW LP1+ watermarks w/ multiple pipes */ | |
240264f4 | 1712 | if (level > 0 && config->num_pipes_active > 1) |
158ae64f VS |
1713 | return 64; |
1714 | ||
1715 | /* otherwise just report max that registers can hold */ | |
4e975081 | 1716 | return ilk_cursor_wm_reg_max(dev, level); |
158ae64f VS |
1717 | } |
1718 | ||
d34ff9c6 | 1719 | static void ilk_compute_wm_maximums(const struct drm_device *dev, |
34982fe1 VS |
1720 | int level, |
1721 | const struct intel_wm_config *config, | |
1722 | enum intel_ddb_partitioning ddb_partitioning, | |
820c1980 | 1723 | struct ilk_wm_maximums *max) |
158ae64f | 1724 | { |
240264f4 VS |
1725 | max->pri = ilk_plane_wm_max(dev, level, config, ddb_partitioning, false); |
1726 | max->spr = ilk_plane_wm_max(dev, level, config, ddb_partitioning, true); | |
1727 | max->cur = ilk_cursor_wm_max(dev, level, config); | |
4e975081 | 1728 | max->fbc = ilk_fbc_wm_reg_max(dev); |
158ae64f VS |
1729 | } |
1730 | ||
a3cb4048 VS |
1731 | static void ilk_compute_wm_reg_maximums(struct drm_device *dev, |
1732 | int level, | |
1733 | struct ilk_wm_maximums *max) | |
1734 | { | |
1735 | max->pri = ilk_plane_wm_reg_max(dev, level, false); | |
1736 | max->spr = ilk_plane_wm_reg_max(dev, level, true); | |
1737 | max->cur = ilk_cursor_wm_reg_max(dev, level); | |
1738 | max->fbc = ilk_fbc_wm_reg_max(dev); | |
1739 | } | |
1740 | ||
d9395655 | 1741 | static bool ilk_validate_wm_level(int level, |
820c1980 | 1742 | const struct ilk_wm_maximums *max, |
d9395655 | 1743 | struct intel_wm_level *result) |
a9786a11 VS |
1744 | { |
1745 | bool ret; | |
1746 | ||
1747 | /* already determined to be invalid? */ | |
1748 | if (!result->enable) | |
1749 | return false; | |
1750 | ||
1751 | result->enable = result->pri_val <= max->pri && | |
1752 | result->spr_val <= max->spr && | |
1753 | result->cur_val <= max->cur; | |
1754 | ||
1755 | ret = result->enable; | |
1756 | ||
1757 | /* | |
1758 | * HACK until we can pre-compute everything, | |
1759 | * and thus fail gracefully if LP0 watermarks | |
1760 | * are exceeded... | |
1761 | */ | |
1762 | if (level == 0 && !result->enable) { | |
1763 | if (result->pri_val > max->pri) | |
1764 | DRM_DEBUG_KMS("Primary WM%d too large %u (max %u)\n", | |
1765 | level, result->pri_val, max->pri); | |
1766 | if (result->spr_val > max->spr) | |
1767 | DRM_DEBUG_KMS("Sprite WM%d too large %u (max %u)\n", | |
1768 | level, result->spr_val, max->spr); | |
1769 | if (result->cur_val > max->cur) | |
1770 | DRM_DEBUG_KMS("Cursor WM%d too large %u (max %u)\n", | |
1771 | level, result->cur_val, max->cur); | |
1772 | ||
1773 | result->pri_val = min_t(uint32_t, result->pri_val, max->pri); | |
1774 | result->spr_val = min_t(uint32_t, result->spr_val, max->spr); | |
1775 | result->cur_val = min_t(uint32_t, result->cur_val, max->cur); | |
1776 | result->enable = true; | |
1777 | } | |
1778 | ||
a9786a11 VS |
1779 | return ret; |
1780 | } | |
1781 | ||
d34ff9c6 | 1782 | static void ilk_compute_wm_level(const struct drm_i915_private *dev_priv, |
6f5ddd17 | 1783 | int level, |
820c1980 | 1784 | const struct ilk_pipe_wm_parameters *p, |
1fd527cc | 1785 | struct intel_wm_level *result) |
6f5ddd17 VS |
1786 | { |
1787 | uint16_t pri_latency = dev_priv->wm.pri_latency[level]; | |
1788 | uint16_t spr_latency = dev_priv->wm.spr_latency[level]; | |
1789 | uint16_t cur_latency = dev_priv->wm.cur_latency[level]; | |
1790 | ||
1791 | /* WM1+ latency values stored in 0.5us units */ | |
1792 | if (level > 0) { | |
1793 | pri_latency *= 5; | |
1794 | spr_latency *= 5; | |
1795 | cur_latency *= 5; | |
1796 | } | |
1797 | ||
1798 | result->pri_val = ilk_compute_pri_wm(p, pri_latency, level); | |
1799 | result->spr_val = ilk_compute_spr_wm(p, spr_latency); | |
1800 | result->cur_val = ilk_compute_cur_wm(p, cur_latency); | |
1801 | result->fbc_val = ilk_compute_fbc_wm(p, result->pri_val); | |
1802 | result->enable = true; | |
1803 | } | |
1804 | ||
801bcfff PZ |
1805 | static uint32_t |
1806 | hsw_compute_linetime_wm(struct drm_device *dev, struct drm_crtc *crtc) | |
1f8eeabf ED |
1807 | { |
1808 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1011d8c4 | 1809 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
6e3c9717 | 1810 | struct drm_display_mode *mode = &intel_crtc->config->base.adjusted_mode; |
85a02deb | 1811 | u32 linetime, ips_linetime; |
1f8eeabf | 1812 | |
3ef00284 | 1813 | if (!intel_crtc->active) |
801bcfff | 1814 | return 0; |
1011d8c4 | 1815 | |
1f8eeabf ED |
1816 | /* The WM are computed with base on how long it takes to fill a single |
1817 | * row at the given clock rate, multiplied by 8. | |
1818 | * */ | |
fec8cba3 JB |
1819 | linetime = DIV_ROUND_CLOSEST(mode->crtc_htotal * 1000 * 8, |
1820 | mode->crtc_clock); | |
1821 | ips_linetime = DIV_ROUND_CLOSEST(mode->crtc_htotal * 1000 * 8, | |
05024da3 | 1822 | dev_priv->cdclk_freq); |
1f8eeabf | 1823 | |
801bcfff PZ |
1824 | return PIPE_WM_LINETIME_IPS_LINETIME(ips_linetime) | |
1825 | PIPE_WM_LINETIME_TIME(linetime); | |
1f8eeabf ED |
1826 | } |
1827 | ||
2af30a5c | 1828 | static void intel_read_wm_latency(struct drm_device *dev, uint16_t wm[8]) |
12b134df VS |
1829 | { |
1830 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1831 | ||
2af30a5c PB |
1832 | if (IS_GEN9(dev)) { |
1833 | uint32_t val; | |
4f947386 | 1834 | int ret, i; |
367294be | 1835 | int level, max_level = ilk_wm_max_level(dev); |
2af30a5c PB |
1836 | |
1837 | /* read the first set of memory latencies[0:3] */ | |
1838 | val = 0; /* data0 to be programmed to 0 for first set */ | |
1839 | mutex_lock(&dev_priv->rps.hw_lock); | |
1840 | ret = sandybridge_pcode_read(dev_priv, | |
1841 | GEN9_PCODE_READ_MEM_LATENCY, | |
1842 | &val); | |
1843 | mutex_unlock(&dev_priv->rps.hw_lock); | |
1844 | ||
1845 | if (ret) { | |
1846 | DRM_ERROR("SKL Mailbox read error = %d\n", ret); | |
1847 | return; | |
1848 | } | |
1849 | ||
1850 | wm[0] = val & GEN9_MEM_LATENCY_LEVEL_MASK; | |
1851 | wm[1] = (val >> GEN9_MEM_LATENCY_LEVEL_1_5_SHIFT) & | |
1852 | GEN9_MEM_LATENCY_LEVEL_MASK; | |
1853 | wm[2] = (val >> GEN9_MEM_LATENCY_LEVEL_2_6_SHIFT) & | |
1854 | GEN9_MEM_LATENCY_LEVEL_MASK; | |
1855 | wm[3] = (val >> GEN9_MEM_LATENCY_LEVEL_3_7_SHIFT) & | |
1856 | GEN9_MEM_LATENCY_LEVEL_MASK; | |
1857 | ||
1858 | /* read the second set of memory latencies[4:7] */ | |
1859 | val = 1; /* data0 to be programmed to 1 for second set */ | |
1860 | mutex_lock(&dev_priv->rps.hw_lock); | |
1861 | ret = sandybridge_pcode_read(dev_priv, | |
1862 | GEN9_PCODE_READ_MEM_LATENCY, | |
1863 | &val); | |
1864 | mutex_unlock(&dev_priv->rps.hw_lock); | |
1865 | if (ret) { | |
1866 | DRM_ERROR("SKL Mailbox read error = %d\n", ret); | |
1867 | return; | |
1868 | } | |
1869 | ||
1870 | wm[4] = val & GEN9_MEM_LATENCY_LEVEL_MASK; | |
1871 | wm[5] = (val >> GEN9_MEM_LATENCY_LEVEL_1_5_SHIFT) & | |
1872 | GEN9_MEM_LATENCY_LEVEL_MASK; | |
1873 | wm[6] = (val >> GEN9_MEM_LATENCY_LEVEL_2_6_SHIFT) & | |
1874 | GEN9_MEM_LATENCY_LEVEL_MASK; | |
1875 | wm[7] = (val >> GEN9_MEM_LATENCY_LEVEL_3_7_SHIFT) & | |
1876 | GEN9_MEM_LATENCY_LEVEL_MASK; | |
1877 | ||
367294be | 1878 | /* |
6f97235b DL |
1879 | * WaWmMemoryReadLatency:skl |
1880 | * | |
367294be VK |
1881 | * punit doesn't take into account the read latency so we need |
1882 | * to add 2us to the various latency levels we retrieve from | |
1883 | * the punit. | |
1884 | * - W0 is a bit special in that it's the only level that | |
1885 | * can't be disabled if we want to have display working, so | |
1886 | * we always add 2us there. | |
1887 | * - For levels >=1, punit returns 0us latency when they are | |
1888 | * disabled, so we respect that and don't add 2us then | |
4f947386 VK |
1889 | * |
1890 | * Additionally, if a level n (n > 1) has a 0us latency, all | |
1891 | * levels m (m >= n) need to be disabled. We make sure to | |
1892 | * sanitize the values out of the punit to satisfy this | |
1893 | * requirement. | |
367294be VK |
1894 | */ |
1895 | wm[0] += 2; | |
1896 | for (level = 1; level <= max_level; level++) | |
1897 | if (wm[level] != 0) | |
1898 | wm[level] += 2; | |
4f947386 VK |
1899 | else { |
1900 | for (i = level + 1; i <= max_level; i++) | |
1901 | wm[i] = 0; | |
367294be | 1902 | |
4f947386 VK |
1903 | break; |
1904 | } | |
2af30a5c | 1905 | } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) { |
12b134df VS |
1906 | uint64_t sskpd = I915_READ64(MCH_SSKPD); |
1907 | ||
1908 | wm[0] = (sskpd >> 56) & 0xFF; | |
1909 | if (wm[0] == 0) | |
1910 | wm[0] = sskpd & 0xF; | |
e5d5019e VS |
1911 | wm[1] = (sskpd >> 4) & 0xFF; |
1912 | wm[2] = (sskpd >> 12) & 0xFF; | |
1913 | wm[3] = (sskpd >> 20) & 0x1FF; | |
1914 | wm[4] = (sskpd >> 32) & 0x1FF; | |
63cf9a13 VS |
1915 | } else if (INTEL_INFO(dev)->gen >= 6) { |
1916 | uint32_t sskpd = I915_READ(MCH_SSKPD); | |
1917 | ||
1918 | wm[0] = (sskpd >> SSKPD_WM0_SHIFT) & SSKPD_WM_MASK; | |
1919 | wm[1] = (sskpd >> SSKPD_WM1_SHIFT) & SSKPD_WM_MASK; | |
1920 | wm[2] = (sskpd >> SSKPD_WM2_SHIFT) & SSKPD_WM_MASK; | |
1921 | wm[3] = (sskpd >> SSKPD_WM3_SHIFT) & SSKPD_WM_MASK; | |
3a88d0ac VS |
1922 | } else if (INTEL_INFO(dev)->gen >= 5) { |
1923 | uint32_t mltr = I915_READ(MLTR_ILK); | |
1924 | ||
1925 | /* ILK primary LP0 latency is 700 ns */ | |
1926 | wm[0] = 7; | |
1927 | wm[1] = (mltr >> MLTR_WM1_SHIFT) & ILK_SRLT_MASK; | |
1928 | wm[2] = (mltr >> MLTR_WM2_SHIFT) & ILK_SRLT_MASK; | |
12b134df VS |
1929 | } |
1930 | } | |
1931 | ||
53615a5e VS |
1932 | static void intel_fixup_spr_wm_latency(struct drm_device *dev, uint16_t wm[5]) |
1933 | { | |
1934 | /* ILK sprite LP0 latency is 1300 ns */ | |
1935 | if (INTEL_INFO(dev)->gen == 5) | |
1936 | wm[0] = 13; | |
1937 | } | |
1938 | ||
1939 | static void intel_fixup_cur_wm_latency(struct drm_device *dev, uint16_t wm[5]) | |
1940 | { | |
1941 | /* ILK cursor LP0 latency is 1300 ns */ | |
1942 | if (INTEL_INFO(dev)->gen == 5) | |
1943 | wm[0] = 13; | |
1944 | ||
1945 | /* WaDoubleCursorLP3Latency:ivb */ | |
1946 | if (IS_IVYBRIDGE(dev)) | |
1947 | wm[3] *= 2; | |
1948 | } | |
1949 | ||
546c81fd | 1950 | int ilk_wm_max_level(const struct drm_device *dev) |
26ec971e | 1951 | { |
26ec971e | 1952 | /* how many WM levels are we expecting */ |
b6e742f6 | 1953 | if (INTEL_INFO(dev)->gen >= 9) |
2af30a5c PB |
1954 | return 7; |
1955 | else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) | |
ad0d6dc4 | 1956 | return 4; |
26ec971e | 1957 | else if (INTEL_INFO(dev)->gen >= 6) |
ad0d6dc4 | 1958 | return 3; |
26ec971e | 1959 | else |
ad0d6dc4 VS |
1960 | return 2; |
1961 | } | |
7526ed79 | 1962 | |
ad0d6dc4 VS |
1963 | static void intel_print_wm_latency(struct drm_device *dev, |
1964 | const char *name, | |
2af30a5c | 1965 | const uint16_t wm[8]) |
ad0d6dc4 VS |
1966 | { |
1967 | int level, max_level = ilk_wm_max_level(dev); | |
26ec971e VS |
1968 | |
1969 | for (level = 0; level <= max_level; level++) { | |
1970 | unsigned int latency = wm[level]; | |
1971 | ||
1972 | if (latency == 0) { | |
1973 | DRM_ERROR("%s WM%d latency not provided\n", | |
1974 | name, level); | |
1975 | continue; | |
1976 | } | |
1977 | ||
2af30a5c PB |
1978 | /* |
1979 | * - latencies are in us on gen9. | |
1980 | * - before then, WM1+ latency values are in 0.5us units | |
1981 | */ | |
1982 | if (IS_GEN9(dev)) | |
1983 | latency *= 10; | |
1984 | else if (level > 0) | |
26ec971e VS |
1985 | latency *= 5; |
1986 | ||
1987 | DRM_DEBUG_KMS("%s WM%d latency %u (%u.%u usec)\n", | |
1988 | name, level, wm[level], | |
1989 | latency / 10, latency % 10); | |
1990 | } | |
1991 | } | |
1992 | ||
e95a2f75 VS |
1993 | static bool ilk_increase_wm_latency(struct drm_i915_private *dev_priv, |
1994 | uint16_t wm[5], uint16_t min) | |
1995 | { | |
1996 | int level, max_level = ilk_wm_max_level(dev_priv->dev); | |
1997 | ||
1998 | if (wm[0] >= min) | |
1999 | return false; | |
2000 | ||
2001 | wm[0] = max(wm[0], min); | |
2002 | for (level = 1; level <= max_level; level++) | |
2003 | wm[level] = max_t(uint16_t, wm[level], DIV_ROUND_UP(min, 5)); | |
2004 | ||
2005 | return true; | |
2006 | } | |
2007 | ||
2008 | static void snb_wm_latency_quirk(struct drm_device *dev) | |
2009 | { | |
2010 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2011 | bool changed; | |
2012 | ||
2013 | /* | |
2014 | * The BIOS provided WM memory latency values are often | |
2015 | * inadequate for high resolution displays. Adjust them. | |
2016 | */ | |
2017 | changed = ilk_increase_wm_latency(dev_priv, dev_priv->wm.pri_latency, 12) | | |
2018 | ilk_increase_wm_latency(dev_priv, dev_priv->wm.spr_latency, 12) | | |
2019 | ilk_increase_wm_latency(dev_priv, dev_priv->wm.cur_latency, 12); | |
2020 | ||
2021 | if (!changed) | |
2022 | return; | |
2023 | ||
2024 | DRM_DEBUG_KMS("WM latency values increased to avoid potential underruns\n"); | |
2025 | intel_print_wm_latency(dev, "Primary", dev_priv->wm.pri_latency); | |
2026 | intel_print_wm_latency(dev, "Sprite", dev_priv->wm.spr_latency); | |
2027 | intel_print_wm_latency(dev, "Cursor", dev_priv->wm.cur_latency); | |
2028 | } | |
2029 | ||
fa50ad61 | 2030 | static void ilk_setup_wm_latency(struct drm_device *dev) |
53615a5e VS |
2031 | { |
2032 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2033 | ||
2034 | intel_read_wm_latency(dev, dev_priv->wm.pri_latency); | |
2035 | ||
2036 | memcpy(dev_priv->wm.spr_latency, dev_priv->wm.pri_latency, | |
2037 | sizeof(dev_priv->wm.pri_latency)); | |
2038 | memcpy(dev_priv->wm.cur_latency, dev_priv->wm.pri_latency, | |
2039 | sizeof(dev_priv->wm.pri_latency)); | |
2040 | ||
2041 | intel_fixup_spr_wm_latency(dev, dev_priv->wm.spr_latency); | |
2042 | intel_fixup_cur_wm_latency(dev, dev_priv->wm.cur_latency); | |
26ec971e VS |
2043 | |
2044 | intel_print_wm_latency(dev, "Primary", dev_priv->wm.pri_latency); | |
2045 | intel_print_wm_latency(dev, "Sprite", dev_priv->wm.spr_latency); | |
2046 | intel_print_wm_latency(dev, "Cursor", dev_priv->wm.cur_latency); | |
e95a2f75 VS |
2047 | |
2048 | if (IS_GEN6(dev)) | |
2049 | snb_wm_latency_quirk(dev); | |
53615a5e VS |
2050 | } |
2051 | ||
2af30a5c PB |
2052 | static void skl_setup_wm_latency(struct drm_device *dev) |
2053 | { | |
2054 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2055 | ||
2056 | intel_read_wm_latency(dev, dev_priv->wm.skl_latency); | |
2057 | intel_print_wm_latency(dev, "Gen9 Plane", dev_priv->wm.skl_latency); | |
2058 | } | |
2059 | ||
820c1980 | 2060 | static void ilk_compute_wm_parameters(struct drm_crtc *crtc, |
2a44b76b | 2061 | struct ilk_pipe_wm_parameters *p) |
1011d8c4 | 2062 | { |
7c4a395f VS |
2063 | struct drm_device *dev = crtc->dev; |
2064 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
2065 | enum pipe pipe = intel_crtc->pipe; | |
7c4a395f | 2066 | struct drm_plane *plane; |
1011d8c4 | 2067 | |
3ef00284 | 2068 | if (!intel_crtc->active) |
2a44b76b | 2069 | return; |
801bcfff | 2070 | |
2a44b76b | 2071 | p->active = true; |
6e3c9717 | 2072 | p->pipe_htotal = intel_crtc->config->base.adjusted_mode.crtc_htotal; |
8cfb3407 | 2073 | p->pixel_rate = ilk_pipe_pixel_rate(intel_crtc->config); |
c9f038a1 | 2074 | |
54da691d | 2075 | if (crtc->primary->state->fb) |
c9f038a1 MR |
2076 | p->pri.bytes_per_pixel = |
2077 | crtc->primary->state->fb->bits_per_pixel / 8; | |
54da691d TG |
2078 | else |
2079 | p->pri.bytes_per_pixel = 4; | |
2080 | ||
2081 | p->cur.bytes_per_pixel = 4; | |
2082 | /* | |
2083 | * TODO: for now, assume primary and cursor planes are always enabled. | |
2084 | * Setting them to false makes the screen flicker. | |
2085 | */ | |
2086 | p->pri.enabled = true; | |
2087 | p->cur.enabled = true; | |
c9f038a1 | 2088 | |
6e3c9717 | 2089 | p->pri.horiz_pixels = intel_crtc->config->pipe_src_w; |
3dd512fb | 2090 | p->cur.horiz_pixels = intel_crtc->base.cursor->state->crtc_w; |
7c4a395f | 2091 | |
af2b653b | 2092 | drm_for_each_legacy_plane(plane, &dev->mode_config.plane_list) { |
801bcfff | 2093 | struct intel_plane *intel_plane = to_intel_plane(plane); |
801bcfff | 2094 | |
2a44b76b | 2095 | if (intel_plane->pipe == pipe) { |
7c4a395f | 2096 | p->spr = intel_plane->wm; |
2a44b76b VS |
2097 | break; |
2098 | } | |
2099 | } | |
2100 | } | |
2101 | ||
2102 | static void ilk_compute_wm_config(struct drm_device *dev, | |
2103 | struct intel_wm_config *config) | |
2104 | { | |
2105 | struct intel_crtc *intel_crtc; | |
2106 | ||
2107 | /* Compute the currently _active_ config */ | |
d3fcc808 | 2108 | for_each_intel_crtc(dev, intel_crtc) { |
2a44b76b | 2109 | const struct intel_pipe_wm *wm = &intel_crtc->wm.active; |
cca32e9a | 2110 | |
2a44b76b VS |
2111 | if (!wm->pipe_enabled) |
2112 | continue; | |
cca32e9a | 2113 | |
2a44b76b VS |
2114 | config->sprites_enabled |= wm->sprites_enabled; |
2115 | config->sprites_scaled |= wm->sprites_scaled; | |
2116 | config->num_pipes_active++; | |
cca32e9a | 2117 | } |
801bcfff PZ |
2118 | } |
2119 | ||
0b2ae6d7 VS |
2120 | /* Compute new watermarks for the pipe */ |
2121 | static bool intel_compute_pipe_wm(struct drm_crtc *crtc, | |
820c1980 | 2122 | const struct ilk_pipe_wm_parameters *params, |
0b2ae6d7 VS |
2123 | struct intel_pipe_wm *pipe_wm) |
2124 | { | |
2125 | struct drm_device *dev = crtc->dev; | |
d34ff9c6 | 2126 | const struct drm_i915_private *dev_priv = dev->dev_private; |
0b2ae6d7 VS |
2127 | int level, max_level = ilk_wm_max_level(dev); |
2128 | /* LP0 watermark maximums depend on this pipe alone */ | |
2129 | struct intel_wm_config config = { | |
2130 | .num_pipes_active = 1, | |
2131 | .sprites_enabled = params->spr.enabled, | |
2132 | .sprites_scaled = params->spr.scaled, | |
2133 | }; | |
820c1980 | 2134 | struct ilk_wm_maximums max; |
0b2ae6d7 | 2135 | |
2a44b76b VS |
2136 | pipe_wm->pipe_enabled = params->active; |
2137 | pipe_wm->sprites_enabled = params->spr.enabled; | |
2138 | pipe_wm->sprites_scaled = params->spr.scaled; | |
2139 | ||
7b39a0b7 VS |
2140 | /* ILK/SNB: LP2+ watermarks only w/o sprites */ |
2141 | if (INTEL_INFO(dev)->gen <= 6 && params->spr.enabled) | |
2142 | max_level = 1; | |
2143 | ||
2144 | /* ILK/SNB/IVB: LP1+ watermarks only w/o scaling */ | |
2145 | if (params->spr.scaled) | |
2146 | max_level = 0; | |
2147 | ||
a3cb4048 | 2148 | ilk_compute_wm_level(dev_priv, 0, params, &pipe_wm->wm[0]); |
0b2ae6d7 | 2149 | |
a42a5719 | 2150 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) |
ce0e0713 | 2151 | pipe_wm->linetime = hsw_compute_linetime_wm(dev, crtc); |
0b2ae6d7 | 2152 | |
a3cb4048 VS |
2153 | /* LP0 watermarks always use 1/2 DDB partitioning */ |
2154 | ilk_compute_wm_maximums(dev, 0, &config, INTEL_DDB_PART_1_2, &max); | |
2155 | ||
0b2ae6d7 | 2156 | /* At least LP0 must be valid */ |
a3cb4048 VS |
2157 | if (!ilk_validate_wm_level(0, &max, &pipe_wm->wm[0])) |
2158 | return false; | |
2159 | ||
2160 | ilk_compute_wm_reg_maximums(dev, 1, &max); | |
2161 | ||
2162 | for (level = 1; level <= max_level; level++) { | |
2163 | struct intel_wm_level wm = {}; | |
2164 | ||
2165 | ilk_compute_wm_level(dev_priv, level, params, &wm); | |
2166 | ||
2167 | /* | |
2168 | * Disable any watermark level that exceeds the | |
2169 | * register maximums since such watermarks are | |
2170 | * always invalid. | |
2171 | */ | |
2172 | if (!ilk_validate_wm_level(level, &max, &wm)) | |
2173 | break; | |
2174 | ||
2175 | pipe_wm->wm[level] = wm; | |
2176 | } | |
2177 | ||
2178 | return true; | |
0b2ae6d7 VS |
2179 | } |
2180 | ||
2181 | /* | |
2182 | * Merge the watermarks from all active pipes for a specific level. | |
2183 | */ | |
2184 | static void ilk_merge_wm_level(struct drm_device *dev, | |
2185 | int level, | |
2186 | struct intel_wm_level *ret_wm) | |
2187 | { | |
2188 | const struct intel_crtc *intel_crtc; | |
2189 | ||
d52fea5b VS |
2190 | ret_wm->enable = true; |
2191 | ||
d3fcc808 | 2192 | for_each_intel_crtc(dev, intel_crtc) { |
fe392efd VS |
2193 | const struct intel_pipe_wm *active = &intel_crtc->wm.active; |
2194 | const struct intel_wm_level *wm = &active->wm[level]; | |
2195 | ||
2196 | if (!active->pipe_enabled) | |
2197 | continue; | |
0b2ae6d7 | 2198 | |
d52fea5b VS |
2199 | /* |
2200 | * The watermark values may have been used in the past, | |
2201 | * so we must maintain them in the registers for some | |
2202 | * time even if the level is now disabled. | |
2203 | */ | |
0b2ae6d7 | 2204 | if (!wm->enable) |
d52fea5b | 2205 | ret_wm->enable = false; |
0b2ae6d7 VS |
2206 | |
2207 | ret_wm->pri_val = max(ret_wm->pri_val, wm->pri_val); | |
2208 | ret_wm->spr_val = max(ret_wm->spr_val, wm->spr_val); | |
2209 | ret_wm->cur_val = max(ret_wm->cur_val, wm->cur_val); | |
2210 | ret_wm->fbc_val = max(ret_wm->fbc_val, wm->fbc_val); | |
2211 | } | |
0b2ae6d7 VS |
2212 | } |
2213 | ||
2214 | /* | |
2215 | * Merge all low power watermarks for all active pipes. | |
2216 | */ | |
2217 | static void ilk_wm_merge(struct drm_device *dev, | |
0ba22e26 | 2218 | const struct intel_wm_config *config, |
820c1980 | 2219 | const struct ilk_wm_maximums *max, |
0b2ae6d7 VS |
2220 | struct intel_pipe_wm *merged) |
2221 | { | |
2222 | int level, max_level = ilk_wm_max_level(dev); | |
d52fea5b | 2223 | int last_enabled_level = max_level; |
0b2ae6d7 | 2224 | |
0ba22e26 VS |
2225 | /* ILK/SNB/IVB: LP1+ watermarks only w/ single pipe */ |
2226 | if ((INTEL_INFO(dev)->gen <= 6 || IS_IVYBRIDGE(dev)) && | |
2227 | config->num_pipes_active > 1) | |
2228 | return; | |
2229 | ||
6c8b6c28 VS |
2230 | /* ILK: FBC WM must be disabled always */ |
2231 | merged->fbc_wm_enabled = INTEL_INFO(dev)->gen >= 6; | |
0b2ae6d7 VS |
2232 | |
2233 | /* merge each WM1+ level */ | |
2234 | for (level = 1; level <= max_level; level++) { | |
2235 | struct intel_wm_level *wm = &merged->wm[level]; | |
2236 | ||
2237 | ilk_merge_wm_level(dev, level, wm); | |
2238 | ||
d52fea5b VS |
2239 | if (level > last_enabled_level) |
2240 | wm->enable = false; | |
2241 | else if (!ilk_validate_wm_level(level, max, wm)) | |
2242 | /* make sure all following levels get disabled */ | |
2243 | last_enabled_level = level - 1; | |
0b2ae6d7 VS |
2244 | |
2245 | /* | |
2246 | * The spec says it is preferred to disable | |
2247 | * FBC WMs instead of disabling a WM level. | |
2248 | */ | |
2249 | if (wm->fbc_val > max->fbc) { | |
d52fea5b VS |
2250 | if (wm->enable) |
2251 | merged->fbc_wm_enabled = false; | |
0b2ae6d7 VS |
2252 | wm->fbc_val = 0; |
2253 | } | |
2254 | } | |
6c8b6c28 VS |
2255 | |
2256 | /* ILK: LP2+ must be disabled when FBC WM is disabled but FBC enabled */ | |
2257 | /* | |
2258 | * FIXME this is racy. FBC might get enabled later. | |
2259 | * What we should check here is whether FBC can be | |
2260 | * enabled sometime later. | |
2261 | */ | |
2262 | if (IS_GEN5(dev) && !merged->fbc_wm_enabled && intel_fbc_enabled(dev)) { | |
2263 | for (level = 2; level <= max_level; level++) { | |
2264 | struct intel_wm_level *wm = &merged->wm[level]; | |
2265 | ||
2266 | wm->enable = false; | |
2267 | } | |
2268 | } | |
0b2ae6d7 VS |
2269 | } |
2270 | ||
b380ca3c VS |
2271 | static int ilk_wm_lp_to_level(int wm_lp, const struct intel_pipe_wm *pipe_wm) |
2272 | { | |
2273 | /* LP1,LP2,LP3 levels are either 1,2,3 or 1,3,4 */ | |
2274 | return wm_lp + (wm_lp >= 2 && pipe_wm->wm[4].enable); | |
2275 | } | |
2276 | ||
a68d68ee VS |
2277 | /* The value we need to program into the WM_LPx latency field */ |
2278 | static unsigned int ilk_wm_lp_latency(struct drm_device *dev, int level) | |
2279 | { | |
2280 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2281 | ||
a42a5719 | 2282 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) |
a68d68ee VS |
2283 | return 2 * level; |
2284 | else | |
2285 | return dev_priv->wm.pri_latency[level]; | |
2286 | } | |
2287 | ||
820c1980 | 2288 | static void ilk_compute_wm_results(struct drm_device *dev, |
0362c781 | 2289 | const struct intel_pipe_wm *merged, |
609cedef | 2290 | enum intel_ddb_partitioning partitioning, |
820c1980 | 2291 | struct ilk_wm_values *results) |
801bcfff | 2292 | { |
0b2ae6d7 VS |
2293 | struct intel_crtc *intel_crtc; |
2294 | int level, wm_lp; | |
cca32e9a | 2295 | |
0362c781 | 2296 | results->enable_fbc_wm = merged->fbc_wm_enabled; |
609cedef | 2297 | results->partitioning = partitioning; |
cca32e9a | 2298 | |
0b2ae6d7 | 2299 | /* LP1+ register values */ |
cca32e9a | 2300 | for (wm_lp = 1; wm_lp <= 3; wm_lp++) { |
1fd527cc | 2301 | const struct intel_wm_level *r; |
801bcfff | 2302 | |
b380ca3c | 2303 | level = ilk_wm_lp_to_level(wm_lp, merged); |
0b2ae6d7 | 2304 | |
0362c781 | 2305 | r = &merged->wm[level]; |
cca32e9a | 2306 | |
d52fea5b VS |
2307 | /* |
2308 | * Maintain the watermark values even if the level is | |
2309 | * disabled. Doing otherwise could cause underruns. | |
2310 | */ | |
2311 | results->wm_lp[wm_lp - 1] = | |
a68d68ee | 2312 | (ilk_wm_lp_latency(dev, level) << WM1_LP_LATENCY_SHIFT) | |
416f4727 VS |
2313 | (r->pri_val << WM1_LP_SR_SHIFT) | |
2314 | r->cur_val; | |
2315 | ||
d52fea5b VS |
2316 | if (r->enable) |
2317 | results->wm_lp[wm_lp - 1] |= WM1_LP_SR_EN; | |
2318 | ||
416f4727 VS |
2319 | if (INTEL_INFO(dev)->gen >= 8) |
2320 | results->wm_lp[wm_lp - 1] |= | |
2321 | r->fbc_val << WM1_LP_FBC_SHIFT_BDW; | |
2322 | else | |
2323 | results->wm_lp[wm_lp - 1] |= | |
2324 | r->fbc_val << WM1_LP_FBC_SHIFT; | |
2325 | ||
d52fea5b VS |
2326 | /* |
2327 | * Always set WM1S_LP_EN when spr_val != 0, even if the | |
2328 | * level is disabled. Doing otherwise could cause underruns. | |
2329 | */ | |
6cef2b8a VS |
2330 | if (INTEL_INFO(dev)->gen <= 6 && r->spr_val) { |
2331 | WARN_ON(wm_lp != 1); | |
2332 | results->wm_lp_spr[wm_lp - 1] = WM1S_LP_EN | r->spr_val; | |
2333 | } else | |
2334 | results->wm_lp_spr[wm_lp - 1] = r->spr_val; | |
cca32e9a | 2335 | } |
801bcfff | 2336 | |
0b2ae6d7 | 2337 | /* LP0 register values */ |
d3fcc808 | 2338 | for_each_intel_crtc(dev, intel_crtc) { |
0b2ae6d7 VS |
2339 | enum pipe pipe = intel_crtc->pipe; |
2340 | const struct intel_wm_level *r = | |
2341 | &intel_crtc->wm.active.wm[0]; | |
2342 | ||
2343 | if (WARN_ON(!r->enable)) | |
2344 | continue; | |
2345 | ||
2346 | results->wm_linetime[pipe] = intel_crtc->wm.active.linetime; | |
1011d8c4 | 2347 | |
0b2ae6d7 VS |
2348 | results->wm_pipe[pipe] = |
2349 | (r->pri_val << WM0_PIPE_PLANE_SHIFT) | | |
2350 | (r->spr_val << WM0_PIPE_SPRITE_SHIFT) | | |
2351 | r->cur_val; | |
801bcfff PZ |
2352 | } |
2353 | } | |
2354 | ||
861f3389 PZ |
2355 | /* Find the result with the highest level enabled. Check for enable_fbc_wm in |
2356 | * case both are at the same level. Prefer r1 in case they're the same. */ | |
820c1980 | 2357 | static struct intel_pipe_wm *ilk_find_best_result(struct drm_device *dev, |
198a1e9b VS |
2358 | struct intel_pipe_wm *r1, |
2359 | struct intel_pipe_wm *r2) | |
861f3389 | 2360 | { |
198a1e9b VS |
2361 | int level, max_level = ilk_wm_max_level(dev); |
2362 | int level1 = 0, level2 = 0; | |
861f3389 | 2363 | |
198a1e9b VS |
2364 | for (level = 1; level <= max_level; level++) { |
2365 | if (r1->wm[level].enable) | |
2366 | level1 = level; | |
2367 | if (r2->wm[level].enable) | |
2368 | level2 = level; | |
861f3389 PZ |
2369 | } |
2370 | ||
198a1e9b VS |
2371 | if (level1 == level2) { |
2372 | if (r2->fbc_wm_enabled && !r1->fbc_wm_enabled) | |
861f3389 PZ |
2373 | return r2; |
2374 | else | |
2375 | return r1; | |
198a1e9b | 2376 | } else if (level1 > level2) { |
861f3389 PZ |
2377 | return r1; |
2378 | } else { | |
2379 | return r2; | |
2380 | } | |
2381 | } | |
2382 | ||
49a687c4 VS |
2383 | /* dirty bits used to track which watermarks need changes */ |
2384 | #define WM_DIRTY_PIPE(pipe) (1 << (pipe)) | |
2385 | #define WM_DIRTY_LINETIME(pipe) (1 << (8 + (pipe))) | |
2386 | #define WM_DIRTY_LP(wm_lp) (1 << (15 + (wm_lp))) | |
2387 | #define WM_DIRTY_LP_ALL (WM_DIRTY_LP(1) | WM_DIRTY_LP(2) | WM_DIRTY_LP(3)) | |
2388 | #define WM_DIRTY_FBC (1 << 24) | |
2389 | #define WM_DIRTY_DDB (1 << 25) | |
2390 | ||
055e393f | 2391 | static unsigned int ilk_compute_wm_dirty(struct drm_i915_private *dev_priv, |
820c1980 ID |
2392 | const struct ilk_wm_values *old, |
2393 | const struct ilk_wm_values *new) | |
49a687c4 VS |
2394 | { |
2395 | unsigned int dirty = 0; | |
2396 | enum pipe pipe; | |
2397 | int wm_lp; | |
2398 | ||
055e393f | 2399 | for_each_pipe(dev_priv, pipe) { |
49a687c4 VS |
2400 | if (old->wm_linetime[pipe] != new->wm_linetime[pipe]) { |
2401 | dirty |= WM_DIRTY_LINETIME(pipe); | |
2402 | /* Must disable LP1+ watermarks too */ | |
2403 | dirty |= WM_DIRTY_LP_ALL; | |
2404 | } | |
2405 | ||
2406 | if (old->wm_pipe[pipe] != new->wm_pipe[pipe]) { | |
2407 | dirty |= WM_DIRTY_PIPE(pipe); | |
2408 | /* Must disable LP1+ watermarks too */ | |
2409 | dirty |= WM_DIRTY_LP_ALL; | |
2410 | } | |
2411 | } | |
2412 | ||
2413 | if (old->enable_fbc_wm != new->enable_fbc_wm) { | |
2414 | dirty |= WM_DIRTY_FBC; | |
2415 | /* Must disable LP1+ watermarks too */ | |
2416 | dirty |= WM_DIRTY_LP_ALL; | |
2417 | } | |
2418 | ||
2419 | if (old->partitioning != new->partitioning) { | |
2420 | dirty |= WM_DIRTY_DDB; | |
2421 | /* Must disable LP1+ watermarks too */ | |
2422 | dirty |= WM_DIRTY_LP_ALL; | |
2423 | } | |
2424 | ||
2425 | /* LP1+ watermarks already deemed dirty, no need to continue */ | |
2426 | if (dirty & WM_DIRTY_LP_ALL) | |
2427 | return dirty; | |
2428 | ||
2429 | /* Find the lowest numbered LP1+ watermark in need of an update... */ | |
2430 | for (wm_lp = 1; wm_lp <= 3; wm_lp++) { | |
2431 | if (old->wm_lp[wm_lp - 1] != new->wm_lp[wm_lp - 1] || | |
2432 | old->wm_lp_spr[wm_lp - 1] != new->wm_lp_spr[wm_lp - 1]) | |
2433 | break; | |
2434 | } | |
2435 | ||
2436 | /* ...and mark it and all higher numbered LP1+ watermarks as dirty */ | |
2437 | for (; wm_lp <= 3; wm_lp++) | |
2438 | dirty |= WM_DIRTY_LP(wm_lp); | |
2439 | ||
2440 | return dirty; | |
2441 | } | |
2442 | ||
8553c18e VS |
2443 | static bool _ilk_disable_lp_wm(struct drm_i915_private *dev_priv, |
2444 | unsigned int dirty) | |
801bcfff | 2445 | { |
820c1980 | 2446 | struct ilk_wm_values *previous = &dev_priv->wm.hw; |
8553c18e | 2447 | bool changed = false; |
801bcfff | 2448 | |
facd619b VS |
2449 | if (dirty & WM_DIRTY_LP(3) && previous->wm_lp[2] & WM1_LP_SR_EN) { |
2450 | previous->wm_lp[2] &= ~WM1_LP_SR_EN; | |
2451 | I915_WRITE(WM3_LP_ILK, previous->wm_lp[2]); | |
8553c18e | 2452 | changed = true; |
facd619b VS |
2453 | } |
2454 | if (dirty & WM_DIRTY_LP(2) && previous->wm_lp[1] & WM1_LP_SR_EN) { | |
2455 | previous->wm_lp[1] &= ~WM1_LP_SR_EN; | |
2456 | I915_WRITE(WM2_LP_ILK, previous->wm_lp[1]); | |
8553c18e | 2457 | changed = true; |
facd619b VS |
2458 | } |
2459 | if (dirty & WM_DIRTY_LP(1) && previous->wm_lp[0] & WM1_LP_SR_EN) { | |
2460 | previous->wm_lp[0] &= ~WM1_LP_SR_EN; | |
2461 | I915_WRITE(WM1_LP_ILK, previous->wm_lp[0]); | |
8553c18e | 2462 | changed = true; |
facd619b | 2463 | } |
801bcfff | 2464 | |
facd619b VS |
2465 | /* |
2466 | * Don't touch WM1S_LP_EN here. | |
2467 | * Doing so could cause underruns. | |
2468 | */ | |
6cef2b8a | 2469 | |
8553c18e VS |
2470 | return changed; |
2471 | } | |
2472 | ||
2473 | /* | |
2474 | * The spec says we shouldn't write when we don't need, because every write | |
2475 | * causes WMs to be re-evaluated, expending some power. | |
2476 | */ | |
820c1980 ID |
2477 | static void ilk_write_wm_values(struct drm_i915_private *dev_priv, |
2478 | struct ilk_wm_values *results) | |
8553c18e VS |
2479 | { |
2480 | struct drm_device *dev = dev_priv->dev; | |
820c1980 | 2481 | struct ilk_wm_values *previous = &dev_priv->wm.hw; |
8553c18e VS |
2482 | unsigned int dirty; |
2483 | uint32_t val; | |
2484 | ||
055e393f | 2485 | dirty = ilk_compute_wm_dirty(dev_priv, previous, results); |
8553c18e VS |
2486 | if (!dirty) |
2487 | return; | |
2488 | ||
2489 | _ilk_disable_lp_wm(dev_priv, dirty); | |
2490 | ||
49a687c4 | 2491 | if (dirty & WM_DIRTY_PIPE(PIPE_A)) |
801bcfff | 2492 | I915_WRITE(WM0_PIPEA_ILK, results->wm_pipe[0]); |
49a687c4 | 2493 | if (dirty & WM_DIRTY_PIPE(PIPE_B)) |
801bcfff | 2494 | I915_WRITE(WM0_PIPEB_ILK, results->wm_pipe[1]); |
49a687c4 | 2495 | if (dirty & WM_DIRTY_PIPE(PIPE_C)) |
801bcfff PZ |
2496 | I915_WRITE(WM0_PIPEC_IVB, results->wm_pipe[2]); |
2497 | ||
49a687c4 | 2498 | if (dirty & WM_DIRTY_LINETIME(PIPE_A)) |
801bcfff | 2499 | I915_WRITE(PIPE_WM_LINETIME(PIPE_A), results->wm_linetime[0]); |
49a687c4 | 2500 | if (dirty & WM_DIRTY_LINETIME(PIPE_B)) |
801bcfff | 2501 | I915_WRITE(PIPE_WM_LINETIME(PIPE_B), results->wm_linetime[1]); |
49a687c4 | 2502 | if (dirty & WM_DIRTY_LINETIME(PIPE_C)) |
801bcfff PZ |
2503 | I915_WRITE(PIPE_WM_LINETIME(PIPE_C), results->wm_linetime[2]); |
2504 | ||
49a687c4 | 2505 | if (dirty & WM_DIRTY_DDB) { |
a42a5719 | 2506 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) { |
ac9545fd VS |
2507 | val = I915_READ(WM_MISC); |
2508 | if (results->partitioning == INTEL_DDB_PART_1_2) | |
2509 | val &= ~WM_MISC_DATA_PARTITION_5_6; | |
2510 | else | |
2511 | val |= WM_MISC_DATA_PARTITION_5_6; | |
2512 | I915_WRITE(WM_MISC, val); | |
2513 | } else { | |
2514 | val = I915_READ(DISP_ARB_CTL2); | |
2515 | if (results->partitioning == INTEL_DDB_PART_1_2) | |
2516 | val &= ~DISP_DATA_PARTITION_5_6; | |
2517 | else | |
2518 | val |= DISP_DATA_PARTITION_5_6; | |
2519 | I915_WRITE(DISP_ARB_CTL2, val); | |
2520 | } | |
1011d8c4 PZ |
2521 | } |
2522 | ||
49a687c4 | 2523 | if (dirty & WM_DIRTY_FBC) { |
cca32e9a PZ |
2524 | val = I915_READ(DISP_ARB_CTL); |
2525 | if (results->enable_fbc_wm) | |
2526 | val &= ~DISP_FBC_WM_DIS; | |
2527 | else | |
2528 | val |= DISP_FBC_WM_DIS; | |
2529 | I915_WRITE(DISP_ARB_CTL, val); | |
2530 | } | |
2531 | ||
954911eb ID |
2532 | if (dirty & WM_DIRTY_LP(1) && |
2533 | previous->wm_lp_spr[0] != results->wm_lp_spr[0]) | |
2534 | I915_WRITE(WM1S_LP_ILK, results->wm_lp_spr[0]); | |
2535 | ||
2536 | if (INTEL_INFO(dev)->gen >= 7) { | |
6cef2b8a VS |
2537 | if (dirty & WM_DIRTY_LP(2) && previous->wm_lp_spr[1] != results->wm_lp_spr[1]) |
2538 | I915_WRITE(WM2S_LP_IVB, results->wm_lp_spr[1]); | |
2539 | if (dirty & WM_DIRTY_LP(3) && previous->wm_lp_spr[2] != results->wm_lp_spr[2]) | |
2540 | I915_WRITE(WM3S_LP_IVB, results->wm_lp_spr[2]); | |
2541 | } | |
801bcfff | 2542 | |
facd619b | 2543 | if (dirty & WM_DIRTY_LP(1) && previous->wm_lp[0] != results->wm_lp[0]) |
801bcfff | 2544 | I915_WRITE(WM1_LP_ILK, results->wm_lp[0]); |
facd619b | 2545 | if (dirty & WM_DIRTY_LP(2) && previous->wm_lp[1] != results->wm_lp[1]) |
801bcfff | 2546 | I915_WRITE(WM2_LP_ILK, results->wm_lp[1]); |
facd619b | 2547 | if (dirty & WM_DIRTY_LP(3) && previous->wm_lp[2] != results->wm_lp[2]) |
801bcfff | 2548 | I915_WRITE(WM3_LP_ILK, results->wm_lp[2]); |
609cedef VS |
2549 | |
2550 | dev_priv->wm.hw = *results; | |
801bcfff PZ |
2551 | } |
2552 | ||
8553c18e VS |
2553 | static bool ilk_disable_lp_wm(struct drm_device *dev) |
2554 | { | |
2555 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2556 | ||
2557 | return _ilk_disable_lp_wm(dev_priv, WM_DIRTY_LP_ALL); | |
2558 | } | |
2559 | ||
b9cec075 DL |
2560 | /* |
2561 | * On gen9, we need to allocate Display Data Buffer (DDB) portions to the | |
2562 | * different active planes. | |
2563 | */ | |
2564 | ||
2565 | #define SKL_DDB_SIZE 896 /* in blocks */ | |
43d735a6 | 2566 | #define BXT_DDB_SIZE 512 |
b9cec075 DL |
2567 | |
2568 | static void | |
2569 | skl_ddb_get_pipe_allocation_limits(struct drm_device *dev, | |
2570 | struct drm_crtc *for_crtc, | |
2571 | const struct intel_wm_config *config, | |
2572 | const struct skl_pipe_wm_parameters *params, | |
2573 | struct skl_ddb_entry *alloc /* out */) | |
2574 | { | |
2575 | struct drm_crtc *crtc; | |
2576 | unsigned int pipe_size, ddb_size; | |
2577 | int nth_active_pipe; | |
2578 | ||
2579 | if (!params->active) { | |
2580 | alloc->start = 0; | |
2581 | alloc->end = 0; | |
2582 | return; | |
2583 | } | |
2584 | ||
43d735a6 DL |
2585 | if (IS_BROXTON(dev)) |
2586 | ddb_size = BXT_DDB_SIZE; | |
2587 | else | |
2588 | ddb_size = SKL_DDB_SIZE; | |
b9cec075 DL |
2589 | |
2590 | ddb_size -= 4; /* 4 blocks for bypass path allocation */ | |
2591 | ||
2592 | nth_active_pipe = 0; | |
2593 | for_each_crtc(dev, crtc) { | |
3ef00284 | 2594 | if (!to_intel_crtc(crtc)->active) |
b9cec075 DL |
2595 | continue; |
2596 | ||
2597 | if (crtc == for_crtc) | |
2598 | break; | |
2599 | ||
2600 | nth_active_pipe++; | |
2601 | } | |
2602 | ||
2603 | pipe_size = ddb_size / config->num_pipes_active; | |
2604 | alloc->start = nth_active_pipe * ddb_size / config->num_pipes_active; | |
16160e3d | 2605 | alloc->end = alloc->start + pipe_size; |
b9cec075 DL |
2606 | } |
2607 | ||
2608 | static unsigned int skl_cursor_allocation(const struct intel_wm_config *config) | |
2609 | { | |
2610 | if (config->num_pipes_active == 1) | |
2611 | return 32; | |
2612 | ||
2613 | return 8; | |
2614 | } | |
2615 | ||
a269c583 DL |
2616 | static void skl_ddb_entry_init_from_hw(struct skl_ddb_entry *entry, u32 reg) |
2617 | { | |
2618 | entry->start = reg & 0x3ff; | |
2619 | entry->end = (reg >> 16) & 0x3ff; | |
16160e3d DL |
2620 | if (entry->end) |
2621 | entry->end += 1; | |
a269c583 DL |
2622 | } |
2623 | ||
08db6652 DL |
2624 | void skl_ddb_get_hw_state(struct drm_i915_private *dev_priv, |
2625 | struct skl_ddb_allocation *ddb /* out */) | |
a269c583 | 2626 | { |
a269c583 DL |
2627 | enum pipe pipe; |
2628 | int plane; | |
2629 | u32 val; | |
2630 | ||
2631 | for_each_pipe(dev_priv, pipe) { | |
dd740780 | 2632 | for_each_plane(dev_priv, pipe, plane) { |
a269c583 DL |
2633 | val = I915_READ(PLANE_BUF_CFG(pipe, plane)); |
2634 | skl_ddb_entry_init_from_hw(&ddb->plane[pipe][plane], | |
2635 | val); | |
2636 | } | |
2637 | ||
2638 | val = I915_READ(CUR_BUF_CFG(pipe)); | |
2639 | skl_ddb_entry_init_from_hw(&ddb->cursor[pipe], val); | |
2640 | } | |
2641 | } | |
2642 | ||
b9cec075 | 2643 | static unsigned int |
2cd601c6 | 2644 | skl_plane_relative_data_rate(const struct intel_plane_wm_parameters *p, int y) |
b9cec075 | 2645 | { |
2cd601c6 CK |
2646 | |
2647 | /* for planar format */ | |
2648 | if (p->y_bytes_per_pixel) { | |
2649 | if (y) /* y-plane data rate */ | |
2650 | return p->horiz_pixels * p->vert_pixels * p->y_bytes_per_pixel; | |
2651 | else /* uv-plane data rate */ | |
2652 | return (p->horiz_pixels/2) * (p->vert_pixels/2) * p->bytes_per_pixel; | |
2653 | } | |
2654 | ||
2655 | /* for packed formats */ | |
b9cec075 DL |
2656 | return p->horiz_pixels * p->vert_pixels * p->bytes_per_pixel; |
2657 | } | |
2658 | ||
2659 | /* | |
2660 | * We don't overflow 32 bits. Worst case is 3 planes enabled, each fetching | |
2661 | * a 8192x4096@32bpp framebuffer: | |
2662 | * 3 * 4096 * 8192 * 4 < 2^32 | |
2663 | */ | |
2664 | static unsigned int | |
2665 | skl_get_total_relative_data_rate(struct intel_crtc *intel_crtc, | |
2666 | const struct skl_pipe_wm_parameters *params) | |
2667 | { | |
2668 | unsigned int total_data_rate = 0; | |
2669 | int plane; | |
2670 | ||
2671 | for (plane = 0; plane < intel_num_planes(intel_crtc); plane++) { | |
2672 | const struct intel_plane_wm_parameters *p; | |
2673 | ||
2674 | p = ¶ms->plane[plane]; | |
2675 | if (!p->enabled) | |
2676 | continue; | |
2677 | ||
2cd601c6 CK |
2678 | total_data_rate += skl_plane_relative_data_rate(p, 0); /* packed/uv */ |
2679 | if (p->y_bytes_per_pixel) { | |
2680 | total_data_rate += skl_plane_relative_data_rate(p, 1); /* y-plane */ | |
2681 | } | |
b9cec075 DL |
2682 | } |
2683 | ||
2684 | return total_data_rate; | |
2685 | } | |
2686 | ||
2687 | static void | |
2688 | skl_allocate_pipe_ddb(struct drm_crtc *crtc, | |
2689 | const struct intel_wm_config *config, | |
2690 | const struct skl_pipe_wm_parameters *params, | |
2691 | struct skl_ddb_allocation *ddb /* out */) | |
2692 | { | |
2693 | struct drm_device *dev = crtc->dev; | |
dd740780 | 2694 | struct drm_i915_private *dev_priv = dev->dev_private; |
b9cec075 DL |
2695 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
2696 | enum pipe pipe = intel_crtc->pipe; | |
34bb56af | 2697 | struct skl_ddb_entry *alloc = &ddb->pipe[pipe]; |
b9cec075 | 2698 | uint16_t alloc_size, start, cursor_blocks; |
80958155 | 2699 | uint16_t minimum[I915_MAX_PLANES]; |
2cd601c6 | 2700 | uint16_t y_minimum[I915_MAX_PLANES]; |
b9cec075 DL |
2701 | unsigned int total_data_rate; |
2702 | int plane; | |
2703 | ||
34bb56af DL |
2704 | skl_ddb_get_pipe_allocation_limits(dev, crtc, config, params, alloc); |
2705 | alloc_size = skl_ddb_entry_size(alloc); | |
b9cec075 DL |
2706 | if (alloc_size == 0) { |
2707 | memset(ddb->plane[pipe], 0, sizeof(ddb->plane[pipe])); | |
2708 | memset(&ddb->cursor[pipe], 0, sizeof(ddb->cursor[pipe])); | |
2709 | return; | |
2710 | } | |
2711 | ||
2712 | cursor_blocks = skl_cursor_allocation(config); | |
34bb56af DL |
2713 | ddb->cursor[pipe].start = alloc->end - cursor_blocks; |
2714 | ddb->cursor[pipe].end = alloc->end; | |
b9cec075 DL |
2715 | |
2716 | alloc_size -= cursor_blocks; | |
34bb56af | 2717 | alloc->end -= cursor_blocks; |
b9cec075 | 2718 | |
80958155 | 2719 | /* 1. Allocate the mininum required blocks for each active plane */ |
dd740780 | 2720 | for_each_plane(dev_priv, pipe, plane) { |
80958155 DL |
2721 | const struct intel_plane_wm_parameters *p; |
2722 | ||
2723 | p = ¶ms->plane[plane]; | |
2724 | if (!p->enabled) | |
2725 | continue; | |
2726 | ||
2727 | minimum[plane] = 8; | |
2728 | alloc_size -= minimum[plane]; | |
2cd601c6 CK |
2729 | y_minimum[plane] = p->y_bytes_per_pixel ? 8 : 0; |
2730 | alloc_size -= y_minimum[plane]; | |
80958155 DL |
2731 | } |
2732 | ||
b9cec075 | 2733 | /* |
80958155 DL |
2734 | * 2. Distribute the remaining space in proportion to the amount of |
2735 | * data each plane needs to fetch from memory. | |
b9cec075 DL |
2736 | * |
2737 | * FIXME: we may not allocate every single block here. | |
2738 | */ | |
2739 | total_data_rate = skl_get_total_relative_data_rate(intel_crtc, params); | |
2740 | ||
34bb56af | 2741 | start = alloc->start; |
b9cec075 DL |
2742 | for (plane = 0; plane < intel_num_planes(intel_crtc); plane++) { |
2743 | const struct intel_plane_wm_parameters *p; | |
2cd601c6 CK |
2744 | unsigned int data_rate, y_data_rate; |
2745 | uint16_t plane_blocks, y_plane_blocks = 0; | |
b9cec075 DL |
2746 | |
2747 | p = ¶ms->plane[plane]; | |
2748 | if (!p->enabled) | |
2749 | continue; | |
2750 | ||
2cd601c6 | 2751 | data_rate = skl_plane_relative_data_rate(p, 0); |
b9cec075 DL |
2752 | |
2753 | /* | |
2cd601c6 | 2754 | * allocation for (packed formats) or (uv-plane part of planar format): |
b9cec075 DL |
2755 | * promote the expression to 64 bits to avoid overflowing, the |
2756 | * result is < available as data_rate / total_data_rate < 1 | |
2757 | */ | |
80958155 DL |
2758 | plane_blocks = minimum[plane]; |
2759 | plane_blocks += div_u64((uint64_t)alloc_size * data_rate, | |
2760 | total_data_rate); | |
b9cec075 DL |
2761 | |
2762 | ddb->plane[pipe][plane].start = start; | |
16160e3d | 2763 | ddb->plane[pipe][plane].end = start + plane_blocks; |
b9cec075 DL |
2764 | |
2765 | start += plane_blocks; | |
2cd601c6 CK |
2766 | |
2767 | /* | |
2768 | * allocation for y_plane part of planar format: | |
2769 | */ | |
2770 | if (p->y_bytes_per_pixel) { | |
2771 | y_data_rate = skl_plane_relative_data_rate(p, 1); | |
2772 | y_plane_blocks = y_minimum[plane]; | |
2773 | y_plane_blocks += div_u64((uint64_t)alloc_size * y_data_rate, | |
2774 | total_data_rate); | |
2775 | ||
2776 | ddb->y_plane[pipe][plane].start = start; | |
2777 | ddb->y_plane[pipe][plane].end = start + y_plane_blocks; | |
2778 | ||
2779 | start += y_plane_blocks; | |
2780 | } | |
2781 | ||
b9cec075 DL |
2782 | } |
2783 | ||
2784 | } | |
2785 | ||
5cec258b | 2786 | static uint32_t skl_pipe_pixel_rate(const struct intel_crtc_state *config) |
2d41c0b5 PB |
2787 | { |
2788 | /* TODO: Take into account the scalers once we support them */ | |
2d112de7 | 2789 | return config->base.adjusted_mode.crtc_clock; |
2d41c0b5 PB |
2790 | } |
2791 | ||
2792 | /* | |
2793 | * The max latency should be 257 (max the punit can code is 255 and we add 2us | |
2794 | * for the read latency) and bytes_per_pixel should always be <= 8, so that | |
2795 | * should allow pixel_rate up to ~2 GHz which seems sufficient since max | |
2796 | * 2xcdclk is 1350 MHz and the pixel rate should never exceed that. | |
2797 | */ | |
2798 | static uint32_t skl_wm_method1(uint32_t pixel_rate, uint8_t bytes_per_pixel, | |
2799 | uint32_t latency) | |
2800 | { | |
2801 | uint32_t wm_intermediate_val, ret; | |
2802 | ||
2803 | if (latency == 0) | |
2804 | return UINT_MAX; | |
2805 | ||
d4c2aa60 | 2806 | wm_intermediate_val = latency * pixel_rate * bytes_per_pixel / 512; |
2d41c0b5 PB |
2807 | ret = DIV_ROUND_UP(wm_intermediate_val, 1000); |
2808 | ||
2809 | return ret; | |
2810 | } | |
2811 | ||
2812 | static uint32_t skl_wm_method2(uint32_t pixel_rate, uint32_t pipe_htotal, | |
2813 | uint32_t horiz_pixels, uint8_t bytes_per_pixel, | |
0fda6568 | 2814 | uint64_t tiling, uint32_t latency) |
2d41c0b5 | 2815 | { |
d4c2aa60 TU |
2816 | uint32_t ret; |
2817 | uint32_t plane_bytes_per_line, plane_blocks_per_line; | |
2818 | uint32_t wm_intermediate_val; | |
2d41c0b5 PB |
2819 | |
2820 | if (latency == 0) | |
2821 | return UINT_MAX; | |
2822 | ||
2823 | plane_bytes_per_line = horiz_pixels * bytes_per_pixel; | |
0fda6568 TU |
2824 | |
2825 | if (tiling == I915_FORMAT_MOD_Y_TILED || | |
2826 | tiling == I915_FORMAT_MOD_Yf_TILED) { | |
2827 | plane_bytes_per_line *= 4; | |
2828 | plane_blocks_per_line = DIV_ROUND_UP(plane_bytes_per_line, 512); | |
2829 | plane_blocks_per_line /= 4; | |
2830 | } else { | |
2831 | plane_blocks_per_line = DIV_ROUND_UP(plane_bytes_per_line, 512); | |
2832 | } | |
2833 | ||
2d41c0b5 PB |
2834 | wm_intermediate_val = latency * pixel_rate; |
2835 | ret = DIV_ROUND_UP(wm_intermediate_val, pipe_htotal * 1000) * | |
d4c2aa60 | 2836 | plane_blocks_per_line; |
2d41c0b5 PB |
2837 | |
2838 | return ret; | |
2839 | } | |
2840 | ||
2d41c0b5 PB |
2841 | static bool skl_ddb_allocation_changed(const struct skl_ddb_allocation *new_ddb, |
2842 | const struct intel_crtc *intel_crtc) | |
2843 | { | |
2844 | struct drm_device *dev = intel_crtc->base.dev; | |
2845 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2846 | const struct skl_ddb_allocation *cur_ddb = &dev_priv->wm.skl_hw.ddb; | |
2847 | enum pipe pipe = intel_crtc->pipe; | |
2848 | ||
2849 | if (memcmp(new_ddb->plane[pipe], cur_ddb->plane[pipe], | |
2850 | sizeof(new_ddb->plane[pipe]))) | |
2851 | return true; | |
2852 | ||
2853 | if (memcmp(&new_ddb->cursor[pipe], &cur_ddb->cursor[pipe], | |
2854 | sizeof(new_ddb->cursor[pipe]))) | |
2855 | return true; | |
2856 | ||
2857 | return false; | |
2858 | } | |
2859 | ||
2860 | static void skl_compute_wm_global_parameters(struct drm_device *dev, | |
2861 | struct intel_wm_config *config) | |
2862 | { | |
2863 | struct drm_crtc *crtc; | |
2864 | struct drm_plane *plane; | |
2865 | ||
2866 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) | |
3ef00284 | 2867 | config->num_pipes_active += to_intel_crtc(crtc)->active; |
2d41c0b5 PB |
2868 | |
2869 | /* FIXME: I don't think we need those two global parameters on SKL */ | |
2870 | list_for_each_entry(plane, &dev->mode_config.plane_list, head) { | |
2871 | struct intel_plane *intel_plane = to_intel_plane(plane); | |
2872 | ||
2873 | config->sprites_enabled |= intel_plane->wm.enabled; | |
2874 | config->sprites_scaled |= intel_plane->wm.scaled; | |
2875 | } | |
2876 | } | |
2877 | ||
2878 | static void skl_compute_wm_pipe_parameters(struct drm_crtc *crtc, | |
2879 | struct skl_pipe_wm_parameters *p) | |
2880 | { | |
2881 | struct drm_device *dev = crtc->dev; | |
2882 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
2883 | enum pipe pipe = intel_crtc->pipe; | |
2884 | struct drm_plane *plane; | |
0fda6568 | 2885 | struct drm_framebuffer *fb; |
2d41c0b5 PB |
2886 | int i = 1; /* Index for sprite planes start */ |
2887 | ||
3ef00284 | 2888 | p->active = intel_crtc->active; |
2d41c0b5 | 2889 | if (p->active) { |
6e3c9717 ACO |
2890 | p->pipe_htotal = intel_crtc->config->base.adjusted_mode.crtc_htotal; |
2891 | p->pixel_rate = skl_pipe_pixel_rate(intel_crtc->config); | |
2d41c0b5 | 2892 | |
0fda6568 | 2893 | fb = crtc->primary->state->fb; |
2cd601c6 | 2894 | /* For planar: Bpp is for uv plane, y_Bpp is for y plane */ |
c9f038a1 MR |
2895 | if (fb) { |
2896 | p->plane[0].enabled = true; | |
2cd601c6 CK |
2897 | p->plane[0].bytes_per_pixel = fb->pixel_format == DRM_FORMAT_NV12 ? |
2898 | drm_format_plane_cpp(fb->pixel_format, 1) : fb->bits_per_pixel / 8; | |
2899 | p->plane[0].y_bytes_per_pixel = fb->pixel_format == DRM_FORMAT_NV12 ? | |
2900 | drm_format_plane_cpp(fb->pixel_format, 0) : 0; | |
0fda6568 | 2901 | p->plane[0].tiling = fb->modifier[0]; |
c9f038a1 MR |
2902 | } else { |
2903 | p->plane[0].enabled = false; | |
2904 | p->plane[0].bytes_per_pixel = 0; | |
2cd601c6 | 2905 | p->plane[0].y_bytes_per_pixel = 0; |
c9f038a1 MR |
2906 | p->plane[0].tiling = DRM_FORMAT_MOD_NONE; |
2907 | } | |
2908 | p->plane[0].horiz_pixels = intel_crtc->config->pipe_src_w; | |
2909 | p->plane[0].vert_pixels = intel_crtc->config->pipe_src_h; | |
1fc0a8f7 | 2910 | p->plane[0].rotation = crtc->primary->state->rotation; |
2d41c0b5 | 2911 | |
c9f038a1 | 2912 | fb = crtc->cursor->state->fb; |
2cd601c6 | 2913 | p->cursor.y_bytes_per_pixel = 0; |
c9f038a1 MR |
2914 | if (fb) { |
2915 | p->cursor.enabled = true; | |
2916 | p->cursor.bytes_per_pixel = fb->bits_per_pixel / 8; | |
2917 | p->cursor.horiz_pixels = crtc->cursor->state->crtc_w; | |
2918 | p->cursor.vert_pixels = crtc->cursor->state->crtc_h; | |
2919 | } else { | |
2920 | p->cursor.enabled = false; | |
2921 | p->cursor.bytes_per_pixel = 0; | |
2922 | p->cursor.horiz_pixels = 64; | |
2923 | p->cursor.vert_pixels = 64; | |
2924 | } | |
2d41c0b5 PB |
2925 | } |
2926 | ||
2927 | list_for_each_entry(plane, &dev->mode_config.plane_list, head) { | |
2928 | struct intel_plane *intel_plane = to_intel_plane(plane); | |
2929 | ||
a712f8eb SJ |
2930 | if (intel_plane->pipe == pipe && |
2931 | plane->type == DRM_PLANE_TYPE_OVERLAY) | |
2d41c0b5 PB |
2932 | p->plane[i++] = intel_plane->wm; |
2933 | } | |
2934 | } | |
2935 | ||
d4c2aa60 TU |
2936 | static bool skl_compute_plane_wm(const struct drm_i915_private *dev_priv, |
2937 | struct skl_pipe_wm_parameters *p, | |
afb024aa DL |
2938 | struct intel_plane_wm_parameters *p_params, |
2939 | uint16_t ddb_allocation, | |
d4c2aa60 | 2940 | int level, |
afb024aa DL |
2941 | uint16_t *out_blocks, /* out */ |
2942 | uint8_t *out_lines /* out */) | |
2d41c0b5 | 2943 | { |
d4c2aa60 TU |
2944 | uint32_t latency = dev_priv->wm.skl_latency[level]; |
2945 | uint32_t method1, method2; | |
2946 | uint32_t plane_bytes_per_line, plane_blocks_per_line; | |
2947 | uint32_t res_blocks, res_lines; | |
2948 | uint32_t selected_result; | |
2cd601c6 | 2949 | uint8_t bytes_per_pixel; |
2d41c0b5 | 2950 | |
d4c2aa60 | 2951 | if (latency == 0 || !p->active || !p_params->enabled) |
2d41c0b5 PB |
2952 | return false; |
2953 | ||
2cd601c6 CK |
2954 | bytes_per_pixel = p_params->y_bytes_per_pixel ? |
2955 | p_params->y_bytes_per_pixel : | |
2956 | p_params->bytes_per_pixel; | |
2d41c0b5 | 2957 | method1 = skl_wm_method1(p->pixel_rate, |
2cd601c6 | 2958 | bytes_per_pixel, |
d4c2aa60 | 2959 | latency); |
2d41c0b5 PB |
2960 | method2 = skl_wm_method2(p->pixel_rate, |
2961 | p->pipe_htotal, | |
2962 | p_params->horiz_pixels, | |
2cd601c6 | 2963 | bytes_per_pixel, |
0fda6568 | 2964 | p_params->tiling, |
d4c2aa60 | 2965 | latency); |
2d41c0b5 | 2966 | |
2cd601c6 | 2967 | plane_bytes_per_line = p_params->horiz_pixels * bytes_per_pixel; |
d4c2aa60 | 2968 | plane_blocks_per_line = DIV_ROUND_UP(plane_bytes_per_line, 512); |
2d41c0b5 | 2969 | |
0fda6568 TU |
2970 | if (p_params->tiling == I915_FORMAT_MOD_Y_TILED || |
2971 | p_params->tiling == I915_FORMAT_MOD_Yf_TILED) { | |
1fc0a8f7 TU |
2972 | uint32_t min_scanlines = 4; |
2973 | uint32_t y_tile_minimum; | |
2974 | if (intel_rotation_90_or_270(p_params->rotation)) { | |
2975 | switch (p_params->bytes_per_pixel) { | |
2976 | case 1: | |
2977 | min_scanlines = 16; | |
2978 | break; | |
2979 | case 2: | |
2980 | min_scanlines = 8; | |
2981 | break; | |
2982 | case 8: | |
2983 | WARN(1, "Unsupported pixel depth for rotation"); | |
2f0b5790 | 2984 | } |
1fc0a8f7 TU |
2985 | } |
2986 | y_tile_minimum = plane_blocks_per_line * min_scanlines; | |
0fda6568 TU |
2987 | selected_result = max(method2, y_tile_minimum); |
2988 | } else { | |
2989 | if ((ddb_allocation / plane_blocks_per_line) >= 1) | |
2990 | selected_result = min(method1, method2); | |
2991 | else | |
2992 | selected_result = method1; | |
2993 | } | |
2d41c0b5 | 2994 | |
d4c2aa60 TU |
2995 | res_blocks = selected_result + 1; |
2996 | res_lines = DIV_ROUND_UP(selected_result, plane_blocks_per_line); | |
e6d66171 | 2997 | |
0fda6568 TU |
2998 | if (level >= 1 && level <= 7) { |
2999 | if (p_params->tiling == I915_FORMAT_MOD_Y_TILED || | |
3000 | p_params->tiling == I915_FORMAT_MOD_Yf_TILED) | |
3001 | res_lines += 4; | |
3002 | else | |
3003 | res_blocks++; | |
3004 | } | |
e6d66171 | 3005 | |
d4c2aa60 | 3006 | if (res_blocks >= ddb_allocation || res_lines > 31) |
e6d66171 DL |
3007 | return false; |
3008 | ||
3009 | *out_blocks = res_blocks; | |
3010 | *out_lines = res_lines; | |
2d41c0b5 PB |
3011 | |
3012 | return true; | |
3013 | } | |
3014 | ||
3015 | static void skl_compute_wm_level(const struct drm_i915_private *dev_priv, | |
3016 | struct skl_ddb_allocation *ddb, | |
3017 | struct skl_pipe_wm_parameters *p, | |
3018 | enum pipe pipe, | |
3019 | int level, | |
3020 | int num_planes, | |
3021 | struct skl_wm_level *result) | |
3022 | { | |
2d41c0b5 PB |
3023 | uint16_t ddb_blocks; |
3024 | int i; | |
3025 | ||
3026 | for (i = 0; i < num_planes; i++) { | |
3027 | ddb_blocks = skl_ddb_entry_size(&ddb->plane[pipe][i]); | |
3028 | ||
d4c2aa60 TU |
3029 | result->plane_en[i] = skl_compute_plane_wm(dev_priv, |
3030 | p, &p->plane[i], | |
2d41c0b5 | 3031 | ddb_blocks, |
d4c2aa60 | 3032 | level, |
2d41c0b5 PB |
3033 | &result->plane_res_b[i], |
3034 | &result->plane_res_l[i]); | |
3035 | } | |
3036 | ||
3037 | ddb_blocks = skl_ddb_entry_size(&ddb->cursor[pipe]); | |
d4c2aa60 TU |
3038 | result->cursor_en = skl_compute_plane_wm(dev_priv, p, &p->cursor, |
3039 | ddb_blocks, level, | |
3040 | &result->cursor_res_b, | |
2d41c0b5 PB |
3041 | &result->cursor_res_l); |
3042 | } | |
3043 | ||
407b50f3 DL |
3044 | static uint32_t |
3045 | skl_compute_linetime_wm(struct drm_crtc *crtc, struct skl_pipe_wm_parameters *p) | |
3046 | { | |
3ef00284 | 3047 | if (!to_intel_crtc(crtc)->active) |
407b50f3 DL |
3048 | return 0; |
3049 | ||
3050 | return DIV_ROUND_UP(8 * p->pipe_htotal * 1000, p->pixel_rate); | |
3051 | ||
3052 | } | |
3053 | ||
3054 | static void skl_compute_transition_wm(struct drm_crtc *crtc, | |
3055 | struct skl_pipe_wm_parameters *params, | |
9414f563 | 3056 | struct skl_wm_level *trans_wm /* out */) |
407b50f3 | 3057 | { |
9414f563 DL |
3058 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
3059 | int i; | |
3060 | ||
407b50f3 DL |
3061 | if (!params->active) |
3062 | return; | |
9414f563 DL |
3063 | |
3064 | /* Until we know more, just disable transition WMs */ | |
3065 | for (i = 0; i < intel_num_planes(intel_crtc); i++) | |
3066 | trans_wm->plane_en[i] = false; | |
3067 | trans_wm->cursor_en = false; | |
407b50f3 DL |
3068 | } |
3069 | ||
2d41c0b5 PB |
3070 | static void skl_compute_pipe_wm(struct drm_crtc *crtc, |
3071 | struct skl_ddb_allocation *ddb, | |
3072 | struct skl_pipe_wm_parameters *params, | |
3073 | struct skl_pipe_wm *pipe_wm) | |
3074 | { | |
3075 | struct drm_device *dev = crtc->dev; | |
3076 | const struct drm_i915_private *dev_priv = dev->dev_private; | |
3077 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
3078 | int level, max_level = ilk_wm_max_level(dev); | |
3079 | ||
3080 | for (level = 0; level <= max_level; level++) { | |
3081 | skl_compute_wm_level(dev_priv, ddb, params, intel_crtc->pipe, | |
3082 | level, intel_num_planes(intel_crtc), | |
3083 | &pipe_wm->wm[level]); | |
3084 | } | |
3085 | pipe_wm->linetime = skl_compute_linetime_wm(crtc, params); | |
3086 | ||
9414f563 | 3087 | skl_compute_transition_wm(crtc, params, &pipe_wm->trans_wm); |
2d41c0b5 PB |
3088 | } |
3089 | ||
3090 | static void skl_compute_wm_results(struct drm_device *dev, | |
3091 | struct skl_pipe_wm_parameters *p, | |
3092 | struct skl_pipe_wm *p_wm, | |
3093 | struct skl_wm_values *r, | |
3094 | struct intel_crtc *intel_crtc) | |
3095 | { | |
3096 | int level, max_level = ilk_wm_max_level(dev); | |
3097 | enum pipe pipe = intel_crtc->pipe; | |
9414f563 DL |
3098 | uint32_t temp; |
3099 | int i; | |
2d41c0b5 PB |
3100 | |
3101 | for (level = 0; level <= max_level; level++) { | |
2d41c0b5 PB |
3102 | for (i = 0; i < intel_num_planes(intel_crtc); i++) { |
3103 | temp = 0; | |
2d41c0b5 PB |
3104 | |
3105 | temp |= p_wm->wm[level].plane_res_l[i] << | |
3106 | PLANE_WM_LINES_SHIFT; | |
3107 | temp |= p_wm->wm[level].plane_res_b[i]; | |
3108 | if (p_wm->wm[level].plane_en[i]) | |
3109 | temp |= PLANE_WM_EN; | |
3110 | ||
3111 | r->plane[pipe][i][level] = temp; | |
2d41c0b5 PB |
3112 | } |
3113 | ||
3114 | temp = 0; | |
2d41c0b5 PB |
3115 | |
3116 | temp |= p_wm->wm[level].cursor_res_l << PLANE_WM_LINES_SHIFT; | |
3117 | temp |= p_wm->wm[level].cursor_res_b; | |
3118 | ||
3119 | if (p_wm->wm[level].cursor_en) | |
3120 | temp |= PLANE_WM_EN; | |
3121 | ||
3122 | r->cursor[pipe][level] = temp; | |
2d41c0b5 PB |
3123 | |
3124 | } | |
3125 | ||
9414f563 DL |
3126 | /* transition WMs */ |
3127 | for (i = 0; i < intel_num_planes(intel_crtc); i++) { | |
3128 | temp = 0; | |
3129 | temp |= p_wm->trans_wm.plane_res_l[i] << PLANE_WM_LINES_SHIFT; | |
3130 | temp |= p_wm->trans_wm.plane_res_b[i]; | |
3131 | if (p_wm->trans_wm.plane_en[i]) | |
3132 | temp |= PLANE_WM_EN; | |
3133 | ||
3134 | r->plane_trans[pipe][i] = temp; | |
3135 | } | |
3136 | ||
3137 | temp = 0; | |
3138 | temp |= p_wm->trans_wm.cursor_res_l << PLANE_WM_LINES_SHIFT; | |
3139 | temp |= p_wm->trans_wm.cursor_res_b; | |
3140 | if (p_wm->trans_wm.cursor_en) | |
3141 | temp |= PLANE_WM_EN; | |
3142 | ||
3143 | r->cursor_trans[pipe] = temp; | |
3144 | ||
2d41c0b5 PB |
3145 | r->wm_linetime[pipe] = p_wm->linetime; |
3146 | } | |
3147 | ||
16160e3d DL |
3148 | static void skl_ddb_entry_write(struct drm_i915_private *dev_priv, uint32_t reg, |
3149 | const struct skl_ddb_entry *entry) | |
3150 | { | |
3151 | if (entry->end) | |
3152 | I915_WRITE(reg, (entry->end - 1) << 16 | entry->start); | |
3153 | else | |
3154 | I915_WRITE(reg, 0); | |
3155 | } | |
3156 | ||
2d41c0b5 PB |
3157 | static void skl_write_wm_values(struct drm_i915_private *dev_priv, |
3158 | const struct skl_wm_values *new) | |
3159 | { | |
3160 | struct drm_device *dev = dev_priv->dev; | |
3161 | struct intel_crtc *crtc; | |
3162 | ||
3163 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) { | |
3164 | int i, level, max_level = ilk_wm_max_level(dev); | |
3165 | enum pipe pipe = crtc->pipe; | |
3166 | ||
5d374d96 DL |
3167 | if (!new->dirty[pipe]) |
3168 | continue; | |
8211bd5b | 3169 | |
5d374d96 | 3170 | I915_WRITE(PIPE_WM_LINETIME(pipe), new->wm_linetime[pipe]); |
8211bd5b | 3171 | |
5d374d96 DL |
3172 | for (level = 0; level <= max_level; level++) { |
3173 | for (i = 0; i < intel_num_planes(crtc); i++) | |
3174 | I915_WRITE(PLANE_WM(pipe, i, level), | |
3175 | new->plane[pipe][i][level]); | |
3176 | I915_WRITE(CUR_WM(pipe, level), | |
3177 | new->cursor[pipe][level]); | |
2d41c0b5 | 3178 | } |
5d374d96 DL |
3179 | for (i = 0; i < intel_num_planes(crtc); i++) |
3180 | I915_WRITE(PLANE_WM_TRANS(pipe, i), | |
3181 | new->plane_trans[pipe][i]); | |
3182 | I915_WRITE(CUR_WM_TRANS(pipe), new->cursor_trans[pipe]); | |
3183 | ||
2cd601c6 | 3184 | for (i = 0; i < intel_num_planes(crtc); i++) { |
5d374d96 DL |
3185 | skl_ddb_entry_write(dev_priv, |
3186 | PLANE_BUF_CFG(pipe, i), | |
3187 | &new->ddb.plane[pipe][i]); | |
2cd601c6 CK |
3188 | skl_ddb_entry_write(dev_priv, |
3189 | PLANE_NV12_BUF_CFG(pipe, i), | |
3190 | &new->ddb.y_plane[pipe][i]); | |
3191 | } | |
5d374d96 DL |
3192 | |
3193 | skl_ddb_entry_write(dev_priv, CUR_BUF_CFG(pipe), | |
3194 | &new->ddb.cursor[pipe]); | |
2d41c0b5 | 3195 | } |
2d41c0b5 PB |
3196 | } |
3197 | ||
0e8fb7ba DL |
3198 | /* |
3199 | * When setting up a new DDB allocation arrangement, we need to correctly | |
3200 | * sequence the times at which the new allocations for the pipes are taken into | |
3201 | * account or we'll have pipes fetching from space previously allocated to | |
3202 | * another pipe. | |
3203 | * | |
3204 | * Roughly the sequence looks like: | |
3205 | * 1. re-allocate the pipe(s) with the allocation being reduced and not | |
3206 | * overlapping with a previous light-up pipe (another way to put it is: | |
3207 | * pipes with their new allocation strickly included into their old ones). | |
3208 | * 2. re-allocate the other pipes that get their allocation reduced | |
3209 | * 3. allocate the pipes having their allocation increased | |
3210 | * | |
3211 | * Steps 1. and 2. are here to take care of the following case: | |
3212 | * - Initially DDB looks like this: | |
3213 | * | B | C | | |
3214 | * - enable pipe A. | |
3215 | * - pipe B has a reduced DDB allocation that overlaps with the old pipe C | |
3216 | * allocation | |
3217 | * | A | B | C | | |
3218 | * | |
3219 | * We need to sequence the re-allocation: C, B, A (and not B, C, A). | |
3220 | */ | |
3221 | ||
d21b795c DL |
3222 | static void |
3223 | skl_wm_flush_pipe(struct drm_i915_private *dev_priv, enum pipe pipe, int pass) | |
0e8fb7ba | 3224 | { |
0e8fb7ba DL |
3225 | int plane; |
3226 | ||
d21b795c DL |
3227 | DRM_DEBUG_KMS("flush pipe %c (pass %d)\n", pipe_name(pipe), pass); |
3228 | ||
dd740780 | 3229 | for_each_plane(dev_priv, pipe, plane) { |
0e8fb7ba DL |
3230 | I915_WRITE(PLANE_SURF(pipe, plane), |
3231 | I915_READ(PLANE_SURF(pipe, plane))); | |
3232 | } | |
3233 | I915_WRITE(CURBASE(pipe), I915_READ(CURBASE(pipe))); | |
3234 | } | |
3235 | ||
3236 | static bool | |
3237 | skl_ddb_allocation_included(const struct skl_ddb_allocation *old, | |
3238 | const struct skl_ddb_allocation *new, | |
3239 | enum pipe pipe) | |
3240 | { | |
3241 | uint16_t old_size, new_size; | |
3242 | ||
3243 | old_size = skl_ddb_entry_size(&old->pipe[pipe]); | |
3244 | new_size = skl_ddb_entry_size(&new->pipe[pipe]); | |
3245 | ||
3246 | return old_size != new_size && | |
3247 | new->pipe[pipe].start >= old->pipe[pipe].start && | |
3248 | new->pipe[pipe].end <= old->pipe[pipe].end; | |
3249 | } | |
3250 | ||
3251 | static void skl_flush_wm_values(struct drm_i915_private *dev_priv, | |
3252 | struct skl_wm_values *new_values) | |
3253 | { | |
3254 | struct drm_device *dev = dev_priv->dev; | |
3255 | struct skl_ddb_allocation *cur_ddb, *new_ddb; | |
c929cb45 | 3256 | bool reallocated[I915_MAX_PIPES] = {}; |
0e8fb7ba DL |
3257 | struct intel_crtc *crtc; |
3258 | enum pipe pipe; | |
3259 | ||
3260 | new_ddb = &new_values->ddb; | |
3261 | cur_ddb = &dev_priv->wm.skl_hw.ddb; | |
3262 | ||
3263 | /* | |
3264 | * First pass: flush the pipes with the new allocation contained into | |
3265 | * the old space. | |
3266 | * | |
3267 | * We'll wait for the vblank on those pipes to ensure we can safely | |
3268 | * re-allocate the freed space without this pipe fetching from it. | |
3269 | */ | |
3270 | for_each_intel_crtc(dev, crtc) { | |
3271 | if (!crtc->active) | |
3272 | continue; | |
3273 | ||
3274 | pipe = crtc->pipe; | |
3275 | ||
3276 | if (!skl_ddb_allocation_included(cur_ddb, new_ddb, pipe)) | |
3277 | continue; | |
3278 | ||
d21b795c | 3279 | skl_wm_flush_pipe(dev_priv, pipe, 1); |
0e8fb7ba DL |
3280 | intel_wait_for_vblank(dev, pipe); |
3281 | ||
3282 | reallocated[pipe] = true; | |
3283 | } | |
3284 | ||
3285 | ||
3286 | /* | |
3287 | * Second pass: flush the pipes that are having their allocation | |
3288 | * reduced, but overlapping with a previous allocation. | |
3289 | * | |
3290 | * Here as well we need to wait for the vblank to make sure the freed | |
3291 | * space is not used anymore. | |
3292 | */ | |
3293 | for_each_intel_crtc(dev, crtc) { | |
3294 | if (!crtc->active) | |
3295 | continue; | |
3296 | ||
3297 | pipe = crtc->pipe; | |
3298 | ||
3299 | if (reallocated[pipe]) | |
3300 | continue; | |
3301 | ||
3302 | if (skl_ddb_entry_size(&new_ddb->pipe[pipe]) < | |
3303 | skl_ddb_entry_size(&cur_ddb->pipe[pipe])) { | |
d21b795c | 3304 | skl_wm_flush_pipe(dev_priv, pipe, 2); |
0e8fb7ba | 3305 | intel_wait_for_vblank(dev, pipe); |
d9d8e6b3 | 3306 | reallocated[pipe] = true; |
0e8fb7ba | 3307 | } |
0e8fb7ba DL |
3308 | } |
3309 | ||
3310 | /* | |
3311 | * Third pass: flush the pipes that got more space allocated. | |
3312 | * | |
3313 | * We don't need to actively wait for the update here, next vblank | |
3314 | * will just get more DDB space with the correct WM values. | |
3315 | */ | |
3316 | for_each_intel_crtc(dev, crtc) { | |
3317 | if (!crtc->active) | |
3318 | continue; | |
3319 | ||
3320 | pipe = crtc->pipe; | |
3321 | ||
3322 | /* | |
3323 | * At this point, only the pipes more space than before are | |
3324 | * left to re-allocate. | |
3325 | */ | |
3326 | if (reallocated[pipe]) | |
3327 | continue; | |
3328 | ||
d21b795c | 3329 | skl_wm_flush_pipe(dev_priv, pipe, 3); |
0e8fb7ba DL |
3330 | } |
3331 | } | |
3332 | ||
2d41c0b5 PB |
3333 | static bool skl_update_pipe_wm(struct drm_crtc *crtc, |
3334 | struct skl_pipe_wm_parameters *params, | |
3335 | struct intel_wm_config *config, | |
3336 | struct skl_ddb_allocation *ddb, /* out */ | |
3337 | struct skl_pipe_wm *pipe_wm /* out */) | |
3338 | { | |
3339 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
3340 | ||
3341 | skl_compute_wm_pipe_parameters(crtc, params); | |
b9cec075 | 3342 | skl_allocate_pipe_ddb(crtc, config, params, ddb); |
2d41c0b5 PB |
3343 | skl_compute_pipe_wm(crtc, ddb, params, pipe_wm); |
3344 | ||
3345 | if (!memcmp(&intel_crtc->wm.skl_active, pipe_wm, sizeof(*pipe_wm))) | |
3346 | return false; | |
3347 | ||
3348 | intel_crtc->wm.skl_active = *pipe_wm; | |
2cd601c6 | 3349 | |
2d41c0b5 PB |
3350 | return true; |
3351 | } | |
3352 | ||
3353 | static void skl_update_other_pipe_wm(struct drm_device *dev, | |
3354 | struct drm_crtc *crtc, | |
3355 | struct intel_wm_config *config, | |
3356 | struct skl_wm_values *r) | |
3357 | { | |
3358 | struct intel_crtc *intel_crtc; | |
3359 | struct intel_crtc *this_crtc = to_intel_crtc(crtc); | |
3360 | ||
3361 | /* | |
3362 | * If the WM update hasn't changed the allocation for this_crtc (the | |
3363 | * crtc we are currently computing the new WM values for), other | |
3364 | * enabled crtcs will keep the same allocation and we don't need to | |
3365 | * recompute anything for them. | |
3366 | */ | |
3367 | if (!skl_ddb_allocation_changed(&r->ddb, this_crtc)) | |
3368 | return; | |
3369 | ||
3370 | /* | |
3371 | * Otherwise, because of this_crtc being freshly enabled/disabled, the | |
3372 | * other active pipes need new DDB allocation and WM values. | |
3373 | */ | |
3374 | list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list, | |
3375 | base.head) { | |
3376 | struct skl_pipe_wm_parameters params = {}; | |
3377 | struct skl_pipe_wm pipe_wm = {}; | |
3378 | bool wm_changed; | |
3379 | ||
3380 | if (this_crtc->pipe == intel_crtc->pipe) | |
3381 | continue; | |
3382 | ||
3383 | if (!intel_crtc->active) | |
3384 | continue; | |
3385 | ||
3386 | wm_changed = skl_update_pipe_wm(&intel_crtc->base, | |
3387 | ¶ms, config, | |
3388 | &r->ddb, &pipe_wm); | |
3389 | ||
3390 | /* | |
3391 | * If we end up re-computing the other pipe WM values, it's | |
3392 | * because it was really needed, so we expect the WM values to | |
3393 | * be different. | |
3394 | */ | |
3395 | WARN_ON(!wm_changed); | |
3396 | ||
3397 | skl_compute_wm_results(dev, ¶ms, &pipe_wm, r, intel_crtc); | |
3398 | r->dirty[intel_crtc->pipe] = true; | |
3399 | } | |
3400 | } | |
3401 | ||
3402 | static void skl_update_wm(struct drm_crtc *crtc) | |
3403 | { | |
3404 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
3405 | struct drm_device *dev = crtc->dev; | |
3406 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3407 | struct skl_pipe_wm_parameters params = {}; | |
3408 | struct skl_wm_values *results = &dev_priv->wm.skl_results; | |
3409 | struct skl_pipe_wm pipe_wm = {}; | |
3410 | struct intel_wm_config config = {}; | |
3411 | ||
3412 | memset(results, 0, sizeof(*results)); | |
3413 | ||
3414 | skl_compute_wm_global_parameters(dev, &config); | |
3415 | ||
3416 | if (!skl_update_pipe_wm(crtc, ¶ms, &config, | |
3417 | &results->ddb, &pipe_wm)) | |
3418 | return; | |
3419 | ||
3420 | skl_compute_wm_results(dev, ¶ms, &pipe_wm, results, intel_crtc); | |
3421 | results->dirty[intel_crtc->pipe] = true; | |
3422 | ||
3423 | skl_update_other_pipe_wm(dev, crtc, &config, results); | |
3424 | skl_write_wm_values(dev_priv, results); | |
0e8fb7ba | 3425 | skl_flush_wm_values(dev_priv, results); |
53b0deb4 DL |
3426 | |
3427 | /* store the new configuration */ | |
3428 | dev_priv->wm.skl_hw = *results; | |
2d41c0b5 PB |
3429 | } |
3430 | ||
3431 | static void | |
3432 | skl_update_sprite_wm(struct drm_plane *plane, struct drm_crtc *crtc, | |
3433 | uint32_t sprite_width, uint32_t sprite_height, | |
3434 | int pixel_size, bool enabled, bool scaled) | |
3435 | { | |
3436 | struct intel_plane *intel_plane = to_intel_plane(plane); | |
0fda6568 | 3437 | struct drm_framebuffer *fb = plane->state->fb; |
2d41c0b5 PB |
3438 | |
3439 | intel_plane->wm.enabled = enabled; | |
3440 | intel_plane->wm.scaled = scaled; | |
3441 | intel_plane->wm.horiz_pixels = sprite_width; | |
3442 | intel_plane->wm.vert_pixels = sprite_height; | |
0fda6568 | 3443 | intel_plane->wm.tiling = DRM_FORMAT_MOD_NONE; |
2cd601c6 CK |
3444 | |
3445 | /* For planar: Bpp is for UV plane, y_Bpp is for Y plane */ | |
3446 | intel_plane->wm.bytes_per_pixel = | |
3447 | (fb && fb->pixel_format == DRM_FORMAT_NV12) ? | |
3448 | drm_format_plane_cpp(plane->state->fb->pixel_format, 1) : pixel_size; | |
3449 | intel_plane->wm.y_bytes_per_pixel = | |
3450 | (fb && fb->pixel_format == DRM_FORMAT_NV12) ? | |
3451 | drm_format_plane_cpp(plane->state->fb->pixel_format, 0) : 0; | |
3452 | ||
0fda6568 TU |
3453 | /* |
3454 | * Framebuffer can be NULL on plane disable, but it does not | |
3455 | * matter for watermarks if we assume no tiling in that case. | |
3456 | */ | |
3457 | if (fb) | |
3458 | intel_plane->wm.tiling = fb->modifier[0]; | |
1fc0a8f7 | 3459 | intel_plane->wm.rotation = plane->state->rotation; |
2d41c0b5 PB |
3460 | |
3461 | skl_update_wm(crtc); | |
3462 | } | |
3463 | ||
820c1980 | 3464 | static void ilk_update_wm(struct drm_crtc *crtc) |
801bcfff | 3465 | { |
7c4a395f | 3466 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
46ba614c | 3467 | struct drm_device *dev = crtc->dev; |
801bcfff | 3468 | struct drm_i915_private *dev_priv = dev->dev_private; |
820c1980 ID |
3469 | struct ilk_wm_maximums max; |
3470 | struct ilk_pipe_wm_parameters params = {}; | |
3471 | struct ilk_wm_values results = {}; | |
77c122bc | 3472 | enum intel_ddb_partitioning partitioning; |
7c4a395f | 3473 | struct intel_pipe_wm pipe_wm = {}; |
198a1e9b | 3474 | struct intel_pipe_wm lp_wm_1_2 = {}, lp_wm_5_6 = {}, *best_lp_wm; |
a485bfb8 | 3475 | struct intel_wm_config config = {}; |
7c4a395f | 3476 | |
2a44b76b | 3477 | ilk_compute_wm_parameters(crtc, ¶ms); |
7c4a395f VS |
3478 | |
3479 | intel_compute_pipe_wm(crtc, ¶ms, &pipe_wm); | |
3480 | ||
3481 | if (!memcmp(&intel_crtc->wm.active, &pipe_wm, sizeof(pipe_wm))) | |
3482 | return; | |
861f3389 | 3483 | |
7c4a395f | 3484 | intel_crtc->wm.active = pipe_wm; |
861f3389 | 3485 | |
2a44b76b VS |
3486 | ilk_compute_wm_config(dev, &config); |
3487 | ||
34982fe1 | 3488 | ilk_compute_wm_maximums(dev, 1, &config, INTEL_DDB_PART_1_2, &max); |
0ba22e26 | 3489 | ilk_wm_merge(dev, &config, &max, &lp_wm_1_2); |
a485bfb8 VS |
3490 | |
3491 | /* 5/6 split only in single pipe config on IVB+ */ | |
ec98c8d1 VS |
3492 | if (INTEL_INFO(dev)->gen >= 7 && |
3493 | config.num_pipes_active == 1 && config.sprites_enabled) { | |
34982fe1 | 3494 | ilk_compute_wm_maximums(dev, 1, &config, INTEL_DDB_PART_5_6, &max); |
0ba22e26 | 3495 | ilk_wm_merge(dev, &config, &max, &lp_wm_5_6); |
0362c781 | 3496 | |
820c1980 | 3497 | best_lp_wm = ilk_find_best_result(dev, &lp_wm_1_2, &lp_wm_5_6); |
861f3389 | 3498 | } else { |
198a1e9b | 3499 | best_lp_wm = &lp_wm_1_2; |
861f3389 PZ |
3500 | } |
3501 | ||
198a1e9b | 3502 | partitioning = (best_lp_wm == &lp_wm_1_2) ? |
77c122bc | 3503 | INTEL_DDB_PART_1_2 : INTEL_DDB_PART_5_6; |
801bcfff | 3504 | |
820c1980 | 3505 | ilk_compute_wm_results(dev, best_lp_wm, partitioning, &results); |
609cedef | 3506 | |
820c1980 | 3507 | ilk_write_wm_values(dev_priv, &results); |
1011d8c4 PZ |
3508 | } |
3509 | ||
ed57cb8a DL |
3510 | static void |
3511 | ilk_update_sprite_wm(struct drm_plane *plane, | |
3512 | struct drm_crtc *crtc, | |
3513 | uint32_t sprite_width, uint32_t sprite_height, | |
3514 | int pixel_size, bool enabled, bool scaled) | |
526682e9 | 3515 | { |
8553c18e | 3516 | struct drm_device *dev = plane->dev; |
adf3d35e | 3517 | struct intel_plane *intel_plane = to_intel_plane(plane); |
526682e9 | 3518 | |
adf3d35e VS |
3519 | intel_plane->wm.enabled = enabled; |
3520 | intel_plane->wm.scaled = scaled; | |
3521 | intel_plane->wm.horiz_pixels = sprite_width; | |
ed57cb8a | 3522 | intel_plane->wm.vert_pixels = sprite_width; |
adf3d35e | 3523 | intel_plane->wm.bytes_per_pixel = pixel_size; |
526682e9 | 3524 | |
8553c18e VS |
3525 | /* |
3526 | * IVB workaround: must disable low power watermarks for at least | |
3527 | * one frame before enabling scaling. LP watermarks can be re-enabled | |
3528 | * when scaling is disabled. | |
3529 | * | |
3530 | * WaCxSRDisabledForSpriteScaling:ivb | |
3531 | */ | |
3532 | if (IS_IVYBRIDGE(dev) && scaled && ilk_disable_lp_wm(dev)) | |
3533 | intel_wait_for_vblank(dev, intel_plane->pipe); | |
3534 | ||
820c1980 | 3535 | ilk_update_wm(crtc); |
526682e9 PZ |
3536 | } |
3537 | ||
3078999f PB |
3538 | static void skl_pipe_wm_active_state(uint32_t val, |
3539 | struct skl_pipe_wm *active, | |
3540 | bool is_transwm, | |
3541 | bool is_cursor, | |
3542 | int i, | |
3543 | int level) | |
3544 | { | |
3545 | bool is_enabled = (val & PLANE_WM_EN) != 0; | |
3546 | ||
3547 | if (!is_transwm) { | |
3548 | if (!is_cursor) { | |
3549 | active->wm[level].plane_en[i] = is_enabled; | |
3550 | active->wm[level].plane_res_b[i] = | |
3551 | val & PLANE_WM_BLOCKS_MASK; | |
3552 | active->wm[level].plane_res_l[i] = | |
3553 | (val >> PLANE_WM_LINES_SHIFT) & | |
3554 | PLANE_WM_LINES_MASK; | |
3555 | } else { | |
3556 | active->wm[level].cursor_en = is_enabled; | |
3557 | active->wm[level].cursor_res_b = | |
3558 | val & PLANE_WM_BLOCKS_MASK; | |
3559 | active->wm[level].cursor_res_l = | |
3560 | (val >> PLANE_WM_LINES_SHIFT) & | |
3561 | PLANE_WM_LINES_MASK; | |
3562 | } | |
3563 | } else { | |
3564 | if (!is_cursor) { | |
3565 | active->trans_wm.plane_en[i] = is_enabled; | |
3566 | active->trans_wm.plane_res_b[i] = | |
3567 | val & PLANE_WM_BLOCKS_MASK; | |
3568 | active->trans_wm.plane_res_l[i] = | |
3569 | (val >> PLANE_WM_LINES_SHIFT) & | |
3570 | PLANE_WM_LINES_MASK; | |
3571 | } else { | |
3572 | active->trans_wm.cursor_en = is_enabled; | |
3573 | active->trans_wm.cursor_res_b = | |
3574 | val & PLANE_WM_BLOCKS_MASK; | |
3575 | active->trans_wm.cursor_res_l = | |
3576 | (val >> PLANE_WM_LINES_SHIFT) & | |
3577 | PLANE_WM_LINES_MASK; | |
3578 | } | |
3579 | } | |
3580 | } | |
3581 | ||
3582 | static void skl_pipe_wm_get_hw_state(struct drm_crtc *crtc) | |
3583 | { | |
3584 | struct drm_device *dev = crtc->dev; | |
3585 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3586 | struct skl_wm_values *hw = &dev_priv->wm.skl_hw; | |
3587 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
3588 | struct skl_pipe_wm *active = &intel_crtc->wm.skl_active; | |
3589 | enum pipe pipe = intel_crtc->pipe; | |
3590 | int level, i, max_level; | |
3591 | uint32_t temp; | |
3592 | ||
3593 | max_level = ilk_wm_max_level(dev); | |
3594 | ||
3595 | hw->wm_linetime[pipe] = I915_READ(PIPE_WM_LINETIME(pipe)); | |
3596 | ||
3597 | for (level = 0; level <= max_level; level++) { | |
3598 | for (i = 0; i < intel_num_planes(intel_crtc); i++) | |
3599 | hw->plane[pipe][i][level] = | |
3600 | I915_READ(PLANE_WM(pipe, i, level)); | |
3601 | hw->cursor[pipe][level] = I915_READ(CUR_WM(pipe, level)); | |
3602 | } | |
3603 | ||
3604 | for (i = 0; i < intel_num_planes(intel_crtc); i++) | |
3605 | hw->plane_trans[pipe][i] = I915_READ(PLANE_WM_TRANS(pipe, i)); | |
3606 | hw->cursor_trans[pipe] = I915_READ(CUR_WM_TRANS(pipe)); | |
3607 | ||
3ef00284 | 3608 | if (!intel_crtc->active) |
3078999f PB |
3609 | return; |
3610 | ||
3611 | hw->dirty[pipe] = true; | |
3612 | ||
3613 | active->linetime = hw->wm_linetime[pipe]; | |
3614 | ||
3615 | for (level = 0; level <= max_level; level++) { | |
3616 | for (i = 0; i < intel_num_planes(intel_crtc); i++) { | |
3617 | temp = hw->plane[pipe][i][level]; | |
3618 | skl_pipe_wm_active_state(temp, active, false, | |
3619 | false, i, level); | |
3620 | } | |
3621 | temp = hw->cursor[pipe][level]; | |
3622 | skl_pipe_wm_active_state(temp, active, false, true, i, level); | |
3623 | } | |
3624 | ||
3625 | for (i = 0; i < intel_num_planes(intel_crtc); i++) { | |
3626 | temp = hw->plane_trans[pipe][i]; | |
3627 | skl_pipe_wm_active_state(temp, active, true, false, i, 0); | |
3628 | } | |
3629 | ||
3630 | temp = hw->cursor_trans[pipe]; | |
3631 | skl_pipe_wm_active_state(temp, active, true, true, i, 0); | |
3632 | } | |
3633 | ||
3634 | void skl_wm_get_hw_state(struct drm_device *dev) | |
3635 | { | |
a269c583 DL |
3636 | struct drm_i915_private *dev_priv = dev->dev_private; |
3637 | struct skl_ddb_allocation *ddb = &dev_priv->wm.skl_hw.ddb; | |
3078999f PB |
3638 | struct drm_crtc *crtc; |
3639 | ||
a269c583 | 3640 | skl_ddb_get_hw_state(dev_priv, ddb); |
3078999f PB |
3641 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) |
3642 | skl_pipe_wm_get_hw_state(crtc); | |
3643 | } | |
3644 | ||
243e6a44 VS |
3645 | static void ilk_pipe_wm_get_hw_state(struct drm_crtc *crtc) |
3646 | { | |
3647 | struct drm_device *dev = crtc->dev; | |
3648 | struct drm_i915_private *dev_priv = dev->dev_private; | |
820c1980 | 3649 | struct ilk_wm_values *hw = &dev_priv->wm.hw; |
243e6a44 VS |
3650 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
3651 | struct intel_pipe_wm *active = &intel_crtc->wm.active; | |
3652 | enum pipe pipe = intel_crtc->pipe; | |
3653 | static const unsigned int wm0_pipe_reg[] = { | |
3654 | [PIPE_A] = WM0_PIPEA_ILK, | |
3655 | [PIPE_B] = WM0_PIPEB_ILK, | |
3656 | [PIPE_C] = WM0_PIPEC_IVB, | |
3657 | }; | |
3658 | ||
3659 | hw->wm_pipe[pipe] = I915_READ(wm0_pipe_reg[pipe]); | |
a42a5719 | 3660 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) |
ce0e0713 | 3661 | hw->wm_linetime[pipe] = I915_READ(PIPE_WM_LINETIME(pipe)); |
243e6a44 | 3662 | |
3ef00284 | 3663 | active->pipe_enabled = intel_crtc->active; |
2a44b76b VS |
3664 | |
3665 | if (active->pipe_enabled) { | |
243e6a44 VS |
3666 | u32 tmp = hw->wm_pipe[pipe]; |
3667 | ||
3668 | /* | |
3669 | * For active pipes LP0 watermark is marked as | |
3670 | * enabled, and LP1+ watermaks as disabled since | |
3671 | * we can't really reverse compute them in case | |
3672 | * multiple pipes are active. | |
3673 | */ | |
3674 | active->wm[0].enable = true; | |
3675 | active->wm[0].pri_val = (tmp & WM0_PIPE_PLANE_MASK) >> WM0_PIPE_PLANE_SHIFT; | |
3676 | active->wm[0].spr_val = (tmp & WM0_PIPE_SPRITE_MASK) >> WM0_PIPE_SPRITE_SHIFT; | |
3677 | active->wm[0].cur_val = tmp & WM0_PIPE_CURSOR_MASK; | |
3678 | active->linetime = hw->wm_linetime[pipe]; | |
3679 | } else { | |
3680 | int level, max_level = ilk_wm_max_level(dev); | |
3681 | ||
3682 | /* | |
3683 | * For inactive pipes, all watermark levels | |
3684 | * should be marked as enabled but zeroed, | |
3685 | * which is what we'd compute them to. | |
3686 | */ | |
3687 | for (level = 0; level <= max_level; level++) | |
3688 | active->wm[level].enable = true; | |
3689 | } | |
3690 | } | |
3691 | ||
3692 | void ilk_wm_get_hw_state(struct drm_device *dev) | |
3693 | { | |
3694 | struct drm_i915_private *dev_priv = dev->dev_private; | |
820c1980 | 3695 | struct ilk_wm_values *hw = &dev_priv->wm.hw; |
243e6a44 VS |
3696 | struct drm_crtc *crtc; |
3697 | ||
70e1e0ec | 3698 | for_each_crtc(dev, crtc) |
243e6a44 VS |
3699 | ilk_pipe_wm_get_hw_state(crtc); |
3700 | ||
3701 | hw->wm_lp[0] = I915_READ(WM1_LP_ILK); | |
3702 | hw->wm_lp[1] = I915_READ(WM2_LP_ILK); | |
3703 | hw->wm_lp[2] = I915_READ(WM3_LP_ILK); | |
3704 | ||
3705 | hw->wm_lp_spr[0] = I915_READ(WM1S_LP_ILK); | |
cfa7698b VS |
3706 | if (INTEL_INFO(dev)->gen >= 7) { |
3707 | hw->wm_lp_spr[1] = I915_READ(WM2S_LP_IVB); | |
3708 | hw->wm_lp_spr[2] = I915_READ(WM3S_LP_IVB); | |
3709 | } | |
243e6a44 | 3710 | |
a42a5719 | 3711 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) |
ac9545fd VS |
3712 | hw->partitioning = (I915_READ(WM_MISC) & WM_MISC_DATA_PARTITION_5_6) ? |
3713 | INTEL_DDB_PART_5_6 : INTEL_DDB_PART_1_2; | |
3714 | else if (IS_IVYBRIDGE(dev)) | |
3715 | hw->partitioning = (I915_READ(DISP_ARB_CTL2) & DISP_DATA_PARTITION_5_6) ? | |
3716 | INTEL_DDB_PART_5_6 : INTEL_DDB_PART_1_2; | |
243e6a44 VS |
3717 | |
3718 | hw->enable_fbc_wm = | |
3719 | !(I915_READ(DISP_ARB_CTL) & DISP_FBC_WM_DIS); | |
3720 | } | |
3721 | ||
b445e3b0 ED |
3722 | /** |
3723 | * intel_update_watermarks - update FIFO watermark values based on current modes | |
3724 | * | |
3725 | * Calculate watermark values for the various WM regs based on current mode | |
3726 | * and plane configuration. | |
3727 | * | |
3728 | * There are several cases to deal with here: | |
3729 | * - normal (i.e. non-self-refresh) | |
3730 | * - self-refresh (SR) mode | |
3731 | * - lines are large relative to FIFO size (buffer can hold up to 2) | |
3732 | * - lines are small relative to FIFO size (buffer can hold more than 2 | |
3733 | * lines), so need to account for TLB latency | |
3734 | * | |
3735 | * The normal calculation is: | |
3736 | * watermark = dotclock * bytes per pixel * latency | |
3737 | * where latency is platform & configuration dependent (we assume pessimal | |
3738 | * values here). | |
3739 | * | |
3740 | * The SR calculation is: | |
3741 | * watermark = (trunc(latency/line time)+1) * surface width * | |
3742 | * bytes per pixel | |
3743 | * where | |
3744 | * line time = htotal / dotclock | |
3745 | * surface width = hdisplay for normal plane and 64 for cursor | |
3746 | * and latency is assumed to be high, as above. | |
3747 | * | |
3748 | * The final value programmed to the register should always be rounded up, | |
3749 | * and include an extra 2 entries to account for clock crossings. | |
3750 | * | |
3751 | * We don't use the sprite, so we can ignore that. And on Crestline we have | |
3752 | * to set the non-SR watermarks to 8. | |
3753 | */ | |
46ba614c | 3754 | void intel_update_watermarks(struct drm_crtc *crtc) |
b445e3b0 | 3755 | { |
46ba614c | 3756 | struct drm_i915_private *dev_priv = crtc->dev->dev_private; |
b445e3b0 ED |
3757 | |
3758 | if (dev_priv->display.update_wm) | |
46ba614c | 3759 | dev_priv->display.update_wm(crtc); |
b445e3b0 ED |
3760 | } |
3761 | ||
adf3d35e VS |
3762 | void intel_update_sprite_watermarks(struct drm_plane *plane, |
3763 | struct drm_crtc *crtc, | |
ed57cb8a DL |
3764 | uint32_t sprite_width, |
3765 | uint32_t sprite_height, | |
3766 | int pixel_size, | |
39db4a4d | 3767 | bool enabled, bool scaled) |
b445e3b0 | 3768 | { |
adf3d35e | 3769 | struct drm_i915_private *dev_priv = plane->dev->dev_private; |
b445e3b0 ED |
3770 | |
3771 | if (dev_priv->display.update_sprite_wm) | |
ed57cb8a DL |
3772 | dev_priv->display.update_sprite_wm(plane, crtc, |
3773 | sprite_width, sprite_height, | |
39db4a4d | 3774 | pixel_size, enabled, scaled); |
b445e3b0 ED |
3775 | } |
3776 | ||
9270388e DV |
3777 | /** |
3778 | * Lock protecting IPS related data structures | |
9270388e DV |
3779 | */ |
3780 | DEFINE_SPINLOCK(mchdev_lock); | |
3781 | ||
3782 | /* Global for IPS driver to get at the current i915 device. Protected by | |
3783 | * mchdev_lock. */ | |
3784 | static struct drm_i915_private *i915_mch_dev; | |
3785 | ||
2b4e57bd ED |
3786 | bool ironlake_set_drps(struct drm_device *dev, u8 val) |
3787 | { | |
3788 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3789 | u16 rgvswctl; | |
3790 | ||
9270388e DV |
3791 | assert_spin_locked(&mchdev_lock); |
3792 | ||
2b4e57bd ED |
3793 | rgvswctl = I915_READ16(MEMSWCTL); |
3794 | if (rgvswctl & MEMCTL_CMD_STS) { | |
3795 | DRM_DEBUG("gpu busy, RCS change rejected\n"); | |
3796 | return false; /* still busy with another command */ | |
3797 | } | |
3798 | ||
3799 | rgvswctl = (MEMCTL_CMD_CHFREQ << MEMCTL_CMD_SHIFT) | | |
3800 | (val << MEMCTL_FREQ_SHIFT) | MEMCTL_SFCAVM; | |
3801 | I915_WRITE16(MEMSWCTL, rgvswctl); | |
3802 | POSTING_READ16(MEMSWCTL); | |
3803 | ||
3804 | rgvswctl |= MEMCTL_CMD_STS; | |
3805 | I915_WRITE16(MEMSWCTL, rgvswctl); | |
3806 | ||
3807 | return true; | |
3808 | } | |
3809 | ||
8090c6b9 | 3810 | static void ironlake_enable_drps(struct drm_device *dev) |
2b4e57bd ED |
3811 | { |
3812 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3813 | u32 rgvmodectl = I915_READ(MEMMODECTL); | |
3814 | u8 fmax, fmin, fstart, vstart; | |
3815 | ||
9270388e DV |
3816 | spin_lock_irq(&mchdev_lock); |
3817 | ||
2b4e57bd ED |
3818 | /* Enable temp reporting */ |
3819 | I915_WRITE16(PMMISC, I915_READ(PMMISC) | MCPPCE_EN); | |
3820 | I915_WRITE16(TSC1, I915_READ(TSC1) | TSE); | |
3821 | ||
3822 | /* 100ms RC evaluation intervals */ | |
3823 | I915_WRITE(RCUPEI, 100000); | |
3824 | I915_WRITE(RCDNEI, 100000); | |
3825 | ||
3826 | /* Set max/min thresholds to 90ms and 80ms respectively */ | |
3827 | I915_WRITE(RCBMAXAVG, 90000); | |
3828 | I915_WRITE(RCBMINAVG, 80000); | |
3829 | ||
3830 | I915_WRITE(MEMIHYST, 1); | |
3831 | ||
3832 | /* Set up min, max, and cur for interrupt handling */ | |
3833 | fmax = (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT; | |
3834 | fmin = (rgvmodectl & MEMMODE_FMIN_MASK); | |
3835 | fstart = (rgvmodectl & MEMMODE_FSTART_MASK) >> | |
3836 | MEMMODE_FSTART_SHIFT; | |
3837 | ||
3838 | vstart = (I915_READ(PXVFREQ_BASE + (fstart * 4)) & PXVFREQ_PX_MASK) >> | |
3839 | PXVFREQ_PX_SHIFT; | |
3840 | ||
20e4d407 DV |
3841 | dev_priv->ips.fmax = fmax; /* IPS callback will increase this */ |
3842 | dev_priv->ips.fstart = fstart; | |
2b4e57bd | 3843 | |
20e4d407 DV |
3844 | dev_priv->ips.max_delay = fstart; |
3845 | dev_priv->ips.min_delay = fmin; | |
3846 | dev_priv->ips.cur_delay = fstart; | |
2b4e57bd ED |
3847 | |
3848 | DRM_DEBUG_DRIVER("fmax: %d, fmin: %d, fstart: %d\n", | |
3849 | fmax, fmin, fstart); | |
3850 | ||
3851 | I915_WRITE(MEMINTREN, MEMINT_CX_SUPR_EN | MEMINT_EVAL_CHG_EN); | |
3852 | ||
3853 | /* | |
3854 | * Interrupts will be enabled in ironlake_irq_postinstall | |
3855 | */ | |
3856 | ||
3857 | I915_WRITE(VIDSTART, vstart); | |
3858 | POSTING_READ(VIDSTART); | |
3859 | ||
3860 | rgvmodectl |= MEMMODE_SWMODE_EN; | |
3861 | I915_WRITE(MEMMODECTL, rgvmodectl); | |
3862 | ||
9270388e | 3863 | if (wait_for_atomic((I915_READ(MEMSWCTL) & MEMCTL_CMD_STS) == 0, 10)) |
2b4e57bd | 3864 | DRM_ERROR("stuck trying to change perf mode\n"); |
9270388e | 3865 | mdelay(1); |
2b4e57bd ED |
3866 | |
3867 | ironlake_set_drps(dev, fstart); | |
3868 | ||
20e4d407 | 3869 | dev_priv->ips.last_count1 = I915_READ(0x112e4) + I915_READ(0x112e8) + |
2b4e57bd | 3870 | I915_READ(0x112e0); |
20e4d407 DV |
3871 | dev_priv->ips.last_time1 = jiffies_to_msecs(jiffies); |
3872 | dev_priv->ips.last_count2 = I915_READ(0x112f4); | |
5ed0bdf2 | 3873 | dev_priv->ips.last_time2 = ktime_get_raw_ns(); |
9270388e DV |
3874 | |
3875 | spin_unlock_irq(&mchdev_lock); | |
2b4e57bd ED |
3876 | } |
3877 | ||
8090c6b9 | 3878 | static void ironlake_disable_drps(struct drm_device *dev) |
2b4e57bd ED |
3879 | { |
3880 | struct drm_i915_private *dev_priv = dev->dev_private; | |
9270388e DV |
3881 | u16 rgvswctl; |
3882 | ||
3883 | spin_lock_irq(&mchdev_lock); | |
3884 | ||
3885 | rgvswctl = I915_READ16(MEMSWCTL); | |
2b4e57bd ED |
3886 | |
3887 | /* Ack interrupts, disable EFC interrupt */ | |
3888 | I915_WRITE(MEMINTREN, I915_READ(MEMINTREN) & ~MEMINT_EVAL_CHG_EN); | |
3889 | I915_WRITE(MEMINTRSTS, MEMINT_EVAL_CHG); | |
3890 | I915_WRITE(DEIER, I915_READ(DEIER) & ~DE_PCU_EVENT); | |
3891 | I915_WRITE(DEIIR, DE_PCU_EVENT); | |
3892 | I915_WRITE(DEIMR, I915_READ(DEIMR) | DE_PCU_EVENT); | |
3893 | ||
3894 | /* Go back to the starting frequency */ | |
20e4d407 | 3895 | ironlake_set_drps(dev, dev_priv->ips.fstart); |
9270388e | 3896 | mdelay(1); |
2b4e57bd ED |
3897 | rgvswctl |= MEMCTL_CMD_STS; |
3898 | I915_WRITE(MEMSWCTL, rgvswctl); | |
9270388e | 3899 | mdelay(1); |
2b4e57bd | 3900 | |
9270388e | 3901 | spin_unlock_irq(&mchdev_lock); |
2b4e57bd ED |
3902 | } |
3903 | ||
acbe9475 DV |
3904 | /* There's a funny hw issue where the hw returns all 0 when reading from |
3905 | * GEN6_RP_INTERRUPT_LIMITS. Hence we always need to compute the desired value | |
3906 | * ourselves, instead of doing a rmw cycle (which might result in us clearing | |
3907 | * all limits and the gpu stuck at whatever frequency it is at atm). | |
3908 | */ | |
74ef1173 | 3909 | static u32 intel_rps_limits(struct drm_i915_private *dev_priv, u8 val) |
2b4e57bd | 3910 | { |
7b9e0ae6 | 3911 | u32 limits; |
2b4e57bd | 3912 | |
20b46e59 DV |
3913 | /* Only set the down limit when we've reached the lowest level to avoid |
3914 | * getting more interrupts, otherwise leave this clear. This prevents a | |
3915 | * race in the hw when coming out of rc6: There's a tiny window where | |
3916 | * the hw runs at the minimal clock before selecting the desired | |
3917 | * frequency, if the down threshold expires in that window we will not | |
3918 | * receive a down interrupt. */ | |
74ef1173 AG |
3919 | if (IS_GEN9(dev_priv->dev)) { |
3920 | limits = (dev_priv->rps.max_freq_softlimit) << 23; | |
3921 | if (val <= dev_priv->rps.min_freq_softlimit) | |
3922 | limits |= (dev_priv->rps.min_freq_softlimit) << 14; | |
3923 | } else { | |
3924 | limits = dev_priv->rps.max_freq_softlimit << 24; | |
3925 | if (val <= dev_priv->rps.min_freq_softlimit) | |
3926 | limits |= dev_priv->rps.min_freq_softlimit << 16; | |
3927 | } | |
20b46e59 DV |
3928 | |
3929 | return limits; | |
3930 | } | |
3931 | ||
dd75fdc8 CW |
3932 | static void gen6_set_rps_thresholds(struct drm_i915_private *dev_priv, u8 val) |
3933 | { | |
3934 | int new_power; | |
8a586437 AG |
3935 | u32 threshold_up = 0, threshold_down = 0; /* in % */ |
3936 | u32 ei_up = 0, ei_down = 0; | |
dd75fdc8 CW |
3937 | |
3938 | new_power = dev_priv->rps.power; | |
3939 | switch (dev_priv->rps.power) { | |
3940 | case LOW_POWER: | |
b39fb297 | 3941 | if (val > dev_priv->rps.efficient_freq + 1 && val > dev_priv->rps.cur_freq) |
dd75fdc8 CW |
3942 | new_power = BETWEEN; |
3943 | break; | |
3944 | ||
3945 | case BETWEEN: | |
b39fb297 | 3946 | if (val <= dev_priv->rps.efficient_freq && val < dev_priv->rps.cur_freq) |
dd75fdc8 | 3947 | new_power = LOW_POWER; |
b39fb297 | 3948 | else if (val >= dev_priv->rps.rp0_freq && val > dev_priv->rps.cur_freq) |
dd75fdc8 CW |
3949 | new_power = HIGH_POWER; |
3950 | break; | |
3951 | ||
3952 | case HIGH_POWER: | |
b39fb297 | 3953 | if (val < (dev_priv->rps.rp1_freq + dev_priv->rps.rp0_freq) >> 1 && val < dev_priv->rps.cur_freq) |
dd75fdc8 CW |
3954 | new_power = BETWEEN; |
3955 | break; | |
3956 | } | |
3957 | /* Max/min bins are special */ | |
aed242ff | 3958 | if (val <= dev_priv->rps.min_freq_softlimit) |
dd75fdc8 | 3959 | new_power = LOW_POWER; |
aed242ff | 3960 | if (val >= dev_priv->rps.max_freq_softlimit) |
dd75fdc8 CW |
3961 | new_power = HIGH_POWER; |
3962 | if (new_power == dev_priv->rps.power) | |
3963 | return; | |
3964 | ||
3965 | /* Note the units here are not exactly 1us, but 1280ns. */ | |
3966 | switch (new_power) { | |
3967 | case LOW_POWER: | |
3968 | /* Upclock if more than 95% busy over 16ms */ | |
8a586437 AG |
3969 | ei_up = 16000; |
3970 | threshold_up = 95; | |
dd75fdc8 CW |
3971 | |
3972 | /* Downclock if less than 85% busy over 32ms */ | |
8a586437 AG |
3973 | ei_down = 32000; |
3974 | threshold_down = 85; | |
dd75fdc8 CW |
3975 | break; |
3976 | ||
3977 | case BETWEEN: | |
3978 | /* Upclock if more than 90% busy over 13ms */ | |
8a586437 AG |
3979 | ei_up = 13000; |
3980 | threshold_up = 90; | |
dd75fdc8 CW |
3981 | |
3982 | /* Downclock if less than 75% busy over 32ms */ | |
8a586437 AG |
3983 | ei_down = 32000; |
3984 | threshold_down = 75; | |
dd75fdc8 CW |
3985 | break; |
3986 | ||
3987 | case HIGH_POWER: | |
3988 | /* Upclock if more than 85% busy over 10ms */ | |
8a586437 AG |
3989 | ei_up = 10000; |
3990 | threshold_up = 85; | |
dd75fdc8 CW |
3991 | |
3992 | /* Downclock if less than 60% busy over 32ms */ | |
8a586437 AG |
3993 | ei_down = 32000; |
3994 | threshold_down = 60; | |
dd75fdc8 CW |
3995 | break; |
3996 | } | |
3997 | ||
8a586437 AG |
3998 | I915_WRITE(GEN6_RP_UP_EI, |
3999 | GT_INTERVAL_FROM_US(dev_priv, ei_up)); | |
4000 | I915_WRITE(GEN6_RP_UP_THRESHOLD, | |
4001 | GT_INTERVAL_FROM_US(dev_priv, (ei_up * threshold_up / 100))); | |
4002 | ||
4003 | I915_WRITE(GEN6_RP_DOWN_EI, | |
4004 | GT_INTERVAL_FROM_US(dev_priv, ei_down)); | |
4005 | I915_WRITE(GEN6_RP_DOWN_THRESHOLD, | |
4006 | GT_INTERVAL_FROM_US(dev_priv, (ei_down * threshold_down / 100))); | |
4007 | ||
4008 | I915_WRITE(GEN6_RP_CONTROL, | |
4009 | GEN6_RP_MEDIA_TURBO | | |
4010 | GEN6_RP_MEDIA_HW_NORMAL_MODE | | |
4011 | GEN6_RP_MEDIA_IS_GFX | | |
4012 | GEN6_RP_ENABLE | | |
4013 | GEN6_RP_UP_BUSY_AVG | | |
4014 | GEN6_RP_DOWN_IDLE_AVG); | |
4015 | ||
dd75fdc8 | 4016 | dev_priv->rps.power = new_power; |
8fb55197 CW |
4017 | dev_priv->rps.up_threshold = threshold_up; |
4018 | dev_priv->rps.down_threshold = threshold_down; | |
dd75fdc8 CW |
4019 | dev_priv->rps.last_adj = 0; |
4020 | } | |
4021 | ||
2876ce73 CW |
4022 | static u32 gen6_rps_pm_mask(struct drm_i915_private *dev_priv, u8 val) |
4023 | { | |
4024 | u32 mask = 0; | |
4025 | ||
4026 | if (val > dev_priv->rps.min_freq_softlimit) | |
6f4b12f8 | 4027 | mask |= GEN6_PM_RP_DOWN_EI_EXPIRED | GEN6_PM_RP_DOWN_THRESHOLD | GEN6_PM_RP_DOWN_TIMEOUT; |
2876ce73 | 4028 | if (val < dev_priv->rps.max_freq_softlimit) |
6f4b12f8 | 4029 | mask |= GEN6_PM_RP_UP_EI_EXPIRED | GEN6_PM_RP_UP_THRESHOLD; |
2876ce73 | 4030 | |
7b3c29f6 CW |
4031 | mask &= dev_priv->pm_rps_events; |
4032 | ||
59d02a1f | 4033 | return gen6_sanitize_rps_pm_mask(dev_priv, ~mask); |
2876ce73 CW |
4034 | } |
4035 | ||
b8a5ff8d JM |
4036 | /* gen6_set_rps is called to update the frequency request, but should also be |
4037 | * called when the range (min_delay and max_delay) is modified so that we can | |
4038 | * update the GEN6_RP_INTERRUPT_LIMITS register accordingly. */ | |
ffe02b40 | 4039 | static void gen6_set_rps(struct drm_device *dev, u8 val) |
20b46e59 DV |
4040 | { |
4041 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7b9e0ae6 | 4042 | |
4fc688ce | 4043 | WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock)); |
aed242ff CW |
4044 | WARN_ON(val > dev_priv->rps.max_freq); |
4045 | WARN_ON(val < dev_priv->rps.min_freq); | |
004777cb | 4046 | |
eb64cad1 CW |
4047 | /* min/max delay may still have been modified so be sure to |
4048 | * write the limits value. | |
4049 | */ | |
4050 | if (val != dev_priv->rps.cur_freq) { | |
4051 | gen6_set_rps_thresholds(dev_priv, val); | |
b8a5ff8d | 4052 | |
5704195c AG |
4053 | if (IS_GEN9(dev)) |
4054 | I915_WRITE(GEN6_RPNSWREQ, | |
4055 | GEN9_FREQUENCY(val)); | |
4056 | else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) | |
eb64cad1 CW |
4057 | I915_WRITE(GEN6_RPNSWREQ, |
4058 | HSW_FREQUENCY(val)); | |
4059 | else | |
4060 | I915_WRITE(GEN6_RPNSWREQ, | |
4061 | GEN6_FREQUENCY(val) | | |
4062 | GEN6_OFFSET(0) | | |
4063 | GEN6_AGGRESSIVE_TURBO); | |
b8a5ff8d | 4064 | } |
7b9e0ae6 | 4065 | |
7b9e0ae6 CW |
4066 | /* Make sure we continue to get interrupts |
4067 | * until we hit the minimum or maximum frequencies. | |
4068 | */ | |
74ef1173 | 4069 | I915_WRITE(GEN6_RP_INTERRUPT_LIMITS, intel_rps_limits(dev_priv, val)); |
2876ce73 | 4070 | I915_WRITE(GEN6_PMINTRMSK, gen6_rps_pm_mask(dev_priv, val)); |
7b9e0ae6 | 4071 | |
d5570a72 BW |
4072 | POSTING_READ(GEN6_RPNSWREQ); |
4073 | ||
b39fb297 | 4074 | dev_priv->rps.cur_freq = val; |
be2cde9a | 4075 | trace_intel_gpu_freq_change(val * 50); |
2b4e57bd ED |
4076 | } |
4077 | ||
ffe02b40 VS |
4078 | static void valleyview_set_rps(struct drm_device *dev, u8 val) |
4079 | { | |
4080 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4081 | ||
4082 | WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock)); | |
aed242ff CW |
4083 | WARN_ON(val > dev_priv->rps.max_freq); |
4084 | WARN_ON(val < dev_priv->rps.min_freq); | |
ffe02b40 VS |
4085 | |
4086 | if (WARN_ONCE(IS_CHERRYVIEW(dev) && (val & 1), | |
4087 | "Odd GPU freq value\n")) | |
4088 | val &= ~1; | |
4089 | ||
8fb55197 | 4090 | if (val != dev_priv->rps.cur_freq) { |
ffe02b40 | 4091 | vlv_punit_write(dev_priv, PUNIT_REG_GPU_FREQ_REQ, val); |
8fb55197 CW |
4092 | if (!IS_CHERRYVIEW(dev_priv)) |
4093 | gen6_set_rps_thresholds(dev_priv, val); | |
4094 | } | |
ffe02b40 VS |
4095 | |
4096 | I915_WRITE(GEN6_PMINTRMSK, gen6_rps_pm_mask(dev_priv, val)); | |
4097 | ||
4098 | dev_priv->rps.cur_freq = val; | |
4099 | trace_intel_gpu_freq_change(intel_gpu_freq(dev_priv, val)); | |
4100 | } | |
4101 | ||
a7f6e231 | 4102 | /* vlv_set_rps_idle: Set the frequency to idle, if Gfx clocks are down |
76c3552f D |
4103 | * |
4104 | * * If Gfx is Idle, then | |
a7f6e231 D |
4105 | * 1. Forcewake Media well. |
4106 | * 2. Request idle freq. | |
4107 | * 3. Release Forcewake of Media well. | |
76c3552f D |
4108 | */ |
4109 | static void vlv_set_rps_idle(struct drm_i915_private *dev_priv) | |
4110 | { | |
aed242ff | 4111 | u32 val = dev_priv->rps.idle_freq; |
5549d25f | 4112 | |
aed242ff | 4113 | if (dev_priv->rps.cur_freq <= val) |
76c3552f D |
4114 | return; |
4115 | ||
a7f6e231 D |
4116 | /* Wake up the media well, as that takes a lot less |
4117 | * power than the Render well. */ | |
4118 | intel_uncore_forcewake_get(dev_priv, FORCEWAKE_MEDIA); | |
4119 | valleyview_set_rps(dev_priv->dev, val); | |
4120 | intel_uncore_forcewake_put(dev_priv, FORCEWAKE_MEDIA); | |
76c3552f D |
4121 | } |
4122 | ||
43cf3bf0 CW |
4123 | void gen6_rps_busy(struct drm_i915_private *dev_priv) |
4124 | { | |
4125 | mutex_lock(&dev_priv->rps.hw_lock); | |
4126 | if (dev_priv->rps.enabled) { | |
4127 | if (dev_priv->pm_rps_events & (GEN6_PM_RP_DOWN_EI_EXPIRED | GEN6_PM_RP_UP_EI_EXPIRED)) | |
4128 | gen6_rps_reset_ei(dev_priv); | |
4129 | I915_WRITE(GEN6_PMINTRMSK, | |
4130 | gen6_rps_pm_mask(dev_priv, dev_priv->rps.cur_freq)); | |
4131 | } | |
4132 | mutex_unlock(&dev_priv->rps.hw_lock); | |
4133 | } | |
4134 | ||
b29c19b6 CW |
4135 | void gen6_rps_idle(struct drm_i915_private *dev_priv) |
4136 | { | |
691bb717 DL |
4137 | struct drm_device *dev = dev_priv->dev; |
4138 | ||
b29c19b6 | 4139 | mutex_lock(&dev_priv->rps.hw_lock); |
c0951f0c | 4140 | if (dev_priv->rps.enabled) { |
21a11fff | 4141 | if (IS_VALLEYVIEW(dev)) |
76c3552f | 4142 | vlv_set_rps_idle(dev_priv); |
7526ed79 | 4143 | else |
aed242ff | 4144 | gen6_set_rps(dev_priv->dev, dev_priv->rps.idle_freq); |
c0951f0c | 4145 | dev_priv->rps.last_adj = 0; |
43cf3bf0 | 4146 | I915_WRITE(GEN6_PMINTRMSK, 0xffffffff); |
c0951f0c | 4147 | } |
8d3afd7d | 4148 | mutex_unlock(&dev_priv->rps.hw_lock); |
1854d5ca | 4149 | |
8d3afd7d | 4150 | spin_lock(&dev_priv->rps.client_lock); |
1854d5ca CW |
4151 | while (!list_empty(&dev_priv->rps.clients)) |
4152 | list_del_init(dev_priv->rps.clients.next); | |
8d3afd7d | 4153 | spin_unlock(&dev_priv->rps.client_lock); |
b29c19b6 CW |
4154 | } |
4155 | ||
1854d5ca | 4156 | void gen6_rps_boost(struct drm_i915_private *dev_priv, |
e61b9958 CW |
4157 | struct intel_rps_client *rps, |
4158 | unsigned long submitted) | |
b29c19b6 | 4159 | { |
8d3afd7d CW |
4160 | /* This is intentionally racy! We peek at the state here, then |
4161 | * validate inside the RPS worker. | |
4162 | */ | |
4163 | if (!(dev_priv->mm.busy && | |
4164 | dev_priv->rps.enabled && | |
4165 | dev_priv->rps.cur_freq < dev_priv->rps.max_freq_softlimit)) | |
4166 | return; | |
43cf3bf0 | 4167 | |
e61b9958 CW |
4168 | /* Force a RPS boost (and don't count it against the client) if |
4169 | * the GPU is severely congested. | |
4170 | */ | |
d0bc54f2 | 4171 | if (rps && time_after(jiffies, submitted + DRM_I915_THROTTLE_JIFFIES)) |
e61b9958 CW |
4172 | rps = NULL; |
4173 | ||
8d3afd7d CW |
4174 | spin_lock(&dev_priv->rps.client_lock); |
4175 | if (rps == NULL || list_empty(&rps->link)) { | |
4176 | spin_lock_irq(&dev_priv->irq_lock); | |
4177 | if (dev_priv->rps.interrupts_enabled) { | |
4178 | dev_priv->rps.client_boost = true; | |
4179 | queue_work(dev_priv->wq, &dev_priv->rps.work); | |
4180 | } | |
4181 | spin_unlock_irq(&dev_priv->irq_lock); | |
1854d5ca | 4182 | |
2e1b8730 CW |
4183 | if (rps != NULL) { |
4184 | list_add(&rps->link, &dev_priv->rps.clients); | |
4185 | rps->boosts++; | |
1854d5ca CW |
4186 | } else |
4187 | dev_priv->rps.boosts++; | |
c0951f0c | 4188 | } |
8d3afd7d | 4189 | spin_unlock(&dev_priv->rps.client_lock); |
b29c19b6 CW |
4190 | } |
4191 | ||
ffe02b40 | 4192 | void intel_set_rps(struct drm_device *dev, u8 val) |
0a073b84 | 4193 | { |
ffe02b40 VS |
4194 | if (IS_VALLEYVIEW(dev)) |
4195 | valleyview_set_rps(dev, val); | |
4196 | else | |
4197 | gen6_set_rps(dev, val); | |
0a073b84 JB |
4198 | } |
4199 | ||
20e49366 ZW |
4200 | static void gen9_disable_rps(struct drm_device *dev) |
4201 | { | |
4202 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4203 | ||
4204 | I915_WRITE(GEN6_RC_CONTROL, 0); | |
38c23527 | 4205 | I915_WRITE(GEN9_PG_ENABLE, 0); |
20e49366 ZW |
4206 | } |
4207 | ||
44fc7d5c | 4208 | static void gen6_disable_rps(struct drm_device *dev) |
d20d4f0c JB |
4209 | { |
4210 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4211 | ||
4212 | I915_WRITE(GEN6_RC_CONTROL, 0); | |
44fc7d5c | 4213 | I915_WRITE(GEN6_RPNSWREQ, 1 << 31); |
44fc7d5c DV |
4214 | } |
4215 | ||
38807746 D |
4216 | static void cherryview_disable_rps(struct drm_device *dev) |
4217 | { | |
4218 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4219 | ||
4220 | I915_WRITE(GEN6_RC_CONTROL, 0); | |
4221 | } | |
4222 | ||
44fc7d5c DV |
4223 | static void valleyview_disable_rps(struct drm_device *dev) |
4224 | { | |
4225 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4226 | ||
98a2e5f9 D |
4227 | /* we're doing forcewake before Disabling RC6, |
4228 | * This what the BIOS expects when going into suspend */ | |
59bad947 | 4229 | intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL); |
98a2e5f9 | 4230 | |
44fc7d5c | 4231 | I915_WRITE(GEN6_RC_CONTROL, 0); |
d20d4f0c | 4232 | |
59bad947 | 4233 | intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL); |
d20d4f0c JB |
4234 | } |
4235 | ||
dc39fff7 BW |
4236 | static void intel_print_rc6_info(struct drm_device *dev, u32 mode) |
4237 | { | |
91ca689a ID |
4238 | if (IS_VALLEYVIEW(dev)) { |
4239 | if (mode & (GEN7_RC_CTL_TO_MODE | GEN6_RC_CTL_EI_MODE(1))) | |
4240 | mode = GEN6_RC_CTL_RC6_ENABLE; | |
4241 | else | |
4242 | mode = 0; | |
4243 | } | |
58abf1da RV |
4244 | if (HAS_RC6p(dev)) |
4245 | DRM_DEBUG_KMS("Enabling RC6 states: RC6 %s RC6p %s RC6pp %s\n", | |
4246 | (mode & GEN6_RC_CTL_RC6_ENABLE) ? "on" : "off", | |
4247 | (mode & GEN6_RC_CTL_RC6p_ENABLE) ? "on" : "off", | |
4248 | (mode & GEN6_RC_CTL_RC6pp_ENABLE) ? "on" : "off"); | |
4249 | ||
4250 | else | |
4251 | DRM_DEBUG_KMS("Enabling RC6 states: RC6 %s\n", | |
4252 | (mode & GEN6_RC_CTL_RC6_ENABLE) ? "on" : "off"); | |
dc39fff7 BW |
4253 | } |
4254 | ||
e6069ca8 | 4255 | static int sanitize_rc6_option(const struct drm_device *dev, int enable_rc6) |
2b4e57bd | 4256 | { |
e7d66d89 DV |
4257 | /* No RC6 before Ironlake and code is gone for ilk. */ |
4258 | if (INTEL_INFO(dev)->gen < 6) | |
e6069ca8 ID |
4259 | return 0; |
4260 | ||
456470eb | 4261 | /* Respect the kernel parameter if it is set */ |
e6069ca8 ID |
4262 | if (enable_rc6 >= 0) { |
4263 | int mask; | |
4264 | ||
58abf1da | 4265 | if (HAS_RC6p(dev)) |
e6069ca8 ID |
4266 | mask = INTEL_RC6_ENABLE | INTEL_RC6p_ENABLE | |
4267 | INTEL_RC6pp_ENABLE; | |
4268 | else | |
4269 | mask = INTEL_RC6_ENABLE; | |
4270 | ||
4271 | if ((enable_rc6 & mask) != enable_rc6) | |
8dfd1f04 DV |
4272 | DRM_DEBUG_KMS("Adjusting RC6 mask to %d (requested %d, valid %d)\n", |
4273 | enable_rc6 & mask, enable_rc6, mask); | |
e6069ca8 ID |
4274 | |
4275 | return enable_rc6 & mask; | |
4276 | } | |
2b4e57bd | 4277 | |
8bade1ad | 4278 | if (IS_IVYBRIDGE(dev)) |
cca84a1f | 4279 | return (INTEL_RC6_ENABLE | INTEL_RC6p_ENABLE); |
8bade1ad BW |
4280 | |
4281 | return INTEL_RC6_ENABLE; | |
2b4e57bd ED |
4282 | } |
4283 | ||
e6069ca8 ID |
4284 | int intel_enable_rc6(const struct drm_device *dev) |
4285 | { | |
4286 | return i915.enable_rc6; | |
4287 | } | |
4288 | ||
93ee2920 | 4289 | static void gen6_init_rps_frequencies(struct drm_device *dev) |
3280e8b0 | 4290 | { |
93ee2920 TR |
4291 | struct drm_i915_private *dev_priv = dev->dev_private; |
4292 | uint32_t rp_state_cap; | |
4293 | u32 ddcc_status = 0; | |
4294 | int ret; | |
4295 | ||
3280e8b0 BW |
4296 | /* All of these values are in units of 50MHz */ |
4297 | dev_priv->rps.cur_freq = 0; | |
93ee2920 | 4298 | /* static values from HW: RP0 > RP1 > RPn (min_freq) */ |
35040562 BP |
4299 | if (IS_BROXTON(dev)) { |
4300 | rp_state_cap = I915_READ(BXT_RP_STATE_CAP); | |
4301 | dev_priv->rps.rp0_freq = (rp_state_cap >> 16) & 0xff; | |
4302 | dev_priv->rps.rp1_freq = (rp_state_cap >> 8) & 0xff; | |
4303 | dev_priv->rps.min_freq = (rp_state_cap >> 0) & 0xff; | |
4304 | } else { | |
4305 | rp_state_cap = I915_READ(GEN6_RP_STATE_CAP); | |
4306 | dev_priv->rps.rp0_freq = (rp_state_cap >> 0) & 0xff; | |
4307 | dev_priv->rps.rp1_freq = (rp_state_cap >> 8) & 0xff; | |
4308 | dev_priv->rps.min_freq = (rp_state_cap >> 16) & 0xff; | |
4309 | } | |
4310 | ||
cee991cb AG |
4311 | if (IS_SKYLAKE(dev)) { |
4312 | /* Store the frequency values in 16.66 MHZ units, which is | |
4313 | the natural hardware unit for SKL */ | |
4314 | dev_priv->rps.rp0_freq *= GEN9_FREQ_SCALER; | |
4315 | dev_priv->rps.rp1_freq *= GEN9_FREQ_SCALER; | |
4316 | dev_priv->rps.min_freq *= GEN9_FREQ_SCALER; | |
4317 | } | |
3280e8b0 BW |
4318 | /* hw_max = RP0 until we check for overclocking */ |
4319 | dev_priv->rps.max_freq = dev_priv->rps.rp0_freq; | |
4320 | ||
93ee2920 TR |
4321 | dev_priv->rps.efficient_freq = dev_priv->rps.rp1_freq; |
4322 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) { | |
4323 | ret = sandybridge_pcode_read(dev_priv, | |
4324 | HSW_PCODE_DYNAMIC_DUTY_CYCLE_CONTROL, | |
4325 | &ddcc_status); | |
4326 | if (0 == ret) | |
4327 | dev_priv->rps.efficient_freq = | |
46efa4ab TR |
4328 | clamp_t(u8, |
4329 | ((ddcc_status >> 8) & 0xff), | |
4330 | dev_priv->rps.min_freq, | |
4331 | dev_priv->rps.max_freq); | |
93ee2920 TR |
4332 | } |
4333 | ||
aed242ff CW |
4334 | dev_priv->rps.idle_freq = dev_priv->rps.min_freq; |
4335 | ||
3280e8b0 BW |
4336 | /* Preserve min/max settings in case of re-init */ |
4337 | if (dev_priv->rps.max_freq_softlimit == 0) | |
4338 | dev_priv->rps.max_freq_softlimit = dev_priv->rps.max_freq; | |
4339 | ||
93ee2920 TR |
4340 | if (dev_priv->rps.min_freq_softlimit == 0) { |
4341 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) | |
4342 | dev_priv->rps.min_freq_softlimit = | |
813b5e69 VS |
4343 | max_t(int, dev_priv->rps.efficient_freq, |
4344 | intel_freq_opcode(dev_priv, 450)); | |
93ee2920 TR |
4345 | else |
4346 | dev_priv->rps.min_freq_softlimit = | |
4347 | dev_priv->rps.min_freq; | |
4348 | } | |
3280e8b0 BW |
4349 | } |
4350 | ||
b6fef0ef | 4351 | /* See the Gen9_GT_PM_Programming_Guide doc for the below */ |
20e49366 | 4352 | static void gen9_enable_rps(struct drm_device *dev) |
b6fef0ef JB |
4353 | { |
4354 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4355 | ||
4356 | intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL); | |
4357 | ||
ba1c554c DL |
4358 | gen6_init_rps_frequencies(dev); |
4359 | ||
0beb059a AG |
4360 | /* Program defaults and thresholds for RPS*/ |
4361 | I915_WRITE(GEN6_RC_VIDEO_FREQ, | |
4362 | GEN9_FREQUENCY(dev_priv->rps.rp1_freq)); | |
4363 | ||
4364 | /* 1 second timeout*/ | |
4365 | I915_WRITE(GEN6_RP_DOWN_TIMEOUT, | |
4366 | GT_INTERVAL_FROM_US(dev_priv, 1000000)); | |
4367 | ||
b6fef0ef | 4368 | I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 0xa); |
b6fef0ef | 4369 | |
0beb059a AG |
4370 | /* Leaning on the below call to gen6_set_rps to program/setup the |
4371 | * Up/Down EI & threshold registers, as well as the RP_CONTROL, | |
4372 | * RP_INTERRUPT_LIMITS & RPNSWREQ registers */ | |
4373 | dev_priv->rps.power = HIGH_POWER; /* force a reset */ | |
4374 | gen6_set_rps(dev_priv->dev, dev_priv->rps.min_freq_softlimit); | |
b6fef0ef JB |
4375 | |
4376 | intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL); | |
4377 | } | |
4378 | ||
4379 | static void gen9_enable_rc6(struct drm_device *dev) | |
20e49366 ZW |
4380 | { |
4381 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4382 | struct intel_engine_cs *ring; | |
4383 | uint32_t rc6_mask = 0; | |
4384 | int unused; | |
4385 | ||
4386 | /* 1a: Software RC state - RC0 */ | |
4387 | I915_WRITE(GEN6_RC_STATE, 0); | |
4388 | ||
4389 | /* 1b: Get forcewake during program sequence. Although the driver | |
4390 | * hasn't enabled a state yet where we need forcewake, BIOS may have.*/ | |
59bad947 | 4391 | intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL); |
20e49366 ZW |
4392 | |
4393 | /* 2a: Disable RC states. */ | |
4394 | I915_WRITE(GEN6_RC_CONTROL, 0); | |
4395 | ||
4396 | /* 2b: Program RC6 thresholds.*/ | |
4397 | I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 54 << 16); | |
4398 | I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */ | |
4399 | I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */ | |
4400 | for_each_ring(ring, dev_priv, unused) | |
4401 | I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10); | |
4402 | I915_WRITE(GEN6_RC_SLEEP, 0); | |
4403 | I915_WRITE(GEN6_RC6_THRESHOLD, 37500); /* 37.5/125ms per EI */ | |
4404 | ||
38c23527 ZW |
4405 | /* 2c: Program Coarse Power Gating Policies. */ |
4406 | I915_WRITE(GEN9_MEDIA_PG_IDLE_HYSTERESIS, 25); | |
4407 | I915_WRITE(GEN9_RENDER_PG_IDLE_HYSTERESIS, 25); | |
4408 | ||
20e49366 ZW |
4409 | /* 3a: Enable RC6 */ |
4410 | if (intel_enable_rc6(dev) & INTEL_RC6_ENABLE) | |
4411 | rc6_mask = GEN6_RC_CTL_RC6_ENABLE; | |
4412 | DRM_INFO("RC6 %s\n", (rc6_mask & GEN6_RC_CTL_RC6_ENABLE) ? | |
4413 | "on" : "off"); | |
4414 | I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE | | |
4415 | GEN6_RC_CTL_EI_MODE(1) | | |
4416 | rc6_mask); | |
4417 | ||
cb07bae0 SK |
4418 | /* |
4419 | * 3b: Enable Coarse Power Gating only when RC6 is enabled. | |
4420 | * WaDisableRenderPowerGating:skl,bxt - Render PG need to be disabled with RC6. | |
4421 | */ | |
a4104c55 | 4422 | I915_WRITE(GEN9_PG_ENABLE, (rc6_mask & GEN6_RC_CTL_RC6_ENABLE) ? |
cb07bae0 | 4423 | GEN9_MEDIA_PG_ENABLE : 0); |
a4104c55 | 4424 | |
38c23527 | 4425 | |
59bad947 | 4426 | intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL); |
20e49366 ZW |
4427 | |
4428 | } | |
4429 | ||
6edee7f3 BW |
4430 | static void gen8_enable_rps(struct drm_device *dev) |
4431 | { | |
4432 | struct drm_i915_private *dev_priv = dev->dev_private; | |
a4872ba6 | 4433 | struct intel_engine_cs *ring; |
93ee2920 | 4434 | uint32_t rc6_mask = 0; |
6edee7f3 BW |
4435 | int unused; |
4436 | ||
4437 | /* 1a: Software RC state - RC0 */ | |
4438 | I915_WRITE(GEN6_RC_STATE, 0); | |
4439 | ||
4440 | /* 1c & 1d: Get forcewake during program sequence. Although the driver | |
4441 | * hasn't enabled a state yet where we need forcewake, BIOS may have.*/ | |
59bad947 | 4442 | intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL); |
6edee7f3 BW |
4443 | |
4444 | /* 2a: Disable RC states. */ | |
4445 | I915_WRITE(GEN6_RC_CONTROL, 0); | |
4446 | ||
93ee2920 TR |
4447 | /* Initialize rps frequencies */ |
4448 | gen6_init_rps_frequencies(dev); | |
6edee7f3 BW |
4449 | |
4450 | /* 2b: Program RC6 thresholds.*/ | |
4451 | I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16); | |
4452 | I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */ | |
4453 | I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */ | |
4454 | for_each_ring(ring, dev_priv, unused) | |
4455 | I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10); | |
4456 | I915_WRITE(GEN6_RC_SLEEP, 0); | |
0d68b25e TR |
4457 | if (IS_BROADWELL(dev)) |
4458 | I915_WRITE(GEN6_RC6_THRESHOLD, 625); /* 800us/1.28 for TO */ | |
4459 | else | |
4460 | I915_WRITE(GEN6_RC6_THRESHOLD, 50000); /* 50/125ms per EI */ | |
6edee7f3 BW |
4461 | |
4462 | /* 3: Enable RC6 */ | |
4463 | if (intel_enable_rc6(dev) & INTEL_RC6_ENABLE) | |
4464 | rc6_mask = GEN6_RC_CTL_RC6_ENABLE; | |
abbf9d2c | 4465 | intel_print_rc6_info(dev, rc6_mask); |
0d68b25e TR |
4466 | if (IS_BROADWELL(dev)) |
4467 | I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE | | |
4468 | GEN7_RC_CTL_TO_MODE | | |
4469 | rc6_mask); | |
4470 | else | |
4471 | I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE | | |
4472 | GEN6_RC_CTL_EI_MODE(1) | | |
4473 | rc6_mask); | |
6edee7f3 BW |
4474 | |
4475 | /* 4 Program defaults and thresholds for RPS*/ | |
f9bdc585 BW |
4476 | I915_WRITE(GEN6_RPNSWREQ, |
4477 | HSW_FREQUENCY(dev_priv->rps.rp1_freq)); | |
4478 | I915_WRITE(GEN6_RC_VIDEO_FREQ, | |
4479 | HSW_FREQUENCY(dev_priv->rps.rp1_freq)); | |
7526ed79 DV |
4480 | /* NB: Docs say 1s, and 1000000 - which aren't equivalent */ |
4481 | I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 100000000 / 128); /* 1 second timeout */ | |
4482 | ||
4483 | /* Docs recommend 900MHz, and 300 MHz respectively */ | |
4484 | I915_WRITE(GEN6_RP_INTERRUPT_LIMITS, | |
4485 | dev_priv->rps.max_freq_softlimit << 24 | | |
4486 | dev_priv->rps.min_freq_softlimit << 16); | |
4487 | ||
4488 | I915_WRITE(GEN6_RP_UP_THRESHOLD, 7600000 / 128); /* 76ms busyness per EI, 90% */ | |
4489 | I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 31300000 / 128); /* 313ms busyness per EI, 70%*/ | |
4490 | I915_WRITE(GEN6_RP_UP_EI, 66000); /* 84.48ms, XXX: random? */ | |
4491 | I915_WRITE(GEN6_RP_DOWN_EI, 350000); /* 448ms, XXX: random? */ | |
4492 | ||
4493 | I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10); | |
6edee7f3 BW |
4494 | |
4495 | /* 5: Enable RPS */ | |
7526ed79 DV |
4496 | I915_WRITE(GEN6_RP_CONTROL, |
4497 | GEN6_RP_MEDIA_TURBO | | |
4498 | GEN6_RP_MEDIA_HW_NORMAL_MODE | | |
4499 | GEN6_RP_MEDIA_IS_GFX | | |
4500 | GEN6_RP_ENABLE | | |
4501 | GEN6_RP_UP_BUSY_AVG | | |
4502 | GEN6_RP_DOWN_IDLE_AVG); | |
4503 | ||
4504 | /* 6: Ring frequency + overclocking (our driver does this later */ | |
4505 | ||
c7f3153a | 4506 | dev_priv->rps.power = HIGH_POWER; /* force a reset */ |
aed242ff | 4507 | gen6_set_rps(dev_priv->dev, dev_priv->rps.idle_freq); |
7526ed79 | 4508 | |
59bad947 | 4509 | intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL); |
6edee7f3 BW |
4510 | } |
4511 | ||
79f5b2c7 | 4512 | static void gen6_enable_rps(struct drm_device *dev) |
2b4e57bd | 4513 | { |
79f5b2c7 | 4514 | struct drm_i915_private *dev_priv = dev->dev_private; |
a4872ba6 | 4515 | struct intel_engine_cs *ring; |
d060c169 | 4516 | u32 rc6vids, pcu_mbox = 0, rc6_mask = 0; |
2b4e57bd | 4517 | u32 gtfifodbg; |
2b4e57bd | 4518 | int rc6_mode; |
42c0526c | 4519 | int i, ret; |
2b4e57bd | 4520 | |
4fc688ce | 4521 | WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock)); |
79f5b2c7 | 4522 | |
2b4e57bd ED |
4523 | /* Here begins a magic sequence of register writes to enable |
4524 | * auto-downclocking. | |
4525 | * | |
4526 | * Perhaps there might be some value in exposing these to | |
4527 | * userspace... | |
4528 | */ | |
4529 | I915_WRITE(GEN6_RC_STATE, 0); | |
2b4e57bd ED |
4530 | |
4531 | /* Clear the DBG now so we don't confuse earlier errors */ | |
4532 | if ((gtfifodbg = I915_READ(GTFIFODBG))) { | |
4533 | DRM_ERROR("GT fifo had a previous error %x\n", gtfifodbg); | |
4534 | I915_WRITE(GTFIFODBG, gtfifodbg); | |
4535 | } | |
4536 | ||
59bad947 | 4537 | intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL); |
2b4e57bd | 4538 | |
93ee2920 TR |
4539 | /* Initialize rps frequencies */ |
4540 | gen6_init_rps_frequencies(dev); | |
dd0a1aa1 | 4541 | |
2b4e57bd ED |
4542 | /* disable the counters and set deterministic thresholds */ |
4543 | I915_WRITE(GEN6_RC_CONTROL, 0); | |
4544 | ||
4545 | I915_WRITE(GEN6_RC1_WAKE_RATE_LIMIT, 1000 << 16); | |
4546 | I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16 | 30); | |
4547 | I915_WRITE(GEN6_RC6pp_WAKE_RATE_LIMIT, 30); | |
4548 | I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); | |
4549 | I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); | |
4550 | ||
b4519513 CW |
4551 | for_each_ring(ring, dev_priv, i) |
4552 | I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10); | |
2b4e57bd ED |
4553 | |
4554 | I915_WRITE(GEN6_RC_SLEEP, 0); | |
4555 | I915_WRITE(GEN6_RC1e_THRESHOLD, 1000); | |
29c78f60 | 4556 | if (IS_IVYBRIDGE(dev)) |
351aa566 SM |
4557 | I915_WRITE(GEN6_RC6_THRESHOLD, 125000); |
4558 | else | |
4559 | I915_WRITE(GEN6_RC6_THRESHOLD, 50000); | |
0920a487 | 4560 | I915_WRITE(GEN6_RC6p_THRESHOLD, 150000); |
2b4e57bd ED |
4561 | I915_WRITE(GEN6_RC6pp_THRESHOLD, 64000); /* unused */ |
4562 | ||
5a7dc92a | 4563 | /* Check if we are enabling RC6 */ |
2b4e57bd ED |
4564 | rc6_mode = intel_enable_rc6(dev_priv->dev); |
4565 | if (rc6_mode & INTEL_RC6_ENABLE) | |
4566 | rc6_mask |= GEN6_RC_CTL_RC6_ENABLE; | |
4567 | ||
5a7dc92a ED |
4568 | /* We don't use those on Haswell */ |
4569 | if (!IS_HASWELL(dev)) { | |
4570 | if (rc6_mode & INTEL_RC6p_ENABLE) | |
4571 | rc6_mask |= GEN6_RC_CTL_RC6p_ENABLE; | |
2b4e57bd | 4572 | |
5a7dc92a ED |
4573 | if (rc6_mode & INTEL_RC6pp_ENABLE) |
4574 | rc6_mask |= GEN6_RC_CTL_RC6pp_ENABLE; | |
4575 | } | |
2b4e57bd | 4576 | |
dc39fff7 | 4577 | intel_print_rc6_info(dev, rc6_mask); |
2b4e57bd ED |
4578 | |
4579 | I915_WRITE(GEN6_RC_CONTROL, | |
4580 | rc6_mask | | |
4581 | GEN6_RC_CTL_EI_MODE(1) | | |
4582 | GEN6_RC_CTL_HW_ENABLE); | |
4583 | ||
dd75fdc8 CW |
4584 | /* Power down if completely idle for over 50ms */ |
4585 | I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 50000); | |
2b4e57bd | 4586 | I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10); |
2b4e57bd | 4587 | |
42c0526c | 4588 | ret = sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_MIN_FREQ_TABLE, 0); |
d060c169 | 4589 | if (ret) |
42c0526c | 4590 | DRM_DEBUG_DRIVER("Failed to set the min frequency\n"); |
d060c169 BW |
4591 | |
4592 | ret = sandybridge_pcode_read(dev_priv, GEN6_READ_OC_PARAMS, &pcu_mbox); | |
4593 | if (!ret && (pcu_mbox & (1<<31))) { /* OC supported */ | |
4594 | DRM_DEBUG_DRIVER("Overclocking supported. Max: %dMHz, Overclock max: %dMHz\n", | |
b39fb297 | 4595 | (dev_priv->rps.max_freq_softlimit & 0xff) * 50, |
d060c169 | 4596 | (pcu_mbox & 0xff) * 50); |
b39fb297 | 4597 | dev_priv->rps.max_freq = pcu_mbox & 0xff; |
2b4e57bd ED |
4598 | } |
4599 | ||
dd75fdc8 | 4600 | dev_priv->rps.power = HIGH_POWER; /* force a reset */ |
aed242ff | 4601 | gen6_set_rps(dev_priv->dev, dev_priv->rps.idle_freq); |
2b4e57bd | 4602 | |
31643d54 BW |
4603 | rc6vids = 0; |
4604 | ret = sandybridge_pcode_read(dev_priv, GEN6_PCODE_READ_RC6VIDS, &rc6vids); | |
4605 | if (IS_GEN6(dev) && ret) { | |
4606 | DRM_DEBUG_DRIVER("Couldn't check for BIOS workaround\n"); | |
4607 | } else if (IS_GEN6(dev) && (GEN6_DECODE_RC6_VID(rc6vids & 0xff) < 450)) { | |
4608 | DRM_DEBUG_DRIVER("You should update your BIOS. Correcting minimum rc6 voltage (%dmV->%dmV)\n", | |
4609 | GEN6_DECODE_RC6_VID(rc6vids & 0xff), 450); | |
4610 | rc6vids &= 0xffff00; | |
4611 | rc6vids |= GEN6_ENCODE_RC6_VID(450); | |
4612 | ret = sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_RC6VIDS, rc6vids); | |
4613 | if (ret) | |
4614 | DRM_ERROR("Couldn't fix incorrect rc6 voltage\n"); | |
4615 | } | |
4616 | ||
59bad947 | 4617 | intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL); |
2b4e57bd ED |
4618 | } |
4619 | ||
c2bc2fc5 | 4620 | static void __gen6_update_ring_freq(struct drm_device *dev) |
2b4e57bd | 4621 | { |
79f5b2c7 | 4622 | struct drm_i915_private *dev_priv = dev->dev_private; |
2b4e57bd | 4623 | int min_freq = 15; |
3ebecd07 CW |
4624 | unsigned int gpu_freq; |
4625 | unsigned int max_ia_freq, min_ring_freq; | |
2b4e57bd | 4626 | int scaling_factor = 180; |
eda79642 | 4627 | struct cpufreq_policy *policy; |
2b4e57bd | 4628 | |
4fc688ce | 4629 | WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock)); |
79f5b2c7 | 4630 | |
eda79642 BW |
4631 | policy = cpufreq_cpu_get(0); |
4632 | if (policy) { | |
4633 | max_ia_freq = policy->cpuinfo.max_freq; | |
4634 | cpufreq_cpu_put(policy); | |
4635 | } else { | |
4636 | /* | |
4637 | * Default to measured freq if none found, PCU will ensure we | |
4638 | * don't go over | |
4639 | */ | |
2b4e57bd | 4640 | max_ia_freq = tsc_khz; |
eda79642 | 4641 | } |
2b4e57bd ED |
4642 | |
4643 | /* Convert from kHz to MHz */ | |
4644 | max_ia_freq /= 1000; | |
4645 | ||
153b4b95 | 4646 | min_ring_freq = I915_READ(DCLK) & 0xf; |
f6aca45c BW |
4647 | /* convert DDR frequency from units of 266.6MHz to bandwidth */ |
4648 | min_ring_freq = mult_frac(min_ring_freq, 8, 3); | |
3ebecd07 | 4649 | |
2b4e57bd ED |
4650 | /* |
4651 | * For each potential GPU frequency, load a ring frequency we'd like | |
4652 | * to use for memory access. We do this by specifying the IA frequency | |
4653 | * the PCU should use as a reference to determine the ring frequency. | |
4654 | */ | |
6985b352 | 4655 | for (gpu_freq = dev_priv->rps.max_freq; gpu_freq >= dev_priv->rps.min_freq; |
2b4e57bd | 4656 | gpu_freq--) { |
6985b352 | 4657 | int diff = dev_priv->rps.max_freq - gpu_freq; |
3ebecd07 CW |
4658 | unsigned int ia_freq = 0, ring_freq = 0; |
4659 | ||
46c764d4 BW |
4660 | if (INTEL_INFO(dev)->gen >= 8) { |
4661 | /* max(2 * GT, DDR). NB: GT is 50MHz units */ | |
4662 | ring_freq = max(min_ring_freq, gpu_freq); | |
4663 | } else if (IS_HASWELL(dev)) { | |
f6aca45c | 4664 | ring_freq = mult_frac(gpu_freq, 5, 4); |
3ebecd07 CW |
4665 | ring_freq = max(min_ring_freq, ring_freq); |
4666 | /* leave ia_freq as the default, chosen by cpufreq */ | |
4667 | } else { | |
4668 | /* On older processors, there is no separate ring | |
4669 | * clock domain, so in order to boost the bandwidth | |
4670 | * of the ring, we need to upclock the CPU (ia_freq). | |
4671 | * | |
4672 | * For GPU frequencies less than 750MHz, | |
4673 | * just use the lowest ring freq. | |
4674 | */ | |
4675 | if (gpu_freq < min_freq) | |
4676 | ia_freq = 800; | |
4677 | else | |
4678 | ia_freq = max_ia_freq - ((diff * scaling_factor) / 2); | |
4679 | ia_freq = DIV_ROUND_CLOSEST(ia_freq, 100); | |
4680 | } | |
2b4e57bd | 4681 | |
42c0526c BW |
4682 | sandybridge_pcode_write(dev_priv, |
4683 | GEN6_PCODE_WRITE_MIN_FREQ_TABLE, | |
3ebecd07 CW |
4684 | ia_freq << GEN6_PCODE_FREQ_IA_RATIO_SHIFT | |
4685 | ring_freq << GEN6_PCODE_FREQ_RING_RATIO_SHIFT | | |
4686 | gpu_freq); | |
2b4e57bd | 4687 | } |
2b4e57bd ED |
4688 | } |
4689 | ||
c2bc2fc5 ID |
4690 | void gen6_update_ring_freq(struct drm_device *dev) |
4691 | { | |
4692 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4693 | ||
4694 | if (INTEL_INFO(dev)->gen < 6 || IS_VALLEYVIEW(dev)) | |
4695 | return; | |
4696 | ||
4697 | mutex_lock(&dev_priv->rps.hw_lock); | |
4698 | __gen6_update_ring_freq(dev); | |
4699 | mutex_unlock(&dev_priv->rps.hw_lock); | |
4700 | } | |
4701 | ||
03af2045 | 4702 | static int cherryview_rps_max_freq(struct drm_i915_private *dev_priv) |
2b6b3a09 | 4703 | { |
095acd5f | 4704 | struct drm_device *dev = dev_priv->dev; |
2b6b3a09 D |
4705 | u32 val, rp0; |
4706 | ||
095acd5f D |
4707 | if (dev->pdev->revision >= 0x20) { |
4708 | val = vlv_punit_read(dev_priv, FB_GFX_FMAX_AT_VMAX_FUSE); | |
2b6b3a09 | 4709 | |
095acd5f D |
4710 | switch (INTEL_INFO(dev)->eu_total) { |
4711 | case 8: | |
4712 | /* (2 * 4) config */ | |
4713 | rp0 = (val >> FB_GFX_FMAX_AT_VMAX_2SS4EU_FUSE_SHIFT); | |
4714 | break; | |
4715 | case 12: | |
4716 | /* (2 * 6) config */ | |
4717 | rp0 = (val >> FB_GFX_FMAX_AT_VMAX_2SS6EU_FUSE_SHIFT); | |
4718 | break; | |
4719 | case 16: | |
4720 | /* (2 * 8) config */ | |
4721 | default: | |
4722 | /* Setting (2 * 8) Min RP0 for any other combination */ | |
4723 | rp0 = (val >> FB_GFX_FMAX_AT_VMAX_2SS8EU_FUSE_SHIFT); | |
4724 | break; | |
4725 | } | |
4726 | rp0 = (rp0 & FB_GFX_FREQ_FUSE_MASK); | |
4727 | } else { | |
4728 | /* For pre-production hardware */ | |
4729 | val = vlv_punit_read(dev_priv, PUNIT_GPU_STATUS_REG); | |
4730 | rp0 = (val >> PUNIT_GPU_STATUS_MAX_FREQ_SHIFT) & | |
4731 | PUNIT_GPU_STATUS_MAX_FREQ_MASK; | |
4732 | } | |
2b6b3a09 D |
4733 | return rp0; |
4734 | } | |
4735 | ||
4736 | static int cherryview_rps_rpe_freq(struct drm_i915_private *dev_priv) | |
4737 | { | |
4738 | u32 val, rpe; | |
4739 | ||
4740 | val = vlv_punit_read(dev_priv, PUNIT_GPU_DUTYCYCLE_REG); | |
4741 | rpe = (val >> PUNIT_GPU_DUTYCYCLE_RPE_FREQ_SHIFT) & PUNIT_GPU_DUTYCYCLE_RPE_FREQ_MASK; | |
4742 | ||
4743 | return rpe; | |
4744 | } | |
4745 | ||
7707df4a D |
4746 | static int cherryview_rps_guar_freq(struct drm_i915_private *dev_priv) |
4747 | { | |
095acd5f | 4748 | struct drm_device *dev = dev_priv->dev; |
7707df4a D |
4749 | u32 val, rp1; |
4750 | ||
095acd5f D |
4751 | if (dev->pdev->revision >= 0x20) { |
4752 | val = vlv_punit_read(dev_priv, FB_GFX_FMAX_AT_VMAX_FUSE); | |
4753 | rp1 = (val & FB_GFX_FREQ_FUSE_MASK); | |
4754 | } else { | |
4755 | /* For pre-production hardware */ | |
4756 | val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS); | |
4757 | rp1 = ((val >> PUNIT_GPU_STATUS_MAX_FREQ_SHIFT) & | |
4758 | PUNIT_GPU_STATUS_MAX_FREQ_MASK); | |
4759 | } | |
7707df4a D |
4760 | return rp1; |
4761 | } | |
4762 | ||
f8f2b001 D |
4763 | static int valleyview_rps_guar_freq(struct drm_i915_private *dev_priv) |
4764 | { | |
4765 | u32 val, rp1; | |
4766 | ||
4767 | val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FREQ_FUSE); | |
4768 | ||
4769 | rp1 = (val & FB_GFX_FGUARANTEED_FREQ_FUSE_MASK) >> FB_GFX_FGUARANTEED_FREQ_FUSE_SHIFT; | |
4770 | ||
4771 | return rp1; | |
4772 | } | |
4773 | ||
03af2045 | 4774 | static int valleyview_rps_max_freq(struct drm_i915_private *dev_priv) |
0a073b84 JB |
4775 | { |
4776 | u32 val, rp0; | |
4777 | ||
64936258 | 4778 | val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FREQ_FUSE); |
0a073b84 JB |
4779 | |
4780 | rp0 = (val & FB_GFX_MAX_FREQ_FUSE_MASK) >> FB_GFX_MAX_FREQ_FUSE_SHIFT; | |
4781 | /* Clamp to max */ | |
4782 | rp0 = min_t(u32, rp0, 0xea); | |
4783 | ||
4784 | return rp0; | |
4785 | } | |
4786 | ||
4787 | static int valleyview_rps_rpe_freq(struct drm_i915_private *dev_priv) | |
4788 | { | |
4789 | u32 val, rpe; | |
4790 | ||
64936258 | 4791 | val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FMAX_FUSE_LO); |
0a073b84 | 4792 | rpe = (val & FB_FMAX_VMIN_FREQ_LO_MASK) >> FB_FMAX_VMIN_FREQ_LO_SHIFT; |
64936258 | 4793 | val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FMAX_FUSE_HI); |
0a073b84 JB |
4794 | rpe |= (val & FB_FMAX_VMIN_FREQ_HI_MASK) << 5; |
4795 | ||
4796 | return rpe; | |
4797 | } | |
4798 | ||
03af2045 | 4799 | static int valleyview_rps_min_freq(struct drm_i915_private *dev_priv) |
0a073b84 | 4800 | { |
64936258 | 4801 | return vlv_punit_read(dev_priv, PUNIT_REG_GPU_LFM) & 0xff; |
0a073b84 JB |
4802 | } |
4803 | ||
ae48434c ID |
4804 | /* Check that the pctx buffer wasn't move under us. */ |
4805 | static void valleyview_check_pctx(struct drm_i915_private *dev_priv) | |
4806 | { | |
4807 | unsigned long pctx_addr = I915_READ(VLV_PCBR) & ~4095; | |
4808 | ||
4809 | WARN_ON(pctx_addr != dev_priv->mm.stolen_base + | |
4810 | dev_priv->vlv_pctx->stolen->start); | |
4811 | } | |
4812 | ||
38807746 D |
4813 | |
4814 | /* Check that the pcbr address is not empty. */ | |
4815 | static void cherryview_check_pctx(struct drm_i915_private *dev_priv) | |
4816 | { | |
4817 | unsigned long pctx_addr = I915_READ(VLV_PCBR) & ~4095; | |
4818 | ||
4819 | WARN_ON((pctx_addr >> VLV_PCBR_ADDR_SHIFT) == 0); | |
4820 | } | |
4821 | ||
4822 | static void cherryview_setup_pctx(struct drm_device *dev) | |
4823 | { | |
4824 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4825 | unsigned long pctx_paddr, paddr; | |
4826 | struct i915_gtt *gtt = &dev_priv->gtt; | |
4827 | u32 pcbr; | |
4828 | int pctx_size = 32*1024; | |
4829 | ||
4830 | WARN_ON(!mutex_is_locked(&dev->struct_mutex)); | |
4831 | ||
4832 | pcbr = I915_READ(VLV_PCBR); | |
4833 | if ((pcbr >> VLV_PCBR_ADDR_SHIFT) == 0) { | |
ce611ef8 | 4834 | DRM_DEBUG_DRIVER("BIOS didn't set up PCBR, fixing up\n"); |
38807746 D |
4835 | paddr = (dev_priv->mm.stolen_base + |
4836 | (gtt->stolen_size - pctx_size)); | |
4837 | ||
4838 | pctx_paddr = (paddr & (~4095)); | |
4839 | I915_WRITE(VLV_PCBR, pctx_paddr); | |
4840 | } | |
ce611ef8 VS |
4841 | |
4842 | DRM_DEBUG_DRIVER("PCBR: 0x%08x\n", I915_READ(VLV_PCBR)); | |
38807746 D |
4843 | } |
4844 | ||
c9cddffc JB |
4845 | static void valleyview_setup_pctx(struct drm_device *dev) |
4846 | { | |
4847 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4848 | struct drm_i915_gem_object *pctx; | |
4849 | unsigned long pctx_paddr; | |
4850 | u32 pcbr; | |
4851 | int pctx_size = 24*1024; | |
4852 | ||
17b0c1f7 ID |
4853 | WARN_ON(!mutex_is_locked(&dev->struct_mutex)); |
4854 | ||
c9cddffc JB |
4855 | pcbr = I915_READ(VLV_PCBR); |
4856 | if (pcbr) { | |
4857 | /* BIOS set it up already, grab the pre-alloc'd space */ | |
4858 | int pcbr_offset; | |
4859 | ||
4860 | pcbr_offset = (pcbr & (~4095)) - dev_priv->mm.stolen_base; | |
4861 | pctx = i915_gem_object_create_stolen_for_preallocated(dev_priv->dev, | |
4862 | pcbr_offset, | |
190d6cd5 | 4863 | I915_GTT_OFFSET_NONE, |
c9cddffc JB |
4864 | pctx_size); |
4865 | goto out; | |
4866 | } | |
4867 | ||
ce611ef8 VS |
4868 | DRM_DEBUG_DRIVER("BIOS didn't set up PCBR, fixing up\n"); |
4869 | ||
c9cddffc JB |
4870 | /* |
4871 | * From the Gunit register HAS: | |
4872 | * The Gfx driver is expected to program this register and ensure | |
4873 | * proper allocation within Gfx stolen memory. For example, this | |
4874 | * register should be programmed such than the PCBR range does not | |
4875 | * overlap with other ranges, such as the frame buffer, protected | |
4876 | * memory, or any other relevant ranges. | |
4877 | */ | |
4878 | pctx = i915_gem_object_create_stolen(dev, pctx_size); | |
4879 | if (!pctx) { | |
4880 | DRM_DEBUG("not enough stolen space for PCTX, disabling\n"); | |
4881 | return; | |
4882 | } | |
4883 | ||
4884 | pctx_paddr = dev_priv->mm.stolen_base + pctx->stolen->start; | |
4885 | I915_WRITE(VLV_PCBR, pctx_paddr); | |
4886 | ||
4887 | out: | |
ce611ef8 | 4888 | DRM_DEBUG_DRIVER("PCBR: 0x%08x\n", I915_READ(VLV_PCBR)); |
c9cddffc JB |
4889 | dev_priv->vlv_pctx = pctx; |
4890 | } | |
4891 | ||
ae48434c ID |
4892 | static void valleyview_cleanup_pctx(struct drm_device *dev) |
4893 | { | |
4894 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4895 | ||
4896 | if (WARN_ON(!dev_priv->vlv_pctx)) | |
4897 | return; | |
4898 | ||
4899 | drm_gem_object_unreference(&dev_priv->vlv_pctx->base); | |
4900 | dev_priv->vlv_pctx = NULL; | |
4901 | } | |
4902 | ||
4e80519e ID |
4903 | static void valleyview_init_gt_powersave(struct drm_device *dev) |
4904 | { | |
4905 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2bb25c17 | 4906 | u32 val; |
4e80519e ID |
4907 | |
4908 | valleyview_setup_pctx(dev); | |
4909 | ||
4910 | mutex_lock(&dev_priv->rps.hw_lock); | |
4911 | ||
2bb25c17 VS |
4912 | val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS); |
4913 | switch ((val >> 6) & 3) { | |
4914 | case 0: | |
4915 | case 1: | |
4916 | dev_priv->mem_freq = 800; | |
4917 | break; | |
4918 | case 2: | |
4919 | dev_priv->mem_freq = 1066; | |
4920 | break; | |
4921 | case 3: | |
4922 | dev_priv->mem_freq = 1333; | |
4923 | break; | |
4924 | } | |
80b83b62 | 4925 | DRM_DEBUG_DRIVER("DDR speed: %d MHz\n", dev_priv->mem_freq); |
2bb25c17 | 4926 | |
4e80519e ID |
4927 | dev_priv->rps.max_freq = valleyview_rps_max_freq(dev_priv); |
4928 | dev_priv->rps.rp0_freq = dev_priv->rps.max_freq; | |
4929 | DRM_DEBUG_DRIVER("max GPU freq: %d MHz (%u)\n", | |
7c59a9c1 | 4930 | intel_gpu_freq(dev_priv, dev_priv->rps.max_freq), |
4e80519e ID |
4931 | dev_priv->rps.max_freq); |
4932 | ||
4933 | dev_priv->rps.efficient_freq = valleyview_rps_rpe_freq(dev_priv); | |
4934 | DRM_DEBUG_DRIVER("RPe GPU freq: %d MHz (%u)\n", | |
7c59a9c1 | 4935 | intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq), |
4e80519e ID |
4936 | dev_priv->rps.efficient_freq); |
4937 | ||
f8f2b001 D |
4938 | dev_priv->rps.rp1_freq = valleyview_rps_guar_freq(dev_priv); |
4939 | DRM_DEBUG_DRIVER("RP1(Guar Freq) GPU freq: %d MHz (%u)\n", | |
7c59a9c1 | 4940 | intel_gpu_freq(dev_priv, dev_priv->rps.rp1_freq), |
f8f2b001 D |
4941 | dev_priv->rps.rp1_freq); |
4942 | ||
4e80519e ID |
4943 | dev_priv->rps.min_freq = valleyview_rps_min_freq(dev_priv); |
4944 | DRM_DEBUG_DRIVER("min GPU freq: %d MHz (%u)\n", | |
7c59a9c1 | 4945 | intel_gpu_freq(dev_priv, dev_priv->rps.min_freq), |
4e80519e ID |
4946 | dev_priv->rps.min_freq); |
4947 | ||
aed242ff CW |
4948 | dev_priv->rps.idle_freq = dev_priv->rps.min_freq; |
4949 | ||
4e80519e ID |
4950 | /* Preserve min/max settings in case of re-init */ |
4951 | if (dev_priv->rps.max_freq_softlimit == 0) | |
4952 | dev_priv->rps.max_freq_softlimit = dev_priv->rps.max_freq; | |
4953 | ||
4954 | if (dev_priv->rps.min_freq_softlimit == 0) | |
4955 | dev_priv->rps.min_freq_softlimit = dev_priv->rps.min_freq; | |
4956 | ||
4957 | mutex_unlock(&dev_priv->rps.hw_lock); | |
4958 | } | |
4959 | ||
38807746 D |
4960 | static void cherryview_init_gt_powersave(struct drm_device *dev) |
4961 | { | |
2b6b3a09 | 4962 | struct drm_i915_private *dev_priv = dev->dev_private; |
2bb25c17 | 4963 | u32 val; |
2b6b3a09 | 4964 | |
38807746 | 4965 | cherryview_setup_pctx(dev); |
2b6b3a09 D |
4966 | |
4967 | mutex_lock(&dev_priv->rps.hw_lock); | |
4968 | ||
a580516d | 4969 | mutex_lock(&dev_priv->sb_lock); |
c6e8f39d | 4970 | val = vlv_cck_read(dev_priv, CCK_FUSE_REG); |
a580516d | 4971 | mutex_unlock(&dev_priv->sb_lock); |
c6e8f39d | 4972 | |
2bb25c17 VS |
4973 | switch ((val >> 2) & 0x7) { |
4974 | case 0: | |
4975 | case 1: | |
4976 | dev_priv->rps.cz_freq = 200; | |
4977 | dev_priv->mem_freq = 1600; | |
4978 | break; | |
4979 | case 2: | |
4980 | dev_priv->rps.cz_freq = 267; | |
4981 | dev_priv->mem_freq = 1600; | |
4982 | break; | |
4983 | case 3: | |
4984 | dev_priv->rps.cz_freq = 333; | |
4985 | dev_priv->mem_freq = 2000; | |
4986 | break; | |
4987 | case 4: | |
4988 | dev_priv->rps.cz_freq = 320; | |
4989 | dev_priv->mem_freq = 1600; | |
4990 | break; | |
4991 | case 5: | |
4992 | dev_priv->rps.cz_freq = 400; | |
4993 | dev_priv->mem_freq = 1600; | |
4994 | break; | |
4995 | } | |
80b83b62 | 4996 | DRM_DEBUG_DRIVER("DDR speed: %d MHz\n", dev_priv->mem_freq); |
2bb25c17 | 4997 | |
2b6b3a09 D |
4998 | dev_priv->rps.max_freq = cherryview_rps_max_freq(dev_priv); |
4999 | dev_priv->rps.rp0_freq = dev_priv->rps.max_freq; | |
5000 | DRM_DEBUG_DRIVER("max GPU freq: %d MHz (%u)\n", | |
7c59a9c1 | 5001 | intel_gpu_freq(dev_priv, dev_priv->rps.max_freq), |
2b6b3a09 D |
5002 | dev_priv->rps.max_freq); |
5003 | ||
5004 | dev_priv->rps.efficient_freq = cherryview_rps_rpe_freq(dev_priv); | |
5005 | DRM_DEBUG_DRIVER("RPe GPU freq: %d MHz (%u)\n", | |
7c59a9c1 | 5006 | intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq), |
2b6b3a09 D |
5007 | dev_priv->rps.efficient_freq); |
5008 | ||
7707df4a D |
5009 | dev_priv->rps.rp1_freq = cherryview_rps_guar_freq(dev_priv); |
5010 | DRM_DEBUG_DRIVER("RP1(Guar) GPU freq: %d MHz (%u)\n", | |
7c59a9c1 | 5011 | intel_gpu_freq(dev_priv, dev_priv->rps.rp1_freq), |
7707df4a D |
5012 | dev_priv->rps.rp1_freq); |
5013 | ||
5b7c91b7 D |
5014 | /* PUnit validated range is only [RPe, RP0] */ |
5015 | dev_priv->rps.min_freq = dev_priv->rps.efficient_freq; | |
2b6b3a09 | 5016 | DRM_DEBUG_DRIVER("min GPU freq: %d MHz (%u)\n", |
7c59a9c1 | 5017 | intel_gpu_freq(dev_priv, dev_priv->rps.min_freq), |
2b6b3a09 D |
5018 | dev_priv->rps.min_freq); |
5019 | ||
1c14762d VS |
5020 | WARN_ONCE((dev_priv->rps.max_freq | |
5021 | dev_priv->rps.efficient_freq | | |
5022 | dev_priv->rps.rp1_freq | | |
5023 | dev_priv->rps.min_freq) & 1, | |
5024 | "Odd GPU freq values\n"); | |
5025 | ||
aed242ff CW |
5026 | dev_priv->rps.idle_freq = dev_priv->rps.min_freq; |
5027 | ||
2b6b3a09 D |
5028 | /* Preserve min/max settings in case of re-init */ |
5029 | if (dev_priv->rps.max_freq_softlimit == 0) | |
5030 | dev_priv->rps.max_freq_softlimit = dev_priv->rps.max_freq; | |
5031 | ||
5032 | if (dev_priv->rps.min_freq_softlimit == 0) | |
5033 | dev_priv->rps.min_freq_softlimit = dev_priv->rps.min_freq; | |
5034 | ||
5035 | mutex_unlock(&dev_priv->rps.hw_lock); | |
38807746 D |
5036 | } |
5037 | ||
4e80519e ID |
5038 | static void valleyview_cleanup_gt_powersave(struct drm_device *dev) |
5039 | { | |
5040 | valleyview_cleanup_pctx(dev); | |
5041 | } | |
5042 | ||
38807746 D |
5043 | static void cherryview_enable_rps(struct drm_device *dev) |
5044 | { | |
5045 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5046 | struct intel_engine_cs *ring; | |
2b6b3a09 | 5047 | u32 gtfifodbg, val, rc6_mode = 0, pcbr; |
38807746 D |
5048 | int i; |
5049 | ||
5050 | WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock)); | |
5051 | ||
5052 | gtfifodbg = I915_READ(GTFIFODBG); | |
5053 | if (gtfifodbg) { | |
5054 | DRM_DEBUG_DRIVER("GT fifo had a previous error %x\n", | |
5055 | gtfifodbg); | |
5056 | I915_WRITE(GTFIFODBG, gtfifodbg); | |
5057 | } | |
5058 | ||
5059 | cherryview_check_pctx(dev_priv); | |
5060 | ||
5061 | /* 1a & 1b: Get forcewake during program sequence. Although the driver | |
5062 | * hasn't enabled a state yet where we need forcewake, BIOS may have.*/ | |
59bad947 | 5063 | intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL); |
38807746 | 5064 | |
160614a2 VS |
5065 | /* Disable RC states. */ |
5066 | I915_WRITE(GEN6_RC_CONTROL, 0); | |
5067 | ||
38807746 D |
5068 | /* 2a: Program RC6 thresholds.*/ |
5069 | I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16); | |
5070 | I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */ | |
5071 | I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */ | |
5072 | ||
5073 | for_each_ring(ring, dev_priv, i) | |
5074 | I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10); | |
5075 | I915_WRITE(GEN6_RC_SLEEP, 0); | |
5076 | ||
f4f71c7d D |
5077 | /* TO threshold set to 500 us ( 0x186 * 1.28 us) */ |
5078 | I915_WRITE(GEN6_RC6_THRESHOLD, 0x186); | |
38807746 D |
5079 | |
5080 | /* allows RC6 residency counter to work */ | |
5081 | I915_WRITE(VLV_COUNTER_CONTROL, | |
5082 | _MASKED_BIT_ENABLE(VLV_COUNT_RANGE_HIGH | | |
5083 | VLV_MEDIA_RC6_COUNT_EN | | |
5084 | VLV_RENDER_RC6_COUNT_EN)); | |
5085 | ||
5086 | /* For now we assume BIOS is allocating and populating the PCBR */ | |
5087 | pcbr = I915_READ(VLV_PCBR); | |
5088 | ||
38807746 D |
5089 | /* 3: Enable RC6 */ |
5090 | if ((intel_enable_rc6(dev) & INTEL_RC6_ENABLE) && | |
5091 | (pcbr >> VLV_PCBR_ADDR_SHIFT)) | |
af5a75a3 | 5092 | rc6_mode = GEN7_RC_CTL_TO_MODE; |
38807746 D |
5093 | |
5094 | I915_WRITE(GEN6_RC_CONTROL, rc6_mode); | |
5095 | ||
2b6b3a09 | 5096 | /* 4 Program defaults and thresholds for RPS*/ |
3cbdb48f | 5097 | I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 1000000); |
2b6b3a09 D |
5098 | I915_WRITE(GEN6_RP_UP_THRESHOLD, 59400); |
5099 | I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 245000); | |
5100 | I915_WRITE(GEN6_RP_UP_EI, 66000); | |
5101 | I915_WRITE(GEN6_RP_DOWN_EI, 350000); | |
5102 | ||
5103 | I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10); | |
5104 | ||
5105 | /* 5: Enable RPS */ | |
5106 | I915_WRITE(GEN6_RP_CONTROL, | |
5107 | GEN6_RP_MEDIA_HW_NORMAL_MODE | | |
eb973a5e | 5108 | GEN6_RP_MEDIA_IS_GFX | |
2b6b3a09 D |
5109 | GEN6_RP_ENABLE | |
5110 | GEN6_RP_UP_BUSY_AVG | | |
5111 | GEN6_RP_DOWN_IDLE_AVG); | |
5112 | ||
3ef62342 D |
5113 | /* Setting Fixed Bias */ |
5114 | val = VLV_OVERRIDE_EN | | |
5115 | VLV_SOC_TDP_EN | | |
5116 | CHV_BIAS_CPU_50_SOC_50; | |
5117 | vlv_punit_write(dev_priv, VLV_TURBO_SOC_OVERRIDE, val); | |
5118 | ||
2b6b3a09 D |
5119 | val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS); |
5120 | ||
8d40c3ae VS |
5121 | /* RPS code assumes GPLL is used */ |
5122 | WARN_ONCE((val & GPLLENABLE) == 0, "GPLL not enabled\n"); | |
5123 | ||
c8e9627d | 5124 | DRM_DEBUG_DRIVER("GPLL enabled? %s\n", val & GPLLENABLE ? "yes" : "no"); |
2b6b3a09 D |
5125 | DRM_DEBUG_DRIVER("GPU status: 0x%08x\n", val); |
5126 | ||
5127 | dev_priv->rps.cur_freq = (val >> 8) & 0xff; | |
5128 | DRM_DEBUG_DRIVER("current GPU freq: %d MHz (%u)\n", | |
7c59a9c1 | 5129 | intel_gpu_freq(dev_priv, dev_priv->rps.cur_freq), |
2b6b3a09 D |
5130 | dev_priv->rps.cur_freq); |
5131 | ||
5132 | DRM_DEBUG_DRIVER("setting GPU freq to %d MHz (%u)\n", | |
7c59a9c1 | 5133 | intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq), |
2b6b3a09 D |
5134 | dev_priv->rps.efficient_freq); |
5135 | ||
5136 | valleyview_set_rps(dev_priv->dev, dev_priv->rps.efficient_freq); | |
5137 | ||
59bad947 | 5138 | intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL); |
38807746 D |
5139 | } |
5140 | ||
0a073b84 JB |
5141 | static void valleyview_enable_rps(struct drm_device *dev) |
5142 | { | |
5143 | struct drm_i915_private *dev_priv = dev->dev_private; | |
a4872ba6 | 5144 | struct intel_engine_cs *ring; |
2a5913a8 | 5145 | u32 gtfifodbg, val, rc6_mode = 0; |
0a073b84 JB |
5146 | int i; |
5147 | ||
5148 | WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock)); | |
5149 | ||
ae48434c ID |
5150 | valleyview_check_pctx(dev_priv); |
5151 | ||
0a073b84 | 5152 | if ((gtfifodbg = I915_READ(GTFIFODBG))) { |
f7d85c1e JB |
5153 | DRM_DEBUG_DRIVER("GT fifo had a previous error %x\n", |
5154 | gtfifodbg); | |
0a073b84 JB |
5155 | I915_WRITE(GTFIFODBG, gtfifodbg); |
5156 | } | |
5157 | ||
c8d9a590 | 5158 | /* If VLV, Forcewake all wells, else re-direct to regular path */ |
59bad947 | 5159 | intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL); |
0a073b84 | 5160 | |
160614a2 VS |
5161 | /* Disable RC states. */ |
5162 | I915_WRITE(GEN6_RC_CONTROL, 0); | |
5163 | ||
cad725fe | 5164 | I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 1000000); |
0a073b84 JB |
5165 | I915_WRITE(GEN6_RP_UP_THRESHOLD, 59400); |
5166 | I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 245000); | |
5167 | I915_WRITE(GEN6_RP_UP_EI, 66000); | |
5168 | I915_WRITE(GEN6_RP_DOWN_EI, 350000); | |
5169 | ||
5170 | I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10); | |
5171 | ||
5172 | I915_WRITE(GEN6_RP_CONTROL, | |
5173 | GEN6_RP_MEDIA_TURBO | | |
5174 | GEN6_RP_MEDIA_HW_NORMAL_MODE | | |
5175 | GEN6_RP_MEDIA_IS_GFX | | |
5176 | GEN6_RP_ENABLE | | |
5177 | GEN6_RP_UP_BUSY_AVG | | |
5178 | GEN6_RP_DOWN_IDLE_CONT); | |
5179 | ||
5180 | I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 0x00280000); | |
5181 | I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); | |
5182 | I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); | |
5183 | ||
5184 | for_each_ring(ring, dev_priv, i) | |
5185 | I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10); | |
5186 | ||
2f0aa304 | 5187 | I915_WRITE(GEN6_RC6_THRESHOLD, 0x557); |
0a073b84 JB |
5188 | |
5189 | /* allows RC6 residency counter to work */ | |
49798eb2 | 5190 | I915_WRITE(VLV_COUNTER_CONTROL, |
31685c25 D |
5191 | _MASKED_BIT_ENABLE(VLV_MEDIA_RC0_COUNT_EN | |
5192 | VLV_RENDER_RC0_COUNT_EN | | |
49798eb2 JB |
5193 | VLV_MEDIA_RC6_COUNT_EN | |
5194 | VLV_RENDER_RC6_COUNT_EN)); | |
31685c25 | 5195 | |
a2b23fe0 | 5196 | if (intel_enable_rc6(dev) & INTEL_RC6_ENABLE) |
6b88f295 | 5197 | rc6_mode = GEN7_RC_CTL_TO_MODE | VLV_RC_CTL_CTX_RST_PARALLEL; |
dc39fff7 BW |
5198 | |
5199 | intel_print_rc6_info(dev, rc6_mode); | |
5200 | ||
a2b23fe0 | 5201 | I915_WRITE(GEN6_RC_CONTROL, rc6_mode); |
0a073b84 | 5202 | |
3ef62342 D |
5203 | /* Setting Fixed Bias */ |
5204 | val = VLV_OVERRIDE_EN | | |
5205 | VLV_SOC_TDP_EN | | |
5206 | VLV_BIAS_CPU_125_SOC_875; | |
5207 | vlv_punit_write(dev_priv, VLV_TURBO_SOC_OVERRIDE, val); | |
5208 | ||
64936258 | 5209 | val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS); |
0a073b84 | 5210 | |
8d40c3ae VS |
5211 | /* RPS code assumes GPLL is used */ |
5212 | WARN_ONCE((val & GPLLENABLE) == 0, "GPLL not enabled\n"); | |
5213 | ||
c8e9627d | 5214 | DRM_DEBUG_DRIVER("GPLL enabled? %s\n", val & GPLLENABLE ? "yes" : "no"); |
0a073b84 JB |
5215 | DRM_DEBUG_DRIVER("GPU status: 0x%08x\n", val); |
5216 | ||
b39fb297 | 5217 | dev_priv->rps.cur_freq = (val >> 8) & 0xff; |
73008b98 | 5218 | DRM_DEBUG_DRIVER("current GPU freq: %d MHz (%u)\n", |
7c59a9c1 | 5219 | intel_gpu_freq(dev_priv, dev_priv->rps.cur_freq), |
b39fb297 | 5220 | dev_priv->rps.cur_freq); |
0a073b84 | 5221 | |
73008b98 | 5222 | DRM_DEBUG_DRIVER("setting GPU freq to %d MHz (%u)\n", |
7c59a9c1 | 5223 | intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq), |
b39fb297 | 5224 | dev_priv->rps.efficient_freq); |
0a073b84 | 5225 | |
b39fb297 | 5226 | valleyview_set_rps(dev_priv->dev, dev_priv->rps.efficient_freq); |
0a073b84 | 5227 | |
59bad947 | 5228 | intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL); |
0a073b84 JB |
5229 | } |
5230 | ||
dde18883 ED |
5231 | static unsigned long intel_pxfreq(u32 vidfreq) |
5232 | { | |
5233 | unsigned long freq; | |
5234 | int div = (vidfreq & 0x3f0000) >> 16; | |
5235 | int post = (vidfreq & 0x3000) >> 12; | |
5236 | int pre = (vidfreq & 0x7); | |
5237 | ||
5238 | if (!pre) | |
5239 | return 0; | |
5240 | ||
5241 | freq = ((div * 133333) / ((1<<post) * pre)); | |
5242 | ||
5243 | return freq; | |
5244 | } | |
5245 | ||
eb48eb00 DV |
5246 | static const struct cparams { |
5247 | u16 i; | |
5248 | u16 t; | |
5249 | u16 m; | |
5250 | u16 c; | |
5251 | } cparams[] = { | |
5252 | { 1, 1333, 301, 28664 }, | |
5253 | { 1, 1066, 294, 24460 }, | |
5254 | { 1, 800, 294, 25192 }, | |
5255 | { 0, 1333, 276, 27605 }, | |
5256 | { 0, 1066, 276, 27605 }, | |
5257 | { 0, 800, 231, 23784 }, | |
5258 | }; | |
5259 | ||
f531dcb2 | 5260 | static unsigned long __i915_chipset_val(struct drm_i915_private *dev_priv) |
eb48eb00 DV |
5261 | { |
5262 | u64 total_count, diff, ret; | |
5263 | u32 count1, count2, count3, m = 0, c = 0; | |
5264 | unsigned long now = jiffies_to_msecs(jiffies), diff1; | |
5265 | int i; | |
5266 | ||
02d71956 DV |
5267 | assert_spin_locked(&mchdev_lock); |
5268 | ||
20e4d407 | 5269 | diff1 = now - dev_priv->ips.last_time1; |
eb48eb00 DV |
5270 | |
5271 | /* Prevent division-by-zero if we are asking too fast. | |
5272 | * Also, we don't get interesting results if we are polling | |
5273 | * faster than once in 10ms, so just return the saved value | |
5274 | * in such cases. | |
5275 | */ | |
5276 | if (diff1 <= 10) | |
20e4d407 | 5277 | return dev_priv->ips.chipset_power; |
eb48eb00 DV |
5278 | |
5279 | count1 = I915_READ(DMIEC); | |
5280 | count2 = I915_READ(DDREC); | |
5281 | count3 = I915_READ(CSIEC); | |
5282 | ||
5283 | total_count = count1 + count2 + count3; | |
5284 | ||
5285 | /* FIXME: handle per-counter overflow */ | |
20e4d407 DV |
5286 | if (total_count < dev_priv->ips.last_count1) { |
5287 | diff = ~0UL - dev_priv->ips.last_count1; | |
eb48eb00 DV |
5288 | diff += total_count; |
5289 | } else { | |
20e4d407 | 5290 | diff = total_count - dev_priv->ips.last_count1; |
eb48eb00 DV |
5291 | } |
5292 | ||
5293 | for (i = 0; i < ARRAY_SIZE(cparams); i++) { | |
20e4d407 DV |
5294 | if (cparams[i].i == dev_priv->ips.c_m && |
5295 | cparams[i].t == dev_priv->ips.r_t) { | |
eb48eb00 DV |
5296 | m = cparams[i].m; |
5297 | c = cparams[i].c; | |
5298 | break; | |
5299 | } | |
5300 | } | |
5301 | ||
5302 | diff = div_u64(diff, diff1); | |
5303 | ret = ((m * diff) + c); | |
5304 | ret = div_u64(ret, 10); | |
5305 | ||
20e4d407 DV |
5306 | dev_priv->ips.last_count1 = total_count; |
5307 | dev_priv->ips.last_time1 = now; | |
eb48eb00 | 5308 | |
20e4d407 | 5309 | dev_priv->ips.chipset_power = ret; |
eb48eb00 DV |
5310 | |
5311 | return ret; | |
5312 | } | |
5313 | ||
f531dcb2 CW |
5314 | unsigned long i915_chipset_val(struct drm_i915_private *dev_priv) |
5315 | { | |
3d13ef2e | 5316 | struct drm_device *dev = dev_priv->dev; |
f531dcb2 CW |
5317 | unsigned long val; |
5318 | ||
3d13ef2e | 5319 | if (INTEL_INFO(dev)->gen != 5) |
f531dcb2 CW |
5320 | return 0; |
5321 | ||
5322 | spin_lock_irq(&mchdev_lock); | |
5323 | ||
5324 | val = __i915_chipset_val(dev_priv); | |
5325 | ||
5326 | spin_unlock_irq(&mchdev_lock); | |
5327 | ||
5328 | return val; | |
5329 | } | |
5330 | ||
eb48eb00 DV |
5331 | unsigned long i915_mch_val(struct drm_i915_private *dev_priv) |
5332 | { | |
5333 | unsigned long m, x, b; | |
5334 | u32 tsfs; | |
5335 | ||
5336 | tsfs = I915_READ(TSFS); | |
5337 | ||
5338 | m = ((tsfs & TSFS_SLOPE_MASK) >> TSFS_SLOPE_SHIFT); | |
5339 | x = I915_READ8(TR1); | |
5340 | ||
5341 | b = tsfs & TSFS_INTR_MASK; | |
5342 | ||
5343 | return ((m * x) / 127) - b; | |
5344 | } | |
5345 | ||
d972d6ee MK |
5346 | static int _pxvid_to_vd(u8 pxvid) |
5347 | { | |
5348 | if (pxvid == 0) | |
5349 | return 0; | |
5350 | ||
5351 | if (pxvid >= 8 && pxvid < 31) | |
5352 | pxvid = 31; | |
5353 | ||
5354 | return (pxvid + 2) * 125; | |
5355 | } | |
5356 | ||
5357 | static u32 pvid_to_extvid(struct drm_i915_private *dev_priv, u8 pxvid) | |
eb48eb00 | 5358 | { |
3d13ef2e | 5359 | struct drm_device *dev = dev_priv->dev; |
d972d6ee MK |
5360 | const int vd = _pxvid_to_vd(pxvid); |
5361 | const int vm = vd - 1125; | |
5362 | ||
3d13ef2e | 5363 | if (INTEL_INFO(dev)->is_mobile) |
d972d6ee MK |
5364 | return vm > 0 ? vm : 0; |
5365 | ||
5366 | return vd; | |
eb48eb00 DV |
5367 | } |
5368 | ||
02d71956 | 5369 | static void __i915_update_gfx_val(struct drm_i915_private *dev_priv) |
eb48eb00 | 5370 | { |
5ed0bdf2 | 5371 | u64 now, diff, diffms; |
eb48eb00 DV |
5372 | u32 count; |
5373 | ||
02d71956 | 5374 | assert_spin_locked(&mchdev_lock); |
eb48eb00 | 5375 | |
5ed0bdf2 TG |
5376 | now = ktime_get_raw_ns(); |
5377 | diffms = now - dev_priv->ips.last_time2; | |
5378 | do_div(diffms, NSEC_PER_MSEC); | |
eb48eb00 DV |
5379 | |
5380 | /* Don't divide by 0 */ | |
eb48eb00 DV |
5381 | if (!diffms) |
5382 | return; | |
5383 | ||
5384 | count = I915_READ(GFXEC); | |
5385 | ||
20e4d407 DV |
5386 | if (count < dev_priv->ips.last_count2) { |
5387 | diff = ~0UL - dev_priv->ips.last_count2; | |
eb48eb00 DV |
5388 | diff += count; |
5389 | } else { | |
20e4d407 | 5390 | diff = count - dev_priv->ips.last_count2; |
eb48eb00 DV |
5391 | } |
5392 | ||
20e4d407 DV |
5393 | dev_priv->ips.last_count2 = count; |
5394 | dev_priv->ips.last_time2 = now; | |
eb48eb00 DV |
5395 | |
5396 | /* More magic constants... */ | |
5397 | diff = diff * 1181; | |
5398 | diff = div_u64(diff, diffms * 10); | |
20e4d407 | 5399 | dev_priv->ips.gfx_power = diff; |
eb48eb00 DV |
5400 | } |
5401 | ||
02d71956 DV |
5402 | void i915_update_gfx_val(struct drm_i915_private *dev_priv) |
5403 | { | |
3d13ef2e DL |
5404 | struct drm_device *dev = dev_priv->dev; |
5405 | ||
5406 | if (INTEL_INFO(dev)->gen != 5) | |
02d71956 DV |
5407 | return; |
5408 | ||
9270388e | 5409 | spin_lock_irq(&mchdev_lock); |
02d71956 DV |
5410 | |
5411 | __i915_update_gfx_val(dev_priv); | |
5412 | ||
9270388e | 5413 | spin_unlock_irq(&mchdev_lock); |
02d71956 DV |
5414 | } |
5415 | ||
f531dcb2 | 5416 | static unsigned long __i915_gfx_val(struct drm_i915_private *dev_priv) |
eb48eb00 DV |
5417 | { |
5418 | unsigned long t, corr, state1, corr2, state2; | |
5419 | u32 pxvid, ext_v; | |
5420 | ||
02d71956 DV |
5421 | assert_spin_locked(&mchdev_lock); |
5422 | ||
b39fb297 | 5423 | pxvid = I915_READ(PXVFREQ_BASE + (dev_priv->rps.cur_freq * 4)); |
eb48eb00 DV |
5424 | pxvid = (pxvid >> 24) & 0x7f; |
5425 | ext_v = pvid_to_extvid(dev_priv, pxvid); | |
5426 | ||
5427 | state1 = ext_v; | |
5428 | ||
5429 | t = i915_mch_val(dev_priv); | |
5430 | ||
5431 | /* Revel in the empirically derived constants */ | |
5432 | ||
5433 | /* Correction factor in 1/100000 units */ | |
5434 | if (t > 80) | |
5435 | corr = ((t * 2349) + 135940); | |
5436 | else if (t >= 50) | |
5437 | corr = ((t * 964) + 29317); | |
5438 | else /* < 50 */ | |
5439 | corr = ((t * 301) + 1004); | |
5440 | ||
5441 | corr = corr * ((150142 * state1) / 10000 - 78642); | |
5442 | corr /= 100000; | |
20e4d407 | 5443 | corr2 = (corr * dev_priv->ips.corr); |
eb48eb00 DV |
5444 | |
5445 | state2 = (corr2 * state1) / 10000; | |
5446 | state2 /= 100; /* convert to mW */ | |
5447 | ||
02d71956 | 5448 | __i915_update_gfx_val(dev_priv); |
eb48eb00 | 5449 | |
20e4d407 | 5450 | return dev_priv->ips.gfx_power + state2; |
eb48eb00 DV |
5451 | } |
5452 | ||
f531dcb2 CW |
5453 | unsigned long i915_gfx_val(struct drm_i915_private *dev_priv) |
5454 | { | |
3d13ef2e | 5455 | struct drm_device *dev = dev_priv->dev; |
f531dcb2 CW |
5456 | unsigned long val; |
5457 | ||
3d13ef2e | 5458 | if (INTEL_INFO(dev)->gen != 5) |
f531dcb2 CW |
5459 | return 0; |
5460 | ||
5461 | spin_lock_irq(&mchdev_lock); | |
5462 | ||
5463 | val = __i915_gfx_val(dev_priv); | |
5464 | ||
5465 | spin_unlock_irq(&mchdev_lock); | |
5466 | ||
5467 | return val; | |
5468 | } | |
5469 | ||
eb48eb00 DV |
5470 | /** |
5471 | * i915_read_mch_val - return value for IPS use | |
5472 | * | |
5473 | * Calculate and return a value for the IPS driver to use when deciding whether | |
5474 | * we have thermal and power headroom to increase CPU or GPU power budget. | |
5475 | */ | |
5476 | unsigned long i915_read_mch_val(void) | |
5477 | { | |
5478 | struct drm_i915_private *dev_priv; | |
5479 | unsigned long chipset_val, graphics_val, ret = 0; | |
5480 | ||
9270388e | 5481 | spin_lock_irq(&mchdev_lock); |
eb48eb00 DV |
5482 | if (!i915_mch_dev) |
5483 | goto out_unlock; | |
5484 | dev_priv = i915_mch_dev; | |
5485 | ||
f531dcb2 CW |
5486 | chipset_val = __i915_chipset_val(dev_priv); |
5487 | graphics_val = __i915_gfx_val(dev_priv); | |
eb48eb00 DV |
5488 | |
5489 | ret = chipset_val + graphics_val; | |
5490 | ||
5491 | out_unlock: | |
9270388e | 5492 | spin_unlock_irq(&mchdev_lock); |
eb48eb00 DV |
5493 | |
5494 | return ret; | |
5495 | } | |
5496 | EXPORT_SYMBOL_GPL(i915_read_mch_val); | |
5497 | ||
5498 | /** | |
5499 | * i915_gpu_raise - raise GPU frequency limit | |
5500 | * | |
5501 | * Raise the limit; IPS indicates we have thermal headroom. | |
5502 | */ | |
5503 | bool i915_gpu_raise(void) | |
5504 | { | |
5505 | struct drm_i915_private *dev_priv; | |
5506 | bool ret = true; | |
5507 | ||
9270388e | 5508 | spin_lock_irq(&mchdev_lock); |
eb48eb00 DV |
5509 | if (!i915_mch_dev) { |
5510 | ret = false; | |
5511 | goto out_unlock; | |
5512 | } | |
5513 | dev_priv = i915_mch_dev; | |
5514 | ||
20e4d407 DV |
5515 | if (dev_priv->ips.max_delay > dev_priv->ips.fmax) |
5516 | dev_priv->ips.max_delay--; | |
eb48eb00 DV |
5517 | |
5518 | out_unlock: | |
9270388e | 5519 | spin_unlock_irq(&mchdev_lock); |
eb48eb00 DV |
5520 | |
5521 | return ret; | |
5522 | } | |
5523 | EXPORT_SYMBOL_GPL(i915_gpu_raise); | |
5524 | ||
5525 | /** | |
5526 | * i915_gpu_lower - lower GPU frequency limit | |
5527 | * | |
5528 | * IPS indicates we're close to a thermal limit, so throttle back the GPU | |
5529 | * frequency maximum. | |
5530 | */ | |
5531 | bool i915_gpu_lower(void) | |
5532 | { | |
5533 | struct drm_i915_private *dev_priv; | |
5534 | bool ret = true; | |
5535 | ||
9270388e | 5536 | spin_lock_irq(&mchdev_lock); |
eb48eb00 DV |
5537 | if (!i915_mch_dev) { |
5538 | ret = false; | |
5539 | goto out_unlock; | |
5540 | } | |
5541 | dev_priv = i915_mch_dev; | |
5542 | ||
20e4d407 DV |
5543 | if (dev_priv->ips.max_delay < dev_priv->ips.min_delay) |
5544 | dev_priv->ips.max_delay++; | |
eb48eb00 DV |
5545 | |
5546 | out_unlock: | |
9270388e | 5547 | spin_unlock_irq(&mchdev_lock); |
eb48eb00 DV |
5548 | |
5549 | return ret; | |
5550 | } | |
5551 | EXPORT_SYMBOL_GPL(i915_gpu_lower); | |
5552 | ||
5553 | /** | |
5554 | * i915_gpu_busy - indicate GPU business to IPS | |
5555 | * | |
5556 | * Tell the IPS driver whether or not the GPU is busy. | |
5557 | */ | |
5558 | bool i915_gpu_busy(void) | |
5559 | { | |
5560 | struct drm_i915_private *dev_priv; | |
a4872ba6 | 5561 | struct intel_engine_cs *ring; |
eb48eb00 | 5562 | bool ret = false; |
f047e395 | 5563 | int i; |
eb48eb00 | 5564 | |
9270388e | 5565 | spin_lock_irq(&mchdev_lock); |
eb48eb00 DV |
5566 | if (!i915_mch_dev) |
5567 | goto out_unlock; | |
5568 | dev_priv = i915_mch_dev; | |
5569 | ||
f047e395 CW |
5570 | for_each_ring(ring, dev_priv, i) |
5571 | ret |= !list_empty(&ring->request_list); | |
eb48eb00 DV |
5572 | |
5573 | out_unlock: | |
9270388e | 5574 | spin_unlock_irq(&mchdev_lock); |
eb48eb00 DV |
5575 | |
5576 | return ret; | |
5577 | } | |
5578 | EXPORT_SYMBOL_GPL(i915_gpu_busy); | |
5579 | ||
5580 | /** | |
5581 | * i915_gpu_turbo_disable - disable graphics turbo | |
5582 | * | |
5583 | * Disable graphics turbo by resetting the max frequency and setting the | |
5584 | * current frequency to the default. | |
5585 | */ | |
5586 | bool i915_gpu_turbo_disable(void) | |
5587 | { | |
5588 | struct drm_i915_private *dev_priv; | |
5589 | bool ret = true; | |
5590 | ||
9270388e | 5591 | spin_lock_irq(&mchdev_lock); |
eb48eb00 DV |
5592 | if (!i915_mch_dev) { |
5593 | ret = false; | |
5594 | goto out_unlock; | |
5595 | } | |
5596 | dev_priv = i915_mch_dev; | |
5597 | ||
20e4d407 | 5598 | dev_priv->ips.max_delay = dev_priv->ips.fstart; |
eb48eb00 | 5599 | |
20e4d407 | 5600 | if (!ironlake_set_drps(dev_priv->dev, dev_priv->ips.fstart)) |
eb48eb00 DV |
5601 | ret = false; |
5602 | ||
5603 | out_unlock: | |
9270388e | 5604 | spin_unlock_irq(&mchdev_lock); |
eb48eb00 DV |
5605 | |
5606 | return ret; | |
5607 | } | |
5608 | EXPORT_SYMBOL_GPL(i915_gpu_turbo_disable); | |
5609 | ||
5610 | /** | |
5611 | * Tells the intel_ips driver that the i915 driver is now loaded, if | |
5612 | * IPS got loaded first. | |
5613 | * | |
5614 | * This awkward dance is so that neither module has to depend on the | |
5615 | * other in order for IPS to do the appropriate communication of | |
5616 | * GPU turbo limits to i915. | |
5617 | */ | |
5618 | static void | |
5619 | ips_ping_for_i915_load(void) | |
5620 | { | |
5621 | void (*link)(void); | |
5622 | ||
5623 | link = symbol_get(ips_link_to_i915_driver); | |
5624 | if (link) { | |
5625 | link(); | |
5626 | symbol_put(ips_link_to_i915_driver); | |
5627 | } | |
5628 | } | |
5629 | ||
5630 | void intel_gpu_ips_init(struct drm_i915_private *dev_priv) | |
5631 | { | |
02d71956 DV |
5632 | /* We only register the i915 ips part with intel-ips once everything is |
5633 | * set up, to avoid intel-ips sneaking in and reading bogus values. */ | |
9270388e | 5634 | spin_lock_irq(&mchdev_lock); |
eb48eb00 | 5635 | i915_mch_dev = dev_priv; |
9270388e | 5636 | spin_unlock_irq(&mchdev_lock); |
eb48eb00 DV |
5637 | |
5638 | ips_ping_for_i915_load(); | |
5639 | } | |
5640 | ||
5641 | void intel_gpu_ips_teardown(void) | |
5642 | { | |
9270388e | 5643 | spin_lock_irq(&mchdev_lock); |
eb48eb00 | 5644 | i915_mch_dev = NULL; |
9270388e | 5645 | spin_unlock_irq(&mchdev_lock); |
eb48eb00 | 5646 | } |
76c3552f | 5647 | |
8090c6b9 | 5648 | static void intel_init_emon(struct drm_device *dev) |
dde18883 ED |
5649 | { |
5650 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5651 | u32 lcfuse; | |
5652 | u8 pxw[16]; | |
5653 | int i; | |
5654 | ||
5655 | /* Disable to program */ | |
5656 | I915_WRITE(ECR, 0); | |
5657 | POSTING_READ(ECR); | |
5658 | ||
5659 | /* Program energy weights for various events */ | |
5660 | I915_WRITE(SDEW, 0x15040d00); | |
5661 | I915_WRITE(CSIEW0, 0x007f0000); | |
5662 | I915_WRITE(CSIEW1, 0x1e220004); | |
5663 | I915_WRITE(CSIEW2, 0x04000004); | |
5664 | ||
5665 | for (i = 0; i < 5; i++) | |
5666 | I915_WRITE(PEW + (i * 4), 0); | |
5667 | for (i = 0; i < 3; i++) | |
5668 | I915_WRITE(DEW + (i * 4), 0); | |
5669 | ||
5670 | /* Program P-state weights to account for frequency power adjustment */ | |
5671 | for (i = 0; i < 16; i++) { | |
5672 | u32 pxvidfreq = I915_READ(PXVFREQ_BASE + (i * 4)); | |
5673 | unsigned long freq = intel_pxfreq(pxvidfreq); | |
5674 | unsigned long vid = (pxvidfreq & PXVFREQ_PX_MASK) >> | |
5675 | PXVFREQ_PX_SHIFT; | |
5676 | unsigned long val; | |
5677 | ||
5678 | val = vid * vid; | |
5679 | val *= (freq / 1000); | |
5680 | val *= 255; | |
5681 | val /= (127*127*900); | |
5682 | if (val > 0xff) | |
5683 | DRM_ERROR("bad pxval: %ld\n", val); | |
5684 | pxw[i] = val; | |
5685 | } | |
5686 | /* Render standby states get 0 weight */ | |
5687 | pxw[14] = 0; | |
5688 | pxw[15] = 0; | |
5689 | ||
5690 | for (i = 0; i < 4; i++) { | |
5691 | u32 val = (pxw[i*4] << 24) | (pxw[(i*4)+1] << 16) | | |
5692 | (pxw[(i*4)+2] << 8) | (pxw[(i*4)+3]); | |
5693 | I915_WRITE(PXW + (i * 4), val); | |
5694 | } | |
5695 | ||
5696 | /* Adjust magic regs to magic values (more experimental results) */ | |
5697 | I915_WRITE(OGW0, 0); | |
5698 | I915_WRITE(OGW1, 0); | |
5699 | I915_WRITE(EG0, 0x00007f00); | |
5700 | I915_WRITE(EG1, 0x0000000e); | |
5701 | I915_WRITE(EG2, 0x000e0000); | |
5702 | I915_WRITE(EG3, 0x68000300); | |
5703 | I915_WRITE(EG4, 0x42000000); | |
5704 | I915_WRITE(EG5, 0x00140031); | |
5705 | I915_WRITE(EG6, 0); | |
5706 | I915_WRITE(EG7, 0); | |
5707 | ||
5708 | for (i = 0; i < 8; i++) | |
5709 | I915_WRITE(PXWL + (i * 4), 0); | |
5710 | ||
5711 | /* Enable PMON + select events */ | |
5712 | I915_WRITE(ECR, 0x80000019); | |
5713 | ||
5714 | lcfuse = I915_READ(LCFUSE02); | |
5715 | ||
20e4d407 | 5716 | dev_priv->ips.corr = (lcfuse & LCFUSE_HIV_MASK); |
dde18883 ED |
5717 | } |
5718 | ||
ae48434c ID |
5719 | void intel_init_gt_powersave(struct drm_device *dev) |
5720 | { | |
e6069ca8 ID |
5721 | i915.enable_rc6 = sanitize_rc6_option(dev, i915.enable_rc6); |
5722 | ||
38807746 D |
5723 | if (IS_CHERRYVIEW(dev)) |
5724 | cherryview_init_gt_powersave(dev); | |
5725 | else if (IS_VALLEYVIEW(dev)) | |
4e80519e | 5726 | valleyview_init_gt_powersave(dev); |
ae48434c ID |
5727 | } |
5728 | ||
5729 | void intel_cleanup_gt_powersave(struct drm_device *dev) | |
5730 | { | |
38807746 D |
5731 | if (IS_CHERRYVIEW(dev)) |
5732 | return; | |
5733 | else if (IS_VALLEYVIEW(dev)) | |
4e80519e | 5734 | valleyview_cleanup_gt_powersave(dev); |
ae48434c ID |
5735 | } |
5736 | ||
dbea3cea ID |
5737 | static void gen6_suspend_rps(struct drm_device *dev) |
5738 | { | |
5739 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5740 | ||
5741 | flush_delayed_work(&dev_priv->rps.delayed_resume_work); | |
5742 | ||
4c2a8897 | 5743 | gen6_disable_rps_interrupts(dev); |
dbea3cea ID |
5744 | } |
5745 | ||
156c7ca0 JB |
5746 | /** |
5747 | * intel_suspend_gt_powersave - suspend PM work and helper threads | |
5748 | * @dev: drm device | |
5749 | * | |
5750 | * We don't want to disable RC6 or other features here, we just want | |
5751 | * to make sure any work we've queued has finished and won't bother | |
5752 | * us while we're suspended. | |
5753 | */ | |
5754 | void intel_suspend_gt_powersave(struct drm_device *dev) | |
5755 | { | |
5756 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5757 | ||
d4d70aa5 ID |
5758 | if (INTEL_INFO(dev)->gen < 6) |
5759 | return; | |
5760 | ||
dbea3cea | 5761 | gen6_suspend_rps(dev); |
b47adc17 D |
5762 | |
5763 | /* Force GPU to min freq during suspend */ | |
5764 | gen6_rps_idle(dev_priv); | |
156c7ca0 JB |
5765 | } |
5766 | ||
8090c6b9 DV |
5767 | void intel_disable_gt_powersave(struct drm_device *dev) |
5768 | { | |
1a01ab3b JB |
5769 | struct drm_i915_private *dev_priv = dev->dev_private; |
5770 | ||
930ebb46 | 5771 | if (IS_IRONLAKE_M(dev)) { |
8090c6b9 | 5772 | ironlake_disable_drps(dev); |
38807746 | 5773 | } else if (INTEL_INFO(dev)->gen >= 6) { |
10d8d366 | 5774 | intel_suspend_gt_powersave(dev); |
e494837a | 5775 | |
4fc688ce | 5776 | mutex_lock(&dev_priv->rps.hw_lock); |
20e49366 ZW |
5777 | if (INTEL_INFO(dev)->gen >= 9) |
5778 | gen9_disable_rps(dev); | |
5779 | else if (IS_CHERRYVIEW(dev)) | |
38807746 D |
5780 | cherryview_disable_rps(dev); |
5781 | else if (IS_VALLEYVIEW(dev)) | |
d20d4f0c JB |
5782 | valleyview_disable_rps(dev); |
5783 | else | |
5784 | gen6_disable_rps(dev); | |
e534770a | 5785 | |
c0951f0c | 5786 | dev_priv->rps.enabled = false; |
4fc688ce | 5787 | mutex_unlock(&dev_priv->rps.hw_lock); |
930ebb46 | 5788 | } |
8090c6b9 DV |
5789 | } |
5790 | ||
1a01ab3b JB |
5791 | static void intel_gen6_powersave_work(struct work_struct *work) |
5792 | { | |
5793 | struct drm_i915_private *dev_priv = | |
5794 | container_of(work, struct drm_i915_private, | |
5795 | rps.delayed_resume_work.work); | |
5796 | struct drm_device *dev = dev_priv->dev; | |
5797 | ||
4fc688ce | 5798 | mutex_lock(&dev_priv->rps.hw_lock); |
0a073b84 | 5799 | |
4c2a8897 | 5800 | gen6_reset_rps_interrupts(dev); |
3cc134e3 | 5801 | |
38807746 D |
5802 | if (IS_CHERRYVIEW(dev)) { |
5803 | cherryview_enable_rps(dev); | |
5804 | } else if (IS_VALLEYVIEW(dev)) { | |
0a073b84 | 5805 | valleyview_enable_rps(dev); |
20e49366 | 5806 | } else if (INTEL_INFO(dev)->gen >= 9) { |
b6fef0ef | 5807 | gen9_enable_rc6(dev); |
20e49366 | 5808 | gen9_enable_rps(dev); |
b6fef0ef | 5809 | __gen6_update_ring_freq(dev); |
6edee7f3 BW |
5810 | } else if (IS_BROADWELL(dev)) { |
5811 | gen8_enable_rps(dev); | |
c2bc2fc5 | 5812 | __gen6_update_ring_freq(dev); |
0a073b84 JB |
5813 | } else { |
5814 | gen6_enable_rps(dev); | |
c2bc2fc5 | 5815 | __gen6_update_ring_freq(dev); |
0a073b84 | 5816 | } |
aed242ff CW |
5817 | |
5818 | WARN_ON(dev_priv->rps.max_freq < dev_priv->rps.min_freq); | |
5819 | WARN_ON(dev_priv->rps.idle_freq > dev_priv->rps.max_freq); | |
5820 | ||
5821 | WARN_ON(dev_priv->rps.efficient_freq < dev_priv->rps.min_freq); | |
5822 | WARN_ON(dev_priv->rps.efficient_freq > dev_priv->rps.max_freq); | |
5823 | ||
c0951f0c | 5824 | dev_priv->rps.enabled = true; |
3cc134e3 | 5825 | |
4c2a8897 | 5826 | gen6_enable_rps_interrupts(dev); |
3cc134e3 | 5827 | |
4fc688ce | 5828 | mutex_unlock(&dev_priv->rps.hw_lock); |
c6df39b5 ID |
5829 | |
5830 | intel_runtime_pm_put(dev_priv); | |
1a01ab3b JB |
5831 | } |
5832 | ||
8090c6b9 DV |
5833 | void intel_enable_gt_powersave(struct drm_device *dev) |
5834 | { | |
1a01ab3b JB |
5835 | struct drm_i915_private *dev_priv = dev->dev_private; |
5836 | ||
f61018b1 YZ |
5837 | /* Powersaving is controlled by the host when inside a VM */ |
5838 | if (intel_vgpu_active(dev)) | |
5839 | return; | |
5840 | ||
8090c6b9 | 5841 | if (IS_IRONLAKE_M(dev)) { |
dc1d0136 | 5842 | mutex_lock(&dev->struct_mutex); |
8090c6b9 | 5843 | ironlake_enable_drps(dev); |
8090c6b9 | 5844 | intel_init_emon(dev); |
dc1d0136 | 5845 | mutex_unlock(&dev->struct_mutex); |
38807746 | 5846 | } else if (INTEL_INFO(dev)->gen >= 6) { |
1a01ab3b JB |
5847 | /* |
5848 | * PCU communication is slow and this doesn't need to be | |
5849 | * done at any specific time, so do this out of our fast path | |
5850 | * to make resume and init faster. | |
c6df39b5 ID |
5851 | * |
5852 | * We depend on the HW RC6 power context save/restore | |
5853 | * mechanism when entering D3 through runtime PM suspend. So | |
5854 | * disable RPM until RPS/RC6 is properly setup. We can only | |
5855 | * get here via the driver load/system resume/runtime resume | |
5856 | * paths, so the _noresume version is enough (and in case of | |
5857 | * runtime resume it's necessary). | |
1a01ab3b | 5858 | */ |
c6df39b5 ID |
5859 | if (schedule_delayed_work(&dev_priv->rps.delayed_resume_work, |
5860 | round_jiffies_up_relative(HZ))) | |
5861 | intel_runtime_pm_get_noresume(dev_priv); | |
8090c6b9 DV |
5862 | } |
5863 | } | |
5864 | ||
c6df39b5 ID |
5865 | void intel_reset_gt_powersave(struct drm_device *dev) |
5866 | { | |
5867 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5868 | ||
dbea3cea ID |
5869 | if (INTEL_INFO(dev)->gen < 6) |
5870 | return; | |
5871 | ||
5872 | gen6_suspend_rps(dev); | |
c6df39b5 | 5873 | dev_priv->rps.enabled = false; |
c6df39b5 ID |
5874 | } |
5875 | ||
3107bd48 DV |
5876 | static void ibx_init_clock_gating(struct drm_device *dev) |
5877 | { | |
5878 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5879 | ||
5880 | /* | |
5881 | * On Ibex Peak and Cougar Point, we need to disable clock | |
5882 | * gating for the panel power sequencer or it will fail to | |
5883 | * start up when no ports are active. | |
5884 | */ | |
5885 | I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE); | |
5886 | } | |
5887 | ||
0e088b8f VS |
5888 | static void g4x_disable_trickle_feed(struct drm_device *dev) |
5889 | { | |
5890 | struct drm_i915_private *dev_priv = dev->dev_private; | |
b12ce1d8 | 5891 | enum pipe pipe; |
0e088b8f | 5892 | |
055e393f | 5893 | for_each_pipe(dev_priv, pipe) { |
0e088b8f VS |
5894 | I915_WRITE(DSPCNTR(pipe), |
5895 | I915_READ(DSPCNTR(pipe)) | | |
5896 | DISPPLANE_TRICKLE_FEED_DISABLE); | |
b12ce1d8 VS |
5897 | |
5898 | I915_WRITE(DSPSURF(pipe), I915_READ(DSPSURF(pipe))); | |
5899 | POSTING_READ(DSPSURF(pipe)); | |
0e088b8f VS |
5900 | } |
5901 | } | |
5902 | ||
017636cc VS |
5903 | static void ilk_init_lp_watermarks(struct drm_device *dev) |
5904 | { | |
5905 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5906 | ||
5907 | I915_WRITE(WM3_LP_ILK, I915_READ(WM3_LP_ILK) & ~WM1_LP_SR_EN); | |
5908 | I915_WRITE(WM2_LP_ILK, I915_READ(WM2_LP_ILK) & ~WM1_LP_SR_EN); | |
5909 | I915_WRITE(WM1_LP_ILK, I915_READ(WM1_LP_ILK) & ~WM1_LP_SR_EN); | |
5910 | ||
5911 | /* | |
5912 | * Don't touch WM1S_LP_EN here. | |
5913 | * Doing so could cause underruns. | |
5914 | */ | |
5915 | } | |
5916 | ||
1fa61106 | 5917 | static void ironlake_init_clock_gating(struct drm_device *dev) |
6f1d69b0 ED |
5918 | { |
5919 | struct drm_i915_private *dev_priv = dev->dev_private; | |
231e54f6 | 5920 | uint32_t dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE; |
6f1d69b0 | 5921 | |
f1e8fa56 DL |
5922 | /* |
5923 | * Required for FBC | |
5924 | * WaFbcDisableDpfcClockGating:ilk | |
5925 | */ | |
4d47e4f5 DL |
5926 | dspclk_gate |= ILK_DPFCRUNIT_CLOCK_GATE_DISABLE | |
5927 | ILK_DPFCUNIT_CLOCK_GATE_DISABLE | | |
5928 | ILK_DPFDUNIT_CLOCK_GATE_ENABLE; | |
6f1d69b0 ED |
5929 | |
5930 | I915_WRITE(PCH_3DCGDIS0, | |
5931 | MARIUNIT_CLOCK_GATE_DISABLE | | |
5932 | SVSMUNIT_CLOCK_GATE_DISABLE); | |
5933 | I915_WRITE(PCH_3DCGDIS1, | |
5934 | VFMUNIT_CLOCK_GATE_DISABLE); | |
5935 | ||
6f1d69b0 ED |
5936 | /* |
5937 | * According to the spec the following bits should be set in | |
5938 | * order to enable memory self-refresh | |
5939 | * The bit 22/21 of 0x42004 | |
5940 | * The bit 5 of 0x42020 | |
5941 | * The bit 15 of 0x45000 | |
5942 | */ | |
5943 | I915_WRITE(ILK_DISPLAY_CHICKEN2, | |
5944 | (I915_READ(ILK_DISPLAY_CHICKEN2) | | |
5945 | ILK_DPARB_GATE | ILK_VSDPFD_FULL)); | |
4d47e4f5 | 5946 | dspclk_gate |= ILK_DPARBUNIT_CLOCK_GATE_ENABLE; |
6f1d69b0 ED |
5947 | I915_WRITE(DISP_ARB_CTL, |
5948 | (I915_READ(DISP_ARB_CTL) | | |
5949 | DISP_FBC_WM_DIS)); | |
017636cc VS |
5950 | |
5951 | ilk_init_lp_watermarks(dev); | |
6f1d69b0 ED |
5952 | |
5953 | /* | |
5954 | * Based on the document from hardware guys the following bits | |
5955 | * should be set unconditionally in order to enable FBC. | |
5956 | * The bit 22 of 0x42000 | |
5957 | * The bit 22 of 0x42004 | |
5958 | * The bit 7,8,9 of 0x42020. | |
5959 | */ | |
5960 | if (IS_IRONLAKE_M(dev)) { | |
4bb35334 | 5961 | /* WaFbcAsynchFlipDisableFbcQueue:ilk */ |
6f1d69b0 ED |
5962 | I915_WRITE(ILK_DISPLAY_CHICKEN1, |
5963 | I915_READ(ILK_DISPLAY_CHICKEN1) | | |
5964 | ILK_FBCQ_DIS); | |
5965 | I915_WRITE(ILK_DISPLAY_CHICKEN2, | |
5966 | I915_READ(ILK_DISPLAY_CHICKEN2) | | |
5967 | ILK_DPARB_GATE); | |
6f1d69b0 ED |
5968 | } |
5969 | ||
4d47e4f5 DL |
5970 | I915_WRITE(ILK_DSPCLK_GATE_D, dspclk_gate); |
5971 | ||
6f1d69b0 ED |
5972 | I915_WRITE(ILK_DISPLAY_CHICKEN2, |
5973 | I915_READ(ILK_DISPLAY_CHICKEN2) | | |
5974 | ILK_ELPIN_409_SELECT); | |
5975 | I915_WRITE(_3D_CHICKEN2, | |
5976 | _3D_CHICKEN2_WM_READ_PIPELINED << 16 | | |
5977 | _3D_CHICKEN2_WM_READ_PIPELINED); | |
4358a374 | 5978 | |
ecdb4eb7 | 5979 | /* WaDisableRenderCachePipelinedFlush:ilk */ |
4358a374 DV |
5980 | I915_WRITE(CACHE_MODE_0, |
5981 | _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE)); | |
3107bd48 | 5982 | |
4e04632e AG |
5983 | /* WaDisable_RenderCache_OperationalFlush:ilk */ |
5984 | I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE)); | |
5985 | ||
0e088b8f | 5986 | g4x_disable_trickle_feed(dev); |
bdad2b2f | 5987 | |
3107bd48 DV |
5988 | ibx_init_clock_gating(dev); |
5989 | } | |
5990 | ||
5991 | static void cpt_init_clock_gating(struct drm_device *dev) | |
5992 | { | |
5993 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5994 | int pipe; | |
3f704fa2 | 5995 | uint32_t val; |
3107bd48 DV |
5996 | |
5997 | /* | |
5998 | * On Ibex Peak and Cougar Point, we need to disable clock | |
5999 | * gating for the panel power sequencer or it will fail to | |
6000 | * start up when no ports are active. | |
6001 | */ | |
cd664078 JB |
6002 | I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE | |
6003 | PCH_DPLUNIT_CLOCK_GATE_DISABLE | | |
6004 | PCH_CPUNIT_CLOCK_GATE_DISABLE); | |
3107bd48 DV |
6005 | I915_WRITE(SOUTH_CHICKEN2, I915_READ(SOUTH_CHICKEN2) | |
6006 | DPLS_EDP_PPS_FIX_DIS); | |
335c07b7 TI |
6007 | /* The below fixes the weird display corruption, a few pixels shifted |
6008 | * downward, on (only) LVDS of some HP laptops with IVY. | |
6009 | */ | |
055e393f | 6010 | for_each_pipe(dev_priv, pipe) { |
dc4bd2d1 PZ |
6011 | val = I915_READ(TRANS_CHICKEN2(pipe)); |
6012 | val |= TRANS_CHICKEN2_TIMING_OVERRIDE; | |
6013 | val &= ~TRANS_CHICKEN2_FDI_POLARITY_REVERSED; | |
41aa3448 | 6014 | if (dev_priv->vbt.fdi_rx_polarity_inverted) |
3f704fa2 | 6015 | val |= TRANS_CHICKEN2_FDI_POLARITY_REVERSED; |
dc4bd2d1 PZ |
6016 | val &= ~TRANS_CHICKEN2_FRAME_START_DELAY_MASK; |
6017 | val &= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_COUNTER; | |
6018 | val &= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_MODESWITCH; | |
3f704fa2 PZ |
6019 | I915_WRITE(TRANS_CHICKEN2(pipe), val); |
6020 | } | |
3107bd48 | 6021 | /* WADP0ClockGatingDisable */ |
055e393f | 6022 | for_each_pipe(dev_priv, pipe) { |
3107bd48 DV |
6023 | I915_WRITE(TRANS_CHICKEN1(pipe), |
6024 | TRANS_CHICKEN1_DP0UNIT_GC_DISABLE); | |
6025 | } | |
6f1d69b0 ED |
6026 | } |
6027 | ||
1d7aaa0c DV |
6028 | static void gen6_check_mch_setup(struct drm_device *dev) |
6029 | { | |
6030 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6031 | uint32_t tmp; | |
6032 | ||
6033 | tmp = I915_READ(MCH_SSKPD); | |
df662a28 DV |
6034 | if ((tmp & MCH_SSKPD_WM0_MASK) != MCH_SSKPD_WM0_VAL) |
6035 | DRM_DEBUG_KMS("Wrong MCH_SSKPD value: 0x%08x This can cause underruns.\n", | |
6036 | tmp); | |
1d7aaa0c DV |
6037 | } |
6038 | ||
1fa61106 | 6039 | static void gen6_init_clock_gating(struct drm_device *dev) |
6f1d69b0 ED |
6040 | { |
6041 | struct drm_i915_private *dev_priv = dev->dev_private; | |
231e54f6 | 6042 | uint32_t dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE; |
6f1d69b0 | 6043 | |
231e54f6 | 6044 | I915_WRITE(ILK_DSPCLK_GATE_D, dspclk_gate); |
6f1d69b0 ED |
6045 | |
6046 | I915_WRITE(ILK_DISPLAY_CHICKEN2, | |
6047 | I915_READ(ILK_DISPLAY_CHICKEN2) | | |
6048 | ILK_ELPIN_409_SELECT); | |
6049 | ||
ecdb4eb7 | 6050 | /* WaDisableHiZPlanesWhenMSAAEnabled:snb */ |
4283908e DV |
6051 | I915_WRITE(_3D_CHICKEN, |
6052 | _MASKED_BIT_ENABLE(_3D_CHICKEN_HIZ_PLANE_DISABLE_MSAA_4X_SNB)); | |
6053 | ||
4e04632e AG |
6054 | /* WaDisable_RenderCache_OperationalFlush:snb */ |
6055 | I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE)); | |
6056 | ||
8d85d272 VS |
6057 | /* |
6058 | * BSpec recoomends 8x4 when MSAA is used, | |
6059 | * however in practice 16x4 seems fastest. | |
c5c98a58 VS |
6060 | * |
6061 | * Note that PS/WM thread counts depend on the WIZ hashing | |
6062 | * disable bit, which we don't touch here, but it's good | |
6063 | * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM). | |
8d85d272 VS |
6064 | */ |
6065 | I915_WRITE(GEN6_GT_MODE, | |
98533251 | 6066 | _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4)); |
8d85d272 | 6067 | |
017636cc | 6068 | ilk_init_lp_watermarks(dev); |
6f1d69b0 | 6069 | |
6f1d69b0 | 6070 | I915_WRITE(CACHE_MODE_0, |
50743298 | 6071 | _MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB)); |
6f1d69b0 ED |
6072 | |
6073 | I915_WRITE(GEN6_UCGCTL1, | |
6074 | I915_READ(GEN6_UCGCTL1) | | |
6075 | GEN6_BLBUNIT_CLOCK_GATE_DISABLE | | |
6076 | GEN6_CSUNIT_CLOCK_GATE_DISABLE); | |
6077 | ||
6078 | /* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock | |
6079 | * gating disable must be set. Failure to set it results in | |
6080 | * flickering pixels due to Z write ordering failures after | |
6081 | * some amount of runtime in the Mesa "fire" demo, and Unigine | |
6082 | * Sanctuary and Tropics, and apparently anything else with | |
6083 | * alpha test or pixel discard. | |
6084 | * | |
6085 | * According to the spec, bit 11 (RCCUNIT) must also be set, | |
6086 | * but we didn't debug actual testcases to find it out. | |
0f846f81 | 6087 | * |
ef59318c VS |
6088 | * WaDisableRCCUnitClockGating:snb |
6089 | * WaDisableRCPBUnitClockGating:snb | |
6f1d69b0 ED |
6090 | */ |
6091 | I915_WRITE(GEN6_UCGCTL2, | |
6092 | GEN6_RCPBUNIT_CLOCK_GATE_DISABLE | | |
6093 | GEN6_RCCUNIT_CLOCK_GATE_DISABLE); | |
6094 | ||
5eb146dd | 6095 | /* WaStripsFansDisableFastClipPerformanceFix:snb */ |
743b57d8 VS |
6096 | I915_WRITE(_3D_CHICKEN3, |
6097 | _MASKED_BIT_ENABLE(_3D_CHICKEN3_SF_DISABLE_FASTCLIP_CULL)); | |
6f1d69b0 | 6098 | |
e927ecde VS |
6099 | /* |
6100 | * Bspec says: | |
6101 | * "This bit must be set if 3DSTATE_CLIP clip mode is set to normal and | |
6102 | * 3DSTATE_SF number of SF output attributes is more than 16." | |
6103 | */ | |
6104 | I915_WRITE(_3D_CHICKEN3, | |
6105 | _MASKED_BIT_ENABLE(_3D_CHICKEN3_SF_DISABLE_PIPELINED_ATTR_FETCH)); | |
6106 | ||
6f1d69b0 ED |
6107 | /* |
6108 | * According to the spec the following bits should be | |
6109 | * set in order to enable memory self-refresh and fbc: | |
6110 | * The bit21 and bit22 of 0x42000 | |
6111 | * The bit21 and bit22 of 0x42004 | |
6112 | * The bit5 and bit7 of 0x42020 | |
6113 | * The bit14 of 0x70180 | |
6114 | * The bit14 of 0x71180 | |
4bb35334 DL |
6115 | * |
6116 | * WaFbcAsynchFlipDisableFbcQueue:snb | |
6f1d69b0 ED |
6117 | */ |
6118 | I915_WRITE(ILK_DISPLAY_CHICKEN1, | |
6119 | I915_READ(ILK_DISPLAY_CHICKEN1) | | |
6120 | ILK_FBCQ_DIS | ILK_PABSTRETCH_DIS); | |
6121 | I915_WRITE(ILK_DISPLAY_CHICKEN2, | |
6122 | I915_READ(ILK_DISPLAY_CHICKEN2) | | |
6123 | ILK_DPARB_GATE | ILK_VSDPFD_FULL); | |
231e54f6 DL |
6124 | I915_WRITE(ILK_DSPCLK_GATE_D, |
6125 | I915_READ(ILK_DSPCLK_GATE_D) | | |
6126 | ILK_DPARBUNIT_CLOCK_GATE_ENABLE | | |
6127 | ILK_DPFDUNIT_CLOCK_GATE_ENABLE); | |
6f1d69b0 | 6128 | |
0e088b8f | 6129 | g4x_disable_trickle_feed(dev); |
f8f2ac9a | 6130 | |
3107bd48 | 6131 | cpt_init_clock_gating(dev); |
1d7aaa0c DV |
6132 | |
6133 | gen6_check_mch_setup(dev); | |
6f1d69b0 ED |
6134 | } |
6135 | ||
6136 | static void gen7_setup_fixed_func_scheduler(struct drm_i915_private *dev_priv) | |
6137 | { | |
6138 | uint32_t reg = I915_READ(GEN7_FF_THREAD_MODE); | |
6139 | ||
3aad9059 | 6140 | /* |
46680e0a | 6141 | * WaVSThreadDispatchOverride:ivb,vlv |
3aad9059 VS |
6142 | * |
6143 | * This actually overrides the dispatch | |
6144 | * mode for all thread types. | |
6145 | */ | |
6f1d69b0 ED |
6146 | reg &= ~GEN7_FF_SCHED_MASK; |
6147 | reg |= GEN7_FF_TS_SCHED_HW; | |
6148 | reg |= GEN7_FF_VS_SCHED_HW; | |
6149 | reg |= GEN7_FF_DS_SCHED_HW; | |
6150 | ||
6151 | I915_WRITE(GEN7_FF_THREAD_MODE, reg); | |
6152 | } | |
6153 | ||
17a303ec PZ |
6154 | static void lpt_init_clock_gating(struct drm_device *dev) |
6155 | { | |
6156 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6157 | ||
6158 | /* | |
6159 | * TODO: this bit should only be enabled when really needed, then | |
6160 | * disabled when not needed anymore in order to save power. | |
6161 | */ | |
6162 | if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) | |
6163 | I915_WRITE(SOUTH_DSPCLK_GATE_D, | |
6164 | I915_READ(SOUTH_DSPCLK_GATE_D) | | |
6165 | PCH_LP_PARTITION_LEVEL_DISABLE); | |
0a790cdb PZ |
6166 | |
6167 | /* WADPOClockGatingDisable:hsw */ | |
6168 | I915_WRITE(_TRANSA_CHICKEN1, | |
6169 | I915_READ(_TRANSA_CHICKEN1) | | |
6170 | TRANS_CHICKEN1_DP0UNIT_GC_DISABLE); | |
17a303ec PZ |
6171 | } |
6172 | ||
7d708ee4 ID |
6173 | static void lpt_suspend_hw(struct drm_device *dev) |
6174 | { | |
6175 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6176 | ||
6177 | if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) { | |
6178 | uint32_t val = I915_READ(SOUTH_DSPCLK_GATE_D); | |
6179 | ||
6180 | val &= ~PCH_LP_PARTITION_LEVEL_DISABLE; | |
6181 | I915_WRITE(SOUTH_DSPCLK_GATE_D, val); | |
6182 | } | |
6183 | } | |
6184 | ||
47c2bd97 | 6185 | static void broadwell_init_clock_gating(struct drm_device *dev) |
1020a5c2 BW |
6186 | { |
6187 | struct drm_i915_private *dev_priv = dev->dev_private; | |
07d27e20 | 6188 | enum pipe pipe; |
4d487cff | 6189 | uint32_t misccpctl; |
1020a5c2 | 6190 | |
7ad0dbab | 6191 | ilk_init_lp_watermarks(dev); |
50ed5fbd | 6192 | |
ab57fff1 | 6193 | /* WaSwitchSolVfFArbitrationPriority:bdw */ |
50ed5fbd | 6194 | I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | HSW_ECOCHK_ARB_PRIO_SOL); |
fe4ab3ce | 6195 | |
ab57fff1 | 6196 | /* WaPsrDPAMaskVBlankInSRD:bdw */ |
fe4ab3ce BW |
6197 | I915_WRITE(CHICKEN_PAR1_1, |
6198 | I915_READ(CHICKEN_PAR1_1) | DPA_MASK_VBLANK_SRD); | |
6199 | ||
ab57fff1 | 6200 | /* WaPsrDPRSUnmaskVBlankInSRD:bdw */ |
055e393f | 6201 | for_each_pipe(dev_priv, pipe) { |
07d27e20 | 6202 | I915_WRITE(CHICKEN_PIPESL_1(pipe), |
c7c65622 | 6203 | I915_READ(CHICKEN_PIPESL_1(pipe)) | |
8f670bb1 | 6204 | BDW_DPRS_MASK_VBLANK_SRD); |
fe4ab3ce | 6205 | } |
63801f21 | 6206 | |
ab57fff1 BW |
6207 | /* WaVSRefCountFullforceMissDisable:bdw */ |
6208 | /* WaDSRefCountFullforceMissDisable:bdw */ | |
6209 | I915_WRITE(GEN7_FF_THREAD_MODE, | |
6210 | I915_READ(GEN7_FF_THREAD_MODE) & | |
6211 | ~(GEN8_FF_DS_REF_CNT_FFME | GEN7_FF_VS_REF_CNT_FFME)); | |
36075a4c | 6212 | |
295e8bb7 VS |
6213 | I915_WRITE(GEN6_RC_SLEEP_PSMI_CONTROL, |
6214 | _MASKED_BIT_ENABLE(GEN8_RC_SEMA_IDLE_MSG_DISABLE)); | |
4f1ca9e9 VS |
6215 | |
6216 | /* WaDisableSDEUnitClockGating:bdw */ | |
6217 | I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) | | |
6218 | GEN8_SDEUNIT_CLOCK_GATE_DISABLE); | |
5d708680 | 6219 | |
4d487cff VS |
6220 | /* |
6221 | * WaProgramL3SqcReg1Default:bdw | |
6222 | * WaTempDisableDOPClkGating:bdw | |
6223 | */ | |
6224 | misccpctl = I915_READ(GEN7_MISCCPCTL); | |
6225 | I915_WRITE(GEN7_MISCCPCTL, misccpctl & ~GEN7_DOP_CLOCK_GATE_ENABLE); | |
6226 | I915_WRITE(GEN8_L3SQCREG1, BDW_WA_L3SQCREG1_DEFAULT); | |
6227 | I915_WRITE(GEN7_MISCCPCTL, misccpctl); | |
6228 | ||
6d50b065 VS |
6229 | /* |
6230 | * WaGttCachingOffByDefault:bdw | |
6231 | * GTT cache may not work with big pages, so if those | |
6232 | * are ever enabled GTT cache may need to be disabled. | |
6233 | */ | |
6234 | I915_WRITE(HSW_GTT_CACHE_EN, GTT_CACHE_EN_ALL); | |
6235 | ||
89d6b2b8 | 6236 | lpt_init_clock_gating(dev); |
1020a5c2 BW |
6237 | } |
6238 | ||
cad2a2d7 ED |
6239 | static void haswell_init_clock_gating(struct drm_device *dev) |
6240 | { | |
6241 | struct drm_i915_private *dev_priv = dev->dev_private; | |
cad2a2d7 | 6242 | |
017636cc | 6243 | ilk_init_lp_watermarks(dev); |
cad2a2d7 | 6244 | |
f3fc4884 FJ |
6245 | /* L3 caching of data atomics doesn't work -- disable it. */ |
6246 | I915_WRITE(HSW_SCRATCH1, HSW_SCRATCH1_L3_DATA_ATOMICS_DISABLE); | |
6247 | I915_WRITE(HSW_ROW_CHICKEN3, | |
6248 | _MASKED_BIT_ENABLE(HSW_ROW_CHICKEN3_L3_GLOBAL_ATOMICS_DISABLE)); | |
6249 | ||
ecdb4eb7 | 6250 | /* This is required by WaCatErrorRejectionIssue:hsw */ |
cad2a2d7 ED |
6251 | I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG, |
6252 | I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) | | |
6253 | GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB); | |
6254 | ||
e36ea7ff VS |
6255 | /* WaVSRefCountFullforceMissDisable:hsw */ |
6256 | I915_WRITE(GEN7_FF_THREAD_MODE, | |
6257 | I915_READ(GEN7_FF_THREAD_MODE) & ~GEN7_FF_VS_REF_CNT_FFME); | |
cad2a2d7 | 6258 | |
4e04632e AG |
6259 | /* WaDisable_RenderCache_OperationalFlush:hsw */ |
6260 | I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE)); | |
6261 | ||
fe27c606 CW |
6262 | /* enable HiZ Raw Stall Optimization */ |
6263 | I915_WRITE(CACHE_MODE_0_GEN7, | |
6264 | _MASKED_BIT_DISABLE(HIZ_RAW_STALL_OPT_DISABLE)); | |
6265 | ||
ecdb4eb7 | 6266 | /* WaDisable4x2SubspanOptimization:hsw */ |
cad2a2d7 ED |
6267 | I915_WRITE(CACHE_MODE_1, |
6268 | _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE)); | |
1544d9d5 | 6269 | |
a12c4967 VS |
6270 | /* |
6271 | * BSpec recommends 8x4 when MSAA is used, | |
6272 | * however in practice 16x4 seems fastest. | |
c5c98a58 VS |
6273 | * |
6274 | * Note that PS/WM thread counts depend on the WIZ hashing | |
6275 | * disable bit, which we don't touch here, but it's good | |
6276 | * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM). | |
a12c4967 VS |
6277 | */ |
6278 | I915_WRITE(GEN7_GT_MODE, | |
98533251 | 6279 | _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4)); |
a12c4967 | 6280 | |
94411593 KG |
6281 | /* WaSampleCChickenBitEnable:hsw */ |
6282 | I915_WRITE(HALF_SLICE_CHICKEN3, | |
6283 | _MASKED_BIT_ENABLE(HSW_SAMPLE_C_PERFORMANCE)); | |
6284 | ||
ecdb4eb7 | 6285 | /* WaSwitchSolVfFArbitrationPriority:hsw */ |
e3dff585 BW |
6286 | I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | HSW_ECOCHK_ARB_PRIO_SOL); |
6287 | ||
90a88643 PZ |
6288 | /* WaRsPkgCStateDisplayPMReq:hsw */ |
6289 | I915_WRITE(CHICKEN_PAR1_1, | |
6290 | I915_READ(CHICKEN_PAR1_1) | FORCE_ARB_IDLE_PLANES); | |
1544d9d5 | 6291 | |
17a303ec | 6292 | lpt_init_clock_gating(dev); |
cad2a2d7 ED |
6293 | } |
6294 | ||
1fa61106 | 6295 | static void ivybridge_init_clock_gating(struct drm_device *dev) |
6f1d69b0 ED |
6296 | { |
6297 | struct drm_i915_private *dev_priv = dev->dev_private; | |
20848223 | 6298 | uint32_t snpcr; |
6f1d69b0 | 6299 | |
017636cc | 6300 | ilk_init_lp_watermarks(dev); |
6f1d69b0 | 6301 | |
231e54f6 | 6302 | I915_WRITE(ILK_DSPCLK_GATE_D, ILK_VRHUNIT_CLOCK_GATE_DISABLE); |
6f1d69b0 | 6303 | |
ecdb4eb7 | 6304 | /* WaDisableEarlyCull:ivb */ |
87f8020e JB |
6305 | I915_WRITE(_3D_CHICKEN3, |
6306 | _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL)); | |
6307 | ||
ecdb4eb7 | 6308 | /* WaDisableBackToBackFlipFix:ivb */ |
6f1d69b0 ED |
6309 | I915_WRITE(IVB_CHICKEN3, |
6310 | CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE | | |
6311 | CHICKEN3_DGMG_DONE_FIX_DISABLE); | |
6312 | ||
ecdb4eb7 | 6313 | /* WaDisablePSDDualDispatchEnable:ivb */ |
12f3382b JB |
6314 | if (IS_IVB_GT1(dev)) |
6315 | I915_WRITE(GEN7_HALF_SLICE_CHICKEN1, | |
6316 | _MASKED_BIT_ENABLE(GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE)); | |
12f3382b | 6317 | |
4e04632e AG |
6318 | /* WaDisable_RenderCache_OperationalFlush:ivb */ |
6319 | I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE)); | |
6320 | ||
ecdb4eb7 | 6321 | /* Apply the WaDisableRHWOOptimizationForRenderHang:ivb workaround. */ |
6f1d69b0 ED |
6322 | I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1, |
6323 | GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC); | |
6324 | ||
ecdb4eb7 | 6325 | /* WaApplyL3ControlAndL3ChickenMode:ivb */ |
6f1d69b0 ED |
6326 | I915_WRITE(GEN7_L3CNTLREG1, |
6327 | GEN7_WA_FOR_GEN7_L3_CONTROL); | |
6328 | I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER, | |
8ab43976 JB |
6329 | GEN7_WA_L3_CHICKEN_MODE); |
6330 | if (IS_IVB_GT1(dev)) | |
6331 | I915_WRITE(GEN7_ROW_CHICKEN2, | |
6332 | _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE)); | |
412236c2 VS |
6333 | else { |
6334 | /* must write both registers */ | |
6335 | I915_WRITE(GEN7_ROW_CHICKEN2, | |
6336 | _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE)); | |
8ab43976 JB |
6337 | I915_WRITE(GEN7_ROW_CHICKEN2_GT2, |
6338 | _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE)); | |
412236c2 | 6339 | } |
6f1d69b0 | 6340 | |
ecdb4eb7 | 6341 | /* WaForceL3Serialization:ivb */ |
61939d97 JB |
6342 | I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) & |
6343 | ~L3SQ_URB_READ_CAM_MATCH_DISABLE); | |
6344 | ||
1b80a19a | 6345 | /* |
0f846f81 | 6346 | * According to the spec, bit 13 (RCZUNIT) must be set on IVB. |
ecdb4eb7 | 6347 | * This implements the WaDisableRCZUnitClockGating:ivb workaround. |
0f846f81 JB |
6348 | */ |
6349 | I915_WRITE(GEN6_UCGCTL2, | |
28acf3b2 | 6350 | GEN6_RCZUNIT_CLOCK_GATE_DISABLE); |
0f846f81 | 6351 | |
ecdb4eb7 | 6352 | /* This is required by WaCatErrorRejectionIssue:ivb */ |
6f1d69b0 ED |
6353 | I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG, |
6354 | I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) | | |
6355 | GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB); | |
6356 | ||
0e088b8f | 6357 | g4x_disable_trickle_feed(dev); |
6f1d69b0 ED |
6358 | |
6359 | gen7_setup_fixed_func_scheduler(dev_priv); | |
97e1930f | 6360 | |
22721343 CW |
6361 | if (0) { /* causes HiZ corruption on ivb:gt1 */ |
6362 | /* enable HiZ Raw Stall Optimization */ | |
6363 | I915_WRITE(CACHE_MODE_0_GEN7, | |
6364 | _MASKED_BIT_DISABLE(HIZ_RAW_STALL_OPT_DISABLE)); | |
6365 | } | |
116f2b6d | 6366 | |
ecdb4eb7 | 6367 | /* WaDisable4x2SubspanOptimization:ivb */ |
97e1930f DV |
6368 | I915_WRITE(CACHE_MODE_1, |
6369 | _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE)); | |
20848223 | 6370 | |
a607c1a4 VS |
6371 | /* |
6372 | * BSpec recommends 8x4 when MSAA is used, | |
6373 | * however in practice 16x4 seems fastest. | |
c5c98a58 VS |
6374 | * |
6375 | * Note that PS/WM thread counts depend on the WIZ hashing | |
6376 | * disable bit, which we don't touch here, but it's good | |
6377 | * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM). | |
a607c1a4 VS |
6378 | */ |
6379 | I915_WRITE(GEN7_GT_MODE, | |
98533251 | 6380 | _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4)); |
a607c1a4 | 6381 | |
20848223 BW |
6382 | snpcr = I915_READ(GEN6_MBCUNIT_SNPCR); |
6383 | snpcr &= ~GEN6_MBC_SNPCR_MASK; | |
6384 | snpcr |= GEN6_MBC_SNPCR_MED; | |
6385 | I915_WRITE(GEN6_MBCUNIT_SNPCR, snpcr); | |
3107bd48 | 6386 | |
ab5c608b BW |
6387 | if (!HAS_PCH_NOP(dev)) |
6388 | cpt_init_clock_gating(dev); | |
1d7aaa0c DV |
6389 | |
6390 | gen6_check_mch_setup(dev); | |
6f1d69b0 ED |
6391 | } |
6392 | ||
c6beb13e VS |
6393 | static void vlv_init_display_clock_gating(struct drm_i915_private *dev_priv) |
6394 | { | |
6395 | I915_WRITE(DSPCLK_GATE_D, VRHUNIT_CLOCK_GATE_DISABLE); | |
6396 | ||
6397 | /* | |
6398 | * Disable trickle feed and enable pnd deadline calculation | |
6399 | */ | |
6400 | I915_WRITE(MI_ARB_VLV, MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE); | |
6401 | I915_WRITE(CBR1_VLV, 0); | |
6402 | } | |
6403 | ||
1fa61106 | 6404 | static void valleyview_init_clock_gating(struct drm_device *dev) |
6f1d69b0 ED |
6405 | { |
6406 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6f1d69b0 | 6407 | |
c6beb13e | 6408 | vlv_init_display_clock_gating(dev_priv); |
6f1d69b0 | 6409 | |
ecdb4eb7 | 6410 | /* WaDisableEarlyCull:vlv */ |
87f8020e JB |
6411 | I915_WRITE(_3D_CHICKEN3, |
6412 | _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL)); | |
6413 | ||
ecdb4eb7 | 6414 | /* WaDisableBackToBackFlipFix:vlv */ |
6f1d69b0 ED |
6415 | I915_WRITE(IVB_CHICKEN3, |
6416 | CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE | | |
6417 | CHICKEN3_DGMG_DONE_FIX_DISABLE); | |
6418 | ||
fad7d36e | 6419 | /* WaPsdDispatchEnable:vlv */ |
ecdb4eb7 | 6420 | /* WaDisablePSDDualDispatchEnable:vlv */ |
12f3382b | 6421 | I915_WRITE(GEN7_HALF_SLICE_CHICKEN1, |
d3bc0303 JB |
6422 | _MASKED_BIT_ENABLE(GEN7_MAX_PS_THREAD_DEP | |
6423 | GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE)); | |
12f3382b | 6424 | |
4e04632e AG |
6425 | /* WaDisable_RenderCache_OperationalFlush:vlv */ |
6426 | I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE)); | |
6427 | ||
ecdb4eb7 | 6428 | /* WaForceL3Serialization:vlv */ |
61939d97 JB |
6429 | I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) & |
6430 | ~L3SQ_URB_READ_CAM_MATCH_DISABLE); | |
6431 | ||
ecdb4eb7 | 6432 | /* WaDisableDopClockGating:vlv */ |
8ab43976 JB |
6433 | I915_WRITE(GEN7_ROW_CHICKEN2, |
6434 | _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE)); | |
6435 | ||
ecdb4eb7 | 6436 | /* This is required by WaCatErrorRejectionIssue:vlv */ |
6f1d69b0 ED |
6437 | I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG, |
6438 | I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) | | |
6439 | GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB); | |
6440 | ||
46680e0a VS |
6441 | gen7_setup_fixed_func_scheduler(dev_priv); |
6442 | ||
3c0edaeb | 6443 | /* |
0f846f81 | 6444 | * According to the spec, bit 13 (RCZUNIT) must be set on IVB. |
ecdb4eb7 | 6445 | * This implements the WaDisableRCZUnitClockGating:vlv workaround. |
0f846f81 JB |
6446 | */ |
6447 | I915_WRITE(GEN6_UCGCTL2, | |
3c0edaeb | 6448 | GEN6_RCZUNIT_CLOCK_GATE_DISABLE); |
0f846f81 | 6449 | |
c98f5062 AG |
6450 | /* WaDisableL3Bank2xClockGate:vlv |
6451 | * Disabling L3 clock gating- MMIO 940c[25] = 1 | |
6452 | * Set bit 25, to disable L3_BANK_2x_CLK_GATING */ | |
6453 | I915_WRITE(GEN7_UCGCTL4, | |
6454 | I915_READ(GEN7_UCGCTL4) | GEN7_L3BANK2X_CLOCK_GATE_DISABLE); | |
e3f33d46 | 6455 | |
afd58e79 VS |
6456 | /* |
6457 | * BSpec says this must be set, even though | |
6458 | * WaDisable4x2SubspanOptimization isn't listed for VLV. | |
6459 | */ | |
6b26c86d DV |
6460 | I915_WRITE(CACHE_MODE_1, |
6461 | _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE)); | |
7983117f | 6462 | |
da2518f9 VS |
6463 | /* |
6464 | * BSpec recommends 8x4 when MSAA is used, | |
6465 | * however in practice 16x4 seems fastest. | |
6466 | * | |
6467 | * Note that PS/WM thread counts depend on the WIZ hashing | |
6468 | * disable bit, which we don't touch here, but it's good | |
6469 | * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM). | |
6470 | */ | |
6471 | I915_WRITE(GEN7_GT_MODE, | |
6472 | _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4)); | |
6473 | ||
031994ee VS |
6474 | /* |
6475 | * WaIncreaseL3CreditsForVLVB0:vlv | |
6476 | * This is the hardware default actually. | |
6477 | */ | |
6478 | I915_WRITE(GEN7_L3SQCREG1, VLV_B0_WA_L3SQCREG1_VALUE); | |
6479 | ||
2d809570 | 6480 | /* |
ecdb4eb7 | 6481 | * WaDisableVLVClockGating_VBIIssue:vlv |
2d809570 JB |
6482 | * Disable clock gating on th GCFG unit to prevent a delay |
6483 | * in the reporting of vblank events. | |
6484 | */ | |
7a0d1eed | 6485 | I915_WRITE(VLV_GUNIT_CLOCK_GATE, GCFG_DIS); |
6f1d69b0 ED |
6486 | } |
6487 | ||
a4565da8 VS |
6488 | static void cherryview_init_clock_gating(struct drm_device *dev) |
6489 | { | |
6490 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6491 | ||
c6beb13e | 6492 | vlv_init_display_clock_gating(dev_priv); |
dd811e70 | 6493 | |
232ce337 VS |
6494 | /* WaVSRefCountFullforceMissDisable:chv */ |
6495 | /* WaDSRefCountFullforceMissDisable:chv */ | |
6496 | I915_WRITE(GEN7_FF_THREAD_MODE, | |
6497 | I915_READ(GEN7_FF_THREAD_MODE) & | |
6498 | ~(GEN8_FF_DS_REF_CNT_FFME | GEN7_FF_VS_REF_CNT_FFME)); | |
acea6f95 VS |
6499 | |
6500 | /* WaDisableSemaphoreAndSyncFlipWait:chv */ | |
6501 | I915_WRITE(GEN6_RC_SLEEP_PSMI_CONTROL, | |
6502 | _MASKED_BIT_ENABLE(GEN8_RC_SEMA_IDLE_MSG_DISABLE)); | |
0846697c VS |
6503 | |
6504 | /* WaDisableCSUnitClockGating:chv */ | |
6505 | I915_WRITE(GEN6_UCGCTL1, I915_READ(GEN6_UCGCTL1) | | |
6506 | GEN6_CSUNIT_CLOCK_GATE_DISABLE); | |
c631780f VS |
6507 | |
6508 | /* WaDisableSDEUnitClockGating:chv */ | |
6509 | I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) | | |
6510 | GEN8_SDEUNIT_CLOCK_GATE_DISABLE); | |
6d50b065 VS |
6511 | |
6512 | /* | |
6513 | * GTT cache may not work with big pages, so if those | |
6514 | * are ever enabled GTT cache may need to be disabled. | |
6515 | */ | |
6516 | I915_WRITE(HSW_GTT_CACHE_EN, GTT_CACHE_EN_ALL); | |
a4565da8 VS |
6517 | } |
6518 | ||
1fa61106 | 6519 | static void g4x_init_clock_gating(struct drm_device *dev) |
6f1d69b0 ED |
6520 | { |
6521 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6522 | uint32_t dspclk_gate; | |
6523 | ||
6524 | I915_WRITE(RENCLK_GATE_D1, 0); | |
6525 | I915_WRITE(RENCLK_GATE_D2, VF_UNIT_CLOCK_GATE_DISABLE | | |
6526 | GS_UNIT_CLOCK_GATE_DISABLE | | |
6527 | CL_UNIT_CLOCK_GATE_DISABLE); | |
6528 | I915_WRITE(RAMCLK_GATE_D, 0); | |
6529 | dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE | | |
6530 | OVRUNIT_CLOCK_GATE_DISABLE | | |
6531 | OVCUNIT_CLOCK_GATE_DISABLE; | |
6532 | if (IS_GM45(dev)) | |
6533 | dspclk_gate |= DSSUNIT_CLOCK_GATE_DISABLE; | |
6534 | I915_WRITE(DSPCLK_GATE_D, dspclk_gate); | |
4358a374 DV |
6535 | |
6536 | /* WaDisableRenderCachePipelinedFlush */ | |
6537 | I915_WRITE(CACHE_MODE_0, | |
6538 | _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE)); | |
de1aa629 | 6539 | |
4e04632e AG |
6540 | /* WaDisable_RenderCache_OperationalFlush:g4x */ |
6541 | I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE)); | |
6542 | ||
0e088b8f | 6543 | g4x_disable_trickle_feed(dev); |
6f1d69b0 ED |
6544 | } |
6545 | ||
1fa61106 | 6546 | static void crestline_init_clock_gating(struct drm_device *dev) |
6f1d69b0 ED |
6547 | { |
6548 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6549 | ||
6550 | I915_WRITE(RENCLK_GATE_D1, I965_RCC_CLOCK_GATE_DISABLE); | |
6551 | I915_WRITE(RENCLK_GATE_D2, 0); | |
6552 | I915_WRITE(DSPCLK_GATE_D, 0); | |
6553 | I915_WRITE(RAMCLK_GATE_D, 0); | |
6554 | I915_WRITE16(DEUC, 0); | |
20f94967 VS |
6555 | I915_WRITE(MI_ARB_STATE, |
6556 | _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE)); | |
4e04632e AG |
6557 | |
6558 | /* WaDisable_RenderCache_OperationalFlush:gen4 */ | |
6559 | I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE)); | |
6f1d69b0 ED |
6560 | } |
6561 | ||
1fa61106 | 6562 | static void broadwater_init_clock_gating(struct drm_device *dev) |
6f1d69b0 ED |
6563 | { |
6564 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6565 | ||
6566 | I915_WRITE(RENCLK_GATE_D1, I965_RCZ_CLOCK_GATE_DISABLE | | |
6567 | I965_RCC_CLOCK_GATE_DISABLE | | |
6568 | I965_RCPB_CLOCK_GATE_DISABLE | | |
6569 | I965_ISC_CLOCK_GATE_DISABLE | | |
6570 | I965_FBC_CLOCK_GATE_DISABLE); | |
6571 | I915_WRITE(RENCLK_GATE_D2, 0); | |
20f94967 VS |
6572 | I915_WRITE(MI_ARB_STATE, |
6573 | _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE)); | |
4e04632e AG |
6574 | |
6575 | /* WaDisable_RenderCache_OperationalFlush:gen4 */ | |
6576 | I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE)); | |
6f1d69b0 ED |
6577 | } |
6578 | ||
1fa61106 | 6579 | static void gen3_init_clock_gating(struct drm_device *dev) |
6f1d69b0 ED |
6580 | { |
6581 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6582 | u32 dstate = I915_READ(D_STATE); | |
6583 | ||
6584 | dstate |= DSTATE_PLL_D3_OFF | DSTATE_GFX_CLOCK_GATING | | |
6585 | DSTATE_DOT_CLOCK_GATING; | |
6586 | I915_WRITE(D_STATE, dstate); | |
13a86b85 CW |
6587 | |
6588 | if (IS_PINEVIEW(dev)) | |
6589 | I915_WRITE(ECOSKPD, _MASKED_BIT_ENABLE(ECO_GATING_CX_ONLY)); | |
974a3b0f DV |
6590 | |
6591 | /* IIR "flip pending" means done if this bit is set */ | |
6592 | I915_WRITE(ECOSKPD, _MASKED_BIT_DISABLE(ECO_FLIP_DONE)); | |
12fabbcb VS |
6593 | |
6594 | /* interrupts should cause a wake up from C3 */ | |
3299254f | 6595 | I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_AGPBUSY_INT_EN)); |
dbb42748 VS |
6596 | |
6597 | /* On GEN3 we really need to make sure the ARB C3 LP bit is set */ | |
6598 | I915_WRITE(MI_ARB_STATE, _MASKED_BIT_ENABLE(MI_ARB_C3_LP_WRITE_ENABLE)); | |
1038392b VS |
6599 | |
6600 | I915_WRITE(MI_ARB_STATE, | |
6601 | _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE)); | |
6f1d69b0 ED |
6602 | } |
6603 | ||
1fa61106 | 6604 | static void i85x_init_clock_gating(struct drm_device *dev) |
6f1d69b0 ED |
6605 | { |
6606 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6607 | ||
6608 | I915_WRITE(RENCLK_GATE_D1, SV_CLOCK_GATE_DISABLE); | |
54e472ae VS |
6609 | |
6610 | /* interrupts should cause a wake up from C3 */ | |
6611 | I915_WRITE(MI_STATE, _MASKED_BIT_ENABLE(MI_AGPBUSY_INT_EN) | | |
6612 | _MASKED_BIT_DISABLE(MI_AGPBUSY_830_MODE)); | |
1038392b VS |
6613 | |
6614 | I915_WRITE(MEM_MODE, | |
6615 | _MASKED_BIT_ENABLE(MEM_DISPLAY_TRICKLE_FEED_DISABLE)); | |
6f1d69b0 ED |
6616 | } |
6617 | ||
1fa61106 | 6618 | static void i830_init_clock_gating(struct drm_device *dev) |
6f1d69b0 ED |
6619 | { |
6620 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6621 | ||
6622 | I915_WRITE(DSPCLK_GATE_D, OVRUNIT_CLOCK_GATE_DISABLE); | |
1038392b VS |
6623 | |
6624 | I915_WRITE(MEM_MODE, | |
6625 | _MASKED_BIT_ENABLE(MEM_DISPLAY_A_TRICKLE_FEED_DISABLE) | | |
6626 | _MASKED_BIT_ENABLE(MEM_DISPLAY_B_TRICKLE_FEED_DISABLE)); | |
6f1d69b0 ED |
6627 | } |
6628 | ||
6f1d69b0 ED |
6629 | void intel_init_clock_gating(struct drm_device *dev) |
6630 | { | |
6631 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6632 | ||
c57e3551 DL |
6633 | if (dev_priv->display.init_clock_gating) |
6634 | dev_priv->display.init_clock_gating(dev); | |
6f1d69b0 ED |
6635 | } |
6636 | ||
7d708ee4 ID |
6637 | void intel_suspend_hw(struct drm_device *dev) |
6638 | { | |
6639 | if (HAS_PCH_LPT(dev)) | |
6640 | lpt_suspend_hw(dev); | |
6641 | } | |
6642 | ||
1fa61106 ED |
6643 | /* Set up chip specific power management-related functions */ |
6644 | void intel_init_pm(struct drm_device *dev) | |
6645 | { | |
6646 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6647 | ||
7ff0ebcc | 6648 | intel_fbc_init(dev_priv); |
1fa61106 | 6649 | |
c921aba8 DV |
6650 | /* For cxsr */ |
6651 | if (IS_PINEVIEW(dev)) | |
6652 | i915_pineview_get_mem_freq(dev); | |
6653 | else if (IS_GEN5(dev)) | |
6654 | i915_ironlake_get_mem_freq(dev); | |
6655 | ||
1fa61106 | 6656 | /* For FIFO watermark updates */ |
f5ed50cb | 6657 | if (INTEL_INFO(dev)->gen >= 9) { |
2af30a5c PB |
6658 | skl_setup_wm_latency(dev); |
6659 | ||
a82abe43 ID |
6660 | if (IS_BROXTON(dev)) |
6661 | dev_priv->display.init_clock_gating = | |
6662 | bxt_init_clock_gating; | |
6663 | else if (IS_SKYLAKE(dev)) | |
6664 | dev_priv->display.init_clock_gating = | |
6665 | skl_init_clock_gating; | |
2d41c0b5 PB |
6666 | dev_priv->display.update_wm = skl_update_wm; |
6667 | dev_priv->display.update_sprite_wm = skl_update_sprite_wm; | |
c83155a6 | 6668 | } else if (HAS_PCH_SPLIT(dev)) { |
fa50ad61 | 6669 | ilk_setup_wm_latency(dev); |
53615a5e | 6670 | |
bd602544 VS |
6671 | if ((IS_GEN5(dev) && dev_priv->wm.pri_latency[1] && |
6672 | dev_priv->wm.spr_latency[1] && dev_priv->wm.cur_latency[1]) || | |
6673 | (!IS_GEN5(dev) && dev_priv->wm.pri_latency[0] && | |
6674 | dev_priv->wm.spr_latency[0] && dev_priv->wm.cur_latency[0])) { | |
6675 | dev_priv->display.update_wm = ilk_update_wm; | |
6676 | dev_priv->display.update_sprite_wm = ilk_update_sprite_wm; | |
6677 | } else { | |
6678 | DRM_DEBUG_KMS("Failed to read display plane latency. " | |
6679 | "Disable CxSR\n"); | |
6680 | } | |
6681 | ||
6682 | if (IS_GEN5(dev)) | |
1fa61106 | 6683 | dev_priv->display.init_clock_gating = ironlake_init_clock_gating; |
bd602544 | 6684 | else if (IS_GEN6(dev)) |
1fa61106 | 6685 | dev_priv->display.init_clock_gating = gen6_init_clock_gating; |
bd602544 | 6686 | else if (IS_IVYBRIDGE(dev)) |
1fa61106 | 6687 | dev_priv->display.init_clock_gating = ivybridge_init_clock_gating; |
bd602544 | 6688 | else if (IS_HASWELL(dev)) |
cad2a2d7 | 6689 | dev_priv->display.init_clock_gating = haswell_init_clock_gating; |
bd602544 | 6690 | else if (INTEL_INFO(dev)->gen == 8) |
47c2bd97 | 6691 | dev_priv->display.init_clock_gating = broadwell_init_clock_gating; |
a4565da8 | 6692 | } else if (IS_CHERRYVIEW(dev)) { |
ae80152d | 6693 | dev_priv->display.update_wm = valleyview_update_wm; |
01e184cc | 6694 | dev_priv->display.update_sprite_wm = valleyview_update_sprite_wm; |
a4565da8 VS |
6695 | dev_priv->display.init_clock_gating = |
6696 | cherryview_init_clock_gating; | |
1fa61106 ED |
6697 | } else if (IS_VALLEYVIEW(dev)) { |
6698 | dev_priv->display.update_wm = valleyview_update_wm; | |
01e184cc | 6699 | dev_priv->display.update_sprite_wm = valleyview_update_sprite_wm; |
1fa61106 ED |
6700 | dev_priv->display.init_clock_gating = |
6701 | valleyview_init_clock_gating; | |
1fa61106 ED |
6702 | } else if (IS_PINEVIEW(dev)) { |
6703 | if (!intel_get_cxsr_latency(IS_PINEVIEW_G(dev), | |
6704 | dev_priv->is_ddr3, | |
6705 | dev_priv->fsb_freq, | |
6706 | dev_priv->mem_freq)) { | |
6707 | DRM_INFO("failed to find known CxSR latency " | |
6708 | "(found ddr%s fsb freq %d, mem freq %d), " | |
6709 | "disabling CxSR\n", | |
6710 | (dev_priv->is_ddr3 == 1) ? "3" : "2", | |
6711 | dev_priv->fsb_freq, dev_priv->mem_freq); | |
6712 | /* Disable CxSR and never update its watermark again */ | |
5209b1f4 | 6713 | intel_set_memory_cxsr(dev_priv, false); |
1fa61106 ED |
6714 | dev_priv->display.update_wm = NULL; |
6715 | } else | |
6716 | dev_priv->display.update_wm = pineview_update_wm; | |
6717 | dev_priv->display.init_clock_gating = gen3_init_clock_gating; | |
6718 | } else if (IS_G4X(dev)) { | |
6719 | dev_priv->display.update_wm = g4x_update_wm; | |
6720 | dev_priv->display.init_clock_gating = g4x_init_clock_gating; | |
6721 | } else if (IS_GEN4(dev)) { | |
6722 | dev_priv->display.update_wm = i965_update_wm; | |
6723 | if (IS_CRESTLINE(dev)) | |
6724 | dev_priv->display.init_clock_gating = crestline_init_clock_gating; | |
6725 | else if (IS_BROADWATER(dev)) | |
6726 | dev_priv->display.init_clock_gating = broadwater_init_clock_gating; | |
6727 | } else if (IS_GEN3(dev)) { | |
6728 | dev_priv->display.update_wm = i9xx_update_wm; | |
6729 | dev_priv->display.get_fifo_size = i9xx_get_fifo_size; | |
6730 | dev_priv->display.init_clock_gating = gen3_init_clock_gating; | |
feb56b93 DV |
6731 | } else if (IS_GEN2(dev)) { |
6732 | if (INTEL_INFO(dev)->num_pipes == 1) { | |
6733 | dev_priv->display.update_wm = i845_update_wm; | |
1fa61106 | 6734 | dev_priv->display.get_fifo_size = i845_get_fifo_size; |
feb56b93 DV |
6735 | } else { |
6736 | dev_priv->display.update_wm = i9xx_update_wm; | |
1fa61106 | 6737 | dev_priv->display.get_fifo_size = i830_get_fifo_size; |
feb56b93 DV |
6738 | } |
6739 | ||
6740 | if (IS_I85X(dev) || IS_I865G(dev)) | |
6741 | dev_priv->display.init_clock_gating = i85x_init_clock_gating; | |
6742 | else | |
6743 | dev_priv->display.init_clock_gating = i830_init_clock_gating; | |
6744 | } else { | |
6745 | DRM_ERROR("unexpected fall-through in intel_init_pm\n"); | |
1fa61106 ED |
6746 | } |
6747 | } | |
6748 | ||
151a49d0 | 6749 | int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u32 mbox, u32 *val) |
42c0526c | 6750 | { |
4fc688ce | 6751 | WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock)); |
42c0526c BW |
6752 | |
6753 | if (I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) { | |
6754 | DRM_DEBUG_DRIVER("warning: pcode (read) mailbox access failed\n"); | |
6755 | return -EAGAIN; | |
6756 | } | |
6757 | ||
6758 | I915_WRITE(GEN6_PCODE_DATA, *val); | |
dddab346 | 6759 | I915_WRITE(GEN6_PCODE_DATA1, 0); |
42c0526c BW |
6760 | I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY | mbox); |
6761 | ||
6762 | if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0, | |
6763 | 500)) { | |
6764 | DRM_ERROR("timeout waiting for pcode read (%d) to finish\n", mbox); | |
6765 | return -ETIMEDOUT; | |
6766 | } | |
6767 | ||
6768 | *val = I915_READ(GEN6_PCODE_DATA); | |
6769 | I915_WRITE(GEN6_PCODE_DATA, 0); | |
6770 | ||
6771 | return 0; | |
6772 | } | |
6773 | ||
151a49d0 | 6774 | int sandybridge_pcode_write(struct drm_i915_private *dev_priv, u32 mbox, u32 val) |
42c0526c | 6775 | { |
4fc688ce | 6776 | WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock)); |
42c0526c BW |
6777 | |
6778 | if (I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) { | |
6779 | DRM_DEBUG_DRIVER("warning: pcode (write) mailbox access failed\n"); | |
6780 | return -EAGAIN; | |
6781 | } | |
6782 | ||
6783 | I915_WRITE(GEN6_PCODE_DATA, val); | |
6784 | I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY | mbox); | |
6785 | ||
6786 | if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0, | |
6787 | 500)) { | |
6788 | DRM_ERROR("timeout waiting for pcode write (%d) to finish\n", mbox); | |
6789 | return -ETIMEDOUT; | |
6790 | } | |
6791 | ||
6792 | I915_WRITE(GEN6_PCODE_DATA, 0); | |
6793 | ||
6794 | return 0; | |
6795 | } | |
a0e4e199 | 6796 | |
dd06f88c | 6797 | static int vlv_gpu_freq_div(unsigned int czclk_freq) |
855ba3be | 6798 | { |
dd06f88c VS |
6799 | switch (czclk_freq) { |
6800 | case 200: | |
6801 | return 10; | |
6802 | case 267: | |
6803 | return 12; | |
6804 | case 320: | |
6805 | case 333: | |
dd06f88c | 6806 | return 16; |
ab3fb157 VS |
6807 | case 400: |
6808 | return 20; | |
855ba3be JB |
6809 | default: |
6810 | return -1; | |
6811 | } | |
dd06f88c | 6812 | } |
855ba3be | 6813 | |
dd06f88c VS |
6814 | static int byt_gpu_freq(struct drm_i915_private *dev_priv, int val) |
6815 | { | |
6816 | int div, czclk_freq = DIV_ROUND_CLOSEST(dev_priv->mem_freq, 4); | |
6817 | ||
6818 | div = vlv_gpu_freq_div(czclk_freq); | |
6819 | if (div < 0) | |
6820 | return div; | |
6821 | ||
6822 | return DIV_ROUND_CLOSEST(czclk_freq * (val + 6 - 0xbd), div); | |
855ba3be JB |
6823 | } |
6824 | ||
b55dd647 | 6825 | static int byt_freq_opcode(struct drm_i915_private *dev_priv, int val) |
855ba3be | 6826 | { |
dd06f88c | 6827 | int mul, czclk_freq = DIV_ROUND_CLOSEST(dev_priv->mem_freq, 4); |
855ba3be | 6828 | |
dd06f88c VS |
6829 | mul = vlv_gpu_freq_div(czclk_freq); |
6830 | if (mul < 0) | |
6831 | return mul; | |
855ba3be | 6832 | |
dd06f88c | 6833 | return DIV_ROUND_CLOSEST(mul * val, czclk_freq) + 0xbd - 6; |
855ba3be JB |
6834 | } |
6835 | ||
b55dd647 | 6836 | static int chv_gpu_freq(struct drm_i915_private *dev_priv, int val) |
22b1b2f8 | 6837 | { |
dd06f88c | 6838 | int div, czclk_freq = dev_priv->rps.cz_freq; |
22b1b2f8 | 6839 | |
dd06f88c VS |
6840 | div = vlv_gpu_freq_div(czclk_freq) / 2; |
6841 | if (div < 0) | |
6842 | return div; | |
22b1b2f8 | 6843 | |
dd06f88c | 6844 | return DIV_ROUND_CLOSEST(czclk_freq * val, 2 * div) / 2; |
22b1b2f8 D |
6845 | } |
6846 | ||
b55dd647 | 6847 | static int chv_freq_opcode(struct drm_i915_private *dev_priv, int val) |
22b1b2f8 | 6848 | { |
dd06f88c | 6849 | int mul, czclk_freq = dev_priv->rps.cz_freq; |
22b1b2f8 | 6850 | |
dd06f88c VS |
6851 | mul = vlv_gpu_freq_div(czclk_freq) / 2; |
6852 | if (mul < 0) | |
6853 | return mul; | |
22b1b2f8 | 6854 | |
1c14762d | 6855 | /* CHV needs even values */ |
dd06f88c | 6856 | return DIV_ROUND_CLOSEST(val * 2 * mul, czclk_freq) * 2; |
22b1b2f8 D |
6857 | } |
6858 | ||
616bc820 | 6859 | int intel_gpu_freq(struct drm_i915_private *dev_priv, int val) |
22b1b2f8 | 6860 | { |
80b6dda4 AG |
6861 | if (IS_GEN9(dev_priv->dev)) |
6862 | return (val * GT_FREQUENCY_MULTIPLIER) / GEN9_FREQ_SCALER; | |
6863 | else if (IS_CHERRYVIEW(dev_priv->dev)) | |
616bc820 | 6864 | return chv_gpu_freq(dev_priv, val); |
22b1b2f8 | 6865 | else if (IS_VALLEYVIEW(dev_priv->dev)) |
616bc820 VS |
6866 | return byt_gpu_freq(dev_priv, val); |
6867 | else | |
6868 | return val * GT_FREQUENCY_MULTIPLIER; | |
22b1b2f8 D |
6869 | } |
6870 | ||
616bc820 VS |
6871 | int intel_freq_opcode(struct drm_i915_private *dev_priv, int val) |
6872 | { | |
80b6dda4 AG |
6873 | if (IS_GEN9(dev_priv->dev)) |
6874 | return (val * GEN9_FREQ_SCALER) / GT_FREQUENCY_MULTIPLIER; | |
6875 | else if (IS_CHERRYVIEW(dev_priv->dev)) | |
616bc820 | 6876 | return chv_freq_opcode(dev_priv, val); |
22b1b2f8 | 6877 | else if (IS_VALLEYVIEW(dev_priv->dev)) |
616bc820 VS |
6878 | return byt_freq_opcode(dev_priv, val); |
6879 | else | |
6880 | return val / GT_FREQUENCY_MULTIPLIER; | |
6881 | } | |
22b1b2f8 | 6882 | |
6ad790c0 CW |
6883 | struct request_boost { |
6884 | struct work_struct work; | |
eed29a5b | 6885 | struct drm_i915_gem_request *req; |
6ad790c0 CW |
6886 | }; |
6887 | ||
6888 | static void __intel_rps_boost_work(struct work_struct *work) | |
6889 | { | |
6890 | struct request_boost *boost = container_of(work, struct request_boost, work); | |
e61b9958 | 6891 | struct drm_i915_gem_request *req = boost->req; |
6ad790c0 | 6892 | |
e61b9958 CW |
6893 | if (!i915_gem_request_completed(req, true)) |
6894 | gen6_rps_boost(to_i915(req->ring->dev), NULL, | |
6895 | req->emitted_jiffies); | |
6ad790c0 | 6896 | |
e61b9958 | 6897 | i915_gem_request_unreference__unlocked(req); |
6ad790c0 CW |
6898 | kfree(boost); |
6899 | } | |
6900 | ||
6901 | void intel_queue_rps_boost_for_request(struct drm_device *dev, | |
eed29a5b | 6902 | struct drm_i915_gem_request *req) |
6ad790c0 CW |
6903 | { |
6904 | struct request_boost *boost; | |
6905 | ||
eed29a5b | 6906 | if (req == NULL || INTEL_INFO(dev)->gen < 6) |
6ad790c0 CW |
6907 | return; |
6908 | ||
e61b9958 CW |
6909 | if (i915_gem_request_completed(req, true)) |
6910 | return; | |
6911 | ||
6ad790c0 CW |
6912 | boost = kmalloc(sizeof(*boost), GFP_ATOMIC); |
6913 | if (boost == NULL) | |
6914 | return; | |
6915 | ||
eed29a5b DV |
6916 | i915_gem_request_reference(req); |
6917 | boost->req = req; | |
6ad790c0 CW |
6918 | |
6919 | INIT_WORK(&boost->work, __intel_rps_boost_work); | |
6920 | queue_work(to_i915(dev)->wq, &boost->work); | |
6921 | } | |
6922 | ||
f742a552 | 6923 | void intel_pm_setup(struct drm_device *dev) |
907b28c5 CW |
6924 | { |
6925 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6926 | ||
f742a552 | 6927 | mutex_init(&dev_priv->rps.hw_lock); |
8d3afd7d | 6928 | spin_lock_init(&dev_priv->rps.client_lock); |
f742a552 | 6929 | |
907b28c5 CW |
6930 | INIT_DELAYED_WORK(&dev_priv->rps.delayed_resume_work, |
6931 | intel_gen6_powersave_work); | |
1854d5ca | 6932 | INIT_LIST_HEAD(&dev_priv->rps.clients); |
2e1b8730 CW |
6933 | INIT_LIST_HEAD(&dev_priv->rps.semaphores.link); |
6934 | INIT_LIST_HEAD(&dev_priv->rps.mmioflips.link); | |
5d584b2e | 6935 | |
33688d95 | 6936 | dev_priv->pm.suspended = false; |
907b28c5 | 6937 | } |