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drm/i915: move FBC vfuncs to struct i915_fbc
[mirror_ubuntu-artful-kernel.git] / drivers / gpu / drm / i915 / intel_pm.c
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85208be0
ED		 1/*
2 * Copyright © 2012 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eugeni Dodonov <eugeni.dodonov@intel.com>
25 *
26 */
27
2b4e57bd 28#include <linux/cpufreq.h>
85208be0
ED		 29#include "i915_drv.h"
30#include "intel_drv.h"
eb48eb00
DV		 31#include "../../../platform/x86/intel_ips.h"
32#include <linux/module.h>
85208be0 33
dc39fff7
BW		 34/**
35 * RC6 is a special power stage which allows the GPU to enter an very
36 * low-voltage mode when idle, using down to 0V while at this stage. This
37 * stage is entered automatically when the GPU is idle when RC6 support is
38 * enabled, and as soon as new workload arises GPU wakes up automatically as well.
39 *
40 * There are different RC6 modes available in Intel GPU, which differentiate
41 * among each other with the latency required to enter and leave RC6 and
42 * voltage consumed by the GPU in different states.
43 *
44 * The combination of the following flags define which states GPU is allowed
45 * to enter, while RC6 is the normal RC6 state, RC6p is the deep RC6, and
46 * RC6pp is deepest RC6. Their support by hardware varies according to the
47 * GPU, BIOS, chipset and platform. RC6 is usually the safest one and the one
48 * which brings the most power savings; deeper states save more power, but
49 * require higher latency to switch to and wake up.
50 */
51#define INTEL_RC6_ENABLE (1<<0)
52#define INTEL_RC6p_ENABLE (1<<1)
53#define INTEL_RC6pp_ENABLE (1<<2)
54
da2078cd
DL		 55static void gen9_init_clock_gating(struct drm_device *dev)
56{
acd5c346
DL		 57 struct drm_i915_private *dev_priv = dev->dev_private;
58
77719d28
DL		 59 /* WaEnableLbsSlaRetryTimerDecrement:skl */
60 I915_WRITE(BDW_SCRATCH1, I915_READ(BDW_SCRATCH1) |
61 GEN9_LBS_SLA_RETRY_TIMER_DECREMENT_ENABLE);
62}
91e41d16 63
45db2194 64static void skl_init_clock_gating(struct drm_device *dev)
da2078cd 65{
acd5c346 66 struct drm_i915_private *dev_priv = dev->dev_private;
3ca5da43 67
77719d28
DL		 68 gen9_init_clock_gating(dev);
69
669506e7 70 if (INTEL_REVID(dev) <= SKL_REVID_B0) {
3dcd020a
HN		 71 /*
72 * WaDisableSDEUnitClockGating:skl
9253c2e5 73 * WaSetGAPSunitClckGateDisable:skl
3dcd020a
HN		 74 */
75 I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
9253c2e5 76 GEN8_GAPSUNIT_CLOCK_GATE_DISABLE |
3dcd020a 77 GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
f9fc42f4
DL		 78
79 /* WaDisableVFUnitClockGating:skl */
80 I915_WRITE(GEN6_UCGCTL2, I915_READ(GEN6_UCGCTL2) |
81 GEN6_VFUNIT_CLOCK_GATE_DISABLE);
3dcd020a 82 }
8bc0ccf6 83
2caa3b26 84 if (INTEL_REVID(dev) <= SKL_REVID_D0) {
81e231af
DL		 85 /* WaDisableHDCInvalidation:skl */
86 I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) |
87 BDW_DISABLE_HDC_INVALIDATION);
88
2caa3b26
DL		 89 /* WaDisableChickenBitTSGBarrierAckForFFSliceCS:skl */
90 I915_WRITE(FF_SLICE_CS_CHICKEN2,
f1d3d34d 91 _MASKED_BIT_ENABLE(GEN9_TSG_BARRIER_ACK_DISABLE));
2caa3b26 92 }
81e231af 93
8bc0ccf6
DL		 94 if (INTEL_REVID(dev) <= SKL_REVID_E0)
95 /* WaDisableLSQCROPERFforOCL:skl */
96 I915_WRITE(GEN8_L3SQCREG4, I915_READ(GEN8_L3SQCREG4) |
97 GEN8_LQSC_RO_PERF_DIS);
da2078cd
DL		 98}
99
a82abe43
ID		 100static void bxt_init_clock_gating(struct drm_device *dev)
101{
32608ca2
ID		 102 struct drm_i915_private *dev_priv = dev->dev_private;
103
a82abe43 104 gen9_init_clock_gating(dev);
32608ca2
ID		 105
106 /*
107 * FIXME:
108 * GEN8_SDEUNIT_CLOCK_GATE_DISABLE applies on A0 only.
868434c5 109 * GEN8_HDCUNIT_CLOCK_GATE_DISABLE_HDCREQ applies on 3x6 GT SKUs only.
32608ca2
ID		 110 */
111 /* WaDisableSDEUnitClockGating:bxt */
112 I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
868434c5
BW		 113 GEN8_SDEUNIT_CLOCK_GATE_DISABLE |
114 GEN8_HDCUNIT_CLOCK_GATE_DISABLE_HDCREQ);
32608ca2 115
e3a29055
RB		 116 /* FIXME: apply on A0 only */
117 I915_WRITE(TILECTL, I915_READ(TILECTL) | TILECTL_TLBPF);
a82abe43
ID		 118}
119
c921aba8
DV		 120static void i915_pineview_get_mem_freq(struct drm_device *dev)
121{
50227e1c 122 struct drm_i915_private *dev_priv = dev->dev_private;
c921aba8
DV		 123 u32 tmp;
124
125 tmp = I915_READ(CLKCFG);
126
127 switch (tmp & CLKCFG_FSB_MASK) {
128 case CLKCFG_FSB_533:
129 dev_priv->fsb_freq = 533; /* 133*4 */
130 break;
131 case CLKCFG_FSB_800:
132 dev_priv->fsb_freq = 800; /* 200*4 */
133 break;
134 case CLKCFG_FSB_667:
135 dev_priv->fsb_freq = 667; /* 167*4 */
136 break;
137 case CLKCFG_FSB_400:
138 dev_priv->fsb_freq = 400; /* 100*4 */
139 break;
140 }
141
142 switch (tmp & CLKCFG_MEM_MASK) {
143 case CLKCFG_MEM_533:
144 dev_priv->mem_freq = 533;
145 break;
146 case CLKCFG_MEM_667:
147 dev_priv->mem_freq = 667;
148 break;
149 case CLKCFG_MEM_800:
150 dev_priv->mem_freq = 800;
151 break;
152 }
153
154 /* detect pineview DDR3 setting */
155 tmp = I915_READ(CSHRDDR3CTL);
156 dev_priv->is_ddr3 = (tmp & CSHRDDR3CTL_DDR3) ? 1 : 0;
157}
158
159static void i915_ironlake_get_mem_freq(struct drm_device *dev)
160{
50227e1c 161 struct drm_i915_private *dev_priv = dev->dev_private;
c921aba8
DV		 162 u16 ddrpll, csipll;
163
164 ddrpll = I915_READ16(DDRMPLL1);
165 csipll = I915_READ16(CSIPLL0);
166
167 switch (ddrpll & 0xff) {
168 case 0xc:
169 dev_priv->mem_freq = 800;
170 break;
171 case 0x10:
172 dev_priv->mem_freq = 1066;
173 break;
174 case 0x14:
175 dev_priv->mem_freq = 1333;
176 break;
177 case 0x18:
178 dev_priv->mem_freq = 1600;
179 break;
180 default:
181 DRM_DEBUG_DRIVER("unknown memory frequency 0x%02x\n",
182 ddrpll & 0xff);
183 dev_priv->mem_freq = 0;
184 break;
185 }
186
20e4d407 187 dev_priv->ips.r_t = dev_priv->mem_freq;
c921aba8
DV		 188
189 switch (csipll & 0x3ff) {
190 case 0x00c:
191 dev_priv->fsb_freq = 3200;
192 break;
193 case 0x00e:
194 dev_priv->fsb_freq = 3733;
195 break;
196 case 0x010:
197 dev_priv->fsb_freq = 4266;
198 break;
199 case 0x012:
200 dev_priv->fsb_freq = 4800;
201 break;
202 case 0x014:
203 dev_priv->fsb_freq = 5333;
204 break;
205 case 0x016:
206 dev_priv->fsb_freq = 5866;
207 break;
208 case 0x018:
209 dev_priv->fsb_freq = 6400;
210 break;
211 default:
212 DRM_DEBUG_DRIVER("unknown fsb frequency 0x%04x\n",
213 csipll & 0x3ff);
214 dev_priv->fsb_freq = 0;
215 break;
216 }
217
218 if (dev_priv->fsb_freq == 3200) {
20e4d407 219 dev_priv->ips.c_m = 0;
c921aba8 220 } else if (dev_priv->fsb_freq > 3200 && dev_priv->fsb_freq <= 4800) {
20e4d407 221 dev_priv->ips.c_m = 1;
c921aba8 222 } else {
20e4d407 223 dev_priv->ips.c_m = 2;
c921aba8
DV		 224 }
225}
226
b445e3b0
ED		 227static const struct cxsr_latency cxsr_latency_table[] = {
228 {1, 0, 800, 400, 3382, 33382, 3983, 33983}, /* DDR2-400 SC */
229 {1, 0, 800, 667, 3354, 33354, 3807, 33807}, /* DDR2-667 SC */
230 {1, 0, 800, 800, 3347, 33347, 3763, 33763}, /* DDR2-800 SC */
231 {1, 1, 800, 667, 6420, 36420, 6873, 36873}, /* DDR3-667 SC */
232 {1, 1, 800, 800, 5902, 35902, 6318, 36318}, /* DDR3-800 SC */
233
234 {1, 0, 667, 400, 3400, 33400, 4021, 34021}, /* DDR2-400 SC */
235 {1, 0, 667, 667, 3372, 33372, 3845, 33845}, /* DDR2-667 SC */
236 {1, 0, 667, 800, 3386, 33386, 3822, 33822}, /* DDR2-800 SC */
237 {1, 1, 667, 667, 6438, 36438, 6911, 36911}, /* DDR3-667 SC */
238 {1, 1, 667, 800, 5941, 35941, 6377, 36377}, /* DDR3-800 SC */
239
240 {1, 0, 400, 400, 3472, 33472, 4173, 34173}, /* DDR2-400 SC */
241 {1, 0, 400, 667, 3443, 33443, 3996, 33996}, /* DDR2-667 SC */
242 {1, 0, 400, 800, 3430, 33430, 3946, 33946}, /* DDR2-800 SC */
243 {1, 1, 400, 667, 6509, 36509, 7062, 37062}, /* DDR3-667 SC */
244 {1, 1, 400, 800, 5985, 35985, 6501, 36501}, /* DDR3-800 SC */
245
246 {0, 0, 800, 400, 3438, 33438, 4065, 34065}, /* DDR2-400 SC */
247 {0, 0, 800, 667, 3410, 33410, 3889, 33889}, /* DDR2-667 SC */
248 {0, 0, 800, 800, 3403, 33403, 3845, 33845}, /* DDR2-800 SC */
249 {0, 1, 800, 667, 6476, 36476, 6955, 36955}, /* DDR3-667 SC */
250 {0, 1, 800, 800, 5958, 35958, 6400, 36400}, /* DDR3-800 SC */
251
252 {0, 0, 667, 400, 3456, 33456, 4103, 34106}, /* DDR2-400 SC */
253 {0, 0, 667, 667, 3428, 33428, 3927, 33927}, /* DDR2-667 SC */
254 {0, 0, 667, 800, 3443, 33443, 3905, 33905}, /* DDR2-800 SC */
255 {0, 1, 667, 667, 6494, 36494, 6993, 36993}, /* DDR3-667 SC */
256 {0, 1, 667, 800, 5998, 35998, 6460, 36460}, /* DDR3-800 SC */
257
258 {0, 0, 400, 400, 3528, 33528, 4255, 34255}, /* DDR2-400 SC */
259 {0, 0, 400, 667, 3500, 33500, 4079, 34079}, /* DDR2-667 SC */
260 {0, 0, 400, 800, 3487, 33487, 4029, 34029}, /* DDR2-800 SC */
261 {0, 1, 400, 667, 6566, 36566, 7145, 37145}, /* DDR3-667 SC */
262 {0, 1, 400, 800, 6042, 36042, 6584, 36584}, /* DDR3-800 SC */
263};
264
63c62275 265static const struct cxsr_latency *intel_get_cxsr_latency(int is_desktop,
b445e3b0
ED		 266 int is_ddr3,
267 int fsb,
268 int mem)
269{
270 const struct cxsr_latency *latency;
271 int i;
272
273 if (fsb == 0 || mem == 0)
274 return NULL;
275
276 for (i = 0; i < ARRAY_SIZE(cxsr_latency_table); i++) {
277 latency = &cxsr_latency_table[i];
278 if (is_desktop == latency->is_desktop &&
279 is_ddr3 == latency->is_ddr3 &&
280 fsb == latency->fsb_freq && mem == latency->mem_freq)
281 return latency;
282 }
283
284 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
285
286 return NULL;
287}
288
fc1ac8de
VS		 289static void chv_set_memory_dvfs(struct drm_i915_private *dev_priv, bool enable)
290{
291 u32 val;
292
293 mutex_lock(&dev_priv->rps.hw_lock);
294
295 val = vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2);
296 if (enable)
297 val &= ~FORCE_DDR_HIGH_FREQ;
298 else
299 val |= FORCE_DDR_HIGH_FREQ;
300 val &= ~FORCE_DDR_LOW_FREQ;
301 val |= FORCE_DDR_FREQ_REQ_ACK;
302 vlv_punit_write(dev_priv, PUNIT_REG_DDR_SETUP2, val);
303
304 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2) &
305 FORCE_DDR_FREQ_REQ_ACK) == 0, 3))
306 DRM_ERROR("timed out waiting for Punit DDR DVFS request\n");
307
308 mutex_unlock(&dev_priv->rps.hw_lock);
309}
310
cfb41411
VS		 311static void chv_set_memory_pm5(struct drm_i915_private *dev_priv, bool enable)
312{
313 u32 val;
314
315 mutex_lock(&dev_priv->rps.hw_lock);
316
317 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
318 if (enable)
319 val |= DSP_MAXFIFO_PM5_ENABLE;
320 else
321 val &= ~DSP_MAXFIFO_PM5_ENABLE;
322 vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
323
324 mutex_unlock(&dev_priv->rps.hw_lock);
325}
326
f4998963
VS		 327#define FW_WM(value, plane) \
328 (((value) << DSPFW_ ## plane ## _SHIFT) & DSPFW_ ## plane ## _MASK)
329
5209b1f4 330void intel_set_memory_cxsr(struct drm_i915_private *dev_priv, bool enable)
b445e3b0 331{
5209b1f4
ID		 332 struct drm_device *dev = dev_priv->dev;
333 u32 val;
b445e3b0 334
5209b1f4
ID		 335 if (IS_VALLEYVIEW(dev)) {
336 I915_WRITE(FW_BLC_SELF_VLV, enable ? FW_CSPWRDWNEN : 0);
a7a6c498 337 POSTING_READ(FW_BLC_SELF_VLV);
852eb00d 338 dev_priv->wm.vlv.cxsr = enable;
5209b1f4
ID		 339 } else if (IS_G4X(dev) || IS_CRESTLINE(dev)) {
340 I915_WRITE(FW_BLC_SELF, enable ? FW_BLC_SELF_EN : 0);
a7a6c498 341 POSTING_READ(FW_BLC_SELF);
5209b1f4
ID		 342 } else if (IS_PINEVIEW(dev)) {
343 val = I915_READ(DSPFW3) & ~PINEVIEW_SELF_REFRESH_EN;
344 val |= enable ? PINEVIEW_SELF_REFRESH_EN : 0;
345 I915_WRITE(DSPFW3, val);
a7a6c498 346 POSTING_READ(DSPFW3);
5209b1f4
ID		 347 } else if (IS_I945G(dev) || IS_I945GM(dev)) {
348 val = enable ? _MASKED_BIT_ENABLE(FW_BLC_SELF_EN) :
349 _MASKED_BIT_DISABLE(FW_BLC_SELF_EN);
350 I915_WRITE(FW_BLC_SELF, val);
a7a6c498 351 POSTING_READ(FW_BLC_SELF);
5209b1f4
ID		 352 } else if (IS_I915GM(dev)) {
353 val = enable ? _MASKED_BIT_ENABLE(INSTPM_SELF_EN) :
354 _MASKED_BIT_DISABLE(INSTPM_SELF_EN);
355 I915_WRITE(INSTPM, val);
a7a6c498 356 POSTING_READ(INSTPM);
5209b1f4
ID		 357 } else {
358 return;
359 }
b445e3b0 360
5209b1f4
ID		 361 DRM_DEBUG_KMS("memory self-refresh is %s\n",
362 enable ? "enabled" : "disabled");
b445e3b0
ED		 363}
364
fc1ac8de 365
b445e3b0
ED		 366/*
367 * Latency for FIFO fetches is dependent on several factors:
368 * - memory configuration (speed, channels)
369 * - chipset
370 * - current MCH state
371 * It can be fairly high in some situations, so here we assume a fairly
372 * pessimal value. It's a tradeoff between extra memory fetches (if we
373 * set this value too high, the FIFO will fetch frequently to stay full)
374 * and power consumption (set it too low to save power and we might see
375 * FIFO underruns and display "flicker").
376 *
377 * A value of 5us seems to be a good balance; safe for very low end
378 * platforms but not overly aggressive on lower latency configs.
379 */
5aef6003 380static const int pessimal_latency_ns = 5000;
b445e3b0 381
b5004720
VS		 382#define VLV_FIFO_START(dsparb, dsparb2, lo_shift, hi_shift) \
383 ((((dsparb) >> (lo_shift)) & 0xff) | ((((dsparb2) >> (hi_shift)) & 0x1) << 8))
384
385static int vlv_get_fifo_size(struct drm_device *dev,
386 enum pipe pipe, int plane)
387{
388 struct drm_i915_private *dev_priv = dev->dev_private;
389 int sprite0_start, sprite1_start, size;
390
391 switch (pipe) {
392 uint32_t dsparb, dsparb2, dsparb3;
393 case PIPE_A:
394 dsparb = I915_READ(DSPARB);
395 dsparb2 = I915_READ(DSPARB2);
396 sprite0_start = VLV_FIFO_START(dsparb, dsparb2, 0, 0);
397 sprite1_start = VLV_FIFO_START(dsparb, dsparb2, 8, 4);
398 break;
399 case PIPE_B:
400 dsparb = I915_READ(DSPARB);
401 dsparb2 = I915_READ(DSPARB2);
402 sprite0_start = VLV_FIFO_START(dsparb, dsparb2, 16, 8);
403 sprite1_start = VLV_FIFO_START(dsparb, dsparb2, 24, 12);
404 break;
405 case PIPE_C:
406 dsparb2 = I915_READ(DSPARB2);
407 dsparb3 = I915_READ(DSPARB3);
408 sprite0_start = VLV_FIFO_START(dsparb3, dsparb2, 0, 16);
409 sprite1_start = VLV_FIFO_START(dsparb3, dsparb2, 8, 20);
410 break;
411 default:
412 return 0;
413 }
414
415 switch (plane) {
416 case 0:
417 size = sprite0_start;
418 break;
419 case 1:
420 size = sprite1_start - sprite0_start;
421 break;
422 case 2:
423 size = 512 - 1 - sprite1_start;
424 break;
425 default:
426 return 0;
427 }
428
429 DRM_DEBUG_KMS("Pipe %c %s %c FIFO size: %d\n",
430 pipe_name(pipe), plane == 0 ? "primary" : "sprite",
431 plane == 0 ? plane_name(pipe) : sprite_name(pipe, plane - 1),
432 size);
433
434 return size;
435}
436
1fa61106 437static int i9xx_get_fifo_size(struct drm_device *dev, int plane)
b445e3b0
ED		 438{
439 struct drm_i915_private *dev_priv = dev->dev_private;
440 uint32_t dsparb = I915_READ(DSPARB);
441 int size;
442
443 size = dsparb & 0x7f;
444 if (plane)
445 size = ((dsparb >> DSPARB_CSTART_SHIFT) & 0x7f) - size;
446
447 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
448 plane ? "B" : "A", size);
449
450 return size;
451}
452
feb56b93 453static int i830_get_fifo_size(struct drm_device *dev, int plane)
b445e3b0
ED		 454{
455 struct drm_i915_private *dev_priv = dev->dev_private;
456 uint32_t dsparb = I915_READ(DSPARB);
457 int size;
458
459 size = dsparb & 0x1ff;
460 if (plane)
461 size = ((dsparb >> DSPARB_BEND_SHIFT) & 0x1ff) - size;
462 size >>= 1; /* Convert to cachelines */
463
464 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
465 plane ? "B" : "A", size);
466
467 return size;
468}
469
1fa61106 470static int i845_get_fifo_size(struct drm_device *dev, int plane)
b445e3b0
ED		 471{
472 struct drm_i915_private *dev_priv = dev->dev_private;
473 uint32_t dsparb = I915_READ(DSPARB);
474 int size;
475
476 size = dsparb & 0x7f;
477 size >>= 2; /* Convert to cachelines */
478
479 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
480 plane ? "B" : "A",
481 size);
482
483 return size;
484}
485
b445e3b0
ED		 486/* Pineview has different values for various configs */
487static const struct intel_watermark_params pineview_display_wm = {
e0f0273e
VS		 488 .fifo_size = PINEVIEW_DISPLAY_FIFO,
489 .max_wm = PINEVIEW_MAX_WM,
490 .default_wm = PINEVIEW_DFT_WM,
491 .guard_size = PINEVIEW_GUARD_WM,
492 .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
b445e3b0
ED		 493};
494static const struct intel_watermark_params pineview_display_hplloff_wm = {
e0f0273e
VS		 495 .fifo_size = PINEVIEW_DISPLAY_FIFO,
496 .max_wm = PINEVIEW_MAX_WM,
497 .default_wm = PINEVIEW_DFT_HPLLOFF_WM,
498 .guard_size = PINEVIEW_GUARD_WM,
499 .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
b445e3b0
ED		 500};
501static const struct intel_watermark_params pineview_cursor_wm = {
e0f0273e
VS		 502 .fifo_size = PINEVIEW_CURSOR_FIFO,
503 .max_wm = PINEVIEW_CURSOR_MAX_WM,
504 .default_wm = PINEVIEW_CURSOR_DFT_WM,
505 .guard_size = PINEVIEW_CURSOR_GUARD_WM,
506 .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
b445e3b0
ED		 507};
508static const struct intel_watermark_params pineview_cursor_hplloff_wm = {
e0f0273e
VS		 509 .fifo_size = PINEVIEW_CURSOR_FIFO,
510 .max_wm = PINEVIEW_CURSOR_MAX_WM,
511 .default_wm = PINEVIEW_CURSOR_DFT_WM,
512 .guard_size = PINEVIEW_CURSOR_GUARD_WM,
513 .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
b445e3b0
ED		 514};
515static const struct intel_watermark_params g4x_wm_info = {
e0f0273e
VS		 516 .fifo_size = G4X_FIFO_SIZE,
517 .max_wm = G4X_MAX_WM,
518 .default_wm = G4X_MAX_WM,
519 .guard_size = 2,
520 .cacheline_size = G4X_FIFO_LINE_SIZE,
b445e3b0
ED		 521};
522static const struct intel_watermark_params g4x_cursor_wm_info = {
e0f0273e
VS		 523 .fifo_size = I965_CURSOR_FIFO,
524 .max_wm = I965_CURSOR_MAX_WM,
525 .default_wm = I965_CURSOR_DFT_WM,
526 .guard_size = 2,
527 .cacheline_size = G4X_FIFO_LINE_SIZE,
b445e3b0
ED		 528};
529static const struct intel_watermark_params valleyview_wm_info = {
e0f0273e
VS		 530 .fifo_size = VALLEYVIEW_FIFO_SIZE,
531 .max_wm = VALLEYVIEW_MAX_WM,
532 .default_wm = VALLEYVIEW_MAX_WM,
533 .guard_size = 2,
534 .cacheline_size = G4X_FIFO_LINE_SIZE,
b445e3b0
ED		 535};
536static const struct intel_watermark_params valleyview_cursor_wm_info = {
e0f0273e
VS		 537 .fifo_size = I965_CURSOR_FIFO,
538 .max_wm = VALLEYVIEW_CURSOR_MAX_WM,
539 .default_wm = I965_CURSOR_DFT_WM,
540 .guard_size = 2,
541 .cacheline_size = G4X_FIFO_LINE_SIZE,
b445e3b0
ED		 542};
543static const struct intel_watermark_params i965_cursor_wm_info = {
e0f0273e
VS		 544 .fifo_size = I965_CURSOR_FIFO,
545 .max_wm = I965_CURSOR_MAX_WM,
546 .default_wm = I965_CURSOR_DFT_WM,
547 .guard_size = 2,
548 .cacheline_size = I915_FIFO_LINE_SIZE,
b445e3b0
ED		 549};
550static const struct intel_watermark_params i945_wm_info = {
e0f0273e
VS		 551 .fifo_size = I945_FIFO_SIZE,
552 .max_wm = I915_MAX_WM,
553 .default_wm = 1,
554 .guard_size = 2,
555 .cacheline_size = I915_FIFO_LINE_SIZE,
b445e3b0
ED		 556};
557static const struct intel_watermark_params i915_wm_info = {
e0f0273e
VS		 558 .fifo_size = I915_FIFO_SIZE,
559 .max_wm = I915_MAX_WM,
560 .default_wm = 1,
561 .guard_size = 2,
562 .cacheline_size = I915_FIFO_LINE_SIZE,
b445e3b0 563};
9d539105 564static const struct intel_watermark_params i830_a_wm_info = {
e0f0273e
VS		 565 .fifo_size = I855GM_FIFO_SIZE,
566 .max_wm = I915_MAX_WM,
567 .default_wm = 1,
568 .guard_size = 2,
569 .cacheline_size = I830_FIFO_LINE_SIZE,
b445e3b0 570};
9d539105
VS		 571static const struct intel_watermark_params i830_bc_wm_info = {
572 .fifo_size = I855GM_FIFO_SIZE,
573 .max_wm = I915_MAX_WM/2,
574 .default_wm = 1,
575 .guard_size = 2,
576 .cacheline_size = I830_FIFO_LINE_SIZE,
577};
feb56b93 578static const struct intel_watermark_params i845_wm_info = {
e0f0273e
VS		 579 .fifo_size = I830_FIFO_SIZE,
580 .max_wm = I915_MAX_WM,
581 .default_wm = 1,
582 .guard_size = 2,
583 .cacheline_size = I830_FIFO_LINE_SIZE,
b445e3b0
ED		 584};
585
b445e3b0
ED		 586/**
587 * intel_calculate_wm - calculate watermark level
588 * @clock_in_khz: pixel clock
589 * @wm: chip FIFO params
590 * @pixel_size: display pixel size
591 * @latency_ns: memory latency for the platform
592 *
593 * Calculate the watermark level (the level at which the display plane will
594 * start fetching from memory again). Each chip has a different display
595 * FIFO size and allocation, so the caller needs to figure that out and pass
596 * in the correct intel_watermark_params structure.
597 *
598 * As the pixel clock runs, the FIFO will be drained at a rate that depends
599 * on the pixel size. When it reaches the watermark level, it'll start
600 * fetching FIFO line sized based chunks from memory until the FIFO fills
601 * past the watermark point. If the FIFO drains completely, a FIFO underrun
602 * will occur, and a display engine hang could result.
603 */
604static unsigned long intel_calculate_wm(unsigned long clock_in_khz,
605 const struct intel_watermark_params *wm,
606 int fifo_size,
607 int pixel_size,
608 unsigned long latency_ns)
609{
610 long entries_required, wm_size;
611
612 /*
613 * Note: we need to make sure we don't overflow for various clock &
614 * latency values.
615 * clocks go from a few thousand to several hundred thousand.
616 * latency is usually a few thousand
617 */
618 entries_required = ((clock_in_khz / 1000) * pixel_size * latency_ns) /
619 1000;
620 entries_required = DIV_ROUND_UP(entries_required, wm->cacheline_size);
621
622 DRM_DEBUG_KMS("FIFO entries required for mode: %ld\n", entries_required);
623
624 wm_size = fifo_size - (entries_required + wm->guard_size);
625
626 DRM_DEBUG_KMS("FIFO watermark level: %ld\n", wm_size);
627
628 /* Don't promote wm_size to unsigned... */
629 if (wm_size > (long)wm->max_wm)
630 wm_size = wm->max_wm;
631 if (wm_size <= 0)
632 wm_size = wm->default_wm;
d6feb196
VS		 633
634 /*
635 * Bspec seems to indicate that the value shouldn't be lower than
636 * 'burst size + 1'. Certainly 830 is quite unhappy with low values.
637 * Lets go for 8 which is the burst size since certain platforms
638 * already use a hardcoded 8 (which is what the spec says should be
639 * done).
640 */
641 if (wm_size <= 8)
642 wm_size = 8;
643
b445e3b0
ED		 644 return wm_size;
645}
646
647static struct drm_crtc *single_enabled_crtc(struct drm_device *dev)
648{
649 struct drm_crtc *crtc, *enabled = NULL;
650
70e1e0ec 651 for_each_crtc(dev, crtc) {
3490ea5d 652 if (intel_crtc_active(crtc)) {
b445e3b0
ED		 653 if (enabled)
654 return NULL;
655 enabled = crtc;
656 }
657 }
658
659 return enabled;
660}
661
46ba614c 662static void pineview_update_wm(struct drm_crtc *unused_crtc)
b445e3b0 663{
46ba614c 664 struct drm_device *dev = unused_crtc->dev;
b445e3b0
ED		 665 struct drm_i915_private *dev_priv = dev->dev_private;
666 struct drm_crtc *crtc;
667 const struct cxsr_latency *latency;
668 u32 reg;
669 unsigned long wm;
670
671 latency = intel_get_cxsr_latency(IS_PINEVIEW_G(dev), dev_priv->is_ddr3,
672 dev_priv->fsb_freq, dev_priv->mem_freq);
673 if (!latency) {
674 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
5209b1f4 675 intel_set_memory_cxsr(dev_priv, false);
b445e3b0
ED		 676 return;
677 }
678
679 crtc = single_enabled_crtc(dev);
680 if (crtc) {
241bfc38 681 const struct drm_display_mode *adjusted_mode;
59bea882 682 int pixel_size = crtc->primary->state->fb->bits_per_pixel / 8;
241bfc38
DL		 683 int clock;
684
6e3c9717 685 adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
241bfc38 686 clock = adjusted_mode->crtc_clock;
b445e3b0
ED		 687
688 /* Display SR */
689 wm = intel_calculate_wm(clock, &pineview_display_wm,
690 pineview_display_wm.fifo_size,
691 pixel_size, latency->display_sr);
692 reg = I915_READ(DSPFW1);
693 reg &= ~DSPFW_SR_MASK;
f4998963 694 reg |= FW_WM(wm, SR);
b445e3b0
ED		 695 I915_WRITE(DSPFW1, reg);
696 DRM_DEBUG_KMS("DSPFW1 register is %x\n", reg);
697
698 /* cursor SR */
699 wm = intel_calculate_wm(clock, &pineview_cursor_wm,
700 pineview_display_wm.fifo_size,
701 pixel_size, latency->cursor_sr);
702 reg = I915_READ(DSPFW3);
703 reg &= ~DSPFW_CURSOR_SR_MASK;
f4998963 704 reg |= FW_WM(wm, CURSOR_SR);
b445e3b0
ED		 705 I915_WRITE(DSPFW3, reg);
706
707 /* Display HPLL off SR */
708 wm = intel_calculate_wm(clock, &pineview_display_hplloff_wm,
709 pineview_display_hplloff_wm.fifo_size,
710 pixel_size, latency->display_hpll_disable);
711 reg = I915_READ(DSPFW3);
712 reg &= ~DSPFW_HPLL_SR_MASK;
f4998963 713 reg |= FW_WM(wm, HPLL_SR);
b445e3b0
ED		 714 I915_WRITE(DSPFW3, reg);
715
716 /* cursor HPLL off SR */
717 wm = intel_calculate_wm(clock, &pineview_cursor_hplloff_wm,
718 pineview_display_hplloff_wm.fifo_size,
719 pixel_size, latency->cursor_hpll_disable);
720 reg = I915_READ(DSPFW3);
721 reg &= ~DSPFW_HPLL_CURSOR_MASK;
f4998963 722 reg |= FW_WM(wm, HPLL_CURSOR);
b445e3b0
ED		 723 I915_WRITE(DSPFW3, reg);
724 DRM_DEBUG_KMS("DSPFW3 register is %x\n", reg);
725
5209b1f4 726 intel_set_memory_cxsr(dev_priv, true);
b445e3b0 727 } else {
5209b1f4 728 intel_set_memory_cxsr(dev_priv, false);
b445e3b0
ED		 729 }
730}
731
732static bool g4x_compute_wm0(struct drm_device *dev,
733 int plane,
734 const struct intel_watermark_params *display,
735 int display_latency_ns,
736 const struct intel_watermark_params *cursor,
737 int cursor_latency_ns,
738 int *plane_wm,
739 int *cursor_wm)
740{
741 struct drm_crtc *crtc;
4fe8590a 742 const struct drm_display_mode *adjusted_mode;
b445e3b0
ED		 743 int htotal, hdisplay, clock, pixel_size;
744 int line_time_us, line_count;
745 int entries, tlb_miss;
746
747 crtc = intel_get_crtc_for_plane(dev, plane);
3490ea5d 748 if (!intel_crtc_active(crtc)) {
b445e3b0
ED		 749 *cursor_wm = cursor->guard_size;
750 *plane_wm = display->guard_size;
751 return false;
752 }
753
6e3c9717 754 adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
241bfc38 755 clock = adjusted_mode->crtc_clock;
fec8cba3 756 htotal = adjusted_mode->crtc_htotal;
6e3c9717 757 hdisplay = to_intel_crtc(crtc)->config->pipe_src_w;
59bea882 758 pixel_size = crtc->primary->state->fb->bits_per_pixel / 8;
b445e3b0
ED		 759
760 /* Use the small buffer method to calculate plane watermark */
761 entries = ((clock * pixel_size / 1000) * display_latency_ns) / 1000;
762 tlb_miss = display->fifo_size*display->cacheline_size - hdisplay * 8;
763 if (tlb_miss > 0)
764 entries += tlb_miss;
765 entries = DIV_ROUND_UP(entries, display->cacheline_size);
766 *plane_wm = entries + display->guard_size;
767 if (*plane_wm > (int)display->max_wm)
768 *plane_wm = display->max_wm;
769
770 /* Use the large buffer method to calculate cursor watermark */
922044c9 771 line_time_us = max(htotal * 1000 / clock, 1);
b445e3b0 772 line_count = (cursor_latency_ns / line_time_us + 1000) / 1000;
3dd512fb 773 entries = line_count * crtc->cursor->state->crtc_w * pixel_size;
b445e3b0
ED		 774 tlb_miss = cursor->fifo_size*cursor->cacheline_size - hdisplay * 8;
775 if (tlb_miss > 0)
776 entries += tlb_miss;
777 entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
778 *cursor_wm = entries + cursor->guard_size;
779 if (*cursor_wm > (int)cursor->max_wm)
780 *cursor_wm = (int)cursor->max_wm;
781
782 return true;
783}
784
785/*
786 * Check the wm result.
787 *
788 * If any calculated watermark values is larger than the maximum value that
789 * can be programmed into the associated watermark register, that watermark
790 * must be disabled.
791 */
792static bool g4x_check_srwm(struct drm_device *dev,
793 int display_wm, int cursor_wm,
794 const struct intel_watermark_params *display,
795 const struct intel_watermark_params *cursor)
796{
797 DRM_DEBUG_KMS("SR watermark: display plane %d, cursor %d\n",
798 display_wm, cursor_wm);
799
800 if (display_wm > display->max_wm) {
801 DRM_DEBUG_KMS("display watermark is too large(%d/%ld), disabling\n",
802 display_wm, display->max_wm);
803 return false;
804 }
805
806 if (cursor_wm > cursor->max_wm) {
807 DRM_DEBUG_KMS("cursor watermark is too large(%d/%ld), disabling\n",
808 cursor_wm, cursor->max_wm);
809 return false;
810 }
811
812 if (!(display_wm || cursor_wm)) {
813 DRM_DEBUG_KMS("SR latency is 0, disabling\n");
814 return false;
815 }
816
817 return true;
818}
819
820static bool g4x_compute_srwm(struct drm_device *dev,
821 int plane,
822 int latency_ns,
823 const struct intel_watermark_params *display,
824 const struct intel_watermark_params *cursor,
825 int *display_wm, int *cursor_wm)
826{
827 struct drm_crtc *crtc;
4fe8590a 828 const struct drm_display_mode *adjusted_mode;
b445e3b0
ED		 829 int hdisplay, htotal, pixel_size, clock;
830 unsigned long line_time_us;
831 int line_count, line_size;
832 int small, large;
833 int entries;
834
835 if (!latency_ns) {
836 *display_wm = *cursor_wm = 0;
837 return false;
838 }
839
840 crtc = intel_get_crtc_for_plane(dev, plane);
6e3c9717 841 adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
241bfc38 842 clock = adjusted_mode->crtc_clock;
fec8cba3 843 htotal = adjusted_mode->crtc_htotal;
6e3c9717 844 hdisplay = to_intel_crtc(crtc)->config->pipe_src_w;
59bea882 845 pixel_size = crtc->primary->state->fb->bits_per_pixel / 8;
b445e3b0 846
922044c9 847 line_time_us = max(htotal * 1000 / clock, 1);
b445e3b0
ED		 848 line_count = (latency_ns / line_time_us + 1000) / 1000;
849 line_size = hdisplay * pixel_size;
850
851 /* Use the minimum of the small and large buffer method for primary */
852 small = ((clock * pixel_size / 1000) * latency_ns) / 1000;
853 large = line_count * line_size;
854
855 entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
856 *display_wm = entries + display->guard_size;
857
858 /* calculate the self-refresh watermark for display cursor */
3dd512fb 859 entries = line_count * pixel_size * crtc->cursor->state->crtc_w;
b445e3b0
ED		 860 entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
861 *cursor_wm = entries + cursor->guard_size;
862
863 return g4x_check_srwm(dev,
864 *display_wm, *cursor_wm,
865 display, cursor);
866}
867
15665979
VS		 868#define FW_WM_VLV(value, plane) \
869 (((value) << DSPFW_ ## plane ## _SHIFT) & DSPFW_ ## plane ## _MASK_VLV)
870
0018fda1
VS		 871static void vlv_write_wm_values(struct intel_crtc *crtc,
872 const struct vlv_wm_values *wm)
873{
874 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
875 enum pipe pipe = crtc->pipe;
876
877 I915_WRITE(VLV_DDL(pipe),
878 (wm->ddl[pipe].cursor << DDL_CURSOR_SHIFT) |
879 (wm->ddl[pipe].sprite[1] << DDL_SPRITE_SHIFT(1)) |
880 (wm->ddl[pipe].sprite[0] << DDL_SPRITE_SHIFT(0)) |
881 (wm->ddl[pipe].primary << DDL_PLANE_SHIFT));
882
ae80152d 883 I915_WRITE(DSPFW1,
15665979
VS		 884 FW_WM(wm->sr.plane, SR) |
885 FW_WM(wm->pipe[PIPE_B].cursor, CURSORB) |
886 FW_WM_VLV(wm->pipe[PIPE_B].primary, PLANEB) |
887 FW_WM_VLV(wm->pipe[PIPE_A].primary, PLANEA));
ae80152d 888 I915_WRITE(DSPFW2,
15665979
VS		 889 FW_WM_VLV(wm->pipe[PIPE_A].sprite[1], SPRITEB) |
890 FW_WM(wm->pipe[PIPE_A].cursor, CURSORA) |
891 FW_WM_VLV(wm->pipe[PIPE_A].sprite[0], SPRITEA));
ae80152d 892 I915_WRITE(DSPFW3,
15665979 893 FW_WM(wm->sr.cursor, CURSOR_SR));
ae80152d
VS		 894
895 if (IS_CHERRYVIEW(dev_priv)) {
896 I915_WRITE(DSPFW7_CHV,
15665979
VS		 897 FW_WM_VLV(wm->pipe[PIPE_B].sprite[1], SPRITED) |
898 FW_WM_VLV(wm->pipe[PIPE_B].sprite[0], SPRITEC));
ae80152d 899 I915_WRITE(DSPFW8_CHV,
15665979
VS		 900 FW_WM_VLV(wm->pipe[PIPE_C].sprite[1], SPRITEF) |
901 FW_WM_VLV(wm->pipe[PIPE_C].sprite[0], SPRITEE));
ae80152d 902 I915_WRITE(DSPFW9_CHV,
15665979
VS		 903 FW_WM_VLV(wm->pipe[PIPE_C].primary, PLANEC) |
904 FW_WM(wm->pipe[PIPE_C].cursor, CURSORC));
ae80152d 905 I915_WRITE(DSPHOWM,
15665979
VS		 906 FW_WM(wm->sr.plane >> 9, SR_HI) |
907 FW_WM(wm->pipe[PIPE_C].sprite[1] >> 8, SPRITEF_HI) |
908 FW_WM(wm->pipe[PIPE_C].sprite[0] >> 8, SPRITEE_HI) |
909 FW_WM(wm->pipe[PIPE_C].primary >> 8, PLANEC_HI) |
910 FW_WM(wm->pipe[PIPE_B].sprite[1] >> 8, SPRITED_HI) |
911 FW_WM(wm->pipe[PIPE_B].sprite[0] >> 8, SPRITEC_HI) |
912 FW_WM(wm->pipe[PIPE_B].primary >> 8, PLANEB_HI) |
913 FW_WM(wm->pipe[PIPE_A].sprite[1] >> 8, SPRITEB_HI) |
914 FW_WM(wm->pipe[PIPE_A].sprite[0] >> 8, SPRITEA_HI) |
915 FW_WM(wm->pipe[PIPE_A].primary >> 8, PLANEA_HI));
ae80152d
VS		 916 } else {
917 I915_WRITE(DSPFW7,
15665979
VS		 918 FW_WM_VLV(wm->pipe[PIPE_B].sprite[1], SPRITED) |
919 FW_WM_VLV(wm->pipe[PIPE_B].sprite[0], SPRITEC));
ae80152d 920 I915_WRITE(DSPHOWM,
15665979
VS		 921 FW_WM(wm->sr.plane >> 9, SR_HI) |
922 FW_WM(wm->pipe[PIPE_B].sprite[1] >> 8, SPRITED_HI) |
923 FW_WM(wm->pipe[PIPE_B].sprite[0] >> 8, SPRITEC_HI) |
924 FW_WM(wm->pipe[PIPE_B].primary >> 8, PLANEB_HI) |
925 FW_WM(wm->pipe[PIPE_A].sprite[1] >> 8, SPRITEB_HI) |
926 FW_WM(wm->pipe[PIPE_A].sprite[0] >> 8, SPRITEA_HI) |
927 FW_WM(wm->pipe[PIPE_A].primary >> 8, PLANEA_HI));
ae80152d
VS		 928 }
929
2cb389b7
VS		 930 /* zero (unused) WM1 watermarks */
931 I915_WRITE(DSPFW4, 0);
932 I915_WRITE(DSPFW5, 0);
933 I915_WRITE(DSPFW6, 0);
934 I915_WRITE(DSPHOWM1, 0);
935
ae80152d 936 POSTING_READ(DSPFW1);
0018fda1
VS		 937}
938
15665979
VS		 939#undef FW_WM_VLV
940
6eb1a681
VS		 941enum vlv_wm_level {
942 VLV_WM_LEVEL_PM2,
943 VLV_WM_LEVEL_PM5,
944 VLV_WM_LEVEL_DDR_DVFS,
945 CHV_WM_NUM_LEVELS,
946 VLV_WM_NUM_LEVELS = 1,
947};
948
262cd2e1
VS		 949/* latency must be in 0.1us units. */
950static unsigned int vlv_wm_method2(unsigned int pixel_rate,
951 unsigned int pipe_htotal,
952 unsigned int horiz_pixels,
953 unsigned int bytes_per_pixel,
954 unsigned int latency)
955{
956 unsigned int ret;
957
958 ret = (latency * pixel_rate) / (pipe_htotal * 10000);
959 ret = (ret + 1) * horiz_pixels * bytes_per_pixel;
960 ret = DIV_ROUND_UP(ret, 64);
961
962 return ret;
963}
964
965static void vlv_setup_wm_latency(struct drm_device *dev)
966{
967 struct drm_i915_private *dev_priv = dev->dev_private;
968
969 /* all latencies in usec */
970 dev_priv->wm.pri_latency[VLV_WM_LEVEL_PM2] = 3;
971
972 if (IS_CHERRYVIEW(dev_priv)) {
973 dev_priv->wm.pri_latency[VLV_WM_LEVEL_PM5] = 12;
974 dev_priv->wm.pri_latency[VLV_WM_LEVEL_DDR_DVFS] = 33;
975 }
976}
977
978static uint16_t vlv_compute_wm_level(struct intel_plane *plane,
979 struct intel_crtc *crtc,
980 const struct intel_plane_state *state,
981 int level)
982{
983 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
984 int clock, htotal, pixel_size, width, wm;
985
986 if (dev_priv->wm.pri_latency[level] == 0)
987 return USHRT_MAX;
988
989 if (!state->visible)
990 return 0;
991
992 pixel_size = drm_format_plane_cpp(state->base.fb->pixel_format, 0);
993 clock = crtc->config->base.adjusted_mode.crtc_clock;
994 htotal = crtc->config->base.adjusted_mode.crtc_htotal;
995 width = crtc->config->pipe_src_w;
996 if (WARN_ON(htotal == 0))
997 htotal = 1;
998
999 if (plane->base.type == DRM_PLANE_TYPE_CURSOR) {
1000 /*
1001 * FIXME the formula gives values that are
1002 * too big for the cursor FIFO, and hence we
1003 * would never be able to use cursors. For
1004 * now just hardcode the watermark.
1005 */
1006 wm = 63;
1007 } else {
1008 wm = vlv_wm_method2(clock, htotal, width, pixel_size,
1009 dev_priv->wm.pri_latency[level] * 10);
1010 }
1011
1012 return min_t(int, wm, USHRT_MAX);
1013}
1014
54f1b6e1
VS		 1015static void vlv_compute_fifo(struct intel_crtc *crtc)
1016{
1017 struct drm_device *dev = crtc->base.dev;
1018 struct vlv_wm_state *wm_state = &crtc->wm_state;
1019 struct intel_plane *plane;
1020 unsigned int total_rate = 0;
1021 const int fifo_size = 512 - 1;
1022 int fifo_extra, fifo_left = fifo_size;
1023
1024 for_each_intel_plane_on_crtc(dev, crtc, plane) {
1025 struct intel_plane_state *state =
1026 to_intel_plane_state(plane->base.state);
1027
1028 if (plane->base.type == DRM_PLANE_TYPE_CURSOR)
1029 continue;
1030
1031 if (state->visible) {
1032 wm_state->num_active_planes++;
1033 total_rate += drm_format_plane_cpp(state->base.fb->pixel_format, 0);
1034 }
1035 }
1036
1037 for_each_intel_plane_on_crtc(dev, crtc, plane) {
1038 struct intel_plane_state *state =
1039 to_intel_plane_state(plane->base.state);
1040 unsigned int rate;
1041
1042 if (plane->base.type == DRM_PLANE_TYPE_CURSOR) {
1043 plane->wm.fifo_size = 63;
1044 continue;
1045 }
1046
1047 if (!state->visible) {
1048 plane->wm.fifo_size = 0;
1049 continue;
1050 }
1051
1052 rate = drm_format_plane_cpp(state->base.fb->pixel_format, 0);
1053 plane->wm.fifo_size = fifo_size * rate / total_rate;
1054 fifo_left -= plane->wm.fifo_size;
1055 }
1056
1057 fifo_extra = DIV_ROUND_UP(fifo_left, wm_state->num_active_planes ?: 1);
1058
1059 /* spread the remainder evenly */
1060 for_each_intel_plane_on_crtc(dev, crtc, plane) {
1061 int plane_extra;
1062
1063 if (fifo_left == 0)
1064 break;
1065
1066 if (plane->base.type == DRM_PLANE_TYPE_CURSOR)
1067 continue;
1068
1069 /* give it all to the first plane if none are active */
1070 if (plane->wm.fifo_size == 0 &&
1071 wm_state->num_active_planes)
1072 continue;
1073
1074 plane_extra = min(fifo_extra, fifo_left);
1075 plane->wm.fifo_size += plane_extra;
1076 fifo_left -= plane_extra;
1077 }
1078
1079 WARN_ON(fifo_left != 0);
1080}
1081
262cd2e1
VS		 1082static void vlv_invert_wms(struct intel_crtc *crtc)
1083{
1084 struct vlv_wm_state *wm_state = &crtc->wm_state;
1085 int level;
1086
1087 for (level = 0; level < wm_state->num_levels; level++) {
1088 struct drm_device *dev = crtc->base.dev;
1089 const int sr_fifo_size = INTEL_INFO(dev)->num_pipes * 512 - 1;
1090 struct intel_plane *plane;
1091
1092 wm_state->sr[level].plane = sr_fifo_size - wm_state->sr[level].plane;
1093 wm_state->sr[level].cursor = 63 - wm_state->sr[level].cursor;
1094
1095 for_each_intel_plane_on_crtc(dev, crtc, plane) {
1096 switch (plane->base.type) {
1097 int sprite;
1098 case DRM_PLANE_TYPE_CURSOR:
1099 wm_state->wm[level].cursor = plane->wm.fifo_size -
1100 wm_state->wm[level].cursor;
1101 break;
1102 case DRM_PLANE_TYPE_PRIMARY:
1103 wm_state->wm[level].primary = plane->wm.fifo_size -
1104 wm_state->wm[level].primary;
1105 break;
1106 case DRM_PLANE_TYPE_OVERLAY:
1107 sprite = plane->plane;
1108 wm_state->wm[level].sprite[sprite] = plane->wm.fifo_size -
1109 wm_state->wm[level].sprite[sprite];
1110 break;
1111 }
1112 }
1113 }
1114}
1115
26e1fe4f 1116static void vlv_compute_wm(struct intel_crtc *crtc)
262cd2e1
VS		 1117{
1118 struct drm_device *dev = crtc->base.dev;
1119 struct vlv_wm_state *wm_state = &crtc->wm_state;
1120 struct intel_plane *plane;
1121 int sr_fifo_size = INTEL_INFO(dev)->num_pipes * 512 - 1;
1122 int level;
1123
1124 memset(wm_state, 0, sizeof(*wm_state));
1125
852eb00d 1126 wm_state->cxsr = crtc->pipe != PIPE_C && crtc->wm.cxsr_allowed;
262cd2e1
VS		 1127 if (IS_CHERRYVIEW(dev))
1128 wm_state->num_levels = CHV_WM_NUM_LEVELS;
1129 else
1130 wm_state->num_levels = VLV_WM_NUM_LEVELS;
1131
1132 wm_state->num_active_planes = 0;
262cd2e1 1133
54f1b6e1 1134 vlv_compute_fifo(crtc);
262cd2e1
VS		 1135
1136 if (wm_state->num_active_planes != 1)
1137 wm_state->cxsr = false;
1138
1139 if (wm_state->cxsr) {
1140 for (level = 0; level < wm_state->num_levels; level++) {
1141 wm_state->sr[level].plane = sr_fifo_size;
1142 wm_state->sr[level].cursor = 63;
1143 }
1144 }
1145
1146 for_each_intel_plane_on_crtc(dev, crtc, plane) {
1147 struct intel_plane_state *state =
1148 to_intel_plane_state(plane->base.state);
1149
1150 if (!state->visible)
1151 continue;
1152
1153 /* normal watermarks */
1154 for (level = 0; level < wm_state->num_levels; level++) {
1155 int wm = vlv_compute_wm_level(plane, crtc, state, level);
1156 int max_wm = plane->base.type == DRM_PLANE_TYPE_CURSOR ? 63 : 511;
1157
1158 /* hack */
1159 if (WARN_ON(level == 0 && wm > max_wm))
1160 wm = max_wm;
1161
1162 if (wm > plane->wm.fifo_size)
1163 break;
1164
1165 switch (plane->base.type) {
1166 int sprite;
1167 case DRM_PLANE_TYPE_CURSOR:
1168 wm_state->wm[level].cursor = wm;
1169 break;
1170 case DRM_PLANE_TYPE_PRIMARY:
1171 wm_state->wm[level].primary = wm;
1172 break;
1173 case DRM_PLANE_TYPE_OVERLAY:
1174 sprite = plane->plane;
1175 wm_state->wm[level].sprite[sprite] = wm;
1176 break;
1177 }
1178 }
1179
1180 wm_state->num_levels = level;
1181
1182 if (!wm_state->cxsr)
1183 continue;
1184
1185 /* maxfifo watermarks */
1186 switch (plane->base.type) {
1187 int sprite, level;
1188 case DRM_PLANE_TYPE_CURSOR:
1189 for (level = 0; level < wm_state->num_levels; level++)
1190 wm_state->sr[level].cursor =
1191 wm_state->sr[level].cursor;
1192 break;
1193 case DRM_PLANE_TYPE_PRIMARY:
1194 for (level = 0; level < wm_state->num_levels; level++)
1195 wm_state->sr[level].plane =
1196 min(wm_state->sr[level].plane,
1197 wm_state->wm[level].primary);
1198 break;
1199 case DRM_PLANE_TYPE_OVERLAY:
1200 sprite = plane->plane;
1201 for (level = 0; level < wm_state->num_levels; level++)
1202 wm_state->sr[level].plane =
1203 min(wm_state->sr[level].plane,
1204 wm_state->wm[level].sprite[sprite]);
1205 break;
1206 }
1207 }
1208
1209 /* clear any (partially) filled invalid levels */
1210 for (level = wm_state->num_levels; level < CHV_WM_NUM_LEVELS; level++) {
1211 memset(&wm_state->wm[level], 0, sizeof(wm_state->wm[level]));
1212 memset(&wm_state->sr[level], 0, sizeof(wm_state->sr[level]));
1213 }
1214
1215 vlv_invert_wms(crtc);
1216}
1217
54f1b6e1
VS		 1218#define VLV_FIFO(plane, value) \
1219 (((value) << DSPARB_ ## plane ## _SHIFT_VLV) & DSPARB_ ## plane ## _MASK_VLV)
1220
1221static void vlv_pipe_set_fifo_size(struct intel_crtc *crtc)
1222{
1223 struct drm_device *dev = crtc->base.dev;
1224 struct drm_i915_private *dev_priv = to_i915(dev);
1225 struct intel_plane *plane;
1226 int sprite0_start = 0, sprite1_start = 0, fifo_size = 0;
1227
1228 for_each_intel_plane_on_crtc(dev, crtc, plane) {
1229 if (plane->base.type == DRM_PLANE_TYPE_CURSOR) {
1230 WARN_ON(plane->wm.fifo_size != 63);
1231 continue;
1232 }
1233
1234 if (plane->base.type == DRM_PLANE_TYPE_PRIMARY)
1235 sprite0_start = plane->wm.fifo_size;
1236 else if (plane->plane == 0)
1237 sprite1_start = sprite0_start + plane->wm.fifo_size;
1238 else
1239 fifo_size = sprite1_start + plane->wm.fifo_size;
1240 }
1241
1242 WARN_ON(fifo_size != 512 - 1);
1243
1244 DRM_DEBUG_KMS("Pipe %c FIFO split %d / %d / %d\n",
1245 pipe_name(crtc->pipe), sprite0_start,
1246 sprite1_start, fifo_size);
1247
1248 switch (crtc->pipe) {
1249 uint32_t dsparb, dsparb2, dsparb3;
1250 case PIPE_A:
1251 dsparb = I915_READ(DSPARB);
1252 dsparb2 = I915_READ(DSPARB2);
1253
1254 dsparb &= ~(VLV_FIFO(SPRITEA, 0xff) |
1255 VLV_FIFO(SPRITEB, 0xff));
1256 dsparb |= (VLV_FIFO(SPRITEA, sprite0_start) |
1257 VLV_FIFO(SPRITEB, sprite1_start));
1258
1259 dsparb2 &= ~(VLV_FIFO(SPRITEA_HI, 0x1) |
1260 VLV_FIFO(SPRITEB_HI, 0x1));
1261 dsparb2 |= (VLV_FIFO(SPRITEA_HI, sprite0_start >> 8) |
1262 VLV_FIFO(SPRITEB_HI, sprite1_start >> 8));
1263
1264 I915_WRITE(DSPARB, dsparb);
1265 I915_WRITE(DSPARB2, dsparb2);
1266 break;
1267 case PIPE_B:
1268 dsparb = I915_READ(DSPARB);
1269 dsparb2 = I915_READ(DSPARB2);
1270
1271 dsparb &= ~(VLV_FIFO(SPRITEC, 0xff) |
1272 VLV_FIFO(SPRITED, 0xff));
1273 dsparb |= (VLV_FIFO(SPRITEC, sprite0_start) |
1274 VLV_FIFO(SPRITED, sprite1_start));
1275
1276 dsparb2 &= ~(VLV_FIFO(SPRITEC_HI, 0xff) |
1277 VLV_FIFO(SPRITED_HI, 0xff));
1278 dsparb2 |= (VLV_FIFO(SPRITEC_HI, sprite0_start >> 8) |
1279 VLV_FIFO(SPRITED_HI, sprite1_start >> 8));
1280
1281 I915_WRITE(DSPARB, dsparb);
1282 I915_WRITE(DSPARB2, dsparb2);
1283 break;
1284 case PIPE_C:
1285 dsparb3 = I915_READ(DSPARB3);
1286 dsparb2 = I915_READ(DSPARB2);
1287
1288 dsparb3 &= ~(VLV_FIFO(SPRITEE, 0xff) |
1289 VLV_FIFO(SPRITEF, 0xff));
1290 dsparb3 |= (VLV_FIFO(SPRITEE, sprite0_start) |
1291 VLV_FIFO(SPRITEF, sprite1_start));
1292
1293 dsparb2 &= ~(VLV_FIFO(SPRITEE_HI, 0xff) |
1294 VLV_FIFO(SPRITEF_HI, 0xff));
1295 dsparb2 |= (VLV_FIFO(SPRITEE_HI, sprite0_start >> 8) |
1296 VLV_FIFO(SPRITEF_HI, sprite1_start >> 8));
1297
1298 I915_WRITE(DSPARB3, dsparb3);
1299 I915_WRITE(DSPARB2, dsparb2);
1300 break;
1301 default:
1302 break;
1303 }
1304}
1305
1306#undef VLV_FIFO
1307
262cd2e1
VS		 1308static void vlv_merge_wm(struct drm_device *dev,
1309 struct vlv_wm_values *wm)
1310{
1311 struct intel_crtc *crtc;
1312 int num_active_crtcs = 0;
1313
1314 if (IS_CHERRYVIEW(dev))
1315 wm->level = VLV_WM_LEVEL_DDR_DVFS;
1316 else
1317 wm->level = VLV_WM_LEVEL_PM2;
1318 wm->cxsr = true;
1319
1320 for_each_intel_crtc(dev, crtc) {
1321 const struct vlv_wm_state *wm_state = &crtc->wm_state;
1322
1323 if (!crtc->active)
1324 continue;
1325
1326 if (!wm_state->cxsr)
1327 wm->cxsr = false;
1328
1329 num_active_crtcs++;
1330 wm->level = min_t(int, wm->level, wm_state->num_levels - 1);
1331 }
1332
1333 if (num_active_crtcs != 1)
1334 wm->cxsr = false;
1335
6f9c784b
VS		 1336 if (num_active_crtcs > 1)
1337 wm->level = VLV_WM_LEVEL_PM2;
1338
262cd2e1
VS		 1339 for_each_intel_crtc(dev, crtc) {
1340 struct vlv_wm_state *wm_state = &crtc->wm_state;
1341 enum pipe pipe = crtc->pipe;
1342
1343 if (!crtc->active)
1344 continue;
1345
1346 wm->pipe[pipe] = wm_state->wm[wm->level];
1347 if (wm->cxsr)
1348 wm->sr = wm_state->sr[wm->level];
1349
1350 wm->ddl[pipe].primary = DDL_PRECISION_HIGH | 2;
1351 wm->ddl[pipe].sprite[0] = DDL_PRECISION_HIGH | 2;
1352 wm->ddl[pipe].sprite[1] = DDL_PRECISION_HIGH | 2;
1353 wm->ddl[pipe].cursor = DDL_PRECISION_HIGH | 2;
1354 }
1355}
1356
1357static void vlv_update_wm(struct drm_crtc *crtc)
1358{
1359 struct drm_device *dev = crtc->dev;
1360 struct drm_i915_private *dev_priv = dev->dev_private;
1361 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1362 enum pipe pipe = intel_crtc->pipe;
1363 struct vlv_wm_values wm = {};
1364
26e1fe4f 1365 vlv_compute_wm(intel_crtc);
262cd2e1
VS		 1366 vlv_merge_wm(dev, &wm);
1367
54f1b6e1
VS		 1368 if (memcmp(&dev_priv->wm.vlv, &wm, sizeof(wm)) == 0) {
1369 /* FIXME should be part of crtc atomic commit */
1370 vlv_pipe_set_fifo_size(intel_crtc);
262cd2e1 1371 return;
54f1b6e1 1372 }
262cd2e1
VS		 1373
1374 if (wm.level < VLV_WM_LEVEL_DDR_DVFS &&
1375 dev_priv->wm.vlv.level >= VLV_WM_LEVEL_DDR_DVFS)
1376 chv_set_memory_dvfs(dev_priv, false);
1377
1378 if (wm.level < VLV_WM_LEVEL_PM5 &&
1379 dev_priv->wm.vlv.level >= VLV_WM_LEVEL_PM5)
1380 chv_set_memory_pm5(dev_priv, false);
1381
852eb00d 1382 if (!wm.cxsr && dev_priv->wm.vlv.cxsr)
262cd2e1 1383 intel_set_memory_cxsr(dev_priv, false);
262cd2e1 1384
54f1b6e1
VS		 1385 /* FIXME should be part of crtc atomic commit */
1386 vlv_pipe_set_fifo_size(intel_crtc);
1387
262cd2e1
VS		 1388 vlv_write_wm_values(intel_crtc, &wm);
1389
1390 DRM_DEBUG_KMS("Setting FIFO watermarks - %c: plane=%d, cursor=%d, "
1391 "sprite0=%d, sprite1=%d, SR: plane=%d, cursor=%d level=%d cxsr=%d\n",
1392 pipe_name(pipe), wm.pipe[pipe].primary, wm.pipe[pipe].cursor,
1393 wm.pipe[pipe].sprite[0], wm.pipe[pipe].sprite[1],
1394 wm.sr.plane, wm.sr.cursor, wm.level, wm.cxsr);
1395
852eb00d 1396 if (wm.cxsr && !dev_priv->wm.vlv.cxsr)
262cd2e1 1397 intel_set_memory_cxsr(dev_priv, true);
262cd2e1
VS		 1398
1399 if (wm.level >= VLV_WM_LEVEL_PM5 &&
1400 dev_priv->wm.vlv.level < VLV_WM_LEVEL_PM5)
1401 chv_set_memory_pm5(dev_priv, true);
1402
1403 if (wm.level >= VLV_WM_LEVEL_DDR_DVFS &&
1404 dev_priv->wm.vlv.level < VLV_WM_LEVEL_DDR_DVFS)
1405 chv_set_memory_dvfs(dev_priv, true);
1406
1407 dev_priv->wm.vlv = wm;
3c2777fd
VS		 1408}
1409
ae80152d
VS		 1410#define single_plane_enabled(mask) is_power_of_2(mask)
1411
46ba614c 1412static void g4x_update_wm(struct drm_crtc *crtc)
b445e3b0 1413{
46ba614c 1414 struct drm_device *dev = crtc->dev;
b445e3b0
ED		 1415 static const int sr_latency_ns = 12000;
1416 struct drm_i915_private *dev_priv = dev->dev_private;
1417 int planea_wm, planeb_wm, cursora_wm, cursorb_wm;
1418 int plane_sr, cursor_sr;
1419 unsigned int enabled = 0;
9858425c 1420 bool cxsr_enabled;
b445e3b0 1421
51cea1f4 1422 if (g4x_compute_wm0(dev, PIPE_A,
5aef6003
CW		 1423 &g4x_wm_info, pessimal_latency_ns,
1424 &g4x_cursor_wm_info, pessimal_latency_ns,
b445e3b0 1425 &planea_wm, &cursora_wm))
51cea1f4 1426 enabled |= 1 << PIPE_A;
b445e3b0 1427
51cea1f4 1428 if (g4x_compute_wm0(dev, PIPE_B,
5aef6003
CW		 1429 &g4x_wm_info, pessimal_latency_ns,
1430 &g4x_cursor_wm_info, pessimal_latency_ns,
b445e3b0 1431 &planeb_wm, &cursorb_wm))
51cea1f4 1432 enabled |= 1 << PIPE_B;
b445e3b0 1433
b445e3b0
ED		 1434 if (single_plane_enabled(enabled) &&
1435 g4x_compute_srwm(dev, ffs(enabled) - 1,
1436 sr_latency_ns,
1437 &g4x_wm_info,
1438 &g4x_cursor_wm_info,
52bd02d8 1439 &plane_sr, &cursor_sr)) {
9858425c 1440 cxsr_enabled = true;
52bd02d8 1441 } else {
9858425c 1442 cxsr_enabled = false;
5209b1f4 1443 intel_set_memory_cxsr(dev_priv, false);
52bd02d8
CW		 1444 plane_sr = cursor_sr = 0;
1445 }
b445e3b0 1446
a5043453
VS		 1447 DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, "
1448 "B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n",
b445e3b0
ED		 1449 planea_wm, cursora_wm,
1450 planeb_wm, cursorb_wm,
1451 plane_sr, cursor_sr);
1452
1453 I915_WRITE(DSPFW1,
f4998963
VS		 1454 FW_WM(plane_sr, SR) |
1455 FW_WM(cursorb_wm, CURSORB) |
1456 FW_WM(planeb_wm, PLANEB) |
1457 FW_WM(planea_wm, PLANEA));
b445e3b0 1458 I915_WRITE(DSPFW2,
8c919b28 1459 (I915_READ(DSPFW2) & ~DSPFW_CURSORA_MASK) |
f4998963 1460 FW_WM(cursora_wm, CURSORA));
b445e3b0
ED		 1461 /* HPLL off in SR has some issues on G4x... disable it */
1462 I915_WRITE(DSPFW3,
8c919b28 1463 (I915_READ(DSPFW3) & ~(DSPFW_HPLL_SR_EN | DSPFW_CURSOR_SR_MASK)) |
f4998963 1464 FW_WM(cursor_sr, CURSOR_SR));
9858425c
ID		 1465
1466 if (cxsr_enabled)
1467 intel_set_memory_cxsr(dev_priv, true);
b445e3b0
ED		 1468}
1469
46ba614c 1470static void i965_update_wm(struct drm_crtc *unused_crtc)
b445e3b0 1471{
46ba614c 1472 struct drm_device *dev = unused_crtc->dev;
b445e3b0
ED		 1473 struct drm_i915_private *dev_priv = dev->dev_private;
1474 struct drm_crtc *crtc;
1475 int srwm = 1;
1476 int cursor_sr = 16;
9858425c 1477 bool cxsr_enabled;
b445e3b0
ED		 1478
1479 /* Calc sr entries for one plane configs */
1480 crtc = single_enabled_crtc(dev);
1481 if (crtc) {
1482 /* self-refresh has much higher latency */
1483 static const int sr_latency_ns = 12000;
4fe8590a 1484 const struct drm_display_mode *adjusted_mode =
6e3c9717 1485 &to_intel_crtc(crtc)->config->base.adjusted_mode;
241bfc38 1486 int clock = adjusted_mode->crtc_clock;
fec8cba3 1487 int htotal = adjusted_mode->crtc_htotal;
6e3c9717 1488 int hdisplay = to_intel_crtc(crtc)->config->pipe_src_w;
59bea882 1489 int pixel_size = crtc->primary->state->fb->bits_per_pixel / 8;
b445e3b0
ED		 1490 unsigned long line_time_us;
1491 int entries;
1492
922044c9 1493 line_time_us = max(htotal * 1000 / clock, 1);
b445e3b0
ED		 1494
1495 /* Use ns/us then divide to preserve precision */
1496 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
1497 pixel_size * hdisplay;
1498 entries = DIV_ROUND_UP(entries, I915_FIFO_LINE_SIZE);
1499 srwm = I965_FIFO_SIZE - entries;
1500 if (srwm < 0)
1501 srwm = 1;
1502 srwm &= 0x1ff;
1503 DRM_DEBUG_KMS("self-refresh entries: %d, wm: %d\n",
1504 entries, srwm);
1505
1506 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
3dd512fb 1507 pixel_size * crtc->cursor->state->crtc_w;
b445e3b0
ED		 1508 entries = DIV_ROUND_UP(entries,
1509 i965_cursor_wm_info.cacheline_size);
1510 cursor_sr = i965_cursor_wm_info.fifo_size -
1511 (entries + i965_cursor_wm_info.guard_size);
1512
1513 if (cursor_sr > i965_cursor_wm_info.max_wm)
1514 cursor_sr = i965_cursor_wm_info.max_wm;
1515
1516 DRM_DEBUG_KMS("self-refresh watermark: display plane %d "
1517 "cursor %d\n", srwm, cursor_sr);
1518
9858425c 1519 cxsr_enabled = true;
b445e3b0 1520 } else {
9858425c 1521 cxsr_enabled = false;
b445e3b0 1522 /* Turn off self refresh if both pipes are enabled */
5209b1f4 1523 intel_set_memory_cxsr(dev_priv, false);
b445e3b0
ED		 1524 }
1525
1526 DRM_DEBUG_KMS("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR %d\n",
1527 srwm);
1528
1529 /* 965 has limitations... */
f4998963
VS		 1530 I915_WRITE(DSPFW1, FW_WM(srwm, SR) |
1531 FW_WM(8, CURSORB) |
1532 FW_WM(8, PLANEB) |
1533 FW_WM(8, PLANEA));
1534 I915_WRITE(DSPFW2, FW_WM(8, CURSORA) |
1535 FW_WM(8, PLANEC_OLD));
b445e3b0 1536 /* update cursor SR watermark */
f4998963 1537 I915_WRITE(DSPFW3, FW_WM(cursor_sr, CURSOR_SR));
9858425c
ID		 1538
1539 if (cxsr_enabled)
1540 intel_set_memory_cxsr(dev_priv, true);
b445e3b0
ED		 1541}
1542
f4998963
VS		 1543#undef FW_WM
1544
46ba614c 1545static void i9xx_update_wm(struct drm_crtc *unused_crtc)
b445e3b0 1546{
46ba614c 1547 struct drm_device *dev = unused_crtc->dev;
b445e3b0
ED		 1548 struct drm_i915_private *dev_priv = dev->dev_private;
1549 const struct intel_watermark_params *wm_info;
1550 uint32_t fwater_lo;
1551 uint32_t fwater_hi;
1552 int cwm, srwm = 1;
1553 int fifo_size;
1554 int planea_wm, planeb_wm;
1555 struct drm_crtc *crtc, *enabled = NULL;
1556
1557 if (IS_I945GM(dev))
1558 wm_info = &i945_wm_info;
1559 else if (!IS_GEN2(dev))
1560 wm_info = &i915_wm_info;
1561 else
9d539105 1562 wm_info = &i830_a_wm_info;
b445e3b0
ED		 1563
1564 fifo_size = dev_priv->display.get_fifo_size(dev, 0);
1565 crtc = intel_get_crtc_for_plane(dev, 0);
3490ea5d 1566 if (intel_crtc_active(crtc)) {
241bfc38 1567 const struct drm_display_mode *adjusted_mode;
59bea882 1568 int cpp = crtc->primary->state->fb->bits_per_pixel / 8;
b9e0bda3
CW		 1569 if (IS_GEN2(dev))
1570 cpp = 4;
1571
6e3c9717 1572 adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
241bfc38 1573 planea_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
b9e0bda3 1574 wm_info, fifo_size, cpp,
5aef6003 1575 pessimal_latency_ns);
b445e3b0 1576 enabled = crtc;
9d539105 1577 } else {
b445e3b0 1578 planea_wm = fifo_size - wm_info->guard_size;
9d539105
VS		 1579 if (planea_wm > (long)wm_info->max_wm)
1580 planea_wm = wm_info->max_wm;
1581 }
1582
1583 if (IS_GEN2(dev))
1584 wm_info = &i830_bc_wm_info;
b445e3b0
ED		 1585
1586 fifo_size = dev_priv->display.get_fifo_size(dev, 1);
1587 crtc = intel_get_crtc_for_plane(dev, 1);
3490ea5d 1588 if (intel_crtc_active(crtc)) {
241bfc38 1589 const struct drm_display_mode *adjusted_mode;
59bea882 1590 int cpp = crtc->primary->state->fb->bits_per_pixel / 8;
b9e0bda3
CW		 1591 if (IS_GEN2(dev))
1592 cpp = 4;
1593
6e3c9717 1594 adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
241bfc38 1595 planeb_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
b9e0bda3 1596 wm_info, fifo_size, cpp,
5aef6003 1597 pessimal_latency_ns);
b445e3b0
ED		 1598 if (enabled == NULL)
1599 enabled = crtc;
1600 else
1601 enabled = NULL;
9d539105 1602 } else {
b445e3b0 1603 planeb_wm = fifo_size - wm_info->guard_size;
9d539105
VS		 1604 if (planeb_wm > (long)wm_info->max_wm)
1605 planeb_wm = wm_info->max_wm;
1606 }
b445e3b0
ED		 1607
1608 DRM_DEBUG_KMS("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm);
1609
2ab1bc9d 1610 if (IS_I915GM(dev) && enabled) {
2ff8fde1 1611 struct drm_i915_gem_object *obj;
2ab1bc9d 1612
59bea882 1613 obj = intel_fb_obj(enabled->primary->state->fb);
2ab1bc9d
DV		 1614
1615 /* self-refresh seems busted with untiled */
2ff8fde1 1616 if (obj->tiling_mode == I915_TILING_NONE)
2ab1bc9d
DV		 1617 enabled = NULL;
1618 }
1619
b445e3b0
ED		 1620 /*
1621 * Overlay gets an aggressive default since video jitter is bad.
1622 */
1623 cwm = 2;
1624
1625 /* Play safe and disable self-refresh before adjusting watermarks. */
5209b1f4 1626 intel_set_memory_cxsr(dev_priv, false);
b445e3b0
ED		 1627
1628 /* Calc sr entries for one plane configs */
1629 if (HAS_FW_BLC(dev) && enabled) {
1630 /* self-refresh has much higher latency */
1631 static const int sr_latency_ns = 6000;
4fe8590a 1632 const struct drm_display_mode *adjusted_mode =
6e3c9717 1633 &to_intel_crtc(enabled)->config->base.adjusted_mode;
241bfc38 1634 int clock = adjusted_mode->crtc_clock;
fec8cba3 1635 int htotal = adjusted_mode->crtc_htotal;
6e3c9717 1636 int hdisplay = to_intel_crtc(enabled)->config->pipe_src_w;
59bea882 1637 int pixel_size = enabled->primary->state->fb->bits_per_pixel / 8;
b445e3b0
ED		 1638 unsigned long line_time_us;
1639 int entries;
1640
922044c9 1641 line_time_us = max(htotal * 1000 / clock, 1);
b445e3b0
ED		 1642
1643 /* Use ns/us then divide to preserve precision */
1644 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
1645 pixel_size * hdisplay;
1646 entries = DIV_ROUND_UP(entries, wm_info->cacheline_size);
1647 DRM_DEBUG_KMS("self-refresh entries: %d\n", entries);
1648 srwm = wm_info->fifo_size - entries;
1649 if (srwm < 0)
1650 srwm = 1;
1651
1652 if (IS_I945G(dev) || IS_I945GM(dev))
1653 I915_WRITE(FW_BLC_SELF,
1654 FW_BLC_SELF_FIFO_MASK | (srwm & 0xff));
1655 else if (IS_I915GM(dev))
1656 I915_WRITE(FW_BLC_SELF, srwm & 0x3f);
1657 }
1658
1659 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n",
1660 planea_wm, planeb_wm, cwm, srwm);
1661
1662 fwater_lo = ((planeb_wm & 0x3f) << 16) | (planea_wm & 0x3f);
1663 fwater_hi = (cwm & 0x1f);
1664
1665 /* Set request length to 8 cachelines per fetch */
1666 fwater_lo = fwater_lo | (1 << 24) | (1 << 8);
1667 fwater_hi = fwater_hi | (1 << 8);
1668
1669 I915_WRITE(FW_BLC, fwater_lo);
1670 I915_WRITE(FW_BLC2, fwater_hi);
1671
5209b1f4
ID		 1672 if (enabled)
1673 intel_set_memory_cxsr(dev_priv, true);
b445e3b0
ED		 1674}
1675
feb56b93 1676static void i845_update_wm(struct drm_crtc *unused_crtc)
b445e3b0 1677{
46ba614c 1678 struct drm_device *dev = unused_crtc->dev;
b445e3b0
ED		 1679 struct drm_i915_private *dev_priv = dev->dev_private;
1680 struct drm_crtc *crtc;
241bfc38 1681 const struct drm_display_mode *adjusted_mode;
b445e3b0
ED		 1682 uint32_t fwater_lo;
1683 int planea_wm;
1684
1685 crtc = single_enabled_crtc(dev);
1686 if (crtc == NULL)
1687 return;
1688
6e3c9717 1689 adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
241bfc38 1690 planea_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
feb56b93 1691 &i845_wm_info,
b445e3b0 1692 dev_priv->display.get_fifo_size(dev, 0),
5aef6003 1693 4, pessimal_latency_ns);
b445e3b0
ED		 1694 fwater_lo = I915_READ(FW_BLC) & ~0xfff;
1695 fwater_lo |= (3<<8) | planea_wm;
1696
1697 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d\n", planea_wm);
1698
1699 I915_WRITE(FW_BLC, fwater_lo);
1700}
1701
8cfb3407 1702uint32_t ilk_pipe_pixel_rate(const struct intel_crtc_state *pipe_config)
801bcfff 1703{
fd4daa9c 1704 uint32_t pixel_rate;
801bcfff 1705
8cfb3407 1706 pixel_rate = pipe_config->base.adjusted_mode.crtc_clock;
801bcfff
PZ		 1707
1708 /* We only use IF-ID interlacing. If we ever use PF-ID we'll need to
1709 * adjust the pixel_rate here. */
1710
8cfb3407 1711 if (pipe_config->pch_pfit.enabled) {
801bcfff 1712 uint64_t pipe_w, pipe_h, pfit_w, pfit_h;
8cfb3407
VS		 1713 uint32_t pfit_size = pipe_config->pch_pfit.size;
1714
1715 pipe_w = pipe_config->pipe_src_w;
1716 pipe_h = pipe_config->pipe_src_h;
801bcfff 1717
801bcfff
PZ		 1718 pfit_w = (pfit_size >> 16) & 0xFFFF;
1719 pfit_h = pfit_size & 0xFFFF;
1720 if (pipe_w < pfit_w)
1721 pipe_w = pfit_w;
1722 if (pipe_h < pfit_h)
1723 pipe_h = pfit_h;
1724
1725 pixel_rate = div_u64((uint64_t) pixel_rate * pipe_w * pipe_h,
1726 pfit_w * pfit_h);
1727 }
1728
1729 return pixel_rate;
1730}
1731
37126462 1732/* latency must be in 0.1us units. */
23297044 1733static uint32_t ilk_wm_method1(uint32_t pixel_rate, uint8_t bytes_per_pixel,
801bcfff
PZ		 1734 uint32_t latency)
1735{
1736 uint64_t ret;
1737
3312ba65
VS		 1738 if (WARN(latency == 0, "Latency value missing\n"))
1739 return UINT_MAX;
1740
801bcfff
PZ		 1741 ret = (uint64_t) pixel_rate * bytes_per_pixel * latency;
1742 ret = DIV_ROUND_UP_ULL(ret, 64 * 10000) + 2;
1743
1744 return ret;
1745}
1746
37126462 1747/* latency must be in 0.1us units. */
23297044 1748static uint32_t ilk_wm_method2(uint32_t pixel_rate, uint32_t pipe_htotal,
801bcfff
PZ		 1749 uint32_t horiz_pixels, uint8_t bytes_per_pixel,
1750 uint32_t latency)
1751{
1752 uint32_t ret;
1753
3312ba65
VS		 1754 if (WARN(latency == 0, "Latency value missing\n"))
1755 return UINT_MAX;
1756
801bcfff
PZ		 1757 ret = (latency * pixel_rate) / (pipe_htotal * 10000);
1758 ret = (ret + 1) * horiz_pixels * bytes_per_pixel;
1759 ret = DIV_ROUND_UP(ret, 64) + 2;
1760 return ret;
1761}
1762
23297044 1763static uint32_t ilk_wm_fbc(uint32_t pri_val, uint32_t horiz_pixels,
cca32e9a
PZ		 1764 uint8_t bytes_per_pixel)
1765{
1766 return DIV_ROUND_UP(pri_val * 64, horiz_pixels * bytes_per_pixel) + 2;
1767}
1768
2ac96d2a
PB		 1769struct skl_pipe_wm_parameters {
1770 bool active;
1771 uint32_t pipe_htotal;
1772 uint32_t pixel_rate; /* in KHz */
1773 struct intel_plane_wm_parameters plane[I915_MAX_PLANES];
1774 struct intel_plane_wm_parameters cursor;
1775};
1776
820c1980 1777struct ilk_pipe_wm_parameters {
801bcfff 1778 bool active;
801bcfff
PZ		 1779 uint32_t pipe_htotal;
1780 uint32_t pixel_rate;
c35426d2
VS		 1781 struct intel_plane_wm_parameters pri;
1782 struct intel_plane_wm_parameters spr;
1783 struct intel_plane_wm_parameters cur;
801bcfff
PZ		 1784};
1785
820c1980 1786struct ilk_wm_maximums {
cca32e9a
PZ		 1787 uint16_t pri;
1788 uint16_t spr;
1789 uint16_t cur;
1790 uint16_t fbc;
1791};
1792
240264f4
VS		 1793/* used in computing the new watermarks state */
1794struct intel_wm_config {
1795 unsigned int num_pipes_active;
1796 bool sprites_enabled;
1797 bool sprites_scaled;
240264f4
VS		 1798};
1799
37126462
VS		 1800/*
1801 * For both WM_PIPE and WM_LP.
1802 * mem_value must be in 0.1us units.
1803 */
820c1980 1804static uint32_t ilk_compute_pri_wm(const struct ilk_pipe_wm_parameters *params,
cca32e9a
PZ		 1805 uint32_t mem_value,
1806 bool is_lp)
801bcfff 1807{
cca32e9a
PZ		 1808 uint32_t method1, method2;
1809
c35426d2 1810 if (!params->active || !params->pri.enabled)
801bcfff
PZ		 1811 return 0;
1812
23297044 1813 method1 = ilk_wm_method1(params->pixel_rate,
c35426d2 1814 params->pri.bytes_per_pixel,
cca32e9a
PZ		 1815 mem_value);
1816
1817 if (!is_lp)
1818 return method1;
1819
23297044 1820 method2 = ilk_wm_method2(params->pixel_rate,
cca32e9a 1821 params->pipe_htotal,
c35426d2
VS		 1822 params->pri.horiz_pixels,
1823 params->pri.bytes_per_pixel,
cca32e9a
PZ		 1824 mem_value);
1825
1826 return min(method1, method2);
801bcfff
PZ		 1827}
1828
37126462
VS		 1829/*
1830 * For both WM_PIPE and WM_LP.
1831 * mem_value must be in 0.1us units.
1832 */
820c1980 1833static uint32_t ilk_compute_spr_wm(const struct ilk_pipe_wm_parameters *params,
801bcfff
PZ		 1834 uint32_t mem_value)
1835{
1836 uint32_t method1, method2;
1837
c35426d2 1838 if (!params->active || !params->spr.enabled)
801bcfff
PZ		 1839 return 0;
1840
23297044 1841 method1 = ilk_wm_method1(params->pixel_rate,
c35426d2 1842 params->spr.bytes_per_pixel,
801bcfff 1843 mem_value);
23297044 1844 method2 = ilk_wm_method2(params->pixel_rate,
801bcfff 1845 params->pipe_htotal,
c35426d2
VS		 1846 params->spr.horiz_pixels,
1847 params->spr.bytes_per_pixel,
801bcfff
PZ		 1848 mem_value);
1849 return min(method1, method2);
1850}
1851
37126462
VS		 1852/*
1853 * For both WM_PIPE and WM_LP.
1854 * mem_value must be in 0.1us units.
1855 */
820c1980 1856static uint32_t ilk_compute_cur_wm(const struct ilk_pipe_wm_parameters *params,
801bcfff
PZ		 1857 uint32_t mem_value)
1858{
c35426d2 1859 if (!params->active || !params->cur.enabled)
801bcfff
PZ		 1860 return 0;
1861
23297044 1862 return ilk_wm_method2(params->pixel_rate,
801bcfff 1863 params->pipe_htotal,
c35426d2
VS		 1864 params->cur.horiz_pixels,
1865 params->cur.bytes_per_pixel,
801bcfff
PZ		 1866 mem_value);
1867}
1868
cca32e9a 1869/* Only for WM_LP. */
820c1980 1870static uint32_t ilk_compute_fbc_wm(const struct ilk_pipe_wm_parameters *params,
1fda9882 1871 uint32_t pri_val)
cca32e9a 1872{
c35426d2 1873 if (!params->active || !params->pri.enabled)
cca32e9a
PZ		 1874 return 0;
1875
23297044 1876 return ilk_wm_fbc(pri_val,
c35426d2
VS		 1877 params->pri.horiz_pixels,
1878 params->pri.bytes_per_pixel);
cca32e9a
PZ		 1879}
1880
158ae64f
VS		 1881static unsigned int ilk_display_fifo_size(const struct drm_device *dev)
1882{
416f4727
VS		 1883 if (INTEL_INFO(dev)->gen >= 8)
1884 return 3072;
1885 else if (INTEL_INFO(dev)->gen >= 7)
158ae64f
VS		 1886 return 768;
1887 else
1888 return 512;
1889}
1890
4e975081
VS		 1891static unsigned int ilk_plane_wm_reg_max(const struct drm_device *dev,
1892 int level, bool is_sprite)
1893{
1894 if (INTEL_INFO(dev)->gen >= 8)
1895 /* BDW primary/sprite plane watermarks */
1896 return level == 0 ? 255 : 2047;
1897 else if (INTEL_INFO(dev)->gen >= 7)
1898 /* IVB/HSW primary/sprite plane watermarks */
1899 return level == 0 ? 127 : 1023;
1900 else if (!is_sprite)
1901 /* ILK/SNB primary plane watermarks */
1902 return level == 0 ? 127 : 511;
1903 else
1904 /* ILK/SNB sprite plane watermarks */
1905 return level == 0 ? 63 : 255;
1906}
1907
1908static unsigned int ilk_cursor_wm_reg_max(const struct drm_device *dev,
1909 int level)
1910{
1911 if (INTEL_INFO(dev)->gen >= 7)
1912 return level == 0 ? 63 : 255;
1913 else
1914 return level == 0 ? 31 : 63;
1915}
1916
1917static unsigned int ilk_fbc_wm_reg_max(const struct drm_device *dev)
1918{
1919 if (INTEL_INFO(dev)->gen >= 8)
1920 return 31;
1921 else
1922 return 15;
1923}
1924
158ae64f
VS		 1925/* Calculate the maximum primary/sprite plane watermark */
1926static unsigned int ilk_plane_wm_max(const struct drm_device *dev,
1927 int level,
240264f4 1928 const struct intel_wm_config *config,
158ae64f
VS		 1929 enum intel_ddb_partitioning ddb_partitioning,
1930 bool is_sprite)
1931{
1932 unsigned int fifo_size = ilk_display_fifo_size(dev);
158ae64f
VS		 1933
1934 /* if sprites aren't enabled, sprites get nothing */
240264f4 1935 if (is_sprite && !config->sprites_enabled)
158ae64f
VS		 1936 return 0;
1937
1938 /* HSW allows LP1+ watermarks even with multiple pipes */
240264f4 1939 if (level == 0 || config->num_pipes_active > 1) {
158ae64f
VS		 1940 fifo_size /= INTEL_INFO(dev)->num_pipes;
1941
1942 /*
1943 * For some reason the non self refresh
1944 * FIFO size is only half of the self
1945 * refresh FIFO size on ILK/SNB.
1946 */
1947 if (INTEL_INFO(dev)->gen <= 6)
1948 fifo_size /= 2;
1949 }
1950
240264f4 1951 if (config->sprites_enabled) {
158ae64f
VS		 1952 /* level 0 is always calculated with 1:1 split */
1953 if (level > 0 && ddb_partitioning == INTEL_DDB_PART_5_6) {
1954 if (is_sprite)
1955 fifo_size *= 5;
1956 fifo_size /= 6;
1957 } else {
1958 fifo_size /= 2;
1959 }
1960 }
1961
1962 /* clamp to max that the registers can hold */
4e975081 1963 return min(fifo_size, ilk_plane_wm_reg_max(dev, level, is_sprite));
158ae64f
VS		 1964}
1965
1966/* Calculate the maximum cursor plane watermark */
1967static unsigned int ilk_cursor_wm_max(const struct drm_device *dev,
240264f4
VS		 1968 int level,
1969 const struct intel_wm_config *config)
158ae64f
VS		 1970{
1971 /* HSW LP1+ watermarks w/ multiple pipes */
240264f4 1972 if (level > 0 && config->num_pipes_active > 1)
158ae64f
VS		 1973 return 64;
1974
1975 /* otherwise just report max that registers can hold */
4e975081 1976 return ilk_cursor_wm_reg_max(dev, level);
158ae64f
VS		 1977}
1978
d34ff9c6 1979static void ilk_compute_wm_maximums(const struct drm_device *dev,
34982fe1
VS		 1980 int level,
1981 const struct intel_wm_config *config,
1982 enum intel_ddb_partitioning ddb_partitioning,
820c1980 1983 struct ilk_wm_maximums *max)
158ae64f 1984{
240264f4
VS		 1985 max->pri = ilk_plane_wm_max(dev, level, config, ddb_partitioning, false);
1986 max->spr = ilk_plane_wm_max(dev, level, config, ddb_partitioning, true);
1987 max->cur = ilk_cursor_wm_max(dev, level, config);
4e975081 1988 max->fbc = ilk_fbc_wm_reg_max(dev);
158ae64f
VS		 1989}
1990
a3cb4048
VS		 1991static void ilk_compute_wm_reg_maximums(struct drm_device *dev,
1992 int level,
1993 struct ilk_wm_maximums *max)
1994{
1995 max->pri = ilk_plane_wm_reg_max(dev, level, false);
1996 max->spr = ilk_plane_wm_reg_max(dev, level, true);
1997 max->cur = ilk_cursor_wm_reg_max(dev, level);
1998 max->fbc = ilk_fbc_wm_reg_max(dev);
1999}
2000
d9395655 2001static bool ilk_validate_wm_level(int level,
820c1980 2002 const struct ilk_wm_maximums *max,
d9395655 2003 struct intel_wm_level *result)
a9786a11
VS		 2004{
2005 bool ret;
2006
2007 /* already determined to be invalid? */
2008 if (!result->enable)
2009 return false;
2010
2011 result->enable = result->pri_val <= max->pri &&
2012 result->spr_val <= max->spr &&
2013 result->cur_val <= max->cur;
2014
2015 ret = result->enable;
2016
2017 /*
2018 * HACK until we can pre-compute everything,
2019 * and thus fail gracefully if LP0 watermarks
2020 * are exceeded...
2021 */
2022 if (level == 0 && !result->enable) {
2023 if (result->pri_val > max->pri)
2024 DRM_DEBUG_KMS("Primary WM%d too large %u (max %u)\n",
2025 level, result->pri_val, max->pri);
2026 if (result->spr_val > max->spr)
2027 DRM_DEBUG_KMS("Sprite WM%d too large %u (max %u)\n",
2028 level, result->spr_val, max->spr);
2029 if (result->cur_val > max->cur)
2030 DRM_DEBUG_KMS("Cursor WM%d too large %u (max %u)\n",
2031 level, result->cur_val, max->cur);
2032
2033 result->pri_val = min_t(uint32_t, result->pri_val, max->pri);
2034 result->spr_val = min_t(uint32_t, result->spr_val, max->spr);
2035 result->cur_val = min_t(uint32_t, result->cur_val, max->cur);
2036 result->enable = true;
2037 }
2038
a9786a11
VS		 2039 return ret;
2040}
2041
d34ff9c6 2042static void ilk_compute_wm_level(const struct drm_i915_private *dev_priv,
6f5ddd17 2043 int level,
820c1980 2044 const struct ilk_pipe_wm_parameters *p,
1fd527cc 2045 struct intel_wm_level *result)
6f5ddd17
VS		 2046{
2047 uint16_t pri_latency = dev_priv->wm.pri_latency[level];
2048 uint16_t spr_latency = dev_priv->wm.spr_latency[level];
2049 uint16_t cur_latency = dev_priv->wm.cur_latency[level];
2050
2051 /* WM1+ latency values stored in 0.5us units */
2052 if (level > 0) {
2053 pri_latency *= 5;
2054 spr_latency *= 5;
2055 cur_latency *= 5;
2056 }
2057
2058 result->pri_val = ilk_compute_pri_wm(p, pri_latency, level);
2059 result->spr_val = ilk_compute_spr_wm(p, spr_latency);
2060 result->cur_val = ilk_compute_cur_wm(p, cur_latency);
2061 result->fbc_val = ilk_compute_fbc_wm(p, result->pri_val);
2062 result->enable = true;
2063}
2064
801bcfff
PZ		 2065static uint32_t
2066hsw_compute_linetime_wm(struct drm_device *dev, struct drm_crtc *crtc)
1f8eeabf
ED		 2067{
2068 struct drm_i915_private *dev_priv = dev->dev_private;
1011d8c4 2069 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6e3c9717 2070 struct drm_display_mode *mode = &intel_crtc->config->base.adjusted_mode;
85a02deb 2071 u32 linetime, ips_linetime;
1f8eeabf 2072
3ef00284 2073 if (!intel_crtc->active)
801bcfff 2074 return 0;
1011d8c4 2075
1f8eeabf
ED		 2076 /* The WM are computed with base on how long it takes to fill a single
2077 * row at the given clock rate, multiplied by 8.
2078 * */
fec8cba3
JB		 2079 linetime = DIV_ROUND_CLOSEST(mode->crtc_htotal * 1000 * 8,
2080 mode->crtc_clock);
2081 ips_linetime = DIV_ROUND_CLOSEST(mode->crtc_htotal * 1000 * 8,
05024da3 2082 dev_priv->cdclk_freq);
1f8eeabf 2083
801bcfff
PZ		 2084 return PIPE_WM_LINETIME_IPS_LINETIME(ips_linetime) |
2085 PIPE_WM_LINETIME_TIME(linetime);
1f8eeabf
ED		 2086}
2087
2af30a5c 2088static void intel_read_wm_latency(struct drm_device *dev, uint16_t wm[8])
12b134df
VS		 2089{
2090 struct drm_i915_private *dev_priv = dev->dev_private;
2091
2af30a5c
PB		 2092 if (IS_GEN9(dev)) {
2093 uint32_t val;
4f947386 2094 int ret, i;
367294be 2095 int level, max_level = ilk_wm_max_level(dev);
2af30a5c
PB		 2096
2097 /* read the first set of memory latencies[0:3] */
2098 val = 0; /* data0 to be programmed to 0 for first set */
2099 mutex_lock(&dev_priv->rps.hw_lock);
2100 ret = sandybridge_pcode_read(dev_priv,
2101 GEN9_PCODE_READ_MEM_LATENCY,
2102 &val);
2103 mutex_unlock(&dev_priv->rps.hw_lock);
2104
2105 if (ret) {
2106 DRM_ERROR("SKL Mailbox read error = %d\n", ret);
2107 return;
2108 }
2109
2110 wm[0] = val & GEN9_MEM_LATENCY_LEVEL_MASK;
2111 wm[1] = (val >> GEN9_MEM_LATENCY_LEVEL_1_5_SHIFT) &
2112 GEN9_MEM_LATENCY_LEVEL_MASK;
2113 wm[2] = (val >> GEN9_MEM_LATENCY_LEVEL_2_6_SHIFT) &
2114 GEN9_MEM_LATENCY_LEVEL_MASK;
2115 wm[3] = (val >> GEN9_MEM_LATENCY_LEVEL_3_7_SHIFT) &
2116 GEN9_MEM_LATENCY_LEVEL_MASK;
2117
2118 /* read the second set of memory latencies[4:7] */
2119 val = 1; /* data0 to be programmed to 1 for second set */
2120 mutex_lock(&dev_priv->rps.hw_lock);
2121 ret = sandybridge_pcode_read(dev_priv,
2122 GEN9_PCODE_READ_MEM_LATENCY,
2123 &val);
2124 mutex_unlock(&dev_priv->rps.hw_lock);
2125 if (ret) {
2126 DRM_ERROR("SKL Mailbox read error = %d\n", ret);
2127 return;
2128 }
2129
2130 wm[4] = val & GEN9_MEM_LATENCY_LEVEL_MASK;
2131 wm[5] = (val >> GEN9_MEM_LATENCY_LEVEL_1_5_SHIFT) &
2132 GEN9_MEM_LATENCY_LEVEL_MASK;
2133 wm[6] = (val >> GEN9_MEM_LATENCY_LEVEL_2_6_SHIFT) &
2134 GEN9_MEM_LATENCY_LEVEL_MASK;
2135 wm[7] = (val >> GEN9_MEM_LATENCY_LEVEL_3_7_SHIFT) &
2136 GEN9_MEM_LATENCY_LEVEL_MASK;
2137
367294be 2138 /*
6f97235b
DL		 2139 * WaWmMemoryReadLatency:skl
2140 *
367294be
VK		 2141 * punit doesn't take into account the read latency so we need
2142 * to add 2us to the various latency levels we retrieve from
2143 * the punit.
2144 * - W0 is a bit special in that it's the only level that
2145 * can't be disabled if we want to have display working, so
2146 * we always add 2us there.
2147 * - For levels >=1, punit returns 0us latency when they are
2148 * disabled, so we respect that and don't add 2us then
4f947386
VK		 2149 *
2150 * Additionally, if a level n (n > 1) has a 0us latency, all
2151 * levels m (m >= n) need to be disabled. We make sure to
2152 * sanitize the values out of the punit to satisfy this
2153 * requirement.
367294be
VK		 2154 */
2155 wm[0] += 2;
2156 for (level = 1; level <= max_level; level++)
2157 if (wm[level] != 0)
2158 wm[level] += 2;
4f947386
VK		 2159 else {
2160 for (i = level + 1; i <= max_level; i++)
2161 wm[i] = 0;
367294be 2162
4f947386
VK		 2163 break;
2164 }
2af30a5c 2165 } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
12b134df
VS		 2166 uint64_t sskpd = I915_READ64(MCH_SSKPD);
2167
2168 wm[0] = (sskpd >> 56) & 0xFF;
2169 if (wm[0] == 0)
2170 wm[0] = sskpd & 0xF;
e5d5019e
VS		 2171 wm[1] = (sskpd >> 4) & 0xFF;
2172 wm[2] = (sskpd >> 12) & 0xFF;
2173 wm[3] = (sskpd >> 20) & 0x1FF;
2174 wm[4] = (sskpd >> 32) & 0x1FF;
63cf9a13
VS		 2175 } else if (INTEL_INFO(dev)->gen >= 6) {
2176 uint32_t sskpd = I915_READ(MCH_SSKPD);
2177
2178 wm[0] = (sskpd >> SSKPD_WM0_SHIFT) & SSKPD_WM_MASK;
2179 wm[1] = (sskpd >> SSKPD_WM1_SHIFT) & SSKPD_WM_MASK;
2180 wm[2] = (sskpd >> SSKPD_WM2_SHIFT) & SSKPD_WM_MASK;
2181 wm[3] = (sskpd >> SSKPD_WM3_SHIFT) & SSKPD_WM_MASK;
3a88d0ac
VS		 2182 } else if (INTEL_INFO(dev)->gen >= 5) {
2183 uint32_t mltr = I915_READ(MLTR_ILK);
2184
2185 /* ILK primary LP0 latency is 700 ns */
2186 wm[0] = 7;
2187 wm[1] = (mltr >> MLTR_WM1_SHIFT) & ILK_SRLT_MASK;
2188 wm[2] = (mltr >> MLTR_WM2_SHIFT) & ILK_SRLT_MASK;
12b134df
VS		 2189 }
2190}
2191
53615a5e
VS		 2192static void intel_fixup_spr_wm_latency(struct drm_device *dev, uint16_t wm[5])
2193{
2194 /* ILK sprite LP0 latency is 1300 ns */
2195 if (INTEL_INFO(dev)->gen == 5)
2196 wm[0] = 13;
2197}
2198
2199static void intel_fixup_cur_wm_latency(struct drm_device *dev, uint16_t wm[5])
2200{
2201 /* ILK cursor LP0 latency is 1300 ns */
2202 if (INTEL_INFO(dev)->gen == 5)
2203 wm[0] = 13;
2204
2205 /* WaDoubleCursorLP3Latency:ivb */
2206 if (IS_IVYBRIDGE(dev))
2207 wm[3] *= 2;
2208}
2209
546c81fd 2210int ilk_wm_max_level(const struct drm_device *dev)
26ec971e 2211{
26ec971e 2212 /* how many WM levels are we expecting */
b6e742f6 2213 if (INTEL_INFO(dev)->gen >= 9)
2af30a5c
PB		 2214 return 7;
2215 else if (IS_HASWELL(dev) || IS_BROADWELL(dev))
ad0d6dc4 2216 return 4;
26ec971e 2217 else if (INTEL_INFO(dev)->gen >= 6)
ad0d6dc4 2218 return 3;
26ec971e 2219 else
ad0d6dc4
VS		 2220 return 2;
2221}
7526ed79 2222
ad0d6dc4
VS		 2223static void intel_print_wm_latency(struct drm_device *dev,
2224 const char *name,
2af30a5c 2225 const uint16_t wm[8])
ad0d6dc4
VS		 2226{
2227 int level, max_level = ilk_wm_max_level(dev);
26ec971e
VS		 2228
2229 for (level = 0; level <= max_level; level++) {
2230 unsigned int latency = wm[level];
2231
2232 if (latency == 0) {
2233 DRM_ERROR("%s WM%d latency not provided\n",
2234 name, level);
2235 continue;
2236 }
2237
2af30a5c
PB		 2238 /*
2239 * - latencies are in us on gen9.
2240 * - before then, WM1+ latency values are in 0.5us units
2241 */
2242 if (IS_GEN9(dev))
2243 latency *= 10;
2244 else if (level > 0)
26ec971e
VS		 2245 latency *= 5;
2246
2247 DRM_DEBUG_KMS("%s WM%d latency %u (%u.%u usec)\n",
2248 name, level, wm[level],
2249 latency / 10, latency % 10);
2250 }
2251}
2252
e95a2f75
VS		 2253static bool ilk_increase_wm_latency(struct drm_i915_private *dev_priv,
2254 uint16_t wm[5], uint16_t min)
2255{
2256 int level, max_level = ilk_wm_max_level(dev_priv->dev);
2257
2258 if (wm[0] >= min)
2259 return false;
2260
2261 wm[0] = max(wm[0], min);
2262 for (level = 1; level <= max_level; level++)
2263 wm[level] = max_t(uint16_t, wm[level], DIV_ROUND_UP(min, 5));
2264
2265 return true;
2266}
2267
2268static void snb_wm_latency_quirk(struct drm_device *dev)
2269{
2270 struct drm_i915_private *dev_priv = dev->dev_private;
2271 bool changed;
2272
2273 /*
2274 * The BIOS provided WM memory latency values are often
2275 * inadequate for high resolution displays. Adjust them.
2276 */
2277 changed = ilk_increase_wm_latency(dev_priv, dev_priv->wm.pri_latency, 12) |
2278 ilk_increase_wm_latency(dev_priv, dev_priv->wm.spr_latency, 12) |
2279 ilk_increase_wm_latency(dev_priv, dev_priv->wm.cur_latency, 12);
2280
2281 if (!changed)
2282 return;
2283
2284 DRM_DEBUG_KMS("WM latency values increased to avoid potential underruns\n");
2285 intel_print_wm_latency(dev, "Primary", dev_priv->wm.pri_latency);
2286 intel_print_wm_latency(dev, "Sprite", dev_priv->wm.spr_latency);
2287 intel_print_wm_latency(dev, "Cursor", dev_priv->wm.cur_latency);
2288}
2289
fa50ad61 2290static void ilk_setup_wm_latency(struct drm_device *dev)
53615a5e
VS		 2291{
2292 struct drm_i915_private *dev_priv = dev->dev_private;
2293
2294 intel_read_wm_latency(dev, dev_priv->wm.pri_latency);
2295
2296 memcpy(dev_priv->wm.spr_latency, dev_priv->wm.pri_latency,
2297 sizeof(dev_priv->wm.pri_latency));
2298 memcpy(dev_priv->wm.cur_latency, dev_priv->wm.pri_latency,
2299 sizeof(dev_priv->wm.pri_latency));
2300
2301 intel_fixup_spr_wm_latency(dev, dev_priv->wm.spr_latency);
2302 intel_fixup_cur_wm_latency(dev, dev_priv->wm.cur_latency);
26ec971e
VS		 2303
2304 intel_print_wm_latency(dev, "Primary", dev_priv->wm.pri_latency);
2305 intel_print_wm_latency(dev, "Sprite", dev_priv->wm.spr_latency);
2306 intel_print_wm_latency(dev, "Cursor", dev_priv->wm.cur_latency);
e95a2f75
VS		 2307
2308 if (IS_GEN6(dev))
2309 snb_wm_latency_quirk(dev);
53615a5e
VS		 2310}
2311
2af30a5c
PB		 2312static void skl_setup_wm_latency(struct drm_device *dev)
2313{
2314 struct drm_i915_private *dev_priv = dev->dev_private;
2315
2316 intel_read_wm_latency(dev, dev_priv->wm.skl_latency);
2317 intel_print_wm_latency(dev, "Gen9 Plane", dev_priv->wm.skl_latency);
2318}
2319
820c1980 2320static void ilk_compute_wm_parameters(struct drm_crtc *crtc,
2a44b76b 2321 struct ilk_pipe_wm_parameters *p)
1011d8c4 2322{
7c4a395f
VS		 2323 struct drm_device *dev = crtc->dev;
2324 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2325 enum pipe pipe = intel_crtc->pipe;
7c4a395f 2326 struct drm_plane *plane;
1011d8c4 2327
3ef00284 2328 if (!intel_crtc->active)
2a44b76b 2329 return;
801bcfff 2330
2a44b76b 2331 p->active = true;
6e3c9717 2332 p->pipe_htotal = intel_crtc->config->base.adjusted_mode.crtc_htotal;
8cfb3407 2333 p->pixel_rate = ilk_pipe_pixel_rate(intel_crtc->config);
c9f038a1 2334
54da691d 2335 if (crtc->primary->state->fb)
c9f038a1
MR		 2336 p->pri.bytes_per_pixel =
2337 crtc->primary->state->fb->bits_per_pixel / 8;
54da691d
TG		 2338 else
2339 p->pri.bytes_per_pixel = 4;
2340
2341 p->cur.bytes_per_pixel = 4;
2342 /*
2343 * TODO: for now, assume primary and cursor planes are always enabled.
2344 * Setting them to false makes the screen flicker.
2345 */
2346 p->pri.enabled = true;
2347 p->cur.enabled = true;
c9f038a1 2348
6e3c9717 2349 p->pri.horiz_pixels = intel_crtc->config->pipe_src_w;
3dd512fb 2350 p->cur.horiz_pixels = intel_crtc->base.cursor->state->crtc_w;
7c4a395f 2351
af2b653b 2352 drm_for_each_legacy_plane(plane, &dev->mode_config.plane_list) {
801bcfff 2353 struct intel_plane *intel_plane = to_intel_plane(plane);
801bcfff 2354
2a44b76b 2355 if (intel_plane->pipe == pipe) {
7c4a395f 2356 p->spr = intel_plane->wm;
2a44b76b
VS		 2357 break;
2358 }
2359 }
2360}
2361
2362static void ilk_compute_wm_config(struct drm_device *dev,
2363 struct intel_wm_config *config)
2364{
2365 struct intel_crtc *intel_crtc;
2366
2367 /* Compute the currently _active_ config */
d3fcc808 2368 for_each_intel_crtc(dev, intel_crtc) {
2a44b76b 2369 const struct intel_pipe_wm *wm = &intel_crtc->wm.active;
cca32e9a 2370
2a44b76b
VS		 2371 if (!wm->pipe_enabled)
2372 continue;
cca32e9a 2373
2a44b76b
VS		 2374 config->sprites_enabled |= wm->sprites_enabled;
2375 config->sprites_scaled |= wm->sprites_scaled;
2376 config->num_pipes_active++;
cca32e9a 2377 }
801bcfff
PZ		 2378}
2379
0b2ae6d7
VS		 2380/* Compute new watermarks for the pipe */
2381static bool intel_compute_pipe_wm(struct drm_crtc *crtc,
820c1980 2382 const struct ilk_pipe_wm_parameters *params,
0b2ae6d7
VS		 2383 struct intel_pipe_wm *pipe_wm)
2384{
2385 struct drm_device *dev = crtc->dev;
d34ff9c6 2386 const struct drm_i915_private *dev_priv = dev->dev_private;
0b2ae6d7
VS		 2387 int level, max_level = ilk_wm_max_level(dev);
2388 /* LP0 watermark maximums depend on this pipe alone */
2389 struct intel_wm_config config = {
2390 .num_pipes_active = 1,
2391 .sprites_enabled = params->spr.enabled,
2392 .sprites_scaled = params->spr.scaled,
2393 };
820c1980 2394 struct ilk_wm_maximums max;
0b2ae6d7 2395
2a44b76b
VS		 2396 pipe_wm->pipe_enabled = params->active;
2397 pipe_wm->sprites_enabled = params->spr.enabled;
2398 pipe_wm->sprites_scaled = params->spr.scaled;
2399
7b39a0b7
VS		 2400 /* ILK/SNB: LP2+ watermarks only w/o sprites */
2401 if (INTEL_INFO(dev)->gen <= 6 && params->spr.enabled)
2402 max_level = 1;
2403
2404 /* ILK/SNB/IVB: LP1+ watermarks only w/o scaling */
2405 if (params->spr.scaled)
2406 max_level = 0;
2407
a3cb4048 2408 ilk_compute_wm_level(dev_priv, 0, params, &pipe_wm->wm[0]);
0b2ae6d7 2409
a42a5719 2410 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
ce0e0713 2411 pipe_wm->linetime = hsw_compute_linetime_wm(dev, crtc);
0b2ae6d7 2412
a3cb4048
VS		 2413 /* LP0 watermarks always use 1/2 DDB partitioning */
2414 ilk_compute_wm_maximums(dev, 0, &config, INTEL_DDB_PART_1_2, &max);
2415
0b2ae6d7 2416 /* At least LP0 must be valid */
a3cb4048
VS		 2417 if (!ilk_validate_wm_level(0, &max, &pipe_wm->wm[0]))
2418 return false;
2419
2420 ilk_compute_wm_reg_maximums(dev, 1, &max);
2421
2422 for (level = 1; level <= max_level; level++) {
2423 struct intel_wm_level wm = {};
2424
2425 ilk_compute_wm_level(dev_priv, level, params, &wm);
2426
2427 /*
2428 * Disable any watermark level that exceeds the
2429 * register maximums since such watermarks are
2430 * always invalid.
2431 */
2432 if (!ilk_validate_wm_level(level, &max, &wm))
2433 break;
2434
2435 pipe_wm->wm[level] = wm;
2436 }
2437
2438 return true;
0b2ae6d7
VS		 2439}
2440
2441/*
2442 * Merge the watermarks from all active pipes for a specific level.
2443 */
2444static void ilk_merge_wm_level(struct drm_device *dev,
2445 int level,
2446 struct intel_wm_level *ret_wm)
2447{
2448 const struct intel_crtc *intel_crtc;
2449
d52fea5b
VS		 2450 ret_wm->enable = true;
2451
d3fcc808 2452 for_each_intel_crtc(dev, intel_crtc) {
fe392efd
VS		 2453 const struct intel_pipe_wm *active = &intel_crtc->wm.active;
2454 const struct intel_wm_level *wm = &active->wm[level];
2455
2456 if (!active->pipe_enabled)
2457 continue;
0b2ae6d7 2458
d52fea5b
VS		 2459 /*
2460 * The watermark values may have been used in the past,
2461 * so we must maintain them in the registers for some
2462 * time even if the level is now disabled.
2463 */
0b2ae6d7 2464 if (!wm->enable)
d52fea5b 2465 ret_wm->enable = false;
0b2ae6d7
VS		 2466
2467 ret_wm->pri_val = max(ret_wm->pri_val, wm->pri_val);
2468 ret_wm->spr_val = max(ret_wm->spr_val, wm->spr_val);
2469 ret_wm->cur_val = max(ret_wm->cur_val, wm->cur_val);
2470 ret_wm->fbc_val = max(ret_wm->fbc_val, wm->fbc_val);
2471 }
0b2ae6d7
VS		 2472}
2473
2474/*
2475 * Merge all low power watermarks for all active pipes.
2476 */
2477static void ilk_wm_merge(struct drm_device *dev,
0ba22e26 2478 const struct intel_wm_config *config,
820c1980 2479 const struct ilk_wm_maximums *max,
0b2ae6d7
VS		 2480 struct intel_pipe_wm *merged)
2481{
2482 int level, max_level = ilk_wm_max_level(dev);
d52fea5b 2483 int last_enabled_level = max_level;
0b2ae6d7 2484
0ba22e26
VS		 2485 /* ILK/SNB/IVB: LP1+ watermarks only w/ single pipe */
2486 if ((INTEL_INFO(dev)->gen <= 6 || IS_IVYBRIDGE(dev)) &&
2487 config->num_pipes_active > 1)
2488 return;
2489
6c8b6c28
VS		 2490 /* ILK: FBC WM must be disabled always */
2491 merged->fbc_wm_enabled = INTEL_INFO(dev)->gen >= 6;
0b2ae6d7
VS		 2492
2493 /* merge each WM1+ level */
2494 for (level = 1; level <= max_level; level++) {
2495 struct intel_wm_level *wm = &merged->wm[level];
2496
2497 ilk_merge_wm_level(dev, level, wm);
2498
d52fea5b
VS		 2499 if (level > last_enabled_level)
2500 wm->enable = false;
2501 else if (!ilk_validate_wm_level(level, max, wm))
2502 /* make sure all following levels get disabled */
2503 last_enabled_level = level - 1;
0b2ae6d7
VS		 2504
2505 /*
2506 * The spec says it is preferred to disable
2507 * FBC WMs instead of disabling a WM level.
2508 */
2509 if (wm->fbc_val > max->fbc) {
d52fea5b
VS		 2510 if (wm->enable)
2511 merged->fbc_wm_enabled = false;
0b2ae6d7
VS		 2512 wm->fbc_val = 0;
2513 }
2514 }
6c8b6c28
VS		 2515
2516 /* ILK: LP2+ must be disabled when FBC WM is disabled but FBC enabled */
2517 /*
2518 * FIXME this is racy. FBC might get enabled later.
2519 * What we should check here is whether FBC can be
2520 * enabled sometime later.
2521 */
2522 if (IS_GEN5(dev) && !merged->fbc_wm_enabled && intel_fbc_enabled(dev)) {
2523 for (level = 2; level <= max_level; level++) {
2524 struct intel_wm_level *wm = &merged->wm[level];
2525
2526 wm->enable = false;
2527 }
2528 }
0b2ae6d7
VS		 2529}
2530
b380ca3c
VS		 2531static int ilk_wm_lp_to_level(int wm_lp, const struct intel_pipe_wm *pipe_wm)
2532{
2533 /* LP1,LP2,LP3 levels are either 1,2,3 or 1,3,4 */
2534 return wm_lp + (wm_lp >= 2 && pipe_wm->wm[4].enable);
2535}
2536
a68d68ee
VS		 2537/* The value we need to program into the WM_LPx latency field */
2538static unsigned int ilk_wm_lp_latency(struct drm_device *dev, int level)
2539{
2540 struct drm_i915_private *dev_priv = dev->dev_private;
2541
a42a5719 2542 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
a68d68ee
VS		 2543 return 2 * level;
2544 else
2545 return dev_priv->wm.pri_latency[level];
2546}
2547
820c1980 2548static void ilk_compute_wm_results(struct drm_device *dev,
0362c781 2549 const struct intel_pipe_wm *merged,
609cedef 2550 enum intel_ddb_partitioning partitioning,
820c1980 2551 struct ilk_wm_values *results)
801bcfff 2552{
0b2ae6d7
VS		 2553 struct intel_crtc *intel_crtc;
2554 int level, wm_lp;
cca32e9a 2555
0362c781 2556 results->enable_fbc_wm = merged->fbc_wm_enabled;
609cedef 2557 results->partitioning = partitioning;
cca32e9a 2558
0b2ae6d7 2559 /* LP1+ register values */
cca32e9a 2560 for (wm_lp = 1; wm_lp <= 3; wm_lp++) {
1fd527cc 2561 const struct intel_wm_level *r;
801bcfff 2562
b380ca3c 2563 level = ilk_wm_lp_to_level(wm_lp, merged);
0b2ae6d7 2564
0362c781 2565 r = &merged->wm[level];
cca32e9a 2566
d52fea5b
VS		 2567 /*
2568 * Maintain the watermark values even if the level is
2569 * disabled. Doing otherwise could cause underruns.
2570 */
2571 results->wm_lp[wm_lp - 1] =
a68d68ee 2572 (ilk_wm_lp_latency(dev, level) << WM1_LP_LATENCY_SHIFT) |
416f4727
VS		 2573 (r->pri_val << WM1_LP_SR_SHIFT) |
2574 r->cur_val;
2575
d52fea5b
VS		 2576 if (r->enable)
2577 results->wm_lp[wm_lp - 1] |= WM1_LP_SR_EN;
2578
416f4727
VS		 2579 if (INTEL_INFO(dev)->gen >= 8)
2580 results->wm_lp[wm_lp - 1] |=
2581 r->fbc_val << WM1_LP_FBC_SHIFT_BDW;
2582 else
2583 results->wm_lp[wm_lp - 1] |=
2584 r->fbc_val << WM1_LP_FBC_SHIFT;
2585
d52fea5b
VS		 2586 /*
2587 * Always set WM1S_LP_EN when spr_val != 0, even if the
2588 * level is disabled. Doing otherwise could cause underruns.
2589 */
6cef2b8a
VS		 2590 if (INTEL_INFO(dev)->gen <= 6 && r->spr_val) {
2591 WARN_ON(wm_lp != 1);
2592 results->wm_lp_spr[wm_lp - 1] = WM1S_LP_EN | r->spr_val;
2593 } else
2594 results->wm_lp_spr[wm_lp - 1] = r->spr_val;
cca32e9a 2595 }
801bcfff 2596
0b2ae6d7 2597 /* LP0 register values */
d3fcc808 2598 for_each_intel_crtc(dev, intel_crtc) {
0b2ae6d7
VS		 2599 enum pipe pipe = intel_crtc->pipe;
2600 const struct intel_wm_level *r =
2601 &intel_crtc->wm.active.wm[0];
2602
2603 if (WARN_ON(!r->enable))
2604 continue;
2605
2606 results->wm_linetime[pipe] = intel_crtc->wm.active.linetime;
1011d8c4 2607
0b2ae6d7
VS		 2608 results->wm_pipe[pipe] =
2609 (r->pri_val << WM0_PIPE_PLANE_SHIFT) |
2610 (r->spr_val << WM0_PIPE_SPRITE_SHIFT) |
2611 r->cur_val;
801bcfff
PZ		 2612 }
2613}
2614
861f3389
PZ		 2615/* Find the result with the highest level enabled. Check for enable_fbc_wm in
2616 * case both are at the same level. Prefer r1 in case they're the same. */
820c1980 2617static struct intel_pipe_wm *ilk_find_best_result(struct drm_device *dev,
198a1e9b
VS		 2618 struct intel_pipe_wm *r1,
2619 struct intel_pipe_wm *r2)
861f3389 2620{
198a1e9b
VS		 2621 int level, max_level = ilk_wm_max_level(dev);
2622 int level1 = 0, level2 = 0;
861f3389 2623
198a1e9b
VS		 2624 for (level = 1; level <= max_level; level++) {
2625 if (r1->wm[level].enable)
2626 level1 = level;
2627 if (r2->wm[level].enable)
2628 level2 = level;
861f3389
PZ		 2629 }
2630
198a1e9b
VS		 2631 if (level1 == level2) {
2632 if (r2->fbc_wm_enabled && !r1->fbc_wm_enabled)
861f3389
PZ		 2633 return r2;
2634 else
2635 return r1;
198a1e9b 2636 } else if (level1 > level2) {
861f3389
PZ		 2637 return r1;
2638 } else {
2639 return r2;
2640 }
2641}
2642
49a687c4
VS		 2643/* dirty bits used to track which watermarks need changes */
2644#define WM_DIRTY_PIPE(pipe) (1 << (pipe))
2645#define WM_DIRTY_LINETIME(pipe) (1 << (8 + (pipe)))
2646#define WM_DIRTY_LP(wm_lp) (1 << (15 + (wm_lp)))
2647#define WM_DIRTY_LP_ALL (WM_DIRTY_LP(1) | WM_DIRTY_LP(2) | WM_DIRTY_LP(3))
2648#define WM_DIRTY_FBC (1 << 24)
2649#define WM_DIRTY_DDB (1 << 25)
2650
055e393f 2651static unsigned int ilk_compute_wm_dirty(struct drm_i915_private *dev_priv,
820c1980
ID		 2652 const struct ilk_wm_values *old,
2653 const struct ilk_wm_values *new)
49a687c4
VS		 2654{
2655 unsigned int dirty = 0;
2656 enum pipe pipe;
2657 int wm_lp;
2658
055e393f 2659 for_each_pipe(dev_priv, pipe) {
49a687c4
VS		 2660 if (old->wm_linetime[pipe] != new->wm_linetime[pipe]) {
2661 dirty |= WM_DIRTY_LINETIME(pipe);
2662 /* Must disable LP1+ watermarks too */
2663 dirty |= WM_DIRTY_LP_ALL;
2664 }
2665
2666 if (old->wm_pipe[pipe] != new->wm_pipe[pipe]) {
2667 dirty |= WM_DIRTY_PIPE(pipe);
2668 /* Must disable LP1+ watermarks too */
2669 dirty |= WM_DIRTY_LP_ALL;
2670 }
2671 }
2672
2673 if (old->enable_fbc_wm != new->enable_fbc_wm) {
2674 dirty |= WM_DIRTY_FBC;
2675 /* Must disable LP1+ watermarks too */
2676 dirty |= WM_DIRTY_LP_ALL;
2677 }
2678
2679 if (old->partitioning != new->partitioning) {
2680 dirty |= WM_DIRTY_DDB;
2681 /* Must disable LP1+ watermarks too */
2682 dirty |= WM_DIRTY_LP_ALL;
2683 }
2684
2685 /* LP1+ watermarks already deemed dirty, no need to continue */
2686 if (dirty & WM_DIRTY_LP_ALL)
2687 return dirty;
2688
2689 /* Find the lowest numbered LP1+ watermark in need of an update... */
2690 for (wm_lp = 1; wm_lp <= 3; wm_lp++) {
2691 if (old->wm_lp[wm_lp - 1] != new->wm_lp[wm_lp - 1] ||
2692 old->wm_lp_spr[wm_lp - 1] != new->wm_lp_spr[wm_lp - 1])
2693 break;
2694 }
2695
2696 /* ...and mark it and all higher numbered LP1+ watermarks as dirty */
2697 for (; wm_lp <= 3; wm_lp++)
2698 dirty |= WM_DIRTY_LP(wm_lp);
2699
2700 return dirty;
2701}
2702
8553c18e
VS		 2703static bool _ilk_disable_lp_wm(struct drm_i915_private *dev_priv,
2704 unsigned int dirty)
801bcfff 2705{
820c1980 2706 struct ilk_wm_values *previous = &dev_priv->wm.hw;
8553c18e 2707 bool changed = false;
801bcfff 2708
facd619b
VS		 2709 if (dirty & WM_DIRTY_LP(3) && previous->wm_lp[2] & WM1_LP_SR_EN) {
2710 previous->wm_lp[2] &= ~WM1_LP_SR_EN;
2711 I915_WRITE(WM3_LP_ILK, previous->wm_lp[2]);
8553c18e 2712 changed = true;
facd619b
VS		 2713 }
2714 if (dirty & WM_DIRTY_LP(2) && previous->wm_lp[1] & WM1_LP_SR_EN) {
2715 previous->wm_lp[1] &= ~WM1_LP_SR_EN;
2716 I915_WRITE(WM2_LP_ILK, previous->wm_lp[1]);
8553c18e 2717 changed = true;
facd619b
VS		 2718 }
2719 if (dirty & WM_DIRTY_LP(1) && previous->wm_lp[0] & WM1_LP_SR_EN) {
2720 previous->wm_lp[0] &= ~WM1_LP_SR_EN;
2721 I915_WRITE(WM1_LP_ILK, previous->wm_lp[0]);
8553c18e 2722 changed = true;
facd619b 2723 }
801bcfff 2724
facd619b
VS		 2725 /*
2726 * Don't touch WM1S_LP_EN here.
2727 * Doing so could cause underruns.
2728 */
6cef2b8a 2729
8553c18e
VS		 2730 return changed;
2731}
2732
2733/*
2734 * The spec says we shouldn't write when we don't need, because every write
2735 * causes WMs to be re-evaluated, expending some power.
2736 */
820c1980
ID		 2737static void ilk_write_wm_values(struct drm_i915_private *dev_priv,
2738 struct ilk_wm_values *results)
8553c18e
VS		 2739{
2740 struct drm_device *dev = dev_priv->dev;
820c1980 2741 struct ilk_wm_values *previous = &dev_priv->wm.hw;
8553c18e
VS		 2742 unsigned int dirty;
2743 uint32_t val;
2744
055e393f 2745 dirty = ilk_compute_wm_dirty(dev_priv, previous, results);
8553c18e
VS		 2746 if (!dirty)
2747 return;
2748
2749 _ilk_disable_lp_wm(dev_priv, dirty);
2750
49a687c4 2751 if (dirty & WM_DIRTY_PIPE(PIPE_A))
801bcfff 2752 I915_WRITE(WM0_PIPEA_ILK, results->wm_pipe[0]);
49a687c4 2753 if (dirty & WM_DIRTY_PIPE(PIPE_B))
801bcfff 2754 I915_WRITE(WM0_PIPEB_ILK, results->wm_pipe[1]);
49a687c4 2755 if (dirty & WM_DIRTY_PIPE(PIPE_C))
801bcfff
PZ		 2756 I915_WRITE(WM0_PIPEC_IVB, results->wm_pipe[2]);
2757
49a687c4 2758 if (dirty & WM_DIRTY_LINETIME(PIPE_A))
801bcfff 2759 I915_WRITE(PIPE_WM_LINETIME(PIPE_A), results->wm_linetime[0]);
49a687c4 2760 if (dirty & WM_DIRTY_LINETIME(PIPE_B))
801bcfff 2761 I915_WRITE(PIPE_WM_LINETIME(PIPE_B), results->wm_linetime[1]);
49a687c4 2762 if (dirty & WM_DIRTY_LINETIME(PIPE_C))
801bcfff
PZ		 2763 I915_WRITE(PIPE_WM_LINETIME(PIPE_C), results->wm_linetime[2]);
2764
49a687c4 2765 if (dirty & WM_DIRTY_DDB) {
a42a5719 2766 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
ac9545fd
VS		 2767 val = I915_READ(WM_MISC);
2768 if (results->partitioning == INTEL_DDB_PART_1_2)
2769 val &= ~WM_MISC_DATA_PARTITION_5_6;
2770 else
2771 val |= WM_MISC_DATA_PARTITION_5_6;
2772 I915_WRITE(WM_MISC, val);
2773 } else {
2774 val = I915_READ(DISP_ARB_CTL2);
2775 if (results->partitioning == INTEL_DDB_PART_1_2)
2776 val &= ~DISP_DATA_PARTITION_5_6;
2777 else
2778 val |= DISP_DATA_PARTITION_5_6;
2779 I915_WRITE(DISP_ARB_CTL2, val);
2780 }
1011d8c4
PZ		 2781 }
2782
49a687c4 2783 if (dirty & WM_DIRTY_FBC) {
cca32e9a
PZ		 2784 val = I915_READ(DISP_ARB_CTL);
2785 if (results->enable_fbc_wm)
2786 val &= ~DISP_FBC_WM_DIS;
2787 else
2788 val |= DISP_FBC_WM_DIS;
2789 I915_WRITE(DISP_ARB_CTL, val);
2790 }
2791
954911eb
ID		 2792 if (dirty & WM_DIRTY_LP(1) &&
2793 previous->wm_lp_spr[0] != results->wm_lp_spr[0])
2794 I915_WRITE(WM1S_LP_ILK, results->wm_lp_spr[0]);
2795
2796 if (INTEL_INFO(dev)->gen >= 7) {
6cef2b8a
VS		 2797 if (dirty & WM_DIRTY_LP(2) && previous->wm_lp_spr[1] != results->wm_lp_spr[1])
2798 I915_WRITE(WM2S_LP_IVB, results->wm_lp_spr[1]);
2799 if (dirty & WM_DIRTY_LP(3) && previous->wm_lp_spr[2] != results->wm_lp_spr[2])
2800 I915_WRITE(WM3S_LP_IVB, results->wm_lp_spr[2]);
2801 }
801bcfff 2802
facd619b 2803 if (dirty & WM_DIRTY_LP(1) && previous->wm_lp[0] != results->wm_lp[0])
801bcfff 2804 I915_WRITE(WM1_LP_ILK, results->wm_lp[0]);
facd619b 2805 if (dirty & WM_DIRTY_LP(2) && previous->wm_lp[1] != results->wm_lp[1])
801bcfff 2806 I915_WRITE(WM2_LP_ILK, results->wm_lp[1]);
facd619b 2807 if (dirty & WM_DIRTY_LP(3) && previous->wm_lp[2] != results->wm_lp[2])
801bcfff 2808 I915_WRITE(WM3_LP_ILK, results->wm_lp[2]);
609cedef
VS		 2809
2810 dev_priv->wm.hw = *results;
801bcfff
PZ		 2811}
2812
8553c18e
VS		 2813static bool ilk_disable_lp_wm(struct drm_device *dev)
2814{
2815 struct drm_i915_private *dev_priv = dev->dev_private;
2816
2817 return _ilk_disable_lp_wm(dev_priv, WM_DIRTY_LP_ALL);
2818}
2819
b9cec075
DL		 2820/*
2821 * On gen9, we need to allocate Display Data Buffer (DDB) portions to the
2822 * different active planes.
2823 */
2824
2825#define SKL_DDB_SIZE 896 /* in blocks */
43d735a6 2826#define BXT_DDB_SIZE 512
b9cec075
DL		 2827
2828static void
2829skl_ddb_get_pipe_allocation_limits(struct drm_device *dev,
2830 struct drm_crtc *for_crtc,
2831 const struct intel_wm_config *config,
2832 const struct skl_pipe_wm_parameters *params,
2833 struct skl_ddb_entry *alloc /* out */)
2834{
2835 struct drm_crtc *crtc;
2836 unsigned int pipe_size, ddb_size;
2837 int nth_active_pipe;
2838
2839 if (!params->active) {
2840 alloc->start = 0;
2841 alloc->end = 0;
2842 return;
2843 }
2844
43d735a6
DL		 2845 if (IS_BROXTON(dev))
2846 ddb_size = BXT_DDB_SIZE;
2847 else
2848 ddb_size = SKL_DDB_SIZE;
b9cec075
DL		 2849
2850 ddb_size -= 4; /* 4 blocks for bypass path allocation */
2851
2852 nth_active_pipe = 0;
2853 for_each_crtc(dev, crtc) {
3ef00284 2854 if (!to_intel_crtc(crtc)->active)
b9cec075
DL		 2855 continue;
2856
2857 if (crtc == for_crtc)
2858 break;
2859
2860 nth_active_pipe++;
2861 }
2862
2863 pipe_size = ddb_size / config->num_pipes_active;
2864 alloc->start = nth_active_pipe * ddb_size / config->num_pipes_active;
16160e3d 2865 alloc->end = alloc->start + pipe_size;
b9cec075
DL		 2866}
2867
2868static unsigned int skl_cursor_allocation(const struct intel_wm_config *config)
2869{
2870 if (config->num_pipes_active == 1)
2871 return 32;
2872
2873 return 8;
2874}
2875
a269c583
DL		 2876static void skl_ddb_entry_init_from_hw(struct skl_ddb_entry *entry, u32 reg)
2877{
2878 entry->start = reg & 0x3ff;
2879 entry->end = (reg >> 16) & 0x3ff;
16160e3d
DL		 2880 if (entry->end)
2881 entry->end += 1;
a269c583
DL		 2882}
2883
08db6652
DL		 2884void skl_ddb_get_hw_state(struct drm_i915_private *dev_priv,
2885 struct skl_ddb_allocation *ddb /* out */)
a269c583 2886{
a269c583
DL		 2887 enum pipe pipe;
2888 int plane;
2889 u32 val;
2890
2891 for_each_pipe(dev_priv, pipe) {
dd740780 2892 for_each_plane(dev_priv, pipe, plane) {
a269c583
DL		 2893 val = I915_READ(PLANE_BUF_CFG(pipe, plane));
2894 skl_ddb_entry_init_from_hw(&ddb->plane[pipe][plane],
2895 val);
2896 }
2897
2898 val = I915_READ(CUR_BUF_CFG(pipe));
2899 skl_ddb_entry_init_from_hw(&ddb->cursor[pipe], val);
2900 }
2901}
2902
b9cec075 2903static unsigned int
2cd601c6 2904skl_plane_relative_data_rate(const struct intel_plane_wm_parameters *p, int y)
b9cec075 2905{
2cd601c6
CK		 2906
2907 /* for planar format */
2908 if (p->y_bytes_per_pixel) {
2909 if (y) /* y-plane data rate */
2910 return p->horiz_pixels * p->vert_pixels * p->y_bytes_per_pixel;
2911 else /* uv-plane data rate */
2912 return (p->horiz_pixels/2) * (p->vert_pixels/2) * p->bytes_per_pixel;
2913 }
2914
2915 /* for packed formats */
b9cec075
DL		 2916 return p->horiz_pixels * p->vert_pixels * p->bytes_per_pixel;
2917}
2918
2919/*
2920 * We don't overflow 32 bits. Worst case is 3 planes enabled, each fetching
2921 * a 8192x4096@32bpp framebuffer:
2922 * 3 * 4096 * 8192 * 4 < 2^32
2923 */
2924static unsigned int
2925skl_get_total_relative_data_rate(struct intel_crtc *intel_crtc,
2926 const struct skl_pipe_wm_parameters *params)
2927{
2928 unsigned int total_data_rate = 0;
2929 int plane;
2930
2931 for (plane = 0; plane < intel_num_planes(intel_crtc); plane++) {
2932 const struct intel_plane_wm_parameters *p;
2933
2934 p = &params->plane[plane];
2935 if (!p->enabled)
2936 continue;
2937
2cd601c6
CK		 2938 total_data_rate += skl_plane_relative_data_rate(p, 0); /* packed/uv */
2939 if (p->y_bytes_per_pixel) {
2940 total_data_rate += skl_plane_relative_data_rate(p, 1); /* y-plane */
2941 }
b9cec075
DL		 2942 }
2943
2944 return total_data_rate;
2945}
2946
2947static void
2948skl_allocate_pipe_ddb(struct drm_crtc *crtc,
2949 const struct intel_wm_config *config,
2950 const struct skl_pipe_wm_parameters *params,
2951 struct skl_ddb_allocation *ddb /* out */)
2952{
2953 struct drm_device *dev = crtc->dev;
dd740780 2954 struct drm_i915_private *dev_priv = dev->dev_private;
b9cec075
DL		 2955 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2956 enum pipe pipe = intel_crtc->pipe;
34bb56af 2957 struct skl_ddb_entry *alloc = &ddb->pipe[pipe];
b9cec075 2958 uint16_t alloc_size, start, cursor_blocks;
80958155 2959 uint16_t minimum[I915_MAX_PLANES];
2cd601c6 2960 uint16_t y_minimum[I915_MAX_PLANES];
b9cec075
DL		 2961 unsigned int total_data_rate;
2962 int plane;
2963
34bb56af
DL		 2964 skl_ddb_get_pipe_allocation_limits(dev, crtc, config, params, alloc);
2965 alloc_size = skl_ddb_entry_size(alloc);
b9cec075
DL		 2966 if (alloc_size == 0) {
2967 memset(ddb->plane[pipe], 0, sizeof(ddb->plane[pipe]));
2968 memset(&ddb->cursor[pipe], 0, sizeof(ddb->cursor[pipe]));
2969 return;
2970 }
2971
2972 cursor_blocks = skl_cursor_allocation(config);
34bb56af
DL		 2973 ddb->cursor[pipe].start = alloc->end - cursor_blocks;
2974 ddb->cursor[pipe].end = alloc->end;
b9cec075
DL		 2975
2976 alloc_size -= cursor_blocks;
34bb56af 2977 alloc->end -= cursor_blocks;
b9cec075 2978
80958155 2979 /* 1. Allocate the mininum required blocks for each active plane */
dd740780 2980 for_each_plane(dev_priv, pipe, plane) {
80958155
DL		 2981 const struct intel_plane_wm_parameters *p;
2982
2983 p = &params->plane[plane];
2984 if (!p->enabled)
2985 continue;
2986
2987 minimum[plane] = 8;
2988 alloc_size -= minimum[plane];
2cd601c6
CK		 2989 y_minimum[plane] = p->y_bytes_per_pixel ? 8 : 0;
2990 alloc_size -= y_minimum[plane];
80958155
DL		 2991 }
2992
b9cec075 2993 /*
80958155
DL		 2994 * 2. Distribute the remaining space in proportion to the amount of
2995 * data each plane needs to fetch from memory.
b9cec075
DL		 2996 *
2997 * FIXME: we may not allocate every single block here.
2998 */
2999 total_data_rate = skl_get_total_relative_data_rate(intel_crtc, params);
3000
34bb56af 3001 start = alloc->start;
b9cec075
DL		 3002 for (plane = 0; plane < intel_num_planes(intel_crtc); plane++) {
3003 const struct intel_plane_wm_parameters *p;
2cd601c6
CK		 3004 unsigned int data_rate, y_data_rate;
3005 uint16_t plane_blocks, y_plane_blocks = 0;
b9cec075
DL		 3006
3007 p = &params->plane[plane];
3008 if (!p->enabled)
3009 continue;
3010
2cd601c6 3011 data_rate = skl_plane_relative_data_rate(p, 0);
b9cec075
DL		 3012
3013 /*
2cd601c6 3014 * allocation for (packed formats) or (uv-plane part of planar format):
b9cec075
DL		 3015 * promote the expression to 64 bits to avoid overflowing, the
3016 * result is < available as data_rate / total_data_rate < 1
3017 */
80958155
DL		 3018 plane_blocks = minimum[plane];
3019 plane_blocks += div_u64((uint64_t)alloc_size * data_rate,
3020 total_data_rate);
b9cec075
DL		 3021
3022 ddb->plane[pipe][plane].start = start;
16160e3d 3023 ddb->plane[pipe][plane].end = start + plane_blocks;
b9cec075
DL		 3024
3025 start += plane_blocks;
2cd601c6
CK		 3026
3027 /*
3028 * allocation for y_plane part of planar format:
3029 */
3030 if (p->y_bytes_per_pixel) {
3031 y_data_rate = skl_plane_relative_data_rate(p, 1);
3032 y_plane_blocks = y_minimum[plane];
3033 y_plane_blocks += div_u64((uint64_t)alloc_size * y_data_rate,
3034 total_data_rate);
3035
3036 ddb->y_plane[pipe][plane].start = start;
3037 ddb->y_plane[pipe][plane].end = start + y_plane_blocks;
3038
3039 start += y_plane_blocks;
3040 }
3041
b9cec075
DL		 3042 }
3043
3044}
3045
5cec258b 3046static uint32_t skl_pipe_pixel_rate(const struct intel_crtc_state *config)
2d41c0b5
PB		 3047{
3048 /* TODO: Take into account the scalers once we support them */
2d112de7 3049 return config->base.adjusted_mode.crtc_clock;
2d41c0b5
PB		 3050}
3051
3052/*
3053 * The max latency should be 257 (max the punit can code is 255 and we add 2us
3054 * for the read latency) and bytes_per_pixel should always be <= 8, so that
3055 * should allow pixel_rate up to ~2 GHz which seems sufficient since max
3056 * 2xcdclk is 1350 MHz and the pixel rate should never exceed that.
3057*/
3058static uint32_t skl_wm_method1(uint32_t pixel_rate, uint8_t bytes_per_pixel,
3059 uint32_t latency)
3060{
3061 uint32_t wm_intermediate_val, ret;
3062
3063 if (latency == 0)
3064 return UINT_MAX;
3065
d4c2aa60 3066 wm_intermediate_val = latency * pixel_rate * bytes_per_pixel / 512;
2d41c0b5
PB		 3067 ret = DIV_ROUND_UP(wm_intermediate_val, 1000);
3068
3069 return ret;
3070}
3071
3072static uint32_t skl_wm_method2(uint32_t pixel_rate, uint32_t pipe_htotal,
3073 uint32_t horiz_pixels, uint8_t bytes_per_pixel,
0fda6568 3074 uint64_t tiling, uint32_t latency)
2d41c0b5 3075{
d4c2aa60
TU		 3076 uint32_t ret;
3077 uint32_t plane_bytes_per_line, plane_blocks_per_line;
3078 uint32_t wm_intermediate_val;
2d41c0b5
PB		 3079
3080 if (latency == 0)
3081 return UINT_MAX;
3082
3083 plane_bytes_per_line = horiz_pixels * bytes_per_pixel;
0fda6568
TU		 3084
3085 if (tiling == I915_FORMAT_MOD_Y_TILED ||
3086 tiling == I915_FORMAT_MOD_Yf_TILED) {
3087 plane_bytes_per_line *= 4;
3088 plane_blocks_per_line = DIV_ROUND_UP(plane_bytes_per_line, 512);
3089 plane_blocks_per_line /= 4;
3090 } else {
3091 plane_blocks_per_line = DIV_ROUND_UP(plane_bytes_per_line, 512);
3092 }
3093
2d41c0b5
PB		 3094 wm_intermediate_val = latency * pixel_rate;
3095 ret = DIV_ROUND_UP(wm_intermediate_val, pipe_htotal * 1000) *
d4c2aa60 3096 plane_blocks_per_line;
2d41c0b5
PB		 3097
3098 return ret;
3099}
3100
2d41c0b5
PB		 3101static bool skl_ddb_allocation_changed(const struct skl_ddb_allocation *new_ddb,
3102 const struct intel_crtc *intel_crtc)
3103{
3104 struct drm_device *dev = intel_crtc->base.dev;
3105 struct drm_i915_private *dev_priv = dev->dev_private;
3106 const struct skl_ddb_allocation *cur_ddb = &dev_priv->wm.skl_hw.ddb;
3107 enum pipe pipe = intel_crtc->pipe;
3108
3109 if (memcmp(new_ddb->plane[pipe], cur_ddb->plane[pipe],
3110 sizeof(new_ddb->plane[pipe])))
3111 return true;
3112
3113 if (memcmp(&new_ddb->cursor[pipe], &cur_ddb->cursor[pipe],
3114 sizeof(new_ddb->cursor[pipe])))
3115 return true;
3116
3117 return false;
3118}
3119
3120static void skl_compute_wm_global_parameters(struct drm_device *dev,
3121 struct intel_wm_config *config)
3122{
3123 struct drm_crtc *crtc;
3124 struct drm_plane *plane;
3125
3126 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head)
3ef00284 3127 config->num_pipes_active += to_intel_crtc(crtc)->active;
2d41c0b5
PB		 3128
3129 /* FIXME: I don't think we need those two global parameters on SKL */
3130 list_for_each_entry(plane, &dev->mode_config.plane_list, head) {
3131 struct intel_plane *intel_plane = to_intel_plane(plane);
3132
3133 config->sprites_enabled |= intel_plane->wm.enabled;
3134 config->sprites_scaled |= intel_plane->wm.scaled;
3135 }
3136}
3137
3138static void skl_compute_wm_pipe_parameters(struct drm_crtc *crtc,
3139 struct skl_pipe_wm_parameters *p)
3140{
3141 struct drm_device *dev = crtc->dev;
3142 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3143 enum pipe pipe = intel_crtc->pipe;
3144 struct drm_plane *plane;
0fda6568 3145 struct drm_framebuffer *fb;
2d41c0b5
PB		 3146 int i = 1; /* Index for sprite planes start */
3147
3ef00284 3148 p->active = intel_crtc->active;
2d41c0b5 3149 if (p->active) {
6e3c9717
ACO		 3150 p->pipe_htotal = intel_crtc->config->base.adjusted_mode.crtc_htotal;
3151 p->pixel_rate = skl_pipe_pixel_rate(intel_crtc->config);
2d41c0b5 3152
0fda6568 3153 fb = crtc->primary->state->fb;
2cd601c6 3154 /* For planar: Bpp is for uv plane, y_Bpp is for y plane */
c9f038a1
MR		 3155 if (fb) {
3156 p->plane[0].enabled = true;
2cd601c6
CK		 3157 p->plane[0].bytes_per_pixel = fb->pixel_format == DRM_FORMAT_NV12 ?
3158 drm_format_plane_cpp(fb->pixel_format, 1) : fb->bits_per_pixel / 8;
3159 p->plane[0].y_bytes_per_pixel = fb->pixel_format == DRM_FORMAT_NV12 ?
3160 drm_format_plane_cpp(fb->pixel_format, 0) : 0;
0fda6568 3161 p->plane[0].tiling = fb->modifier[0];
c9f038a1
MR		 3162 } else {
3163 p->plane[0].enabled = false;
3164 p->plane[0].bytes_per_pixel = 0;
2cd601c6 3165 p->plane[0].y_bytes_per_pixel = 0;
c9f038a1
MR		 3166 p->plane[0].tiling = DRM_FORMAT_MOD_NONE;
3167 }
3168 p->plane[0].horiz_pixels = intel_crtc->config->pipe_src_w;
3169 p->plane[0].vert_pixels = intel_crtc->config->pipe_src_h;
1fc0a8f7 3170 p->plane[0].rotation = crtc->primary->state->rotation;
2d41c0b5 3171
c9f038a1 3172 fb = crtc->cursor->state->fb;
2cd601c6 3173 p->cursor.y_bytes_per_pixel = 0;
c9f038a1
MR		 3174 if (fb) {
3175 p->cursor.enabled = true;
3176 p->cursor.bytes_per_pixel = fb->bits_per_pixel / 8;
3177 p->cursor.horiz_pixels = crtc->cursor->state->crtc_w;
3178 p->cursor.vert_pixels = crtc->cursor->state->crtc_h;
3179 } else {
3180 p->cursor.enabled = false;
3181 p->cursor.bytes_per_pixel = 0;
3182 p->cursor.horiz_pixels = 64;
3183 p->cursor.vert_pixels = 64;
3184 }
2d41c0b5
PB		 3185 }
3186
3187 list_for_each_entry(plane, &dev->mode_config.plane_list, head) {
3188 struct intel_plane *intel_plane = to_intel_plane(plane);
3189
a712f8eb
SJ		 3190 if (intel_plane->pipe == pipe &&
3191 plane->type == DRM_PLANE_TYPE_OVERLAY)
2d41c0b5
PB		 3192 p->plane[i++] = intel_plane->wm;
3193 }
3194}
3195
d4c2aa60
TU		 3196static bool skl_compute_plane_wm(const struct drm_i915_private *dev_priv,
3197 struct skl_pipe_wm_parameters *p,
afb024aa
DL		 3198 struct intel_plane_wm_parameters *p_params,
3199 uint16_t ddb_allocation,
d4c2aa60 3200 int level,
afb024aa
DL		 3201 uint16_t *out_blocks, /* out */
3202 uint8_t *out_lines /* out */)
2d41c0b5 3203{
d4c2aa60
TU		 3204 uint32_t latency = dev_priv->wm.skl_latency[level];
3205 uint32_t method1, method2;
3206 uint32_t plane_bytes_per_line, plane_blocks_per_line;
3207 uint32_t res_blocks, res_lines;
3208 uint32_t selected_result;
2cd601c6 3209 uint8_t bytes_per_pixel;
2d41c0b5 3210
d4c2aa60 3211 if (latency == 0 || !p->active || !p_params->enabled)
2d41c0b5
PB		 3212 return false;
3213
2cd601c6
CK		 3214 bytes_per_pixel = p_params->y_bytes_per_pixel ?
3215 p_params->y_bytes_per_pixel :
3216 p_params->bytes_per_pixel;
2d41c0b5 3217 method1 = skl_wm_method1(p->pixel_rate,
2cd601c6 3218 bytes_per_pixel,
d4c2aa60 3219 latency);
2d41c0b5
PB		 3220 method2 = skl_wm_method2(p->pixel_rate,
3221 p->pipe_htotal,
3222 p_params->horiz_pixels,
2cd601c6 3223 bytes_per_pixel,
0fda6568 3224 p_params->tiling,
d4c2aa60 3225 latency);
2d41c0b5 3226
2cd601c6 3227 plane_bytes_per_line = p_params->horiz_pixels * bytes_per_pixel;
d4c2aa60 3228 plane_blocks_per_line = DIV_ROUND_UP(plane_bytes_per_line, 512);
2d41c0b5 3229
0fda6568
TU		 3230 if (p_params->tiling == I915_FORMAT_MOD_Y_TILED ||
3231 p_params->tiling == I915_FORMAT_MOD_Yf_TILED) {
1fc0a8f7
TU		 3232 uint32_t min_scanlines = 4;
3233 uint32_t y_tile_minimum;
3234 if (intel_rotation_90_or_270(p_params->rotation)) {
3235 switch (p_params->bytes_per_pixel) {
3236 case 1:
3237 min_scanlines = 16;
3238 break;
3239 case 2:
3240 min_scanlines = 8;
3241 break;
3242 case 8:
3243 WARN(1, "Unsupported pixel depth for rotation");
2f0b5790 3244 }
1fc0a8f7
TU		 3245 }
3246 y_tile_minimum = plane_blocks_per_line * min_scanlines;
0fda6568
TU		 3247 selected_result = max(method2, y_tile_minimum);
3248 } else {
3249 if ((ddb_allocation / plane_blocks_per_line) >= 1)
3250 selected_result = min(method1, method2);
3251 else
3252 selected_result = method1;
3253 }
2d41c0b5 3254
d4c2aa60
TU		 3255 res_blocks = selected_result + 1;
3256 res_lines = DIV_ROUND_UP(selected_result, plane_blocks_per_line);
e6d66171 3257
0fda6568
TU		 3258 if (level >= 1 && level <= 7) {
3259 if (p_params->tiling == I915_FORMAT_MOD_Y_TILED ||
3260 p_params->tiling == I915_FORMAT_MOD_Yf_TILED)
3261 res_lines += 4;
3262 else
3263 res_blocks++;
3264 }
e6d66171 3265
d4c2aa60 3266 if (res_blocks >= ddb_allocation || res_lines > 31)
e6d66171
DL		 3267 return false;
3268
3269 *out_blocks = res_blocks;
3270 *out_lines = res_lines;
2d41c0b5
PB		 3271
3272 return true;
3273}
3274
3275static void skl_compute_wm_level(const struct drm_i915_private *dev_priv,
3276 struct skl_ddb_allocation *ddb,
3277 struct skl_pipe_wm_parameters *p,
3278 enum pipe pipe,
3279 int level,
3280 int num_planes,
3281 struct skl_wm_level *result)
3282{
2d41c0b5
PB		 3283 uint16_t ddb_blocks;
3284 int i;
3285
3286 for (i = 0; i < num_planes; i++) {
3287 ddb_blocks = skl_ddb_entry_size(&ddb->plane[pipe][i]);
3288
d4c2aa60
TU		 3289 result->plane_en[i] = skl_compute_plane_wm(dev_priv,
3290 p, &p->plane[i],
2d41c0b5 3291 ddb_blocks,
d4c2aa60 3292 level,
2d41c0b5
PB		 3293 &result->plane_res_b[i],
3294 &result->plane_res_l[i]);
3295 }
3296
3297 ddb_blocks = skl_ddb_entry_size(&ddb->cursor[pipe]);
d4c2aa60
TU		 3298 result->cursor_en = skl_compute_plane_wm(dev_priv, p, &p->cursor,
3299 ddb_blocks, level,
3300 &result->cursor_res_b,
2d41c0b5
PB		 3301 &result->cursor_res_l);
3302}
3303
407b50f3
DL		 3304static uint32_t
3305skl_compute_linetime_wm(struct drm_crtc *crtc, struct skl_pipe_wm_parameters *p)
3306{
3ef00284 3307 if (!to_intel_crtc(crtc)->active)
407b50f3
DL		 3308 return 0;
3309
3310 return DIV_ROUND_UP(8 * p->pipe_htotal * 1000, p->pixel_rate);
3311
3312}
3313
3314static void skl_compute_transition_wm(struct drm_crtc *crtc,
3315 struct skl_pipe_wm_parameters *params,
9414f563 3316 struct skl_wm_level *trans_wm /* out */)
407b50f3 3317{
9414f563
DL		 3318 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3319 int i;
3320
407b50f3
DL		 3321 if (!params->active)
3322 return;
9414f563
DL		 3323
3324 /* Until we know more, just disable transition WMs */
3325 for (i = 0; i < intel_num_planes(intel_crtc); i++)
3326 trans_wm->plane_en[i] = false;
3327 trans_wm->cursor_en = false;
407b50f3
DL		 3328}
3329
2d41c0b5
PB		 3330static void skl_compute_pipe_wm(struct drm_crtc *crtc,
3331 struct skl_ddb_allocation *ddb,
3332 struct skl_pipe_wm_parameters *params,
3333 struct skl_pipe_wm *pipe_wm)
3334{
3335 struct drm_device *dev = crtc->dev;
3336 const struct drm_i915_private *dev_priv = dev->dev_private;
3337 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3338 int level, max_level = ilk_wm_max_level(dev);
3339
3340 for (level = 0; level <= max_level; level++) {
3341 skl_compute_wm_level(dev_priv, ddb, params, intel_crtc->pipe,
3342 level, intel_num_planes(intel_crtc),
3343 &pipe_wm->wm[level]);
3344 }
3345 pipe_wm->linetime = skl_compute_linetime_wm(crtc, params);
3346
9414f563 3347 skl_compute_transition_wm(crtc, params, &pipe_wm->trans_wm);
2d41c0b5
PB		 3348}
3349
3350static void skl_compute_wm_results(struct drm_device *dev,
3351 struct skl_pipe_wm_parameters *p,
3352 struct skl_pipe_wm *p_wm,
3353 struct skl_wm_values *r,
3354 struct intel_crtc *intel_crtc)
3355{
3356 int level, max_level = ilk_wm_max_level(dev);
3357 enum pipe pipe = intel_crtc->pipe;
9414f563
DL		 3358 uint32_t temp;
3359 int i;
2d41c0b5
PB		 3360
3361 for (level = 0; level <= max_level; level++) {
2d41c0b5
PB		 3362 for (i = 0; i < intel_num_planes(intel_crtc); i++) {
3363 temp = 0;
2d41c0b5
PB		 3364
3365 temp |= p_wm->wm[level].plane_res_l[i] <<
3366 PLANE_WM_LINES_SHIFT;
3367 temp |= p_wm->wm[level].plane_res_b[i];
3368 if (p_wm->wm[level].plane_en[i])
3369 temp |= PLANE_WM_EN;
3370
3371 r->plane[pipe][i][level] = temp;
2d41c0b5
PB		 3372 }
3373
3374 temp = 0;
2d41c0b5
PB		 3375
3376 temp |= p_wm->wm[level].cursor_res_l << PLANE_WM_LINES_SHIFT;
3377 temp |= p_wm->wm[level].cursor_res_b;
3378
3379 if (p_wm->wm[level].cursor_en)
3380 temp |= PLANE_WM_EN;
3381
3382 r->cursor[pipe][level] = temp;
2d41c0b5
PB		 3383
3384 }
3385
9414f563
DL		 3386 /* transition WMs */
3387 for (i = 0; i < intel_num_planes(intel_crtc); i++) {
3388 temp = 0;
3389 temp |= p_wm->trans_wm.plane_res_l[i] << PLANE_WM_LINES_SHIFT;
3390 temp |= p_wm->trans_wm.plane_res_b[i];
3391 if (p_wm->trans_wm.plane_en[i])
3392 temp |= PLANE_WM_EN;
3393
3394 r->plane_trans[pipe][i] = temp;
3395 }
3396
3397 temp = 0;
3398 temp |= p_wm->trans_wm.cursor_res_l << PLANE_WM_LINES_SHIFT;
3399 temp |= p_wm->trans_wm.cursor_res_b;
3400 if (p_wm->trans_wm.cursor_en)
3401 temp |= PLANE_WM_EN;
3402
3403 r->cursor_trans[pipe] = temp;
3404
2d41c0b5
PB		 3405 r->wm_linetime[pipe] = p_wm->linetime;
3406}
3407
16160e3d
DL		 3408static void skl_ddb_entry_write(struct drm_i915_private *dev_priv, uint32_t reg,
3409 const struct skl_ddb_entry *entry)
3410{
3411 if (entry->end)
3412 I915_WRITE(reg, (entry->end - 1) << 16 | entry->start);
3413 else
3414 I915_WRITE(reg, 0);
3415}
3416
2d41c0b5
PB		 3417static void skl_write_wm_values(struct drm_i915_private *dev_priv,
3418 const struct skl_wm_values *new)
3419{
3420 struct drm_device *dev = dev_priv->dev;
3421 struct intel_crtc *crtc;
3422
3423 list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) {
3424 int i, level, max_level = ilk_wm_max_level(dev);
3425 enum pipe pipe = crtc->pipe;
3426
5d374d96
DL		 3427 if (!new->dirty[pipe])
3428 continue;
8211bd5b 3429
5d374d96 3430 I915_WRITE(PIPE_WM_LINETIME(pipe), new->wm_linetime[pipe]);
8211bd5b 3431
5d374d96
DL		 3432 for (level = 0; level <= max_level; level++) {
3433 for (i = 0; i < intel_num_planes(crtc); i++)
3434 I915_WRITE(PLANE_WM(pipe, i, level),
3435 new->plane[pipe][i][level]);
3436 I915_WRITE(CUR_WM(pipe, level),
3437 new->cursor[pipe][level]);
2d41c0b5 3438 }
5d374d96
DL		 3439 for (i = 0; i < intel_num_planes(crtc); i++)
3440 I915_WRITE(PLANE_WM_TRANS(pipe, i),
3441 new->plane_trans[pipe][i]);
3442 I915_WRITE(CUR_WM_TRANS(pipe), new->cursor_trans[pipe]);
3443
2cd601c6 3444 for (i = 0; i < intel_num_planes(crtc); i++) {
5d374d96
DL		 3445 skl_ddb_entry_write(dev_priv,
3446 PLANE_BUF_CFG(pipe, i),
3447 &new->ddb.plane[pipe][i]);
2cd601c6
CK		 3448 skl_ddb_entry_write(dev_priv,
3449 PLANE_NV12_BUF_CFG(pipe, i),
3450 &new->ddb.y_plane[pipe][i]);
3451 }
5d374d96
DL		 3452
3453 skl_ddb_entry_write(dev_priv, CUR_BUF_CFG(pipe),
3454 &new->ddb.cursor[pipe]);
2d41c0b5 3455 }
2d41c0b5
PB		 3456}
3457
0e8fb7ba
DL		 3458/*
3459 * When setting up a new DDB allocation arrangement, we need to correctly
3460 * sequence the times at which the new allocations for the pipes are taken into
3461 * account or we'll have pipes fetching from space previously allocated to
3462 * another pipe.
3463 *
3464 * Roughly the sequence looks like:
3465 * 1. re-allocate the pipe(s) with the allocation being reduced and not
3466 * overlapping with a previous light-up pipe (another way to put it is:
3467 * pipes with their new allocation strickly included into their old ones).
3468 * 2. re-allocate the other pipes that get their allocation reduced
3469 * 3. allocate the pipes having their allocation increased
3470 *
3471 * Steps 1. and 2. are here to take care of the following case:
3472 * - Initially DDB looks like this:
3473 * | B | C |
3474 * - enable pipe A.
3475 * - pipe B has a reduced DDB allocation that overlaps with the old pipe C
3476 * allocation
3477 * | A | B | C |
3478 *
3479 * We need to sequence the re-allocation: C, B, A (and not B, C, A).
3480 */
3481
d21b795c
DL		 3482static void
3483skl_wm_flush_pipe(struct drm_i915_private *dev_priv, enum pipe pipe, int pass)
0e8fb7ba 3484{
0e8fb7ba
DL		 3485 int plane;
3486
d21b795c
DL		 3487 DRM_DEBUG_KMS("flush pipe %c (pass %d)\n", pipe_name(pipe), pass);
3488
dd740780 3489 for_each_plane(dev_priv, pipe, plane) {
0e8fb7ba
DL		 3490 I915_WRITE(PLANE_SURF(pipe, plane),
3491 I915_READ(PLANE_SURF(pipe, plane)));
3492 }
3493 I915_WRITE(CURBASE(pipe), I915_READ(CURBASE(pipe)));
3494}
3495
3496static bool
3497skl_ddb_allocation_included(const struct skl_ddb_allocation *old,
3498 const struct skl_ddb_allocation *new,
3499 enum pipe pipe)
3500{
3501 uint16_t old_size, new_size;
3502
3503 old_size = skl_ddb_entry_size(&old->pipe[pipe]);
3504 new_size = skl_ddb_entry_size(&new->pipe[pipe]);
3505
3506 return old_size != new_size &&
3507 new->pipe[pipe].start >= old->pipe[pipe].start &&
3508 new->pipe[pipe].end <= old->pipe[pipe].end;
3509}
3510
3511static void skl_flush_wm_values(struct drm_i915_private *dev_priv,
3512 struct skl_wm_values *new_values)
3513{
3514 struct drm_device *dev = dev_priv->dev;
3515 struct skl_ddb_allocation *cur_ddb, *new_ddb;
c929cb45 3516 bool reallocated[I915_MAX_PIPES] = {};
0e8fb7ba
DL		 3517 struct intel_crtc *crtc;
3518 enum pipe pipe;
3519
3520 new_ddb = &new_values->ddb;
3521 cur_ddb = &dev_priv->wm.skl_hw.ddb;
3522
3523 /*
3524 * First pass: flush the pipes with the new allocation contained into
3525 * the old space.
3526 *
3527 * We'll wait for the vblank on those pipes to ensure we can safely
3528 * re-allocate the freed space without this pipe fetching from it.
3529 */
3530 for_each_intel_crtc(dev, crtc) {
3531 if (!crtc->active)
3532 continue;
3533
3534 pipe = crtc->pipe;
3535
3536 if (!skl_ddb_allocation_included(cur_ddb, new_ddb, pipe))
3537 continue;
3538
d21b795c 3539 skl_wm_flush_pipe(dev_priv, pipe, 1);
0e8fb7ba
DL		 3540 intel_wait_for_vblank(dev, pipe);
3541
3542 reallocated[pipe] = true;
3543 }
3544
3545
3546 /*
3547 * Second pass: flush the pipes that are having their allocation
3548 * reduced, but overlapping with a previous allocation.
3549 *
3550 * Here as well we need to wait for the vblank to make sure the freed
3551 * space is not used anymore.
3552 */
3553 for_each_intel_crtc(dev, crtc) {
3554 if (!crtc->active)
3555 continue;
3556
3557 pipe = crtc->pipe;
3558
3559 if (reallocated[pipe])
3560 continue;
3561
3562 if (skl_ddb_entry_size(&new_ddb->pipe[pipe]) <
3563 skl_ddb_entry_size(&cur_ddb->pipe[pipe])) {
d21b795c 3564 skl_wm_flush_pipe(dev_priv, pipe, 2);
0e8fb7ba 3565 intel_wait_for_vblank(dev, pipe);
d9d8e6b3 3566 reallocated[pipe] = true;
0e8fb7ba 3567 }
0e8fb7ba
DL		 3568 }
3569
3570 /*
3571 * Third pass: flush the pipes that got more space allocated.
3572 *
3573 * We don't need to actively wait for the update here, next vblank
3574 * will just get more DDB space with the correct WM values.
3575 */
3576 for_each_intel_crtc(dev, crtc) {
3577 if (!crtc->active)
3578 continue;
3579
3580 pipe = crtc->pipe;
3581
3582 /*
3583 * At this point, only the pipes more space than before are
3584 * left to re-allocate.
3585 */
3586 if (reallocated[pipe])
3587 continue;
3588
d21b795c 3589 skl_wm_flush_pipe(dev_priv, pipe, 3);
0e8fb7ba
DL		 3590 }
3591}
3592
2d41c0b5
PB		 3593static bool skl_update_pipe_wm(struct drm_crtc *crtc,
3594 struct skl_pipe_wm_parameters *params,
3595 struct intel_wm_config *config,
3596 struct skl_ddb_allocation *ddb, /* out */
3597 struct skl_pipe_wm *pipe_wm /* out */)
3598{
3599 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3600
3601 skl_compute_wm_pipe_parameters(crtc, params);
b9cec075 3602 skl_allocate_pipe_ddb(crtc, config, params, ddb);
2d41c0b5
PB		 3603 skl_compute_pipe_wm(crtc, ddb, params, pipe_wm);
3604
3605 if (!memcmp(&intel_crtc->wm.skl_active, pipe_wm, sizeof(*pipe_wm)))
3606 return false;
3607
3608 intel_crtc->wm.skl_active = *pipe_wm;
2cd601c6 3609
2d41c0b5
PB		 3610 return true;
3611}
3612
3613static void skl_update_other_pipe_wm(struct drm_device *dev,
3614 struct drm_crtc *crtc,
3615 struct intel_wm_config *config,
3616 struct skl_wm_values *r)
3617{
3618 struct intel_crtc *intel_crtc;
3619 struct intel_crtc *this_crtc = to_intel_crtc(crtc);
3620
3621 /*
3622 * If the WM update hasn't changed the allocation for this_crtc (the
3623 * crtc we are currently computing the new WM values for), other
3624 * enabled crtcs will keep the same allocation and we don't need to
3625 * recompute anything for them.
3626 */
3627 if (!skl_ddb_allocation_changed(&r->ddb, this_crtc))
3628 return;
3629
3630 /*
3631 * Otherwise, because of this_crtc being freshly enabled/disabled, the
3632 * other active pipes need new DDB allocation and WM values.
3633 */
3634 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
3635 base.head) {
3636 struct skl_pipe_wm_parameters params = {};
3637 struct skl_pipe_wm pipe_wm = {};
3638 bool wm_changed;
3639
3640 if (this_crtc->pipe == intel_crtc->pipe)
3641 continue;
3642
3643 if (!intel_crtc->active)
3644 continue;
3645
3646 wm_changed = skl_update_pipe_wm(&intel_crtc->base,
3647 &params, config,
3648 &r->ddb, &pipe_wm);
3649
3650 /*
3651 * If we end up re-computing the other pipe WM values, it's
3652 * because it was really needed, so we expect the WM values to
3653 * be different.
3654 */
3655 WARN_ON(!wm_changed);
3656
3657 skl_compute_wm_results(dev, &params, &pipe_wm, r, intel_crtc);
3658 r->dirty[intel_crtc->pipe] = true;
3659 }
3660}
3661
3662static void skl_update_wm(struct drm_crtc *crtc)
3663{
3664 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3665 struct drm_device *dev = crtc->dev;
3666 struct drm_i915_private *dev_priv = dev->dev_private;
3667 struct skl_pipe_wm_parameters params = {};
3668 struct skl_wm_values *results = &dev_priv->wm.skl_results;
3669 struct skl_pipe_wm pipe_wm = {};
3670 struct intel_wm_config config = {};
3671
3672 memset(results, 0, sizeof(*results));
3673
3674 skl_compute_wm_global_parameters(dev, &config);
3675
3676 if (!skl_update_pipe_wm(crtc, &params, &config,
3677 &results->ddb, &pipe_wm))
3678 return;
3679
3680 skl_compute_wm_results(dev, &params, &pipe_wm, results, intel_crtc);
3681 results->dirty[intel_crtc->pipe] = true;
3682
3683 skl_update_other_pipe_wm(dev, crtc, &config, results);
3684 skl_write_wm_values(dev_priv, results);
0e8fb7ba 3685 skl_flush_wm_values(dev_priv, results);
53b0deb4
DL		 3686
3687 /* store the new configuration */
3688 dev_priv->wm.skl_hw = *results;
2d41c0b5
PB		 3689}
3690
3691static void
3692skl_update_sprite_wm(struct drm_plane *plane, struct drm_crtc *crtc,
3693 uint32_t sprite_width, uint32_t sprite_height,
3694 int pixel_size, bool enabled, bool scaled)
3695{
3696 struct intel_plane *intel_plane = to_intel_plane(plane);
0fda6568 3697 struct drm_framebuffer *fb = plane->state->fb;
2d41c0b5
PB		 3698
3699 intel_plane->wm.enabled = enabled;
3700 intel_plane->wm.scaled = scaled;
3701 intel_plane->wm.horiz_pixels = sprite_width;
3702 intel_plane->wm.vert_pixels = sprite_height;
0fda6568 3703 intel_plane->wm.tiling = DRM_FORMAT_MOD_NONE;
2cd601c6
CK		 3704
3705 /* For planar: Bpp is for UV plane, y_Bpp is for Y plane */
3706 intel_plane->wm.bytes_per_pixel =
3707 (fb && fb->pixel_format == DRM_FORMAT_NV12) ?
3708 drm_format_plane_cpp(plane->state->fb->pixel_format, 1) : pixel_size;
3709 intel_plane->wm.y_bytes_per_pixel =
3710 (fb && fb->pixel_format == DRM_FORMAT_NV12) ?
3711 drm_format_plane_cpp(plane->state->fb->pixel_format, 0) : 0;
3712
0fda6568
TU		 3713 /*
3714 * Framebuffer can be NULL on plane disable, but it does not
3715 * matter for watermarks if we assume no tiling in that case.
3716 */
3717 if (fb)
3718 intel_plane->wm.tiling = fb->modifier[0];
1fc0a8f7 3719 intel_plane->wm.rotation = plane->state->rotation;
2d41c0b5
PB		 3720
3721 skl_update_wm(crtc);
3722}
3723
820c1980 3724static void ilk_update_wm(struct drm_crtc *crtc)
801bcfff 3725{
7c4a395f 3726 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
46ba614c 3727 struct drm_device *dev = crtc->dev;
801bcfff 3728 struct drm_i915_private *dev_priv = dev->dev_private;
820c1980
ID		 3729 struct ilk_wm_maximums max;
3730 struct ilk_pipe_wm_parameters params = {};
3731 struct ilk_wm_values results = {};
77c122bc 3732 enum intel_ddb_partitioning partitioning;
7c4a395f 3733 struct intel_pipe_wm pipe_wm = {};
198a1e9b 3734 struct intel_pipe_wm lp_wm_1_2 = {}, lp_wm_5_6 = {}, *best_lp_wm;
a485bfb8 3735 struct intel_wm_config config = {};
7c4a395f 3736
2a44b76b 3737 ilk_compute_wm_parameters(crtc, &params);
7c4a395f
VS		 3738
3739 intel_compute_pipe_wm(crtc, &params, &pipe_wm);
3740
3741 if (!memcmp(&intel_crtc->wm.active, &pipe_wm, sizeof(pipe_wm)))
3742 return;
861f3389 3743
7c4a395f 3744 intel_crtc->wm.active = pipe_wm;
861f3389 3745
2a44b76b
VS		 3746 ilk_compute_wm_config(dev, &config);
3747
34982fe1 3748 ilk_compute_wm_maximums(dev, 1, &config, INTEL_DDB_PART_1_2, &max);
0ba22e26 3749 ilk_wm_merge(dev, &config, &max, &lp_wm_1_2);
a485bfb8
VS		 3750
3751 /* 5/6 split only in single pipe config on IVB+ */
ec98c8d1
VS		 3752 if (INTEL_INFO(dev)->gen >= 7 &&
3753 config.num_pipes_active == 1 && config.sprites_enabled) {
34982fe1 3754 ilk_compute_wm_maximums(dev, 1, &config, INTEL_DDB_PART_5_6, &max);
0ba22e26 3755 ilk_wm_merge(dev, &config, &max, &lp_wm_5_6);
0362c781 3756
820c1980 3757 best_lp_wm = ilk_find_best_result(dev, &lp_wm_1_2, &lp_wm_5_6);
861f3389 3758 } else {
198a1e9b 3759 best_lp_wm = &lp_wm_1_2;
861f3389
PZ		 3760 }
3761
198a1e9b 3762 partitioning = (best_lp_wm == &lp_wm_1_2) ?
77c122bc 3763 INTEL_DDB_PART_1_2 : INTEL_DDB_PART_5_6;
801bcfff 3764
820c1980 3765 ilk_compute_wm_results(dev, best_lp_wm, partitioning, &results);
609cedef 3766
820c1980 3767 ilk_write_wm_values(dev_priv, &results);
1011d8c4
PZ		 3768}
3769
ed57cb8a
DL		 3770static void
3771ilk_update_sprite_wm(struct drm_plane *plane,
3772 struct drm_crtc *crtc,
3773 uint32_t sprite_width, uint32_t sprite_height,
3774 int pixel_size, bool enabled, bool scaled)
526682e9 3775{
8553c18e 3776 struct drm_device *dev = plane->dev;
adf3d35e 3777 struct intel_plane *intel_plane = to_intel_plane(plane);
526682e9 3778
adf3d35e
VS		 3779 intel_plane->wm.enabled = enabled;
3780 intel_plane->wm.scaled = scaled;
3781 intel_plane->wm.horiz_pixels = sprite_width;
ed57cb8a 3782 intel_plane->wm.vert_pixels = sprite_width;
adf3d35e 3783 intel_plane->wm.bytes_per_pixel = pixel_size;
526682e9 3784
8553c18e
VS		 3785 /*
3786 * IVB workaround: must disable low power watermarks for at least
3787 * one frame before enabling scaling. LP watermarks can be re-enabled
3788 * when scaling is disabled.
3789 *
3790 * WaCxSRDisabledForSpriteScaling:ivb
3791 */
3792 if (IS_IVYBRIDGE(dev) && scaled && ilk_disable_lp_wm(dev))
3793 intel_wait_for_vblank(dev, intel_plane->pipe);
3794
820c1980 3795 ilk_update_wm(crtc);
526682e9
PZ		 3796}
3797
3078999f
PB		 3798static void skl_pipe_wm_active_state(uint32_t val,
3799 struct skl_pipe_wm *active,
3800 bool is_transwm,
3801 bool is_cursor,
3802 int i,
3803 int level)
3804{
3805 bool is_enabled = (val & PLANE_WM_EN) != 0;
3806
3807 if (!is_transwm) {
3808 if (!is_cursor) {
3809 active->wm[level].plane_en[i] = is_enabled;
3810 active->wm[level].plane_res_b[i] =
3811 val & PLANE_WM_BLOCKS_MASK;
3812 active->wm[level].plane_res_l[i] =
3813 (val >> PLANE_WM_LINES_SHIFT) &
3814 PLANE_WM_LINES_MASK;
3815 } else {
3816 active->wm[level].cursor_en = is_enabled;
3817 active->wm[level].cursor_res_b =
3818 val & PLANE_WM_BLOCKS_MASK;
3819 active->wm[level].cursor_res_l =
3820 (val >> PLANE_WM_LINES_SHIFT) &
3821 PLANE_WM_LINES_MASK;
3822 }
3823 } else {
3824 if (!is_cursor) {
3825 active->trans_wm.plane_en[i] = is_enabled;
3826 active->trans_wm.plane_res_b[i] =
3827 val & PLANE_WM_BLOCKS_MASK;
3828 active->trans_wm.plane_res_l[i] =
3829 (val >> PLANE_WM_LINES_SHIFT) &
3830 PLANE_WM_LINES_MASK;
3831 } else {
3832 active->trans_wm.cursor_en = is_enabled;
3833 active->trans_wm.cursor_res_b =
3834 val & PLANE_WM_BLOCKS_MASK;
3835 active->trans_wm.cursor_res_l =
3836 (val >> PLANE_WM_LINES_SHIFT) &
3837 PLANE_WM_LINES_MASK;
3838 }
3839 }
3840}
3841
3842static void skl_pipe_wm_get_hw_state(struct drm_crtc *crtc)
3843{
3844 struct drm_device *dev = crtc->dev;
3845 struct drm_i915_private *dev_priv = dev->dev_private;
3846 struct skl_wm_values *hw = &dev_priv->wm.skl_hw;
3847 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3848 struct skl_pipe_wm *active = &intel_crtc->wm.skl_active;
3849 enum pipe pipe = intel_crtc->pipe;
3850 int level, i, max_level;
3851 uint32_t temp;
3852
3853 max_level = ilk_wm_max_level(dev);
3854
3855 hw->wm_linetime[pipe] = I915_READ(PIPE_WM_LINETIME(pipe));
3856
3857 for (level = 0; level <= max_level; level++) {
3858 for (i = 0; i < intel_num_planes(intel_crtc); i++)
3859 hw->plane[pipe][i][level] =
3860 I915_READ(PLANE_WM(pipe, i, level));
3861 hw->cursor[pipe][level] = I915_READ(CUR_WM(pipe, level));
3862 }
3863
3864 for (i = 0; i < intel_num_planes(intel_crtc); i++)
3865 hw->plane_trans[pipe][i] = I915_READ(PLANE_WM_TRANS(pipe, i));
3866 hw->cursor_trans[pipe] = I915_READ(CUR_WM_TRANS(pipe));
3867
3ef00284 3868 if (!intel_crtc->active)
3078999f
PB		 3869 return;
3870
3871 hw->dirty[pipe] = true;
3872
3873 active->linetime = hw->wm_linetime[pipe];
3874
3875 for (level = 0; level <= max_level; level++) {
3876 for (i = 0; i < intel_num_planes(intel_crtc); i++) {
3877 temp = hw->plane[pipe][i][level];
3878 skl_pipe_wm_active_state(temp, active, false,
3879 false, i, level);
3880 }
3881 temp = hw->cursor[pipe][level];
3882 skl_pipe_wm_active_state(temp, active, false, true, i, level);
3883 }
3884
3885 for (i = 0; i < intel_num_planes(intel_crtc); i++) {
3886 temp = hw->plane_trans[pipe][i];
3887 skl_pipe_wm_active_state(temp, active, true, false, i, 0);
3888 }
3889
3890 temp = hw->cursor_trans[pipe];
3891 skl_pipe_wm_active_state(temp, active, true, true, i, 0);
3892}
3893
3894void skl_wm_get_hw_state(struct drm_device *dev)
3895{
a269c583
DL		 3896 struct drm_i915_private *dev_priv = dev->dev_private;
3897 struct skl_ddb_allocation *ddb = &dev_priv->wm.skl_hw.ddb;
3078999f
PB		 3898 struct drm_crtc *crtc;
3899
a269c583 3900 skl_ddb_get_hw_state(dev_priv, ddb);
3078999f
PB		 3901 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head)
3902 skl_pipe_wm_get_hw_state(crtc);
3903}
3904
243e6a44
VS		 3905static void ilk_pipe_wm_get_hw_state(struct drm_crtc *crtc)
3906{
3907 struct drm_device *dev = crtc->dev;
3908 struct drm_i915_private *dev_priv = dev->dev_private;
820c1980 3909 struct ilk_wm_values *hw = &dev_priv->wm.hw;
243e6a44
VS		 3910 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3911 struct intel_pipe_wm *active = &intel_crtc->wm.active;
3912 enum pipe pipe = intel_crtc->pipe;
3913 static const unsigned int wm0_pipe_reg[] = {
3914 [PIPE_A] = WM0_PIPEA_ILK,
3915 [PIPE_B] = WM0_PIPEB_ILK,
3916 [PIPE_C] = WM0_PIPEC_IVB,
3917 };
3918
3919 hw->wm_pipe[pipe] = I915_READ(wm0_pipe_reg[pipe]);
a42a5719 3920 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
ce0e0713 3921 hw->wm_linetime[pipe] = I915_READ(PIPE_WM_LINETIME(pipe));
243e6a44 3922
3ef00284 3923 active->pipe_enabled = intel_crtc->active;
2a44b76b
VS		 3924
3925 if (active->pipe_enabled) {
243e6a44
VS		 3926 u32 tmp = hw->wm_pipe[pipe];
3927
3928 /*
3929 * For active pipes LP0 watermark is marked as
3930 * enabled, and LP1+ watermaks as disabled since
3931 * we can't really reverse compute them in case
3932 * multiple pipes are active.
3933 */
3934 active->wm[0].enable = true;
3935 active->wm[0].pri_val = (tmp & WM0_PIPE_PLANE_MASK) >> WM0_PIPE_PLANE_SHIFT;
3936 active->wm[0].spr_val = (tmp & WM0_PIPE_SPRITE_MASK) >> WM0_PIPE_SPRITE_SHIFT;
3937 active->wm[0].cur_val = tmp & WM0_PIPE_CURSOR_MASK;
3938 active->linetime = hw->wm_linetime[pipe];
3939 } else {
3940 int level, max_level = ilk_wm_max_level(dev);
3941
3942 /*
3943 * For inactive pipes, all watermark levels
3944 * should be marked as enabled but zeroed,
3945 * which is what we'd compute them to.
3946 */
3947 for (level = 0; level <= max_level; level++)
3948 active->wm[level].enable = true;
3949 }
3950}
3951
6eb1a681
VS		 3952#define _FW_WM(value, plane) \
3953 (((value) & DSPFW_ ## plane ## _MASK) >> DSPFW_ ## plane ## _SHIFT)
3954#define _FW_WM_VLV(value, plane) \
3955 (((value) & DSPFW_ ## plane ## _MASK_VLV) >> DSPFW_ ## plane ## _SHIFT)
3956
3957static void vlv_read_wm_values(struct drm_i915_private *dev_priv,
3958 struct vlv_wm_values *wm)
3959{
3960 enum pipe pipe;
3961 uint32_t tmp;
3962
3963 for_each_pipe(dev_priv, pipe) {
3964 tmp = I915_READ(VLV_DDL(pipe));
3965
3966 wm->ddl[pipe].primary =
3967 (tmp >> DDL_PLANE_SHIFT) & (DDL_PRECISION_HIGH | DRAIN_LATENCY_MASK);
3968 wm->ddl[pipe].cursor =
3969 (tmp >> DDL_CURSOR_SHIFT) & (DDL_PRECISION_HIGH | DRAIN_LATENCY_MASK);
3970 wm->ddl[pipe].sprite[0] =
3971 (tmp >> DDL_SPRITE_SHIFT(0)) & (DDL_PRECISION_HIGH | DRAIN_LATENCY_MASK);
3972 wm->ddl[pipe].sprite[1] =
3973 (tmp >> DDL_SPRITE_SHIFT(1)) & (DDL_PRECISION_HIGH | DRAIN_LATENCY_MASK);
3974 }
3975
3976 tmp = I915_READ(DSPFW1);
3977 wm->sr.plane = _FW_WM(tmp, SR);
3978 wm->pipe[PIPE_B].cursor = _FW_WM(tmp, CURSORB);
3979 wm->pipe[PIPE_B].primary = _FW_WM_VLV(tmp, PLANEB);
3980 wm->pipe[PIPE_A].primary = _FW_WM_VLV(tmp, PLANEA);
3981
3982 tmp = I915_READ(DSPFW2);
3983 wm->pipe[PIPE_A].sprite[1] = _FW_WM_VLV(tmp, SPRITEB);
3984 wm->pipe[PIPE_A].cursor = _FW_WM(tmp, CURSORA);
3985 wm->pipe[PIPE_A].sprite[0] = _FW_WM_VLV(tmp, SPRITEA);
3986
3987 tmp = I915_READ(DSPFW3);
3988 wm->sr.cursor = _FW_WM(tmp, CURSOR_SR);
3989
3990 if (IS_CHERRYVIEW(dev_priv)) {
3991 tmp = I915_READ(DSPFW7_CHV);
3992 wm->pipe[PIPE_B].sprite[1] = _FW_WM_VLV(tmp, SPRITED);
3993 wm->pipe[PIPE_B].sprite[0] = _FW_WM_VLV(tmp, SPRITEC);
3994
3995 tmp = I915_READ(DSPFW8_CHV);
3996 wm->pipe[PIPE_C].sprite[1] = _FW_WM_VLV(tmp, SPRITEF);
3997 wm->pipe[PIPE_C].sprite[0] = _FW_WM_VLV(tmp, SPRITEE);
3998
3999 tmp = I915_READ(DSPFW9_CHV);
4000 wm->pipe[PIPE_C].primary = _FW_WM_VLV(tmp, PLANEC);
4001 wm->pipe[PIPE_C].cursor = _FW_WM(tmp, CURSORC);
4002
4003 tmp = I915_READ(DSPHOWM);
4004 wm->sr.plane |= _FW_WM(tmp, SR_HI) << 9;
4005 wm->pipe[PIPE_C].sprite[1] |= _FW_WM(tmp, SPRITEF_HI) << 8;
4006 wm->pipe[PIPE_C].sprite[0] |= _FW_WM(tmp, SPRITEE_HI) << 8;
4007 wm->pipe[PIPE_C].primary |= _FW_WM(tmp, PLANEC_HI) << 8;
4008 wm->pipe[PIPE_B].sprite[1] |= _FW_WM(tmp, SPRITED_HI) << 8;
4009 wm->pipe[PIPE_B].sprite[0] |= _FW_WM(tmp, SPRITEC_HI) << 8;
4010 wm->pipe[PIPE_B].primary |= _FW_WM(tmp, PLANEB_HI) << 8;
4011 wm->pipe[PIPE_A].sprite[1] |= _FW_WM(tmp, SPRITEB_HI) << 8;
4012 wm->pipe[PIPE_A].sprite[0] |= _FW_WM(tmp, SPRITEA_HI) << 8;
4013 wm->pipe[PIPE_A].primary |= _FW_WM(tmp, PLANEA_HI) << 8;
4014 } else {
4015 tmp = I915_READ(DSPFW7);
4016 wm->pipe[PIPE_B].sprite[1] = _FW_WM_VLV(tmp, SPRITED);
4017 wm->pipe[PIPE_B].sprite[0] = _FW_WM_VLV(tmp, SPRITEC);
4018
4019 tmp = I915_READ(DSPHOWM);
4020 wm->sr.plane |= _FW_WM(tmp, SR_HI) << 9;
4021 wm->pipe[PIPE_B].sprite[1] |= _FW_WM(tmp, SPRITED_HI) << 8;
4022 wm->pipe[PIPE_B].sprite[0] |= _FW_WM(tmp, SPRITEC_HI) << 8;
4023 wm->pipe[PIPE_B].primary |= _FW_WM(tmp, PLANEB_HI) << 8;
4024 wm->pipe[PIPE_A].sprite[1] |= _FW_WM(tmp, SPRITEB_HI) << 8;
4025 wm->pipe[PIPE_A].sprite[0] |= _FW_WM(tmp, SPRITEA_HI) << 8;
4026 wm->pipe[PIPE_A].primary |= _FW_WM(tmp, PLANEA_HI) << 8;
4027 }
4028}
4029
4030#undef _FW_WM
4031#undef _FW_WM_VLV
4032
4033void vlv_wm_get_hw_state(struct drm_device *dev)
4034{
4035 struct drm_i915_private *dev_priv = to_i915(dev);
4036 struct vlv_wm_values *wm = &dev_priv->wm.vlv;
4037 struct intel_plane *plane;
4038 enum pipe pipe;
4039 u32 val;
4040
4041 vlv_read_wm_values(dev_priv, wm);
4042
4043 for_each_intel_plane(dev, plane) {
4044 switch (plane->base.type) {
4045 int sprite;
4046 case DRM_PLANE_TYPE_CURSOR:
4047 plane->wm.fifo_size = 63;
4048 break;
4049 case DRM_PLANE_TYPE_PRIMARY:
4050 plane->wm.fifo_size = vlv_get_fifo_size(dev, plane->pipe, 0);
4051 break;
4052 case DRM_PLANE_TYPE_OVERLAY:
4053 sprite = plane->plane;
4054 plane->wm.fifo_size = vlv_get_fifo_size(dev, plane->pipe, sprite + 1);
4055 break;
4056 }
4057 }
4058
4059 wm->cxsr = I915_READ(FW_BLC_SELF_VLV) & FW_CSPWRDWNEN;
4060 wm->level = VLV_WM_LEVEL_PM2;
4061
4062 if (IS_CHERRYVIEW(dev_priv)) {
4063 mutex_lock(&dev_priv->rps.hw_lock);
4064
4065 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
4066 if (val & DSP_MAXFIFO_PM5_ENABLE)
4067 wm->level = VLV_WM_LEVEL_PM5;
4068
4069 val = vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2);
4070 if ((val & FORCE_DDR_HIGH_FREQ) == 0)
4071 wm->level = VLV_WM_LEVEL_DDR_DVFS;
4072
4073 mutex_unlock(&dev_priv->rps.hw_lock);
4074 }
4075
4076 for_each_pipe(dev_priv, pipe)
4077 DRM_DEBUG_KMS("Initial watermarks: pipe %c, plane=%d, cursor=%d, sprite0=%d, sprite1=%d\n",
4078 pipe_name(pipe), wm->pipe[pipe].primary, wm->pipe[pipe].cursor,
4079 wm->pipe[pipe].sprite[0], wm->pipe[pipe].sprite[1]);
4080
4081 DRM_DEBUG_KMS("Initial watermarks: SR plane=%d, SR cursor=%d level=%d cxsr=%d\n",
4082 wm->sr.plane, wm->sr.cursor, wm->level, wm->cxsr);
4083}
4084
243e6a44
VS		 4085void ilk_wm_get_hw_state(struct drm_device *dev)
4086{
4087 struct drm_i915_private *dev_priv = dev->dev_private;
820c1980 4088 struct ilk_wm_values *hw = &dev_priv->wm.hw;
243e6a44
VS		 4089 struct drm_crtc *crtc;
4090
70e1e0ec 4091 for_each_crtc(dev, crtc)
243e6a44
VS		 4092 ilk_pipe_wm_get_hw_state(crtc);
4093
4094 hw->wm_lp[0] = I915_READ(WM1_LP_ILK);
4095 hw->wm_lp[1] = I915_READ(WM2_LP_ILK);
4096 hw->wm_lp[2] = I915_READ(WM3_LP_ILK);
4097
4098 hw->wm_lp_spr[0] = I915_READ(WM1S_LP_ILK);
cfa7698b
VS		 4099 if (INTEL_INFO(dev)->gen >= 7) {
4100 hw->wm_lp_spr[1] = I915_READ(WM2S_LP_IVB);
4101 hw->wm_lp_spr[2] = I915_READ(WM3S_LP_IVB);
4102 }
243e6a44 4103
a42a5719 4104 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
ac9545fd
VS		 4105 hw->partitioning = (I915_READ(WM_MISC) & WM_MISC_DATA_PARTITION_5_6) ?
4106 INTEL_DDB_PART_5_6 : INTEL_DDB_PART_1_2;
4107 else if (IS_IVYBRIDGE(dev))
4108 hw->partitioning = (I915_READ(DISP_ARB_CTL2) & DISP_DATA_PARTITION_5_6) ?
4109 INTEL_DDB_PART_5_6 : INTEL_DDB_PART_1_2;
243e6a44
VS		 4110
4111 hw->enable_fbc_wm =
4112 !(I915_READ(DISP_ARB_CTL) & DISP_FBC_WM_DIS);
4113}
4114
b445e3b0
ED		 4115/**
4116 * intel_update_watermarks - update FIFO watermark values based on current modes
4117 *
4118 * Calculate watermark values for the various WM regs based on current mode
4119 * and plane configuration.
4120 *
4121 * There are several cases to deal with here:
4122 * - normal (i.e. non-self-refresh)
4123 * - self-refresh (SR) mode
4124 * - lines are large relative to FIFO size (buffer can hold up to 2)
4125 * - lines are small relative to FIFO size (buffer can hold more than 2
4126 * lines), so need to account for TLB latency
4127 *
4128 * The normal calculation is:
4129 * watermark = dotclock * bytes per pixel * latency
4130 * where latency is platform & configuration dependent (we assume pessimal
4131 * values here).
4132 *
4133 * The SR calculation is:
4134 * watermark = (trunc(latency/line time)+1) * surface width *
4135 * bytes per pixel
4136 * where
4137 * line time = htotal / dotclock
4138 * surface width = hdisplay for normal plane and 64 for cursor
4139 * and latency is assumed to be high, as above.
4140 *
4141 * The final value programmed to the register should always be rounded up,
4142 * and include an extra 2 entries to account for clock crossings.
4143 *
4144 * We don't use the sprite, so we can ignore that. And on Crestline we have
4145 * to set the non-SR watermarks to 8.
4146 */
46ba614c 4147void intel_update_watermarks(struct drm_crtc *crtc)
b445e3b0 4148{
46ba614c 4149 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
b445e3b0
ED		 4150
4151 if (dev_priv->display.update_wm)
46ba614c 4152 dev_priv->display.update_wm(crtc);
b445e3b0
ED		 4153}
4154
adf3d35e
VS		 4155void intel_update_sprite_watermarks(struct drm_plane *plane,
4156 struct drm_crtc *crtc,
ed57cb8a
DL		 4157 uint32_t sprite_width,
4158 uint32_t sprite_height,
4159 int pixel_size,
39db4a4d 4160 bool enabled, bool scaled)
b445e3b0 4161{
adf3d35e 4162 struct drm_i915_private *dev_priv = plane->dev->dev_private;
b445e3b0
ED		 4163
4164 if (dev_priv->display.update_sprite_wm)
ed57cb8a
DL		 4165 dev_priv->display.update_sprite_wm(plane, crtc,
4166 sprite_width, sprite_height,
39db4a4d 4167 pixel_size, enabled, scaled);
b445e3b0
ED		 4168}
4169
9270388e
DV		 4170/**
4171 * Lock protecting IPS related data structures
9270388e
DV		 4172 */
4173DEFINE_SPINLOCK(mchdev_lock);
4174
4175/* Global for IPS driver to get at the current i915 device. Protected by
4176 * mchdev_lock. */
4177static struct drm_i915_private *i915_mch_dev;
4178
2b4e57bd
ED		 4179bool ironlake_set_drps(struct drm_device *dev, u8 val)
4180{
4181 struct drm_i915_private *dev_priv = dev->dev_private;
4182 u16 rgvswctl;
4183
9270388e
DV		 4184 assert_spin_locked(&mchdev_lock);
4185
2b4e57bd
ED		 4186 rgvswctl = I915_READ16(MEMSWCTL);
4187 if (rgvswctl & MEMCTL_CMD_STS) {
4188 DRM_DEBUG("gpu busy, RCS change rejected\n");
4189 return false; /* still busy with another command */
4190 }
4191
4192 rgvswctl = (MEMCTL_CMD_CHFREQ << MEMCTL_CMD_SHIFT) |
4193 (val << MEMCTL_FREQ_SHIFT) | MEMCTL_SFCAVM;
4194 I915_WRITE16(MEMSWCTL, rgvswctl);
4195 POSTING_READ16(MEMSWCTL);
4196
4197 rgvswctl |= MEMCTL_CMD_STS;
4198 I915_WRITE16(MEMSWCTL, rgvswctl);
4199
4200 return true;
4201}
4202
8090c6b9 4203static void ironlake_enable_drps(struct drm_device *dev)
2b4e57bd
ED		 4204{
4205 struct drm_i915_private *dev_priv = dev->dev_private;
4206 u32 rgvmodectl = I915_READ(MEMMODECTL);
4207 u8 fmax, fmin, fstart, vstart;
4208
9270388e
DV		 4209 spin_lock_irq(&mchdev_lock);
4210
2b4e57bd
ED		 4211 /* Enable temp reporting */
4212 I915_WRITE16(PMMISC, I915_READ(PMMISC) | MCPPCE_EN);
4213 I915_WRITE16(TSC1, I915_READ(TSC1) | TSE);
4214
4215 /* 100ms RC evaluation intervals */
4216 I915_WRITE(RCUPEI, 100000);
4217 I915_WRITE(RCDNEI, 100000);
4218
4219 /* Set max/min thresholds to 90ms and 80ms respectively */
4220 I915_WRITE(RCBMAXAVG, 90000);
4221 I915_WRITE(RCBMINAVG, 80000);
4222
4223 I915_WRITE(MEMIHYST, 1);
4224
4225 /* Set up min, max, and cur for interrupt handling */
4226 fmax = (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT;
4227 fmin = (rgvmodectl & MEMMODE_FMIN_MASK);
4228 fstart = (rgvmodectl & MEMMODE_FSTART_MASK) >>
4229 MEMMODE_FSTART_SHIFT;
4230
4231 vstart = (I915_READ(PXVFREQ_BASE + (fstart * 4)) & PXVFREQ_PX_MASK) >>
4232 PXVFREQ_PX_SHIFT;
4233
20e4d407
DV		 4234 dev_priv->ips.fmax = fmax; /* IPS callback will increase this */
4235 dev_priv->ips.fstart = fstart;
2b4e57bd 4236
20e4d407
DV		 4237 dev_priv->ips.max_delay = fstart;
4238 dev_priv->ips.min_delay = fmin;
4239 dev_priv->ips.cur_delay = fstart;
2b4e57bd
ED		 4240
4241 DRM_DEBUG_DRIVER("fmax: %d, fmin: %d, fstart: %d\n",
4242 fmax, fmin, fstart);
4243
4244 I915_WRITE(MEMINTREN, MEMINT_CX_SUPR_EN | MEMINT_EVAL_CHG_EN);
4245
4246 /*
4247 * Interrupts will be enabled in ironlake_irq_postinstall
4248 */
4249
4250 I915_WRITE(VIDSTART, vstart);
4251 POSTING_READ(VIDSTART);
4252
4253 rgvmodectl |= MEMMODE_SWMODE_EN;
4254 I915_WRITE(MEMMODECTL, rgvmodectl);
4255
9270388e 4256 if (wait_for_atomic((I915_READ(MEMSWCTL) & MEMCTL_CMD_STS) == 0, 10))
2b4e57bd 4257 DRM_ERROR("stuck trying to change perf mode\n");
6adfb1ef 4258 msleep(1);
2b4e57bd
ED		 4259
4260 ironlake_set_drps(dev, fstart);
4261
20e4d407 4262 dev_priv->ips.last_count1 = I915_READ(0x112e4) + I915_READ(0x112e8) +
2b4e57bd 4263 I915_READ(0x112e0);
20e4d407
DV		 4264 dev_priv->ips.last_time1 = jiffies_to_msecs(jiffies);
4265 dev_priv->ips.last_count2 = I915_READ(0x112f4);
5ed0bdf2 4266 dev_priv->ips.last_time2 = ktime_get_raw_ns();
9270388e
DV		 4267
4268 spin_unlock_irq(&mchdev_lock);
2b4e57bd
ED		 4269}
4270
8090c6b9 4271static void ironlake_disable_drps(struct drm_device *dev)
2b4e57bd
ED		 4272{
4273 struct drm_i915_private *dev_priv = dev->dev_private;
9270388e
DV		 4274 u16 rgvswctl;
4275
4276 spin_lock_irq(&mchdev_lock);
4277
4278 rgvswctl = I915_READ16(MEMSWCTL);
2b4e57bd
ED		 4279
4280 /* Ack interrupts, disable EFC interrupt */
4281 I915_WRITE(MEMINTREN, I915_READ(MEMINTREN) & ~MEMINT_EVAL_CHG_EN);
4282 I915_WRITE(MEMINTRSTS, MEMINT_EVAL_CHG);
4283 I915_WRITE(DEIER, I915_READ(DEIER) & ~DE_PCU_EVENT);
4284 I915_WRITE(DEIIR, DE_PCU_EVENT);
4285 I915_WRITE(DEIMR, I915_READ(DEIMR) | DE_PCU_EVENT);
4286
4287 /* Go back to the starting frequency */
20e4d407 4288 ironlake_set_drps(dev, dev_priv->ips.fstart);
6adfb1ef 4289 msleep(1);
2b4e57bd
ED		 4290 rgvswctl |= MEMCTL_CMD_STS;
4291 I915_WRITE(MEMSWCTL, rgvswctl);
6adfb1ef 4292 msleep(1);
2b4e57bd 4293
9270388e 4294 spin_unlock_irq(&mchdev_lock);
2b4e57bd
ED		 4295}
4296
acbe9475
DV		 4297/* There's a funny hw issue where the hw returns all 0 when reading from
4298 * GEN6_RP_INTERRUPT_LIMITS. Hence we always need to compute the desired value
4299 * ourselves, instead of doing a rmw cycle (which might result in us clearing
4300 * all limits and the gpu stuck at whatever frequency it is at atm).
4301 */
74ef1173 4302static u32 intel_rps_limits(struct drm_i915_private *dev_priv, u8 val)
2b4e57bd 4303{
7b9e0ae6 4304 u32 limits;
2b4e57bd 4305
20b46e59
DV		 4306 /* Only set the down limit when we've reached the lowest level to avoid
4307 * getting more interrupts, otherwise leave this clear. This prevents a
4308 * race in the hw when coming out of rc6: There's a tiny window where
4309 * the hw runs at the minimal clock before selecting the desired
4310 * frequency, if the down threshold expires in that window we will not
4311 * receive a down interrupt. */
74ef1173
AG		 4312 if (IS_GEN9(dev_priv->dev)) {
4313 limits = (dev_priv->rps.max_freq_softlimit) << 23;
4314 if (val <= dev_priv->rps.min_freq_softlimit)
4315 limits |= (dev_priv->rps.min_freq_softlimit) << 14;
4316 } else {
4317 limits = dev_priv->rps.max_freq_softlimit << 24;
4318 if (val <= dev_priv->rps.min_freq_softlimit)
4319 limits |= dev_priv->rps.min_freq_softlimit << 16;
4320 }
20b46e59
DV		 4321
4322 return limits;
4323}
4324
dd75fdc8
CW		 4325static void gen6_set_rps_thresholds(struct drm_i915_private *dev_priv, u8 val)
4326{
4327 int new_power;
8a586437
AG		 4328 u32 threshold_up = 0, threshold_down = 0; /* in % */
4329 u32 ei_up = 0, ei_down = 0;
dd75fdc8
CW		 4330
4331 new_power = dev_priv->rps.power;
4332 switch (dev_priv->rps.power) {
4333 case LOW_POWER:
b39fb297 4334 if (val > dev_priv->rps.efficient_freq + 1 && val > dev_priv->rps.cur_freq)
dd75fdc8
CW		 4335 new_power = BETWEEN;
4336 break;
4337
4338 case BETWEEN:
b39fb297 4339 if (val <= dev_priv->rps.efficient_freq && val < dev_priv->rps.cur_freq)
dd75fdc8 4340 new_power = LOW_POWER;
b39fb297 4341 else if (val >= dev_priv->rps.rp0_freq && val > dev_priv->rps.cur_freq)
dd75fdc8
CW		 4342 new_power = HIGH_POWER;
4343 break;
4344
4345 case HIGH_POWER:
b39fb297 4346 if (val < (dev_priv->rps.rp1_freq + dev_priv->rps.rp0_freq) >> 1 && val < dev_priv->rps.cur_freq)
dd75fdc8
CW		 4347 new_power = BETWEEN;
4348 break;
4349 }
4350 /* Max/min bins are special */
aed242ff 4351 if (val <= dev_priv->rps.min_freq_softlimit)
dd75fdc8 4352 new_power = LOW_POWER;
aed242ff 4353 if (val >= dev_priv->rps.max_freq_softlimit)
dd75fdc8
CW		 4354 new_power = HIGH_POWER;
4355 if (new_power == dev_priv->rps.power)
4356 return;
4357
4358 /* Note the units here are not exactly 1us, but 1280ns. */
4359 switch (new_power) {
4360 case LOW_POWER:
4361 /* Upclock if more than 95% busy over 16ms */
8a586437
AG		 4362 ei_up = 16000;
4363 threshold_up = 95;
dd75fdc8
CW		 4364
4365 /* Downclock if less than 85% busy over 32ms */
8a586437
AG		 4366 ei_down = 32000;
4367 threshold_down = 85;
dd75fdc8
CW		 4368 break;
4369
4370 case BETWEEN:
4371 /* Upclock if more than 90% busy over 13ms */
8a586437
AG		 4372 ei_up = 13000;
4373 threshold_up = 90;
dd75fdc8
CW		 4374
4375 /* Downclock if less than 75% busy over 32ms */
8a586437
AG		 4376 ei_down = 32000;
4377 threshold_down = 75;
dd75fdc8
CW		 4378 break;
4379
4380 case HIGH_POWER:
4381 /* Upclock if more than 85% busy over 10ms */
8a586437
AG		 4382 ei_up = 10000;
4383 threshold_up = 85;
dd75fdc8
CW		 4384
4385 /* Downclock if less than 60% busy over 32ms */
8a586437
AG		 4386 ei_down = 32000;
4387 threshold_down = 60;
dd75fdc8
CW		 4388 break;
4389 }
4390
8a586437
AG		 4391 I915_WRITE(GEN6_RP_UP_EI,
4392 GT_INTERVAL_FROM_US(dev_priv, ei_up));
4393 I915_WRITE(GEN6_RP_UP_THRESHOLD,
4394 GT_INTERVAL_FROM_US(dev_priv, (ei_up * threshold_up / 100)));
4395
4396 I915_WRITE(GEN6_RP_DOWN_EI,
4397 GT_INTERVAL_FROM_US(dev_priv, ei_down));
4398 I915_WRITE(GEN6_RP_DOWN_THRESHOLD,
4399 GT_INTERVAL_FROM_US(dev_priv, (ei_down * threshold_down / 100)));
4400
4401 I915_WRITE(GEN6_RP_CONTROL,
4402 GEN6_RP_MEDIA_TURBO |
4403 GEN6_RP_MEDIA_HW_NORMAL_MODE |
4404 GEN6_RP_MEDIA_IS_GFX |
4405 GEN6_RP_ENABLE |
4406 GEN6_RP_UP_BUSY_AVG |
4407 GEN6_RP_DOWN_IDLE_AVG);
4408
dd75fdc8 4409 dev_priv->rps.power = new_power;
8fb55197
CW		 4410 dev_priv->rps.up_threshold = threshold_up;
4411 dev_priv->rps.down_threshold = threshold_down;
dd75fdc8
CW		 4412 dev_priv->rps.last_adj = 0;
4413}
4414
2876ce73
CW		 4415static u32 gen6_rps_pm_mask(struct drm_i915_private *dev_priv, u8 val)
4416{
4417 u32 mask = 0;
4418
4419 if (val > dev_priv->rps.min_freq_softlimit)
6f4b12f8 4420 mask |= GEN6_PM_RP_DOWN_EI_EXPIRED | GEN6_PM_RP_DOWN_THRESHOLD | GEN6_PM_RP_DOWN_TIMEOUT;
2876ce73 4421 if (val < dev_priv->rps.max_freq_softlimit)
6f4b12f8 4422 mask |= GEN6_PM_RP_UP_EI_EXPIRED | GEN6_PM_RP_UP_THRESHOLD;
2876ce73 4423
7b3c29f6
CW		 4424 mask &= dev_priv->pm_rps_events;
4425
59d02a1f 4426 return gen6_sanitize_rps_pm_mask(dev_priv, ~mask);
2876ce73
CW		 4427}
4428
b8a5ff8d
JM		 4429/* gen6_set_rps is called to update the frequency request, but should also be
4430 * called when the range (min_delay and max_delay) is modified so that we can
4431 * update the GEN6_RP_INTERRUPT_LIMITS register accordingly. */
ffe02b40 4432static void gen6_set_rps(struct drm_device *dev, u8 val)
20b46e59
DV		 4433{
4434 struct drm_i915_private *dev_priv = dev->dev_private;
7b9e0ae6 4435
4fc688ce 4436 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
aed242ff
CW		 4437 WARN_ON(val > dev_priv->rps.max_freq);
4438 WARN_ON(val < dev_priv->rps.min_freq);
004777cb 4439
eb64cad1
CW		 4440 /* min/max delay may still have been modified so be sure to
4441 * write the limits value.
4442 */
4443 if (val != dev_priv->rps.cur_freq) {
4444 gen6_set_rps_thresholds(dev_priv, val);
b8a5ff8d 4445
5704195c
AG		 4446 if (IS_GEN9(dev))
4447 I915_WRITE(GEN6_RPNSWREQ,
4448 GEN9_FREQUENCY(val));
4449 else if (IS_HASWELL(dev) || IS_BROADWELL(dev))
eb64cad1
CW		 4450 I915_WRITE(GEN6_RPNSWREQ,
4451 HSW_FREQUENCY(val));
4452 else
4453 I915_WRITE(GEN6_RPNSWREQ,
4454 GEN6_FREQUENCY(val) |
4455 GEN6_OFFSET(0) |
4456 GEN6_AGGRESSIVE_TURBO);
b8a5ff8d 4457 }
7b9e0ae6 4458
7b9e0ae6
CW		 4459 /* Make sure we continue to get interrupts
4460 * until we hit the minimum or maximum frequencies.
4461 */
74ef1173 4462 I915_WRITE(GEN6_RP_INTERRUPT_LIMITS, intel_rps_limits(dev_priv, val));
2876ce73 4463 I915_WRITE(GEN6_PMINTRMSK, gen6_rps_pm_mask(dev_priv, val));
7b9e0ae6 4464
d5570a72
BW		 4465 POSTING_READ(GEN6_RPNSWREQ);
4466
b39fb297 4467 dev_priv->rps.cur_freq = val;
be2cde9a 4468 trace_intel_gpu_freq_change(val * 50);
2b4e57bd
ED		 4469}
4470
ffe02b40
VS		 4471static void valleyview_set_rps(struct drm_device *dev, u8 val)
4472{
4473 struct drm_i915_private *dev_priv = dev->dev_private;
4474
4475 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
aed242ff
CW		 4476 WARN_ON(val > dev_priv->rps.max_freq);
4477 WARN_ON(val < dev_priv->rps.min_freq);
ffe02b40
VS		 4478
4479 if (WARN_ONCE(IS_CHERRYVIEW(dev) && (val & 1),
4480 "Odd GPU freq value\n"))
4481 val &= ~1;
4482
8fb55197 4483 if (val != dev_priv->rps.cur_freq) {
ffe02b40 4484 vlv_punit_write(dev_priv, PUNIT_REG_GPU_FREQ_REQ, val);
8fb55197
CW		 4485 if (!IS_CHERRYVIEW(dev_priv))
4486 gen6_set_rps_thresholds(dev_priv, val);
4487 }
ffe02b40
VS		 4488
4489 I915_WRITE(GEN6_PMINTRMSK, gen6_rps_pm_mask(dev_priv, val));
4490
4491 dev_priv->rps.cur_freq = val;
4492 trace_intel_gpu_freq_change(intel_gpu_freq(dev_priv, val));
4493}
4494
a7f6e231 4495/* vlv_set_rps_idle: Set the frequency to idle, if Gfx clocks are down
76c3552f
D		 4496 *
4497 * * If Gfx is Idle, then
a7f6e231
D		 4498 * 1. Forcewake Media well.
4499 * 2. Request idle freq.
4500 * 3. Release Forcewake of Media well.
76c3552f
D		 4501*/
4502static void vlv_set_rps_idle(struct drm_i915_private *dev_priv)
4503{
aed242ff 4504 u32 val = dev_priv->rps.idle_freq;
5549d25f 4505
aed242ff 4506 if (dev_priv->rps.cur_freq <= val)
76c3552f
D		 4507 return;
4508
a7f6e231
D		 4509 /* Wake up the media well, as that takes a lot less
4510 * power than the Render well. */
4511 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_MEDIA);
4512 valleyview_set_rps(dev_priv->dev, val);
4513 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_MEDIA);
76c3552f
D		 4514}
4515
43cf3bf0
CW		 4516void gen6_rps_busy(struct drm_i915_private *dev_priv)
4517{
4518 mutex_lock(&dev_priv->rps.hw_lock);
4519 if (dev_priv->rps.enabled) {
4520 if (dev_priv->pm_rps_events & (GEN6_PM_RP_DOWN_EI_EXPIRED | GEN6_PM_RP_UP_EI_EXPIRED))
4521 gen6_rps_reset_ei(dev_priv);
4522 I915_WRITE(GEN6_PMINTRMSK,
4523 gen6_rps_pm_mask(dev_priv, dev_priv->rps.cur_freq));
4524 }
4525 mutex_unlock(&dev_priv->rps.hw_lock);
4526}
4527
b29c19b6
CW		 4528void gen6_rps_idle(struct drm_i915_private *dev_priv)
4529{
691bb717
DL		 4530 struct drm_device *dev = dev_priv->dev;
4531
b29c19b6 4532 mutex_lock(&dev_priv->rps.hw_lock);
c0951f0c 4533 if (dev_priv->rps.enabled) {
21a11fff 4534 if (IS_VALLEYVIEW(dev))
76c3552f 4535 vlv_set_rps_idle(dev_priv);
7526ed79 4536 else
aed242ff 4537 gen6_set_rps(dev_priv->dev, dev_priv->rps.idle_freq);
c0951f0c 4538 dev_priv->rps.last_adj = 0;
43cf3bf0 4539 I915_WRITE(GEN6_PMINTRMSK, 0xffffffff);
c0951f0c 4540 }
8d3afd7d 4541 mutex_unlock(&dev_priv->rps.hw_lock);
1854d5ca 4542
8d3afd7d 4543 spin_lock(&dev_priv->rps.client_lock);
1854d5ca
CW		 4544 while (!list_empty(&dev_priv->rps.clients))
4545 list_del_init(dev_priv->rps.clients.next);
8d3afd7d 4546 spin_unlock(&dev_priv->rps.client_lock);
b29c19b6
CW		 4547}
4548
1854d5ca 4549void gen6_rps_boost(struct drm_i915_private *dev_priv,
e61b9958
CW		 4550 struct intel_rps_client *rps,
4551 unsigned long submitted)
b29c19b6 4552{
8d3afd7d
CW		 4553 /* This is intentionally racy! We peek at the state here, then
4554 * validate inside the RPS worker.
4555 */
4556 if (!(dev_priv->mm.busy &&
4557 dev_priv->rps.enabled &&
4558 dev_priv->rps.cur_freq < dev_priv->rps.max_freq_softlimit))
4559 return;
43cf3bf0 4560
e61b9958
CW		 4561 /* Force a RPS boost (and don't count it against the client) if
4562 * the GPU is severely congested.
4563 */
d0bc54f2 4564 if (rps && time_after(jiffies, submitted + DRM_I915_THROTTLE_JIFFIES))
e61b9958
CW		 4565 rps = NULL;
4566
8d3afd7d
CW		 4567 spin_lock(&dev_priv->rps.client_lock);
4568 if (rps == NULL || list_empty(&rps->link)) {
4569 spin_lock_irq(&dev_priv->irq_lock);
4570 if (dev_priv->rps.interrupts_enabled) {
4571 dev_priv->rps.client_boost = true;
4572 queue_work(dev_priv->wq, &dev_priv->rps.work);
4573 }
4574 spin_unlock_irq(&dev_priv->irq_lock);
1854d5ca 4575
2e1b8730
CW		 4576 if (rps != NULL) {
4577 list_add(&rps->link, &dev_priv->rps.clients);
4578 rps->boosts++;
1854d5ca
CW		 4579 } else
4580 dev_priv->rps.boosts++;
c0951f0c 4581 }
8d3afd7d 4582 spin_unlock(&dev_priv->rps.client_lock);
b29c19b6
CW		 4583}
4584
ffe02b40 4585void intel_set_rps(struct drm_device *dev, u8 val)
0a073b84 4586{
ffe02b40
VS		 4587 if (IS_VALLEYVIEW(dev))
4588 valleyview_set_rps(dev, val);
4589 else
4590 gen6_set_rps(dev, val);
0a073b84
JB		 4591}
4592
20e49366
ZW		 4593static void gen9_disable_rps(struct drm_device *dev)
4594{
4595 struct drm_i915_private *dev_priv = dev->dev_private;
4596
4597 I915_WRITE(GEN6_RC_CONTROL, 0);
38c23527 4598 I915_WRITE(GEN9_PG_ENABLE, 0);
20e49366
ZW		 4599}
4600
44fc7d5c 4601static void gen6_disable_rps(struct drm_device *dev)
d20d4f0c
JB		 4602{
4603 struct drm_i915_private *dev_priv = dev->dev_private;
4604
4605 I915_WRITE(GEN6_RC_CONTROL, 0);
44fc7d5c 4606 I915_WRITE(GEN6_RPNSWREQ, 1 << 31);
44fc7d5c
DV		 4607}
4608
38807746
D		 4609static void cherryview_disable_rps(struct drm_device *dev)
4610{
4611 struct drm_i915_private *dev_priv = dev->dev_private;
4612
4613 I915_WRITE(GEN6_RC_CONTROL, 0);
4614}
4615
44fc7d5c
DV		 4616static void valleyview_disable_rps(struct drm_device *dev)
4617{
4618 struct drm_i915_private *dev_priv = dev->dev_private;
4619
98a2e5f9
D		 4620 /* we're doing forcewake before Disabling RC6,
4621 * This what the BIOS expects when going into suspend */
59bad947 4622 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
98a2e5f9 4623
44fc7d5c 4624 I915_WRITE(GEN6_RC_CONTROL, 0);
d20d4f0c 4625
59bad947 4626 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
d20d4f0c
JB		 4627}
4628
dc39fff7
BW		 4629static void intel_print_rc6_info(struct drm_device *dev, u32 mode)
4630{
91ca689a
ID		 4631 if (IS_VALLEYVIEW(dev)) {
4632 if (mode & (GEN7_RC_CTL_TO_MODE | GEN6_RC_CTL_EI_MODE(1)))
4633 mode = GEN6_RC_CTL_RC6_ENABLE;
4634 else
4635 mode = 0;
4636 }
58abf1da
RV		 4637 if (HAS_RC6p(dev))
4638 DRM_DEBUG_KMS("Enabling RC6 states: RC6 %s RC6p %s RC6pp %s\n",
4639 (mode & GEN6_RC_CTL_RC6_ENABLE) ? "on" : "off",
4640 (mode & GEN6_RC_CTL_RC6p_ENABLE) ? "on" : "off",
4641 (mode & GEN6_RC_CTL_RC6pp_ENABLE) ? "on" : "off");
4642
4643 else
4644 DRM_DEBUG_KMS("Enabling RC6 states: RC6 %s\n",
4645 (mode & GEN6_RC_CTL_RC6_ENABLE) ? "on" : "off");
dc39fff7
BW		 4646}
4647
e6069ca8 4648static int sanitize_rc6_option(const struct drm_device *dev, int enable_rc6)
2b4e57bd 4649{
e7d66d89
DV		 4650 /* No RC6 before Ironlake and code is gone for ilk. */
4651 if (INTEL_INFO(dev)->gen < 6)
e6069ca8
ID		 4652 return 0;
4653
456470eb 4654 /* Respect the kernel parameter if it is set */
e6069ca8
ID		 4655 if (enable_rc6 >= 0) {
4656 int mask;
4657
58abf1da 4658 if (HAS_RC6p(dev))
e6069ca8
ID		 4659 mask = INTEL_RC6_ENABLE | INTEL_RC6p_ENABLE |
4660 INTEL_RC6pp_ENABLE;
4661 else
4662 mask = INTEL_RC6_ENABLE;
4663
4664 if ((enable_rc6 & mask) != enable_rc6)
8dfd1f04
DV		 4665 DRM_DEBUG_KMS("Adjusting RC6 mask to %d (requested %d, valid %d)\n",
4666 enable_rc6 & mask, enable_rc6, mask);
e6069ca8
ID		 4667
4668 return enable_rc6 & mask;
4669 }
2b4e57bd 4670
8bade1ad 4671 if (IS_IVYBRIDGE(dev))
cca84a1f 4672 return (INTEL_RC6_ENABLE | INTEL_RC6p_ENABLE);
8bade1ad
BW		 4673
4674 return INTEL_RC6_ENABLE;
2b4e57bd
ED		 4675}
4676
e6069ca8
ID		 4677int intel_enable_rc6(const struct drm_device *dev)
4678{
4679 return i915.enable_rc6;
4680}
4681
93ee2920 4682static void gen6_init_rps_frequencies(struct drm_device *dev)
3280e8b0 4683{
93ee2920
TR		 4684 struct drm_i915_private *dev_priv = dev->dev_private;
4685 uint32_t rp_state_cap;
4686 u32 ddcc_status = 0;
4687 int ret;
4688
3280e8b0
BW		 4689 /* All of these values are in units of 50MHz */
4690 dev_priv->rps.cur_freq = 0;
93ee2920 4691 /* static values from HW: RP0 > RP1 > RPn (min_freq) */
35040562
BP		 4692 if (IS_BROXTON(dev)) {
4693 rp_state_cap = I915_READ(BXT_RP_STATE_CAP);
4694 dev_priv->rps.rp0_freq = (rp_state_cap >> 16) & 0xff;
4695 dev_priv->rps.rp1_freq = (rp_state_cap >> 8) & 0xff;
4696 dev_priv->rps.min_freq = (rp_state_cap >> 0) & 0xff;
4697 } else {
4698 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
4699 dev_priv->rps.rp0_freq = (rp_state_cap >> 0) & 0xff;
4700 dev_priv->rps.rp1_freq = (rp_state_cap >> 8) & 0xff;
4701 dev_priv->rps.min_freq = (rp_state_cap >> 16) & 0xff;
4702 }
4703
cee991cb
AG		 4704 if (IS_SKYLAKE(dev)) {
4705 /* Store the frequency values in 16.66 MHZ units, which is
4706 the natural hardware unit for SKL */
4707 dev_priv->rps.rp0_freq *= GEN9_FREQ_SCALER;
4708 dev_priv->rps.rp1_freq *= GEN9_FREQ_SCALER;
4709 dev_priv->rps.min_freq *= GEN9_FREQ_SCALER;
4710 }
3280e8b0
BW		 4711 /* hw_max = RP0 until we check for overclocking */
4712 dev_priv->rps.max_freq = dev_priv->rps.rp0_freq;
4713
93ee2920
TR		 4714 dev_priv->rps.efficient_freq = dev_priv->rps.rp1_freq;
4715 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
4716 ret = sandybridge_pcode_read(dev_priv,
4717 HSW_PCODE_DYNAMIC_DUTY_CYCLE_CONTROL,
4718 &ddcc_status);
4719 if (0 == ret)
4720 dev_priv->rps.efficient_freq =
46efa4ab
TR		 4721 clamp_t(u8,
4722 ((ddcc_status >> 8) & 0xff),
4723 dev_priv->rps.min_freq,
4724 dev_priv->rps.max_freq);
93ee2920
TR		 4725 }
4726
aed242ff
CW		 4727 dev_priv->rps.idle_freq = dev_priv->rps.min_freq;
4728
3280e8b0
BW		 4729 /* Preserve min/max settings in case of re-init */
4730 if (dev_priv->rps.max_freq_softlimit == 0)
4731 dev_priv->rps.max_freq_softlimit = dev_priv->rps.max_freq;
4732
93ee2920
TR		 4733 if (dev_priv->rps.min_freq_softlimit == 0) {
4734 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
4735 dev_priv->rps.min_freq_softlimit =
813b5e69
VS		 4736 max_t(int, dev_priv->rps.efficient_freq,
4737 intel_freq_opcode(dev_priv, 450));
93ee2920
TR		 4738 else
4739 dev_priv->rps.min_freq_softlimit =
4740 dev_priv->rps.min_freq;
4741 }
3280e8b0
BW		 4742}
4743
b6fef0ef 4744/* See the Gen9_GT_PM_Programming_Guide doc for the below */
20e49366 4745static void gen9_enable_rps(struct drm_device *dev)
b6fef0ef
JB		 4746{
4747 struct drm_i915_private *dev_priv = dev->dev_private;
4748
4749 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
4750
ba1c554c
DL		 4751 gen6_init_rps_frequencies(dev);
4752
0beb059a
AG		 4753 /* Program defaults and thresholds for RPS*/
4754 I915_WRITE(GEN6_RC_VIDEO_FREQ,
4755 GEN9_FREQUENCY(dev_priv->rps.rp1_freq));
4756
4757 /* 1 second timeout*/
4758 I915_WRITE(GEN6_RP_DOWN_TIMEOUT,
4759 GT_INTERVAL_FROM_US(dev_priv, 1000000));
4760
b6fef0ef 4761 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 0xa);
b6fef0ef 4762
0beb059a
AG		 4763 /* Leaning on the below call to gen6_set_rps to program/setup the
4764 * Up/Down EI & threshold registers, as well as the RP_CONTROL,
4765 * RP_INTERRUPT_LIMITS & RPNSWREQ registers */
4766 dev_priv->rps.power = HIGH_POWER; /* force a reset */
4767 gen6_set_rps(dev_priv->dev, dev_priv->rps.min_freq_softlimit);
b6fef0ef
JB		 4768
4769 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
4770}
4771
4772static void gen9_enable_rc6(struct drm_device *dev)
20e49366
ZW		 4773{
4774 struct drm_i915_private *dev_priv = dev->dev_private;
4775 struct intel_engine_cs *ring;
4776 uint32_t rc6_mask = 0;
4777 int unused;
4778
4779 /* 1a: Software RC state - RC0 */
4780 I915_WRITE(GEN6_RC_STATE, 0);
4781
4782 /* 1b: Get forcewake during program sequence. Although the driver
4783 * hasn't enabled a state yet where we need forcewake, BIOS may have.*/
59bad947 4784 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
20e49366
ZW		 4785
4786 /* 2a: Disable RC states. */
4787 I915_WRITE(GEN6_RC_CONTROL, 0);
4788
4789 /* 2b: Program RC6 thresholds.*/
4790 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 54 << 16);
4791 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */
4792 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */
4793 for_each_ring(ring, dev_priv, unused)
4794 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
4795 I915_WRITE(GEN6_RC_SLEEP, 0);
4796 I915_WRITE(GEN6_RC6_THRESHOLD, 37500); /* 37.5/125ms per EI */
4797
38c23527
ZW		 4798 /* 2c: Program Coarse Power Gating Policies. */
4799 I915_WRITE(GEN9_MEDIA_PG_IDLE_HYSTERESIS, 25);
4800 I915_WRITE(GEN9_RENDER_PG_IDLE_HYSTERESIS, 25);
4801
20e49366
ZW		 4802 /* 3a: Enable RC6 */
4803 if (intel_enable_rc6(dev) & INTEL_RC6_ENABLE)
4804 rc6_mask = GEN6_RC_CTL_RC6_ENABLE;
4805 DRM_INFO("RC6 %s\n", (rc6_mask & GEN6_RC_CTL_RC6_ENABLE) ?
4806 "on" : "off");
4807 I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE |
4808 GEN6_RC_CTL_EI_MODE(1) |
4809 rc6_mask);
4810
cb07bae0
SK		 4811 /*
4812 * 3b: Enable Coarse Power Gating only when RC6 is enabled.
4813 * WaDisableRenderPowerGating:skl,bxt - Render PG need to be disabled with RC6.
4814 */
a4104c55 4815 I915_WRITE(GEN9_PG_ENABLE, (rc6_mask & GEN6_RC_CTL_RC6_ENABLE) ?
cb07bae0 4816 GEN9_MEDIA_PG_ENABLE : 0);
a4104c55 4817
38c23527 4818
59bad947 4819 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
20e49366
ZW		 4820
4821}
4822
6edee7f3
BW		 4823static void gen8_enable_rps(struct drm_device *dev)
4824{
4825 struct drm_i915_private *dev_priv = dev->dev_private;
a4872ba6 4826 struct intel_engine_cs *ring;
93ee2920 4827 uint32_t rc6_mask = 0;
6edee7f3
BW		 4828 int unused;
4829
4830 /* 1a: Software RC state - RC0 */
4831 I915_WRITE(GEN6_RC_STATE, 0);
4832
4833 /* 1c & 1d: Get forcewake during program sequence. Although the driver
4834 * hasn't enabled a state yet where we need forcewake, BIOS may have.*/
59bad947 4835 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
6edee7f3
BW		 4836
4837 /* 2a: Disable RC states. */
4838 I915_WRITE(GEN6_RC_CONTROL, 0);
4839
93ee2920
TR		 4840 /* Initialize rps frequencies */
4841 gen6_init_rps_frequencies(dev);
6edee7f3
BW		 4842
4843 /* 2b: Program RC6 thresholds.*/
4844 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16);
4845 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */
4846 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */
4847 for_each_ring(ring, dev_priv, unused)
4848 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
4849 I915_WRITE(GEN6_RC_SLEEP, 0);
0d68b25e
TR		 4850 if (IS_BROADWELL(dev))
4851 I915_WRITE(GEN6_RC6_THRESHOLD, 625); /* 800us/1.28 for TO */
4852 else
4853 I915_WRITE(GEN6_RC6_THRESHOLD, 50000); /* 50/125ms per EI */
6edee7f3
BW		 4854
4855 /* 3: Enable RC6 */
4856 if (intel_enable_rc6(dev) & INTEL_RC6_ENABLE)
4857 rc6_mask = GEN6_RC_CTL_RC6_ENABLE;
abbf9d2c 4858 intel_print_rc6_info(dev, rc6_mask);
0d68b25e
TR		 4859 if (IS_BROADWELL(dev))
4860 I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE |
4861 GEN7_RC_CTL_TO_MODE |
4862 rc6_mask);
4863 else
4864 I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE |
4865 GEN6_RC_CTL_EI_MODE(1) |
4866 rc6_mask);
6edee7f3
BW		 4867
4868 /* 4 Program defaults and thresholds for RPS*/
f9bdc585
BW		 4869 I915_WRITE(GEN6_RPNSWREQ,
4870 HSW_FREQUENCY(dev_priv->rps.rp1_freq));
4871 I915_WRITE(GEN6_RC_VIDEO_FREQ,
4872 HSW_FREQUENCY(dev_priv->rps.rp1_freq));
7526ed79
DV		 4873 /* NB: Docs say 1s, and 1000000 - which aren't equivalent */
4874 I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 100000000 / 128); /* 1 second timeout */
4875
4876 /* Docs recommend 900MHz, and 300 MHz respectively */
4877 I915_WRITE(GEN6_RP_INTERRUPT_LIMITS,
4878 dev_priv->rps.max_freq_softlimit << 24 |
4879 dev_priv->rps.min_freq_softlimit << 16);
4880
4881 I915_WRITE(GEN6_RP_UP_THRESHOLD, 7600000 / 128); /* 76ms busyness per EI, 90% */
4882 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 31300000 / 128); /* 313ms busyness per EI, 70%*/
4883 I915_WRITE(GEN6_RP_UP_EI, 66000); /* 84.48ms, XXX: random? */
4884 I915_WRITE(GEN6_RP_DOWN_EI, 350000); /* 448ms, XXX: random? */
4885
4886 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
6edee7f3
BW		 4887
4888 /* 5: Enable RPS */
7526ed79
DV		 4889 I915_WRITE(GEN6_RP_CONTROL,
4890 GEN6_RP_MEDIA_TURBO |
4891 GEN6_RP_MEDIA_HW_NORMAL_MODE |
4892 GEN6_RP_MEDIA_IS_GFX |
4893 GEN6_RP_ENABLE |
4894 GEN6_RP_UP_BUSY_AVG |
4895 GEN6_RP_DOWN_IDLE_AVG);
4896
4897 /* 6: Ring frequency + overclocking (our driver does this later */
4898
c7f3153a 4899 dev_priv->rps.power = HIGH_POWER; /* force a reset */
aed242ff 4900 gen6_set_rps(dev_priv->dev, dev_priv->rps.idle_freq);
7526ed79 4901
59bad947 4902 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
6edee7f3
BW		 4903}
4904
79f5b2c7 4905static void gen6_enable_rps(struct drm_device *dev)
2b4e57bd 4906{
79f5b2c7 4907 struct drm_i915_private *dev_priv = dev->dev_private;
a4872ba6 4908 struct intel_engine_cs *ring;
d060c169 4909 u32 rc6vids, pcu_mbox = 0, rc6_mask = 0;
2b4e57bd 4910 u32 gtfifodbg;
2b4e57bd 4911 int rc6_mode;
42c0526c 4912 int i, ret;
2b4e57bd 4913
4fc688ce 4914 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
79f5b2c7 4915
2b4e57bd
ED		 4916 /* Here begins a magic sequence of register writes to enable
4917 * auto-downclocking.
4918 *
4919 * Perhaps there might be some value in exposing these to
4920 * userspace...
4921 */
4922 I915_WRITE(GEN6_RC_STATE, 0);
2b4e57bd
ED		 4923
4924 /* Clear the DBG now so we don't confuse earlier errors */
4925 if ((gtfifodbg = I915_READ(GTFIFODBG))) {
4926 DRM_ERROR("GT fifo had a previous error %x\n", gtfifodbg);
4927 I915_WRITE(GTFIFODBG, gtfifodbg);
4928 }
4929
59bad947 4930 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
2b4e57bd 4931
93ee2920
TR		 4932 /* Initialize rps frequencies */
4933 gen6_init_rps_frequencies(dev);
dd0a1aa1 4934
2b4e57bd
ED		 4935 /* disable the counters and set deterministic thresholds */
4936 I915_WRITE(GEN6_RC_CONTROL, 0);
4937
4938 I915_WRITE(GEN6_RC1_WAKE_RATE_LIMIT, 1000 << 16);
4939 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16 | 30);
4940 I915_WRITE(GEN6_RC6pp_WAKE_RATE_LIMIT, 30);
4941 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000);
4942 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25);
4943
b4519513
CW		 4944 for_each_ring(ring, dev_priv, i)
4945 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
2b4e57bd
ED		 4946
4947 I915_WRITE(GEN6_RC_SLEEP, 0);
4948 I915_WRITE(GEN6_RC1e_THRESHOLD, 1000);
29c78f60 4949 if (IS_IVYBRIDGE(dev))
351aa566
SM		 4950 I915_WRITE(GEN6_RC6_THRESHOLD, 125000);
4951 else
4952 I915_WRITE(GEN6_RC6_THRESHOLD, 50000);
0920a487 4953 I915_WRITE(GEN6_RC6p_THRESHOLD, 150000);
2b4e57bd
ED		 4954 I915_WRITE(GEN6_RC6pp_THRESHOLD, 64000); /* unused */
4955
5a7dc92a 4956 /* Check if we are enabling RC6 */
2b4e57bd
ED		 4957 rc6_mode = intel_enable_rc6(dev_priv->dev);
4958 if (rc6_mode & INTEL_RC6_ENABLE)
4959 rc6_mask |= GEN6_RC_CTL_RC6_ENABLE;
4960
5a7dc92a
ED		 4961 /* We don't use those on Haswell */
4962 if (!IS_HASWELL(dev)) {
4963 if (rc6_mode & INTEL_RC6p_ENABLE)
4964 rc6_mask |= GEN6_RC_CTL_RC6p_ENABLE;
2b4e57bd 4965
5a7dc92a
ED		 4966 if (rc6_mode & INTEL_RC6pp_ENABLE)
4967 rc6_mask |= GEN6_RC_CTL_RC6pp_ENABLE;
4968 }
2b4e57bd 4969
dc39fff7 4970 intel_print_rc6_info(dev, rc6_mask);
2b4e57bd
ED		 4971
4972 I915_WRITE(GEN6_RC_CONTROL,
4973 rc6_mask |
4974 GEN6_RC_CTL_EI_MODE(1) |
4975 GEN6_RC_CTL_HW_ENABLE);
4976
dd75fdc8
CW		 4977 /* Power down if completely idle for over 50ms */
4978 I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 50000);
2b4e57bd 4979 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
2b4e57bd 4980
42c0526c 4981 ret = sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_MIN_FREQ_TABLE, 0);
d060c169 4982 if (ret)
42c0526c 4983 DRM_DEBUG_DRIVER("Failed to set the min frequency\n");
d060c169
BW		 4984
4985 ret = sandybridge_pcode_read(dev_priv, GEN6_READ_OC_PARAMS, &pcu_mbox);
4986 if (!ret && (pcu_mbox & (1<<31))) { /* OC supported */
4987 DRM_DEBUG_DRIVER("Overclocking supported. Max: %dMHz, Overclock max: %dMHz\n",
b39fb297 4988 (dev_priv->rps.max_freq_softlimit & 0xff) * 50,
d060c169 4989 (pcu_mbox & 0xff) * 50);
b39fb297 4990 dev_priv->rps.max_freq = pcu_mbox & 0xff;
2b4e57bd
ED		 4991 }
4992
dd75fdc8 4993 dev_priv->rps.power = HIGH_POWER; /* force a reset */
aed242ff 4994 gen6_set_rps(dev_priv->dev, dev_priv->rps.idle_freq);
2b4e57bd 4995
31643d54
BW		 4996 rc6vids = 0;
4997 ret = sandybridge_pcode_read(dev_priv, GEN6_PCODE_READ_RC6VIDS, &rc6vids);
4998 if (IS_GEN6(dev) && ret) {
4999 DRM_DEBUG_DRIVER("Couldn't check for BIOS workaround\n");
5000 } else if (IS_GEN6(dev) && (GEN6_DECODE_RC6_VID(rc6vids & 0xff) < 450)) {
5001 DRM_DEBUG_DRIVER("You should update your BIOS. Correcting minimum rc6 voltage (%dmV->%dmV)\n",
5002 GEN6_DECODE_RC6_VID(rc6vids & 0xff), 450);
5003 rc6vids &= 0xffff00;
5004 rc6vids |= GEN6_ENCODE_RC6_VID(450);
5005 ret = sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_RC6VIDS, rc6vids);
5006 if (ret)
5007 DRM_ERROR("Couldn't fix incorrect rc6 voltage\n");
5008 }
5009
59bad947 5010 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
2b4e57bd
ED		 5011}
5012
c2bc2fc5 5013static void __gen6_update_ring_freq(struct drm_device *dev)
2b4e57bd 5014{
79f5b2c7 5015 struct drm_i915_private *dev_priv = dev->dev_private;
2b4e57bd 5016 int min_freq = 15;
3ebecd07
CW		 5017 unsigned int gpu_freq;
5018 unsigned int max_ia_freq, min_ring_freq;
2b4e57bd 5019 int scaling_factor = 180;
eda79642 5020 struct cpufreq_policy *policy;
2b4e57bd 5021
4fc688ce 5022 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
79f5b2c7 5023
eda79642
BW		 5024 policy = cpufreq_cpu_get(0);
5025 if (policy) {
5026 max_ia_freq = policy->cpuinfo.max_freq;
5027 cpufreq_cpu_put(policy);
5028 } else {
5029 /*
5030 * Default to measured freq if none found, PCU will ensure we
5031 * don't go over
5032 */
2b4e57bd 5033 max_ia_freq = tsc_khz;
eda79642 5034 }
2b4e57bd
ED		 5035
5036 /* Convert from kHz to MHz */
5037 max_ia_freq /= 1000;
5038
153b4b95 5039 min_ring_freq = I915_READ(DCLK) & 0xf;
f6aca45c
BW		 5040 /* convert DDR frequency from units of 266.6MHz to bandwidth */
5041 min_ring_freq = mult_frac(min_ring_freq, 8, 3);
3ebecd07 5042
2b4e57bd
ED		 5043 /*
5044 * For each potential GPU frequency, load a ring frequency we'd like
5045 * to use for memory access. We do this by specifying the IA frequency
5046 * the PCU should use as a reference to determine the ring frequency.
5047 */
6985b352 5048 for (gpu_freq = dev_priv->rps.max_freq; gpu_freq >= dev_priv->rps.min_freq;
2b4e57bd 5049 gpu_freq--) {
6985b352 5050 int diff = dev_priv->rps.max_freq - gpu_freq;
3ebecd07
CW		 5051 unsigned int ia_freq = 0, ring_freq = 0;
5052
46c764d4
BW		 5053 if (INTEL_INFO(dev)->gen >= 8) {
5054 /* max(2 * GT, DDR). NB: GT is 50MHz units */
5055 ring_freq = max(min_ring_freq, gpu_freq);
5056 } else if (IS_HASWELL(dev)) {
f6aca45c 5057 ring_freq = mult_frac(gpu_freq, 5, 4);
3ebecd07
CW		 5058 ring_freq = max(min_ring_freq, ring_freq);
5059 /* leave ia_freq as the default, chosen by cpufreq */
5060 } else {
5061 /* On older processors, there is no separate ring
5062 * clock domain, so in order to boost the bandwidth
5063 * of the ring, we need to upclock the CPU (ia_freq).
5064 *
5065 * For GPU frequencies less than 750MHz,
5066 * just use the lowest ring freq.
5067 */
5068 if (gpu_freq < min_freq)
5069 ia_freq = 800;
5070 else
5071 ia_freq = max_ia_freq - ((diff * scaling_factor) / 2);
5072 ia_freq = DIV_ROUND_CLOSEST(ia_freq, 100);
5073 }
2b4e57bd 5074
42c0526c
BW		 5075 sandybridge_pcode_write(dev_priv,
5076 GEN6_PCODE_WRITE_MIN_FREQ_TABLE,
3ebecd07
CW		 5077 ia_freq << GEN6_PCODE_FREQ_IA_RATIO_SHIFT |
5078 ring_freq << GEN6_PCODE_FREQ_RING_RATIO_SHIFT |
5079 gpu_freq);
2b4e57bd 5080 }
2b4e57bd
ED		 5081}
5082
c2bc2fc5
ID		 5083void gen6_update_ring_freq(struct drm_device *dev)
5084{
5085 struct drm_i915_private *dev_priv = dev->dev_private;
5086
5087 if (INTEL_INFO(dev)->gen < 6 || IS_VALLEYVIEW(dev))
5088 return;
5089
5090 mutex_lock(&dev_priv->rps.hw_lock);
5091 __gen6_update_ring_freq(dev);
5092 mutex_unlock(&dev_priv->rps.hw_lock);
5093}
5094
03af2045 5095static int cherryview_rps_max_freq(struct drm_i915_private *dev_priv)
2b6b3a09 5096{
095acd5f 5097 struct drm_device *dev = dev_priv->dev;
2b6b3a09
D		 5098 u32 val, rp0;
5099
095acd5f
D		 5100 if (dev->pdev->revision >= 0x20) {
5101 val = vlv_punit_read(dev_priv, FB_GFX_FMAX_AT_VMAX_FUSE);
2b6b3a09 5102
095acd5f
D		 5103 switch (INTEL_INFO(dev)->eu_total) {
5104 case 8:
5105 /* (2 * 4) config */
5106 rp0 = (val >> FB_GFX_FMAX_AT_VMAX_2SS4EU_FUSE_SHIFT);
5107 break;
5108 case 12:
5109 /* (2 * 6) config */
5110 rp0 = (val >> FB_GFX_FMAX_AT_VMAX_2SS6EU_FUSE_SHIFT);
5111 break;
5112 case 16:
5113 /* (2 * 8) config */
5114 default:
5115 /* Setting (2 * 8) Min RP0 for any other combination */
5116 rp0 = (val >> FB_GFX_FMAX_AT_VMAX_2SS8EU_FUSE_SHIFT);
5117 break;
5118 }
5119 rp0 = (rp0 & FB_GFX_FREQ_FUSE_MASK);
5120 } else {
5121 /* For pre-production hardware */
5122 val = vlv_punit_read(dev_priv, PUNIT_GPU_STATUS_REG);
5123 rp0 = (val >> PUNIT_GPU_STATUS_MAX_FREQ_SHIFT) &
5124 PUNIT_GPU_STATUS_MAX_FREQ_MASK;
5125 }
2b6b3a09
D		 5126 return rp0;
5127}
5128
5129static int cherryview_rps_rpe_freq(struct drm_i915_private *dev_priv)
5130{
5131 u32 val, rpe;
5132
5133 val = vlv_punit_read(dev_priv, PUNIT_GPU_DUTYCYCLE_REG);
5134 rpe = (val >> PUNIT_GPU_DUTYCYCLE_RPE_FREQ_SHIFT) & PUNIT_GPU_DUTYCYCLE_RPE_FREQ_MASK;
5135
5136 return rpe;
5137}
5138
7707df4a
D		 5139static int cherryview_rps_guar_freq(struct drm_i915_private *dev_priv)
5140{
095acd5f 5141 struct drm_device *dev = dev_priv->dev;
7707df4a
D		 5142 u32 val, rp1;
5143
095acd5f
D		 5144 if (dev->pdev->revision >= 0x20) {
5145 val = vlv_punit_read(dev_priv, FB_GFX_FMAX_AT_VMAX_FUSE);
5146 rp1 = (val & FB_GFX_FREQ_FUSE_MASK);
5147 } else {
5148 /* For pre-production hardware */
5149 val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
5150 rp1 = ((val >> PUNIT_GPU_STATUS_MAX_FREQ_SHIFT) &
5151 PUNIT_GPU_STATUS_MAX_FREQ_MASK);
5152 }
7707df4a
D		 5153 return rp1;
5154}
5155
f8f2b001
D		 5156static int valleyview_rps_guar_freq(struct drm_i915_private *dev_priv)
5157{
5158 u32 val, rp1;
5159
5160 val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FREQ_FUSE);
5161
5162 rp1 = (val & FB_GFX_FGUARANTEED_FREQ_FUSE_MASK) >> FB_GFX_FGUARANTEED_FREQ_FUSE_SHIFT;
5163
5164 return rp1;
5165}
5166
03af2045 5167static int valleyview_rps_max_freq(struct drm_i915_private *dev_priv)
0a073b84
JB		 5168{
5169 u32 val, rp0;
5170
64936258 5171 val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FREQ_FUSE);
0a073b84
JB		 5172
5173 rp0 = (val & FB_GFX_MAX_FREQ_FUSE_MASK) >> FB_GFX_MAX_FREQ_FUSE_SHIFT;
5174 /* Clamp to max */
5175 rp0 = min_t(u32, rp0, 0xea);
5176
5177 return rp0;
5178}
5179
5180static int valleyview_rps_rpe_freq(struct drm_i915_private *dev_priv)
5181{
5182 u32 val, rpe;
5183
64936258 5184 val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FMAX_FUSE_LO);
0a073b84 5185 rpe = (val & FB_FMAX_VMIN_FREQ_LO_MASK) >> FB_FMAX_VMIN_FREQ_LO_SHIFT;
64936258 5186 val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FMAX_FUSE_HI);
0a073b84
JB		 5187 rpe |= (val & FB_FMAX_VMIN_FREQ_HI_MASK) << 5;
5188
5189 return rpe;
5190}
5191
03af2045 5192static int valleyview_rps_min_freq(struct drm_i915_private *dev_priv)
0a073b84 5193{
64936258 5194 return vlv_punit_read(dev_priv, PUNIT_REG_GPU_LFM) & 0xff;
0a073b84
JB		 5195}
5196
ae48434c
ID		 5197/* Check that the pctx buffer wasn't move under us. */
5198static void valleyview_check_pctx(struct drm_i915_private *dev_priv)
5199{
5200 unsigned long pctx_addr = I915_READ(VLV_PCBR) & ~4095;
5201
5202 WARN_ON(pctx_addr != dev_priv->mm.stolen_base +
5203 dev_priv->vlv_pctx->stolen->start);
5204}
5205
38807746
D		 5206
5207/* Check that the pcbr address is not empty. */
5208static void cherryview_check_pctx(struct drm_i915_private *dev_priv)
5209{
5210 unsigned long pctx_addr = I915_READ(VLV_PCBR) & ~4095;
5211
5212 WARN_ON((pctx_addr >> VLV_PCBR_ADDR_SHIFT) == 0);
5213}
5214
5215static void cherryview_setup_pctx(struct drm_device *dev)
5216{
5217 struct drm_i915_private *dev_priv = dev->dev_private;
5218 unsigned long pctx_paddr, paddr;
5219 struct i915_gtt *gtt = &dev_priv->gtt;
5220 u32 pcbr;
5221 int pctx_size = 32*1024;
5222
5223 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
5224
5225 pcbr = I915_READ(VLV_PCBR);
5226 if ((pcbr >> VLV_PCBR_ADDR_SHIFT) == 0) {
ce611ef8 5227 DRM_DEBUG_DRIVER("BIOS didn't set up PCBR, fixing up\n");
38807746
D		 5228 paddr = (dev_priv->mm.stolen_base +
5229 (gtt->stolen_size - pctx_size));
5230
5231 pctx_paddr = (paddr & (~4095));
5232 I915_WRITE(VLV_PCBR, pctx_paddr);
5233 }
ce611ef8
VS		 5234
5235 DRM_DEBUG_DRIVER("PCBR: 0x%08x\n", I915_READ(VLV_PCBR));
38807746
D		 5236}
5237
c9cddffc
JB		 5238static void valleyview_setup_pctx(struct drm_device *dev)
5239{
5240 struct drm_i915_private *dev_priv = dev->dev_private;
5241 struct drm_i915_gem_object *pctx;
5242 unsigned long pctx_paddr;
5243 u32 pcbr;
5244 int pctx_size = 24*1024;
5245
17b0c1f7
ID		 5246 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
5247
c9cddffc
JB		 5248 pcbr = I915_READ(VLV_PCBR);
5249 if (pcbr) {
5250 /* BIOS set it up already, grab the pre-alloc'd space */
5251 int pcbr_offset;
5252
5253 pcbr_offset = (pcbr & (~4095)) - dev_priv->mm.stolen_base;
5254 pctx = i915_gem_object_create_stolen_for_preallocated(dev_priv->dev,
5255 pcbr_offset,
190d6cd5 5256 I915_GTT_OFFSET_NONE,
c9cddffc
JB		 5257 pctx_size);
5258 goto out;
5259 }
5260
ce611ef8
VS		 5261 DRM_DEBUG_DRIVER("BIOS didn't set up PCBR, fixing up\n");
5262
c9cddffc
JB		 5263 /*
5264 * From the Gunit register HAS:
5265 * The Gfx driver is expected to program this register and ensure
5266 * proper allocation within Gfx stolen memory. For example, this
5267 * register should be programmed such than the PCBR range does not
5268 * overlap with other ranges, such as the frame buffer, protected
5269 * memory, or any other relevant ranges.
5270 */
5271 pctx = i915_gem_object_create_stolen(dev, pctx_size);
5272 if (!pctx) {
5273 DRM_DEBUG("not enough stolen space for PCTX, disabling\n");
5274 return;
5275 }
5276
5277 pctx_paddr = dev_priv->mm.stolen_base + pctx->stolen->start;
5278 I915_WRITE(VLV_PCBR, pctx_paddr);
5279
5280out:
ce611ef8 5281 DRM_DEBUG_DRIVER("PCBR: 0x%08x\n", I915_READ(VLV_PCBR));
c9cddffc
JB		 5282 dev_priv->vlv_pctx = pctx;
5283}
5284
ae48434c
ID		 5285static void valleyview_cleanup_pctx(struct drm_device *dev)
5286{
5287 struct drm_i915_private *dev_priv = dev->dev_private;
5288
5289 if (WARN_ON(!dev_priv->vlv_pctx))
5290 return;
5291
5292 drm_gem_object_unreference(&dev_priv->vlv_pctx->base);
5293 dev_priv->vlv_pctx = NULL;
5294}
5295
4e80519e
ID		 5296static void valleyview_init_gt_powersave(struct drm_device *dev)
5297{
5298 struct drm_i915_private *dev_priv = dev->dev_private;
2bb25c17 5299 u32 val;
4e80519e
ID		 5300
5301 valleyview_setup_pctx(dev);
5302
5303 mutex_lock(&dev_priv->rps.hw_lock);
5304
2bb25c17
VS		 5305 val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
5306 switch ((val >> 6) & 3) {
5307 case 0:
5308 case 1:
5309 dev_priv->mem_freq = 800;
5310 break;
5311 case 2:
5312 dev_priv->mem_freq = 1066;
5313 break;
5314 case 3:
5315 dev_priv->mem_freq = 1333;
5316 break;
5317 }
80b83b62 5318 DRM_DEBUG_DRIVER("DDR speed: %d MHz\n", dev_priv->mem_freq);
2bb25c17 5319
4e80519e
ID		 5320 dev_priv->rps.max_freq = valleyview_rps_max_freq(dev_priv);
5321 dev_priv->rps.rp0_freq = dev_priv->rps.max_freq;
5322 DRM_DEBUG_DRIVER("max GPU freq: %d MHz (%u)\n",
7c59a9c1 5323 intel_gpu_freq(dev_priv, dev_priv->rps.max_freq),
4e80519e
ID		 5324 dev_priv->rps.max_freq);
5325
5326 dev_priv->rps.efficient_freq = valleyview_rps_rpe_freq(dev_priv);
5327 DRM_DEBUG_DRIVER("RPe GPU freq: %d MHz (%u)\n",
7c59a9c1 5328 intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
4e80519e
ID		 5329 dev_priv->rps.efficient_freq);
5330
f8f2b001
D		 5331 dev_priv->rps.rp1_freq = valleyview_rps_guar_freq(dev_priv);
5332 DRM_DEBUG_DRIVER("RP1(Guar Freq) GPU freq: %d MHz (%u)\n",
7c59a9c1 5333 intel_gpu_freq(dev_priv, dev_priv->rps.rp1_freq),
f8f2b001
D		 5334 dev_priv->rps.rp1_freq);
5335
4e80519e
ID		 5336 dev_priv->rps.min_freq = valleyview_rps_min_freq(dev_priv);
5337 DRM_DEBUG_DRIVER("min GPU freq: %d MHz (%u)\n",
7c59a9c1 5338 intel_gpu_freq(dev_priv, dev_priv->rps.min_freq),
4e80519e
ID		 5339 dev_priv->rps.min_freq);
5340
aed242ff
CW		 5341 dev_priv->rps.idle_freq = dev_priv->rps.min_freq;
5342
4e80519e
ID		 5343 /* Preserve min/max settings in case of re-init */
5344 if (dev_priv->rps.max_freq_softlimit == 0)
5345 dev_priv->rps.max_freq_softlimit = dev_priv->rps.max_freq;
5346
5347 if (dev_priv->rps.min_freq_softlimit == 0)
5348 dev_priv->rps.min_freq_softlimit = dev_priv->rps.min_freq;
5349
5350 mutex_unlock(&dev_priv->rps.hw_lock);
5351}
5352
38807746
D		 5353static void cherryview_init_gt_powersave(struct drm_device *dev)
5354{
2b6b3a09 5355 struct drm_i915_private *dev_priv = dev->dev_private;
2bb25c17 5356 u32 val;
2b6b3a09 5357
38807746 5358 cherryview_setup_pctx(dev);
2b6b3a09
D		 5359
5360 mutex_lock(&dev_priv->rps.hw_lock);
5361
a580516d 5362 mutex_lock(&dev_priv->sb_lock);
c6e8f39d 5363 val = vlv_cck_read(dev_priv, CCK_FUSE_REG);
a580516d 5364 mutex_unlock(&dev_priv->sb_lock);
c6e8f39d 5365
2bb25c17
VS		 5366 switch ((val >> 2) & 0x7) {
5367 case 0:
5368 case 1:
5369 dev_priv->rps.cz_freq = 200;
5370 dev_priv->mem_freq = 1600;
5371 break;
5372 case 2:
5373 dev_priv->rps.cz_freq = 267;
5374 dev_priv->mem_freq = 1600;
5375 break;
5376 case 3:
5377 dev_priv->rps.cz_freq = 333;
5378 dev_priv->mem_freq = 2000;
5379 break;
5380 case 4:
5381 dev_priv->rps.cz_freq = 320;
5382 dev_priv->mem_freq = 1600;
5383 break;
5384 case 5:
5385 dev_priv->rps.cz_freq = 400;
5386 dev_priv->mem_freq = 1600;
5387 break;
5388 }
80b83b62 5389 DRM_DEBUG_DRIVER("DDR speed: %d MHz\n", dev_priv->mem_freq);
2bb25c17 5390
2b6b3a09
D		 5391 dev_priv->rps.max_freq = cherryview_rps_max_freq(dev_priv);
5392 dev_priv->rps.rp0_freq = dev_priv->rps.max_freq;
5393 DRM_DEBUG_DRIVER("max GPU freq: %d MHz (%u)\n",
7c59a9c1 5394 intel_gpu_freq(dev_priv, dev_priv->rps.max_freq),
2b6b3a09
D		 5395 dev_priv->rps.max_freq);
5396
5397 dev_priv->rps.efficient_freq = cherryview_rps_rpe_freq(dev_priv);
5398 DRM_DEBUG_DRIVER("RPe GPU freq: %d MHz (%u)\n",
7c59a9c1 5399 intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
2b6b3a09
D		 5400 dev_priv->rps.efficient_freq);
5401
7707df4a
D		 5402 dev_priv->rps.rp1_freq = cherryview_rps_guar_freq(dev_priv);
5403 DRM_DEBUG_DRIVER("RP1(Guar) GPU freq: %d MHz (%u)\n",
7c59a9c1 5404 intel_gpu_freq(dev_priv, dev_priv->rps.rp1_freq),
7707df4a
D		 5405 dev_priv->rps.rp1_freq);
5406
5b7c91b7
D		 5407 /* PUnit validated range is only [RPe, RP0] */
5408 dev_priv->rps.min_freq = dev_priv->rps.efficient_freq;
2b6b3a09 5409 DRM_DEBUG_DRIVER("min GPU freq: %d MHz (%u)\n",
7c59a9c1 5410 intel_gpu_freq(dev_priv, dev_priv->rps.min_freq),
2b6b3a09
D		 5411 dev_priv->rps.min_freq);
5412
1c14762d
VS		 5413 WARN_ONCE((dev_priv->rps.max_freq |
5414 dev_priv->rps.efficient_freq |
5415 dev_priv->rps.rp1_freq |
5416 dev_priv->rps.min_freq) & 1,
5417 "Odd GPU freq values\n");
5418
aed242ff
CW		 5419 dev_priv->rps.idle_freq = dev_priv->rps.min_freq;
5420
2b6b3a09
D		 5421 /* Preserve min/max settings in case of re-init */
5422 if (dev_priv->rps.max_freq_softlimit == 0)
5423 dev_priv->rps.max_freq_softlimit = dev_priv->rps.max_freq;
5424
5425 if (dev_priv->rps.min_freq_softlimit == 0)
5426 dev_priv->rps.min_freq_softlimit = dev_priv->rps.min_freq;
5427
5428 mutex_unlock(&dev_priv->rps.hw_lock);
38807746
D		 5429}
5430
4e80519e
ID		 5431static void valleyview_cleanup_gt_powersave(struct drm_device *dev)
5432{
5433 valleyview_cleanup_pctx(dev);
5434}
5435
38807746
D		 5436static void cherryview_enable_rps(struct drm_device *dev)
5437{
5438 struct drm_i915_private *dev_priv = dev->dev_private;
5439 struct intel_engine_cs *ring;
2b6b3a09 5440 u32 gtfifodbg, val, rc6_mode = 0, pcbr;
38807746
D		 5441 int i;
5442
5443 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
5444
5445 gtfifodbg = I915_READ(GTFIFODBG);
5446 if (gtfifodbg) {
5447 DRM_DEBUG_DRIVER("GT fifo had a previous error %x\n",
5448 gtfifodbg);
5449 I915_WRITE(GTFIFODBG, gtfifodbg);
5450 }
5451
5452 cherryview_check_pctx(dev_priv);
5453
5454 /* 1a & 1b: Get forcewake during program sequence. Although the driver
5455 * hasn't enabled a state yet where we need forcewake, BIOS may have.*/
59bad947 5456 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
38807746 5457
160614a2
VS		 5458 /* Disable RC states. */
5459 I915_WRITE(GEN6_RC_CONTROL, 0);
5460
38807746
D		 5461 /* 2a: Program RC6 thresholds.*/
5462 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16);
5463 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */
5464 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */
5465
5466 for_each_ring(ring, dev_priv, i)
5467 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
5468 I915_WRITE(GEN6_RC_SLEEP, 0);
5469
f4f71c7d
D		 5470 /* TO threshold set to 500 us ( 0x186 * 1.28 us) */
5471 I915_WRITE(GEN6_RC6_THRESHOLD, 0x186);
38807746
D		 5472
5473 /* allows RC6 residency counter to work */
5474 I915_WRITE(VLV_COUNTER_CONTROL,
5475 _MASKED_BIT_ENABLE(VLV_COUNT_RANGE_HIGH |
5476 VLV_MEDIA_RC6_COUNT_EN |
5477 VLV_RENDER_RC6_COUNT_EN));
5478
5479 /* For now we assume BIOS is allocating and populating the PCBR */
5480 pcbr = I915_READ(VLV_PCBR);
5481
38807746
D		 5482 /* 3: Enable RC6 */
5483 if ((intel_enable_rc6(dev) & INTEL_RC6_ENABLE) &&
5484 (pcbr >> VLV_PCBR_ADDR_SHIFT))
af5a75a3 5485 rc6_mode = GEN7_RC_CTL_TO_MODE;
38807746
D		 5486
5487 I915_WRITE(GEN6_RC_CONTROL, rc6_mode);
5488
2b6b3a09 5489 /* 4 Program defaults and thresholds for RPS*/
3cbdb48f 5490 I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 1000000);
2b6b3a09
D		 5491 I915_WRITE(GEN6_RP_UP_THRESHOLD, 59400);
5492 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 245000);
5493 I915_WRITE(GEN6_RP_UP_EI, 66000);
5494 I915_WRITE(GEN6_RP_DOWN_EI, 350000);
5495
5496 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
5497
5498 /* 5: Enable RPS */
5499 I915_WRITE(GEN6_RP_CONTROL,
5500 GEN6_RP_MEDIA_HW_NORMAL_MODE |
eb973a5e 5501 GEN6_RP_MEDIA_IS_GFX |
2b6b3a09
D		 5502 GEN6_RP_ENABLE |
5503 GEN6_RP_UP_BUSY_AVG |
5504 GEN6_RP_DOWN_IDLE_AVG);
5505
3ef62342
D		 5506 /* Setting Fixed Bias */
5507 val = VLV_OVERRIDE_EN |
5508 VLV_SOC_TDP_EN |
5509 CHV_BIAS_CPU_50_SOC_50;
5510 vlv_punit_write(dev_priv, VLV_TURBO_SOC_OVERRIDE, val);
5511
2b6b3a09
D		 5512 val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
5513
8d40c3ae
VS		 5514 /* RPS code assumes GPLL is used */
5515 WARN_ONCE((val & GPLLENABLE) == 0, "GPLL not enabled\n");
5516
c8e9627d 5517 DRM_DEBUG_DRIVER("GPLL enabled? %s\n", val & GPLLENABLE ? "yes" : "no");
2b6b3a09
D		 5518 DRM_DEBUG_DRIVER("GPU status: 0x%08x\n", val);
5519
5520 dev_priv->rps.cur_freq = (val >> 8) & 0xff;
5521 DRM_DEBUG_DRIVER("current GPU freq: %d MHz (%u)\n",
7c59a9c1 5522 intel_gpu_freq(dev_priv, dev_priv->rps.cur_freq),
2b6b3a09
D		 5523 dev_priv->rps.cur_freq);
5524
5525 DRM_DEBUG_DRIVER("setting GPU freq to %d MHz (%u)\n",
7c59a9c1 5526 intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
2b6b3a09
D		 5527 dev_priv->rps.efficient_freq);
5528
5529 valleyview_set_rps(dev_priv->dev, dev_priv->rps.efficient_freq);
5530
59bad947 5531 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
38807746
D		 5532}
5533
0a073b84
JB		 5534static void valleyview_enable_rps(struct drm_device *dev)
5535{
5536 struct drm_i915_private *dev_priv = dev->dev_private;
a4872ba6 5537 struct intel_engine_cs *ring;
2a5913a8 5538 u32 gtfifodbg, val, rc6_mode = 0;
0a073b84
JB		 5539 int i;
5540
5541 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
5542
ae48434c
ID		 5543 valleyview_check_pctx(dev_priv);
5544
0a073b84 5545 if ((gtfifodbg = I915_READ(GTFIFODBG))) {
f7d85c1e
JB		 5546 DRM_DEBUG_DRIVER("GT fifo had a previous error %x\n",
5547 gtfifodbg);
0a073b84
JB		 5548 I915_WRITE(GTFIFODBG, gtfifodbg);
5549 }
5550
c8d9a590 5551 /* If VLV, Forcewake all wells, else re-direct to regular path */
59bad947 5552 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
0a073b84 5553
160614a2
VS		 5554 /* Disable RC states. */
5555 I915_WRITE(GEN6_RC_CONTROL, 0);
5556
cad725fe 5557 I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 1000000);
0a073b84
JB		 5558 I915_WRITE(GEN6_RP_UP_THRESHOLD, 59400);
5559 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 245000);
5560 I915_WRITE(GEN6_RP_UP_EI, 66000);
5561 I915_WRITE(GEN6_RP_DOWN_EI, 350000);
5562
5563 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
5564
5565 I915_WRITE(GEN6_RP_CONTROL,
5566 GEN6_RP_MEDIA_TURBO |
5567 GEN6_RP_MEDIA_HW_NORMAL_MODE |
5568 GEN6_RP_MEDIA_IS_GFX |
5569 GEN6_RP_ENABLE |
5570 GEN6_RP_UP_BUSY_AVG |
5571 GEN6_RP_DOWN_IDLE_CONT);
5572
5573 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 0x00280000);
5574 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000);
5575 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25);
5576
5577 for_each_ring(ring, dev_priv, i)
5578 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
5579
2f0aa304 5580 I915_WRITE(GEN6_RC6_THRESHOLD, 0x557);
0a073b84
JB		 5581
5582 /* allows RC6 residency counter to work */
49798eb2 5583 I915_WRITE(VLV_COUNTER_CONTROL,
31685c25
D		 5584 _MASKED_BIT_ENABLE(VLV_MEDIA_RC0_COUNT_EN |
5585 VLV_RENDER_RC0_COUNT_EN |
49798eb2
JB		 5586 VLV_MEDIA_RC6_COUNT_EN |
5587 VLV_RENDER_RC6_COUNT_EN));
31685c25 5588
a2b23fe0 5589 if (intel_enable_rc6(dev) & INTEL_RC6_ENABLE)
6b88f295 5590 rc6_mode = GEN7_RC_CTL_TO_MODE | VLV_RC_CTL_CTX_RST_PARALLEL;
dc39fff7
BW		 5591
5592 intel_print_rc6_info(dev, rc6_mode);
5593
a2b23fe0 5594 I915_WRITE(GEN6_RC_CONTROL, rc6_mode);
0a073b84 5595
3ef62342
D		 5596 /* Setting Fixed Bias */
5597 val = VLV_OVERRIDE_EN |
5598 VLV_SOC_TDP_EN |
5599 VLV_BIAS_CPU_125_SOC_875;
5600 vlv_punit_write(dev_priv, VLV_TURBO_SOC_OVERRIDE, val);
5601
64936258 5602 val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
0a073b84 5603
8d40c3ae
VS		 5604 /* RPS code assumes GPLL is used */
5605 WARN_ONCE((val & GPLLENABLE) == 0, "GPLL not enabled\n");
5606
c8e9627d 5607 DRM_DEBUG_DRIVER("GPLL enabled? %s\n", val & GPLLENABLE ? "yes" : "no");
0a073b84
JB		 5608 DRM_DEBUG_DRIVER("GPU status: 0x%08x\n", val);
5609
b39fb297 5610 dev_priv->rps.cur_freq = (val >> 8) & 0xff;
73008b98 5611 DRM_DEBUG_DRIVER("current GPU freq: %d MHz (%u)\n",
7c59a9c1 5612 intel_gpu_freq(dev_priv, dev_priv->rps.cur_freq),
b39fb297 5613 dev_priv->rps.cur_freq);
0a073b84 5614
73008b98 5615 DRM_DEBUG_DRIVER("setting GPU freq to %d MHz (%u)\n",
7c59a9c1 5616 intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
b39fb297 5617 dev_priv->rps.efficient_freq);
0a073b84 5618
b39fb297 5619 valleyview_set_rps(dev_priv->dev, dev_priv->rps.efficient_freq);
0a073b84 5620
59bad947 5621 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
0a073b84
JB		 5622}
5623
dde18883
ED		 5624static unsigned long intel_pxfreq(u32 vidfreq)
5625{
5626 unsigned long freq;
5627 int div = (vidfreq & 0x3f0000) >> 16;
5628 int post = (vidfreq & 0x3000) >> 12;
5629 int pre = (vidfreq & 0x7);
5630
5631 if (!pre)
5632 return 0;
5633
5634 freq = ((div * 133333) / ((1<<post) * pre));
5635
5636 return freq;
5637}
5638
eb48eb00
DV		 5639static const struct cparams {
5640 u16 i;
5641 u16 t;
5642 u16 m;
5643 u16 c;
5644} cparams[] = {
5645 { 1, 1333, 301, 28664 },
5646 { 1, 1066, 294, 24460 },
5647 { 1, 800, 294, 25192 },
5648 { 0, 1333, 276, 27605 },
5649 { 0, 1066, 276, 27605 },
5650 { 0, 800, 231, 23784 },
5651};
5652
f531dcb2 5653static unsigned long __i915_chipset_val(struct drm_i915_private *dev_priv)
eb48eb00
DV		 5654{
5655 u64 total_count, diff, ret;
5656 u32 count1, count2, count3, m = 0, c = 0;
5657 unsigned long now = jiffies_to_msecs(jiffies), diff1;
5658 int i;
5659
02d71956
DV		 5660 assert_spin_locked(&mchdev_lock);
5661
20e4d407 5662 diff1 = now - dev_priv->ips.last_time1;
eb48eb00
DV		 5663
5664 /* Prevent division-by-zero if we are asking too fast.
5665 * Also, we don't get interesting results if we are polling
5666 * faster than once in 10ms, so just return the saved value
5667 * in such cases.
5668 */
5669 if (diff1 <= 10)
20e4d407 5670 return dev_priv->ips.chipset_power;
eb48eb00
DV		 5671
5672 count1 = I915_READ(DMIEC);
5673 count2 = I915_READ(DDREC);
5674 count3 = I915_READ(CSIEC);
5675
5676 total_count = count1 + count2 + count3;
5677
5678 /* FIXME: handle per-counter overflow */
20e4d407
DV		 5679 if (total_count < dev_priv->ips.last_count1) {
5680 diff = ~0UL - dev_priv->ips.last_count1;
eb48eb00
DV		 5681 diff += total_count;
5682 } else {
20e4d407 5683 diff = total_count - dev_priv->ips.last_count1;
eb48eb00
DV		 5684 }
5685
5686 for (i = 0; i < ARRAY_SIZE(cparams); i++) {
20e4d407
DV		 5687 if (cparams[i].i == dev_priv->ips.c_m &&
5688 cparams[i].t == dev_priv->ips.r_t) {
eb48eb00
DV		 5689 m = cparams[i].m;
5690 c = cparams[i].c;
5691 break;
5692 }
5693 }
5694
5695 diff = div_u64(diff, diff1);
5696 ret = ((m * diff) + c);
5697 ret = div_u64(ret, 10);
5698
20e4d407
DV		 5699 dev_priv->ips.last_count1 = total_count;
5700 dev_priv->ips.last_time1 = now;
eb48eb00 5701
20e4d407 5702 dev_priv->ips.chipset_power = ret;
eb48eb00
DV		 5703
5704 return ret;
5705}
5706
f531dcb2
CW		 5707unsigned long i915_chipset_val(struct drm_i915_private *dev_priv)
5708{
3d13ef2e 5709 struct drm_device *dev = dev_priv->dev;
f531dcb2
CW		 5710 unsigned long val;
5711
3d13ef2e 5712 if (INTEL_INFO(dev)->gen != 5)
f531dcb2
CW		 5713 return 0;
5714
5715 spin_lock_irq(&mchdev_lock);
5716
5717 val = __i915_chipset_val(dev_priv);
5718
5719 spin_unlock_irq(&mchdev_lock);
5720
5721 return val;
5722}
5723
eb48eb00
DV		 5724unsigned long i915_mch_val(struct drm_i915_private *dev_priv)
5725{
5726 unsigned long m, x, b;
5727 u32 tsfs;
5728
5729 tsfs = I915_READ(TSFS);
5730
5731 m = ((tsfs & TSFS_SLOPE_MASK) >> TSFS_SLOPE_SHIFT);
5732 x = I915_READ8(TR1);
5733
5734 b = tsfs & TSFS_INTR_MASK;
5735
5736 return ((m * x) / 127) - b;
5737}
5738
d972d6ee
MK		 5739static int _pxvid_to_vd(u8 pxvid)
5740{
5741 if (pxvid == 0)
5742 return 0;
5743
5744 if (pxvid >= 8 && pxvid < 31)
5745 pxvid = 31;
5746
5747 return (pxvid + 2) * 125;
5748}
5749
5750static u32 pvid_to_extvid(struct drm_i915_private *dev_priv, u8 pxvid)
eb48eb00 5751{
3d13ef2e 5752 struct drm_device *dev = dev_priv->dev;
d972d6ee
MK		 5753 const int vd = _pxvid_to_vd(pxvid);
5754 const int vm = vd - 1125;
5755
3d13ef2e 5756 if (INTEL_INFO(dev)->is_mobile)
d972d6ee
MK		 5757 return vm > 0 ? vm : 0;
5758
5759 return vd;
eb48eb00
DV		 5760}
5761
02d71956 5762static void __i915_update_gfx_val(struct drm_i915_private *dev_priv)
eb48eb00 5763{
5ed0bdf2 5764 u64 now, diff, diffms;
eb48eb00
DV		 5765 u32 count;
5766
02d71956 5767 assert_spin_locked(&mchdev_lock);
eb48eb00 5768
5ed0bdf2
TG		 5769 now = ktime_get_raw_ns();
5770 diffms = now - dev_priv->ips.last_time2;
5771 do_div(diffms, NSEC_PER_MSEC);
eb48eb00
DV		 5772
5773 /* Don't divide by 0 */
eb48eb00
DV		 5774 if (!diffms)
5775 return;
5776
5777 count = I915_READ(GFXEC);
5778
20e4d407
DV		 5779 if (count < dev_priv->ips.last_count2) {
5780 diff = ~0UL - dev_priv->ips.last_count2;
eb48eb00
DV		 5781 diff += count;
5782 } else {
20e4d407 5783 diff = count - dev_priv->ips.last_count2;
eb48eb00
DV		 5784 }
5785
20e4d407
DV		 5786 dev_priv->ips.last_count2 = count;
5787 dev_priv->ips.last_time2 = now;
eb48eb00
DV		 5788
5789 /* More magic constants... */
5790 diff = diff * 1181;
5791 diff = div_u64(diff, diffms * 10);
20e4d407 5792 dev_priv->ips.gfx_power = diff;
eb48eb00
DV		 5793}
5794
02d71956
DV		 5795void i915_update_gfx_val(struct drm_i915_private *dev_priv)
5796{
3d13ef2e
DL		 5797 struct drm_device *dev = dev_priv->dev;
5798
5799 if (INTEL_INFO(dev)->gen != 5)
02d71956
DV		 5800 return;
5801
9270388e 5802 spin_lock_irq(&mchdev_lock);
02d71956
DV		 5803
5804 __i915_update_gfx_val(dev_priv);
5805
9270388e 5806 spin_unlock_irq(&mchdev_lock);
02d71956
DV		 5807}
5808
f531dcb2 5809static unsigned long __i915_gfx_val(struct drm_i915_private *dev_priv)
eb48eb00
DV		 5810{
5811 unsigned long t, corr, state1, corr2, state2;
5812 u32 pxvid, ext_v;
5813
02d71956
DV		 5814 assert_spin_locked(&mchdev_lock);
5815
b39fb297 5816 pxvid = I915_READ(PXVFREQ_BASE + (dev_priv->rps.cur_freq * 4));
eb48eb00
DV		 5817 pxvid = (pxvid >> 24) & 0x7f;
5818 ext_v = pvid_to_extvid(dev_priv, pxvid);
5819
5820 state1 = ext_v;
5821
5822 t = i915_mch_val(dev_priv);
5823
5824 /* Revel in the empirically derived constants */
5825
5826 /* Correction factor in 1/100000 units */
5827 if (t > 80)
5828 corr = ((t * 2349) + 135940);
5829 else if (t >= 50)
5830 corr = ((t * 964) + 29317);
5831 else /* < 50 */
5832 corr = ((t * 301) + 1004);
5833
5834 corr = corr * ((150142 * state1) / 10000 - 78642);
5835 corr /= 100000;
20e4d407 5836 corr2 = (corr * dev_priv->ips.corr);
eb48eb00
DV		 5837
5838 state2 = (corr2 * state1) / 10000;
5839 state2 /= 100; /* convert to mW */
5840
02d71956 5841 __i915_update_gfx_val(dev_priv);
eb48eb00 5842
20e4d407 5843 return dev_priv->ips.gfx_power + state2;
eb48eb00
DV		 5844}
5845
f531dcb2
CW		 5846unsigned long i915_gfx_val(struct drm_i915_private *dev_priv)
5847{
3d13ef2e 5848 struct drm_device *dev = dev_priv->dev;
f531dcb2
CW		 5849 unsigned long val;
5850
3d13ef2e 5851 if (INTEL_INFO(dev)->gen != 5)
f531dcb2
CW		 5852 return 0;
5853
5854 spin_lock_irq(&mchdev_lock);
5855
5856 val = __i915_gfx_val(dev_priv);
5857
5858 spin_unlock_irq(&mchdev_lock);
5859
5860 return val;
5861}
5862
eb48eb00
DV		 5863/**
5864 * i915_read_mch_val - return value for IPS use
5865 *
5866 * Calculate and return a value for the IPS driver to use when deciding whether
5867 * we have thermal and power headroom to increase CPU or GPU power budget.
5868 */
5869unsigned long i915_read_mch_val(void)
5870{
5871 struct drm_i915_private *dev_priv;
5872 unsigned long chipset_val, graphics_val, ret = 0;
5873
9270388e 5874 spin_lock_irq(&mchdev_lock);
eb48eb00
DV		 5875 if (!i915_mch_dev)
5876 goto out_unlock;
5877 dev_priv = i915_mch_dev;
5878
f531dcb2
CW		 5879 chipset_val = __i915_chipset_val(dev_priv);
5880 graphics_val = __i915_gfx_val(dev_priv);
eb48eb00
DV		 5881
5882 ret = chipset_val + graphics_val;
5883
5884out_unlock:
9270388e 5885 spin_unlock_irq(&mchdev_lock);
eb48eb00
DV		 5886
5887 return ret;
5888}
5889EXPORT_SYMBOL_GPL(i915_read_mch_val);
5890
5891/**
5892 * i915_gpu_raise - raise GPU frequency limit
5893 *
5894 * Raise the limit; IPS indicates we have thermal headroom.
5895 */
5896bool i915_gpu_raise(void)
5897{
5898 struct drm_i915_private *dev_priv;
5899 bool ret = true;
5900
9270388e 5901 spin_lock_irq(&mchdev_lock);
eb48eb00
DV		 5902 if (!i915_mch_dev) {
5903 ret = false;
5904 goto out_unlock;
5905 }
5906 dev_priv = i915_mch_dev;
5907
20e4d407
DV		 5908 if (dev_priv->ips.max_delay > dev_priv->ips.fmax)
5909 dev_priv->ips.max_delay--;
eb48eb00
DV		 5910
5911out_unlock:
9270388e 5912 spin_unlock_irq(&mchdev_lock);
eb48eb00
DV		 5913
5914 return ret;
5915}
5916EXPORT_SYMBOL_GPL(i915_gpu_raise);
5917
5918/**
5919 * i915_gpu_lower - lower GPU frequency limit
5920 *
5921 * IPS indicates we're close to a thermal limit, so throttle back the GPU
5922 * frequency maximum.
5923 */
5924bool i915_gpu_lower(void)
5925{
5926 struct drm_i915_private *dev_priv;
5927 bool ret = true;
5928
9270388e 5929 spin_lock_irq(&mchdev_lock);
eb48eb00
DV		 5930 if (!i915_mch_dev) {
5931 ret = false;
5932 goto out_unlock;
5933 }
5934 dev_priv = i915_mch_dev;
5935
20e4d407
DV		 5936 if (dev_priv->ips.max_delay < dev_priv->ips.min_delay)
5937 dev_priv->ips.max_delay++;
eb48eb00
DV		 5938
5939out_unlock:
9270388e 5940 spin_unlock_irq(&mchdev_lock);
eb48eb00
DV		 5941
5942 return ret;
5943}
5944EXPORT_SYMBOL_GPL(i915_gpu_lower);
5945
5946/**
5947 * i915_gpu_busy - indicate GPU business to IPS
5948 *
5949 * Tell the IPS driver whether or not the GPU is busy.
5950 */
5951bool i915_gpu_busy(void)
5952{
5953 struct drm_i915_private *dev_priv;
a4872ba6 5954 struct intel_engine_cs *ring;
eb48eb00 5955 bool ret = false;
f047e395 5956 int i;
eb48eb00 5957
9270388e 5958 spin_lock_irq(&mchdev_lock);
eb48eb00
DV		 5959 if (!i915_mch_dev)
5960 goto out_unlock;
5961 dev_priv = i915_mch_dev;
5962
f047e395
CW		 5963 for_each_ring(ring, dev_priv, i)
5964 ret |= !list_empty(&ring->request_list);
eb48eb00
DV		 5965
5966out_unlock:
9270388e 5967 spin_unlock_irq(&mchdev_lock);
eb48eb00
DV		 5968
5969 return ret;
5970}
5971EXPORT_SYMBOL_GPL(i915_gpu_busy);
5972
5973/**
5974 * i915_gpu_turbo_disable - disable graphics turbo
5975 *
5976 * Disable graphics turbo by resetting the max frequency and setting the
5977 * current frequency to the default.
5978 */
5979bool i915_gpu_turbo_disable(void)
5980{
5981 struct drm_i915_private *dev_priv;
5982 bool ret = true;
5983
9270388e 5984 spin_lock_irq(&mchdev_lock);
eb48eb00
DV		 5985 if (!i915_mch_dev) {
5986 ret = false;
5987 goto out_unlock;
5988 }
5989 dev_priv = i915_mch_dev;
5990
20e4d407 5991 dev_priv->ips.max_delay = dev_priv->ips.fstart;
eb48eb00 5992
20e4d407 5993 if (!ironlake_set_drps(dev_priv->dev, dev_priv->ips.fstart))
eb48eb00
DV		 5994 ret = false;
5995
5996out_unlock:
9270388e 5997 spin_unlock_irq(&mchdev_lock);
eb48eb00
DV		 5998
5999 return ret;
6000}
6001EXPORT_SYMBOL_GPL(i915_gpu_turbo_disable);
6002
6003/**
6004 * Tells the intel_ips driver that the i915 driver is now loaded, if
6005 * IPS got loaded first.
6006 *
6007 * This awkward dance is so that neither module has to depend on the
6008 * other in order for IPS to do the appropriate communication of
6009 * GPU turbo limits to i915.
6010 */
6011static void
6012ips_ping_for_i915_load(void)
6013{
6014 void (*link)(void);
6015
6016 link = symbol_get(ips_link_to_i915_driver);
6017 if (link) {
6018 link();
6019 symbol_put(ips_link_to_i915_driver);
6020 }
6021}
6022
6023void intel_gpu_ips_init(struct drm_i915_private *dev_priv)
6024{
02d71956
DV		 6025 /* We only register the i915 ips part with intel-ips once everything is
6026 * set up, to avoid intel-ips sneaking in and reading bogus values. */
9270388e 6027 spin_lock_irq(&mchdev_lock);
eb48eb00 6028 i915_mch_dev = dev_priv;
9270388e 6029 spin_unlock_irq(&mchdev_lock);
eb48eb00
DV		 6030
6031 ips_ping_for_i915_load();
6032}
6033
6034void intel_gpu_ips_teardown(void)
6035{
9270388e 6036 spin_lock_irq(&mchdev_lock);
eb48eb00 6037 i915_mch_dev = NULL;
9270388e 6038 spin_unlock_irq(&mchdev_lock);
eb48eb00 6039}
76c3552f 6040
8090c6b9 6041static void intel_init_emon(struct drm_device *dev)
dde18883
ED		 6042{
6043 struct drm_i915_private *dev_priv = dev->dev_private;
6044 u32 lcfuse;
6045 u8 pxw[16];
6046 int i;
6047
6048 /* Disable to program */
6049 I915_WRITE(ECR, 0);
6050 POSTING_READ(ECR);
6051
6052 /* Program energy weights for various events */
6053 I915_WRITE(SDEW, 0x15040d00);
6054 I915_WRITE(CSIEW0, 0x007f0000);
6055 I915_WRITE(CSIEW1, 0x1e220004);
6056 I915_WRITE(CSIEW2, 0x04000004);
6057
6058 for (i = 0; i < 5; i++)
6059 I915_WRITE(PEW + (i * 4), 0);
6060 for (i = 0; i < 3; i++)
6061 I915_WRITE(DEW + (i * 4), 0);
6062
6063 /* Program P-state weights to account for frequency power adjustment */
6064 for (i = 0; i < 16; i++) {
6065 u32 pxvidfreq = I915_READ(PXVFREQ_BASE + (i * 4));
6066 unsigned long freq = intel_pxfreq(pxvidfreq);
6067 unsigned long vid = (pxvidfreq & PXVFREQ_PX_MASK) >>
6068 PXVFREQ_PX_SHIFT;
6069 unsigned long val;
6070
6071 val = vid * vid;
6072 val *= (freq / 1000);
6073 val *= 255;
6074 val /= (127*127*900);
6075 if (val > 0xff)
6076 DRM_ERROR("bad pxval: %ld\n", val);
6077 pxw[i] = val;
6078 }
6079 /* Render standby states get 0 weight */
6080 pxw[14] = 0;
6081 pxw[15] = 0;
6082
6083 for (i = 0; i < 4; i++) {
6084 u32 val = (pxw[i*4] << 24) | (pxw[(i*4)+1] << 16) |
6085 (pxw[(i*4)+2] << 8) | (pxw[(i*4)+3]);
6086 I915_WRITE(PXW + (i * 4), val);
6087 }
6088
6089 /* Adjust magic regs to magic values (more experimental results) */
6090 I915_WRITE(OGW0, 0);
6091 I915_WRITE(OGW1, 0);
6092 I915_WRITE(EG0, 0x00007f00);
6093 I915_WRITE(EG1, 0x0000000e);
6094 I915_WRITE(EG2, 0x000e0000);
6095 I915_WRITE(EG3, 0x68000300);
6096 I915_WRITE(EG4, 0x42000000);
6097 I915_WRITE(EG5, 0x00140031);
6098 I915_WRITE(EG6, 0);
6099 I915_WRITE(EG7, 0);
6100
6101 for (i = 0; i < 8; i++)
6102 I915_WRITE(PXWL + (i * 4), 0);
6103
6104 /* Enable PMON + select events */
6105 I915_WRITE(ECR, 0x80000019);
6106
6107 lcfuse = I915_READ(LCFUSE02);
6108
20e4d407 6109 dev_priv->ips.corr = (lcfuse & LCFUSE_HIV_MASK);
dde18883
ED		 6110}
6111
ae48434c
ID		 6112void intel_init_gt_powersave(struct drm_device *dev)
6113{
e6069ca8
ID		 6114 i915.enable_rc6 = sanitize_rc6_option(dev, i915.enable_rc6);
6115
38807746
D		 6116 if (IS_CHERRYVIEW(dev))
6117 cherryview_init_gt_powersave(dev);
6118 else if (IS_VALLEYVIEW(dev))
4e80519e 6119 valleyview_init_gt_powersave(dev);
ae48434c
ID		 6120}
6121
6122void intel_cleanup_gt_powersave(struct drm_device *dev)
6123{
38807746
D		 6124 if (IS_CHERRYVIEW(dev))
6125 return;
6126 else if (IS_VALLEYVIEW(dev))
4e80519e 6127 valleyview_cleanup_gt_powersave(dev);
ae48434c
ID		 6128}
6129
dbea3cea
ID		 6130static void gen6_suspend_rps(struct drm_device *dev)
6131{
6132 struct drm_i915_private *dev_priv = dev->dev_private;
6133
6134 flush_delayed_work(&dev_priv->rps.delayed_resume_work);
6135
4c2a8897 6136 gen6_disable_rps_interrupts(dev);
dbea3cea
ID		 6137}
6138
156c7ca0
JB		 6139/**
6140 * intel_suspend_gt_powersave - suspend PM work and helper threads
6141 * @dev: drm device
6142 *
6143 * We don't want to disable RC6 or other features here, we just want
6144 * to make sure any work we've queued has finished and won't bother
6145 * us while we're suspended.
6146 */
6147void intel_suspend_gt_powersave(struct drm_device *dev)
6148{
6149 struct drm_i915_private *dev_priv = dev->dev_private;
6150
d4d70aa5
ID		 6151 if (INTEL_INFO(dev)->gen < 6)
6152 return;
6153
dbea3cea 6154 gen6_suspend_rps(dev);
b47adc17
D		 6155
6156 /* Force GPU to min freq during suspend */
6157 gen6_rps_idle(dev_priv);
156c7ca0
JB		 6158}
6159
8090c6b9
DV		 6160void intel_disable_gt_powersave(struct drm_device *dev)
6161{
1a01ab3b
JB		 6162 struct drm_i915_private *dev_priv = dev->dev_private;
6163
930ebb46 6164 if (IS_IRONLAKE_M(dev)) {
8090c6b9 6165 ironlake_disable_drps(dev);
38807746 6166 } else if (INTEL_INFO(dev)->gen >= 6) {
10d8d366 6167 intel_suspend_gt_powersave(dev);
e494837a 6168
4fc688ce 6169 mutex_lock(&dev_priv->rps.hw_lock);
20e49366
ZW		 6170 if (INTEL_INFO(dev)->gen >= 9)
6171 gen9_disable_rps(dev);
6172 else if (IS_CHERRYVIEW(dev))
38807746
D		 6173 cherryview_disable_rps(dev);
6174 else if (IS_VALLEYVIEW(dev))
d20d4f0c
JB		 6175 valleyview_disable_rps(dev);
6176 else
6177 gen6_disable_rps(dev);
e534770a 6178
c0951f0c 6179 dev_priv->rps.enabled = false;
4fc688ce 6180 mutex_unlock(&dev_priv->rps.hw_lock);
930ebb46 6181 }
8090c6b9
DV		 6182}
6183
1a01ab3b
JB		 6184static void intel_gen6_powersave_work(struct work_struct *work)
6185{
6186 struct drm_i915_private *dev_priv =
6187 container_of(work, struct drm_i915_private,
6188 rps.delayed_resume_work.work);
6189 struct drm_device *dev = dev_priv->dev;
6190
4fc688ce 6191 mutex_lock(&dev_priv->rps.hw_lock);
0a073b84 6192
4c2a8897 6193 gen6_reset_rps_interrupts(dev);
3cc134e3 6194
38807746
D		 6195 if (IS_CHERRYVIEW(dev)) {
6196 cherryview_enable_rps(dev);
6197 } else if (IS_VALLEYVIEW(dev)) {
0a073b84 6198 valleyview_enable_rps(dev);
20e49366 6199 } else if (INTEL_INFO(dev)->gen >= 9) {
b6fef0ef 6200 gen9_enable_rc6(dev);
20e49366 6201 gen9_enable_rps(dev);
b6fef0ef 6202 __gen6_update_ring_freq(dev);
6edee7f3
BW		 6203 } else if (IS_BROADWELL(dev)) {
6204 gen8_enable_rps(dev);
c2bc2fc5 6205 __gen6_update_ring_freq(dev);
0a073b84
JB		 6206 } else {
6207 gen6_enable_rps(dev);
c2bc2fc5 6208 __gen6_update_ring_freq(dev);
0a073b84 6209 }
aed242ff
CW		 6210
6211 WARN_ON(dev_priv->rps.max_freq < dev_priv->rps.min_freq);
6212 WARN_ON(dev_priv->rps.idle_freq > dev_priv->rps.max_freq);
6213
6214 WARN_ON(dev_priv->rps.efficient_freq < dev_priv->rps.min_freq);
6215 WARN_ON(dev_priv->rps.efficient_freq > dev_priv->rps.max_freq);
6216
c0951f0c 6217 dev_priv->rps.enabled = true;
3cc134e3 6218
4c2a8897 6219 gen6_enable_rps_interrupts(dev);
3cc134e3 6220
4fc688ce 6221 mutex_unlock(&dev_priv->rps.hw_lock);
c6df39b5
ID		 6222
6223 intel_runtime_pm_put(dev_priv);
1a01ab3b
JB		 6224}
6225
8090c6b9
DV		 6226void intel_enable_gt_powersave(struct drm_device *dev)
6227{
1a01ab3b
JB		 6228 struct drm_i915_private *dev_priv = dev->dev_private;
6229
f61018b1
YZ		 6230 /* Powersaving is controlled by the host when inside a VM */
6231 if (intel_vgpu_active(dev))
6232 return;
6233
8090c6b9 6234 if (IS_IRONLAKE_M(dev)) {
dc1d0136 6235 mutex_lock(&dev->struct_mutex);
8090c6b9 6236 ironlake_enable_drps(dev);
8090c6b9 6237 intel_init_emon(dev);
dc1d0136 6238 mutex_unlock(&dev->struct_mutex);
38807746 6239 } else if (INTEL_INFO(dev)->gen >= 6) {
1a01ab3b
JB		 6240 /*
6241 * PCU communication is slow and this doesn't need to be
6242 * done at any specific time, so do this out of our fast path
6243 * to make resume and init faster.
c6df39b5
ID		 6244 *
6245 * We depend on the HW RC6 power context save/restore
6246 * mechanism when entering D3 through runtime PM suspend. So
6247 * disable RPM until RPS/RC6 is properly setup. We can only
6248 * get here via the driver load/system resume/runtime resume
6249 * paths, so the _noresume version is enough (and in case of
6250 * runtime resume it's necessary).
1a01ab3b 6251 */
c6df39b5
ID		 6252 if (schedule_delayed_work(&dev_priv->rps.delayed_resume_work,
6253 round_jiffies_up_relative(HZ)))
6254 intel_runtime_pm_get_noresume(dev_priv);
8090c6b9
DV		 6255 }
6256}
6257
c6df39b5
ID		 6258void intel_reset_gt_powersave(struct drm_device *dev)
6259{
6260 struct drm_i915_private *dev_priv = dev->dev_private;
6261
dbea3cea
ID		 6262 if (INTEL_INFO(dev)->gen < 6)
6263 return;
6264
6265 gen6_suspend_rps(dev);
c6df39b5 6266 dev_priv->rps.enabled = false;
c6df39b5
ID		 6267}
6268
3107bd48
DV		 6269static void ibx_init_clock_gating(struct drm_device *dev)
6270{
6271 struct drm_i915_private *dev_priv = dev->dev_private;
6272
6273 /*
6274 * On Ibex Peak and Cougar Point, we need to disable clock
6275 * gating for the panel power sequencer or it will fail to
6276 * start up when no ports are active.
6277 */
6278 I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);
6279}
6280
0e088b8f
VS		 6281static void g4x_disable_trickle_feed(struct drm_device *dev)
6282{
6283 struct drm_i915_private *dev_priv = dev->dev_private;
b12ce1d8 6284 enum pipe pipe;
0e088b8f 6285
055e393f 6286 for_each_pipe(dev_priv, pipe) {
0e088b8f
VS		 6287 I915_WRITE(DSPCNTR(pipe),
6288 I915_READ(DSPCNTR(pipe)) |
6289 DISPPLANE_TRICKLE_FEED_DISABLE);
b12ce1d8
VS		 6290
6291 I915_WRITE(DSPSURF(pipe), I915_READ(DSPSURF(pipe)));
6292 POSTING_READ(DSPSURF(pipe));
0e088b8f
VS		 6293 }
6294}
6295
017636cc
VS		 6296static void ilk_init_lp_watermarks(struct drm_device *dev)
6297{
6298 struct drm_i915_private *dev_priv = dev->dev_private;
6299
6300 I915_WRITE(WM3_LP_ILK, I915_READ(WM3_LP_ILK) & ~WM1_LP_SR_EN);
6301 I915_WRITE(WM2_LP_ILK, I915_READ(WM2_LP_ILK) & ~WM1_LP_SR_EN);
6302 I915_WRITE(WM1_LP_ILK, I915_READ(WM1_LP_ILK) & ~WM1_LP_SR_EN);
6303
6304 /*
6305 * Don't touch WM1S_LP_EN here.
6306 * Doing so could cause underruns.
6307 */
6308}
6309
1fa61106 6310static void ironlake_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 6311{
6312 struct drm_i915_private *dev_priv = dev->dev_private;
231e54f6 6313 uint32_t dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE;
6f1d69b0 6314
f1e8fa56
DL		 6315 /*
6316 * Required for FBC
6317 * WaFbcDisableDpfcClockGating:ilk
6318 */
4d47e4f5
DL		 6319 dspclk_gate |= ILK_DPFCRUNIT_CLOCK_GATE_DISABLE |
6320 ILK_DPFCUNIT_CLOCK_GATE_DISABLE |
6321 ILK_DPFDUNIT_CLOCK_GATE_ENABLE;
6f1d69b0
ED		 6322
6323 I915_WRITE(PCH_3DCGDIS0,
6324 MARIUNIT_CLOCK_GATE_DISABLE |
6325 SVSMUNIT_CLOCK_GATE_DISABLE);
6326 I915_WRITE(PCH_3DCGDIS1,
6327 VFMUNIT_CLOCK_GATE_DISABLE);
6328
6f1d69b0
ED		 6329 /*
6330 * According to the spec the following bits should be set in
6331 * order to enable memory self-refresh
6332 * The bit 22/21 of 0x42004
6333 * The bit 5 of 0x42020
6334 * The bit 15 of 0x45000
6335 */
6336 I915_WRITE(ILK_DISPLAY_CHICKEN2,
6337 (I915_READ(ILK_DISPLAY_CHICKEN2) |
6338 ILK_DPARB_GATE | ILK_VSDPFD_FULL));
4d47e4f5 6339 dspclk_gate |= ILK_DPARBUNIT_CLOCK_GATE_ENABLE;
6f1d69b0
ED		 6340 I915_WRITE(DISP_ARB_CTL,
6341 (I915_READ(DISP_ARB_CTL) |
6342 DISP_FBC_WM_DIS));
017636cc
VS		 6343
6344 ilk_init_lp_watermarks(dev);
6f1d69b0
ED		 6345
6346 /*
6347 * Based on the document from hardware guys the following bits
6348 * should be set unconditionally in order to enable FBC.
6349 * The bit 22 of 0x42000
6350 * The bit 22 of 0x42004
6351 * The bit 7,8,9 of 0x42020.
6352 */
6353 if (IS_IRONLAKE_M(dev)) {
4bb35334 6354 /* WaFbcAsynchFlipDisableFbcQueue:ilk */
6f1d69b0
ED		 6355 I915_WRITE(ILK_DISPLAY_CHICKEN1,
6356 I915_READ(ILK_DISPLAY_CHICKEN1) |
6357 ILK_FBCQ_DIS);
6358 I915_WRITE(ILK_DISPLAY_CHICKEN2,
6359 I915_READ(ILK_DISPLAY_CHICKEN2) |
6360 ILK_DPARB_GATE);
6f1d69b0
ED		 6361 }
6362
4d47e4f5
DL		 6363 I915_WRITE(ILK_DSPCLK_GATE_D, dspclk_gate);
6364
6f1d69b0
ED		 6365 I915_WRITE(ILK_DISPLAY_CHICKEN2,
6366 I915_READ(ILK_DISPLAY_CHICKEN2) |
6367 ILK_ELPIN_409_SELECT);
6368 I915_WRITE(_3D_CHICKEN2,
6369 _3D_CHICKEN2_WM_READ_PIPELINED << 16 |
6370 _3D_CHICKEN2_WM_READ_PIPELINED);
4358a374 6371
ecdb4eb7 6372 /* WaDisableRenderCachePipelinedFlush:ilk */
4358a374
DV		 6373 I915_WRITE(CACHE_MODE_0,
6374 _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE));
3107bd48 6375
4e04632e
AG		 6376 /* WaDisable_RenderCache_OperationalFlush:ilk */
6377 I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6378
0e088b8f 6379 g4x_disable_trickle_feed(dev);
bdad2b2f 6380
3107bd48
DV		 6381 ibx_init_clock_gating(dev);
6382}
6383
6384static void cpt_init_clock_gating(struct drm_device *dev)
6385{
6386 struct drm_i915_private *dev_priv = dev->dev_private;
6387 int pipe;
3f704fa2 6388 uint32_t val;
3107bd48
DV		 6389
6390 /*
6391 * On Ibex Peak and Cougar Point, we need to disable clock
6392 * gating for the panel power sequencer or it will fail to
6393 * start up when no ports are active.
6394 */
cd664078
JB		 6395 I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE |
6396 PCH_DPLUNIT_CLOCK_GATE_DISABLE |
6397 PCH_CPUNIT_CLOCK_GATE_DISABLE);
3107bd48
DV		 6398 I915_WRITE(SOUTH_CHICKEN2, I915_READ(SOUTH_CHICKEN2) |
6399 DPLS_EDP_PPS_FIX_DIS);
335c07b7
TI		 6400 /* The below fixes the weird display corruption, a few pixels shifted
6401 * downward, on (only) LVDS of some HP laptops with IVY.
6402 */
055e393f 6403 for_each_pipe(dev_priv, pipe) {
dc4bd2d1
PZ		 6404 val = I915_READ(TRANS_CHICKEN2(pipe));
6405 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
6406 val &= ~TRANS_CHICKEN2_FDI_POLARITY_REVERSED;
41aa3448 6407 if (dev_priv->vbt.fdi_rx_polarity_inverted)
3f704fa2 6408 val |= TRANS_CHICKEN2_FDI_POLARITY_REVERSED;
dc4bd2d1
PZ		 6409 val &= ~TRANS_CHICKEN2_FRAME_START_DELAY_MASK;
6410 val &= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_COUNTER;
6411 val &= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_MODESWITCH;
3f704fa2
PZ		 6412 I915_WRITE(TRANS_CHICKEN2(pipe), val);
6413 }
3107bd48 6414 /* WADP0ClockGatingDisable */
055e393f 6415 for_each_pipe(dev_priv, pipe) {
3107bd48
DV		 6416 I915_WRITE(TRANS_CHICKEN1(pipe),
6417 TRANS_CHICKEN1_DP0UNIT_GC_DISABLE);
6418 }
6f1d69b0
ED		 6419}
6420
1d7aaa0c
DV		 6421static void gen6_check_mch_setup(struct drm_device *dev)
6422{
6423 struct drm_i915_private *dev_priv = dev->dev_private;
6424 uint32_t tmp;
6425
6426 tmp = I915_READ(MCH_SSKPD);
df662a28
DV		 6427 if ((tmp & MCH_SSKPD_WM0_MASK) != MCH_SSKPD_WM0_VAL)
6428 DRM_DEBUG_KMS("Wrong MCH_SSKPD value: 0x%08x This can cause underruns.\n",
6429 tmp);
1d7aaa0c
DV		 6430}
6431
1fa61106 6432static void gen6_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 6433{
6434 struct drm_i915_private *dev_priv = dev->dev_private;
231e54f6 6435 uint32_t dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE;
6f1d69b0 6436
231e54f6 6437 I915_WRITE(ILK_DSPCLK_GATE_D, dspclk_gate);
6f1d69b0
ED		 6438
6439 I915_WRITE(ILK_DISPLAY_CHICKEN2,
6440 I915_READ(ILK_DISPLAY_CHICKEN2) |
6441 ILK_ELPIN_409_SELECT);
6442
ecdb4eb7 6443 /* WaDisableHiZPlanesWhenMSAAEnabled:snb */
4283908e
DV		 6444 I915_WRITE(_3D_CHICKEN,
6445 _MASKED_BIT_ENABLE(_3D_CHICKEN_HIZ_PLANE_DISABLE_MSAA_4X_SNB));
6446
4e04632e
AG		 6447 /* WaDisable_RenderCache_OperationalFlush:snb */
6448 I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6449
8d85d272
VS		 6450 /*
6451 * BSpec recoomends 8x4 when MSAA is used,
6452 * however in practice 16x4 seems fastest.
c5c98a58
VS		 6453 *
6454 * Note that PS/WM thread counts depend on the WIZ hashing
6455 * disable bit, which we don't touch here, but it's good
6456 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
8d85d272
VS		 6457 */
6458 I915_WRITE(GEN6_GT_MODE,
98533251 6459 _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4));
8d85d272 6460
017636cc 6461 ilk_init_lp_watermarks(dev);
6f1d69b0 6462
6f1d69b0 6463 I915_WRITE(CACHE_MODE_0,
50743298 6464 _MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB));
6f1d69b0
ED		 6465
6466 I915_WRITE(GEN6_UCGCTL1,
6467 I915_READ(GEN6_UCGCTL1) |
6468 GEN6_BLBUNIT_CLOCK_GATE_DISABLE |
6469 GEN6_CSUNIT_CLOCK_GATE_DISABLE);
6470
6471 /* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock
6472 * gating disable must be set. Failure to set it results in
6473 * flickering pixels due to Z write ordering failures after
6474 * some amount of runtime in the Mesa "fire" demo, and Unigine
6475 * Sanctuary and Tropics, and apparently anything else with
6476 * alpha test or pixel discard.
6477 *
6478 * According to the spec, bit 11 (RCCUNIT) must also be set,
6479 * but we didn't debug actual testcases to find it out.
0f846f81 6480 *
ef59318c
VS		 6481 * WaDisableRCCUnitClockGating:snb
6482 * WaDisableRCPBUnitClockGating:snb
6f1d69b0
ED		 6483 */
6484 I915_WRITE(GEN6_UCGCTL2,
6485 GEN6_RCPBUNIT_CLOCK_GATE_DISABLE |
6486 GEN6_RCCUNIT_CLOCK_GATE_DISABLE);
6487
5eb146dd 6488 /* WaStripsFansDisableFastClipPerformanceFix:snb */
743b57d8
VS		 6489 I915_WRITE(_3D_CHICKEN3,
6490 _MASKED_BIT_ENABLE(_3D_CHICKEN3_SF_DISABLE_FASTCLIP_CULL));
6f1d69b0 6491
e927ecde
VS		 6492 /*
6493 * Bspec says:
6494 * "This bit must be set if 3DSTATE_CLIP clip mode is set to normal and
6495 * 3DSTATE_SF number of SF output attributes is more than 16."
6496 */
6497 I915_WRITE(_3D_CHICKEN3,
6498 _MASKED_BIT_ENABLE(_3D_CHICKEN3_SF_DISABLE_PIPELINED_ATTR_FETCH));
6499
6f1d69b0
ED		 6500 /*
6501 * According to the spec the following bits should be
6502 * set in order to enable memory self-refresh and fbc:
6503 * The bit21 and bit22 of 0x42000
6504 * The bit21 and bit22 of 0x42004
6505 * The bit5 and bit7 of 0x42020
6506 * The bit14 of 0x70180
6507 * The bit14 of 0x71180
4bb35334
DL		 6508 *
6509 * WaFbcAsynchFlipDisableFbcQueue:snb
6f1d69b0
ED		 6510 */
6511 I915_WRITE(ILK_DISPLAY_CHICKEN1,
6512 I915_READ(ILK_DISPLAY_CHICKEN1) |
6513 ILK_FBCQ_DIS | ILK_PABSTRETCH_DIS);
6514 I915_WRITE(ILK_DISPLAY_CHICKEN2,
6515 I915_READ(ILK_DISPLAY_CHICKEN2) |
6516 ILK_DPARB_GATE | ILK_VSDPFD_FULL);
231e54f6
DL		 6517 I915_WRITE(ILK_DSPCLK_GATE_D,
6518 I915_READ(ILK_DSPCLK_GATE_D) |
6519 ILK_DPARBUNIT_CLOCK_GATE_ENABLE |
6520 ILK_DPFDUNIT_CLOCK_GATE_ENABLE);
6f1d69b0 6521
0e088b8f 6522 g4x_disable_trickle_feed(dev);
f8f2ac9a 6523
3107bd48 6524 cpt_init_clock_gating(dev);
1d7aaa0c
DV		 6525
6526 gen6_check_mch_setup(dev);
6f1d69b0
ED		 6527}
6528
6529static void gen7_setup_fixed_func_scheduler(struct drm_i915_private *dev_priv)
6530{
6531 uint32_t reg = I915_READ(GEN7_FF_THREAD_MODE);
6532
3aad9059 6533 /*
46680e0a 6534 * WaVSThreadDispatchOverride:ivb,vlv
3aad9059
VS		 6535 *
6536 * This actually overrides the dispatch
6537 * mode for all thread types.
6538 */
6f1d69b0
ED		 6539 reg &= ~GEN7_FF_SCHED_MASK;
6540 reg |= GEN7_FF_TS_SCHED_HW;
6541 reg |= GEN7_FF_VS_SCHED_HW;
6542 reg |= GEN7_FF_DS_SCHED_HW;
6543
6544 I915_WRITE(GEN7_FF_THREAD_MODE, reg);
6545}
6546
17a303ec
PZ		 6547static void lpt_init_clock_gating(struct drm_device *dev)
6548{
6549 struct drm_i915_private *dev_priv = dev->dev_private;
6550
6551 /*
6552 * TODO: this bit should only be enabled when really needed, then
6553 * disabled when not needed anymore in order to save power.
6554 */
6555 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE)
6556 I915_WRITE(SOUTH_DSPCLK_GATE_D,
6557 I915_READ(SOUTH_DSPCLK_GATE_D) |
6558 PCH_LP_PARTITION_LEVEL_DISABLE);
0a790cdb
PZ		 6559
6560 /* WADPOClockGatingDisable:hsw */
6561 I915_WRITE(_TRANSA_CHICKEN1,
6562 I915_READ(_TRANSA_CHICKEN1) |
6563 TRANS_CHICKEN1_DP0UNIT_GC_DISABLE);
17a303ec
PZ		 6564}
6565
7d708ee4
ID		 6566static void lpt_suspend_hw(struct drm_device *dev)
6567{
6568 struct drm_i915_private *dev_priv = dev->dev_private;
6569
6570 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
6571 uint32_t val = I915_READ(SOUTH_DSPCLK_GATE_D);
6572
6573 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
6574 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
6575 }
6576}
6577
47c2bd97 6578static void broadwell_init_clock_gating(struct drm_device *dev)
1020a5c2
BW		 6579{
6580 struct drm_i915_private *dev_priv = dev->dev_private;
07d27e20 6581 enum pipe pipe;
4d487cff 6582 uint32_t misccpctl;
1020a5c2 6583
7ad0dbab 6584 ilk_init_lp_watermarks(dev);
50ed5fbd 6585
ab57fff1 6586 /* WaSwitchSolVfFArbitrationPriority:bdw */
50ed5fbd 6587 I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | HSW_ECOCHK_ARB_PRIO_SOL);
fe4ab3ce 6588
ab57fff1 6589 /* WaPsrDPAMaskVBlankInSRD:bdw */
fe4ab3ce
BW		 6590 I915_WRITE(CHICKEN_PAR1_1,
6591 I915_READ(CHICKEN_PAR1_1) | DPA_MASK_VBLANK_SRD);
6592
ab57fff1 6593 /* WaPsrDPRSUnmaskVBlankInSRD:bdw */
055e393f 6594 for_each_pipe(dev_priv, pipe) {
07d27e20 6595 I915_WRITE(CHICKEN_PIPESL_1(pipe),
c7c65622 6596 I915_READ(CHICKEN_PIPESL_1(pipe)) |
8f670bb1 6597 BDW_DPRS_MASK_VBLANK_SRD);
fe4ab3ce 6598 }
63801f21 6599
ab57fff1
BW		 6600 /* WaVSRefCountFullforceMissDisable:bdw */
6601 /* WaDSRefCountFullforceMissDisable:bdw */
6602 I915_WRITE(GEN7_FF_THREAD_MODE,
6603 I915_READ(GEN7_FF_THREAD_MODE) &
6604 ~(GEN8_FF_DS_REF_CNT_FFME | GEN7_FF_VS_REF_CNT_FFME));
36075a4c 6605
295e8bb7
VS		 6606 I915_WRITE(GEN6_RC_SLEEP_PSMI_CONTROL,
6607 _MASKED_BIT_ENABLE(GEN8_RC_SEMA_IDLE_MSG_DISABLE));
4f1ca9e9
VS		 6608
6609 /* WaDisableSDEUnitClockGating:bdw */
6610 I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
6611 GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
5d708680 6612
4d487cff
VS		 6613 /*
6614 * WaProgramL3SqcReg1Default:bdw
6615 * WaTempDisableDOPClkGating:bdw
6616 */
6617 misccpctl = I915_READ(GEN7_MISCCPCTL);
6618 I915_WRITE(GEN7_MISCCPCTL, misccpctl & ~GEN7_DOP_CLOCK_GATE_ENABLE);
6619 I915_WRITE(GEN8_L3SQCREG1, BDW_WA_L3SQCREG1_DEFAULT);
6620 I915_WRITE(GEN7_MISCCPCTL, misccpctl);
6621
6d50b065
VS		 6622 /*
6623 * WaGttCachingOffByDefault:bdw
6624 * GTT cache may not work with big pages, so if those
6625 * are ever enabled GTT cache may need to be disabled.
6626 */
6627 I915_WRITE(HSW_GTT_CACHE_EN, GTT_CACHE_EN_ALL);
6628
89d6b2b8 6629 lpt_init_clock_gating(dev);
1020a5c2
BW		 6630}
6631
cad2a2d7
ED		 6632static void haswell_init_clock_gating(struct drm_device *dev)
6633{
6634 struct drm_i915_private *dev_priv = dev->dev_private;
cad2a2d7 6635
017636cc 6636 ilk_init_lp_watermarks(dev);
cad2a2d7 6637
f3fc4884
FJ		 6638 /* L3 caching of data atomics doesn't work -- disable it. */
6639 I915_WRITE(HSW_SCRATCH1, HSW_SCRATCH1_L3_DATA_ATOMICS_DISABLE);
6640 I915_WRITE(HSW_ROW_CHICKEN3,
6641 _MASKED_BIT_ENABLE(HSW_ROW_CHICKEN3_L3_GLOBAL_ATOMICS_DISABLE));
6642
ecdb4eb7 6643 /* This is required by WaCatErrorRejectionIssue:hsw */
cad2a2d7
ED		 6644 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
6645 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
6646 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
6647
e36ea7ff
VS		 6648 /* WaVSRefCountFullforceMissDisable:hsw */
6649 I915_WRITE(GEN7_FF_THREAD_MODE,
6650 I915_READ(GEN7_FF_THREAD_MODE) & ~GEN7_FF_VS_REF_CNT_FFME);
cad2a2d7 6651
4e04632e
AG		 6652 /* WaDisable_RenderCache_OperationalFlush:hsw */
6653 I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6654
fe27c606
CW		 6655 /* enable HiZ Raw Stall Optimization */
6656 I915_WRITE(CACHE_MODE_0_GEN7,
6657 _MASKED_BIT_DISABLE(HIZ_RAW_STALL_OPT_DISABLE));
6658
ecdb4eb7 6659 /* WaDisable4x2SubspanOptimization:hsw */
cad2a2d7
ED		 6660 I915_WRITE(CACHE_MODE_1,
6661 _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
1544d9d5 6662
a12c4967
VS		 6663 /*
6664 * BSpec recommends 8x4 when MSAA is used,
6665 * however in practice 16x4 seems fastest.
c5c98a58
VS		 6666 *
6667 * Note that PS/WM thread counts depend on the WIZ hashing
6668 * disable bit, which we don't touch here, but it's good
6669 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
a12c4967
VS		 6670 */
6671 I915_WRITE(GEN7_GT_MODE,
98533251 6672 _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4));
a12c4967 6673
94411593
KG		 6674 /* WaSampleCChickenBitEnable:hsw */
6675 I915_WRITE(HALF_SLICE_CHICKEN3,
6676 _MASKED_BIT_ENABLE(HSW_SAMPLE_C_PERFORMANCE));
6677
ecdb4eb7 6678 /* WaSwitchSolVfFArbitrationPriority:hsw */
e3dff585
BW		 6679 I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | HSW_ECOCHK_ARB_PRIO_SOL);
6680
90a88643
PZ		 6681 /* WaRsPkgCStateDisplayPMReq:hsw */
6682 I915_WRITE(CHICKEN_PAR1_1,
6683 I915_READ(CHICKEN_PAR1_1) | FORCE_ARB_IDLE_PLANES);
1544d9d5 6684
17a303ec 6685 lpt_init_clock_gating(dev);
cad2a2d7
ED		 6686}
6687
1fa61106 6688static void ivybridge_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 6689{
6690 struct drm_i915_private *dev_priv = dev->dev_private;
20848223 6691 uint32_t snpcr;
6f1d69b0 6692
017636cc 6693 ilk_init_lp_watermarks(dev);
6f1d69b0 6694
231e54f6 6695 I915_WRITE(ILK_DSPCLK_GATE_D, ILK_VRHUNIT_CLOCK_GATE_DISABLE);
6f1d69b0 6696
ecdb4eb7 6697 /* WaDisableEarlyCull:ivb */
87f8020e
JB		 6698 I915_WRITE(_3D_CHICKEN3,
6699 _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL));
6700
ecdb4eb7 6701 /* WaDisableBackToBackFlipFix:ivb */
6f1d69b0
ED		 6702 I915_WRITE(IVB_CHICKEN3,
6703 CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
6704 CHICKEN3_DGMG_DONE_FIX_DISABLE);
6705
ecdb4eb7 6706 /* WaDisablePSDDualDispatchEnable:ivb */
12f3382b
JB		 6707 if (IS_IVB_GT1(dev))
6708 I915_WRITE(GEN7_HALF_SLICE_CHICKEN1,
6709 _MASKED_BIT_ENABLE(GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
12f3382b 6710
4e04632e
AG		 6711 /* WaDisable_RenderCache_OperationalFlush:ivb */
6712 I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6713
ecdb4eb7 6714 /* Apply the WaDisableRHWOOptimizationForRenderHang:ivb workaround. */
6f1d69b0
ED		 6715 I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1,
6716 GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC);
6717
ecdb4eb7 6718 /* WaApplyL3ControlAndL3ChickenMode:ivb */
6f1d69b0
ED		 6719 I915_WRITE(GEN7_L3CNTLREG1,
6720 GEN7_WA_FOR_GEN7_L3_CONTROL);
6721 I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER,
8ab43976
JB		 6722 GEN7_WA_L3_CHICKEN_MODE);
6723 if (IS_IVB_GT1(dev))
6724 I915_WRITE(GEN7_ROW_CHICKEN2,
6725 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
412236c2
VS		 6726 else {
6727 /* must write both registers */
6728 I915_WRITE(GEN7_ROW_CHICKEN2,
6729 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
8ab43976
JB		 6730 I915_WRITE(GEN7_ROW_CHICKEN2_GT2,
6731 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
412236c2 6732 }
6f1d69b0 6733
ecdb4eb7 6734 /* WaForceL3Serialization:ivb */
61939d97
JB		 6735 I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) &
6736 ~L3SQ_URB_READ_CAM_MATCH_DISABLE);
6737
1b80a19a 6738 /*
0f846f81 6739 * According to the spec, bit 13 (RCZUNIT) must be set on IVB.
ecdb4eb7 6740 * This implements the WaDisableRCZUnitClockGating:ivb workaround.
0f846f81
JB		 6741 */
6742 I915_WRITE(GEN6_UCGCTL2,
28acf3b2 6743 GEN6_RCZUNIT_CLOCK_GATE_DISABLE);
0f846f81 6744
ecdb4eb7 6745 /* This is required by WaCatErrorRejectionIssue:ivb */
6f1d69b0
ED		 6746 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
6747 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
6748 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
6749
0e088b8f 6750 g4x_disable_trickle_feed(dev);
6f1d69b0
ED		 6751
6752 gen7_setup_fixed_func_scheduler(dev_priv);
97e1930f 6753
22721343
CW		 6754 if (0) { /* causes HiZ corruption on ivb:gt1 */
6755 /* enable HiZ Raw Stall Optimization */
6756 I915_WRITE(CACHE_MODE_0_GEN7,
6757 _MASKED_BIT_DISABLE(HIZ_RAW_STALL_OPT_DISABLE));
6758 }
116f2b6d 6759
ecdb4eb7 6760 /* WaDisable4x2SubspanOptimization:ivb */
97e1930f
DV		 6761 I915_WRITE(CACHE_MODE_1,
6762 _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
20848223 6763
a607c1a4
VS		 6764 /*
6765 * BSpec recommends 8x4 when MSAA is used,
6766 * however in practice 16x4 seems fastest.
c5c98a58
VS		 6767 *
6768 * Note that PS/WM thread counts depend on the WIZ hashing
6769 * disable bit, which we don't touch here, but it's good
6770 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
a607c1a4
VS		 6771 */
6772 I915_WRITE(GEN7_GT_MODE,
98533251 6773 _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4));
a607c1a4 6774
20848223
BW		 6775 snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
6776 snpcr &= ~GEN6_MBC_SNPCR_MASK;
6777 snpcr |= GEN6_MBC_SNPCR_MED;
6778 I915_WRITE(GEN6_MBCUNIT_SNPCR, snpcr);
3107bd48 6779
ab5c608b
BW		 6780 if (!HAS_PCH_NOP(dev))
6781 cpt_init_clock_gating(dev);
1d7aaa0c
DV		 6782
6783 gen6_check_mch_setup(dev);
6f1d69b0
ED		 6784}
6785
c6beb13e
VS		 6786static void vlv_init_display_clock_gating(struct drm_i915_private *dev_priv)
6787{
6788 I915_WRITE(DSPCLK_GATE_D, VRHUNIT_CLOCK_GATE_DISABLE);
6789
6790 /*
6791 * Disable trickle feed and enable pnd deadline calculation
6792 */
6793 I915_WRITE(MI_ARB_VLV, MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE);
6794 I915_WRITE(CBR1_VLV, 0);
6795}
6796
1fa61106 6797static void valleyview_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 6798{
6799 struct drm_i915_private *dev_priv = dev->dev_private;
6f1d69b0 6800
c6beb13e 6801 vlv_init_display_clock_gating(dev_priv);
6f1d69b0 6802
ecdb4eb7 6803 /* WaDisableEarlyCull:vlv */
87f8020e
JB		 6804 I915_WRITE(_3D_CHICKEN3,
6805 _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL));
6806
ecdb4eb7 6807 /* WaDisableBackToBackFlipFix:vlv */
6f1d69b0
ED		 6808 I915_WRITE(IVB_CHICKEN3,
6809 CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
6810 CHICKEN3_DGMG_DONE_FIX_DISABLE);
6811
fad7d36e 6812 /* WaPsdDispatchEnable:vlv */
ecdb4eb7 6813 /* WaDisablePSDDualDispatchEnable:vlv */
12f3382b 6814 I915_WRITE(GEN7_HALF_SLICE_CHICKEN1,
d3bc0303
JB		 6815 _MASKED_BIT_ENABLE(GEN7_MAX_PS_THREAD_DEP |
6816 GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
12f3382b 6817
4e04632e
AG		 6818 /* WaDisable_RenderCache_OperationalFlush:vlv */
6819 I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6820
ecdb4eb7 6821 /* WaForceL3Serialization:vlv */
61939d97
JB		 6822 I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) &
6823 ~L3SQ_URB_READ_CAM_MATCH_DISABLE);
6824
ecdb4eb7 6825 /* WaDisableDopClockGating:vlv */
8ab43976
JB		 6826 I915_WRITE(GEN7_ROW_CHICKEN2,
6827 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
6828
ecdb4eb7 6829 /* This is required by WaCatErrorRejectionIssue:vlv */
6f1d69b0
ED		 6830 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
6831 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
6832 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
6833
46680e0a
VS		 6834 gen7_setup_fixed_func_scheduler(dev_priv);
6835
3c0edaeb 6836 /*
0f846f81 6837 * According to the spec, bit 13 (RCZUNIT) must be set on IVB.
ecdb4eb7 6838 * This implements the WaDisableRCZUnitClockGating:vlv workaround.
0f846f81
JB		 6839 */
6840 I915_WRITE(GEN6_UCGCTL2,
3c0edaeb 6841 GEN6_RCZUNIT_CLOCK_GATE_DISABLE);
0f846f81 6842
c98f5062
AG		 6843 /* WaDisableL3Bank2xClockGate:vlv
6844 * Disabling L3 clock gating- MMIO 940c[25] = 1
6845 * Set bit 25, to disable L3_BANK_2x_CLK_GATING */
6846 I915_WRITE(GEN7_UCGCTL4,
6847 I915_READ(GEN7_UCGCTL4) | GEN7_L3BANK2X_CLOCK_GATE_DISABLE);
e3f33d46 6848
afd58e79
VS		 6849 /*
6850 * BSpec says this must be set, even though
6851 * WaDisable4x2SubspanOptimization isn't listed for VLV.
6852 */
6b26c86d
DV		 6853 I915_WRITE(CACHE_MODE_1,
6854 _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
7983117f 6855
da2518f9
VS		 6856 /*
6857 * BSpec recommends 8x4 when MSAA is used,
6858 * however in practice 16x4 seems fastest.
6859 *
6860 * Note that PS/WM thread counts depend on the WIZ hashing
6861 * disable bit, which we don't touch here, but it's good
6862 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
6863 */
6864 I915_WRITE(GEN7_GT_MODE,
6865 _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4));
6866
031994ee
VS		 6867 /*
6868 * WaIncreaseL3CreditsForVLVB0:vlv
6869 * This is the hardware default actually.
6870 */
6871 I915_WRITE(GEN7_L3SQCREG1, VLV_B0_WA_L3SQCREG1_VALUE);
6872
2d809570 6873 /*
ecdb4eb7 6874 * WaDisableVLVClockGating_VBIIssue:vlv
2d809570
JB		 6875 * Disable clock gating on th GCFG unit to prevent a delay
6876 * in the reporting of vblank events.
6877 */
7a0d1eed 6878 I915_WRITE(VLV_GUNIT_CLOCK_GATE, GCFG_DIS);
6f1d69b0
ED		 6879}
6880
a4565da8
VS		 6881static void cherryview_init_clock_gating(struct drm_device *dev)
6882{
6883 struct drm_i915_private *dev_priv = dev->dev_private;
6884
c6beb13e 6885 vlv_init_display_clock_gating(dev_priv);
dd811e70 6886
232ce337
VS		 6887 /* WaVSRefCountFullforceMissDisable:chv */
6888 /* WaDSRefCountFullforceMissDisable:chv */
6889 I915_WRITE(GEN7_FF_THREAD_MODE,
6890 I915_READ(GEN7_FF_THREAD_MODE) &
6891 ~(GEN8_FF_DS_REF_CNT_FFME | GEN7_FF_VS_REF_CNT_FFME));
acea6f95
VS		 6892
6893 /* WaDisableSemaphoreAndSyncFlipWait:chv */
6894 I915_WRITE(GEN6_RC_SLEEP_PSMI_CONTROL,
6895 _MASKED_BIT_ENABLE(GEN8_RC_SEMA_IDLE_MSG_DISABLE));
0846697c
VS		 6896
6897 /* WaDisableCSUnitClockGating:chv */
6898 I915_WRITE(GEN6_UCGCTL1, I915_READ(GEN6_UCGCTL1) |
6899 GEN6_CSUNIT_CLOCK_GATE_DISABLE);
c631780f
VS		 6900
6901 /* WaDisableSDEUnitClockGating:chv */
6902 I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
6903 GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
6d50b065
VS		 6904
6905 /*
6906 * GTT cache may not work with big pages, so if those
6907 * are ever enabled GTT cache may need to be disabled.
6908 */
6909 I915_WRITE(HSW_GTT_CACHE_EN, GTT_CACHE_EN_ALL);
a4565da8
VS		 6910}
6911
1fa61106 6912static void g4x_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 6913{
6914 struct drm_i915_private *dev_priv = dev->dev_private;
6915 uint32_t dspclk_gate;
6916
6917 I915_WRITE(RENCLK_GATE_D1, 0);
6918 I915_WRITE(RENCLK_GATE_D2, VF_UNIT_CLOCK_GATE_DISABLE |
6919 GS_UNIT_CLOCK_GATE_DISABLE |
6920 CL_UNIT_CLOCK_GATE_DISABLE);
6921 I915_WRITE(RAMCLK_GATE_D, 0);
6922 dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE |
6923 OVRUNIT_CLOCK_GATE_DISABLE |
6924 OVCUNIT_CLOCK_GATE_DISABLE;
6925 if (IS_GM45(dev))
6926 dspclk_gate |= DSSUNIT_CLOCK_GATE_DISABLE;
6927 I915_WRITE(DSPCLK_GATE_D, dspclk_gate);
4358a374
DV		 6928
6929 /* WaDisableRenderCachePipelinedFlush */
6930 I915_WRITE(CACHE_MODE_0,
6931 _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE));
de1aa629 6932
4e04632e
AG		 6933 /* WaDisable_RenderCache_OperationalFlush:g4x */
6934 I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6935
0e088b8f 6936 g4x_disable_trickle_feed(dev);
6f1d69b0
ED		 6937}
6938
1fa61106 6939static void crestline_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 6940{
6941 struct drm_i915_private *dev_priv = dev->dev_private;
6942
6943 I915_WRITE(RENCLK_GATE_D1, I965_RCC_CLOCK_GATE_DISABLE);
6944 I915_WRITE(RENCLK_GATE_D2, 0);
6945 I915_WRITE(DSPCLK_GATE_D, 0);
6946 I915_WRITE(RAMCLK_GATE_D, 0);
6947 I915_WRITE16(DEUC, 0);
20f94967
VS		 6948 I915_WRITE(MI_ARB_STATE,
6949 _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));
4e04632e
AG		 6950
6951 /* WaDisable_RenderCache_OperationalFlush:gen4 */
6952 I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6f1d69b0
ED		 6953}
6954
1fa61106 6955static void broadwater_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 6956{
6957 struct drm_i915_private *dev_priv = dev->dev_private;
6958
6959 I915_WRITE(RENCLK_GATE_D1, I965_RCZ_CLOCK_GATE_DISABLE |
6960 I965_RCC_CLOCK_GATE_DISABLE |
6961 I965_RCPB_CLOCK_GATE_DISABLE |
6962 I965_ISC_CLOCK_GATE_DISABLE |
6963 I965_FBC_CLOCK_GATE_DISABLE);
6964 I915_WRITE(RENCLK_GATE_D2, 0);
20f94967
VS		 6965 I915_WRITE(MI_ARB_STATE,
6966 _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));
4e04632e
AG		 6967
6968 /* WaDisable_RenderCache_OperationalFlush:gen4 */
6969 I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6f1d69b0
ED		 6970}
6971
1fa61106 6972static void gen3_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 6973{
6974 struct drm_i915_private *dev_priv = dev->dev_private;
6975 u32 dstate = I915_READ(D_STATE);
6976
6977 dstate |= DSTATE_PLL_D3_OFF | DSTATE_GFX_CLOCK_GATING |
6978 DSTATE_DOT_CLOCK_GATING;
6979 I915_WRITE(D_STATE, dstate);
13a86b85
CW		 6980
6981 if (IS_PINEVIEW(dev))
6982 I915_WRITE(ECOSKPD, _MASKED_BIT_ENABLE(ECO_GATING_CX_ONLY));
974a3b0f
DV		 6983
6984 /* IIR "flip pending" means done if this bit is set */
6985 I915_WRITE(ECOSKPD, _MASKED_BIT_DISABLE(ECO_FLIP_DONE));
12fabbcb
VS		 6986
6987 /* interrupts should cause a wake up from C3 */
3299254f 6988 I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_AGPBUSY_INT_EN));
dbb42748
VS		 6989
6990 /* On GEN3 we really need to make sure the ARB C3 LP bit is set */
6991 I915_WRITE(MI_ARB_STATE, _MASKED_BIT_ENABLE(MI_ARB_C3_LP_WRITE_ENABLE));
1038392b
VS		 6992
6993 I915_WRITE(MI_ARB_STATE,
6994 _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));
6f1d69b0
ED		 6995}
6996
1fa61106 6997static void i85x_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 6998{
6999 struct drm_i915_private *dev_priv = dev->dev_private;
7000
7001 I915_WRITE(RENCLK_GATE_D1, SV_CLOCK_GATE_DISABLE);
54e472ae
VS		 7002
7003 /* interrupts should cause a wake up from C3 */
7004 I915_WRITE(MI_STATE, _MASKED_BIT_ENABLE(MI_AGPBUSY_INT_EN) |
7005 _MASKED_BIT_DISABLE(MI_AGPBUSY_830_MODE));
1038392b
VS		 7006
7007 I915_WRITE(MEM_MODE,
7008 _MASKED_BIT_ENABLE(MEM_DISPLAY_TRICKLE_FEED_DISABLE));
6f1d69b0
ED		 7009}
7010
1fa61106 7011static void i830_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 7012{
7013 struct drm_i915_private *dev_priv = dev->dev_private;
7014
7015 I915_WRITE(DSPCLK_GATE_D, OVRUNIT_CLOCK_GATE_DISABLE);
1038392b
VS		 7016
7017 I915_WRITE(MEM_MODE,
7018 _MASKED_BIT_ENABLE(MEM_DISPLAY_A_TRICKLE_FEED_DISABLE) |
7019 _MASKED_BIT_ENABLE(MEM_DISPLAY_B_TRICKLE_FEED_DISABLE));
6f1d69b0
ED		 7020}
7021
6f1d69b0
ED		 7022void intel_init_clock_gating(struct drm_device *dev)
7023{
7024 struct drm_i915_private *dev_priv = dev->dev_private;
7025
c57e3551
DL		 7026 if (dev_priv->display.init_clock_gating)
7027 dev_priv->display.init_clock_gating(dev);
6f1d69b0
ED		 7028}
7029
7d708ee4
ID		 7030void intel_suspend_hw(struct drm_device *dev)
7031{
7032 if (HAS_PCH_LPT(dev))
7033 lpt_suspend_hw(dev);
7034}
7035
1fa61106
ED		 7036/* Set up chip specific power management-related functions */
7037void intel_init_pm(struct drm_device *dev)
7038{
7039 struct drm_i915_private *dev_priv = dev->dev_private;
7040
7ff0ebcc 7041 intel_fbc_init(dev_priv);
1fa61106 7042
c921aba8
DV		 7043 /* For cxsr */
7044 if (IS_PINEVIEW(dev))
7045 i915_pineview_get_mem_freq(dev);
7046 else if (IS_GEN5(dev))
7047 i915_ironlake_get_mem_freq(dev);
7048
1fa61106 7049 /* For FIFO watermark updates */
f5ed50cb 7050 if (INTEL_INFO(dev)->gen >= 9) {
2af30a5c
PB		 7051 skl_setup_wm_latency(dev);
7052
a82abe43
ID		 7053 if (IS_BROXTON(dev))
7054 dev_priv->display.init_clock_gating =
7055 bxt_init_clock_gating;
7056 else if (IS_SKYLAKE(dev))
7057 dev_priv->display.init_clock_gating =
7058 skl_init_clock_gating;
2d41c0b5
PB		 7059 dev_priv->display.update_wm = skl_update_wm;
7060 dev_priv->display.update_sprite_wm = skl_update_sprite_wm;
c83155a6 7061 } else if (HAS_PCH_SPLIT(dev)) {
fa50ad61 7062 ilk_setup_wm_latency(dev);
53615a5e 7063
bd602544
VS		 7064 if ((IS_GEN5(dev) && dev_priv->wm.pri_latency[1] &&
7065 dev_priv->wm.spr_latency[1] && dev_priv->wm.cur_latency[1]) ||
7066 (!IS_GEN5(dev) && dev_priv->wm.pri_latency[0] &&
7067 dev_priv->wm.spr_latency[0] && dev_priv->wm.cur_latency[0])) {
7068 dev_priv->display.update_wm = ilk_update_wm;
7069 dev_priv->display.update_sprite_wm = ilk_update_sprite_wm;
7070 } else {
7071 DRM_DEBUG_KMS("Failed to read display plane latency. "
7072 "Disable CxSR\n");
7073 }
7074
7075 if (IS_GEN5(dev))
1fa61106 7076 dev_priv->display.init_clock_gating = ironlake_init_clock_gating;
bd602544 7077 else if (IS_GEN6(dev))
1fa61106 7078 dev_priv->display.init_clock_gating = gen6_init_clock_gating;
bd602544 7079 else if (IS_IVYBRIDGE(dev))
1fa61106 7080 dev_priv->display.init_clock_gating = ivybridge_init_clock_gating;
bd602544 7081 else if (IS_HASWELL(dev))
cad2a2d7 7082 dev_priv->display.init_clock_gating = haswell_init_clock_gating;
bd602544 7083 else if (INTEL_INFO(dev)->gen == 8)
47c2bd97 7084 dev_priv->display.init_clock_gating = broadwell_init_clock_gating;
a4565da8 7085 } else if (IS_CHERRYVIEW(dev)) {
262cd2e1
VS		 7086 vlv_setup_wm_latency(dev);
7087
7088 dev_priv->display.update_wm = vlv_update_wm;
a4565da8
VS		 7089 dev_priv->display.init_clock_gating =
7090 cherryview_init_clock_gating;
1fa61106 7091 } else if (IS_VALLEYVIEW(dev)) {
26e1fe4f
VS		 7092 vlv_setup_wm_latency(dev);
7093
7094 dev_priv->display.update_wm = vlv_update_wm;
1fa61106
ED		 7095 dev_priv->display.init_clock_gating =
7096 valleyview_init_clock_gating;
1fa61106
ED		 7097 } else if (IS_PINEVIEW(dev)) {
7098 if (!intel_get_cxsr_latency(IS_PINEVIEW_G(dev),
7099 dev_priv->is_ddr3,
7100 dev_priv->fsb_freq,
7101 dev_priv->mem_freq)) {
7102 DRM_INFO("failed to find known CxSR latency "
7103 "(found ddr%s fsb freq %d, mem freq %d), "
7104 "disabling CxSR\n",
7105 (dev_priv->is_ddr3 == 1) ? "3" : "2",
7106 dev_priv->fsb_freq, dev_priv->mem_freq);
7107 /* Disable CxSR and never update its watermark again */
5209b1f4 7108 intel_set_memory_cxsr(dev_priv, false);
1fa61106
ED		 7109 dev_priv->display.update_wm = NULL;
7110 } else
7111 dev_priv->display.update_wm = pineview_update_wm;
7112 dev_priv->display.init_clock_gating = gen3_init_clock_gating;
7113 } else if (IS_G4X(dev)) {
7114 dev_priv->display.update_wm = g4x_update_wm;
7115 dev_priv->display.init_clock_gating = g4x_init_clock_gating;
7116 } else if (IS_GEN4(dev)) {
7117 dev_priv->display.update_wm = i965_update_wm;
7118 if (IS_CRESTLINE(dev))
7119 dev_priv->display.init_clock_gating = crestline_init_clock_gating;
7120 else if (IS_BROADWATER(dev))
7121 dev_priv->display.init_clock_gating = broadwater_init_clock_gating;
7122 } else if (IS_GEN3(dev)) {
7123 dev_priv->display.update_wm = i9xx_update_wm;
7124 dev_priv->display.get_fifo_size = i9xx_get_fifo_size;
7125 dev_priv->display.init_clock_gating = gen3_init_clock_gating;
feb56b93
DV		 7126 } else if (IS_GEN2(dev)) {
7127 if (INTEL_INFO(dev)->num_pipes == 1) {
7128 dev_priv->display.update_wm = i845_update_wm;
1fa61106 7129 dev_priv->display.get_fifo_size = i845_get_fifo_size;
feb56b93
DV		 7130 } else {
7131 dev_priv->display.update_wm = i9xx_update_wm;
1fa61106 7132 dev_priv->display.get_fifo_size = i830_get_fifo_size;
feb56b93
DV		 7133 }
7134
7135 if (IS_I85X(dev) || IS_I865G(dev))
7136 dev_priv->display.init_clock_gating = i85x_init_clock_gating;
7137 else
7138 dev_priv->display.init_clock_gating = i830_init_clock_gating;
7139 } else {
7140 DRM_ERROR("unexpected fall-through in intel_init_pm\n");
1fa61106
ED		 7141 }
7142}
7143
151a49d0 7144int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u32 mbox, u32 *val)
42c0526c 7145{
4fc688ce 7146 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
42c0526c
BW		 7147
7148 if (I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) {
7149 DRM_DEBUG_DRIVER("warning: pcode (read) mailbox access failed\n");
7150 return -EAGAIN;
7151 }
7152
7153 I915_WRITE(GEN6_PCODE_DATA, *val);
dddab346 7154 I915_WRITE(GEN6_PCODE_DATA1, 0);
42c0526c
BW		 7155 I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY | mbox);
7156
7157 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
7158 500)) {
7159 DRM_ERROR("timeout waiting for pcode read (%d) to finish\n", mbox);
7160 return -ETIMEDOUT;
7161 }
7162
7163 *val = I915_READ(GEN6_PCODE_DATA);
7164 I915_WRITE(GEN6_PCODE_DATA, 0);
7165
7166 return 0;
7167}
7168
151a49d0 7169int sandybridge_pcode_write(struct drm_i915_private *dev_priv, u32 mbox, u32 val)
42c0526c 7170{
4fc688ce 7171 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
42c0526c
BW		 7172
7173 if (I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) {
7174 DRM_DEBUG_DRIVER("warning: pcode (write) mailbox access failed\n");
7175 return -EAGAIN;
7176 }
7177
7178 I915_WRITE(GEN6_PCODE_DATA, val);
7179 I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY | mbox);
7180
7181 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
7182 500)) {
7183 DRM_ERROR("timeout waiting for pcode write (%d) to finish\n", mbox);
7184 return -ETIMEDOUT;
7185 }
7186
7187 I915_WRITE(GEN6_PCODE_DATA, 0);
7188
7189 return 0;
7190}
a0e4e199 7191
dd06f88c 7192static int vlv_gpu_freq_div(unsigned int czclk_freq)
855ba3be 7193{
dd06f88c
VS		 7194 switch (czclk_freq) {
7195 case 200:
7196 return 10;
7197 case 267:
7198 return 12;
7199 case 320:
7200 case 333:
dd06f88c 7201 return 16;
ab3fb157
VS		 7202 case 400:
7203 return 20;
855ba3be
JB		 7204 default:
7205 return -1;
7206 }
dd06f88c 7207}
855ba3be 7208
dd06f88c
VS		 7209static int byt_gpu_freq(struct drm_i915_private *dev_priv, int val)
7210{
7211 int div, czclk_freq = DIV_ROUND_CLOSEST(dev_priv->mem_freq, 4);
7212
7213 div = vlv_gpu_freq_div(czclk_freq);
7214 if (div < 0)
7215 return div;
7216
7217 return DIV_ROUND_CLOSEST(czclk_freq * (val + 6 - 0xbd), div);
855ba3be
JB		 7218}
7219
b55dd647 7220static int byt_freq_opcode(struct drm_i915_private *dev_priv, int val)
855ba3be 7221{
dd06f88c 7222 int mul, czclk_freq = DIV_ROUND_CLOSEST(dev_priv->mem_freq, 4);
855ba3be 7223
dd06f88c
VS		 7224 mul = vlv_gpu_freq_div(czclk_freq);
7225 if (mul < 0)
7226 return mul;
855ba3be 7227
dd06f88c 7228 return DIV_ROUND_CLOSEST(mul * val, czclk_freq) + 0xbd - 6;
855ba3be
JB		 7229}
7230
b55dd647 7231static int chv_gpu_freq(struct drm_i915_private *dev_priv, int val)
22b1b2f8 7232{
dd06f88c 7233 int div, czclk_freq = dev_priv->rps.cz_freq;
22b1b2f8 7234
dd06f88c
VS		 7235 div = vlv_gpu_freq_div(czclk_freq) / 2;
7236 if (div < 0)
7237 return div;
22b1b2f8 7238
dd06f88c 7239 return DIV_ROUND_CLOSEST(czclk_freq * val, 2 * div) / 2;
22b1b2f8
D		 7240}
7241
b55dd647 7242static int chv_freq_opcode(struct drm_i915_private *dev_priv, int val)
22b1b2f8 7243{
dd06f88c 7244 int mul, czclk_freq = dev_priv->rps.cz_freq;
22b1b2f8 7245
dd06f88c
VS		 7246 mul = vlv_gpu_freq_div(czclk_freq) / 2;
7247 if (mul < 0)
7248 return mul;
22b1b2f8 7249
1c14762d 7250 /* CHV needs even values */
dd06f88c 7251 return DIV_ROUND_CLOSEST(val * 2 * mul, czclk_freq) * 2;
22b1b2f8
D		 7252}
7253
616bc820 7254int intel_gpu_freq(struct drm_i915_private *dev_priv, int val)
22b1b2f8 7255{
80b6dda4
AG		 7256 if (IS_GEN9(dev_priv->dev))
7257 return (val * GT_FREQUENCY_MULTIPLIER) / GEN9_FREQ_SCALER;
7258 else if (IS_CHERRYVIEW(dev_priv->dev))
616bc820 7259 return chv_gpu_freq(dev_priv, val);
22b1b2f8 7260 else if (IS_VALLEYVIEW(dev_priv->dev))
616bc820
VS		 7261 return byt_gpu_freq(dev_priv, val);
7262 else
7263 return val * GT_FREQUENCY_MULTIPLIER;
22b1b2f8
D		 7264}
7265
616bc820
VS		 7266int intel_freq_opcode(struct drm_i915_private *dev_priv, int val)
7267{
80b6dda4
AG		 7268 if (IS_GEN9(dev_priv->dev))
7269 return (val * GEN9_FREQ_SCALER) / GT_FREQUENCY_MULTIPLIER;
7270 else if (IS_CHERRYVIEW(dev_priv->dev))
616bc820 7271 return chv_freq_opcode(dev_priv, val);
22b1b2f8 7272 else if (IS_VALLEYVIEW(dev_priv->dev))
616bc820
VS		 7273 return byt_freq_opcode(dev_priv, val);
7274 else
7275 return val / GT_FREQUENCY_MULTIPLIER;
7276}
22b1b2f8 7277
6ad790c0
CW		 7278struct request_boost {
7279 struct work_struct work;
eed29a5b 7280 struct drm_i915_gem_request *req;
6ad790c0
CW		 7281};
7282
7283static void __intel_rps_boost_work(struct work_struct *work)
7284{
7285 struct request_boost *boost = container_of(work, struct request_boost, work);
e61b9958 7286 struct drm_i915_gem_request *req = boost->req;
6ad790c0 7287
e61b9958
CW		 7288 if (!i915_gem_request_completed(req, true))
7289 gen6_rps_boost(to_i915(req->ring->dev), NULL,
7290 req->emitted_jiffies);
6ad790c0 7291
e61b9958 7292 i915_gem_request_unreference__unlocked(req);
6ad790c0
CW		 7293 kfree(boost);
7294}
7295
7296void intel_queue_rps_boost_for_request(struct drm_device *dev,
eed29a5b 7297 struct drm_i915_gem_request *req)
6ad790c0
CW		 7298{
7299 struct request_boost *boost;
7300
eed29a5b 7301 if (req == NULL || INTEL_INFO(dev)->gen < 6)
6ad790c0
CW		 7302 return;
7303
e61b9958
CW		 7304 if (i915_gem_request_completed(req, true))
7305 return;
7306
6ad790c0
CW		 7307 boost = kmalloc(sizeof(*boost), GFP_ATOMIC);
7308 if (boost == NULL)
7309 return;
7310
eed29a5b
DV		 7311 i915_gem_request_reference(req);
7312 boost->req = req;
6ad790c0
CW		 7313
7314 INIT_WORK(&boost->work, __intel_rps_boost_work);
7315 queue_work(to_i915(dev)->wq, &boost->work);
7316}
7317
f742a552 7318void intel_pm_setup(struct drm_device *dev)
907b28c5
CW		 7319{
7320 struct drm_i915_private *dev_priv = dev->dev_private;
7321
f742a552 7322 mutex_init(&dev_priv->rps.hw_lock);
8d3afd7d 7323 spin_lock_init(&dev_priv->rps.client_lock);
f742a552 7324
907b28c5
CW		 7325 INIT_DELAYED_WORK(&dev_priv->rps.delayed_resume_work,
7326 intel_gen6_powersave_work);
1854d5ca 7327 INIT_LIST_HEAD(&dev_priv->rps.clients);
2e1b8730
CW		 7328 INIT_LIST_HEAD(&dev_priv->rps.semaphores.link);
7329 INIT_LIST_HEAD(&dev_priv->rps.mmioflips.link);
5d584b2e 7330
33688d95 7331 dev_priv->pm.suspended = false;
907b28c5 7332}
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