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drm/i915/sdvo: Shut up state checker with hdmi cards on gen3
[mirror_ubuntu-bionic-kernel.git] / drivers / gpu / drm / i915 / intel_sdvo.c
CommitLineData
79e53945
JB		 1/*
2 * Copyright 2006 Dave Airlie <airlied@linux.ie>
3 * Copyright © 2006-2007 Intel Corporation
4 * Jesse Barnes <jesse.barnes@intel.com>
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
15 * Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
22 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
23 * DEALINGS IN THE SOFTWARE.
24 *
25 * Authors:
26 * Eric Anholt <eric@anholt.net>
27 */
28#include <linux/i2c.h>
5a0e3ad6 29#include <linux/slab.h>
79e53945 30#include <linux/delay.h>
2d1a8a48 31#include <linux/export.h>
760285e7 32#include <drm/drmP.h>
c6f95f27 33#include <drm/drm_atomic_helper.h>
760285e7
DH		 34#include <drm/drm_crtc.h>
35#include <drm/drm_edid.h>
ea5b213a 36#include "intel_drv.h"
760285e7 37#include <drm/i915_drm.h>
79e53945
JB		 38#include "i915_drv.h"
39#include "intel_sdvo_regs.h"
40
14571b4c
ZW		 41#define SDVO_TMDS_MASK (SDVO_OUTPUT_TMDS0 | SDVO_OUTPUT_TMDS1)
42#define SDVO_RGB_MASK (SDVO_OUTPUT_RGB0 | SDVO_OUTPUT_RGB1)
43#define SDVO_LVDS_MASK (SDVO_OUTPUT_LVDS0 | SDVO_OUTPUT_LVDS1)
a0b1c7a5 44#define SDVO_TV_MASK (SDVO_OUTPUT_CVBS0 | SDVO_OUTPUT_SVID0 | SDVO_OUTPUT_YPRPB0)
14571b4c
ZW		 45
46#define SDVO_OUTPUT_MASK (SDVO_TMDS_MASK | SDVO_RGB_MASK | SDVO_LVDS_MASK |\
0206e353 47 SDVO_TV_MASK)
14571b4c
ZW		 48
49#define IS_TV(c) (c->output_flag & SDVO_TV_MASK)
13946743 50#define IS_TMDS(c) (c->output_flag & SDVO_TMDS_MASK)
14571b4c 51#define IS_LVDS(c) (c->output_flag & SDVO_LVDS_MASK)
32aad86f 52#define IS_TV_OR_LVDS(c) (c->output_flag & (SDVO_TV_MASK | SDVO_LVDS_MASK))
52220085 53#define IS_DIGITAL(c) (c->output_flag & (SDVO_TMDS_MASK | SDVO_LVDS_MASK))
14571b4c 54
79e53945 55
4d9194de 56static const char * const tv_format_names[] = {
ce6feabd
ZY		 57 "NTSC_M" , "NTSC_J" , "NTSC_443",
58 "PAL_B" , "PAL_D" , "PAL_G" ,
59 "PAL_H" , "PAL_I" , "PAL_M" ,
60 "PAL_N" , "PAL_NC" , "PAL_60" ,
61 "SECAM_B" , "SECAM_D" , "SECAM_G" ,
62 "SECAM_K" , "SECAM_K1", "SECAM_L" ,
63 "SECAM_60"
64};
65
53abb679 66#define TV_FORMAT_NUM ARRAY_SIZE(tv_format_names)
ce6feabd 67
ea5b213a
CW		 68struct intel_sdvo {
69 struct intel_encoder base;
70
f899fc64 71 struct i2c_adapter *i2c;
f9c10a9b 72 u8 slave_addr;
e2f0ba97 73
e957d772
CW		 74 struct i2c_adapter ddc;
75
e2f0ba97 76 /* Register for the SDVO device: SDVOB or SDVOC */
f0f59a00 77 i915_reg_t sdvo_reg;
79e53945 78
e2f0ba97
JB		 79 /* Active outputs controlled by this SDVO output */
80 uint16_t controlled_output;
79e53945 81
e2f0ba97
JB		 82 /*
83 * Capabilities of the SDVO device returned by
19d415a2 84 * intel_sdvo_get_capabilities()
e2f0ba97 85 */
79e53945 86 struct intel_sdvo_caps caps;
e2f0ba97
JB		 87
88 /* Pixel clock limitations reported by the SDVO device, in kHz */
79e53945
JB		 89 int pixel_clock_min, pixel_clock_max;
90
fb7a46f3 91 /*
92 * For multiple function SDVO device,
93 * this is for current attached outputs.
94 */
95 uint16_t attached_output;
96
cc68c81a
SF		 97 /*
98 * Hotplug activation bits for this device
99 */
5fa7ac9c 100 uint16_t hotplug_active;
cc68c81a 101
e2f0ba97
JB		 102 /**
103 * This is set if we're going to treat the device as TV-out.
104 *
105 * While we have these nice friendly flags for output types that ought
106 * to decide this for us, the S-Video output on our HDMI+S-Video card
107 * shows up as RGB1 (VGA).
108 */
109 bool is_tv;
110
2a5c0832 111 enum port port;
eef4eacb 112
e2f0ba97
JB		 113 /**
114 * This is set if we treat the device as HDMI, instead of DVI.
115 */
116 bool is_hdmi;
da79de97
CW		 117 bool has_hdmi_monitor;
118 bool has_hdmi_audio;
abedc077 119 bool rgb_quant_range_selectable;
12682a97 120
7086c87f 121 /**
6c9547ff
CW		 122 * This is set if we detect output of sdvo device as LVDS and
123 * have a valid fixed mode to use with the panel.
7086c87f
ML		 124 */
125 bool is_lvds;
e2f0ba97 126
12682a97 127 /**
128 * This is sdvo fixed pannel mode pointer
129 */
130 struct drm_display_mode *sdvo_lvds_fixed_mode;
131
c751ce4f 132 /* DDC bus used by this SDVO encoder */
e2f0ba97 133 uint8_t ddc_bus;
e751823d
EE		 134
135 /*
136 * the sdvo flag gets lost in round trip: dtd->adjusted_mode->dtd
137 */
138 uint8_t dtd_sdvo_flags;
14571b4c
ZW		 139};
140
141struct intel_sdvo_connector {
615fb93f
CW		 142 struct intel_connector base;
143
14571b4c
ZW		 144 /* Mark the type of connector */
145 uint16_t output_flag;
146
147 /* This contains all current supported TV format */
40039750 148 u8 tv_format_supported[TV_FORMAT_NUM];
14571b4c 149 int format_supported_num;
c5521706 150 struct drm_property *tv_format;
14571b4c 151
b9219c5e 152 /* add the property for the SDVO-TV */
c5521706
CW		 153 struct drm_property *left;
154 struct drm_property *right;
155 struct drm_property *top;
156 struct drm_property *bottom;
157 struct drm_property *hpos;
158 struct drm_property *vpos;
159 struct drm_property *contrast;
160 struct drm_property *saturation;
161 struct drm_property *hue;
162 struct drm_property *sharpness;
163 struct drm_property *flicker_filter;
164 struct drm_property *flicker_filter_adaptive;
165 struct drm_property *flicker_filter_2d;
166 struct drm_property *tv_chroma_filter;
167 struct drm_property *tv_luma_filter;
e044218a 168 struct drm_property *dot_crawl;
b9219c5e
ZY		 169
170 /* add the property for the SDVO-TV/LVDS */
c5521706 171 struct drm_property *brightness;
b9219c5e 172
b9219c5e 173 /* this is to get the range of margin.*/
630d30a4
ML		 174 u32 max_hscan, max_vscan;
175};
176
177struct intel_sdvo_connector_state {
178 /* base.base: tv.saturation/contrast/hue/brightness */
179 struct intel_digital_connector_state base;
180
181 struct {
182 unsigned overscan_h, overscan_v, hpos, vpos, sharpness;
183 unsigned flicker_filter, flicker_filter_2d, flicker_filter_adaptive;
184 unsigned chroma_filter, luma_filter, dot_crawl;
185 } tv;
79e53945
JB		 186};
187
8aca63aa 188static struct intel_sdvo *to_sdvo(struct intel_encoder *encoder)
ea5b213a 189{
8aca63aa 190 return container_of(encoder, struct intel_sdvo, base);
ea5b213a
CW		 191}
192
df0e9248
CW		 193static struct intel_sdvo *intel_attached_sdvo(struct drm_connector *connector)
194{
8aca63aa 195 return to_sdvo(intel_attached_encoder(connector));
df0e9248
CW		 196}
197
630d30a4
ML		 198static struct intel_sdvo_connector *
199to_intel_sdvo_connector(struct drm_connector *connector)
200{
201 return container_of(connector, struct intel_sdvo_connector, base.base);
202}
203
204static struct intel_sdvo_connector_state *
205to_intel_sdvo_connector_state(struct drm_connector_state *conn_state)
615fb93f 206{
630d30a4 207 return container_of(conn_state, struct intel_sdvo_connector_state, base.base);
615fb93f
CW		 208}
209
fb7a46f3 210static bool
ea5b213a 211intel_sdvo_output_setup(struct intel_sdvo *intel_sdvo, uint16_t flags);
32aad86f
CW		 212static bool
213intel_sdvo_tv_create_property(struct intel_sdvo *intel_sdvo,
214 struct intel_sdvo_connector *intel_sdvo_connector,
215 int type);
216static bool
217intel_sdvo_create_enhance_property(struct intel_sdvo *intel_sdvo,
218 struct intel_sdvo_connector *intel_sdvo_connector);
fb7a46f3 219
79e53945
JB		 220/**
221 * Writes the SDVOB or SDVOC with the given value, but always writes both
222 * SDVOB and SDVOC to work around apparent hardware issues (according to
223 * comments in the BIOS).
224 */
ea5b213a 225static void intel_sdvo_write_sdvox(struct intel_sdvo *intel_sdvo, u32 val)
79e53945 226{
4ef69c7a 227 struct drm_device *dev = intel_sdvo->base.base.dev;
fac5e23e 228 struct drm_i915_private *dev_priv = to_i915(dev);
79e53945
JB		 229 u32 bval = val, cval = val;
230 int i;
231
2a5c0832 232 if (HAS_PCH_SPLIT(dev_priv)) {
ea5b213a 233 I915_WRITE(intel_sdvo->sdvo_reg, val);
abab6311 234 POSTING_READ(intel_sdvo->sdvo_reg);
e8504ee2
VS		 235 /*
236 * HW workaround, need to write this twice for issue
237 * that may result in first write getting masked.
238 */
6e266956 239 if (HAS_PCH_IBX(dev_priv)) {
e8504ee2
VS		 240 I915_WRITE(intel_sdvo->sdvo_reg, val);
241 POSTING_READ(intel_sdvo->sdvo_reg);
242 }
461ed3ca
ZY		 243 return;
244 }
245
2a5c0832 246 if (intel_sdvo->port == PORT_B)
e2debe91
PZ		 247 cval = I915_READ(GEN3_SDVOC);
248 else
249 bval = I915_READ(GEN3_SDVOB);
250
79e53945
JB		 251 /*
252 * Write the registers twice for luck. Sometimes,
253 * writing them only once doesn't appear to 'stick'.
254 * The BIOS does this too. Yay, magic
255 */
256 for (i = 0; i < 2; i++)
257 {
e2debe91 258 I915_WRITE(GEN3_SDVOB, bval);
abab6311 259 POSTING_READ(GEN3_SDVOB);
e2debe91 260 I915_WRITE(GEN3_SDVOC, cval);
abab6311 261 POSTING_READ(GEN3_SDVOC);
79e53945
JB		 262 }
263}
264
32aad86f 265static bool intel_sdvo_read_byte(struct intel_sdvo *intel_sdvo, u8 addr, u8 *ch)
79e53945 266{
79e53945
JB		 267 struct i2c_msg msgs[] = {
268 {
e957d772 269 .addr = intel_sdvo->slave_addr,
79e53945
JB		 270 .flags = 0,
271 .len = 1,
e957d772 272 .buf = &addr,
79e53945
JB		 273 },
274 {
e957d772 275 .addr = intel_sdvo->slave_addr,
79e53945
JB		 276 .flags = I2C_M_RD,
277 .len = 1,
e957d772 278 .buf = ch,
79e53945
JB		 279 }
280 };
32aad86f 281 int ret;
79e53945 282
f899fc64 283 if ((ret = i2c_transfer(intel_sdvo->i2c, msgs, 2)) == 2)
79e53945 284 return true;
79e53945 285
8a4c47f3 286 DRM_DEBUG_KMS("i2c transfer returned %d\n", ret);
79e53945
JB		 287 return false;
288}
289
79e53945
JB		 290#define SDVO_CMD_NAME_ENTRY(cmd) {cmd, #cmd}
291/** Mapping of command numbers to names, for debug output */
005568be 292static const struct _sdvo_cmd_name {
e2f0ba97 293 u8 cmd;
2e88e40b 294 const char *name;
579627ea 295} __attribute__ ((packed)) sdvo_cmd_names[] = {
0206e353
AJ		 296 SDVO_CMD_NAME_ENTRY(SDVO_CMD_RESET),
297 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_DEVICE_CAPS),
298 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_FIRMWARE_REV),
299 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_TRAINED_INPUTS),
300 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ACTIVE_OUTPUTS),
301 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ACTIVE_OUTPUTS),
302 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_IN_OUT_MAP),
303 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_IN_OUT_MAP),
304 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ATTACHED_DISPLAYS),
305 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HOT_PLUG_SUPPORT),
306 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ACTIVE_HOT_PLUG),
307 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ACTIVE_HOT_PLUG),
308 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INTERRUPT_EVENT_SOURCE),
309 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TARGET_INPUT),
310 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TARGET_OUTPUT),
311 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INPUT_TIMINGS_PART1),
312 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INPUT_TIMINGS_PART2),
313 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_INPUT_TIMINGS_PART1),
314 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_INPUT_TIMINGS_PART2),
315 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_INPUT_TIMINGS_PART1),
316 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_OUTPUT_TIMINGS_PART1),
317 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_OUTPUT_TIMINGS_PART2),
318 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OUTPUT_TIMINGS_PART1),
319 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OUTPUT_TIMINGS_PART2),
320 SDVO_CMD_NAME_ENTRY(SDVO_CMD_CREATE_PREFERRED_INPUT_TIMING),
321 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART1),
322 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART2),
323 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INPUT_PIXEL_CLOCK_RANGE),
324 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OUTPUT_PIXEL_CLOCK_RANGE),
325 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_CLOCK_RATE_MULTS),
326 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_CLOCK_RATE_MULT),
327 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_CLOCK_RATE_MULT),
328 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_TV_FORMATS),
329 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_TV_FORMAT),
330 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TV_FORMAT),
331 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_POWER_STATES),
332 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_POWER_STATE),
333 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ENCODER_POWER_STATE),
334 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_DISPLAY_POWER_STATE),
335 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_CONTROL_BUS_SWITCH),
336 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SDTV_RESOLUTION_SUPPORT),
337 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SCALED_HDTV_RESOLUTION_SUPPORT),
338 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_ENHANCEMENTS),
339
340 /* Add the op code for SDVO enhancements */
341 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_HPOS),
342 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HPOS),
343 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HPOS),
344 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_VPOS),
345 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_VPOS),
346 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_VPOS),
347 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_SATURATION),
348 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SATURATION),
349 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_SATURATION),
350 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_HUE),
351 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HUE),
352 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HUE),
353 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_CONTRAST),
354 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_CONTRAST),
355 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_CONTRAST),
356 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_BRIGHTNESS),
357 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_BRIGHTNESS),
358 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_BRIGHTNESS),
359 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_OVERSCAN_H),
360 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OVERSCAN_H),
361 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_OVERSCAN_H),
362 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_OVERSCAN_V),
363 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OVERSCAN_V),
364 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_OVERSCAN_V),
365 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_FLICKER_FILTER),
366 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_FLICKER_FILTER),
367 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_FLICKER_FILTER),
368 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_FLICKER_FILTER_ADAPTIVE),
369 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_FLICKER_FILTER_ADAPTIVE),
370 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_FLICKER_FILTER_ADAPTIVE),
371 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_FLICKER_FILTER_2D),
372 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_FLICKER_FILTER_2D),
373 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_FLICKER_FILTER_2D),
374 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_SHARPNESS),
375 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SHARPNESS),
376 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_SHARPNESS),
377 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_DOT_CRAWL),
378 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_DOT_CRAWL),
379 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_TV_CHROMA_FILTER),
380 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_TV_CHROMA_FILTER),
381 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TV_CHROMA_FILTER),
382 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_TV_LUMA_FILTER),
383 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_TV_LUMA_FILTER),
384 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TV_LUMA_FILTER),
385
386 /* HDMI op code */
387 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPP_ENCODE),
388 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ENCODE),
389 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ENCODE),
390 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_PIXEL_REPLI),
391 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_PIXEL_REPLI),
392 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_COLORIMETRY_CAP),
393 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_COLORIMETRY),
394 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_COLORIMETRY),
395 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_AUDIO_ENCRYPT_PREFER),
396 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_AUDIO_STAT),
397 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_AUDIO_STAT),
398 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_INDEX),
399 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HBUF_INDEX),
400 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_INFO),
401 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_AV_SPLIT),
402 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HBUF_AV_SPLIT),
403 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_TXRATE),
404 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HBUF_TXRATE),
405 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HBUF_DATA),
406 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_DATA),
79e53945
JB		 407};
408
2a5c0832 409#define SDVO_NAME(svdo) ((svdo)->port == PORT_B ? "SDVOB" : "SDVOC")
79e53945 410
ea5b213a 411static void intel_sdvo_debug_write(struct intel_sdvo *intel_sdvo, u8 cmd,
32aad86f 412 const void *args, int args_len)
79e53945 413{
84fcb469
DV		 414 int i, pos = 0;
415#define BUF_LEN 256
416 char buffer[BUF_LEN];
417
418#define BUF_PRINT(args...) \
419 pos += snprintf(buffer + pos, max_t(int, BUF_LEN - pos, 0), args)
420
79e53945 421
84fcb469
DV		 422 for (i = 0; i < args_len; i++) {
423 BUF_PRINT("%02X ", ((u8 *)args)[i]);
424 }
425 for (; i < 8; i++) {
426 BUF_PRINT(" ");
427 }
04ad327f 428 for (i = 0; i < ARRAY_SIZE(sdvo_cmd_names); i++) {
79e53945 429 if (cmd == sdvo_cmd_names[i].cmd) {
84fcb469 430 BUF_PRINT("(%s)", sdvo_cmd_names[i].name);
79e53945
JB		 431 break;
432 }
433 }
84fcb469
DV		 434 if (i == ARRAY_SIZE(sdvo_cmd_names)) {
435 BUF_PRINT("(%02X)", cmd);
436 }
437 BUG_ON(pos >= BUF_LEN - 1);
438#undef BUF_PRINT
439#undef BUF_LEN
440
441 DRM_DEBUG_KMS("%s: W: %02X %s\n", SDVO_NAME(intel_sdvo), cmd, buffer);
79e53945 442}
79e53945 443
4d9194de 444static const char * const cmd_status_names[] = {
e957d772
CW		 445 "Power on",
446 "Success",
447 "Not supported",
448 "Invalid arg",
449 "Pending",
450 "Target not specified",
451 "Scaling not supported"
452};
453
a8506684
DV		 454static bool __intel_sdvo_write_cmd(struct intel_sdvo *intel_sdvo, u8 cmd,
455 const void *args, int args_len,
456 bool unlocked)
79e53945 457{
3bf3f452
BW		 458 u8 *buf, status;
459 struct i2c_msg *msgs;
460 int i, ret = true;
461
a8506684 462 /* Would be simpler to allocate both in one go ? */
5c67eeb6 463 buf = kzalloc(args_len * 2 + 2, GFP_KERNEL);
3bf3f452
BW		 464 if (!buf)
465 return false;
466
467 msgs = kcalloc(args_len + 3, sizeof(*msgs), GFP_KERNEL);
0274df3e 468 if (!msgs) {
a8506684 469 kfree(buf);
3bf3f452 470 return false;
a8506684 471 }
79e53945 472
ea5b213a 473 intel_sdvo_debug_write(intel_sdvo, cmd, args, args_len);
79e53945
JB		 474
475 for (i = 0; i < args_len; i++) {
e957d772
CW		 476 msgs[i].addr = intel_sdvo->slave_addr;
477 msgs[i].flags = 0;
478 msgs[i].len = 2;
479 msgs[i].buf = buf + 2 *i;
480 buf[2*i + 0] = SDVO_I2C_ARG_0 - i;
481 buf[2*i + 1] = ((u8*)args)[i];
482 }
483 msgs[i].addr = intel_sdvo->slave_addr;
484 msgs[i].flags = 0;
485 msgs[i].len = 2;
486 msgs[i].buf = buf + 2*i;
487 buf[2*i + 0] = SDVO_I2C_OPCODE;
488 buf[2*i + 1] = cmd;
489
490 /* the following two are to read the response */
491 status = SDVO_I2C_CMD_STATUS;
492 msgs[i+1].addr = intel_sdvo->slave_addr;
493 msgs[i+1].flags = 0;
494 msgs[i+1].len = 1;
495 msgs[i+1].buf = &status;
496
497 msgs[i+2].addr = intel_sdvo->slave_addr;
498 msgs[i+2].flags = I2C_M_RD;
499 msgs[i+2].len = 1;
500 msgs[i+2].buf = &status;
501
a8506684
DV		 502 if (unlocked)
503 ret = i2c_transfer(intel_sdvo->i2c, msgs, i+3);
504 else
505 ret = __i2c_transfer(intel_sdvo->i2c, msgs, i+3);
e957d772
CW		 506 if (ret < 0) {
507 DRM_DEBUG_KMS("I2c transfer returned %d\n", ret);
3bf3f452
BW		 508 ret = false;
509 goto out;
e957d772
CW		 510 }
511 if (ret != i+3) {
512 /* failure in I2C transfer */
513 DRM_DEBUG_KMS("I2c transfer returned %d/%d\n", ret, i+3);
3bf3f452 514 ret = false;
e957d772
CW		 515 }
516
3bf3f452
BW		 517out:
518 kfree(msgs);
519 kfree(buf);
520 return ret;
79e53945
JB		 521}
522
a8506684
DV		 523static bool intel_sdvo_write_cmd(struct intel_sdvo *intel_sdvo, u8 cmd,
524 const void *args, int args_len)
525{
526 return __intel_sdvo_write_cmd(intel_sdvo, cmd, args, args_len, true);
527}
528
b5c616a7
CW		 529static bool intel_sdvo_read_response(struct intel_sdvo *intel_sdvo,
530 void *response, int response_len)
79e53945 531{
fc37381c 532 u8 retry = 15; /* 5 quick checks, followed by 10 long checks */
b5c616a7 533 u8 status;
84fcb469
DV		 534 int i, pos = 0;
535#define BUF_LEN 256
536 char buffer[BUF_LEN];
79e53945 537
d121a5d2 538
b5c616a7
CW		 539 /*
540 * The documentation states that all commands will be
541 * processed within 15µs, and that we need only poll
542 * the status byte a maximum of 3 times in order for the
543 * command to be complete.
544 *
545 * Check 5 times in case the hardware failed to read the docs.
fc37381c
CW		 546 *
547 * Also beware that the first response by many devices is to
548 * reply PENDING and stall for time. TVs are notorious for
549 * requiring longer than specified to complete their replies.
550 * Originally (in the DDX long ago), the delay was only ever 15ms
551 * with an additional delay of 30ms applied for TVs added later after
552 * many experiments. To accommodate both sets of delays, we do a
553 * sequence of slow checks if the device is falling behind and fails
554 * to reply within 5*15µs.
b5c616a7 555 */
d121a5d2
CW		 556 if (!intel_sdvo_read_byte(intel_sdvo,
557 SDVO_I2C_CMD_STATUS,
558 &status))
559 goto log_fail;
560
1ad87e72 561 while ((status == SDVO_CMD_STATUS_PENDING ||
46a3f4a3 562 status == SDVO_CMD_STATUS_TARGET_NOT_SPECIFIED) && --retry) {
fc37381c
CW		 563 if (retry < 10)
564 msleep(15);
565 else
566 udelay(15);
567
b5c616a7
CW		 568 if (!intel_sdvo_read_byte(intel_sdvo,
569 SDVO_I2C_CMD_STATUS,
570 &status))
d121a5d2
CW		 571 goto log_fail;
572 }
b5c616a7 573
84fcb469
DV		 574#define BUF_PRINT(args...) \
575 pos += snprintf(buffer + pos, max_t(int, BUF_LEN - pos, 0), args)
576
79e53945 577 if (status <= SDVO_CMD_STATUS_SCALING_NOT_SUPP)
84fcb469 578 BUF_PRINT("(%s)", cmd_status_names[status]);
79e53945 579 else
84fcb469 580 BUF_PRINT("(??? %d)", status);
79e53945 581
b5c616a7
CW		 582 if (status != SDVO_CMD_STATUS_SUCCESS)
583 goto log_fail;
79e53945 584
b5c616a7
CW		 585 /* Read the command response */
586 for (i = 0; i < response_len; i++) {
587 if (!intel_sdvo_read_byte(intel_sdvo,
588 SDVO_I2C_RETURN_0 + i,
589 &((u8 *)response)[i]))
590 goto log_fail;
84fcb469 591 BUF_PRINT(" %02X", ((u8 *)response)[i]);
b5c616a7 592 }
84fcb469
DV		 593 BUG_ON(pos >= BUF_LEN - 1);
594#undef BUF_PRINT
595#undef BUF_LEN
596
597 DRM_DEBUG_KMS("%s: R: %s\n", SDVO_NAME(intel_sdvo), buffer);
b5c616a7 598 return true;
79e53945 599
b5c616a7 600log_fail:
84fcb469 601 DRM_DEBUG_KMS("%s: R: ... failed\n", SDVO_NAME(intel_sdvo));
b5c616a7 602 return false;
79e53945
JB		 603}
604
5e7234c9 605static int intel_sdvo_get_pixel_multiplier(const struct drm_display_mode *adjusted_mode)
79e53945 606{
aad941d5 607 if (adjusted_mode->crtc_clock >= 100000)
79e53945 608 return 1;
aad941d5 609 else if (adjusted_mode->crtc_clock >= 50000)
79e53945
JB		 610 return 2;
611 else
612 return 4;
613}
614
a8506684
DV		 615static bool __intel_sdvo_set_control_bus_switch(struct intel_sdvo *intel_sdvo,
616 u8 ddc_bus)
79e53945 617{
d121a5d2 618 /* This must be the immediately preceding write before the i2c xfer */
a8506684
DV		 619 return __intel_sdvo_write_cmd(intel_sdvo,
620 SDVO_CMD_SET_CONTROL_BUS_SWITCH,
621 &ddc_bus, 1, false);
79e53945
JB		 622}
623
32aad86f 624static bool intel_sdvo_set_value(struct intel_sdvo *intel_sdvo, u8 cmd, const void *data, int len)
79e53945 625{
d121a5d2
CW		 626 if (!intel_sdvo_write_cmd(intel_sdvo, cmd, data, len))
627 return false;
628
629 return intel_sdvo_read_response(intel_sdvo, NULL, 0);
32aad86f 630}
79e53945 631
32aad86f
CW		 632static bool
633intel_sdvo_get_value(struct intel_sdvo *intel_sdvo, u8 cmd, void *value, int len)
634{
635 if (!intel_sdvo_write_cmd(intel_sdvo, cmd, NULL, 0))
636 return false;
79e53945 637
32aad86f
CW		 638 return intel_sdvo_read_response(intel_sdvo, value, len);
639}
79e53945 640
32aad86f
CW		 641static bool intel_sdvo_set_target_input(struct intel_sdvo *intel_sdvo)
642{
643 struct intel_sdvo_set_target_input_args targets = {0};
644 return intel_sdvo_set_value(intel_sdvo,
645 SDVO_CMD_SET_TARGET_INPUT,
646 &targets, sizeof(targets));
79e53945
JB		 647}
648
649/**
650 * Return whether each input is trained.
651 *
652 * This function is making an assumption about the layout of the response,
653 * which should be checked against the docs.
654 */
ea5b213a 655static bool intel_sdvo_get_trained_inputs(struct intel_sdvo *intel_sdvo, bool *input_1, bool *input_2)
79e53945
JB		 656{
657 struct intel_sdvo_get_trained_inputs_response response;
79e53945 658
1a3665c8 659 BUILD_BUG_ON(sizeof(response) != 1);
32aad86f
CW		 660 if (!intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_TRAINED_INPUTS,
661 &response, sizeof(response)))
79e53945
JB		 662 return false;
663
664 *input_1 = response.input0_trained;
665 *input_2 = response.input1_trained;
666 return true;
667}
668
ea5b213a 669static bool intel_sdvo_set_active_outputs(struct intel_sdvo *intel_sdvo,
79e53945
JB		 670 u16 outputs)
671{
32aad86f
CW		 672 return intel_sdvo_set_value(intel_sdvo,
673 SDVO_CMD_SET_ACTIVE_OUTPUTS,
674 &outputs, sizeof(outputs));
79e53945
JB		 675}
676
4ac41f47
DV		 677static bool intel_sdvo_get_active_outputs(struct intel_sdvo *intel_sdvo,
678 u16 *outputs)
679{
680 return intel_sdvo_get_value(intel_sdvo,
681 SDVO_CMD_GET_ACTIVE_OUTPUTS,
682 outputs, sizeof(*outputs));
683}
684
ea5b213a 685static bool intel_sdvo_set_encoder_power_state(struct intel_sdvo *intel_sdvo,
79e53945
JB		 686 int mode)
687{
32aad86f 688 u8 state = SDVO_ENCODER_STATE_ON;
79e53945
JB		 689
690 switch (mode) {
691 case DRM_MODE_DPMS_ON:
692 state = SDVO_ENCODER_STATE_ON;
693 break;
694 case DRM_MODE_DPMS_STANDBY:
695 state = SDVO_ENCODER_STATE_STANDBY;
696 break;
697 case DRM_MODE_DPMS_SUSPEND:
698 state = SDVO_ENCODER_STATE_SUSPEND;
699 break;
700 case DRM_MODE_DPMS_OFF:
701 state = SDVO_ENCODER_STATE_OFF;
702 break;
703 }
704
32aad86f
CW		 705 return intel_sdvo_set_value(intel_sdvo,
706 SDVO_CMD_SET_ENCODER_POWER_STATE, &state, sizeof(state));
79e53945
JB		 707}
708
ea5b213a 709static bool intel_sdvo_get_input_pixel_clock_range(struct intel_sdvo *intel_sdvo,
79e53945
JB		 710 int *clock_min,
711 int *clock_max)
712{
713 struct intel_sdvo_pixel_clock_range clocks;
79e53945 714
1a3665c8 715 BUILD_BUG_ON(sizeof(clocks) != 4);
32aad86f
CW		 716 if (!intel_sdvo_get_value(intel_sdvo,
717 SDVO_CMD_GET_INPUT_PIXEL_CLOCK_RANGE,
718 &clocks, sizeof(clocks)))
79e53945
JB		 719 return false;
720
721 /* Convert the values from units of 10 kHz to kHz. */
722 *clock_min = clocks.min * 10;
723 *clock_max = clocks.max * 10;
79e53945
JB		 724 return true;
725}
726
ea5b213a 727static bool intel_sdvo_set_target_output(struct intel_sdvo *intel_sdvo,
79e53945
JB		 728 u16 outputs)
729{
32aad86f
CW		 730 return intel_sdvo_set_value(intel_sdvo,
731 SDVO_CMD_SET_TARGET_OUTPUT,
732 &outputs, sizeof(outputs));
79e53945
JB		 733}
734
ea5b213a 735static bool intel_sdvo_set_timing(struct intel_sdvo *intel_sdvo, u8 cmd,
79e53945
JB		 736 struct intel_sdvo_dtd *dtd)
737{
32aad86f
CW		 738 return intel_sdvo_set_value(intel_sdvo, cmd, &dtd->part1, sizeof(dtd->part1)) &&
739 intel_sdvo_set_value(intel_sdvo, cmd + 1, &dtd->part2, sizeof(dtd->part2));
79e53945
JB		 740}
741
045ac3b5
JB		 742static bool intel_sdvo_get_timing(struct intel_sdvo *intel_sdvo, u8 cmd,
743 struct intel_sdvo_dtd *dtd)
744{
745 return intel_sdvo_get_value(intel_sdvo, cmd, &dtd->part1, sizeof(dtd->part1)) &&
746 intel_sdvo_get_value(intel_sdvo, cmd + 1, &dtd->part2, sizeof(dtd->part2));
747}
748
ea5b213a 749static bool intel_sdvo_set_input_timing(struct intel_sdvo *intel_sdvo,
79e53945
JB		 750 struct intel_sdvo_dtd *dtd)
751{
ea5b213a 752 return intel_sdvo_set_timing(intel_sdvo,
79e53945
JB		 753 SDVO_CMD_SET_INPUT_TIMINGS_PART1, dtd);
754}
755
ea5b213a 756static bool intel_sdvo_set_output_timing(struct intel_sdvo *intel_sdvo,
79e53945
JB		 757 struct intel_sdvo_dtd *dtd)
758{
ea5b213a 759 return intel_sdvo_set_timing(intel_sdvo,
79e53945
JB		 760 SDVO_CMD_SET_OUTPUT_TIMINGS_PART1, dtd);
761}
762
045ac3b5
JB		 763static bool intel_sdvo_get_input_timing(struct intel_sdvo *intel_sdvo,
764 struct intel_sdvo_dtd *dtd)
765{
766 return intel_sdvo_get_timing(intel_sdvo,
767 SDVO_CMD_GET_INPUT_TIMINGS_PART1, dtd);
768}
769
e2f0ba97 770static bool
ea5b213a 771intel_sdvo_create_preferred_input_timing(struct intel_sdvo *intel_sdvo,
e2f0ba97
JB		 772 uint16_t clock,
773 uint16_t width,
774 uint16_t height)
775{
776 struct intel_sdvo_preferred_input_timing_args args;
e2f0ba97 777
e642c6f1 778 memset(&args, 0, sizeof(args));
e2f0ba97
JB		 779 args.clock = clock;
780 args.width = width;
781 args.height = height;
e642c6f1 782 args.interlace = 0;
12682a97 783
ea5b213a
CW		 784 if (intel_sdvo->is_lvds &&
785 (intel_sdvo->sdvo_lvds_fixed_mode->hdisplay != width ||
786 intel_sdvo->sdvo_lvds_fixed_mode->vdisplay != height))
12682a97 787 args.scaled = 1;
788
32aad86f
CW		 789 return intel_sdvo_set_value(intel_sdvo,
790 SDVO_CMD_CREATE_PREFERRED_INPUT_TIMING,
791 &args, sizeof(args));
e2f0ba97
JB		 792}
793
ea5b213a 794static bool intel_sdvo_get_preferred_input_timing(struct intel_sdvo *intel_sdvo,
e2f0ba97
JB		 795 struct intel_sdvo_dtd *dtd)
796{
1a3665c8
CW		 797 BUILD_BUG_ON(sizeof(dtd->part1) != 8);
798 BUILD_BUG_ON(sizeof(dtd->part2) != 8);
32aad86f
CW		 799 return intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART1,
800 &dtd->part1, sizeof(dtd->part1)) &&
801 intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART2,
802 &dtd->part2, sizeof(dtd->part2));
e2f0ba97 803}
79e53945 804
ea5b213a 805static bool intel_sdvo_set_clock_rate_mult(struct intel_sdvo *intel_sdvo, u8 val)
79e53945 806{
32aad86f 807 return intel_sdvo_set_value(intel_sdvo, SDVO_CMD_SET_CLOCK_RATE_MULT, &val, 1);
79e53945
JB		 808}
809
e2f0ba97 810static void intel_sdvo_get_dtd_from_mode(struct intel_sdvo_dtd *dtd,
32aad86f 811 const struct drm_display_mode *mode)
79e53945 812{
e2f0ba97
JB		 813 uint16_t width, height;
814 uint16_t h_blank_len, h_sync_len, v_blank_len, v_sync_len;
815 uint16_t h_sync_offset, v_sync_offset;
6651819b 816 int mode_clock;
79e53945 817
1c4a814e
DV		 818 memset(dtd, 0, sizeof(*dtd));
819
c6ebd4c0
DV		 820 width = mode->hdisplay;
821 height = mode->vdisplay;
79e53945
JB		 822
823 /* do some mode translations */
c6ebd4c0
DV		 824 h_blank_len = mode->htotal - mode->hdisplay;
825 h_sync_len = mode->hsync_end - mode->hsync_start;
79e53945 826
c6ebd4c0
DV		 827 v_blank_len = mode->vtotal - mode->vdisplay;
828 v_sync_len = mode->vsync_end - mode->vsync_start;
79e53945 829
c6ebd4c0
DV		 830 h_sync_offset = mode->hsync_start - mode->hdisplay;
831 v_sync_offset = mode->vsync_start - mode->vdisplay;
79e53945 832
6651819b 833 mode_clock = mode->clock;
6651819b
DV		 834 mode_clock /= 10;
835 dtd->part1.clock = mode_clock;
836
e2f0ba97
JB		 837 dtd->part1.h_active = width & 0xff;
838 dtd->part1.h_blank = h_blank_len & 0xff;
839 dtd->part1.h_high = (((width >> 8) & 0xf) << 4) |
79e53945 840 ((h_blank_len >> 8) & 0xf);
e2f0ba97
JB		 841 dtd->part1.v_active = height & 0xff;
842 dtd->part1.v_blank = v_blank_len & 0xff;
843 dtd->part1.v_high = (((height >> 8) & 0xf) << 4) |
79e53945
JB		 844 ((v_blank_len >> 8) & 0xf);
845
171a9e96 846 dtd->part2.h_sync_off = h_sync_offset & 0xff;
e2f0ba97
JB		 847 dtd->part2.h_sync_width = h_sync_len & 0xff;
848 dtd->part2.v_sync_off_width = (v_sync_offset & 0xf) << 4 |
79e53945 849 (v_sync_len & 0xf);
e2f0ba97 850 dtd->part2.sync_off_width_high = ((h_sync_offset & 0x300) >> 2) |
79e53945
JB		 851 ((h_sync_len & 0x300) >> 4) | ((v_sync_offset & 0x30) >> 2) |
852 ((v_sync_len & 0x30) >> 4);
853
e2f0ba97 854 dtd->part2.dtd_flags = 0x18;
59d92bfa
DV		 855 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
856 dtd->part2.dtd_flags |= DTD_FLAG_INTERLACE;
79e53945 857 if (mode->flags & DRM_MODE_FLAG_PHSYNC)
59d92bfa 858 dtd->part2.dtd_flags |= DTD_FLAG_HSYNC_POSITIVE;
79e53945 859 if (mode->flags & DRM_MODE_FLAG_PVSYNC)
59d92bfa 860 dtd->part2.dtd_flags |= DTD_FLAG_VSYNC_POSITIVE;
e2f0ba97 861
e2f0ba97 862 dtd->part2.v_sync_off_high = v_sync_offset & 0xc0;
e2f0ba97
JB		 863}
864
1c4a814e 865static void intel_sdvo_get_mode_from_dtd(struct drm_display_mode *pmode,
32aad86f 866 const struct intel_sdvo_dtd *dtd)
e2f0ba97 867{
1c4a814e
DV		 868 struct drm_display_mode mode = {};
869
870 mode.hdisplay = dtd->part1.h_active;
871 mode.hdisplay += ((dtd->part1.h_high >> 4) & 0x0f) << 8;
872 mode.hsync_start = mode.hdisplay + dtd->part2.h_sync_off;
873 mode.hsync_start += (dtd->part2.sync_off_width_high & 0xc0) << 2;
874 mode.hsync_end = mode.hsync_start + dtd->part2.h_sync_width;
875 mode.hsync_end += (dtd->part2.sync_off_width_high & 0x30) << 4;
876 mode.htotal = mode.hdisplay + dtd->part1.h_blank;
877 mode.htotal += (dtd->part1.h_high & 0xf) << 8;
878
879 mode.vdisplay = dtd->part1.v_active;
880 mode.vdisplay += ((dtd->part1.v_high >> 4) & 0x0f) << 8;
881 mode.vsync_start = mode.vdisplay;
882 mode.vsync_start += (dtd->part2.v_sync_off_width >> 4) & 0xf;
883 mode.vsync_start += (dtd->part2.sync_off_width_high & 0x0c) << 2;
884 mode.vsync_start += dtd->part2.v_sync_off_high & 0xc0;
885 mode.vsync_end = mode.vsync_start +
e2f0ba97 886 (dtd->part2.v_sync_off_width & 0xf);
1c4a814e
DV		 887 mode.vsync_end += (dtd->part2.sync_off_width_high & 0x3) << 4;
888 mode.vtotal = mode.vdisplay + dtd->part1.v_blank;
889 mode.vtotal += (dtd->part1.v_high & 0xf) << 8;
e2f0ba97 890
1c4a814e 891 mode.clock = dtd->part1.clock * 10;
e2f0ba97 892
59d92bfa 893 if (dtd->part2.dtd_flags & DTD_FLAG_INTERLACE)
1c4a814e 894 mode.flags |= DRM_MODE_FLAG_INTERLACE;
59d92bfa 895 if (dtd->part2.dtd_flags & DTD_FLAG_HSYNC_POSITIVE)
1c4a814e 896 mode.flags |= DRM_MODE_FLAG_PHSYNC;
3cea210f 897 else
1c4a814e 898 mode.flags |= DRM_MODE_FLAG_NHSYNC;
59d92bfa 899 if (dtd->part2.dtd_flags & DTD_FLAG_VSYNC_POSITIVE)
1c4a814e 900 mode.flags |= DRM_MODE_FLAG_PVSYNC;
3cea210f 901 else
1c4a814e
DV		 902 mode.flags |= DRM_MODE_FLAG_NVSYNC;
903
904 drm_mode_set_crtcinfo(&mode, 0);
905
906 drm_mode_copy(pmode, &mode);
e2f0ba97
JB		 907}
908
e27d8538 909static bool intel_sdvo_check_supp_encode(struct intel_sdvo *intel_sdvo)
e2f0ba97 910{
e27d8538 911 struct intel_sdvo_encode encode;
e2f0ba97 912
1a3665c8 913 BUILD_BUG_ON(sizeof(encode) != 2);
e27d8538
CW		 914 return intel_sdvo_get_value(intel_sdvo,
915 SDVO_CMD_GET_SUPP_ENCODE,
916 &encode, sizeof(encode));
e2f0ba97
JB		 917}
918
ea5b213a 919static bool intel_sdvo_set_encode(struct intel_sdvo *intel_sdvo,
c751ce4f 920 uint8_t mode)
e2f0ba97 921{
32aad86f 922 return intel_sdvo_set_value(intel_sdvo, SDVO_CMD_SET_ENCODE, &mode, 1);
e2f0ba97
JB		 923}
924
ea5b213a 925static bool intel_sdvo_set_colorimetry(struct intel_sdvo *intel_sdvo,
e2f0ba97
JB		 926 uint8_t mode)
927{
32aad86f 928 return intel_sdvo_set_value(intel_sdvo, SDVO_CMD_SET_COLORIMETRY, &mode, 1);
e2f0ba97
JB		 929}
930
931#if 0
ea5b213a 932static void intel_sdvo_dump_hdmi_buf(struct intel_sdvo *intel_sdvo)
e2f0ba97
JB		 933{
934 int i, j;
935 uint8_t set_buf_index[2];
936 uint8_t av_split;
937 uint8_t buf_size;
938 uint8_t buf[48];
939 uint8_t *pos;
940
32aad86f 941 intel_sdvo_get_value(encoder, SDVO_CMD_GET_HBUF_AV_SPLIT, &av_split, 1);
e2f0ba97
JB		 942
943 for (i = 0; i <= av_split; i++) {
944 set_buf_index[0] = i; set_buf_index[1] = 0;
c751ce4f 945 intel_sdvo_write_cmd(encoder, SDVO_CMD_SET_HBUF_INDEX,
e2f0ba97 946 set_buf_index, 2);
c751ce4f
EA		 947 intel_sdvo_write_cmd(encoder, SDVO_CMD_GET_HBUF_INFO, NULL, 0);
948 intel_sdvo_read_response(encoder, &buf_size, 1);
e2f0ba97
JB		 949
950 pos = buf;
951 for (j = 0; j <= buf_size; j += 8) {
c751ce4f 952 intel_sdvo_write_cmd(encoder, SDVO_CMD_GET_HBUF_DATA,
e2f0ba97 953 NULL, 0);
c751ce4f 954 intel_sdvo_read_response(encoder, pos, 8);
e2f0ba97
JB		 955 pos += 8;
956 }
957 }
958}
959#endif
960
b6e0e543
DV		 961static bool intel_sdvo_write_infoframe(struct intel_sdvo *intel_sdvo,
962 unsigned if_index, uint8_t tx_rate,
fff63867 963 const uint8_t *data, unsigned length)
b6e0e543
DV		 964{
965 uint8_t set_buf_index[2] = { if_index, 0 };
966 uint8_t hbuf_size, tmp[8];
967 int i;
968
969 if (!intel_sdvo_set_value(intel_sdvo,
970 SDVO_CMD_SET_HBUF_INDEX,
971 set_buf_index, 2))
972 return false;
973
974 if (!intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_HBUF_INFO,
975 &hbuf_size, 1))
976 return false;
977
978 /* Buffer size is 0 based, hooray! */
979 hbuf_size++;
980
981 DRM_DEBUG_KMS("writing sdvo hbuf: %i, hbuf_size %i, hbuf_size: %i\n",
982 if_index, length, hbuf_size);
983
984 for (i = 0; i < hbuf_size; i += 8) {
985 memset(tmp, 0, 8);
986 if (i < length)
987 memcpy(tmp, data + i, min_t(unsigned, 8, length - i));
988
989 if (!intel_sdvo_set_value(intel_sdvo,
990 SDVO_CMD_SET_HBUF_DATA,
991 tmp, 8))
992 return false;
993 }
994
995 return intel_sdvo_set_value(intel_sdvo,
996 SDVO_CMD_SET_HBUF_TXRATE,
997 &tx_rate, 1);
998}
999
abedc077 1000static bool intel_sdvo_set_avi_infoframe(struct intel_sdvo *intel_sdvo,
f9fe0530 1001 struct intel_crtc_state *pipe_config)
e2f0ba97 1002{
15dcd350 1003 uint8_t sdvo_data[HDMI_INFOFRAME_SIZE(AVI)];
15dcd350
DL		 1004 union hdmi_infoframe frame;
1005 int ret;
1006 ssize_t len;
1007
1008 ret = drm_hdmi_avi_infoframe_from_display_mode(&frame.avi,
0c1f528c
SS		 1009 &pipe_config->base.adjusted_mode,
1010 false);
15dcd350
DL		 1011 if (ret < 0) {
1012 DRM_ERROR("couldn't fill AVI infoframe\n");
1013 return false;
1014 }
3c17fe4b 1015
abedc077 1016 if (intel_sdvo->rgb_quant_range_selectable) {
f9fe0530 1017 if (pipe_config->limited_color_range)
15dcd350
DL		 1018 frame.avi.quantization_range =
1019 HDMI_QUANTIZATION_RANGE_LIMITED;
abedc077 1020 else
15dcd350
DL		 1021 frame.avi.quantization_range =
1022 HDMI_QUANTIZATION_RANGE_FULL;
abedc077
VS		 1023 }
1024
15dcd350
DL		 1025 len = hdmi_infoframe_pack(&frame, sdvo_data, sizeof(sdvo_data));
1026 if (len < 0)
1027 return false;
81014b9d 1028
b6e0e543
DV		 1029 return intel_sdvo_write_infoframe(intel_sdvo, SDVO_HBUF_INDEX_AVI_IF,
1030 SDVO_HBUF_TX_VSYNC,
1031 sdvo_data, sizeof(sdvo_data));
e2f0ba97
JB		 1032}
1033
630d30a4
ML		 1034static bool intel_sdvo_set_tv_format(struct intel_sdvo *intel_sdvo,
1035 struct drm_connector_state *conn_state)
7026d4ac 1036{
ce6feabd 1037 struct intel_sdvo_tv_format format;
40039750 1038 uint32_t format_map;
ce6feabd 1039
630d30a4 1040 format_map = 1 << conn_state->tv.mode;
ce6feabd 1041 memset(&format, 0, sizeof(format));
32aad86f 1042 memcpy(&format, &format_map, min(sizeof(format), sizeof(format_map)));
ce6feabd 1043
32aad86f
CW		 1044 BUILD_BUG_ON(sizeof(format) != 6);
1045 return intel_sdvo_set_value(intel_sdvo,
1046 SDVO_CMD_SET_TV_FORMAT,
1047 &format, sizeof(format));
7026d4ac
ZW		 1048}
1049
32aad86f
CW		 1050static bool
1051intel_sdvo_set_output_timings_from_mode(struct intel_sdvo *intel_sdvo,
e811f5ae 1052 const struct drm_display_mode *mode)
e2f0ba97 1053{
32aad86f 1054 struct intel_sdvo_dtd output_dtd;
79e53945 1055
32aad86f
CW		 1056 if (!intel_sdvo_set_target_output(intel_sdvo,
1057 intel_sdvo->attached_output))
1058 return false;
e2f0ba97 1059
32aad86f
CW		 1060 intel_sdvo_get_dtd_from_mode(&output_dtd, mode);
1061 if (!intel_sdvo_set_output_timing(intel_sdvo, &output_dtd))
1062 return false;
e2f0ba97 1063
32aad86f
CW		 1064 return true;
1065}
1066
c9a29698
DV		 1067/* Asks the sdvo controller for the preferred input mode given the output mode.
1068 * Unfortunately we have to set up the full output mode to do that. */
32aad86f 1069static bool
c9a29698 1070intel_sdvo_get_preferred_input_mode(struct intel_sdvo *intel_sdvo,
e811f5ae 1071 const struct drm_display_mode *mode,
c9a29698 1072 struct drm_display_mode *adjusted_mode)
32aad86f 1073{
c9a29698
DV		 1074 struct intel_sdvo_dtd input_dtd;
1075
32aad86f
CW		 1076 /* Reset the input timing to the screen. Assume always input 0. */
1077 if (!intel_sdvo_set_target_input(intel_sdvo))
1078 return false;
e2f0ba97 1079
32aad86f
CW		 1080 if (!intel_sdvo_create_preferred_input_timing(intel_sdvo,
1081 mode->clock / 10,
1082 mode->hdisplay,
1083 mode->vdisplay))
1084 return false;
e2f0ba97 1085
32aad86f 1086 if (!intel_sdvo_get_preferred_input_timing(intel_sdvo,
c9a29698 1087 &input_dtd))
32aad86f 1088 return false;
e2f0ba97 1089
c9a29698 1090 intel_sdvo_get_mode_from_dtd(adjusted_mode, &input_dtd);
e751823d 1091 intel_sdvo->dtd_sdvo_flags = input_dtd.part2.sdvo_flags;
79e53945 1092
32aad86f
CW		 1093 return true;
1094}
12682a97 1095
5cec258b 1096static void i9xx_adjust_sdvo_tv_clock(struct intel_crtc_state *pipe_config)
70484559 1097{
3c52f4eb 1098 unsigned dotclock = pipe_config->port_clock;
70484559
DV		 1099 struct dpll *clock = &pipe_config->dpll;
1100
1101 /* SDVO TV has fixed PLL values depend on its clock range,
1102 this mirrors vbios setting. */
1103 if (dotclock >= 100000 && dotclock < 140500) {
1104 clock->p1 = 2;
1105 clock->p2 = 10;
1106 clock->n = 3;
1107 clock->m1 = 16;
1108 clock->m2 = 8;
1109 } else if (dotclock >= 140500 && dotclock <= 200000) {
1110 clock->p1 = 1;
1111 clock->p2 = 10;
1112 clock->n = 6;
1113 clock->m1 = 12;
1114 clock->m2 = 8;
1115 } else {
1116 WARN(1, "SDVO TV clock out of range: %i\n", dotclock);
1117 }
1118
1119 pipe_config->clock_set = true;
1120}
1121
6cc5f341 1122static bool intel_sdvo_compute_config(struct intel_encoder *encoder,
0a478c27
ML		 1123 struct intel_crtc_state *pipe_config,
1124 struct drm_connector_state *conn_state)
32aad86f 1125{
8aca63aa 1126 struct intel_sdvo *intel_sdvo = to_sdvo(encoder);
630d30a4
ML		 1127 struct intel_sdvo_connector_state *intel_sdvo_state =
1128 to_intel_sdvo_connector_state(conn_state);
2d112de7
ACO		 1129 struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
1130 struct drm_display_mode *mode = &pipe_config->base.mode;
12682a97 1131
5d2d38dd
DV		 1132 DRM_DEBUG_KMS("forcing bpc to 8 for SDVO\n");
1133 pipe_config->pipe_bpp = 8*3;
1134
6e266956 1135 if (HAS_PCH_SPLIT(to_i915(encoder->base.dev)))
5bfe2ac0
DV		 1136 pipe_config->has_pch_encoder = true;
1137
32aad86f
CW		 1138 /* We need to construct preferred input timings based on our
1139 * output timings. To do that, we have to set the output
1140 * timings, even though this isn't really the right place in
1141 * the sequence to do it. Oh well.
1142 */
1143 if (intel_sdvo->is_tv) {
1144 if (!intel_sdvo_set_output_timings_from_mode(intel_sdvo, mode))
1145 return false;
12682a97 1146
c9a29698
DV		 1147 (void) intel_sdvo_get_preferred_input_mode(intel_sdvo,
1148 mode,
1149 adjusted_mode);
09ede541 1150 pipe_config->sdvo_tv_clock = true;
ea5b213a 1151 } else if (intel_sdvo->is_lvds) {
32aad86f 1152 if (!intel_sdvo_set_output_timings_from_mode(intel_sdvo,
6c9547ff 1153 intel_sdvo->sdvo_lvds_fixed_mode))
e2f0ba97 1154 return false;
12682a97 1155
c9a29698
DV		 1156 (void) intel_sdvo_get_preferred_input_mode(intel_sdvo,
1157 mode,
1158 adjusted_mode);
e2f0ba97 1159 }
32aad86f
CW		 1160
1161 /* Make the CRTC code factor in the SDVO pixel multiplier. The
6c9547ff 1162 * SDVO device will factor out the multiplier during mode_set.
32aad86f 1163 */
6cc5f341
DV		 1164 pipe_config->pixel_multiplier =
1165 intel_sdvo_get_pixel_multiplier(adjusted_mode);
32aad86f 1166
630d30a4 1167 if (intel_sdvo_state->base.force_audio != HDMI_AUDIO_OFF_DVI)
b32962f8
ML		 1168 pipe_config->has_hdmi_sink = intel_sdvo->has_hdmi_monitor;
1169
630d30a4
ML		 1170 if (intel_sdvo_state->base.force_audio == HDMI_AUDIO_ON ||
1171 (intel_sdvo_state->base.force_audio == HDMI_AUDIO_AUTO && intel_sdvo->has_hdmi_audio))
b32962f8 1172 pipe_config->has_audio = true;
9f04003e 1173
630d30a4 1174 if (intel_sdvo_state->base.broadcast_rgb == INTEL_BROADCAST_RGB_AUTO) {
55bc60db 1175 /* See CEA-861-E - 5.1 Default Encoding Parameters */
4f3a8bc7
PZ		 1176 /* FIXME: This bit is only valid when using TMDS encoding and 8
1177 * bit per color mode. */
9f04003e 1178 if (pipe_config->has_hdmi_sink &&
18316c8c 1179 drm_match_cea_mode(adjusted_mode) > 1)
69f5acc8
DV		 1180 pipe_config->limited_color_range = true;
1181 } else {
9f04003e 1182 if (pipe_config->has_hdmi_sink &&
630d30a4 1183 intel_sdvo_state->base.broadcast_rgb == INTEL_BROADCAST_RGB_LIMITED)
69f5acc8 1184 pipe_config->limited_color_range = true;
55bc60db
VS		 1185 }
1186
70484559
DV		 1187 /* Clock computation needs to happen after pixel multiplier. */
1188 if (intel_sdvo->is_tv)
1189 i9xx_adjust_sdvo_tv_clock(pipe_config);
1190
7949dd47
VS		 1191 /* Set user selected PAR to incoming mode's member */
1192 if (intel_sdvo->is_hdmi)
0e9f25d0 1193 adjusted_mode->picture_aspect_ratio = conn_state->picture_aspect_ratio;
7949dd47 1194
e2f0ba97
JB		 1195 return true;
1196}
1197
630d30a4
ML		 1198#define UPDATE_PROPERTY(input, NAME) \
1199 do { \
1200 val = input; \
1201 intel_sdvo_set_value(intel_sdvo, SDVO_CMD_SET_##NAME, &val, sizeof(val)); \
1202 } while (0)
1203
1204static void intel_sdvo_update_props(struct intel_sdvo *intel_sdvo,
1205 struct intel_sdvo_connector_state *sdvo_state)
1206{
1207 struct drm_connector_state *conn_state = &sdvo_state->base.base;
1208 struct intel_sdvo_connector *intel_sdvo_conn =
1209 to_intel_sdvo_connector(conn_state->connector);
1210 uint16_t val;
1211
1212 if (intel_sdvo_conn->left)
1213 UPDATE_PROPERTY(sdvo_state->tv.overscan_h, OVERSCAN_H);
1214
1215 if (intel_sdvo_conn->top)
1216 UPDATE_PROPERTY(sdvo_state->tv.overscan_v, OVERSCAN_V);
1217
1218 if (intel_sdvo_conn->hpos)
1219 UPDATE_PROPERTY(sdvo_state->tv.hpos, HPOS);
1220
1221 if (intel_sdvo_conn->vpos)
1222 UPDATE_PROPERTY(sdvo_state->tv.vpos, VPOS);
1223
1224 if (intel_sdvo_conn->saturation)
1225 UPDATE_PROPERTY(conn_state->tv.saturation, SATURATION);
1226
1227 if (intel_sdvo_conn->contrast)
1228 UPDATE_PROPERTY(conn_state->tv.contrast, CONTRAST);
1229
1230 if (intel_sdvo_conn->hue)
1231 UPDATE_PROPERTY(conn_state->tv.hue, HUE);
1232
1233 if (intel_sdvo_conn->brightness)
1234 UPDATE_PROPERTY(conn_state->tv.brightness, BRIGHTNESS);
1235
1236 if (intel_sdvo_conn->sharpness)
1237 UPDATE_PROPERTY(sdvo_state->tv.sharpness, SHARPNESS);
1238
1239 if (intel_sdvo_conn->flicker_filter)
1240 UPDATE_PROPERTY(sdvo_state->tv.flicker_filter, FLICKER_FILTER);
1241
1242 if (intel_sdvo_conn->flicker_filter_2d)
1243 UPDATE_PROPERTY(sdvo_state->tv.flicker_filter_2d, FLICKER_FILTER_2D);
1244
1245 if (intel_sdvo_conn->flicker_filter_adaptive)
1246 UPDATE_PROPERTY(sdvo_state->tv.flicker_filter_adaptive, FLICKER_FILTER_ADAPTIVE);
1247
1248 if (intel_sdvo_conn->tv_chroma_filter)
1249 UPDATE_PROPERTY(sdvo_state->tv.chroma_filter, TV_CHROMA_FILTER);
1250
1251 if (intel_sdvo_conn->tv_luma_filter)
1252 UPDATE_PROPERTY(sdvo_state->tv.luma_filter, TV_LUMA_FILTER);
1253
1254 if (intel_sdvo_conn->dot_crawl)
1255 UPDATE_PROPERTY(sdvo_state->tv.dot_crawl, DOT_CRAWL);
1256
1257#undef UPDATE_PROPERTY
1258}
1259
fd6bbda9
ML		 1260static void intel_sdvo_pre_enable(struct intel_encoder *intel_encoder,
1261 struct intel_crtc_state *crtc_state,
1262 struct drm_connector_state *conn_state)
e2f0ba97 1263{
66478475 1264 struct drm_i915_private *dev_priv = to_i915(intel_encoder->base.dev);
f9fe0530
ML		 1265 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
1266 const struct drm_display_mode *adjusted_mode = &crtc_state->base.adjusted_mode;
630d30a4 1267 struct intel_sdvo_connector_state *sdvo_state = to_intel_sdvo_connector_state(conn_state);
f9fe0530 1268 struct drm_display_mode *mode = &crtc_state->base.mode;
8aca63aa 1269 struct intel_sdvo *intel_sdvo = to_sdvo(intel_encoder);
6c9547ff 1270 u32 sdvox;
e2f0ba97 1271 struct intel_sdvo_in_out_map in_out;
6651819b 1272 struct intel_sdvo_dtd input_dtd, output_dtd;
6c9547ff 1273 int rate;
e2f0ba97 1274
630d30a4
ML		 1275 intel_sdvo_update_props(intel_sdvo, sdvo_state);
1276
e2f0ba97
JB		 1277 /* First, set the input mapping for the first input to our controlled
1278 * output. This is only correct if we're a single-input device, in
1279 * which case the first input is the output from the appropriate SDVO
1280 * channel on the motherboard. In a two-input device, the first input
1281 * will be SDVOB and the second SDVOC.
1282 */
ea5b213a 1283 in_out.in0 = intel_sdvo->attached_output;
e2f0ba97
JB		 1284 in_out.in1 = 0;
1285
c74696b9
PR		 1286 intel_sdvo_set_value(intel_sdvo,
1287 SDVO_CMD_SET_IN_OUT_MAP,
1288 &in_out, sizeof(in_out));
e2f0ba97 1289
6c9547ff
CW		 1290 /* Set the output timings to the screen */
1291 if (!intel_sdvo_set_target_output(intel_sdvo,
1292 intel_sdvo->attached_output))
1293 return;
e2f0ba97 1294
6651819b
DV		 1295 /* lvds has a special fixed output timing. */
1296 if (intel_sdvo->is_lvds)
1297 intel_sdvo_get_dtd_from_mode(&output_dtd,
1298 intel_sdvo->sdvo_lvds_fixed_mode);
1299 else
1300 intel_sdvo_get_dtd_from_mode(&output_dtd, mode);
c8d4bb54
DV		 1301 if (!intel_sdvo_set_output_timing(intel_sdvo, &output_dtd))
1302 DRM_INFO("Setting output timings on %s failed\n",
1303 SDVO_NAME(intel_sdvo));
79e53945
JB		 1304
1305 /* Set the input timing to the screen. Assume always input 0. */
32aad86f
CW		 1306 if (!intel_sdvo_set_target_input(intel_sdvo))
1307 return;
79e53945 1308
f9fe0530 1309 if (crtc_state->has_hdmi_sink) {
97aaf910
CW		 1310 intel_sdvo_set_encode(intel_sdvo, SDVO_ENCODE_HDMI);
1311 intel_sdvo_set_colorimetry(intel_sdvo,
1312 SDVO_COLORIMETRY_RGB256);
f9fe0530 1313 intel_sdvo_set_avi_infoframe(intel_sdvo, crtc_state);
97aaf910
CW		 1314 } else
1315 intel_sdvo_set_encode(intel_sdvo, SDVO_ENCODE_DVI);
7026d4ac 1316
6c9547ff 1317 if (intel_sdvo->is_tv &&
630d30a4 1318 !intel_sdvo_set_tv_format(intel_sdvo, conn_state))
6c9547ff 1319 return;
e2f0ba97 1320
6651819b 1321 intel_sdvo_get_dtd_from_mode(&input_dtd, adjusted_mode);
eeb47937 1322
e751823d
EE		 1323 if (intel_sdvo->is_tv || intel_sdvo->is_lvds)
1324 input_dtd.part2.sdvo_flags = intel_sdvo->dtd_sdvo_flags;
c8d4bb54
DV		 1325 if (!intel_sdvo_set_input_timing(intel_sdvo, &input_dtd))
1326 DRM_INFO("Setting input timings on %s failed\n",
1327 SDVO_NAME(intel_sdvo));
79e53945 1328
f9fe0530 1329 switch (crtc_state->pixel_multiplier) {
6c9547ff 1330 default:
fd0753cf 1331 WARN(1, "unknown pixel multiplier specified\n");
32aad86f
CW		 1332 case 1: rate = SDVO_CLOCK_RATE_MULT_1X; break;
1333 case 2: rate = SDVO_CLOCK_RATE_MULT_2X; break;
1334 case 4: rate = SDVO_CLOCK_RATE_MULT_4X; break;
79e53945 1335 }
32aad86f
CW		 1336 if (!intel_sdvo_set_clock_rate_mult(intel_sdvo, rate))
1337 return;
79e53945
JB		 1338
1339 /* Set the SDVO control regs. */
66478475 1340 if (INTEL_GEN(dev_priv) >= 4) {
ba68e086
PZ		 1341 /* The real mode polarity is set by the SDVO commands, using
1342 * struct intel_sdvo_dtd. */
1343 sdvox = SDVO_VSYNC_ACTIVE_HIGH | SDVO_HSYNC_ACTIVE_HIGH;
6e266956 1344 if (!HAS_PCH_SPLIT(dev_priv) && crtc_state->limited_color_range)
69f5acc8 1345 sdvox |= HDMI_COLOR_RANGE_16_235;
66478475 1346 if (INTEL_GEN(dev_priv) < 5)
6714afb1 1347 sdvox |= SDVO_BORDER_ENABLE;
e2f0ba97 1348 } else {
6c9547ff 1349 sdvox = I915_READ(intel_sdvo->sdvo_reg);
2a5c0832 1350 if (intel_sdvo->port == PORT_B)
e2f0ba97 1351 sdvox &= SDVOB_PRESERVE_MASK;
2a5c0832 1352 else
e2f0ba97 1353 sdvox &= SDVOC_PRESERVE_MASK;
e2f0ba97
JB		 1354 sdvox |= (9 << 19) | SDVO_BORDER_ENABLE;
1355 }
3573c410 1356
b9eb89b2 1357 if (HAS_PCH_CPT(dev_priv))
eeb47937 1358 sdvox |= SDVO_PIPE_SEL_CPT(crtc->pipe);
3573c410 1359 else
eeb47937 1360 sdvox |= SDVO_PIPE_SEL(crtc->pipe);
3573c410 1361
de44e256
DV		 1362 if (crtc_state->has_audio) {
1363 WARN_ON_ONCE(INTEL_GEN(dev_priv) < 4);
6c9547ff 1364 sdvox |= SDVO_AUDIO_ENABLE;
de44e256 1365 }
79e53945 1366
66478475 1367 if (INTEL_GEN(dev_priv) >= 4) {
e2f0ba97 1368 /* done in crtc_mode_set as the dpll_md reg must be written early */
50a0bc90 1369 } else if (IS_I945G(dev_priv) || IS_I945GM(dev_priv) ||
73f67aa8 1370 IS_G33(dev_priv) || IS_PINEVIEW(dev_priv)) {
e2f0ba97 1371 /* done in crtc_mode_set as it lives inside the dpll register */
79e53945 1372 } else {
f9fe0530 1373 sdvox |= (crtc_state->pixel_multiplier - 1)
6cc5f341 1374 << SDVO_PORT_MULTIPLY_SHIFT;
79e53945
JB		 1375 }
1376
6714afb1 1377 if (input_dtd.part2.sdvo_flags & SDVO_NEED_TO_STALL &&
66478475 1378 INTEL_GEN(dev_priv) < 5)
12682a97 1379 sdvox |= SDVO_STALL_SELECT;
ea5b213a 1380 intel_sdvo_write_sdvox(intel_sdvo, sdvox);
79e53945
JB		 1381}
1382
4ac41f47 1383static bool intel_sdvo_connector_get_hw_state(struct intel_connector *connector)
79e53945 1384{
4ac41f47
DV		 1385 struct intel_sdvo_connector *intel_sdvo_connector =
1386 to_intel_sdvo_connector(&connector->base);
1387 struct intel_sdvo *intel_sdvo = intel_attached_sdvo(&connector->base);
2f28c50b 1388 u16 active_outputs = 0;
4ac41f47
DV		 1389
1390 intel_sdvo_get_active_outputs(intel_sdvo, &active_outputs);
1391
1392 if (active_outputs & intel_sdvo_connector->output_flag)
1393 return true;
1394 else
1395 return false;
1396}
1397
1398static bool intel_sdvo_get_hw_state(struct intel_encoder *encoder,
1399 enum pipe *pipe)
1400{
1401 struct drm_device *dev = encoder->base.dev;
fac5e23e 1402 struct drm_i915_private *dev_priv = to_i915(dev);
8aca63aa 1403 struct intel_sdvo *intel_sdvo = to_sdvo(encoder);
2f28c50b 1404 u16 active_outputs = 0;
4ac41f47
DV		 1405 u32 tmp;
1406
1407 tmp = I915_READ(intel_sdvo->sdvo_reg);
7a7d1fb7 1408 intel_sdvo_get_active_outputs(intel_sdvo, &active_outputs);
4ac41f47 1409
7a7d1fb7 1410 if (!(tmp & SDVO_ENABLE) && (active_outputs == 0))
4ac41f47
DV		 1411 return false;
1412
6e266956 1413 if (HAS_PCH_CPT(dev_priv))
4ac41f47
DV		 1414 *pipe = PORT_TO_PIPE_CPT(tmp);
1415 else
1416 *pipe = PORT_TO_PIPE(tmp);
1417
1418 return true;
1419}
1420
045ac3b5 1421static void intel_sdvo_get_config(struct intel_encoder *encoder,
5cec258b 1422 struct intel_crtc_state *pipe_config)
045ac3b5 1423{
6c49f241 1424 struct drm_device *dev = encoder->base.dev;
fac5e23e 1425 struct drm_i915_private *dev_priv = to_i915(dev);
8aca63aa 1426 struct intel_sdvo *intel_sdvo = to_sdvo(encoder);
045ac3b5 1427 struct intel_sdvo_dtd dtd;
6c49f241 1428 int encoder_pixel_multiplier = 0;
18442d08 1429 int dotclock;
6c49f241
DV		 1430 u32 flags = 0, sdvox;
1431 u8 val;
045ac3b5
JB		 1432 bool ret;
1433
b5a9fa09
DV		 1434 sdvox = I915_READ(intel_sdvo->sdvo_reg);
1435
045ac3b5
JB		 1436 ret = intel_sdvo_get_input_timing(intel_sdvo, &dtd);
1437 if (!ret) {
bb760063
DV		 1438 /* Some sdvo encoders are not spec compliant and don't
1439 * implement the mandatory get_timings function. */
045ac3b5 1440 DRM_DEBUG_DRIVER("failed to retrieve SDVO DTD\n");
bb760063
DV		 1441 pipe_config->quirks |= PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS;
1442 } else {
1443 if (dtd.part2.dtd_flags & DTD_FLAG_HSYNC_POSITIVE)
1444 flags |= DRM_MODE_FLAG_PHSYNC;
1445 else
1446 flags |= DRM_MODE_FLAG_NHSYNC;
045ac3b5 1447
bb760063
DV		 1448 if (dtd.part2.dtd_flags & DTD_FLAG_VSYNC_POSITIVE)
1449 flags |= DRM_MODE_FLAG_PVSYNC;
1450 else
1451 flags |= DRM_MODE_FLAG_NVSYNC;
045ac3b5
JB		 1452 }
1453
2d112de7 1454 pipe_config->base.adjusted_mode.flags |= flags;
045ac3b5 1455
fdafa9e2
DV		 1456 /*
1457 * pixel multiplier readout is tricky: Only on i915g/gm it is stored in
1458 * the sdvo port register, on all other platforms it is part of the dpll
1459 * state. Since the general pipe state readout happens before the
1460 * encoder->get_config we so already have a valid pixel multplier on all
1461 * other platfroms.
1462 */
50a0bc90 1463 if (IS_I915G(dev_priv) || IS_I915GM(dev_priv)) {
6c49f241
DV		 1464 pipe_config->pixel_multiplier =
1465 ((sdvox & SDVO_PORT_MULTIPLY_MASK)
1466 >> SDVO_PORT_MULTIPLY_SHIFT) + 1;
1467 }
045ac3b5 1468
2b85886a 1469 dotclock = pipe_config->port_clock;
e3b247da 1470
2b85886a
VS		 1471 if (pipe_config->pixel_multiplier)
1472 dotclock /= pipe_config->pixel_multiplier;
18442d08 1473
2d112de7 1474 pipe_config->base.adjusted_mode.crtc_clock = dotclock;
18442d08 1475
6c49f241 1476 /* Cross check the port pixel multiplier with the sdvo encoder state. */
53b91408
DL		 1477 if (intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_CLOCK_RATE_MULT,
1478 &val, 1)) {
1479 switch (val) {
1480 case SDVO_CLOCK_RATE_MULT_1X:
1481 encoder_pixel_multiplier = 1;
1482 break;
1483 case SDVO_CLOCK_RATE_MULT_2X:
1484 encoder_pixel_multiplier = 2;
1485 break;
1486 case SDVO_CLOCK_RATE_MULT_4X:
1487 encoder_pixel_multiplier = 4;
1488 break;
1489 }
6c49f241 1490 }
fdafa9e2 1491
b5a9fa09
DV		 1492 if (sdvox & HDMI_COLOR_RANGE_16_235)
1493 pipe_config->limited_color_range = true;
1494
de44e256
DV		 1495 if (sdvox & SDVO_AUDIO_ENABLE)
1496 pipe_config->has_audio = true;
1497
9f04003e
DV		 1498 if (intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_ENCODE,
1499 &val, 1)) {
1500 if (val == SDVO_ENCODE_HDMI)
1501 pipe_config->has_hdmi_sink = true;
1502 }
1503
6c49f241
DV		 1504 WARN(encoder_pixel_multiplier != pipe_config->pixel_multiplier,
1505 "SDVO pixel multiplier mismatch, port: %i, encoder: %i\n",
1506 pipe_config->pixel_multiplier, encoder_pixel_multiplier);
045ac3b5
JB		 1507}
1508
fd6bbda9
ML		 1509static void intel_disable_sdvo(struct intel_encoder *encoder,
1510 struct intel_crtc_state *old_crtc_state,
1511 struct drm_connector_state *conn_state)
ce22c320 1512{
fac5e23e 1513 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
8aca63aa 1514 struct intel_sdvo *intel_sdvo = to_sdvo(encoder);
1612c8bd 1515 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
ce22c320
DV		 1516 u32 temp;
1517
1518 intel_sdvo_set_active_outputs(intel_sdvo, 0);
1519 if (0)
1520 intel_sdvo_set_encoder_power_state(intel_sdvo,
1521 DRM_MODE_DPMS_OFF);
1522
1523 temp = I915_READ(intel_sdvo->sdvo_reg);
776ca7cf 1524
1612c8bd
VS		 1525 temp &= ~SDVO_ENABLE;
1526 intel_sdvo_write_sdvox(intel_sdvo, temp);
1527
1528 /*
1529 * HW workaround for IBX, we need to move the port
1530 * to transcoder A after disabling it to allow the
1531 * matching DP port to be enabled on transcoder A.
1532 */
1533 if (HAS_PCH_IBX(dev_priv) && crtc->pipe == PIPE_B) {
0c241d5b
VS		 1534 /*
1535 * We get CPU/PCH FIFO underruns on the other pipe when
1536 * doing the workaround. Sweep them under the rug.
1537 */
1538 intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, false);
1539 intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, false);
1540
1612c8bd
VS		 1541 temp &= ~SDVO_PIPE_B_SELECT;
1542 temp |= SDVO_ENABLE;
1543 intel_sdvo_write_sdvox(intel_sdvo, temp);
1544
1545 temp &= ~SDVO_ENABLE;
1546 intel_sdvo_write_sdvox(intel_sdvo, temp);
0c241d5b 1547
0f0f74bc 1548 intel_wait_for_vblank_if_active(dev_priv, PIPE_A);
0c241d5b
VS		 1549 intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, true);
1550 intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, true);
ce22c320
DV		 1551 }
1552}
1553
fd6bbda9
ML		 1554static void pch_disable_sdvo(struct intel_encoder *encoder,
1555 struct intel_crtc_state *old_crtc_state,
1556 struct drm_connector_state *old_conn_state)
3c65d1d1
VS		 1557{
1558}
1559
fd6bbda9
ML		 1560static void pch_post_disable_sdvo(struct intel_encoder *encoder,
1561 struct intel_crtc_state *old_crtc_state,
1562 struct drm_connector_state *old_conn_state)
3c65d1d1 1563{
fd6bbda9 1564 intel_disable_sdvo(encoder, old_crtc_state, old_conn_state);
3c65d1d1
VS		 1565}
1566
fd6bbda9
ML		 1567static void intel_enable_sdvo(struct intel_encoder *encoder,
1568 struct intel_crtc_state *pipe_config,
1569 struct drm_connector_state *conn_state)
ce22c320
DV		 1570{
1571 struct drm_device *dev = encoder->base.dev;
fac5e23e 1572 struct drm_i915_private *dev_priv = to_i915(dev);
8aca63aa 1573 struct intel_sdvo *intel_sdvo = to_sdvo(encoder);
ce22c320 1574 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
79e53945 1575 u32 temp;
ce22c320
DV		 1576 bool input1, input2;
1577 int i;
d0a7b6de 1578 bool success;
ce22c320
DV		 1579
1580 temp = I915_READ(intel_sdvo->sdvo_reg);
3c65d1d1
VS		 1581 temp |= SDVO_ENABLE;
1582 intel_sdvo_write_sdvox(intel_sdvo, temp);
776ca7cf 1583
ce22c320 1584 for (i = 0; i < 2; i++)
0f0f74bc 1585 intel_wait_for_vblank(dev_priv, intel_crtc->pipe);
ce22c320 1586
d0a7b6de 1587 success = intel_sdvo_get_trained_inputs(intel_sdvo, &input1, &input2);
ce22c320
DV		 1588 /* Warn if the device reported failure to sync.
1589 * A lot of SDVO devices fail to notify of sync, but it's
1590 * a given it the status is a success, we succeeded.
1591 */
d0a7b6de 1592 if (success && !input1) {
ce22c320
DV		 1593 DRM_DEBUG_KMS("First %s output reported failure to "
1594 "sync\n", SDVO_NAME(intel_sdvo));
1595 }
1596
1597 if (0)
1598 intel_sdvo_set_encoder_power_state(intel_sdvo,
1599 DRM_MODE_DPMS_ON);
1600 intel_sdvo_set_active_outputs(intel_sdvo, intel_sdvo->attached_output);
1601}
1602
c19de8eb
DL		 1603static enum drm_mode_status
1604intel_sdvo_mode_valid(struct drm_connector *connector,
1605 struct drm_display_mode *mode)
79e53945 1606{
df0e9248 1607 struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector);
24b23882 1608 int max_dotclk = to_i915(connector->dev)->max_dotclk_freq;
79e53945
JB		 1609
1610 if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
1611 return MODE_NO_DBLESCAN;
1612
ea5b213a 1613 if (intel_sdvo->pixel_clock_min > mode->clock)
79e53945
JB		 1614 return MODE_CLOCK_LOW;
1615
ea5b213a 1616 if (intel_sdvo->pixel_clock_max < mode->clock)
79e53945
JB		 1617 return MODE_CLOCK_HIGH;
1618
24b23882
MK		 1619 if (mode->clock > max_dotclk)
1620 return MODE_CLOCK_HIGH;
1621
8545423a 1622 if (intel_sdvo->is_lvds) {
ea5b213a 1623 if (mode->hdisplay > intel_sdvo->sdvo_lvds_fixed_mode->hdisplay)
12682a97 1624 return MODE_PANEL;
1625
ea5b213a 1626 if (mode->vdisplay > intel_sdvo->sdvo_lvds_fixed_mode->vdisplay)
12682a97 1627 return MODE_PANEL;
1628 }
1629
79e53945
JB		 1630 return MODE_OK;
1631}
1632
ea5b213a 1633static bool intel_sdvo_get_capabilities(struct intel_sdvo *intel_sdvo, struct intel_sdvo_caps *caps)
79e53945 1634{
1a3665c8 1635 BUILD_BUG_ON(sizeof(*caps) != 8);
e957d772
CW		 1636 if (!intel_sdvo_get_value(intel_sdvo,
1637 SDVO_CMD_GET_DEVICE_CAPS,
1638 caps, sizeof(*caps)))
1639 return false;
1640
1641 DRM_DEBUG_KMS("SDVO capabilities:\n"
1642 " vendor_id: %d\n"
1643 " device_id: %d\n"
1644 " device_rev_id: %d\n"
1645 " sdvo_version_major: %d\n"
1646 " sdvo_version_minor: %d\n"
1647 " sdvo_inputs_mask: %d\n"
1648 " smooth_scaling: %d\n"
1649 " sharp_scaling: %d\n"
1650 " up_scaling: %d\n"
1651 " down_scaling: %d\n"
1652 " stall_support: %d\n"
1653 " output_flags: %d\n",
1654 caps->vendor_id,
1655 caps->device_id,
1656 caps->device_rev_id,
1657 caps->sdvo_version_major,
1658 caps->sdvo_version_minor,
1659 caps->sdvo_inputs_mask,
1660 caps->smooth_scaling,
1661 caps->sharp_scaling,
1662 caps->up_scaling,
1663 caps->down_scaling,
1664 caps->stall_support,
1665 caps->output_flags);
1666
1667 return true;
79e53945
JB		 1668}
1669
5fa7ac9c 1670static uint16_t intel_sdvo_get_hotplug_support(struct intel_sdvo *intel_sdvo)
79e53945 1671{
50a0bc90 1672 struct drm_i915_private *dev_priv = to_i915(intel_sdvo->base.base.dev);
5fa7ac9c 1673 uint16_t hotplug;
79e53945 1674
50a0bc90 1675 if (!I915_HAS_HOTPLUG(dev_priv))
1d83d957
VS		 1676 return 0;
1677
768b107e
DV		 1678 /* HW Erratum: SDVO Hotplug is broken on all i945G chips, there's noise
1679 * on the line. */
50a0bc90 1680 if (IS_I945G(dev_priv) || IS_I945GM(dev_priv))
5fa7ac9c 1681 return 0;
768b107e 1682
5fa7ac9c
JN		 1683 if (!intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_HOT_PLUG_SUPPORT,
1684 &hotplug, sizeof(hotplug)))
1685 return 0;
768b107e 1686
5fa7ac9c 1687 return hotplug;
79e53945
JB		 1688}
1689
cc68c81a 1690static void intel_sdvo_enable_hotplug(struct intel_encoder *encoder)
79e53945 1691{
8aca63aa 1692 struct intel_sdvo *intel_sdvo = to_sdvo(encoder);
79e53945 1693
5fa7ac9c
JN		 1694 intel_sdvo_write_cmd(intel_sdvo, SDVO_CMD_SET_ACTIVE_HOT_PLUG,
1695 &intel_sdvo->hotplug_active, 2);
79e53945
JB		 1696}
1697
fb7a46f3 1698static bool
ea5b213a 1699intel_sdvo_multifunc_encoder(struct intel_sdvo *intel_sdvo)
fb7a46f3 1700{
bc65212c 1701 /* Is there more than one type of output? */
2294488d 1702 return hweight16(intel_sdvo->caps.output_flags) > 1;
fb7a46f3 1703}
1704
f899fc64 1705static struct edid *
e957d772 1706intel_sdvo_get_edid(struct drm_connector *connector)
f899fc64 1707{
e957d772
CW		 1708 struct intel_sdvo *sdvo = intel_attached_sdvo(connector);
1709 return drm_get_edid(connector, &sdvo->ddc);
f899fc64
CW		 1710}
1711
ff482d83
CW		 1712/* Mac mini hack -- use the same DDC as the analog connector */
1713static struct edid *
1714intel_sdvo_get_analog_edid(struct drm_connector *connector)
1715{
fac5e23e 1716 struct drm_i915_private *dev_priv = to_i915(connector->dev);
ff482d83 1717
0c1dab89 1718 return drm_get_edid(connector,
3bd7d909 1719 intel_gmbus_get_adapter(dev_priv,
41aa3448 1720 dev_priv->vbt.crt_ddc_pin));
ff482d83
CW		 1721}
1722
c43b5634 1723static enum drm_connector_status
8bf38485 1724intel_sdvo_tmds_sink_detect(struct drm_connector *connector)
9dff6af8 1725{
df0e9248 1726 struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector);
9d1a903d
CW		 1727 enum drm_connector_status status;
1728 struct edid *edid;
9dff6af8 1729
e957d772 1730 edid = intel_sdvo_get_edid(connector);
57cdaf90 1731
ea5b213a 1732 if (edid == NULL && intel_sdvo_multifunc_encoder(intel_sdvo)) {
e957d772 1733 u8 ddc, saved_ddc = intel_sdvo->ddc_bus;
9d1a903d 1734
7c3f0a27
ZY		 1735 /*
1736 * Don't use the 1 as the argument of DDC bus switch to get
1737 * the EDID. It is used for SDVO SPD ROM.
1738 */
9d1a903d 1739 for (ddc = intel_sdvo->ddc_bus >> 1; ddc > 1; ddc >>= 1) {
e957d772
CW		 1740 intel_sdvo->ddc_bus = ddc;
1741 edid = intel_sdvo_get_edid(connector);
1742 if (edid)
7c3f0a27 1743 break;
7c3f0a27 1744 }
e957d772
CW		 1745 /*
1746 * If we found the EDID on the other bus,
1747 * assume that is the correct DDC bus.
1748 */
1749 if (edid == NULL)
1750 intel_sdvo->ddc_bus = saved_ddc;
7c3f0a27 1751 }
9d1a903d
CW		 1752
1753 /*
1754 * When there is no edid and no monitor is connected with VGA
1755 * port, try to use the CRT ddc to read the EDID for DVI-connector.
57cdaf90 1756 */
ff482d83
CW		 1757 if (edid == NULL)
1758 edid = intel_sdvo_get_analog_edid(connector);
149c36a3 1759
2f551c84 1760 status = connector_status_unknown;
9dff6af8 1761 if (edid != NULL) {
149c36a3 1762 /* DDC bus is shared, match EDID to connector type */
9d1a903d
CW		 1763 if (edid->input & DRM_EDID_INPUT_DIGITAL) {
1764 status = connector_status_connected;
da79de97
CW		 1765 if (intel_sdvo->is_hdmi) {
1766 intel_sdvo->has_hdmi_monitor = drm_detect_hdmi_monitor(edid);
1767 intel_sdvo->has_hdmi_audio = drm_detect_monitor_audio(edid);
abedc077
VS		 1768 intel_sdvo->rgb_quant_range_selectable =
1769 drm_rgb_quant_range_selectable(edid);
da79de97 1770 }
13946743
CW		 1771 } else
1772 status = connector_status_disconnected;
9d1a903d
CW		 1773 kfree(edid);
1774 }
7f36e7ed 1775
2b8d33f7 1776 return status;
9dff6af8
ML		 1777}
1778
52220085
CW		 1779static bool
1780intel_sdvo_connector_matches_edid(struct intel_sdvo_connector *sdvo,
1781 struct edid *edid)
1782{
1783 bool monitor_is_digital = !!(edid->input & DRM_EDID_INPUT_DIGITAL);
1784 bool connector_is_digital = !!IS_DIGITAL(sdvo);
1785
1786 DRM_DEBUG_KMS("connector_is_digital? %d, monitor_is_digital? %d\n",
1787 connector_is_digital, monitor_is_digital);
1788 return connector_is_digital == monitor_is_digital;
1789}
1790
7b334fcb 1791static enum drm_connector_status
930a9e28 1792intel_sdvo_detect(struct drm_connector *connector, bool force)
79e53945 1793{
fb7a46f3 1794 uint16_t response;
df0e9248 1795 struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector);
615fb93f 1796 struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector);
14571b4c 1797 enum drm_connector_status ret;
79e53945 1798
164c8598 1799 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
c23cc417 1800 connector->base.id, connector->name);
164c8598 1801
fc37381c
CW		 1802 if (!intel_sdvo_get_value(intel_sdvo,
1803 SDVO_CMD_GET_ATTACHED_DISPLAYS,
1804 &response, 2))
32aad86f 1805 return connector_status_unknown;
79e53945 1806
e957d772
CW		 1807 DRM_DEBUG_KMS("SDVO response %d %d [%x]\n",
1808 response & 0xff, response >> 8,
1809 intel_sdvo_connector->output_flag);
e2f0ba97 1810
fb7a46f3 1811 if (response == 0)
79e53945 1812 return connector_status_disconnected;
fb7a46f3 1813
ea5b213a 1814 intel_sdvo->attached_output = response;
14571b4c 1815
97aaf910
CW		 1816 intel_sdvo->has_hdmi_monitor = false;
1817 intel_sdvo->has_hdmi_audio = false;
abedc077 1818 intel_sdvo->rgb_quant_range_selectable = false;
97aaf910 1819
615fb93f 1820 if ((intel_sdvo_connector->output_flag & response) == 0)
14571b4c 1821 ret = connector_status_disconnected;
13946743 1822 else if (IS_TMDS(intel_sdvo_connector))
8bf38485 1823 ret = intel_sdvo_tmds_sink_detect(connector);
13946743
CW		 1824 else {
1825 struct edid *edid;
1826
1827 /* if we have an edid check it matches the connection */
1828 edid = intel_sdvo_get_edid(connector);
1829 if (edid == NULL)
1830 edid = intel_sdvo_get_analog_edid(connector);
1831 if (edid != NULL) {
52220085
CW		 1832 if (intel_sdvo_connector_matches_edid(intel_sdvo_connector,
1833 edid))
13946743 1834 ret = connector_status_connected;
52220085
CW		 1835 else
1836 ret = connector_status_disconnected;
1837
13946743
CW		 1838 kfree(edid);
1839 } else
1840 ret = connector_status_connected;
1841 }
14571b4c
ZW		 1842
1843 /* May update encoder flag for like clock for SDVO TV, etc.*/
1844 if (ret == connector_status_connected) {
ea5b213a
CW		 1845 intel_sdvo->is_tv = false;
1846 intel_sdvo->is_lvds = false;
14571b4c 1847
09ede541 1848 if (response & SDVO_TV_MASK)
ea5b213a 1849 intel_sdvo->is_tv = true;
14571b4c 1850 if (response & SDVO_LVDS_MASK)
8545423a 1851 intel_sdvo->is_lvds = intel_sdvo->sdvo_lvds_fixed_mode != NULL;
fb7a46f3 1852 }
14571b4c
ZW		 1853
1854 return ret;
79e53945
JB		 1855}
1856
e2f0ba97 1857static void intel_sdvo_get_ddc_modes(struct drm_connector *connector)
79e53945 1858{
ff482d83 1859 struct edid *edid;
79e53945 1860
46a3f4a3 1861 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
c23cc417 1862 connector->base.id, connector->name);
46a3f4a3 1863
79e53945 1864 /* set the bus switch and get the modes */
e957d772 1865 edid = intel_sdvo_get_edid(connector);
79e53945 1866
57cdaf90
KP		 1867 /*
1868 * Mac mini hack. On this device, the DVI-I connector shares one DDC
1869 * link between analog and digital outputs. So, if the regular SDVO
1870 * DDC fails, check to see if the analog output is disconnected, in
1871 * which case we'll look there for the digital DDC data.
e2f0ba97 1872 */
f899fc64
CW		 1873 if (edid == NULL)
1874 edid = intel_sdvo_get_analog_edid(connector);
1875
ff482d83 1876 if (edid != NULL) {
52220085
CW		 1877 if (intel_sdvo_connector_matches_edid(to_intel_sdvo_connector(connector),
1878 edid)) {
0c1dab89
CW		 1879 drm_mode_connector_update_edid_property(connector, edid);
1880 drm_add_edid_modes(connector, edid);
1881 }
13946743 1882
ff482d83 1883 kfree(edid);
e2f0ba97 1884 }
e2f0ba97
JB		 1885}
1886
1887/*
1888 * Set of SDVO TV modes.
1889 * Note! This is in reply order (see loop in get_tv_modes).
1890 * XXX: all 60Hz refresh?
1891 */
b1f559ec 1892static const struct drm_display_mode sdvo_tv_modes[] = {
7026d4ac
ZW		 1893 { DRM_MODE("320x200", DRM_MODE_TYPE_DRIVER, 5815, 320, 321, 384,
1894 416, 0, 200, 201, 232, 233, 0,
e2f0ba97 1895 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1896 { DRM_MODE("320x240", DRM_MODE_TYPE_DRIVER, 6814, 320, 321, 384,
1897 416, 0, 240, 241, 272, 273, 0,
e2f0ba97 1898 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1899 { DRM_MODE("400x300", DRM_MODE_TYPE_DRIVER, 9910, 400, 401, 464,
1900 496, 0, 300, 301, 332, 333, 0,
e2f0ba97 1901 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1902 { DRM_MODE("640x350", DRM_MODE_TYPE_DRIVER, 16913, 640, 641, 704,
1903 736, 0, 350, 351, 382, 383, 0,
e2f0ba97 1904 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1905 { DRM_MODE("640x400", DRM_MODE_TYPE_DRIVER, 19121, 640, 641, 704,
1906 736, 0, 400, 401, 432, 433, 0,
e2f0ba97 1907 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1908 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 22654, 640, 641, 704,
1909 736, 0, 480, 481, 512, 513, 0,
e2f0ba97 1910 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1911 { DRM_MODE("704x480", DRM_MODE_TYPE_DRIVER, 24624, 704, 705, 768,
1912 800, 0, 480, 481, 512, 513, 0,
e2f0ba97 1913 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1914 { DRM_MODE("704x576", DRM_MODE_TYPE_DRIVER, 29232, 704, 705, 768,
1915 800, 0, 576, 577, 608, 609, 0,
e2f0ba97 1916 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1917 { DRM_MODE("720x350", DRM_MODE_TYPE_DRIVER, 18751, 720, 721, 784,
1918 816, 0, 350, 351, 382, 383, 0,
e2f0ba97 1919 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1920 { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 21199, 720, 721, 784,
1921 816, 0, 400, 401, 432, 433, 0,
e2f0ba97 1922 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1923 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 25116, 720, 721, 784,
1924 816, 0, 480, 481, 512, 513, 0,
e2f0ba97 1925 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1926 { DRM_MODE("720x540", DRM_MODE_TYPE_DRIVER, 28054, 720, 721, 784,
1927 816, 0, 540, 541, 572, 573, 0,
e2f0ba97 1928 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1929 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 29816, 720, 721, 784,
1930 816, 0, 576, 577, 608, 609, 0,
e2f0ba97 1931 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1932 { DRM_MODE("768x576", DRM_MODE_TYPE_DRIVER, 31570, 768, 769, 832,
1933 864, 0, 576, 577, 608, 609, 0,
e2f0ba97 1934 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1935 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 34030, 800, 801, 864,
1936 896, 0, 600, 601, 632, 633, 0,
e2f0ba97 1937 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1938 { DRM_MODE("832x624", DRM_MODE_TYPE_DRIVER, 36581, 832, 833, 896,
1939 928, 0, 624, 625, 656, 657, 0,
e2f0ba97 1940 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1941 { DRM_MODE("920x766", DRM_MODE_TYPE_DRIVER, 48707, 920, 921, 984,
1942 1016, 0, 766, 767, 798, 799, 0,
e2f0ba97 1943 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1944 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 53827, 1024, 1025, 1088,
1945 1120, 0, 768, 769, 800, 801, 0,
e2f0ba97 1946 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1947 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 87265, 1280, 1281, 1344,
1948 1376, 0, 1024, 1025, 1056, 1057, 0,
e2f0ba97
JB		 1949 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1950};
1951
1952static void intel_sdvo_get_tv_modes(struct drm_connector *connector)
1953{
df0e9248 1954 struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector);
630d30a4 1955 const struct drm_connector_state *conn_state = connector->state;
7026d4ac 1956 struct intel_sdvo_sdtv_resolution_request tv_res;
ce6feabd
ZY		 1957 uint32_t reply = 0, format_map = 0;
1958 int i;
e2f0ba97 1959
46a3f4a3 1960 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
c23cc417 1961 connector->base.id, connector->name);
46a3f4a3 1962
e2f0ba97
JB		 1963 /* Read the list of supported input resolutions for the selected TV
1964 * format.
1965 */
630d30a4 1966 format_map = 1 << conn_state->tv.mode;
ce6feabd 1967 memcpy(&tv_res, &format_map,
32aad86f 1968 min(sizeof(format_map), sizeof(struct intel_sdvo_sdtv_resolution_request)));
ce6feabd 1969
32aad86f
CW		 1970 if (!intel_sdvo_set_target_output(intel_sdvo, intel_sdvo->attached_output))
1971 return;
ce6feabd 1972
32aad86f 1973 BUILD_BUG_ON(sizeof(tv_res) != 3);
e957d772
CW		 1974 if (!intel_sdvo_write_cmd(intel_sdvo,
1975 SDVO_CMD_GET_SDTV_RESOLUTION_SUPPORT,
32aad86f
CW		 1976 &tv_res, sizeof(tv_res)))
1977 return;
1978 if (!intel_sdvo_read_response(intel_sdvo, &reply, 3))
e2f0ba97
JB		 1979 return;
1980
1981 for (i = 0; i < ARRAY_SIZE(sdvo_tv_modes); i++)
7026d4ac
ZW		 1982 if (reply & (1 << i)) {
1983 struct drm_display_mode *nmode;
1984 nmode = drm_mode_duplicate(connector->dev,
32aad86f 1985 &sdvo_tv_modes[i]);
7026d4ac
ZW		 1986 if (nmode)
1987 drm_mode_probed_add(connector, nmode);
1988 }
e2f0ba97
JB		 1989}
1990
7086c87f
ML		 1991static void intel_sdvo_get_lvds_modes(struct drm_connector *connector)
1992{
df0e9248 1993 struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector);
fac5e23e 1994 struct drm_i915_private *dev_priv = to_i915(connector->dev);
12682a97 1995 struct drm_display_mode *newmode;
7086c87f 1996
46a3f4a3 1997 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
c23cc417 1998 connector->base.id, connector->name);
46a3f4a3 1999
7086c87f 2000 /*
c3456fb3 2001 * Fetch modes from VBT. For SDVO prefer the VBT mode since some
4300a0f8 2002 * SDVO->LVDS transcoders can't cope with the EDID mode.
7086c87f 2003 */
41aa3448 2004 if (dev_priv->vbt.sdvo_lvds_vbt_mode != NULL) {
7086c87f 2005 newmode = drm_mode_duplicate(connector->dev,
41aa3448 2006 dev_priv->vbt.sdvo_lvds_vbt_mode);
7086c87f
ML		 2007 if (newmode != NULL) {
2008 /* Guarantee the mode is preferred */
2009 newmode->type = (DRM_MODE_TYPE_PREFERRED |
2010 DRM_MODE_TYPE_DRIVER);
2011 drm_mode_probed_add(connector, newmode);
2012 }
2013 }
12682a97 2014
4300a0f8
DA		 2015 /*
2016 * Attempt to get the mode list from DDC.
2017 * Assume that the preferred modes are
2018 * arranged in priority order.
2019 */
2020 intel_ddc_get_modes(connector, &intel_sdvo->ddc);
2021
12682a97 2022 list_for_each_entry(newmode, &connector->probed_modes, head) {
2023 if (newmode->type & DRM_MODE_TYPE_PREFERRED) {
ea5b213a 2024 intel_sdvo->sdvo_lvds_fixed_mode =
12682a97 2025 drm_mode_duplicate(connector->dev, newmode);
6c9547ff 2026
8545423a 2027 intel_sdvo->is_lvds = true;
12682a97 2028 break;
2029 }
2030 }
7086c87f
ML		 2031}
2032
e2f0ba97
JB		 2033static int intel_sdvo_get_modes(struct drm_connector *connector)
2034{
615fb93f 2035 struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector);
e2f0ba97 2036
615fb93f 2037 if (IS_TV(intel_sdvo_connector))
e2f0ba97 2038 intel_sdvo_get_tv_modes(connector);
615fb93f 2039 else if (IS_LVDS(intel_sdvo_connector))
7086c87f 2040 intel_sdvo_get_lvds_modes(connector);
e2f0ba97
JB		 2041 else
2042 intel_sdvo_get_ddc_modes(connector);
2043
32aad86f 2044 return !list_empty(&connector->probed_modes);
79e53945
JB		 2045}
2046
2047static void intel_sdvo_destroy(struct drm_connector *connector)
2048{
615fb93f 2049 struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector);
79e53945 2050
79e53945 2051 drm_connector_cleanup(connector);
4b745b1e 2052 kfree(intel_sdvo_connector);
79e53945
JB		 2053}
2054
ce6feabd 2055static int
630d30a4
ML		 2056intel_sdvo_connector_atomic_get_property(struct drm_connector *connector,
2057 const struct drm_connector_state *state,
2058 struct drm_property *property,
2059 uint64_t *val)
ce6feabd 2060{
615fb93f 2061 struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector);
630d30a4 2062 const struct intel_sdvo_connector_state *sdvo_state = to_intel_sdvo_connector_state((void *)state);
c5521706
CW		 2063
2064 if (property == intel_sdvo_connector->tv_format) {
630d30a4 2065 int i;
b9219c5e 2066
630d30a4
ML		 2067 for (i = 0; i < intel_sdvo_connector->format_supported_num; i++)
2068 if (state->tv.mode == intel_sdvo_connector->tv_format_supported[i]) {
2069 *val = i;
b9219c5e 2070
32aad86f 2071 return 0;
630d30a4 2072 }
b9219c5e 2073
630d30a4
ML		 2074 WARN_ON(1);
2075 *val = 0;
2076 } else if (property == intel_sdvo_connector->top ||
2077 property == intel_sdvo_connector->bottom)
2078 *val = intel_sdvo_connector->max_vscan - sdvo_state->tv.overscan_v;
2079 else if (property == intel_sdvo_connector->left ||
2080 property == intel_sdvo_connector->right)
2081 *val = intel_sdvo_connector->max_hscan - sdvo_state->tv.overscan_h;
2082 else if (property == intel_sdvo_connector->hpos)
2083 *val = sdvo_state->tv.hpos;
2084 else if (property == intel_sdvo_connector->vpos)
2085 *val = sdvo_state->tv.vpos;
2086 else if (property == intel_sdvo_connector->saturation)
2087 *val = state->tv.saturation;
2088 else if (property == intel_sdvo_connector->contrast)
2089 *val = state->tv.contrast;
2090 else if (property == intel_sdvo_connector->hue)
2091 *val = state->tv.hue;
2092 else if (property == intel_sdvo_connector->brightness)
2093 *val = state->tv.brightness;
2094 else if (property == intel_sdvo_connector->sharpness)
2095 *val = sdvo_state->tv.sharpness;
2096 else if (property == intel_sdvo_connector->flicker_filter)
2097 *val = sdvo_state->tv.flicker_filter;
2098 else if (property == intel_sdvo_connector->flicker_filter_2d)
2099 *val = sdvo_state->tv.flicker_filter_2d;
2100 else if (property == intel_sdvo_connector->flicker_filter_adaptive)
2101 *val = sdvo_state->tv.flicker_filter_adaptive;
2102 else if (property == intel_sdvo_connector->tv_chroma_filter)
2103 *val = sdvo_state->tv.chroma_filter;
2104 else if (property == intel_sdvo_connector->tv_luma_filter)
2105 *val = sdvo_state->tv.luma_filter;
2106 else if (property == intel_sdvo_connector->dot_crawl)
2107 *val = sdvo_state->tv.dot_crawl;
2108 else
2109 return intel_digital_connector_atomic_get_property(connector, state, property, val);
32aad86f 2110
630d30a4
ML		 2111 return 0;
2112}
b9219c5e 2113
630d30a4
ML		 2114static int
2115intel_sdvo_connector_atomic_set_property(struct drm_connector *connector,
2116 struct drm_connector_state *state,
2117 struct drm_property *property,
2118 uint64_t val)
2119{
2120 struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector);
2121 struct intel_sdvo_connector_state *sdvo_state = to_intel_sdvo_connector_state(state);
b9219c5e 2122
630d30a4
ML		 2123 if (property == intel_sdvo_connector->tv_format) {
2124 state->tv.mode = intel_sdvo_connector->tv_format_supported[val];
b9219c5e 2125
630d30a4
ML		 2126 if (state->crtc) {
2127 struct drm_crtc_state *crtc_state =
2128 drm_atomic_get_new_crtc_state(state->state, state->crtc);
b9219c5e 2129
630d30a4
ML		 2130 crtc_state->connectors_changed = true;
2131 }
2132 } else if (property == intel_sdvo_connector->top ||
2133 property == intel_sdvo_connector->bottom)
2134 /* Cannot set these independent from each other */
2135 sdvo_state->tv.overscan_v = intel_sdvo_connector->max_vscan - val;
2136 else if (property == intel_sdvo_connector->left ||
2137 property == intel_sdvo_connector->right)
2138 /* Cannot set these independent from each other */
2139 sdvo_state->tv.overscan_h = intel_sdvo_connector->max_hscan - val;
2140 else if (property == intel_sdvo_connector->hpos)
2141 sdvo_state->tv.hpos = val;
2142 else if (property == intel_sdvo_connector->vpos)
2143 sdvo_state->tv.vpos = val;
2144 else if (property == intel_sdvo_connector->saturation)
2145 state->tv.saturation = val;
2146 else if (property == intel_sdvo_connector->contrast)
2147 state->tv.contrast = val;
2148 else if (property == intel_sdvo_connector->hue)
2149 state->tv.hue = val;
2150 else if (property == intel_sdvo_connector->brightness)
2151 state->tv.brightness = val;
2152 else if (property == intel_sdvo_connector->sharpness)
2153 sdvo_state->tv.sharpness = val;
2154 else if (property == intel_sdvo_connector->flicker_filter)
2155 sdvo_state->tv.flicker_filter = val;
2156 else if (property == intel_sdvo_connector->flicker_filter_2d)
2157 sdvo_state->tv.flicker_filter_2d = val;
2158 else if (property == intel_sdvo_connector->flicker_filter_adaptive)
2159 sdvo_state->tv.flicker_filter_adaptive = val;
2160 else if (property == intel_sdvo_connector->tv_chroma_filter)
2161 sdvo_state->tv.chroma_filter = val;
2162 else if (property == intel_sdvo_connector->tv_luma_filter)
2163 sdvo_state->tv.luma_filter = val;
2164 else if (property == intel_sdvo_connector->dot_crawl)
2165 sdvo_state->tv.dot_crawl = val;
2166 else
2167 return intel_digital_connector_atomic_set_property(connector, state, property, val);
c5521706 2168
32aad86f 2169 return 0;
ce6feabd
ZY		 2170}
2171
7a418e34
CW		 2172static int
2173intel_sdvo_connector_register(struct drm_connector *connector)
2174{
2175 struct intel_sdvo *sdvo = intel_attached_sdvo(connector);
1ebaa0b9
CW		 2176 int ret;
2177
2178 ret = intel_connector_register(connector);
2179 if (ret)
2180 return ret;
7a418e34
CW		 2181
2182 return sysfs_create_link(&connector->kdev->kobj,
2183 &sdvo->ddc.dev.kobj,
2184 sdvo->ddc.dev.kobj.name);
2185}
2186
c191eca1
CW		 2187static void
2188intel_sdvo_connector_unregister(struct drm_connector *connector)
2189{
2190 struct intel_sdvo *sdvo = intel_attached_sdvo(connector);
2191
2192 sysfs_remove_link(&connector->kdev->kobj,
2193 sdvo->ddc.dev.kobj.name);
2194 intel_connector_unregister(connector);
2195}
2196
630d30a4
ML		 2197static struct drm_connector_state *
2198intel_sdvo_connector_duplicate_state(struct drm_connector *connector)
2199{
2200 struct intel_sdvo_connector_state *state;
2201
2202 state = kmemdup(connector->state, sizeof(*state), GFP_KERNEL);
2203 if (!state)
2204 return NULL;
2205
2206 __drm_atomic_helper_connector_duplicate_state(connector, &state->base.base);
2207 return &state->base.base;
2208}
2209
79e53945 2210static const struct drm_connector_funcs intel_sdvo_connector_funcs = {
4d688a2a 2211 .dpms = drm_atomic_helper_connector_dpms,
79e53945
JB		 2212 .detect = intel_sdvo_detect,
2213 .fill_modes = drm_helper_probe_single_connector_modes,
630d30a4
ML		 2214 .set_property = drm_atomic_helper_connector_set_property,
2215 .atomic_get_property = intel_sdvo_connector_atomic_get_property,
2216 .atomic_set_property = intel_sdvo_connector_atomic_set_property,
7a418e34 2217 .late_register = intel_sdvo_connector_register,
c191eca1 2218 .early_unregister = intel_sdvo_connector_unregister,
79e53945 2219 .destroy = intel_sdvo_destroy,
c6f95f27 2220 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
630d30a4 2221 .atomic_duplicate_state = intel_sdvo_connector_duplicate_state,
79e53945
JB		 2222};
2223
630d30a4
ML		 2224static int intel_sdvo_atomic_check(struct drm_connector *conn,
2225 struct drm_connector_state *new_conn_state)
2226{
2227 struct drm_atomic_state *state = new_conn_state->state;
2228 struct drm_connector_state *old_conn_state =
2229 drm_atomic_get_old_connector_state(state, conn);
2230 struct intel_sdvo_connector_state *old_state =
2231 to_intel_sdvo_connector_state(old_conn_state);
2232 struct intel_sdvo_connector_state *new_state =
2233 to_intel_sdvo_connector_state(new_conn_state);
2234
2235 if (new_conn_state->crtc &&
2236 (memcmp(&old_state->tv, &new_state->tv, sizeof(old_state->tv)) ||
2237 memcmp(&old_conn_state->tv, &new_conn_state->tv, sizeof(old_conn_state->tv)))) {
2238 struct drm_crtc_state *crtc_state =
2239 drm_atomic_get_new_crtc_state(new_conn_state->state,
2240 new_conn_state->crtc);
2241
2242 crtc_state->connectors_changed = true;
2243 }
2244
2245 return intel_digital_connector_atomic_check(conn, new_conn_state);
2246}
2247
79e53945
JB		 2248static const struct drm_connector_helper_funcs intel_sdvo_connector_helper_funcs = {
2249 .get_modes = intel_sdvo_get_modes,
2250 .mode_valid = intel_sdvo_mode_valid,
630d30a4 2251 .atomic_check = intel_sdvo_atomic_check,
79e53945
JB		 2252};
2253
b358d0a6 2254static void intel_sdvo_enc_destroy(struct drm_encoder *encoder)
79e53945 2255{
8aca63aa 2256 struct intel_sdvo *intel_sdvo = to_sdvo(to_intel_encoder(encoder));
d2a82a6f 2257
ea5b213a 2258 if (intel_sdvo->sdvo_lvds_fixed_mode != NULL)
d2a82a6f 2259 drm_mode_destroy(encoder->dev,
ea5b213a 2260 intel_sdvo->sdvo_lvds_fixed_mode);
d2a82a6f 2261
e957d772 2262 i2c_del_adapter(&intel_sdvo->ddc);
ea5b213a 2263 intel_encoder_destroy(encoder);
79e53945
JB		 2264}
2265
2266static const struct drm_encoder_funcs intel_sdvo_enc_funcs = {
2267 .destroy = intel_sdvo_enc_destroy,
2268};
2269
b66d8424
CW		 2270static void
2271intel_sdvo_guess_ddc_bus(struct intel_sdvo *sdvo)
2272{
2273 uint16_t mask = 0;
2274 unsigned int num_bits;
2275
2276 /* Make a mask of outputs less than or equal to our own priority in the
2277 * list.
2278 */
2279 switch (sdvo->controlled_output) {
2280 case SDVO_OUTPUT_LVDS1:
2281 mask |= SDVO_OUTPUT_LVDS1;
2282 case SDVO_OUTPUT_LVDS0:
2283 mask |= SDVO_OUTPUT_LVDS0;
2284 case SDVO_OUTPUT_TMDS1:
2285 mask |= SDVO_OUTPUT_TMDS1;
2286 case SDVO_OUTPUT_TMDS0:
2287 mask |= SDVO_OUTPUT_TMDS0;
2288 case SDVO_OUTPUT_RGB1:
2289 mask |= SDVO_OUTPUT_RGB1;
2290 case SDVO_OUTPUT_RGB0:
2291 mask |= SDVO_OUTPUT_RGB0;
2292 break;
2293 }
2294
2295 /* Count bits to find what number we are in the priority list. */
2296 mask &= sdvo->caps.output_flags;
2297 num_bits = hweight16(mask);
2298 /* If more than 3 outputs, default to DDC bus 3 for now. */
2299 if (num_bits > 3)
2300 num_bits = 3;
2301
2302 /* Corresponds to SDVO_CONTROL_BUS_DDCx */
2303 sdvo->ddc_bus = 1 << num_bits;
2304}
79e53945 2305
e2f0ba97
JB		 2306/**
2307 * Choose the appropriate DDC bus for control bus switch command for this
2308 * SDVO output based on the controlled output.
2309 *
2310 * DDC bus number assignment is in a priority order of RGB outputs, then TMDS
2311 * outputs, then LVDS outputs.
2312 */
2313static void
b1083333 2314intel_sdvo_select_ddc_bus(struct drm_i915_private *dev_priv,
8bd864b8 2315 struct intel_sdvo *sdvo)
e2f0ba97 2316{
b1083333 2317 struct sdvo_device_mapping *mapping;
e2f0ba97 2318
2a5c0832 2319 if (sdvo->port == PORT_B)
9d6c875d 2320 mapping = &dev_priv->vbt.sdvo_mappings[0];
b1083333 2321 else
9d6c875d 2322 mapping = &dev_priv->vbt.sdvo_mappings[1];
e2f0ba97 2323
b66d8424
CW		 2324 if (mapping->initialized)
2325 sdvo->ddc_bus = 1 << ((mapping->ddc_pin & 0xf0) >> 4);
2326 else
2327 intel_sdvo_guess_ddc_bus(sdvo);
e2f0ba97
JB		 2328}
2329
e957d772
CW		 2330static void
2331intel_sdvo_select_i2c_bus(struct drm_i915_private *dev_priv,
8bd864b8 2332 struct intel_sdvo *sdvo)
e957d772
CW		 2333{
2334 struct sdvo_device_mapping *mapping;
46eb3036 2335 u8 pin;
e957d772 2336
2a5c0832 2337 if (sdvo->port == PORT_B)
9d6c875d 2338 mapping = &dev_priv->vbt.sdvo_mappings[0];
e957d772 2339 else
9d6c875d 2340 mapping = &dev_priv->vbt.sdvo_mappings[1];
e957d772 2341
88ac7939
JN		 2342 if (mapping->initialized &&
2343 intel_gmbus_is_valid_pin(dev_priv, mapping->i2c_pin))
e957d772 2344 pin = mapping->i2c_pin;
6cb1612a 2345 else
988c7015 2346 pin = GMBUS_PIN_DPB;
e957d772 2347
6cb1612a
JN		 2348 sdvo->i2c = intel_gmbus_get_adapter(dev_priv, pin);
2349
2350 /* With gmbus we should be able to drive sdvo i2c at 2MHz, but somehow
2351 * our code totally fails once we start using gmbus. Hence fall back to
2352 * bit banging for now. */
2353 intel_gmbus_force_bit(sdvo->i2c, true);
e957d772
CW		 2354}
2355
fbfcc4f3
JN		 2356/* undo any changes intel_sdvo_select_i2c_bus() did to sdvo->i2c */
2357static void
2358intel_sdvo_unselect_i2c_bus(struct intel_sdvo *sdvo)
2359{
2360 intel_gmbus_force_bit(sdvo->i2c, false);
e957d772
CW		 2361}
2362
e2f0ba97 2363static bool
e27d8538 2364intel_sdvo_is_hdmi_connector(struct intel_sdvo *intel_sdvo, int device)
e2f0ba97 2365{
97aaf910 2366 return intel_sdvo_check_supp_encode(intel_sdvo);
e2f0ba97
JB		 2367}
2368
714605e4 2369static u8
c39055b0
ACO		 2370intel_sdvo_get_slave_addr(struct drm_i915_private *dev_priv,
2371 struct intel_sdvo *sdvo)
714605e4 2372{
714605e4 2373 struct sdvo_device_mapping *my_mapping, *other_mapping;
2374
2a5c0832 2375 if (sdvo->port == PORT_B) {
9d6c875d
JN		 2376 my_mapping = &dev_priv->vbt.sdvo_mappings[0];
2377 other_mapping = &dev_priv->vbt.sdvo_mappings[1];
714605e4 2378 } else {
9d6c875d
JN		 2379 my_mapping = &dev_priv->vbt.sdvo_mappings[1];
2380 other_mapping = &dev_priv->vbt.sdvo_mappings[0];
714605e4 2381 }
2382
2383 /* If the BIOS described our SDVO device, take advantage of it. */
2384 if (my_mapping->slave_addr)
2385 return my_mapping->slave_addr;
2386
2387 /* If the BIOS only described a different SDVO device, use the
2388 * address that it isn't using.
2389 */
2390 if (other_mapping->slave_addr) {
2391 if (other_mapping->slave_addr == 0x70)
2392 return 0x72;
2393 else
2394 return 0x70;
2395 }
2396
2397 /* No SDVO device info is found for another DVO port,
2398 * so use mapping assumption we had before BIOS parsing.
2399 */
2a5c0832 2400 if (sdvo->port == PORT_B)
714605e4 2401 return 0x70;
2402 else
2403 return 0x72;
2404}
2405
c393454d 2406static int
df0e9248
CW		 2407intel_sdvo_connector_init(struct intel_sdvo_connector *connector,
2408 struct intel_sdvo *encoder)
14571b4c 2409{
c393454d
ID		 2410 struct drm_connector *drm_connector;
2411 int ret;
2412
2413 drm_connector = &connector->base.base;
2414 ret = drm_connector_init(encoder->base.base.dev,
2415 drm_connector,
df0e9248
CW		 2416 &intel_sdvo_connector_funcs,
2417 connector->base.base.connector_type);
c393454d
ID		 2418 if (ret < 0)
2419 return ret;
6070a4a9 2420
c393454d 2421 drm_connector_helper_add(drm_connector,
df0e9248 2422 &intel_sdvo_connector_helper_funcs);
14571b4c 2423
8f4839e2 2424 connector->base.base.interlace_allowed = 1;
df0e9248
CW		 2425 connector->base.base.doublescan_allowed = 0;
2426 connector->base.base.display_info.subpixel_order = SubPixelHorizontalRGB;
4ac41f47 2427 connector->base.get_hw_state = intel_sdvo_connector_get_hw_state;
14571b4c 2428
df0e9248 2429 intel_connector_attach_encoder(&connector->base, &encoder->base);
c393454d
ID		 2430
2431 return 0;
14571b4c 2432}
6070a4a9 2433
7f36e7ed 2434static void
55bc60db
VS		 2435intel_sdvo_add_hdmi_properties(struct intel_sdvo *intel_sdvo,
2436 struct intel_sdvo_connector *connector)
7f36e7ed 2437{
646d5772 2438 struct drm_i915_private *dev_priv = to_i915(connector->base.base.dev);
7f36e7ed 2439
3f43c48d 2440 intel_attach_force_audio_property(&connector->base.base);
646d5772 2441 if (INTEL_GEN(dev_priv) >= 4 && IS_MOBILE(dev_priv)) {
e953fd7b 2442 intel_attach_broadcast_rgb_property(&connector->base.base);
55bc60db 2443 }
7949dd47 2444 intel_attach_aspect_ratio_property(&connector->base.base);
0e9f25d0 2445 connector->base.base.state->picture_aspect_ratio = HDMI_PICTURE_ASPECT_NONE;
7f36e7ed
CW		 2446}
2447
08d9bc92
ACO		 2448static struct intel_sdvo_connector *intel_sdvo_connector_alloc(void)
2449{
2450 struct intel_sdvo_connector *sdvo_connector;
630d30a4 2451 struct intel_sdvo_connector_state *conn_state;
08d9bc92
ACO		 2452
2453 sdvo_connector = kzalloc(sizeof(*sdvo_connector), GFP_KERNEL);
2454 if (!sdvo_connector)
2455 return NULL;
2456
630d30a4
ML		 2457 conn_state = kzalloc(sizeof(*conn_state), GFP_KERNEL);
2458 if (!conn_state) {
08d9bc92
ACO		 2459 kfree(sdvo_connector);
2460 return NULL;
2461 }
2462
630d30a4
ML		 2463 __drm_atomic_helper_connector_reset(&sdvo_connector->base.base,
2464 &conn_state->base.base);
2465
08d9bc92
ACO		 2466 return sdvo_connector;
2467}
2468
fb7a46f3 2469static bool
ea5b213a 2470intel_sdvo_dvi_init(struct intel_sdvo *intel_sdvo, int device)
fb7a46f3 2471{
4ef69c7a 2472 struct drm_encoder *encoder = &intel_sdvo->base.base;
de44e256 2473 struct drm_i915_private *dev_priv = to_i915(encoder->dev);
14571b4c 2474 struct drm_connector *connector;
cc68c81a 2475 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
14571b4c 2476 struct intel_connector *intel_connector;
615fb93f 2477 struct intel_sdvo_connector *intel_sdvo_connector;
14571b4c 2478
46a3f4a3
CW		 2479 DRM_DEBUG_KMS("initialising DVI device %d\n", device);
2480
08d9bc92 2481 intel_sdvo_connector = intel_sdvo_connector_alloc();
615fb93f 2482 if (!intel_sdvo_connector)
14571b4c
ZW		 2483 return false;
2484
14571b4c 2485 if (device == 0) {
ea5b213a 2486 intel_sdvo->controlled_output |= SDVO_OUTPUT_TMDS0;
615fb93f 2487 intel_sdvo_connector->output_flag = SDVO_OUTPUT_TMDS0;
14571b4c 2488 } else if (device == 1) {
ea5b213a 2489 intel_sdvo->controlled_output |= SDVO_OUTPUT_TMDS1;
615fb93f 2490 intel_sdvo_connector->output_flag = SDVO_OUTPUT_TMDS1;
14571b4c
ZW		 2491 }
2492
615fb93f 2493 intel_connector = &intel_sdvo_connector->base;
14571b4c 2494 connector = &intel_connector->base;
5fa7ac9c
JN		 2495 if (intel_sdvo_get_hotplug_support(intel_sdvo) &
2496 intel_sdvo_connector->output_flag) {
5fa7ac9c 2497 intel_sdvo->hotplug_active |= intel_sdvo_connector->output_flag;
cc68c81a
SF		 2498 /* Some SDVO devices have one-shot hotplug interrupts.
2499 * Ensure that they get re-enabled when an interrupt happens.
2500 */
2501 intel_encoder->hot_plug = intel_sdvo_enable_hotplug;
3a2fb2c3 2502 intel_sdvo_enable_hotplug(intel_encoder);
5fa7ac9c 2503 } else {
821450c6 2504 intel_connector->polled = DRM_CONNECTOR_POLL_CONNECT | DRM_CONNECTOR_POLL_DISCONNECT;
5fa7ac9c 2505 }
14571b4c
ZW		 2506 encoder->encoder_type = DRM_MODE_ENCODER_TMDS;
2507 connector->connector_type = DRM_MODE_CONNECTOR_DVID;
2508
de44e256
DV		 2509 /* gen3 doesn't do the hdmi bits in the SDVO register */
2510 if (INTEL_GEN(dev_priv) >= 4 &&
2511 intel_sdvo_is_hdmi_connector(intel_sdvo, device)) {
14571b4c 2512 connector->connector_type = DRM_MODE_CONNECTOR_HDMIA;
e27d8538 2513 intel_sdvo->is_hdmi = true;
14571b4c 2514 }
14571b4c 2515
c393454d
ID		 2516 if (intel_sdvo_connector_init(intel_sdvo_connector, intel_sdvo) < 0) {
2517 kfree(intel_sdvo_connector);
2518 return false;
2519 }
2520
f797d221 2521 if (intel_sdvo->is_hdmi)
55bc60db 2522 intel_sdvo_add_hdmi_properties(intel_sdvo, intel_sdvo_connector);
14571b4c
ZW		 2523
2524 return true;
2525}
2526
2527static bool
ea5b213a 2528intel_sdvo_tv_init(struct intel_sdvo *intel_sdvo, int type)
14571b4c 2529{
4ef69c7a
CW		 2530 struct drm_encoder *encoder = &intel_sdvo->base.base;
2531 struct drm_connector *connector;
2532 struct intel_connector *intel_connector;
2533 struct intel_sdvo_connector *intel_sdvo_connector;
14571b4c 2534
46a3f4a3
CW		 2535 DRM_DEBUG_KMS("initialising TV type %d\n", type);
2536
08d9bc92 2537 intel_sdvo_connector = intel_sdvo_connector_alloc();
615fb93f
CW		 2538 if (!intel_sdvo_connector)
2539 return false;
14571b4c 2540
615fb93f 2541 intel_connector = &intel_sdvo_connector->base;
4ef69c7a
CW		 2542 connector = &intel_connector->base;
2543 encoder->encoder_type = DRM_MODE_ENCODER_TVDAC;
2544 connector->connector_type = DRM_MODE_CONNECTOR_SVIDEO;
14571b4c 2545
4ef69c7a
CW		 2546 intel_sdvo->controlled_output |= type;
2547 intel_sdvo_connector->output_flag = type;
14571b4c 2548
4ef69c7a 2549 intel_sdvo->is_tv = true;
14571b4c 2550
c393454d
ID		 2551 if (intel_sdvo_connector_init(intel_sdvo_connector, intel_sdvo) < 0) {
2552 kfree(intel_sdvo_connector);
2553 return false;
2554 }
14571b4c 2555
4ef69c7a 2556 if (!intel_sdvo_tv_create_property(intel_sdvo, intel_sdvo_connector, type))
32aad86f 2557 goto err;
14571b4c 2558
4ef69c7a 2559 if (!intel_sdvo_create_enhance_property(intel_sdvo, intel_sdvo_connector))
32aad86f 2560 goto err;
14571b4c 2561
4ef69c7a 2562 return true;
32aad86f
CW		 2563
2564err:
123d5c01 2565 intel_sdvo_destroy(connector);
32aad86f 2566 return false;
14571b4c
ZW		 2567}
2568
2569static bool
ea5b213a 2570intel_sdvo_analog_init(struct intel_sdvo *intel_sdvo, int device)
14571b4c 2571{
4ef69c7a
CW		 2572 struct drm_encoder *encoder = &intel_sdvo->base.base;
2573 struct drm_connector *connector;
2574 struct intel_connector *intel_connector;
2575 struct intel_sdvo_connector *intel_sdvo_connector;
14571b4c 2576
46a3f4a3
CW		 2577 DRM_DEBUG_KMS("initialising analog device %d\n", device);
2578
8ce7da47 2579 intel_sdvo_connector = intel_sdvo_connector_alloc();
615fb93f
CW		 2580 if (!intel_sdvo_connector)
2581 return false;
14571b4c 2582
615fb93f 2583 intel_connector = &intel_sdvo_connector->base;
4ef69c7a 2584 connector = &intel_connector->base;
821450c6 2585 intel_connector->polled = DRM_CONNECTOR_POLL_CONNECT;
4ef69c7a
CW		 2586 encoder->encoder_type = DRM_MODE_ENCODER_DAC;
2587 connector->connector_type = DRM_MODE_CONNECTOR_VGA;
2588
2589 if (device == 0) {
2590 intel_sdvo->controlled_output |= SDVO_OUTPUT_RGB0;
2591 intel_sdvo_connector->output_flag = SDVO_OUTPUT_RGB0;
2592 } else if (device == 1) {
2593 intel_sdvo->controlled_output |= SDVO_OUTPUT_RGB1;
2594 intel_sdvo_connector->output_flag = SDVO_OUTPUT_RGB1;
2595 }
2596
c393454d
ID		 2597 if (intel_sdvo_connector_init(intel_sdvo_connector, intel_sdvo) < 0) {
2598 kfree(intel_sdvo_connector);
2599 return false;
2600 }
2601
4ef69c7a 2602 return true;
14571b4c
ZW		 2603}
2604
2605static bool
ea5b213a 2606intel_sdvo_lvds_init(struct intel_sdvo *intel_sdvo, int device)
14571b4c 2607{
4ef69c7a
CW		 2608 struct drm_encoder *encoder = &intel_sdvo->base.base;
2609 struct drm_connector *connector;
2610 struct intel_connector *intel_connector;
2611 struct intel_sdvo_connector *intel_sdvo_connector;
14571b4c 2612
46a3f4a3
CW		 2613 DRM_DEBUG_KMS("initialising LVDS device %d\n", device);
2614
08d9bc92 2615 intel_sdvo_connector = intel_sdvo_connector_alloc();
615fb93f
CW		 2616 if (!intel_sdvo_connector)
2617 return false;
14571b4c 2618
615fb93f
CW		 2619 intel_connector = &intel_sdvo_connector->base;
2620 connector = &intel_connector->base;
4ef69c7a
CW		 2621 encoder->encoder_type = DRM_MODE_ENCODER_LVDS;
2622 connector->connector_type = DRM_MODE_CONNECTOR_LVDS;
2623
2624 if (device == 0) {
2625 intel_sdvo->controlled_output |= SDVO_OUTPUT_LVDS0;
2626 intel_sdvo_connector->output_flag = SDVO_OUTPUT_LVDS0;
2627 } else if (device == 1) {
2628 intel_sdvo->controlled_output |= SDVO_OUTPUT_LVDS1;
2629 intel_sdvo_connector->output_flag = SDVO_OUTPUT_LVDS1;
2630 }
2631
c393454d
ID		 2632 if (intel_sdvo_connector_init(intel_sdvo_connector, intel_sdvo) < 0) {
2633 kfree(intel_sdvo_connector);
2634 return false;
2635 }
2636
4ef69c7a 2637 if (!intel_sdvo_create_enhance_property(intel_sdvo, intel_sdvo_connector))
32aad86f
CW		 2638 goto err;
2639
2640 return true;
2641
2642err:
123d5c01 2643 intel_sdvo_destroy(connector);
32aad86f 2644 return false;
14571b4c
ZW		 2645}
2646
2647static bool
ea5b213a 2648intel_sdvo_output_setup(struct intel_sdvo *intel_sdvo, uint16_t flags)
14571b4c 2649{
ea5b213a 2650 intel_sdvo->is_tv = false;
ea5b213a 2651 intel_sdvo->is_lvds = false;
fb7a46f3 2652
14571b4c 2653 /* SDVO requires XXX1 function may not exist unless it has XXX0 function.*/
fb7a46f3 2654
14571b4c 2655 if (flags & SDVO_OUTPUT_TMDS0)
ea5b213a 2656 if (!intel_sdvo_dvi_init(intel_sdvo, 0))
14571b4c
ZW		 2657 return false;
2658
2659 if ((flags & SDVO_TMDS_MASK) == SDVO_TMDS_MASK)
ea5b213a 2660 if (!intel_sdvo_dvi_init(intel_sdvo, 1))
14571b4c
ZW		 2661 return false;
2662
2663 /* TV has no XXX1 function block */
a1f4b7ff 2664 if (flags & SDVO_OUTPUT_SVID0)
ea5b213a 2665 if (!intel_sdvo_tv_init(intel_sdvo, SDVO_OUTPUT_SVID0))
14571b4c
ZW		 2666 return false;
2667
2668 if (flags & SDVO_OUTPUT_CVBS0)
ea5b213a 2669 if (!intel_sdvo_tv_init(intel_sdvo, SDVO_OUTPUT_CVBS0))
14571b4c 2670 return false;
fb7a46f3 2671
a0b1c7a5
CW		 2672 if (flags & SDVO_OUTPUT_YPRPB0)
2673 if (!intel_sdvo_tv_init(intel_sdvo, SDVO_OUTPUT_YPRPB0))
2674 return false;
2675
14571b4c 2676 if (flags & SDVO_OUTPUT_RGB0)
ea5b213a 2677 if (!intel_sdvo_analog_init(intel_sdvo, 0))
14571b4c
ZW		 2678 return false;
2679
2680 if ((flags & SDVO_RGB_MASK) == SDVO_RGB_MASK)
ea5b213a 2681 if (!intel_sdvo_analog_init(intel_sdvo, 1))
14571b4c
ZW		 2682 return false;
2683
2684 if (flags & SDVO_OUTPUT_LVDS0)
ea5b213a 2685 if (!intel_sdvo_lvds_init(intel_sdvo, 0))
14571b4c
ZW		 2686 return false;
2687
2688 if ((flags & SDVO_LVDS_MASK) == SDVO_LVDS_MASK)
ea5b213a 2689 if (!intel_sdvo_lvds_init(intel_sdvo, 1))
14571b4c 2690 return false;
fb7a46f3 2691
14571b4c 2692 if ((flags & SDVO_OUTPUT_MASK) == 0) {
fb7a46f3 2693 unsigned char bytes[2];
2694
ea5b213a
CW		 2695 intel_sdvo->controlled_output = 0;
2696 memcpy(bytes, &intel_sdvo->caps.output_flags, 2);
51c8b407 2697 DRM_DEBUG_KMS("%s: Unknown SDVO output type (0x%02x%02x)\n",
ea5b213a 2698 SDVO_NAME(intel_sdvo),
51c8b407 2699 bytes[0], bytes[1]);
14571b4c 2700 return false;
fb7a46f3 2701 }
27f8227b 2702 intel_sdvo->base.crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
fb7a46f3 2703
14571b4c 2704 return true;
fb7a46f3 2705}
2706
d0ddfbd3
JN		 2707static void intel_sdvo_output_cleanup(struct intel_sdvo *intel_sdvo)
2708{
2709 struct drm_device *dev = intel_sdvo->base.base.dev;
2710 struct drm_connector *connector, *tmp;
2711
2712 list_for_each_entry_safe(connector, tmp,
2713 &dev->mode_config.connector_list, head) {
d9255d57 2714 if (intel_attached_encoder(connector) == &intel_sdvo->base) {
34ea3d38 2715 drm_connector_unregister(connector);
d0ddfbd3 2716 intel_sdvo_destroy(connector);
d9255d57 2717 }
d0ddfbd3
JN		 2718 }
2719}
2720
32aad86f
CW		 2721static bool intel_sdvo_tv_create_property(struct intel_sdvo *intel_sdvo,
2722 struct intel_sdvo_connector *intel_sdvo_connector,
2723 int type)
ce6feabd 2724{
4ef69c7a 2725 struct drm_device *dev = intel_sdvo->base.base.dev;
ce6feabd
ZY		 2726 struct intel_sdvo_tv_format format;
2727 uint32_t format_map, i;
ce6feabd 2728
32aad86f
CW		 2729 if (!intel_sdvo_set_target_output(intel_sdvo, type))
2730 return false;
ce6feabd 2731
1a3665c8 2732 BUILD_BUG_ON(sizeof(format) != 6);
32aad86f
CW		 2733 if (!intel_sdvo_get_value(intel_sdvo,
2734 SDVO_CMD_GET_SUPPORTED_TV_FORMATS,
2735 &format, sizeof(format)))
2736 return false;
ce6feabd 2737
32aad86f 2738 memcpy(&format_map, &format, min(sizeof(format_map), sizeof(format)));
ce6feabd
ZY		 2739
2740 if (format_map == 0)
32aad86f 2741 return false;
ce6feabd 2742
615fb93f 2743 intel_sdvo_connector->format_supported_num = 0;
ce6feabd 2744 for (i = 0 ; i < TV_FORMAT_NUM; i++)
40039750
CW		 2745 if (format_map & (1 << i))
2746 intel_sdvo_connector->tv_format_supported[intel_sdvo_connector->format_supported_num++] = i;
ce6feabd
ZY		 2747
2748
c5521706 2749 intel_sdvo_connector->tv_format =
32aad86f
CW		 2750 drm_property_create(dev, DRM_MODE_PROP_ENUM,
2751 "mode", intel_sdvo_connector->format_supported_num);
c5521706 2752 if (!intel_sdvo_connector->tv_format)
fcc8d672 2753 return false;
ce6feabd 2754
615fb93f 2755 for (i = 0; i < intel_sdvo_connector->format_supported_num; i++)
ce6feabd 2756 drm_property_add_enum(
c5521706 2757 intel_sdvo_connector->tv_format, i,
40039750 2758 i, tv_format_names[intel_sdvo_connector->tv_format_supported[i]]);
ce6feabd 2759
630d30a4 2760 intel_sdvo_connector->base.base.state->tv.mode = intel_sdvo_connector->tv_format_supported[0];
10223df2
VS		 2761 drm_object_attach_property(&intel_sdvo_connector->base.base.base,
2762 intel_sdvo_connector->tv_format, 0);
32aad86f 2763 return true;
ce6feabd
ZY		 2764
2765}
2766
630d30a4 2767#define _ENHANCEMENT(state_assignment, name, NAME) do { \
c5521706
CW		 2768 if (enhancements.name) { \
2769 if (!intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_MAX_##NAME, &data_value, 4) || \
2770 !intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_##NAME, &response, 2)) \
2771 return false; \
c5521706 2772 intel_sdvo_connector->name = \
d9bc3c02 2773 drm_property_create_range(dev, 0, #name, 0, data_value[0]); \
c5521706 2774 if (!intel_sdvo_connector->name) return false; \
630d30a4 2775 state_assignment = response; \
662595df 2776 drm_object_attach_property(&connector->base, \
630d30a4 2777 intel_sdvo_connector->name, 0); \
c5521706
CW		 2778 DRM_DEBUG_KMS(#name ": max %d, default %d, current %d\n", \
2779 data_value[0], data_value[1], response); \
2780 } \
0206e353 2781} while (0)
c5521706 2782
630d30a4
ML		 2783#define ENHANCEMENT(state, name, NAME) _ENHANCEMENT((state)->name, name, NAME)
2784
c5521706
CW		 2785static bool
2786intel_sdvo_create_enhance_property_tv(struct intel_sdvo *intel_sdvo,
2787 struct intel_sdvo_connector *intel_sdvo_connector,
2788 struct intel_sdvo_enhancements_reply enhancements)
b9219c5e 2789{
4ef69c7a 2790 struct drm_device *dev = intel_sdvo->base.base.dev;
32aad86f 2791 struct drm_connector *connector = &intel_sdvo_connector->base.base;
630d30a4
ML		 2792 struct drm_connector_state *conn_state = connector->state;
2793 struct intel_sdvo_connector_state *sdvo_state =
2794 to_intel_sdvo_connector_state(conn_state);
b9219c5e
ZY		 2795 uint16_t response, data_value[2];
2796
c5521706
CW		 2797 /* when horizontal overscan is supported, Add the left/right property */
2798 if (enhancements.overscan_h) {
2799 if (!intel_sdvo_get_value(intel_sdvo,
2800 SDVO_CMD_GET_MAX_OVERSCAN_H,
2801 &data_value, 4))
2802 return false;
32aad86f 2803
c5521706
CW		 2804 if (!intel_sdvo_get_value(intel_sdvo,
2805 SDVO_CMD_GET_OVERSCAN_H,
2806 &response, 2))
2807 return false;
fcc8d672 2808
630d30a4
ML		 2809 sdvo_state->tv.overscan_h = response;
2810
c5521706 2811 intel_sdvo_connector->max_hscan = data_value[0];
c5521706 2812 intel_sdvo_connector->left =
d9bc3c02 2813 drm_property_create_range(dev, 0, "left_margin", 0, data_value[0]);
c5521706
CW		 2814 if (!intel_sdvo_connector->left)
2815 return false;
fcc8d672 2816
662595df 2817 drm_object_attach_property(&connector->base,
630d30a4 2818 intel_sdvo_connector->left, 0);
fcc8d672 2819
c5521706 2820 intel_sdvo_connector->right =
d9bc3c02 2821 drm_property_create_range(dev, 0, "right_margin", 0, data_value[0]);
c5521706
CW		 2822 if (!intel_sdvo_connector->right)
2823 return false;
32aad86f 2824
662595df 2825 drm_object_attach_property(&connector->base,
630d30a4 2826 intel_sdvo_connector->right, 0);
c5521706
CW		 2827 DRM_DEBUG_KMS("h_overscan: max %d, "
2828 "default %d, current %d\n",
2829 data_value[0], data_value[1], response);
2830 }
32aad86f 2831
c5521706
CW		 2832 if (enhancements.overscan_v) {
2833 if (!intel_sdvo_get_value(intel_sdvo,
2834 SDVO_CMD_GET_MAX_OVERSCAN_V,
2835 &data_value, 4))
2836 return false;
fcc8d672 2837
c5521706
CW		 2838 if (!intel_sdvo_get_value(intel_sdvo,
2839 SDVO_CMD_GET_OVERSCAN_V,
2840 &response, 2))
2841 return false;
32aad86f 2842
630d30a4
ML		 2843 sdvo_state->tv.overscan_v = response;
2844
c5521706 2845 intel_sdvo_connector->max_vscan = data_value[0];
c5521706 2846 intel_sdvo_connector->top =
d9bc3c02
SH		 2847 drm_property_create_range(dev, 0,
2848 "top_margin", 0, data_value[0]);
c5521706
CW		 2849 if (!intel_sdvo_connector->top)
2850 return false;
32aad86f 2851
662595df 2852 drm_object_attach_property(&connector->base,
630d30a4 2853 intel_sdvo_connector->top, 0);
fcc8d672 2854
c5521706 2855 intel_sdvo_connector->bottom =
d9bc3c02
SH		 2856 drm_property_create_range(dev, 0,
2857 "bottom_margin", 0, data_value[0]);
c5521706
CW		 2858 if (!intel_sdvo_connector->bottom)
2859 return false;
32aad86f 2860
662595df 2861 drm_object_attach_property(&connector->base,
630d30a4 2862 intel_sdvo_connector->bottom, 0);
c5521706
CW		 2863 DRM_DEBUG_KMS("v_overscan: max %d, "
2864 "default %d, current %d\n",
2865 data_value[0], data_value[1], response);
2866 }
32aad86f 2867
630d30a4
ML		 2868 ENHANCEMENT(&sdvo_state->tv, hpos, HPOS);
2869 ENHANCEMENT(&sdvo_state->tv, vpos, VPOS);
2870 ENHANCEMENT(&conn_state->tv, saturation, SATURATION);
2871 ENHANCEMENT(&conn_state->tv, contrast, CONTRAST);
2872 ENHANCEMENT(&conn_state->tv, hue, HUE);
2873 ENHANCEMENT(&conn_state->tv, brightness, BRIGHTNESS);
2874 ENHANCEMENT(&sdvo_state->tv, sharpness, SHARPNESS);
2875 ENHANCEMENT(&sdvo_state->tv, flicker_filter, FLICKER_FILTER);
2876 ENHANCEMENT(&sdvo_state->tv, flicker_filter_adaptive, FLICKER_FILTER_ADAPTIVE);
2877 ENHANCEMENT(&sdvo_state->tv, flicker_filter_2d, FLICKER_FILTER_2D);
2878 _ENHANCEMENT(sdvo_state->tv.chroma_filter, tv_chroma_filter, TV_CHROMA_FILTER);
2879 _ENHANCEMENT(sdvo_state->tv.luma_filter, tv_luma_filter, TV_LUMA_FILTER);
fcc8d672 2880
e044218a
CW		 2881 if (enhancements.dot_crawl) {
2882 if (!intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_DOT_CRAWL, &response, 2))
2883 return false;
2884
630d30a4 2885 sdvo_state->tv.dot_crawl = response & 0x1;
e044218a 2886 intel_sdvo_connector->dot_crawl =
d9bc3c02 2887 drm_property_create_range(dev, 0, "dot_crawl", 0, 1);
e044218a
CW		 2888 if (!intel_sdvo_connector->dot_crawl)
2889 return false;
2890
662595df 2891 drm_object_attach_property(&connector->base,
630d30a4 2892 intel_sdvo_connector->dot_crawl, 0);
e044218a
CW		 2893 DRM_DEBUG_KMS("dot crawl: current %d\n", response);
2894 }
2895
c5521706
CW		 2896 return true;
2897}
32aad86f 2898
c5521706
CW		 2899static bool
2900intel_sdvo_create_enhance_property_lvds(struct intel_sdvo *intel_sdvo,
2901 struct intel_sdvo_connector *intel_sdvo_connector,
2902 struct intel_sdvo_enhancements_reply enhancements)
2903{
4ef69c7a 2904 struct drm_device *dev = intel_sdvo->base.base.dev;
c5521706
CW		 2905 struct drm_connector *connector = &intel_sdvo_connector->base.base;
2906 uint16_t response, data_value[2];
32aad86f 2907
630d30a4 2908 ENHANCEMENT(&connector->state->tv, brightness, BRIGHTNESS);
fcc8d672 2909
c5521706
CW		 2910 return true;
2911}
2912#undef ENHANCEMENT
630d30a4 2913#undef _ENHANCEMENT
32aad86f 2914
c5521706
CW		 2915static bool intel_sdvo_create_enhance_property(struct intel_sdvo *intel_sdvo,
2916 struct intel_sdvo_connector *intel_sdvo_connector)
2917{
2918 union {
2919 struct intel_sdvo_enhancements_reply reply;
2920 uint16_t response;
2921 } enhancements;
32aad86f 2922
1a3665c8
CW		 2923 BUILD_BUG_ON(sizeof(enhancements) != 2);
2924
99016646
ID		 2925 if (!intel_sdvo_get_value(intel_sdvo,
2926 SDVO_CMD_GET_SUPPORTED_ENHANCEMENTS,
2927 &enhancements, sizeof(enhancements)) ||
2928 enhancements.response == 0) {
c5521706
CW		 2929 DRM_DEBUG_KMS("No enhancement is supported\n");
2930 return true;
b9219c5e 2931 }
32aad86f 2932
c5521706
CW		 2933 if (IS_TV(intel_sdvo_connector))
2934 return intel_sdvo_create_enhance_property_tv(intel_sdvo, intel_sdvo_connector, enhancements.reply);
0206e353 2935 else if (IS_LVDS(intel_sdvo_connector))
c5521706
CW		 2936 return intel_sdvo_create_enhance_property_lvds(intel_sdvo, intel_sdvo_connector, enhancements.reply);
2937 else
2938 return true;
e957d772
CW		 2939}
2940
2941static int intel_sdvo_ddc_proxy_xfer(struct i2c_adapter *adapter,
2942 struct i2c_msg *msgs,
2943 int num)
2944{
2945 struct intel_sdvo *sdvo = adapter->algo_data;
fcc8d672 2946
a8506684 2947 if (!__intel_sdvo_set_control_bus_switch(sdvo, sdvo->ddc_bus))
e957d772
CW		 2948 return -EIO;
2949
2950 return sdvo->i2c->algo->master_xfer(sdvo->i2c, msgs, num);
2951}
2952
2953static u32 intel_sdvo_ddc_proxy_func(struct i2c_adapter *adapter)
2954{
2955 struct intel_sdvo *sdvo = adapter->algo_data;
2956 return sdvo->i2c->algo->functionality(sdvo->i2c);
2957}
2958
2959static const struct i2c_algorithm intel_sdvo_ddc_proxy = {
2960 .master_xfer = intel_sdvo_ddc_proxy_xfer,
2961 .functionality = intel_sdvo_ddc_proxy_func
2962};
2963
a8506684
DV		 2964static void proxy_lock_bus(struct i2c_adapter *adapter,
2965 unsigned int flags)
2966{
2967 struct intel_sdvo *sdvo = adapter->algo_data;
2968 sdvo->i2c->lock_ops->lock_bus(sdvo->i2c, flags);
2969}
2970
2971static int proxy_trylock_bus(struct i2c_adapter *adapter,
2972 unsigned int flags)
2973{
2974 struct intel_sdvo *sdvo = adapter->algo_data;
2975 return sdvo->i2c->lock_ops->trylock_bus(sdvo->i2c, flags);
2976}
2977
2978static void proxy_unlock_bus(struct i2c_adapter *adapter,
2979 unsigned int flags)
2980{
2981 struct intel_sdvo *sdvo = adapter->algo_data;
2982 sdvo->i2c->lock_ops->unlock_bus(sdvo->i2c, flags);
2983}
2984
2985const struct i2c_lock_operations proxy_lock_ops = {
2986 .lock_bus = proxy_lock_bus,
2987 .trylock_bus = proxy_trylock_bus,
2988 .unlock_bus = proxy_unlock_bus,
2989};
2990
e957d772
CW		 2991static bool
2992intel_sdvo_init_ddc_proxy(struct intel_sdvo *sdvo,
c39055b0 2993 struct drm_i915_private *dev_priv)
e957d772 2994{
c39055b0 2995 struct pci_dev *pdev = dev_priv->drm.pdev;
52a05c30 2996
e957d772
CW		 2997 sdvo->ddc.owner = THIS_MODULE;
2998 sdvo->ddc.class = I2C_CLASS_DDC;
2999 snprintf(sdvo->ddc.name, I2C_NAME_SIZE, "SDVO DDC proxy");
52a05c30 3000 sdvo->ddc.dev.parent = &pdev->dev;
e957d772
CW		 3001 sdvo->ddc.algo_data = sdvo;
3002 sdvo->ddc.algo = &intel_sdvo_ddc_proxy;
a8506684 3003 sdvo->ddc.lock_ops = &proxy_lock_ops;
e957d772
CW		 3004
3005 return i2c_add_adapter(&sdvo->ddc) == 0;
b9219c5e
ZY		 3006}
3007
2a5c0832
VS		 3008static void assert_sdvo_port_valid(const struct drm_i915_private *dev_priv,
3009 enum port port)
3010{
3011 if (HAS_PCH_SPLIT(dev_priv))
3012 WARN_ON(port != PORT_B);
3013 else
3014 WARN_ON(port != PORT_B && port != PORT_C);
3015}
3016
c39055b0 3017bool intel_sdvo_init(struct drm_i915_private *dev_priv,
f0f59a00 3018 i915_reg_t sdvo_reg, enum port port)
79e53945 3019{
21d40d37 3020 struct intel_encoder *intel_encoder;
ea5b213a 3021 struct intel_sdvo *intel_sdvo;
79e53945 3022 int i;
2a5c0832
VS		 3023
3024 assert_sdvo_port_valid(dev_priv, port);
3025
b14c5679 3026 intel_sdvo = kzalloc(sizeof(*intel_sdvo), GFP_KERNEL);
ea5b213a 3027 if (!intel_sdvo)
7d57382e 3028 return false;
79e53945 3029
56184e3d 3030 intel_sdvo->sdvo_reg = sdvo_reg;
2a5c0832 3031 intel_sdvo->port = port;
c39055b0
ACO		 3032 intel_sdvo->slave_addr =
3033 intel_sdvo_get_slave_addr(dev_priv, intel_sdvo) >> 1;
8bd864b8 3034 intel_sdvo_select_i2c_bus(dev_priv, intel_sdvo);
c39055b0 3035 if (!intel_sdvo_init_ddc_proxy(intel_sdvo, dev_priv))
fbfcc4f3 3036 goto err_i2c_bus;
e957d772 3037
56184e3d 3038 /* encoder type will be decided later */
ea5b213a 3039 intel_encoder = &intel_sdvo->base;
21d40d37 3040 intel_encoder->type = INTEL_OUTPUT_SDVO;
79f255a0 3041 intel_encoder->power_domain = POWER_DOMAIN_PORT_OTHER;
03cdc1d4 3042 intel_encoder->port = port;
c39055b0
ACO		 3043 drm_encoder_init(&dev_priv->drm, &intel_encoder->base,
3044 &intel_sdvo_enc_funcs, 0,
580d8ed5 3045 "SDVO %c", port_name(port));
79e53945 3046
79e53945
JB		 3047 /* Read the regs to test if we can talk to the device */
3048 for (i = 0; i < 0x40; i++) {
f899fc64
CW		 3049 u8 byte;
3050
3051 if (!intel_sdvo_read_byte(intel_sdvo, i, &byte)) {
eef4eacb
DV		 3052 DRM_DEBUG_KMS("No SDVO device found on %s\n",
3053 SDVO_NAME(intel_sdvo));
f899fc64 3054 goto err;
79e53945
JB		 3055 }
3056 }
3057
6cc5f341 3058 intel_encoder->compute_config = intel_sdvo_compute_config;
6e266956 3059 if (HAS_PCH_SPLIT(dev_priv)) {
3c65d1d1
VS		 3060 intel_encoder->disable = pch_disable_sdvo;
3061 intel_encoder->post_disable = pch_post_disable_sdvo;
3062 } else {
3063 intel_encoder->disable = intel_disable_sdvo;
3064 }
192d47a6 3065 intel_encoder->pre_enable = intel_sdvo_pre_enable;
ce22c320 3066 intel_encoder->enable = intel_enable_sdvo;
4ac41f47 3067 intel_encoder->get_hw_state = intel_sdvo_get_hw_state;
045ac3b5 3068 intel_encoder->get_config = intel_sdvo_get_config;
ce22c320 3069
af901ca1 3070 /* In default case sdvo lvds is false */
32aad86f 3071 if (!intel_sdvo_get_capabilities(intel_sdvo, &intel_sdvo->caps))
f899fc64 3072 goto err;
79e53945 3073
ea5b213a
CW		 3074 if (intel_sdvo_output_setup(intel_sdvo,
3075 intel_sdvo->caps.output_flags) != true) {
eef4eacb
DV		 3076 DRM_DEBUG_KMS("SDVO output failed to setup on %s\n",
3077 SDVO_NAME(intel_sdvo));
d0ddfbd3
JN		 3078 /* Output_setup can leave behind connectors! */
3079 goto err_output;
79e53945
JB		 3080 }
3081
7ba220ce
CW		 3082 /* Only enable the hotplug irq if we need it, to work around noisy
3083 * hotplug lines.
3084 */
3085 if (intel_sdvo->hotplug_active) {
2a5c0832
VS		 3086 if (intel_sdvo->port == PORT_B)
3087 intel_encoder->hpd_pin = HPD_SDVO_B;
3088 else
3089 intel_encoder->hpd_pin = HPD_SDVO_C;
7ba220ce
CW		 3090 }
3091
e506d6fd
DV		 3092 /*
3093 * Cloning SDVO with anything is often impossible, since the SDVO
3094 * encoder can request a special input timing mode. And even if that's
3095 * not the case we have evidence that cloning a plain unscaled mode with
3096 * VGA doesn't really work. Furthermore the cloning flags are way too
3097 * simplistic anyway to express such constraints, so just give up on
3098 * cloning for SDVO encoders.
3099 */
bc079e8b 3100 intel_sdvo->base.cloneable = 0;
e506d6fd 3101
8bd864b8 3102 intel_sdvo_select_ddc_bus(dev_priv, intel_sdvo);
e2f0ba97 3103
79e53945 3104 /* Set the input timing to the screen. Assume always input 0. */
32aad86f 3105 if (!intel_sdvo_set_target_input(intel_sdvo))
d0ddfbd3 3106 goto err_output;
79e53945 3107
32aad86f
CW		 3108 if (!intel_sdvo_get_input_pixel_clock_range(intel_sdvo,
3109 &intel_sdvo->pixel_clock_min,
3110 &intel_sdvo->pixel_clock_max))
d0ddfbd3 3111 goto err_output;
79e53945 3112
8a4c47f3 3113 DRM_DEBUG_KMS("%s device VID/DID: %02X:%02X.%02X, "
342dc382 3114 "clock range %dMHz - %dMHz, "
3115 "input 1: %c, input 2: %c, "
3116 "output 1: %c, output 2: %c\n",
ea5b213a
CW		 3117 SDVO_NAME(intel_sdvo),
3118 intel_sdvo->caps.vendor_id, intel_sdvo->caps.device_id,
3119 intel_sdvo->caps.device_rev_id,
3120 intel_sdvo->pixel_clock_min / 1000,
3121 intel_sdvo->pixel_clock_max / 1000,
3122 (intel_sdvo->caps.sdvo_inputs_mask & 0x1) ? 'Y' : 'N',
3123 (intel_sdvo->caps.sdvo_inputs_mask & 0x2) ? 'Y' : 'N',
342dc382 3124 /* check currently supported outputs */
ea5b213a 3125 intel_sdvo->caps.output_flags &
79e53945 3126 (SDVO_OUTPUT_TMDS0 | SDVO_OUTPUT_RGB0) ? 'Y' : 'N',
ea5b213a 3127 intel_sdvo->caps.output_flags &
79e53945 3128 (SDVO_OUTPUT_TMDS1 | SDVO_OUTPUT_RGB1) ? 'Y' : 'N');
7d57382e 3129 return true;
79e53945 3130
d0ddfbd3
JN		 3131err_output:
3132 intel_sdvo_output_cleanup(intel_sdvo);
3133
f899fc64 3134err:
373a3cf7 3135 drm_encoder_cleanup(&intel_encoder->base);
e957d772 3136 i2c_del_adapter(&intel_sdvo->ddc);
fbfcc4f3
JN		 3137err_i2c_bus:
3138 intel_sdvo_unselect_i2c_bus(intel_sdvo);
ea5b213a 3139 kfree(intel_sdvo);
79e53945 3140
7d57382e 3141 return false;
79e53945 3142}
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