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drm/i915: wait for a vblank to pass after tv detect
[mirror_ubuntu-bionic-kernel.git] / drivers / gpu / drm / i915 / intel_tv.c
CommitLineData
79e53945
JB		 1/*
2 * Copyright © 2006-2008 Intel Corporation
3 * Jesse Barnes <jesse.barnes@intel.com>
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
22 * DEALINGS IN THE SOFTWARE.
23 *
24 * Authors:
25 * Eric Anholt <eric@anholt.net>
26 *
27 */
28
29/** @file
30 * Integrated TV-out support for the 915GM and 945GM.
31 */
32
33#include "drmP.h"
34#include "drm.h"
35#include "drm_crtc.h"
36#include "drm_edid.h"
37#include "intel_drv.h"
38#include "i915_drm.h"
39#include "i915_drv.h"
40
41enum tv_margin {
42 TV_MARGIN_LEFT, TV_MARGIN_TOP,
43 TV_MARGIN_RIGHT, TV_MARGIN_BOTTOM
44};
45
46/** Private structure for the integrated TV support */
ea5b213a
CW		 47struct intel_tv {
48 struct intel_encoder base;
49
79e53945 50 int type;
763a4a01 51 const char *tv_format;
79e53945
JB		 52 int margin[4];
53 u32 save_TV_H_CTL_1;
54 u32 save_TV_H_CTL_2;
55 u32 save_TV_H_CTL_3;
56 u32 save_TV_V_CTL_1;
57 u32 save_TV_V_CTL_2;
58 u32 save_TV_V_CTL_3;
59 u32 save_TV_V_CTL_4;
60 u32 save_TV_V_CTL_5;
61 u32 save_TV_V_CTL_6;
62 u32 save_TV_V_CTL_7;
63 u32 save_TV_SC_CTL_1, save_TV_SC_CTL_2, save_TV_SC_CTL_3;
64
65 u32 save_TV_CSC_Y;
66 u32 save_TV_CSC_Y2;
67 u32 save_TV_CSC_U;
68 u32 save_TV_CSC_U2;
69 u32 save_TV_CSC_V;
70 u32 save_TV_CSC_V2;
71 u32 save_TV_CLR_KNOBS;
72 u32 save_TV_CLR_LEVEL;
73 u32 save_TV_WIN_POS;
74 u32 save_TV_WIN_SIZE;
75 u32 save_TV_FILTER_CTL_1;
76 u32 save_TV_FILTER_CTL_2;
77 u32 save_TV_FILTER_CTL_3;
78
79 u32 save_TV_H_LUMA[60];
80 u32 save_TV_H_CHROMA[60];
81 u32 save_TV_V_LUMA[43];
82 u32 save_TV_V_CHROMA[43];
83
84 u32 save_TV_DAC;
85 u32 save_TV_CTL;
86};
87
88struct video_levels {
89 int blank, black, burst;
90};
91
92struct color_conversion {
93 u16 ry, gy, by, ay;
94 u16 ru, gu, bu, au;
95 u16 rv, gv, bv, av;
96};
97
98static const u32 filter_table[] = {
99 0xB1403000, 0x2E203500, 0x35002E20, 0x3000B140,
100 0x35A0B160, 0x2DC02E80, 0xB1403480, 0xB1603000,
101 0x2EA03640, 0x34002D80, 0x3000B120, 0x36E0B160,
102 0x2D202EF0, 0xB1203380, 0xB1603000, 0x2F303780,
103 0x33002CC0, 0x3000B100, 0x3820B160, 0x2C802F50,
104 0xB10032A0, 0xB1603000, 0x2F9038C0, 0x32202C20,
105 0x3000B0E0, 0x3980B160, 0x2BC02FC0, 0xB0E031C0,
106 0xB1603000, 0x2FF03A20, 0x31602B60, 0xB020B0C0,
107 0x3AE0B160, 0x2B001810, 0xB0C03120, 0xB140B020,
108 0x18283BA0, 0x30C02A80, 0xB020B0A0, 0x3C60B140,
109 0x2A201838, 0xB0A03080, 0xB120B020, 0x18383D20,
110 0x304029C0, 0xB040B080, 0x3DE0B100, 0x29601848,
111 0xB0803000, 0xB100B040, 0x18483EC0, 0xB0402900,
112 0xB040B060, 0x3F80B0C0, 0x28801858, 0xB060B080,
113 0xB0A0B060, 0x18602820, 0xB0A02820, 0x0000B060,
114 0xB1403000, 0x2E203500, 0x35002E20, 0x3000B140,
115 0x35A0B160, 0x2DC02E80, 0xB1403480, 0xB1603000,
116 0x2EA03640, 0x34002D80, 0x3000B120, 0x36E0B160,
117 0x2D202EF0, 0xB1203380, 0xB1603000, 0x2F303780,
118 0x33002CC0, 0x3000B100, 0x3820B160, 0x2C802F50,
119 0xB10032A0, 0xB1603000, 0x2F9038C0, 0x32202C20,
120 0x3000B0E0, 0x3980B160, 0x2BC02FC0, 0xB0E031C0,
121 0xB1603000, 0x2FF03A20, 0x31602B60, 0xB020B0C0,
122 0x3AE0B160, 0x2B001810, 0xB0C03120, 0xB140B020,
123 0x18283BA0, 0x30C02A80, 0xB020B0A0, 0x3C60B140,
124 0x2A201838, 0xB0A03080, 0xB120B020, 0x18383D20,
125 0x304029C0, 0xB040B080, 0x3DE0B100, 0x29601848,
126 0xB0803000, 0xB100B040, 0x18483EC0, 0xB0402900,
127 0xB040B060, 0x3F80B0C0, 0x28801858, 0xB060B080,
128 0xB0A0B060, 0x18602820, 0xB0A02820, 0x0000B060,
129 0x36403000, 0x2D002CC0, 0x30003640, 0x2D0036C0,
130 0x35C02CC0, 0x37403000, 0x2C802D40, 0x30003540,
131 0x2D8037C0, 0x34C02C40, 0x38403000, 0x2BC02E00,
132 0x30003440, 0x2E2038C0, 0x34002B80, 0x39803000,
133 0x2B402E40, 0x30003380, 0x2E603A00, 0x33402B00,
134 0x3A803040, 0x2A802EA0, 0x30403300, 0x2EC03B40,
135 0x32802A40, 0x3C003040, 0x2A002EC0, 0x30803240,
136 0x2EC03C80, 0x320029C0, 0x3D403080, 0x29402F00,
137 0x308031C0, 0x2F203DC0, 0x31802900, 0x3E8030C0,
138 0x28802F40, 0x30C03140, 0x2F203F40, 0x31402840,
139 0x28003100, 0x28002F00, 0x00003100, 0x36403000,
140 0x2D002CC0, 0x30003640, 0x2D0036C0,
141 0x35C02CC0, 0x37403000, 0x2C802D40, 0x30003540,
142 0x2D8037C0, 0x34C02C40, 0x38403000, 0x2BC02E00,
143 0x30003440, 0x2E2038C0, 0x34002B80, 0x39803000,
144 0x2B402E40, 0x30003380, 0x2E603A00, 0x33402B00,
145 0x3A803040, 0x2A802EA0, 0x30403300, 0x2EC03B40,
146 0x32802A40, 0x3C003040, 0x2A002EC0, 0x30803240,
147 0x2EC03C80, 0x320029C0, 0x3D403080, 0x29402F00,
148 0x308031C0, 0x2F203DC0, 0x31802900, 0x3E8030C0,
149 0x28802F40, 0x30C03140, 0x2F203F40, 0x31402840,
150 0x28003100, 0x28002F00, 0x00003100,
151};
152
153/*
154 * Color conversion values have 3 separate fixed point formats:
155 *
156 * 10 bit fields (ay, au)
157 * 1.9 fixed point (b.bbbbbbbbb)
158 * 11 bit fields (ry, by, ru, gu, gv)
159 * exp.mantissa (ee.mmmmmmmmm)
160 * ee = 00 = 10^-1 (0.mmmmmmmmm)
161 * ee = 01 = 10^-2 (0.0mmmmmmmmm)
162 * ee = 10 = 10^-3 (0.00mmmmmmmmm)
163 * ee = 11 = 10^-4 (0.000mmmmmmmmm)
164 * 12 bit fields (gy, rv, bu)
165 * exp.mantissa (eee.mmmmmmmmm)
166 * eee = 000 = 10^-1 (0.mmmmmmmmm)
167 * eee = 001 = 10^-2 (0.0mmmmmmmmm)
168 * eee = 010 = 10^-3 (0.00mmmmmmmmm)
169 * eee = 011 = 10^-4 (0.000mmmmmmmmm)
170 * eee = 100 = reserved
171 * eee = 101 = reserved
172 * eee = 110 = reserved
173 * eee = 111 = 10^0 (m.mmmmmmmm) (only usable for 1.0 representation)
174 *
175 * Saturation and contrast are 8 bits, with their own representation:
176 * 8 bit field (saturation, contrast)
177 * exp.mantissa (ee.mmmmmm)
178 * ee = 00 = 10^-1 (0.mmmmmm)
179 * ee = 01 = 10^0 (m.mmmmm)
180 * ee = 10 = 10^1 (mm.mmmm)
181 * ee = 11 = 10^2 (mmm.mmm)
182 *
183 * Simple conversion function:
184 *
185 * static u32
186 * float_to_csc_11(float f)
187 * {
188 * u32 exp;
189 * u32 mant;
190 * u32 ret;
191 *
192 * if (f < 0)
193 * f = -f;
194 *
195 * if (f >= 1) {
196 * exp = 0x7;
0206e353 197 * mant = 1 << 8;
79e53945
JB		 198 * } else {
199 * for (exp = 0; exp < 3 && f < 0.5; exp++)
0206e353 200 * f *= 2.0;
79e53945
JB		 201 * mant = (f * (1 << 9) + 0.5);
202 * if (mant >= (1 << 9))
203 * mant = (1 << 9) - 1;
204 * }
205 * ret = (exp << 9) | mant;
206 * return ret;
207 * }
208 */
209
210/*
211 * Behold, magic numbers! If we plant them they might grow a big
212 * s-video cable to the sky... or something.
213 *
214 * Pre-converted to appropriate hex value.
215 */
216
217/*
218 * PAL & NTSC values for composite & s-video connections
219 */
220static const struct color_conversion ntsc_m_csc_composite = {
221 .ry = 0x0332, .gy = 0x012d, .by = 0x07d3, .ay = 0x0104,
ba01079c
ZW		 222 .ru = 0x0733, .gu = 0x052d, .bu = 0x05c7, .au = 0x0200,
223 .rv = 0x0340, .gv = 0x030c, .bv = 0x06d0, .av = 0x0200,
79e53945
JB		 224};
225
226static const struct video_levels ntsc_m_levels_composite = {
227 .blank = 225, .black = 267, .burst = 113,
228};
229
230static const struct color_conversion ntsc_m_csc_svideo = {
ba01079c
ZW		 231 .ry = 0x0332, .gy = 0x012d, .by = 0x07d3, .ay = 0x0133,
232 .ru = 0x076a, .gu = 0x0564, .bu = 0x030d, .au = 0x0200,
233 .rv = 0x037a, .gv = 0x033d, .bv = 0x06f6, .av = 0x0200,
79e53945
JB		 234};
235
236static const struct video_levels ntsc_m_levels_svideo = {
237 .blank = 266, .black = 316, .burst = 133,
238};
239
240static const struct color_conversion ntsc_j_csc_composite = {
241 .ry = 0x0332, .gy = 0x012d, .by = 0x07d3, .ay = 0x0119,
ba01079c
ZW		 242 .ru = 0x074c, .gu = 0x0546, .bu = 0x05ec, .au = 0x0200,
243 .rv = 0x035a, .gv = 0x0322, .bv = 0x06e1, .av = 0x0200,
79e53945
JB		 244};
245
246static const struct video_levels ntsc_j_levels_composite = {
247 .blank = 225, .black = 225, .burst = 113,
248};
249
250static const struct color_conversion ntsc_j_csc_svideo = {
251 .ry = 0x0332, .gy = 0x012d, .by = 0x07d3, .ay = 0x014c,
ba01079c
ZW		 252 .ru = 0x0788, .gu = 0x0581, .bu = 0x0322, .au = 0x0200,
253 .rv = 0x0399, .gv = 0x0356, .bv = 0x070a, .av = 0x0200,
79e53945
JB		 254};
255
256static const struct video_levels ntsc_j_levels_svideo = {
257 .blank = 266, .black = 266, .burst = 133,
258};
259
260static const struct color_conversion pal_csc_composite = {
261 .ry = 0x0332, .gy = 0x012d, .by = 0x07d3, .ay = 0x0113,
ba01079c
ZW		 262 .ru = 0x0745, .gu = 0x053f, .bu = 0x05e1, .au = 0x0200,
263 .rv = 0x0353, .gv = 0x031c, .bv = 0x06dc, .av = 0x0200,
79e53945
JB		 264};
265
266static const struct video_levels pal_levels_composite = {
267 .blank = 237, .black = 237, .burst = 118,
268};
269
270static const struct color_conversion pal_csc_svideo = {
271 .ry = 0x0332, .gy = 0x012d, .by = 0x07d3, .ay = 0x0145,
ba01079c
ZW		 272 .ru = 0x0780, .gu = 0x0579, .bu = 0x031c, .au = 0x0200,
273 .rv = 0x0390, .gv = 0x034f, .bv = 0x0705, .av = 0x0200,
79e53945
JB		 274};
275
276static const struct video_levels pal_levels_svideo = {
277 .blank = 280, .black = 280, .burst = 139,
278};
279
280static const struct color_conversion pal_m_csc_composite = {
281 .ry = 0x0332, .gy = 0x012d, .by = 0x07d3, .ay = 0x0104,
ba01079c
ZW		 282 .ru = 0x0733, .gu = 0x052d, .bu = 0x05c7, .au = 0x0200,
283 .rv = 0x0340, .gv = 0x030c, .bv = 0x06d0, .av = 0x0200,
79e53945
JB		 284};
285
286static const struct video_levels pal_m_levels_composite = {
287 .blank = 225, .black = 267, .burst = 113,
288};
289
290static const struct color_conversion pal_m_csc_svideo = {
ba01079c
ZW		 291 .ry = 0x0332, .gy = 0x012d, .by = 0x07d3, .ay = 0x0133,
292 .ru = 0x076a, .gu = 0x0564, .bu = 0x030d, .au = 0x0200,
293 .rv = 0x037a, .gv = 0x033d, .bv = 0x06f6, .av = 0x0200,
79e53945
JB		 294};
295
296static const struct video_levels pal_m_levels_svideo = {
297 .blank = 266, .black = 316, .burst = 133,
298};
299
300static const struct color_conversion pal_n_csc_composite = {
301 .ry = 0x0332, .gy = 0x012d, .by = 0x07d3, .ay = 0x0104,
ba01079c
ZW		 302 .ru = 0x0733, .gu = 0x052d, .bu = 0x05c7, .au = 0x0200,
303 .rv = 0x0340, .gv = 0x030c, .bv = 0x06d0, .av = 0x0200,
79e53945
JB		 304};
305
306static const struct video_levels pal_n_levels_composite = {
307 .blank = 225, .black = 267, .burst = 118,
308};
309
310static const struct color_conversion pal_n_csc_svideo = {
ba01079c
ZW		 311 .ry = 0x0332, .gy = 0x012d, .by = 0x07d3, .ay = 0x0133,
312 .ru = 0x076a, .gu = 0x0564, .bu = 0x030d, .au = 0x0200,
313 .rv = 0x037a, .gv = 0x033d, .bv = 0x06f6, .av = 0x0200,
79e53945
JB		 314};
315
316static const struct video_levels pal_n_levels_svideo = {
317 .blank = 266, .black = 316, .burst = 139,
318};
319
320/*
321 * Component connections
322 */
323static const struct color_conversion sdtv_csc_yprpb = {
ba01079c
ZW		 324 .ry = 0x0332, .gy = 0x012d, .by = 0x07d3, .ay = 0x0145,
325 .ru = 0x0559, .gu = 0x0353, .bu = 0x0100, .au = 0x0200,
326 .rv = 0x0100, .gv = 0x03ad, .bv = 0x074d, .av = 0x0200,
79e53945
JB		 327};
328
329static const struct color_conversion sdtv_csc_rgb = {
330 .ry = 0x0000, .gy = 0x0f00, .by = 0x0000, .ay = 0x0166,
331 .ru = 0x0000, .gu = 0x0000, .bu = 0x0f00, .au = 0x0166,
332 .rv = 0x0f00, .gv = 0x0000, .bv = 0x0000, .av = 0x0166,
333};
334
335static const struct color_conversion hdtv_csc_yprpb = {
ba01079c
ZW		 336 .ry = 0x05b3, .gy = 0x016e, .by = 0x0728, .ay = 0x0145,
337 .ru = 0x07d5, .gu = 0x038b, .bu = 0x0100, .au = 0x0200,
338 .rv = 0x0100, .gv = 0x03d1, .bv = 0x06bc, .av = 0x0200,
79e53945
JB		 339};
340
341static const struct color_conversion hdtv_csc_rgb = {
342 .ry = 0x0000, .gy = 0x0f00, .by = 0x0000, .ay = 0x0166,
343 .ru = 0x0000, .gu = 0x0000, .bu = 0x0f00, .au = 0x0166,
344 .rv = 0x0f00, .gv = 0x0000, .bv = 0x0000, .av = 0x0166,
345};
346
347static const struct video_levels component_levels = {
348 .blank = 279, .black = 279, .burst = 0,
349};
350
351
352struct tv_mode {
763a4a01 353 const char *name;
79e53945
JB		 354 int clock;
355 int refresh; /* in millihertz (for precision) */
356 u32 oversample;
357 int hsync_end, hblank_start, hblank_end, htotal;
358 bool progressive, trilevel_sync, component_only;
359 int vsync_start_f1, vsync_start_f2, vsync_len;
360 bool veq_ena;
361 int veq_start_f1, veq_start_f2, veq_len;
362 int vi_end_f1, vi_end_f2, nbr_end;
363 bool burst_ena;
364 int hburst_start, hburst_len;
365 int vburst_start_f1, vburst_end_f1;
366 int vburst_start_f2, vburst_end_f2;
367 int vburst_start_f3, vburst_end_f3;
368 int vburst_start_f4, vburst_end_f4;
369 /*
370 * subcarrier programming
371 */
372 int dda2_size, dda3_size, dda1_inc, dda2_inc, dda3_inc;
373 u32 sc_reset;
374 bool pal_burst;
375 /*
376 * blank/black levels
377 */
378 const struct video_levels *composite_levels, *svideo_levels;
379 const struct color_conversion *composite_color, *svideo_color;
380 const u32 *filter_table;
381 int max_srcw;
382};
383
384
385/*
386 * Sub carrier DDA
387 *
388 * I think this works as follows:
389 *
390 * subcarrier freq = pixel_clock * (dda1_inc + dda2_inc / dda2_size) / 4096
391 *
392 * Presumably, when dda3 is added in, it gets to adjust the dda2_inc value
393 *
394 * So,
395 * dda1_ideal = subcarrier/pixel * 4096
396 * dda1_inc = floor (dda1_ideal)
397 * dda2 = dda1_ideal - dda1_inc
398 *
399 * then pick a ratio for dda2 that gives the closest approximation. If
400 * you can't get close enough, you can play with dda3 as well. This
401 * seems likely to happen when dda2 is small as the jumps would be larger
402 *
403 * To invert this,
404 *
405 * pixel_clock = subcarrier * 4096 / (dda1_inc + dda2_inc / dda2_size)
406 *
407 * The constants below were all computed using a 107.520MHz clock
408 */
409
410/**
411 * Register programming values for TV modes.
412 *
413 * These values account for -1s required.
414 */
415
005568be 416static const struct tv_mode tv_modes[] = {
79e53945
JB		 417 {
418 .name = "NTSC-M",
ba01079c 419 .clock = 108000,
23bd15ec 420 .refresh = 59940,
79e53945
JB		 421 .oversample = TV_OVERSAMPLE_8X,
422 .component_only = 0,
423 /* 525 Lines, 60 Fields, 15.734KHz line, Sub-Carrier 3.580MHz */
424
425 .hsync_end = 64, .hblank_end = 124,
426 .hblank_start = 836, .htotal = 857,
427
428 .progressive = false, .trilevel_sync = false,
429
430 .vsync_start_f1 = 6, .vsync_start_f2 = 7,
431 .vsync_len = 6,
432
0206e353 433 .veq_ena = true, .veq_start_f1 = 0,
79e53945
JB		 434 .veq_start_f2 = 1, .veq_len = 18,
435
436 .vi_end_f1 = 20, .vi_end_f2 = 21,
437 .nbr_end = 240,
438
439 .burst_ena = true,
440 .hburst_start = 72, .hburst_len = 34,
441 .vburst_start_f1 = 9, .vburst_end_f1 = 240,
442 .vburst_start_f2 = 10, .vburst_end_f2 = 240,
443 .vburst_start_f3 = 9, .vburst_end_f3 = 240,
444 .vburst_start_f4 = 10, .vburst_end_f4 = 240,
445
446 /* desired 3.5800000 actual 3.5800000 clock 107.52 */
ba01079c
ZW		 447 .dda1_inc = 135,
448 .dda2_inc = 20800, .dda2_size = 27456,
79e53945
JB		 449 .dda3_inc = 0, .dda3_size = 0,
450 .sc_reset = TV_SC_RESET_EVERY_4,
451 .pal_burst = false,
452
453 .composite_levels = &ntsc_m_levels_composite,
454 .composite_color = &ntsc_m_csc_composite,
455 .svideo_levels = &ntsc_m_levels_svideo,
456 .svideo_color = &ntsc_m_csc_svideo,
457
458 .filter_table = filter_table,
459 },
460 {
461 .name = "NTSC-443",
ba01079c 462 .clock = 108000,
23bd15ec 463 .refresh = 59940,
79e53945
JB		 464 .oversample = TV_OVERSAMPLE_8X,
465 .component_only = 0,
466 /* 525 Lines, 60 Fields, 15.734KHz line, Sub-Carrier 4.43MHz */
467 .hsync_end = 64, .hblank_end = 124,
468 .hblank_start = 836, .htotal = 857,
469
470 .progressive = false, .trilevel_sync = false,
471
472 .vsync_start_f1 = 6, .vsync_start_f2 = 7,
473 .vsync_len = 6,
474
0206e353 475 .veq_ena = true, .veq_start_f1 = 0,
79e53945
JB		 476 .veq_start_f2 = 1, .veq_len = 18,
477
478 .vi_end_f1 = 20, .vi_end_f2 = 21,
479 .nbr_end = 240,
480
3ca87e82 481 .burst_ena = true,
79e53945
JB		 482 .hburst_start = 72, .hburst_len = 34,
483 .vburst_start_f1 = 9, .vburst_end_f1 = 240,
484 .vburst_start_f2 = 10, .vburst_end_f2 = 240,
485 .vburst_start_f3 = 9, .vburst_end_f3 = 240,
486 .vburst_start_f4 = 10, .vburst_end_f4 = 240,
487
488 /* desired 4.4336180 actual 4.4336180 clock 107.52 */
489 .dda1_inc = 168,
ba01079c
ZW		 490 .dda2_inc = 4093, .dda2_size = 27456,
491 .dda3_inc = 310, .dda3_size = 525,
492 .sc_reset = TV_SC_RESET_NEVER,
493 .pal_burst = false,
79e53945
JB		 494
495 .composite_levels = &ntsc_m_levels_composite,
496 .composite_color = &ntsc_m_csc_composite,
497 .svideo_levels = &ntsc_m_levels_svideo,
498 .svideo_color = &ntsc_m_csc_svideo,
499
500 .filter_table = filter_table,
501 },
502 {
503 .name = "NTSC-J",
ba01079c 504 .clock = 108000,
23bd15ec 505 .refresh = 59940,
79e53945
JB		 506 .oversample = TV_OVERSAMPLE_8X,
507 .component_only = 0,
508
509 /* 525 Lines, 60 Fields, 15.734KHz line, Sub-Carrier 3.580MHz */
510 .hsync_end = 64, .hblank_end = 124,
511 .hblank_start = 836, .htotal = 857,
512
513 .progressive = false, .trilevel_sync = false,
514
515 .vsync_start_f1 = 6, .vsync_start_f2 = 7,
516 .vsync_len = 6,
517
0206e353 518 .veq_ena = true, .veq_start_f1 = 0,
79e53945
JB		 519 .veq_start_f2 = 1, .veq_len = 18,
520
521 .vi_end_f1 = 20, .vi_end_f2 = 21,
522 .nbr_end = 240,
523
524 .burst_ena = true,
525 .hburst_start = 72, .hburst_len = 34,
526 .vburst_start_f1 = 9, .vburst_end_f1 = 240,
527 .vburst_start_f2 = 10, .vburst_end_f2 = 240,
528 .vburst_start_f3 = 9, .vburst_end_f3 = 240,
529 .vburst_start_f4 = 10, .vburst_end_f4 = 240,
530
531 /* desired 3.5800000 actual 3.5800000 clock 107.52 */
ba01079c
ZW		 532 .dda1_inc = 135,
533 .dda2_inc = 20800, .dda2_size = 27456,
79e53945
JB		 534 .dda3_inc = 0, .dda3_size = 0,
535 .sc_reset = TV_SC_RESET_EVERY_4,
536 .pal_burst = false,
537
538 .composite_levels = &ntsc_j_levels_composite,
539 .composite_color = &ntsc_j_csc_composite,
540 .svideo_levels = &ntsc_j_levels_svideo,
541 .svideo_color = &ntsc_j_csc_svideo,
542
543 .filter_table = filter_table,
544 },
545 {
546 .name = "PAL-M",
ba01079c 547 .clock = 108000,
23bd15ec 548 .refresh = 59940,
79e53945
JB		 549 .oversample = TV_OVERSAMPLE_8X,
550 .component_only = 0,
551
552 /* 525 Lines, 60 Fields, 15.734KHz line, Sub-Carrier 3.580MHz */
553 .hsync_end = 64, .hblank_end = 124,
554 .hblank_start = 836, .htotal = 857,
555
556 .progressive = false, .trilevel_sync = false,
557
558 .vsync_start_f1 = 6, .vsync_start_f2 = 7,
559 .vsync_len = 6,
560
0206e353 561 .veq_ena = true, .veq_start_f1 = 0,
79e53945
JB		 562 .veq_start_f2 = 1, .veq_len = 18,
563
564 .vi_end_f1 = 20, .vi_end_f2 = 21,
565 .nbr_end = 240,
566
567 .burst_ena = true,
568 .hburst_start = 72, .hburst_len = 34,
569 .vburst_start_f1 = 9, .vburst_end_f1 = 240,
570 .vburst_start_f2 = 10, .vburst_end_f2 = 240,
571 .vburst_start_f3 = 9, .vburst_end_f3 = 240,
572 .vburst_start_f4 = 10, .vburst_end_f4 = 240,
573
574 /* desired 3.5800000 actual 3.5800000 clock 107.52 */
ba01079c
ZW		 575 .dda1_inc = 135,
576 .dda2_inc = 16704, .dda2_size = 27456,
79e53945 577 .dda3_inc = 0, .dda3_size = 0,
ba01079c
ZW		 578 .sc_reset = TV_SC_RESET_EVERY_8,
579 .pal_burst = true,
79e53945
JB		 580
581 .composite_levels = &pal_m_levels_composite,
582 .composite_color = &pal_m_csc_composite,
583 .svideo_levels = &pal_m_levels_svideo,
584 .svideo_color = &pal_m_csc_svideo,
585
586 .filter_table = filter_table,
587 },
588 {
589 /* 625 Lines, 50 Fields, 15.625KHz line, Sub-Carrier 4.434MHz */
590 .name = "PAL-N",
ba01079c 591 .clock = 108000,
23bd15ec 592 .refresh = 50000,
79e53945
JB		 593 .oversample = TV_OVERSAMPLE_8X,
594 .component_only = 0,
595
596 .hsync_end = 64, .hblank_end = 128,
597 .hblank_start = 844, .htotal = 863,
598
599 .progressive = false, .trilevel_sync = false,
600
601
602 .vsync_start_f1 = 6, .vsync_start_f2 = 7,
603 .vsync_len = 6,
604
0206e353 605 .veq_ena = true, .veq_start_f1 = 0,
79e53945
JB		 606 .veq_start_f2 = 1, .veq_len = 18,
607
608 .vi_end_f1 = 24, .vi_end_f2 = 25,
609 .nbr_end = 286,
610
611 .burst_ena = true,
0206e353 612 .hburst_start = 73, .hburst_len = 34,
79e53945
JB		 613 .vburst_start_f1 = 8, .vburst_end_f1 = 285,
614 .vburst_start_f2 = 8, .vburst_end_f2 = 286,
615 .vburst_start_f3 = 9, .vburst_end_f3 = 286,
616 .vburst_start_f4 = 9, .vburst_end_f4 = 285,
617
618
619 /* desired 4.4336180 actual 4.4336180 clock 107.52 */
ba01079c
ZW		 620 .dda1_inc = 135,
621 .dda2_inc = 23578, .dda2_size = 27648,
622 .dda3_inc = 134, .dda3_size = 625,
79e53945
JB		 623 .sc_reset = TV_SC_RESET_EVERY_8,
624 .pal_burst = true,
625
626 .composite_levels = &pal_n_levels_composite,
627 .composite_color = &pal_n_csc_composite,
628 .svideo_levels = &pal_n_levels_svideo,
629 .svideo_color = &pal_n_csc_svideo,
630
631 .filter_table = filter_table,
632 },
633 {
634 /* 625 Lines, 50 Fields, 15.625KHz line, Sub-Carrier 4.434MHz */
635 .name = "PAL",
ba01079c 636 .clock = 108000,
23bd15ec 637 .refresh = 50000,
79e53945
JB		 638 .oversample = TV_OVERSAMPLE_8X,
639 .component_only = 0,
640
ba01079c 641 .hsync_end = 64, .hblank_end = 142,
79e53945
JB		 642 .hblank_start = 844, .htotal = 863,
643
644 .progressive = false, .trilevel_sync = false,
645
646 .vsync_start_f1 = 5, .vsync_start_f2 = 6,
647 .vsync_len = 5,
648
0206e353 649 .veq_ena = true, .veq_start_f1 = 0,
79e53945
JB		 650 .veq_start_f2 = 1, .veq_len = 15,
651
652 .vi_end_f1 = 24, .vi_end_f2 = 25,
653 .nbr_end = 286,
654
655 .burst_ena = true,
656 .hburst_start = 73, .hburst_len = 32,
657 .vburst_start_f1 = 8, .vburst_end_f1 = 285,
658 .vburst_start_f2 = 8, .vburst_end_f2 = 286,
659 .vburst_start_f3 = 9, .vburst_end_f3 = 286,
660 .vburst_start_f4 = 9, .vburst_end_f4 = 285,
661
662 /* desired 4.4336180 actual 4.4336180 clock 107.52 */
663 .dda1_inc = 168,
ba01079c
ZW		 664 .dda2_inc = 4122, .dda2_size = 27648,
665 .dda3_inc = 67, .dda3_size = 625,
79e53945
JB		 666 .sc_reset = TV_SC_RESET_EVERY_8,
667 .pal_burst = true,
668
669 .composite_levels = &pal_levels_composite,
670 .composite_color = &pal_csc_composite,
671 .svideo_levels = &pal_levels_svideo,
672 .svideo_color = &pal_csc_svideo,
673
674 .filter_table = filter_table,
675 },
79e53945
JB		 676 {
677 .name = "720p@60Hz",
678 .clock = 148800,
679 .refresh = 60000,
680 .oversample = TV_OVERSAMPLE_2X,
681 .component_only = 1,
682
683 .hsync_end = 80, .hblank_end = 300,
684 .hblank_start = 1580, .htotal = 1649,
685
0206e353 686 .progressive = true, .trilevel_sync = true,
79e53945
JB		 687
688 .vsync_start_f1 = 10, .vsync_start_f2 = 10,
689 .vsync_len = 10,
690
691 .veq_ena = false,
692
693 .vi_end_f1 = 29, .vi_end_f2 = 29,
694 .nbr_end = 719,
695
696 .burst_ena = false,
697
698 .filter_table = filter_table,
699 },
79e53945
JB		 700 {
701 .name = "720p@50Hz",
702 .clock = 148800,
703 .refresh = 50000,
704 .oversample = TV_OVERSAMPLE_2X,
705 .component_only = 1,
706
707 .hsync_end = 80, .hblank_end = 300,
708 .hblank_start = 1580, .htotal = 1979,
709
0206e353 710 .progressive = true, .trilevel_sync = true,
79e53945
JB		 711
712 .vsync_start_f1 = 10, .vsync_start_f2 = 10,
713 .vsync_len = 10,
714
715 .veq_ena = false,
716
717 .vi_end_f1 = 29, .vi_end_f2 = 29,
718 .nbr_end = 719,
719
720 .burst_ena = false,
721
722 .filter_table = filter_table,
723 .max_srcw = 800
724 },
725 {
726 .name = "1080i@50Hz",
727 .clock = 148800,
23bd15ec 728 .refresh = 50000,
79e53945
JB		 729 .oversample = TV_OVERSAMPLE_2X,
730 .component_only = 1,
731
732 .hsync_end = 88, .hblank_end = 235,
733 .hblank_start = 2155, .htotal = 2639,
734
0206e353 735 .progressive = false, .trilevel_sync = true,
79e53945
JB		 736
737 .vsync_start_f1 = 4, .vsync_start_f2 = 5,
738 .vsync_len = 10,
739
0206e353 740 .veq_ena = true, .veq_start_f1 = 4,
79e53945
JB		 741 .veq_start_f2 = 4, .veq_len = 10,
742
743
744 .vi_end_f1 = 21, .vi_end_f2 = 22,
745 .nbr_end = 539,
746
747 .burst_ena = false,
748
749 .filter_table = filter_table,
750 },
751 {
752 .name = "1080i@60Hz",
753 .clock = 148800,
23bd15ec 754 .refresh = 60000,
79e53945
JB		 755 .oversample = TV_OVERSAMPLE_2X,
756 .component_only = 1,
757
758 .hsync_end = 88, .hblank_end = 235,
759 .hblank_start = 2155, .htotal = 2199,
760
0206e353 761 .progressive = false, .trilevel_sync = true,
79e53945
JB		 762
763 .vsync_start_f1 = 4, .vsync_start_f2 = 5,
764 .vsync_len = 10,
765
0206e353 766 .veq_ena = true, .veq_start_f1 = 4,
79e53945
JB		 767 .veq_start_f2 = 4, .veq_len = 10,
768
769
770 .vi_end_f1 = 21, .vi_end_f2 = 22,
771 .nbr_end = 539,
772
773 .burst_ena = false,
774
79e53945
JB		 775 .filter_table = filter_table,
776 },
777};
778
ea5b213a
CW		 779static struct intel_tv *enc_to_intel_tv(struct drm_encoder *encoder)
780{
4ef69c7a 781 return container_of(encoder, struct intel_tv, base.base);
ea5b213a
CW		 782}
783
df0e9248
CW		 784static struct intel_tv *intel_attached_tv(struct drm_connector *connector)
785{
786 return container_of(intel_attached_encoder(connector),
787 struct intel_tv,
788 base);
789}
790
79e53945
JB		 791static void
792intel_tv_dpms(struct drm_encoder *encoder, int mode)
793{
794 struct drm_device *dev = encoder->dev;
795 struct drm_i915_private *dev_priv = dev->dev_private;
796
0206e353 797 switch (mode) {
79e53945
JB		 798 case DRM_MODE_DPMS_ON:
799 I915_WRITE(TV_CTL, I915_READ(TV_CTL) | TV_ENC_ENABLE);
800 break;
801 case DRM_MODE_DPMS_STANDBY:
802 case DRM_MODE_DPMS_SUSPEND:
803 case DRM_MODE_DPMS_OFF:
804 I915_WRITE(TV_CTL, I915_READ(TV_CTL) & ~TV_ENC_ENABLE);
805 break;
806 }
807}
808
79e53945 809static const struct tv_mode *
763a4a01 810intel_tv_mode_lookup(const char *tv_format)
79e53945
JB		 811{
812 int i;
813
3801a7fd 814 for (i = 0; i < ARRAY_SIZE(tv_modes); i++) {
79e53945
JB		 815 const struct tv_mode *tv_mode = &tv_modes[i];
816
817 if (!strcmp(tv_format, tv_mode->name))
818 return tv_mode;
819 }
820 return NULL;
821}
822
823static const struct tv_mode *
763a4a01 824intel_tv_mode_find(struct intel_tv *intel_tv)
79e53945 825{
ea5b213a 826 return intel_tv_mode_lookup(intel_tv->tv_format);
79e53945
JB		 827}
828
829static enum drm_mode_status
763a4a01
CW		 830intel_tv_mode_valid(struct drm_connector *connector,
831 struct drm_display_mode *mode)
79e53945 832{
df0e9248 833 struct intel_tv *intel_tv = intel_attached_tv(connector);
ea5b213a 834 const struct tv_mode *tv_mode = intel_tv_mode_find(intel_tv);
79e53945
JB		 835
836 /* Ensure TV refresh is close to desired refresh */
0d0884ce
ZY		 837 if (tv_mode && abs(tv_mode->refresh - drm_mode_vrefresh(mode) * 1000)
838 < 1000)
79e53945 839 return MODE_OK;
763a4a01 840
79e53945
JB		 841 return MODE_CLOCK_RANGE;
842}
843
844
845static bool
846intel_tv_mode_fixup(struct drm_encoder *encoder, struct drm_display_mode *mode,
847 struct drm_display_mode *adjusted_mode)
848{
849 struct drm_device *dev = encoder->dev;
850 struct drm_mode_config *drm_config = &dev->mode_config;
ea5b213a
CW		 851 struct intel_tv *intel_tv = enc_to_intel_tv(encoder);
852 const struct tv_mode *tv_mode = intel_tv_mode_find(intel_tv);
79e53945
JB		 853 struct drm_encoder *other_encoder;
854
855 if (!tv_mode)
856 return false;
857
858 /* FIXME: lock encoder list */
859 list_for_each_entry(other_encoder, &drm_config->encoder_list, head) {
860 if (other_encoder != encoder &&
861 other_encoder->crtc == encoder->crtc)
862 return false;
863 }
864
865 adjusted_mode->clock = tv_mode->clock;
866 return true;
867}
868
869static void
870intel_tv_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode,
871 struct drm_display_mode *adjusted_mode)
872{
873 struct drm_device *dev = encoder->dev;
874 struct drm_i915_private *dev_priv = dev->dev_private;
875 struct drm_crtc *crtc = encoder->crtc;
876 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ea5b213a
CW		 877 struct intel_tv *intel_tv = enc_to_intel_tv(encoder);
878 const struct tv_mode *tv_mode = intel_tv_mode_find(intel_tv);
79e53945
JB		 879 u32 tv_ctl;
880 u32 hctl1, hctl2, hctl3;
881 u32 vctl1, vctl2, vctl3, vctl4, vctl5, vctl6, vctl7;
882 u32 scctl1, scctl2, scctl3;
883 int i, j;
884 const struct video_levels *video_levels;
885 const struct color_conversion *color_conversion;
886 bool burst_ena;
9db4a9c7 887 int pipe = intel_crtc->pipe;
79e53945
JB		 888
889 if (!tv_mode)
890 return; /* can't happen (mode_prepare prevents this) */
891
d2d9f232
ZW		 892 tv_ctl = I915_READ(TV_CTL);
893 tv_ctl &= TV_CTL_SAVE;
79e53945 894
ea5b213a 895 switch (intel_tv->type) {
79e53945
JB		 896 default:
897 case DRM_MODE_CONNECTOR_Unknown:
898 case DRM_MODE_CONNECTOR_Composite:
899 tv_ctl |= TV_ENC_OUTPUT_COMPOSITE;
900 video_levels = tv_mode->composite_levels;
901 color_conversion = tv_mode->composite_color;
902 burst_ena = tv_mode->burst_ena;
903 break;
904 case DRM_MODE_CONNECTOR_Component:
905 tv_ctl |= TV_ENC_OUTPUT_COMPONENT;
906 video_levels = &component_levels;
907 if (tv_mode->burst_ena)
908 color_conversion = &sdtv_csc_yprpb;
909 else
910 color_conversion = &hdtv_csc_yprpb;
911 burst_ena = false;
912 break;
913 case DRM_MODE_CONNECTOR_SVIDEO:
914 tv_ctl |= TV_ENC_OUTPUT_SVIDEO;
915 video_levels = tv_mode->svideo_levels;
916 color_conversion = tv_mode->svideo_color;
917 burst_ena = tv_mode->burst_ena;
918 break;
919 }
920 hctl1 = (tv_mode->hsync_end << TV_HSYNC_END_SHIFT) |
921 (tv_mode->htotal << TV_HTOTAL_SHIFT);
922
923 hctl2 = (tv_mode->hburst_start << 16) |
924 (tv_mode->hburst_len << TV_HBURST_LEN_SHIFT);
925
926 if (burst_ena)
927 hctl2 |= TV_BURST_ENA;
928
929 hctl3 = (tv_mode->hblank_start << TV_HBLANK_START_SHIFT) |
930 (tv_mode->hblank_end << TV_HBLANK_END_SHIFT);
931
932 vctl1 = (tv_mode->nbr_end << TV_NBR_END_SHIFT) |
933 (tv_mode->vi_end_f1 << TV_VI_END_F1_SHIFT) |
934 (tv_mode->vi_end_f2 << TV_VI_END_F2_SHIFT);
935
936 vctl2 = (tv_mode->vsync_len << TV_VSYNC_LEN_SHIFT) |
937 (tv_mode->vsync_start_f1 << TV_VSYNC_START_F1_SHIFT) |
938 (tv_mode->vsync_start_f2 << TV_VSYNC_START_F2_SHIFT);
939
940 vctl3 = (tv_mode->veq_len << TV_VEQ_LEN_SHIFT) |
941 (tv_mode->veq_start_f1 << TV_VEQ_START_F1_SHIFT) |
942 (tv_mode->veq_start_f2 << TV_VEQ_START_F2_SHIFT);
943
944 if (tv_mode->veq_ena)
945 vctl3 |= TV_EQUAL_ENA;
946
947 vctl4 = (tv_mode->vburst_start_f1 << TV_VBURST_START_F1_SHIFT) |
948 (tv_mode->vburst_end_f1 << TV_VBURST_END_F1_SHIFT);
949
950 vctl5 = (tv_mode->vburst_start_f2 << TV_VBURST_START_F2_SHIFT) |
951 (tv_mode->vburst_end_f2 << TV_VBURST_END_F2_SHIFT);
952
953 vctl6 = (tv_mode->vburst_start_f3 << TV_VBURST_START_F3_SHIFT) |
954 (tv_mode->vburst_end_f3 << TV_VBURST_END_F3_SHIFT);
955
956 vctl7 = (tv_mode->vburst_start_f4 << TV_VBURST_START_F4_SHIFT) |
957 (tv_mode->vburst_end_f4 << TV_VBURST_END_F4_SHIFT);
958
959 if (intel_crtc->pipe == 1)
960 tv_ctl |= TV_ENC_PIPEB_SELECT;
961 tv_ctl |= tv_mode->oversample;
962
963 if (tv_mode->progressive)
964 tv_ctl |= TV_PROGRESSIVE;
965 if (tv_mode->trilevel_sync)
966 tv_ctl |= TV_TRILEVEL_SYNC;
967 if (tv_mode->pal_burst)
968 tv_ctl |= TV_PAL_BURST;
d271817b 969
79e53945 970 scctl1 = 0;
d271817b 971 if (tv_mode->dda1_inc)
79e53945 972 scctl1 |= TV_SC_DDA1_EN;
79e53945
JB		 973 if (tv_mode->dda2_inc)
974 scctl1 |= TV_SC_DDA2_EN;
79e53945
JB		 975 if (tv_mode->dda3_inc)
976 scctl1 |= TV_SC_DDA3_EN;
79e53945 977 scctl1 |= tv_mode->sc_reset;
d271817b
CW		 978 if (video_levels)
979 scctl1 |= video_levels->burst << TV_BURST_LEVEL_SHIFT;
79e53945
JB		 980 scctl1 |= tv_mode->dda1_inc << TV_SCDDA1_INC_SHIFT;
981
982 scctl2 = tv_mode->dda2_size << TV_SCDDA2_SIZE_SHIFT |
983 tv_mode->dda2_inc << TV_SCDDA2_INC_SHIFT;
984
985 scctl3 = tv_mode->dda3_size << TV_SCDDA3_SIZE_SHIFT |
986 tv_mode->dda3_inc << TV_SCDDA3_INC_SHIFT;
987
988 /* Enable two fixes for the chips that need them. */
989 if (dev->pci_device < 0x2772)
990 tv_ctl |= TV_ENC_C0_FIX | TV_ENC_SDP_FIX;
991
992 I915_WRITE(TV_H_CTL_1, hctl1);
993 I915_WRITE(TV_H_CTL_2, hctl2);
994 I915_WRITE(TV_H_CTL_3, hctl3);
995 I915_WRITE(TV_V_CTL_1, vctl1);
996 I915_WRITE(TV_V_CTL_2, vctl2);
997 I915_WRITE(TV_V_CTL_3, vctl3);
998 I915_WRITE(TV_V_CTL_4, vctl4);
999 I915_WRITE(TV_V_CTL_5, vctl5);
1000 I915_WRITE(TV_V_CTL_6, vctl6);
1001 I915_WRITE(TV_V_CTL_7, vctl7);
1002 I915_WRITE(TV_SC_CTL_1, scctl1);
1003 I915_WRITE(TV_SC_CTL_2, scctl2);
1004 I915_WRITE(TV_SC_CTL_3, scctl3);
1005
1006 if (color_conversion) {
1007 I915_WRITE(TV_CSC_Y, (color_conversion->ry << 16) |
1008 color_conversion->gy);
0206e353 1009 I915_WRITE(TV_CSC_Y2, (color_conversion->by << 16) |
79e53945
JB		 1010 color_conversion->ay);
1011 I915_WRITE(TV_CSC_U, (color_conversion->ru << 16) |
1012 color_conversion->gu);
1013 I915_WRITE(TV_CSC_U2, (color_conversion->bu << 16) |
1014 color_conversion->au);
1015 I915_WRITE(TV_CSC_V, (color_conversion->rv << 16) |
1016 color_conversion->gv);
1017 I915_WRITE(TV_CSC_V2, (color_conversion->bv << 16) |
1018 color_conversion->av);
1019 }
1020
a6c45cf0 1021 if (INTEL_INFO(dev)->gen >= 4)
d2d9f232
ZW		 1022 I915_WRITE(TV_CLR_KNOBS, 0x00404000);
1023 else
1024 I915_WRITE(TV_CLR_KNOBS, 0x00606000);
1025
79e53945
JB		 1026 if (video_levels)
1027 I915_WRITE(TV_CLR_LEVEL,
1028 ((video_levels->black << TV_BLACK_LEVEL_SHIFT) |
1029 (video_levels->blank << TV_BLANK_LEVEL_SHIFT)));
1030 {
9db4a9c7 1031 int pipeconf_reg = PIPECONF(pipe);
ccacfec6 1032 int dspcntr_reg = DSPCNTR(intel_crtc->plane);
79e53945
JB		 1033 int pipeconf = I915_READ(pipeconf_reg);
1034 int dspcntr = I915_READ(dspcntr_reg);
ccacfec6 1035 int dspbase_reg = DSPADDR(intel_crtc->plane);
79e53945
JB		 1036 int xpos = 0x0, ypos = 0x0;
1037 unsigned int xsize, ysize;
1038 /* Pipe must be off here */
1039 I915_WRITE(dspcntr_reg, dspcntr & ~DISPLAY_PLANE_ENABLE);
1040 /* Flush the plane changes */
1041 I915_WRITE(dspbase_reg, I915_READ(dspbase_reg));
1042
1043 /* Wait for vblank for the disable to take effect */
a6c45cf0 1044 if (IS_GEN2(dev))
9d0498a2 1045 intel_wait_for_vblank(dev, intel_crtc->pipe);
79e53945 1046
5eddb70b 1047 I915_WRITE(pipeconf_reg, pipeconf & ~PIPECONF_ENABLE);
79e53945 1048 /* Wait for vblank for the disable to take effect. */
58e10eb9 1049 intel_wait_for_pipe_off(dev, intel_crtc->pipe);
79e53945
JB		 1050
1051 /* Filter ctl must be set before TV_WIN_SIZE */
1052 I915_WRITE(TV_FILTER_CTL_1, TV_AUTO_SCALE);
1053 xsize = tv_mode->hblank_start - tv_mode->hblank_end;
1054 if (tv_mode->progressive)
1055 ysize = tv_mode->nbr_end + 1;
1056 else
1057 ysize = 2*tv_mode->nbr_end + 1;
1058
ea5b213a
CW		 1059 xpos += intel_tv->margin[TV_MARGIN_LEFT];
1060 ypos += intel_tv->margin[TV_MARGIN_TOP];
1061 xsize -= (intel_tv->margin[TV_MARGIN_LEFT] +
1062 intel_tv->margin[TV_MARGIN_RIGHT]);
1063 ysize -= (intel_tv->margin[TV_MARGIN_TOP] +
1064 intel_tv->margin[TV_MARGIN_BOTTOM]);
79e53945
JB		 1065 I915_WRITE(TV_WIN_POS, (xpos<<16)|ypos);
1066 I915_WRITE(TV_WIN_SIZE, (xsize<<16)|ysize);
1067
1068 I915_WRITE(pipeconf_reg, pipeconf);
1069 I915_WRITE(dspcntr_reg, dspcntr);
1070 /* Flush the plane changes */
1071 I915_WRITE(dspbase_reg, I915_READ(dspbase_reg));
1072 }
1073
1074 j = 0;
1075 for (i = 0; i < 60; i++)
1076 I915_WRITE(TV_H_LUMA_0 + (i<<2), tv_mode->filter_table[j++]);
1077 for (i = 0; i < 60; i++)
1078 I915_WRITE(TV_H_CHROMA_0 + (i<<2), tv_mode->filter_table[j++]);
1079 for (i = 0; i < 43; i++)
1080 I915_WRITE(TV_V_LUMA_0 + (i<<2), tv_mode->filter_table[j++]);
1081 for (i = 0; i < 43; i++)
1082 I915_WRITE(TV_V_CHROMA_0 + (i<<2), tv_mode->filter_table[j++]);
b8ed2a4f 1083 I915_WRITE(TV_DAC, I915_READ(TV_DAC) & TV_DAC_SAVE);
79e53945
JB		 1084 I915_WRITE(TV_CTL, tv_ctl);
1085}
1086
1087static const struct drm_display_mode reported_modes[] = {
1088 {
1089 .name = "NTSC 480i",
1090 .clock = 107520,
1091 .hdisplay = 1280,
1092 .hsync_start = 1368,
1093 .hsync_end = 1496,
1094 .htotal = 1712,
1095
1096 .vdisplay = 1024,
1097 .vsync_start = 1027,
1098 .vsync_end = 1034,
1099 .vtotal = 1104,
1100 .type = DRM_MODE_TYPE_DRIVER,
1101 },
1102};
1103
1104/**
1105 * Detects TV presence by checking for load.
1106 *
1107 * Requires that the current pipe's DPLL is active.
1108
1109 * \return true if TV is connected.
1110 * \return false if TV is disconnected.
1111 */
1112static int
0206e353 1113intel_tv_detect_type(struct intel_tv *intel_tv,
8102e126 1114 struct drm_connector *connector)
79e53945 1115{
4ef69c7a 1116 struct drm_encoder *encoder = &intel_tv->base.base;
835bff7e
KP		 1117 struct drm_crtc *crtc = encoder->crtc;
1118 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
79e53945
JB		 1119 struct drm_device *dev = encoder->dev;
1120 struct drm_i915_private *dev_priv = dev->dev_private;
1121 unsigned long irqflags;
1122 u32 tv_ctl, save_tv_ctl;
1123 u32 tv_dac, save_tv_dac;
974b9331 1124 int type;
79e53945
JB		 1125
1126 /* Disable TV interrupts around load detect or we'll recurse */
8102e126
CW		 1127 if (connector->polled & DRM_CONNECTOR_POLL_HPD) {
1128 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
1129 i915_disable_pipestat(dev_priv, 0,
1130 PIPE_HOTPLUG_INTERRUPT_ENABLE |
1131 PIPE_HOTPLUG_TV_INTERRUPT_ENABLE);
1132 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
1133 }
79e53945 1134
974b9331
CW		 1135 save_tv_dac = tv_dac = I915_READ(TV_DAC);
1136 save_tv_ctl = tv_ctl = I915_READ(TV_CTL);
1137
1138 /* Poll for TV detection */
1139 tv_ctl &= ~(TV_ENC_ENABLE | TV_TEST_MODE_MASK);
8ed9a5bc 1140 tv_ctl |= TV_TEST_MODE_MONITOR_DETECT;
835bff7e
KP		 1141 if (intel_crtc->pipe == 1)
1142 tv_ctl |= TV_ENC_PIPEB_SELECT;
1143 else
1144 tv_ctl &= ~TV_ENC_PIPEB_SELECT;
974b9331
CW		 1145
1146 tv_dac &= ~(TVDAC_SENSE_MASK | DAC_A_MASK | DAC_B_MASK | DAC_C_MASK);
8ed9a5bc 1147 tv_dac |= (TVDAC_STATE_CHG_EN |
1148 TVDAC_A_SENSE_CTL |
1149 TVDAC_B_SENSE_CTL |
1150 TVDAC_C_SENSE_CTL |
1151 DAC_CTL_OVERRIDE |
1152 DAC_A_0_7_V |
1153 DAC_B_0_7_V |
1154 DAC_C_0_7_V);
974b9331 1155
d42c9e2c
DV		 1156
1157 /*
1158 * The TV sense state should be cleared to zero on cantiga platform. Otherwise
1159 * the TV is misdetected. This is hardware requirement.
1160 */
1161 if (IS_GM45(dev))
1162 tv_dac &= ~(TVDAC_STATE_CHG_EN | TVDAC_A_SENSE_CTL |
1163 TVDAC_B_SENSE_CTL | TVDAC_C_SENSE_CTL);
1164
8ed9a5bc 1165 I915_WRITE(TV_CTL, tv_ctl);
1166 I915_WRITE(TV_DAC, tv_dac);
4f233eff 1167 POSTING_READ(TV_DAC);
4f233eff 1168
29e1316a
CW		 1169 intel_wait_for_vblank(intel_tv->base.base.dev,
1170 to_intel_crtc(intel_tv->base.base.crtc)->pipe);
1171
974b9331 1172 type = -1;
2bf71160
KP		 1173 tv_dac = I915_READ(TV_DAC);
1174 DRM_DEBUG_KMS("TV detected: %x, %x\n", tv_ctl, tv_dac);
1175 /*
1176 * A B C
1177 * 0 1 1 Composite
1178 * 1 0 X svideo
1179 * 0 0 0 Component
1180 */
1181 if ((tv_dac & TVDAC_SENSE_MASK) == (TVDAC_B_SENSE | TVDAC_C_SENSE)) {
1182 DRM_DEBUG_KMS("Detected Composite TV connection\n");
1183 type = DRM_MODE_CONNECTOR_Composite;
1184 } else if ((tv_dac & (TVDAC_A_SENSE|TVDAC_B_SENSE)) == TVDAC_A_SENSE) {
1185 DRM_DEBUG_KMS("Detected S-Video TV connection\n");
1186 type = DRM_MODE_CONNECTOR_SVIDEO;
1187 } else if ((tv_dac & TVDAC_SENSE_MASK) == 0) {
1188 DRM_DEBUG_KMS("Detected Component TV connection\n");
1189 type = DRM_MODE_CONNECTOR_Component;
1190 } else {
1191 DRM_DEBUG_KMS("Unrecognised TV connection\n");
1192 type = -1;
79e53945
JB		 1193 }
1194
974b9331
CW		 1195 I915_WRITE(TV_DAC, save_tv_dac & ~TVDAC_STATE_CHG_EN);
1196 I915_WRITE(TV_CTL, save_tv_ctl);
bf2125e2
DV		 1197 POSTING_READ(TV_CTL);
1198
1199 /* For unknown reasons the hw barfs if we don't do this vblank wait. */
1200 intel_wait_for_vblank(intel_tv->base.base.dev,
1201 to_intel_crtc(intel_tv->base.base.crtc)->pipe);
974b9331 1202
79e53945 1203 /* Restore interrupt config */
8102e126
CW		 1204 if (connector->polled & DRM_CONNECTOR_POLL_HPD) {
1205 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
1206 i915_enable_pipestat(dev_priv, 0,
1207 PIPE_HOTPLUG_INTERRUPT_ENABLE |
1208 PIPE_HOTPLUG_TV_INTERRUPT_ENABLE);
1209 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
1210 }
79e53945
JB		 1211
1212 return type;
1213}
1214
213c2e64
ML		 1215/*
1216 * Here we set accurate tv format according to connector type
1217 * i.e Component TV should not be assigned by NTSC or PAL
1218 */
1219static void intel_tv_find_better_format(struct drm_connector *connector)
1220{
df0e9248 1221 struct intel_tv *intel_tv = intel_attached_tv(connector);
ea5b213a 1222 const struct tv_mode *tv_mode = intel_tv_mode_find(intel_tv);
213c2e64
ML		 1223 int i;
1224
ea5b213a 1225 if ((intel_tv->type == DRM_MODE_CONNECTOR_Component) ==
213c2e64
ML		 1226 tv_mode->component_only)
1227 return;
1228
1229
1230 for (i = 0; i < sizeof(tv_modes) / sizeof(*tv_modes); i++) {
1231 tv_mode = tv_modes + i;
1232
ea5b213a 1233 if ((intel_tv->type == DRM_MODE_CONNECTOR_Component) ==
213c2e64
ML		 1234 tv_mode->component_only)
1235 break;
1236 }
1237
ea5b213a 1238 intel_tv->tv_format = tv_mode->name;
213c2e64
ML		 1239 drm_connector_property_set_value(connector,
1240 connector->dev->mode_config.tv_mode_property, i);
1241}
1242
79e53945
JB		 1243/**
1244 * Detect the TV connection.
1245 *
1246 * Currently this always returns CONNECTOR_STATUS_UNKNOWN, as we need to be sure
1247 * we have a pipe programmed in order to probe the TV.
1248 */
1249static enum drm_connector_status
930a9e28 1250intel_tv_detect(struct drm_connector *connector, bool force)
79e53945 1251{
79e53945 1252 struct drm_display_mode mode;
df0e9248 1253 struct intel_tv *intel_tv = intel_attached_tv(connector);
ea5b213a 1254 int type;
79e53945
JB		 1255
1256 mode = reported_modes[0];
79e53945 1257
38de45c5 1258 if (force) {
8261b191 1259 struct intel_load_detect_pipe tmp;
ea5b213a 1260
7173188d 1261 if (intel_get_load_detect_pipe(&intel_tv->base, connector,
8261b191 1262 &mode, &tmp)) {
8102e126 1263 type = intel_tv_detect_type(intel_tv, connector);
8261b191
CW		 1264 intel_release_load_detect_pipe(&intel_tv->base,
1265 connector,
1266 &tmp);
79e53945 1267 } else
7b334fcb
CW		 1268 return connector_status_unknown;
1269 } else
1270 return connector->status;
bf5a269a 1271
79e53945
JB		 1272 if (type < 0)
1273 return connector_status_disconnected;
1274
d5627663 1275 intel_tv->type = type;
213c2e64 1276 intel_tv_find_better_format(connector);
d5627663 1277
79e53945
JB		 1278 return connector_status_connected;
1279}
1280
763a4a01
CW		 1281static const struct input_res {
1282 const char *name;
79e53945 1283 int w, h;
763a4a01 1284} input_res_table[] = {
79e53945
JB		 1285 {"640x480", 640, 480},
1286 {"800x600", 800, 600},
1287 {"1024x768", 1024, 768},
1288 {"1280x1024", 1280, 1024},
1289 {"848x480", 848, 480},
1290 {"1280x720", 1280, 720},
1291 {"1920x1080", 1920, 1080},
1292};
1293
bcae2ca8 1294/*
1295 * Chose preferred mode according to line number of TV format
1296 */
1297static void
1298intel_tv_chose_preferred_modes(struct drm_connector *connector,
1299 struct drm_display_mode *mode_ptr)
1300{
df0e9248 1301 struct intel_tv *intel_tv = intel_attached_tv(connector);
ea5b213a 1302 const struct tv_mode *tv_mode = intel_tv_mode_find(intel_tv);
bcae2ca8 1303
1304 if (tv_mode->nbr_end < 480 && mode_ptr->vdisplay == 480)
1305 mode_ptr->type |= DRM_MODE_TYPE_PREFERRED;
1306 else if (tv_mode->nbr_end > 480) {
1307 if (tv_mode->progressive == true && tv_mode->nbr_end < 720) {
1308 if (mode_ptr->vdisplay == 720)
1309 mode_ptr->type |= DRM_MODE_TYPE_PREFERRED;
1310 } else if (mode_ptr->vdisplay == 1080)
1311 mode_ptr->type |= DRM_MODE_TYPE_PREFERRED;
1312 }
1313}
1314
79e53945
JB		 1315/**
1316 * Stub get_modes function.
1317 *
1318 * This should probably return a set of fixed modes, unless we can figure out
1319 * how to probe modes off of TV connections.
1320 */
1321
1322static int
1323intel_tv_get_modes(struct drm_connector *connector)
1324{
1325 struct drm_display_mode *mode_ptr;
df0e9248 1326 struct intel_tv *intel_tv = intel_attached_tv(connector);
ea5b213a 1327 const struct tv_mode *tv_mode = intel_tv_mode_find(intel_tv);
02c5dd98
ZW		 1328 int j, count = 0;
1329 u64 tmp;
79e53945 1330
04ad327f 1331 for (j = 0; j < ARRAY_SIZE(input_res_table);
79e53945 1332 j++) {
763a4a01 1333 const struct input_res *input = &input_res_table[j];
79e53945
JB		 1334 unsigned int hactive_s = input->w;
1335 unsigned int vactive_s = input->h;
1336
1337 if (tv_mode->max_srcw && input->w > tv_mode->max_srcw)
1338 continue;
1339
1340 if (input->w > 1024 && (!tv_mode->progressive
1341 && !tv_mode->component_only))
1342 continue;
1343
02c5dd98
ZW		 1344 mode_ptr = drm_mode_create(connector->dev);
1345 if (!mode_ptr)
1346 continue;
79e53945
JB		 1347 strncpy(mode_ptr->name, input->name, DRM_DISPLAY_MODE_LEN);
1348
1349 mode_ptr->hdisplay = hactive_s;
1350 mode_ptr->hsync_start = hactive_s + 1;
1351 mode_ptr->hsync_end = hactive_s + 64;
1352 if (mode_ptr->hsync_end <= mode_ptr->hsync_start)
1353 mode_ptr->hsync_end = mode_ptr->hsync_start + 1;
1354 mode_ptr->htotal = hactive_s + 96;
1355
1356 mode_ptr->vdisplay = vactive_s;
1357 mode_ptr->vsync_start = vactive_s + 1;
1358 mode_ptr->vsync_end = vactive_s + 32;
1359 if (mode_ptr->vsync_end <= mode_ptr->vsync_start)
1360 mode_ptr->vsync_end = mode_ptr->vsync_start + 1;
1361 mode_ptr->vtotal = vactive_s + 33;
1362
02c5dd98
ZW		 1363 tmp = (u64) tv_mode->refresh * mode_ptr->vtotal;
1364 tmp *= mode_ptr->htotal;
1365 tmp = div_u64(tmp, 1000000);
1366 mode_ptr->clock = (int) tmp;
79e53945
JB		 1367
1368 mode_ptr->type = DRM_MODE_TYPE_DRIVER;
bcae2ca8 1369 intel_tv_chose_preferred_modes(connector, mode_ptr);
79e53945 1370 drm_mode_probed_add(connector, mode_ptr);
02c5dd98 1371 count++;
79e53945
JB		 1372 }
1373
02c5dd98 1374 return count;
79e53945
JB		 1375}
1376
1377static void
0206e353 1378intel_tv_destroy(struct drm_connector *connector)
79e53945 1379{
79e53945
JB		 1380 drm_sysfs_connector_remove(connector);
1381 drm_connector_cleanup(connector);
0c41ee2b 1382 kfree(connector);
79e53945
JB		 1383}
1384
1385
1386static int
1387intel_tv_set_property(struct drm_connector *connector, struct drm_property *property,
1388 uint64_t val)
1389{
1390 struct drm_device *dev = connector->dev;
df0e9248
CW		 1391 struct intel_tv *intel_tv = intel_attached_tv(connector);
1392 struct drm_crtc *crtc = intel_tv->base.base.crtc;
79e53945 1393 int ret = 0;
ebcc8f2e 1394 bool changed = false;
79e53945
JB		 1395
1396 ret = drm_connector_property_set_value(connector, property, val);
1397 if (ret < 0)
1398 goto out;
1399
ebcc8f2e 1400 if (property == dev->mode_config.tv_left_margin_property &&
ea5b213a
CW		 1401 intel_tv->margin[TV_MARGIN_LEFT] != val) {
1402 intel_tv->margin[TV_MARGIN_LEFT] = val;
ebcc8f2e
ZW		 1403 changed = true;
1404 } else if (property == dev->mode_config.tv_right_margin_property &&
ea5b213a
CW		 1405 intel_tv->margin[TV_MARGIN_RIGHT] != val) {
1406 intel_tv->margin[TV_MARGIN_RIGHT] = val;
ebcc8f2e
ZW		 1407 changed = true;
1408 } else if (property == dev->mode_config.tv_top_margin_property &&
ea5b213a
CW		 1409 intel_tv->margin[TV_MARGIN_TOP] != val) {
1410 intel_tv->margin[TV_MARGIN_TOP] = val;
ebcc8f2e
ZW		 1411 changed = true;
1412 } else if (property == dev->mode_config.tv_bottom_margin_property &&
ea5b213a
CW		 1413 intel_tv->margin[TV_MARGIN_BOTTOM] != val) {
1414 intel_tv->margin[TV_MARGIN_BOTTOM] = val;
ebcc8f2e
ZW		 1415 changed = true;
1416 } else if (property == dev->mode_config.tv_mode_property) {
2991196f 1417 if (val >= ARRAY_SIZE(tv_modes)) {
79e53945
JB		 1418 ret = -EINVAL;
1419 goto out;
1420 }
ea5b213a 1421 if (!strcmp(intel_tv->tv_format, tv_modes[val].name))
ebcc8f2e
ZW		 1422 goto out;
1423
ea5b213a 1424 intel_tv->tv_format = tv_modes[val].name;
ebcc8f2e 1425 changed = true;
79e53945
JB		 1426 } else {
1427 ret = -EINVAL;
1428 goto out;
1429 }
1430
7d6ff785
ZW		 1431 if (changed && crtc)
1432 drm_crtc_helper_set_mode(crtc, &crtc->mode, crtc->x,
1433 crtc->y, crtc->fb);
79e53945
JB		 1434out:
1435 return ret;
1436}
1437
1438static const struct drm_encoder_helper_funcs intel_tv_helper_funcs = {
1439 .dpms = intel_tv_dpms,
1440 .mode_fixup = intel_tv_mode_fixup,
1441 .prepare = intel_encoder_prepare,
1442 .mode_set = intel_tv_mode_set,
1443 .commit = intel_encoder_commit,
1444};
1445
1446static const struct drm_connector_funcs intel_tv_connector_funcs = {
c9fb15f6 1447 .dpms = drm_helper_connector_dpms,
79e53945
JB		 1448 .detect = intel_tv_detect,
1449 .destroy = intel_tv_destroy,
1450 .set_property = intel_tv_set_property,
1451 .fill_modes = drm_helper_probe_single_connector_modes,
1452};
1453
1454static const struct drm_connector_helper_funcs intel_tv_connector_helper_funcs = {
1455 .mode_valid = intel_tv_mode_valid,
1456 .get_modes = intel_tv_get_modes,
df0e9248 1457 .best_encoder = intel_best_encoder,
79e53945
JB		 1458};
1459
79e53945 1460static const struct drm_encoder_funcs intel_tv_enc_funcs = {
ea5b213a 1461 .destroy = intel_encoder_destroy,
79e53945
JB		 1462};
1463
c3561438
ZY		 1464/*
1465 * Enumerate the child dev array parsed from VBT to check whether
1466 * the integrated TV is present.
1467 * If it is present, return 1.
1468 * If it is not present, return false.
1469 * If no child dev is parsed from VBT, it assumes that the TV is present.
1470 */
6e36595a 1471static int tv_is_present_in_vbt(struct drm_device *dev)
c3561438
ZY		 1472{
1473 struct drm_i915_private *dev_priv = dev->dev_private;
1474 struct child_device_config *p_child;
1475 int i, ret;
1476
1477 if (!dev_priv->child_dev_num)
1478 return 1;
1479
1480 ret = 0;
1481 for (i = 0; i < dev_priv->child_dev_num; i++) {
1482 p_child = dev_priv->child_dev + i;
1483 /*
1484 * If the device type is not TV, continue.
1485 */
1486 if (p_child->device_type != DEVICE_TYPE_INT_TV &&
1487 p_child->device_type != DEVICE_TYPE_TV)
1488 continue;
1489 /* Only when the addin_offset is non-zero, it is regarded
1490 * as present.
1491 */
1492 if (p_child->addin_offset) {
1493 ret = 1;
1494 break;
1495 }
1496 }
1497 return ret;
1498}
79e53945
JB		 1499
1500void
1501intel_tv_init(struct drm_device *dev)
1502{
1503 struct drm_i915_private *dev_priv = dev->dev_private;
1504 struct drm_connector *connector;
ea5b213a 1505 struct intel_tv *intel_tv;
21d40d37 1506 struct intel_encoder *intel_encoder;
0c41ee2b 1507 struct intel_connector *intel_connector;
79e53945 1508 u32 tv_dac_on, tv_dac_off, save_tv_dac;
763a4a01 1509 char *tv_format_names[ARRAY_SIZE(tv_modes)];
79e53945
JB		 1510 int i, initial_mode = 0;
1511
1512 if ((I915_READ(TV_CTL) & TV_FUSE_STATE_MASK) == TV_FUSE_STATE_DISABLED)
1513 return;
1514
c3561438
ZY		 1515 if (!tv_is_present_in_vbt(dev)) {
1516 DRM_DEBUG_KMS("Integrated TV is not present.\n");
1517 return;
1518 }
79e53945
JB		 1519 /* Even if we have an encoder we may not have a connector */
1520 if (!dev_priv->int_tv_support)
1521 return;
1522
1523 /*
1524 * Sanity check the TV output by checking to see if the
1525 * DAC register holds a value
1526 */
1527 save_tv_dac = I915_READ(TV_DAC);
1528
1529 I915_WRITE(TV_DAC, save_tv_dac | TVDAC_STATE_CHG_EN);
1530 tv_dac_on = I915_READ(TV_DAC);
1531
1532 I915_WRITE(TV_DAC, save_tv_dac & ~TVDAC_STATE_CHG_EN);
1533 tv_dac_off = I915_READ(TV_DAC);
1534
1535 I915_WRITE(TV_DAC, save_tv_dac);
1536
1537 /*
1538 * If the register does not hold the state change enable
1539 * bit, (either as a 0 or a 1), assume it doesn't really
1540 * exist
1541 */
1542 if ((tv_dac_on & TVDAC_STATE_CHG_EN) == 0 ||
1543 (tv_dac_off & TVDAC_STATE_CHG_EN) != 0)
1544 return;
1545
ea5b213a
CW		 1546 intel_tv = kzalloc(sizeof(struct intel_tv), GFP_KERNEL);
1547 if (!intel_tv) {
79e53945
JB		 1548 return;
1549 }
f8aed700 1550
0c41ee2b
ZW		 1551 intel_connector = kzalloc(sizeof(struct intel_connector), GFP_KERNEL);
1552 if (!intel_connector) {
ea5b213a 1553 kfree(intel_tv);
0c41ee2b
ZW		 1554 return;
1555 }
1556
ea5b213a 1557 intel_encoder = &intel_tv->base;
0c41ee2b 1558 connector = &intel_connector->base;
79e53945 1559
8102e126
CW		 1560 /* The documentation, for the older chipsets at least, recommend
1561 * using a polling method rather than hotplug detection for TVs.
1562 * This is because in order to perform the hotplug detection, the PLLs
1563 * for the TV must be kept alive increasing power drain and starving
1564 * bandwidth from other encoders. Notably for instance, it causes
1565 * pipe underruns on Crestline when this encoder is supposedly idle.
1566 *
1567 * More recent chipsets favour HDMI rather than integrated S-Video.
1568 */
89ea42d7 1569 connector->polled = DRM_CONNECTOR_POLL_CONNECT;
8102e126 1570
79e53945
JB		 1571 drm_connector_init(dev, connector, &intel_tv_connector_funcs,
1572 DRM_MODE_CONNECTOR_SVIDEO);
1573
4ef69c7a 1574 drm_encoder_init(dev, &intel_encoder->base, &intel_tv_enc_funcs,
79e53945
JB		 1575 DRM_MODE_ENCODER_TVDAC);
1576
df0e9248 1577 intel_connector_attach_encoder(intel_connector, intel_encoder);
21d40d37
EA		 1578 intel_encoder->type = INTEL_OUTPUT_TVOUT;
1579 intel_encoder->crtc_mask = (1 << 0) | (1 << 1);
1580 intel_encoder->clone_mask = (1 << INTEL_TV_CLONE_BIT);
4ef69c7a
CW		 1581 intel_encoder->base.possible_crtcs = ((1 << 0) | (1 << 1));
1582 intel_encoder->base.possible_clones = (1 << INTEL_OUTPUT_TVOUT);
ea5b213a 1583 intel_tv->type = DRM_MODE_CONNECTOR_Unknown;
79e53945
JB		 1584
1585 /* BIOS margin values */
ea5b213a
CW		 1586 intel_tv->margin[TV_MARGIN_LEFT] = 54;
1587 intel_tv->margin[TV_MARGIN_TOP] = 36;
1588 intel_tv->margin[TV_MARGIN_RIGHT] = 46;
1589 intel_tv->margin[TV_MARGIN_BOTTOM] = 37;
79e53945 1590
763a4a01 1591 intel_tv->tv_format = tv_modes[initial_mode].name;
79e53945 1592
4ef69c7a 1593 drm_encoder_helper_add(&intel_encoder->base, &intel_tv_helper_funcs);
79e53945
JB		 1594 drm_connector_helper_add(connector, &intel_tv_connector_helper_funcs);
1595 connector->interlace_allowed = false;
1596 connector->doublescan_allowed = false;
1597
1598 /* Create TV properties then attach current values */
2991196f 1599 for (i = 0; i < ARRAY_SIZE(tv_modes); i++)
763a4a01
CW		 1600 tv_format_names[i] = (char *)tv_modes[i].name;
1601 drm_mode_create_tv_properties(dev,
1602 ARRAY_SIZE(tv_modes),
1603 tv_format_names);
79e53945
JB		 1604
1605 drm_connector_attach_property(connector, dev->mode_config.tv_mode_property,
1606 initial_mode);
1607 drm_connector_attach_property(connector,
1608 dev->mode_config.tv_left_margin_property,
ea5b213a 1609 intel_tv->margin[TV_MARGIN_LEFT]);
79e53945
JB		 1610 drm_connector_attach_property(connector,
1611 dev->mode_config.tv_top_margin_property,
ea5b213a 1612 intel_tv->margin[TV_MARGIN_TOP]);
79e53945
JB		 1613 drm_connector_attach_property(connector,
1614 dev->mode_config.tv_right_margin_property,
ea5b213a 1615 intel_tv->margin[TV_MARGIN_RIGHT]);
79e53945
JB		 1616 drm_connector_attach_property(connector,
1617 dev->mode_config.tv_bottom_margin_property,
ea5b213a 1618 intel_tv->margin[TV_MARGIN_BOTTOM]);
79e53945
JB		 1619 drm_sysfs_connector_add(connector);
1620}
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