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79e53945 JB |
1 | /* |
2 | * Copyright © 2006-2008 Intel Corporation | |
3 | * Jesse Barnes <jesse.barnes@intel.com> | |
4 | * | |
5 | * Permission is hereby granted, free of charge, to any person obtaining a | |
6 | * copy of this software and associated documentation files (the "Software"), | |
7 | * to deal in the Software without restriction, including without limitation | |
8 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
9 | * and/or sell copies of the Software, and to permit persons to whom the | |
10 | * Software is furnished to do so, subject to the following conditions: | |
11 | * | |
12 | * The above copyright notice and this permission notice (including the next | |
13 | * paragraph) shall be included in all copies or substantial portions of the | |
14 | * Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
21 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | |
22 | * DEALINGS IN THE SOFTWARE. | |
23 | * | |
24 | * Authors: | |
25 | * Eric Anholt <eric@anholt.net> | |
26 | * | |
27 | */ | |
28 | ||
29 | /** @file | |
30 | * Integrated TV-out support for the 915GM and 945GM. | |
31 | */ | |
32 | ||
760285e7 | 33 | #include <drm/drmP.h> |
c6f95f27 | 34 | #include <drm/drm_atomic_helper.h> |
760285e7 DH |
35 | #include <drm/drm_crtc.h> |
36 | #include <drm/drm_edid.h> | |
79e53945 | 37 | #include "intel_drv.h" |
760285e7 | 38 | #include <drm/i915_drm.h> |
79e53945 JB |
39 | #include "i915_drv.h" |
40 | ||
41 | enum tv_margin { | |
42 | TV_MARGIN_LEFT, TV_MARGIN_TOP, | |
43 | TV_MARGIN_RIGHT, TV_MARGIN_BOTTOM | |
44 | }; | |
45 | ||
46 | /** Private structure for the integrated TV support */ | |
ea5b213a CW |
47 | struct intel_tv { |
48 | struct intel_encoder base; | |
49 | ||
79e53945 | 50 | int type; |
763a4a01 | 51 | const char *tv_format; |
79e53945 JB |
52 | int margin[4]; |
53 | u32 save_TV_H_CTL_1; | |
54 | u32 save_TV_H_CTL_2; | |
55 | u32 save_TV_H_CTL_3; | |
56 | u32 save_TV_V_CTL_1; | |
57 | u32 save_TV_V_CTL_2; | |
58 | u32 save_TV_V_CTL_3; | |
59 | u32 save_TV_V_CTL_4; | |
60 | u32 save_TV_V_CTL_5; | |
61 | u32 save_TV_V_CTL_6; | |
62 | u32 save_TV_V_CTL_7; | |
63 | u32 save_TV_SC_CTL_1, save_TV_SC_CTL_2, save_TV_SC_CTL_3; | |
64 | ||
65 | u32 save_TV_CSC_Y; | |
66 | u32 save_TV_CSC_Y2; | |
67 | u32 save_TV_CSC_U; | |
68 | u32 save_TV_CSC_U2; | |
69 | u32 save_TV_CSC_V; | |
70 | u32 save_TV_CSC_V2; | |
71 | u32 save_TV_CLR_KNOBS; | |
72 | u32 save_TV_CLR_LEVEL; | |
73 | u32 save_TV_WIN_POS; | |
74 | u32 save_TV_WIN_SIZE; | |
75 | u32 save_TV_FILTER_CTL_1; | |
76 | u32 save_TV_FILTER_CTL_2; | |
77 | u32 save_TV_FILTER_CTL_3; | |
78 | ||
79 | u32 save_TV_H_LUMA[60]; | |
80 | u32 save_TV_H_CHROMA[60]; | |
81 | u32 save_TV_V_LUMA[43]; | |
82 | u32 save_TV_V_CHROMA[43]; | |
83 | ||
84 | u32 save_TV_DAC; | |
85 | u32 save_TV_CTL; | |
86 | }; | |
87 | ||
88 | struct video_levels { | |
db49296b TU |
89 | u16 blank, black; |
90 | u8 burst; | |
79e53945 JB |
91 | }; |
92 | ||
93 | struct color_conversion { | |
94 | u16 ry, gy, by, ay; | |
95 | u16 ru, gu, bu, au; | |
96 | u16 rv, gv, bv, av; | |
97 | }; | |
98 | ||
99 | static const u32 filter_table[] = { | |
100 | 0xB1403000, 0x2E203500, 0x35002E20, 0x3000B140, | |
101 | 0x35A0B160, 0x2DC02E80, 0xB1403480, 0xB1603000, | |
102 | 0x2EA03640, 0x34002D80, 0x3000B120, 0x36E0B160, | |
103 | 0x2D202EF0, 0xB1203380, 0xB1603000, 0x2F303780, | |
104 | 0x33002CC0, 0x3000B100, 0x3820B160, 0x2C802F50, | |
105 | 0xB10032A0, 0xB1603000, 0x2F9038C0, 0x32202C20, | |
106 | 0x3000B0E0, 0x3980B160, 0x2BC02FC0, 0xB0E031C0, | |
107 | 0xB1603000, 0x2FF03A20, 0x31602B60, 0xB020B0C0, | |
108 | 0x3AE0B160, 0x2B001810, 0xB0C03120, 0xB140B020, | |
109 | 0x18283BA0, 0x30C02A80, 0xB020B0A0, 0x3C60B140, | |
110 | 0x2A201838, 0xB0A03080, 0xB120B020, 0x18383D20, | |
111 | 0x304029C0, 0xB040B080, 0x3DE0B100, 0x29601848, | |
112 | 0xB0803000, 0xB100B040, 0x18483EC0, 0xB0402900, | |
113 | 0xB040B060, 0x3F80B0C0, 0x28801858, 0xB060B080, | |
114 | 0xB0A0B060, 0x18602820, 0xB0A02820, 0x0000B060, | |
115 | 0xB1403000, 0x2E203500, 0x35002E20, 0x3000B140, | |
116 | 0x35A0B160, 0x2DC02E80, 0xB1403480, 0xB1603000, | |
117 | 0x2EA03640, 0x34002D80, 0x3000B120, 0x36E0B160, | |
118 | 0x2D202EF0, 0xB1203380, 0xB1603000, 0x2F303780, | |
119 | 0x33002CC0, 0x3000B100, 0x3820B160, 0x2C802F50, | |
120 | 0xB10032A0, 0xB1603000, 0x2F9038C0, 0x32202C20, | |
121 | 0x3000B0E0, 0x3980B160, 0x2BC02FC0, 0xB0E031C0, | |
122 | 0xB1603000, 0x2FF03A20, 0x31602B60, 0xB020B0C0, | |
123 | 0x3AE0B160, 0x2B001810, 0xB0C03120, 0xB140B020, | |
124 | 0x18283BA0, 0x30C02A80, 0xB020B0A0, 0x3C60B140, | |
125 | 0x2A201838, 0xB0A03080, 0xB120B020, 0x18383D20, | |
126 | 0x304029C0, 0xB040B080, 0x3DE0B100, 0x29601848, | |
127 | 0xB0803000, 0xB100B040, 0x18483EC0, 0xB0402900, | |
128 | 0xB040B060, 0x3F80B0C0, 0x28801858, 0xB060B080, | |
129 | 0xB0A0B060, 0x18602820, 0xB0A02820, 0x0000B060, | |
130 | 0x36403000, 0x2D002CC0, 0x30003640, 0x2D0036C0, | |
131 | 0x35C02CC0, 0x37403000, 0x2C802D40, 0x30003540, | |
132 | 0x2D8037C0, 0x34C02C40, 0x38403000, 0x2BC02E00, | |
133 | 0x30003440, 0x2E2038C0, 0x34002B80, 0x39803000, | |
134 | 0x2B402E40, 0x30003380, 0x2E603A00, 0x33402B00, | |
135 | 0x3A803040, 0x2A802EA0, 0x30403300, 0x2EC03B40, | |
136 | 0x32802A40, 0x3C003040, 0x2A002EC0, 0x30803240, | |
137 | 0x2EC03C80, 0x320029C0, 0x3D403080, 0x29402F00, | |
138 | 0x308031C0, 0x2F203DC0, 0x31802900, 0x3E8030C0, | |
139 | 0x28802F40, 0x30C03140, 0x2F203F40, 0x31402840, | |
140 | 0x28003100, 0x28002F00, 0x00003100, 0x36403000, | |
141 | 0x2D002CC0, 0x30003640, 0x2D0036C0, | |
142 | 0x35C02CC0, 0x37403000, 0x2C802D40, 0x30003540, | |
143 | 0x2D8037C0, 0x34C02C40, 0x38403000, 0x2BC02E00, | |
144 | 0x30003440, 0x2E2038C0, 0x34002B80, 0x39803000, | |
145 | 0x2B402E40, 0x30003380, 0x2E603A00, 0x33402B00, | |
146 | 0x3A803040, 0x2A802EA0, 0x30403300, 0x2EC03B40, | |
147 | 0x32802A40, 0x3C003040, 0x2A002EC0, 0x30803240, | |
148 | 0x2EC03C80, 0x320029C0, 0x3D403080, 0x29402F00, | |
149 | 0x308031C0, 0x2F203DC0, 0x31802900, 0x3E8030C0, | |
150 | 0x28802F40, 0x30C03140, 0x2F203F40, 0x31402840, | |
151 | 0x28003100, 0x28002F00, 0x00003100, | |
152 | }; | |
153 | ||
154 | /* | |
155 | * Color conversion values have 3 separate fixed point formats: | |
156 | * | |
157 | * 10 bit fields (ay, au) | |
158 | * 1.9 fixed point (b.bbbbbbbbb) | |
159 | * 11 bit fields (ry, by, ru, gu, gv) | |
160 | * exp.mantissa (ee.mmmmmmmmm) | |
161 | * ee = 00 = 10^-1 (0.mmmmmmmmm) | |
162 | * ee = 01 = 10^-2 (0.0mmmmmmmmm) | |
163 | * ee = 10 = 10^-3 (0.00mmmmmmmmm) | |
164 | * ee = 11 = 10^-4 (0.000mmmmmmmmm) | |
165 | * 12 bit fields (gy, rv, bu) | |
166 | * exp.mantissa (eee.mmmmmmmmm) | |
167 | * eee = 000 = 10^-1 (0.mmmmmmmmm) | |
168 | * eee = 001 = 10^-2 (0.0mmmmmmmmm) | |
169 | * eee = 010 = 10^-3 (0.00mmmmmmmmm) | |
170 | * eee = 011 = 10^-4 (0.000mmmmmmmmm) | |
171 | * eee = 100 = reserved | |
172 | * eee = 101 = reserved | |
173 | * eee = 110 = reserved | |
174 | * eee = 111 = 10^0 (m.mmmmmmmm) (only usable for 1.0 representation) | |
175 | * | |
176 | * Saturation and contrast are 8 bits, with their own representation: | |
177 | * 8 bit field (saturation, contrast) | |
178 | * exp.mantissa (ee.mmmmmm) | |
179 | * ee = 00 = 10^-1 (0.mmmmmm) | |
180 | * ee = 01 = 10^0 (m.mmmmm) | |
181 | * ee = 10 = 10^1 (mm.mmmm) | |
182 | * ee = 11 = 10^2 (mmm.mmm) | |
183 | * | |
184 | * Simple conversion function: | |
185 | * | |
186 | * static u32 | |
187 | * float_to_csc_11(float f) | |
188 | * { | |
189 | * u32 exp; | |
190 | * u32 mant; | |
191 | * u32 ret; | |
192 | * | |
193 | * if (f < 0) | |
194 | * f = -f; | |
195 | * | |
196 | * if (f >= 1) { | |
197 | * exp = 0x7; | |
0206e353 | 198 | * mant = 1 << 8; |
79e53945 JB |
199 | * } else { |
200 | * for (exp = 0; exp < 3 && f < 0.5; exp++) | |
0206e353 | 201 | * f *= 2.0; |
79e53945 JB |
202 | * mant = (f * (1 << 9) + 0.5); |
203 | * if (mant >= (1 << 9)) | |
204 | * mant = (1 << 9) - 1; | |
205 | * } | |
206 | * ret = (exp << 9) | mant; | |
207 | * return ret; | |
208 | * } | |
209 | */ | |
210 | ||
211 | /* | |
212 | * Behold, magic numbers! If we plant them they might grow a big | |
213 | * s-video cable to the sky... or something. | |
214 | * | |
215 | * Pre-converted to appropriate hex value. | |
216 | */ | |
217 | ||
218 | /* | |
219 | * PAL & NTSC values for composite & s-video connections | |
220 | */ | |
221 | static const struct color_conversion ntsc_m_csc_composite = { | |
222 | .ry = 0x0332, .gy = 0x012d, .by = 0x07d3, .ay = 0x0104, | |
ba01079c ZW |
223 | .ru = 0x0733, .gu = 0x052d, .bu = 0x05c7, .au = 0x0200, |
224 | .rv = 0x0340, .gv = 0x030c, .bv = 0x06d0, .av = 0x0200, | |
79e53945 JB |
225 | }; |
226 | ||
227 | static const struct video_levels ntsc_m_levels_composite = { | |
228 | .blank = 225, .black = 267, .burst = 113, | |
229 | }; | |
230 | ||
231 | static const struct color_conversion ntsc_m_csc_svideo = { | |
ba01079c ZW |
232 | .ry = 0x0332, .gy = 0x012d, .by = 0x07d3, .ay = 0x0133, |
233 | .ru = 0x076a, .gu = 0x0564, .bu = 0x030d, .au = 0x0200, | |
234 | .rv = 0x037a, .gv = 0x033d, .bv = 0x06f6, .av = 0x0200, | |
79e53945 JB |
235 | }; |
236 | ||
237 | static const struct video_levels ntsc_m_levels_svideo = { | |
238 | .blank = 266, .black = 316, .burst = 133, | |
239 | }; | |
240 | ||
241 | static const struct color_conversion ntsc_j_csc_composite = { | |
242 | .ry = 0x0332, .gy = 0x012d, .by = 0x07d3, .ay = 0x0119, | |
ba01079c ZW |
243 | .ru = 0x074c, .gu = 0x0546, .bu = 0x05ec, .au = 0x0200, |
244 | .rv = 0x035a, .gv = 0x0322, .bv = 0x06e1, .av = 0x0200, | |
79e53945 JB |
245 | }; |
246 | ||
247 | static const struct video_levels ntsc_j_levels_composite = { | |
248 | .blank = 225, .black = 225, .burst = 113, | |
249 | }; | |
250 | ||
251 | static const struct color_conversion ntsc_j_csc_svideo = { | |
252 | .ry = 0x0332, .gy = 0x012d, .by = 0x07d3, .ay = 0x014c, | |
ba01079c ZW |
253 | .ru = 0x0788, .gu = 0x0581, .bu = 0x0322, .au = 0x0200, |
254 | .rv = 0x0399, .gv = 0x0356, .bv = 0x070a, .av = 0x0200, | |
79e53945 JB |
255 | }; |
256 | ||
257 | static const struct video_levels ntsc_j_levels_svideo = { | |
258 | .blank = 266, .black = 266, .burst = 133, | |
259 | }; | |
260 | ||
261 | static const struct color_conversion pal_csc_composite = { | |
262 | .ry = 0x0332, .gy = 0x012d, .by = 0x07d3, .ay = 0x0113, | |
ba01079c ZW |
263 | .ru = 0x0745, .gu = 0x053f, .bu = 0x05e1, .au = 0x0200, |
264 | .rv = 0x0353, .gv = 0x031c, .bv = 0x06dc, .av = 0x0200, | |
79e53945 JB |
265 | }; |
266 | ||
267 | static const struct video_levels pal_levels_composite = { | |
268 | .blank = 237, .black = 237, .burst = 118, | |
269 | }; | |
270 | ||
271 | static const struct color_conversion pal_csc_svideo = { | |
272 | .ry = 0x0332, .gy = 0x012d, .by = 0x07d3, .ay = 0x0145, | |
ba01079c ZW |
273 | .ru = 0x0780, .gu = 0x0579, .bu = 0x031c, .au = 0x0200, |
274 | .rv = 0x0390, .gv = 0x034f, .bv = 0x0705, .av = 0x0200, | |
79e53945 JB |
275 | }; |
276 | ||
277 | static const struct video_levels pal_levels_svideo = { | |
278 | .blank = 280, .black = 280, .burst = 139, | |
279 | }; | |
280 | ||
281 | static const struct color_conversion pal_m_csc_composite = { | |
282 | .ry = 0x0332, .gy = 0x012d, .by = 0x07d3, .ay = 0x0104, | |
ba01079c ZW |
283 | .ru = 0x0733, .gu = 0x052d, .bu = 0x05c7, .au = 0x0200, |
284 | .rv = 0x0340, .gv = 0x030c, .bv = 0x06d0, .av = 0x0200, | |
79e53945 JB |
285 | }; |
286 | ||
287 | static const struct video_levels pal_m_levels_composite = { | |
288 | .blank = 225, .black = 267, .burst = 113, | |
289 | }; | |
290 | ||
291 | static const struct color_conversion pal_m_csc_svideo = { | |
ba01079c ZW |
292 | .ry = 0x0332, .gy = 0x012d, .by = 0x07d3, .ay = 0x0133, |
293 | .ru = 0x076a, .gu = 0x0564, .bu = 0x030d, .au = 0x0200, | |
294 | .rv = 0x037a, .gv = 0x033d, .bv = 0x06f6, .av = 0x0200, | |
79e53945 JB |
295 | }; |
296 | ||
297 | static const struct video_levels pal_m_levels_svideo = { | |
298 | .blank = 266, .black = 316, .burst = 133, | |
299 | }; | |
300 | ||
301 | static const struct color_conversion pal_n_csc_composite = { | |
302 | .ry = 0x0332, .gy = 0x012d, .by = 0x07d3, .ay = 0x0104, | |
ba01079c ZW |
303 | .ru = 0x0733, .gu = 0x052d, .bu = 0x05c7, .au = 0x0200, |
304 | .rv = 0x0340, .gv = 0x030c, .bv = 0x06d0, .av = 0x0200, | |
79e53945 JB |
305 | }; |
306 | ||
307 | static const struct video_levels pal_n_levels_composite = { | |
308 | .blank = 225, .black = 267, .burst = 118, | |
309 | }; | |
310 | ||
311 | static const struct color_conversion pal_n_csc_svideo = { | |
ba01079c ZW |
312 | .ry = 0x0332, .gy = 0x012d, .by = 0x07d3, .ay = 0x0133, |
313 | .ru = 0x076a, .gu = 0x0564, .bu = 0x030d, .au = 0x0200, | |
314 | .rv = 0x037a, .gv = 0x033d, .bv = 0x06f6, .av = 0x0200, | |
79e53945 JB |
315 | }; |
316 | ||
317 | static const struct video_levels pal_n_levels_svideo = { | |
318 | .blank = 266, .black = 316, .burst = 139, | |
319 | }; | |
320 | ||
321 | /* | |
322 | * Component connections | |
323 | */ | |
324 | static const struct color_conversion sdtv_csc_yprpb = { | |
ba01079c ZW |
325 | .ry = 0x0332, .gy = 0x012d, .by = 0x07d3, .ay = 0x0145, |
326 | .ru = 0x0559, .gu = 0x0353, .bu = 0x0100, .au = 0x0200, | |
327 | .rv = 0x0100, .gv = 0x03ad, .bv = 0x074d, .av = 0x0200, | |
79e53945 JB |
328 | }; |
329 | ||
79e53945 | 330 | static const struct color_conversion hdtv_csc_yprpb = { |
ba01079c ZW |
331 | .ry = 0x05b3, .gy = 0x016e, .by = 0x0728, .ay = 0x0145, |
332 | .ru = 0x07d5, .gu = 0x038b, .bu = 0x0100, .au = 0x0200, | |
333 | .rv = 0x0100, .gv = 0x03d1, .bv = 0x06bc, .av = 0x0200, | |
79e53945 JB |
334 | }; |
335 | ||
79e53945 JB |
336 | static const struct video_levels component_levels = { |
337 | .blank = 279, .black = 279, .burst = 0, | |
338 | }; | |
339 | ||
340 | ||
341 | struct tv_mode { | |
763a4a01 | 342 | const char *name; |
db49296b TU |
343 | |
344 | u32 clock; | |
345 | u16 refresh; /* in millihertz (for precision) */ | |
79e53945 | 346 | u32 oversample; |
db49296b TU |
347 | u8 hsync_end; |
348 | u16 hblank_start, hblank_end, htotal; | |
349 | bool progressive : 1, trilevel_sync : 1, component_only : 1; | |
350 | u8 vsync_start_f1, vsync_start_f2, vsync_len; | |
351 | bool veq_ena : 1; | |
352 | u8 veq_start_f1, veq_start_f2, veq_len; | |
353 | u8 vi_end_f1, vi_end_f2; | |
354 | u16 nbr_end; | |
355 | bool burst_ena : 1; | |
356 | u8 hburst_start, hburst_len; | |
357 | u8 vburst_start_f1; | |
358 | u16 vburst_end_f1; | |
359 | u8 vburst_start_f2; | |
360 | u16 vburst_end_f2; | |
361 | u8 vburst_start_f3; | |
362 | u16 vburst_end_f3; | |
363 | u8 vburst_start_f4; | |
364 | u16 vburst_end_f4; | |
79e53945 JB |
365 | /* |
366 | * subcarrier programming | |
367 | */ | |
db49296b TU |
368 | u16 dda2_size, dda3_size; |
369 | u8 dda1_inc; | |
370 | u16 dda2_inc, dda3_inc; | |
79e53945 | 371 | u32 sc_reset; |
db49296b | 372 | bool pal_burst : 1; |
79e53945 JB |
373 | /* |
374 | * blank/black levels | |
375 | */ | |
376 | const struct video_levels *composite_levels, *svideo_levels; | |
377 | const struct color_conversion *composite_color, *svideo_color; | |
378 | const u32 *filter_table; | |
db49296b | 379 | u16 max_srcw; |
79e53945 JB |
380 | }; |
381 | ||
382 | ||
383 | /* | |
384 | * Sub carrier DDA | |
385 | * | |
386 | * I think this works as follows: | |
387 | * | |
388 | * subcarrier freq = pixel_clock * (dda1_inc + dda2_inc / dda2_size) / 4096 | |
389 | * | |
390 | * Presumably, when dda3 is added in, it gets to adjust the dda2_inc value | |
391 | * | |
392 | * So, | |
393 | * dda1_ideal = subcarrier/pixel * 4096 | |
394 | * dda1_inc = floor (dda1_ideal) | |
395 | * dda2 = dda1_ideal - dda1_inc | |
396 | * | |
397 | * then pick a ratio for dda2 that gives the closest approximation. If | |
398 | * you can't get close enough, you can play with dda3 as well. This | |
399 | * seems likely to happen when dda2 is small as the jumps would be larger | |
400 | * | |
401 | * To invert this, | |
402 | * | |
403 | * pixel_clock = subcarrier * 4096 / (dda1_inc + dda2_inc / dda2_size) | |
404 | * | |
405 | * The constants below were all computed using a 107.520MHz clock | |
406 | */ | |
407 | ||
408 | /** | |
409 | * Register programming values for TV modes. | |
410 | * | |
411 | * These values account for -1s required. | |
412 | */ | |
413 | ||
005568be | 414 | static const struct tv_mode tv_modes[] = { |
79e53945 JB |
415 | { |
416 | .name = "NTSC-M", | |
ba01079c | 417 | .clock = 108000, |
23bd15ec | 418 | .refresh = 59940, |
79e53945 JB |
419 | .oversample = TV_OVERSAMPLE_8X, |
420 | .component_only = 0, | |
421 | /* 525 Lines, 60 Fields, 15.734KHz line, Sub-Carrier 3.580MHz */ | |
422 | ||
423 | .hsync_end = 64, .hblank_end = 124, | |
424 | .hblank_start = 836, .htotal = 857, | |
425 | ||
426 | .progressive = false, .trilevel_sync = false, | |
427 | ||
428 | .vsync_start_f1 = 6, .vsync_start_f2 = 7, | |
429 | .vsync_len = 6, | |
430 | ||
0206e353 | 431 | .veq_ena = true, .veq_start_f1 = 0, |
79e53945 JB |
432 | .veq_start_f2 = 1, .veq_len = 18, |
433 | ||
434 | .vi_end_f1 = 20, .vi_end_f2 = 21, | |
435 | .nbr_end = 240, | |
436 | ||
437 | .burst_ena = true, | |
438 | .hburst_start = 72, .hburst_len = 34, | |
439 | .vburst_start_f1 = 9, .vburst_end_f1 = 240, | |
440 | .vburst_start_f2 = 10, .vburst_end_f2 = 240, | |
441 | .vburst_start_f3 = 9, .vburst_end_f3 = 240, | |
442 | .vburst_start_f4 = 10, .vburst_end_f4 = 240, | |
443 | ||
444 | /* desired 3.5800000 actual 3.5800000 clock 107.52 */ | |
ba01079c ZW |
445 | .dda1_inc = 135, |
446 | .dda2_inc = 20800, .dda2_size = 27456, | |
79e53945 JB |
447 | .dda3_inc = 0, .dda3_size = 0, |
448 | .sc_reset = TV_SC_RESET_EVERY_4, | |
449 | .pal_burst = false, | |
450 | ||
451 | .composite_levels = &ntsc_m_levels_composite, | |
452 | .composite_color = &ntsc_m_csc_composite, | |
453 | .svideo_levels = &ntsc_m_levels_svideo, | |
454 | .svideo_color = &ntsc_m_csc_svideo, | |
455 | ||
456 | .filter_table = filter_table, | |
457 | }, | |
458 | { | |
459 | .name = "NTSC-443", | |
ba01079c | 460 | .clock = 108000, |
23bd15ec | 461 | .refresh = 59940, |
79e53945 JB |
462 | .oversample = TV_OVERSAMPLE_8X, |
463 | .component_only = 0, | |
464 | /* 525 Lines, 60 Fields, 15.734KHz line, Sub-Carrier 4.43MHz */ | |
465 | .hsync_end = 64, .hblank_end = 124, | |
466 | .hblank_start = 836, .htotal = 857, | |
467 | ||
468 | .progressive = false, .trilevel_sync = false, | |
469 | ||
470 | .vsync_start_f1 = 6, .vsync_start_f2 = 7, | |
471 | .vsync_len = 6, | |
472 | ||
0206e353 | 473 | .veq_ena = true, .veq_start_f1 = 0, |
79e53945 JB |
474 | .veq_start_f2 = 1, .veq_len = 18, |
475 | ||
476 | .vi_end_f1 = 20, .vi_end_f2 = 21, | |
477 | .nbr_end = 240, | |
478 | ||
3ca87e82 | 479 | .burst_ena = true, |
79e53945 JB |
480 | .hburst_start = 72, .hburst_len = 34, |
481 | .vburst_start_f1 = 9, .vburst_end_f1 = 240, | |
482 | .vburst_start_f2 = 10, .vburst_end_f2 = 240, | |
483 | .vburst_start_f3 = 9, .vburst_end_f3 = 240, | |
484 | .vburst_start_f4 = 10, .vburst_end_f4 = 240, | |
485 | ||
486 | /* desired 4.4336180 actual 4.4336180 clock 107.52 */ | |
487 | .dda1_inc = 168, | |
ba01079c ZW |
488 | .dda2_inc = 4093, .dda2_size = 27456, |
489 | .dda3_inc = 310, .dda3_size = 525, | |
490 | .sc_reset = TV_SC_RESET_NEVER, | |
491 | .pal_burst = false, | |
79e53945 JB |
492 | |
493 | .composite_levels = &ntsc_m_levels_composite, | |
494 | .composite_color = &ntsc_m_csc_composite, | |
495 | .svideo_levels = &ntsc_m_levels_svideo, | |
496 | .svideo_color = &ntsc_m_csc_svideo, | |
497 | ||
498 | .filter_table = filter_table, | |
499 | }, | |
500 | { | |
501 | .name = "NTSC-J", | |
ba01079c | 502 | .clock = 108000, |
23bd15ec | 503 | .refresh = 59940, |
79e53945 JB |
504 | .oversample = TV_OVERSAMPLE_8X, |
505 | .component_only = 0, | |
506 | ||
507 | /* 525 Lines, 60 Fields, 15.734KHz line, Sub-Carrier 3.580MHz */ | |
508 | .hsync_end = 64, .hblank_end = 124, | |
509 | .hblank_start = 836, .htotal = 857, | |
510 | ||
511 | .progressive = false, .trilevel_sync = false, | |
512 | ||
513 | .vsync_start_f1 = 6, .vsync_start_f2 = 7, | |
514 | .vsync_len = 6, | |
515 | ||
0206e353 | 516 | .veq_ena = true, .veq_start_f1 = 0, |
79e53945 JB |
517 | .veq_start_f2 = 1, .veq_len = 18, |
518 | ||
519 | .vi_end_f1 = 20, .vi_end_f2 = 21, | |
520 | .nbr_end = 240, | |
521 | ||
522 | .burst_ena = true, | |
523 | .hburst_start = 72, .hburst_len = 34, | |
524 | .vburst_start_f1 = 9, .vburst_end_f1 = 240, | |
525 | .vburst_start_f2 = 10, .vburst_end_f2 = 240, | |
526 | .vburst_start_f3 = 9, .vburst_end_f3 = 240, | |
527 | .vburst_start_f4 = 10, .vburst_end_f4 = 240, | |
528 | ||
529 | /* desired 3.5800000 actual 3.5800000 clock 107.52 */ | |
ba01079c ZW |
530 | .dda1_inc = 135, |
531 | .dda2_inc = 20800, .dda2_size = 27456, | |
79e53945 JB |
532 | .dda3_inc = 0, .dda3_size = 0, |
533 | .sc_reset = TV_SC_RESET_EVERY_4, | |
534 | .pal_burst = false, | |
535 | ||
536 | .composite_levels = &ntsc_j_levels_composite, | |
537 | .composite_color = &ntsc_j_csc_composite, | |
538 | .svideo_levels = &ntsc_j_levels_svideo, | |
539 | .svideo_color = &ntsc_j_csc_svideo, | |
540 | ||
541 | .filter_table = filter_table, | |
542 | }, | |
543 | { | |
544 | .name = "PAL-M", | |
ba01079c | 545 | .clock = 108000, |
23bd15ec | 546 | .refresh = 59940, |
79e53945 JB |
547 | .oversample = TV_OVERSAMPLE_8X, |
548 | .component_only = 0, | |
549 | ||
550 | /* 525 Lines, 60 Fields, 15.734KHz line, Sub-Carrier 3.580MHz */ | |
551 | .hsync_end = 64, .hblank_end = 124, | |
552 | .hblank_start = 836, .htotal = 857, | |
553 | ||
554 | .progressive = false, .trilevel_sync = false, | |
555 | ||
556 | .vsync_start_f1 = 6, .vsync_start_f2 = 7, | |
557 | .vsync_len = 6, | |
558 | ||
0206e353 | 559 | .veq_ena = true, .veq_start_f1 = 0, |
79e53945 JB |
560 | .veq_start_f2 = 1, .veq_len = 18, |
561 | ||
562 | .vi_end_f1 = 20, .vi_end_f2 = 21, | |
563 | .nbr_end = 240, | |
564 | ||
565 | .burst_ena = true, | |
566 | .hburst_start = 72, .hburst_len = 34, | |
567 | .vburst_start_f1 = 9, .vburst_end_f1 = 240, | |
568 | .vburst_start_f2 = 10, .vburst_end_f2 = 240, | |
569 | .vburst_start_f3 = 9, .vburst_end_f3 = 240, | |
570 | .vburst_start_f4 = 10, .vburst_end_f4 = 240, | |
571 | ||
572 | /* desired 3.5800000 actual 3.5800000 clock 107.52 */ | |
ba01079c ZW |
573 | .dda1_inc = 135, |
574 | .dda2_inc = 16704, .dda2_size = 27456, | |
79e53945 | 575 | .dda3_inc = 0, .dda3_size = 0, |
ba01079c ZW |
576 | .sc_reset = TV_SC_RESET_EVERY_8, |
577 | .pal_burst = true, | |
79e53945 JB |
578 | |
579 | .composite_levels = &pal_m_levels_composite, | |
580 | .composite_color = &pal_m_csc_composite, | |
581 | .svideo_levels = &pal_m_levels_svideo, | |
582 | .svideo_color = &pal_m_csc_svideo, | |
583 | ||
584 | .filter_table = filter_table, | |
585 | }, | |
586 | { | |
587 | /* 625 Lines, 50 Fields, 15.625KHz line, Sub-Carrier 4.434MHz */ | |
588 | .name = "PAL-N", | |
ba01079c | 589 | .clock = 108000, |
23bd15ec | 590 | .refresh = 50000, |
79e53945 JB |
591 | .oversample = TV_OVERSAMPLE_8X, |
592 | .component_only = 0, | |
593 | ||
594 | .hsync_end = 64, .hblank_end = 128, | |
595 | .hblank_start = 844, .htotal = 863, | |
596 | ||
597 | .progressive = false, .trilevel_sync = false, | |
598 | ||
599 | ||
600 | .vsync_start_f1 = 6, .vsync_start_f2 = 7, | |
601 | .vsync_len = 6, | |
602 | ||
0206e353 | 603 | .veq_ena = true, .veq_start_f1 = 0, |
79e53945 JB |
604 | .veq_start_f2 = 1, .veq_len = 18, |
605 | ||
606 | .vi_end_f1 = 24, .vi_end_f2 = 25, | |
607 | .nbr_end = 286, | |
608 | ||
609 | .burst_ena = true, | |
0206e353 | 610 | .hburst_start = 73, .hburst_len = 34, |
79e53945 JB |
611 | .vburst_start_f1 = 8, .vburst_end_f1 = 285, |
612 | .vburst_start_f2 = 8, .vburst_end_f2 = 286, | |
613 | .vburst_start_f3 = 9, .vburst_end_f3 = 286, | |
614 | .vburst_start_f4 = 9, .vburst_end_f4 = 285, | |
615 | ||
616 | ||
617 | /* desired 4.4336180 actual 4.4336180 clock 107.52 */ | |
ba01079c ZW |
618 | .dda1_inc = 135, |
619 | .dda2_inc = 23578, .dda2_size = 27648, | |
620 | .dda3_inc = 134, .dda3_size = 625, | |
79e53945 JB |
621 | .sc_reset = TV_SC_RESET_EVERY_8, |
622 | .pal_burst = true, | |
623 | ||
624 | .composite_levels = &pal_n_levels_composite, | |
625 | .composite_color = &pal_n_csc_composite, | |
626 | .svideo_levels = &pal_n_levels_svideo, | |
627 | .svideo_color = &pal_n_csc_svideo, | |
628 | ||
629 | .filter_table = filter_table, | |
630 | }, | |
631 | { | |
632 | /* 625 Lines, 50 Fields, 15.625KHz line, Sub-Carrier 4.434MHz */ | |
633 | .name = "PAL", | |
ba01079c | 634 | .clock = 108000, |
23bd15ec | 635 | .refresh = 50000, |
79e53945 JB |
636 | .oversample = TV_OVERSAMPLE_8X, |
637 | .component_only = 0, | |
638 | ||
ba01079c | 639 | .hsync_end = 64, .hblank_end = 142, |
79e53945 JB |
640 | .hblank_start = 844, .htotal = 863, |
641 | ||
642 | .progressive = false, .trilevel_sync = false, | |
643 | ||
644 | .vsync_start_f1 = 5, .vsync_start_f2 = 6, | |
645 | .vsync_len = 5, | |
646 | ||
0206e353 | 647 | .veq_ena = true, .veq_start_f1 = 0, |
79e53945 JB |
648 | .veq_start_f2 = 1, .veq_len = 15, |
649 | ||
650 | .vi_end_f1 = 24, .vi_end_f2 = 25, | |
651 | .nbr_end = 286, | |
652 | ||
653 | .burst_ena = true, | |
654 | .hburst_start = 73, .hburst_len = 32, | |
655 | .vburst_start_f1 = 8, .vburst_end_f1 = 285, | |
656 | .vburst_start_f2 = 8, .vburst_end_f2 = 286, | |
657 | .vburst_start_f3 = 9, .vburst_end_f3 = 286, | |
658 | .vburst_start_f4 = 9, .vburst_end_f4 = 285, | |
659 | ||
660 | /* desired 4.4336180 actual 4.4336180 clock 107.52 */ | |
661 | .dda1_inc = 168, | |
ba01079c ZW |
662 | .dda2_inc = 4122, .dda2_size = 27648, |
663 | .dda3_inc = 67, .dda3_size = 625, | |
79e53945 JB |
664 | .sc_reset = TV_SC_RESET_EVERY_8, |
665 | .pal_burst = true, | |
666 | ||
667 | .composite_levels = &pal_levels_composite, | |
668 | .composite_color = &pal_csc_composite, | |
669 | .svideo_levels = &pal_levels_svideo, | |
670 | .svideo_color = &pal_csc_svideo, | |
671 | ||
672 | .filter_table = filter_table, | |
673 | }, | |
9589919f RV |
674 | { |
675 | .name = "480p", | |
676 | .clock = 107520, | |
677 | .refresh = 59940, | |
678 | .oversample = TV_OVERSAMPLE_4X, | |
679 | .component_only = 1, | |
680 | ||
681 | .hsync_end = 64, .hblank_end = 122, | |
682 | .hblank_start = 842, .htotal = 857, | |
683 | ||
684 | .progressive = true, .trilevel_sync = false, | |
685 | ||
686 | .vsync_start_f1 = 12, .vsync_start_f2 = 12, | |
687 | .vsync_len = 12, | |
688 | ||
689 | .veq_ena = false, | |
690 | ||
691 | .vi_end_f1 = 44, .vi_end_f2 = 44, | |
692 | .nbr_end = 479, | |
693 | ||
694 | .burst_ena = false, | |
695 | ||
696 | .filter_table = filter_table, | |
697 | }, | |
698 | { | |
699 | .name = "576p", | |
700 | .clock = 107520, | |
701 | .refresh = 50000, | |
702 | .oversample = TV_OVERSAMPLE_4X, | |
703 | .component_only = 1, | |
704 | ||
705 | .hsync_end = 64, .hblank_end = 139, | |
706 | .hblank_start = 859, .htotal = 863, | |
707 | ||
708 | .progressive = true, .trilevel_sync = false, | |
709 | ||
710 | .vsync_start_f1 = 10, .vsync_start_f2 = 10, | |
711 | .vsync_len = 10, | |
712 | ||
713 | .veq_ena = false, | |
714 | ||
715 | .vi_end_f1 = 48, .vi_end_f2 = 48, | |
716 | .nbr_end = 575, | |
717 | ||
718 | .burst_ena = false, | |
719 | ||
720 | .filter_table = filter_table, | |
721 | }, | |
79e53945 JB |
722 | { |
723 | .name = "720p@60Hz", | |
724 | .clock = 148800, | |
725 | .refresh = 60000, | |
726 | .oversample = TV_OVERSAMPLE_2X, | |
727 | .component_only = 1, | |
728 | ||
729 | .hsync_end = 80, .hblank_end = 300, | |
730 | .hblank_start = 1580, .htotal = 1649, | |
731 | ||
0206e353 | 732 | .progressive = true, .trilevel_sync = true, |
79e53945 JB |
733 | |
734 | .vsync_start_f1 = 10, .vsync_start_f2 = 10, | |
735 | .vsync_len = 10, | |
736 | ||
737 | .veq_ena = false, | |
738 | ||
739 | .vi_end_f1 = 29, .vi_end_f2 = 29, | |
740 | .nbr_end = 719, | |
741 | ||
742 | .burst_ena = false, | |
743 | ||
744 | .filter_table = filter_table, | |
745 | }, | |
79e53945 JB |
746 | { |
747 | .name = "720p@50Hz", | |
748 | .clock = 148800, | |
749 | .refresh = 50000, | |
750 | .oversample = TV_OVERSAMPLE_2X, | |
751 | .component_only = 1, | |
752 | ||
753 | .hsync_end = 80, .hblank_end = 300, | |
754 | .hblank_start = 1580, .htotal = 1979, | |
755 | ||
0206e353 | 756 | .progressive = true, .trilevel_sync = true, |
79e53945 JB |
757 | |
758 | .vsync_start_f1 = 10, .vsync_start_f2 = 10, | |
759 | .vsync_len = 10, | |
760 | ||
761 | .veq_ena = false, | |
762 | ||
763 | .vi_end_f1 = 29, .vi_end_f2 = 29, | |
764 | .nbr_end = 719, | |
765 | ||
766 | .burst_ena = false, | |
767 | ||
768 | .filter_table = filter_table, | |
769 | .max_srcw = 800 | |
770 | }, | |
771 | { | |
772 | .name = "1080i@50Hz", | |
773 | .clock = 148800, | |
23bd15ec | 774 | .refresh = 50000, |
79e53945 JB |
775 | .oversample = TV_OVERSAMPLE_2X, |
776 | .component_only = 1, | |
777 | ||
778 | .hsync_end = 88, .hblank_end = 235, | |
779 | .hblank_start = 2155, .htotal = 2639, | |
780 | ||
0206e353 | 781 | .progressive = false, .trilevel_sync = true, |
79e53945 JB |
782 | |
783 | .vsync_start_f1 = 4, .vsync_start_f2 = 5, | |
784 | .vsync_len = 10, | |
785 | ||
0206e353 | 786 | .veq_ena = true, .veq_start_f1 = 4, |
79e53945 JB |
787 | .veq_start_f2 = 4, .veq_len = 10, |
788 | ||
789 | ||
790 | .vi_end_f1 = 21, .vi_end_f2 = 22, | |
791 | .nbr_end = 539, | |
792 | ||
793 | .burst_ena = false, | |
794 | ||
795 | .filter_table = filter_table, | |
796 | }, | |
797 | { | |
798 | .name = "1080i@60Hz", | |
799 | .clock = 148800, | |
23bd15ec | 800 | .refresh = 60000, |
79e53945 JB |
801 | .oversample = TV_OVERSAMPLE_2X, |
802 | .component_only = 1, | |
803 | ||
804 | .hsync_end = 88, .hblank_end = 235, | |
805 | .hblank_start = 2155, .htotal = 2199, | |
806 | ||
0206e353 | 807 | .progressive = false, .trilevel_sync = true, |
79e53945 JB |
808 | |
809 | .vsync_start_f1 = 4, .vsync_start_f2 = 5, | |
810 | .vsync_len = 10, | |
811 | ||
0206e353 | 812 | .veq_ena = true, .veq_start_f1 = 4, |
79e53945 JB |
813 | .veq_start_f2 = 4, .veq_len = 10, |
814 | ||
815 | ||
816 | .vi_end_f1 = 21, .vi_end_f2 = 22, | |
817 | .nbr_end = 539, | |
818 | ||
819 | .burst_ena = false, | |
820 | ||
79e53945 JB |
821 | .filter_table = filter_table, |
822 | }, | |
823 | }; | |
824 | ||
cd91ef23 | 825 | static struct intel_tv *enc_to_tv(struct intel_encoder *encoder) |
ea5b213a | 826 | { |
cd91ef23 | 827 | return container_of(encoder, struct intel_tv, base); |
ea5b213a CW |
828 | } |
829 | ||
df0e9248 CW |
830 | static struct intel_tv *intel_attached_tv(struct drm_connector *connector) |
831 | { | |
cd91ef23 | 832 | return enc_to_tv(intel_attached_encoder(connector)); |
df0e9248 CW |
833 | } |
834 | ||
9a8ee983 DV |
835 | static bool |
836 | intel_tv_get_hw_state(struct intel_encoder *encoder, enum pipe *pipe) | |
837 | { | |
838 | struct drm_device *dev = encoder->base.dev; | |
fac5e23e | 839 | struct drm_i915_private *dev_priv = to_i915(dev); |
9a8ee983 DV |
840 | u32 tmp = I915_READ(TV_CTL); |
841 | ||
842 | if (!(tmp & TV_ENC_ENABLE)) | |
843 | return false; | |
844 | ||
845 | *pipe = PORT_TO_PIPE(tmp); | |
846 | ||
847 | return true; | |
848 | } | |
849 | ||
79e53945 | 850 | static void |
fd6bbda9 ML |
851 | intel_enable_tv(struct intel_encoder *encoder, |
852 | struct intel_crtc_state *pipe_config, | |
853 | struct drm_connector_state *conn_state) | |
79e53945 | 854 | { |
6b5756a0 | 855 | struct drm_device *dev = encoder->base.dev; |
fac5e23e | 856 | struct drm_i915_private *dev_priv = to_i915(dev); |
79e53945 | 857 | |
7a98948f VS |
858 | /* Prevents vblank waits from timing out in intel_tv_detect_type() */ |
859 | intel_wait_for_vblank(encoder->base.dev, | |
860 | to_intel_crtc(encoder->base.crtc)->pipe); | |
861 | ||
6b5756a0 DV |
862 | I915_WRITE(TV_CTL, I915_READ(TV_CTL) | TV_ENC_ENABLE); |
863 | } | |
864 | ||
865 | static void | |
fd6bbda9 ML |
866 | intel_disable_tv(struct intel_encoder *encoder, |
867 | struct intel_crtc_state *old_crtc_state, | |
868 | struct drm_connector_state *old_conn_state) | |
6b5756a0 DV |
869 | { |
870 | struct drm_device *dev = encoder->base.dev; | |
fac5e23e | 871 | struct drm_i915_private *dev_priv = to_i915(dev); |
6b5756a0 DV |
872 | |
873 | I915_WRITE(TV_CTL, I915_READ(TV_CTL) & ~TV_ENC_ENABLE); | |
79e53945 JB |
874 | } |
875 | ||
79e53945 | 876 | static const struct tv_mode * |
763a4a01 | 877 | intel_tv_mode_lookup(const char *tv_format) |
79e53945 JB |
878 | { |
879 | int i; | |
880 | ||
3801a7fd | 881 | for (i = 0; i < ARRAY_SIZE(tv_modes); i++) { |
79e53945 JB |
882 | const struct tv_mode *tv_mode = &tv_modes[i]; |
883 | ||
884 | if (!strcmp(tv_format, tv_mode->name)) | |
885 | return tv_mode; | |
886 | } | |
887 | return NULL; | |
888 | } | |
889 | ||
890 | static const struct tv_mode * | |
763a4a01 | 891 | intel_tv_mode_find(struct intel_tv *intel_tv) |
79e53945 | 892 | { |
ea5b213a | 893 | return intel_tv_mode_lookup(intel_tv->tv_format); |
79e53945 JB |
894 | } |
895 | ||
896 | static enum drm_mode_status | |
763a4a01 CW |
897 | intel_tv_mode_valid(struct drm_connector *connector, |
898 | struct drm_display_mode *mode) | |
79e53945 | 899 | { |
df0e9248 | 900 | struct intel_tv *intel_tv = intel_attached_tv(connector); |
ea5b213a | 901 | const struct tv_mode *tv_mode = intel_tv_mode_find(intel_tv); |
54c032b3 MK |
902 | int max_dotclk = to_i915(connector->dev)->max_dotclk_freq; |
903 | ||
904 | if (mode->clock > max_dotclk) | |
905 | return MODE_CLOCK_HIGH; | |
79e53945 JB |
906 | |
907 | /* Ensure TV refresh is close to desired refresh */ | |
0d0884ce ZY |
908 | if (tv_mode && abs(tv_mode->refresh - drm_mode_vrefresh(mode) * 1000) |
909 | < 1000) | |
79e53945 | 910 | return MODE_OK; |
763a4a01 | 911 | |
79e53945 JB |
912 | return MODE_CLOCK_RANGE; |
913 | } | |
914 | ||
915 | ||
7a495cfd DV |
916 | static void |
917 | intel_tv_get_config(struct intel_encoder *encoder, | |
5cec258b | 918 | struct intel_crtc_state *pipe_config) |
7a495cfd | 919 | { |
2d112de7 | 920 | pipe_config->base.adjusted_mode.crtc_clock = pipe_config->port_clock; |
7a495cfd DV |
921 | } |
922 | ||
79e53945 | 923 | static bool |
5d2d38dd | 924 | intel_tv_compute_config(struct intel_encoder *encoder, |
0a478c27 ML |
925 | struct intel_crtc_state *pipe_config, |
926 | struct drm_connector_state *conn_state) | |
79e53945 | 927 | { |
cd91ef23 | 928 | struct intel_tv *intel_tv = enc_to_tv(encoder); |
ea5b213a | 929 | const struct tv_mode *tv_mode = intel_tv_mode_find(intel_tv); |
79e53945 JB |
930 | |
931 | if (!tv_mode) | |
932 | return false; | |
933 | ||
2d112de7 | 934 | pipe_config->base.adjusted_mode.crtc_clock = tv_mode->clock; |
5d2d38dd DV |
935 | DRM_DEBUG_KMS("forcing bpc to 8 for TV\n"); |
936 | pipe_config->pipe_bpp = 8*3; | |
937 | ||
1062b815 | 938 | /* TV has it's own notion of sync and other mode flags, so clear them. */ |
2d112de7 | 939 | pipe_config->base.adjusted_mode.flags = 0; |
1062b815 DV |
940 | |
941 | /* | |
942 | * FIXME: We don't check whether the input mode is actually what we want | |
943 | * or whether userspace is doing something stupid. | |
944 | */ | |
945 | ||
79e53945 JB |
946 | return true; |
947 | } | |
948 | ||
8cb92203 DV |
949 | static void |
950 | set_tv_mode_timings(struct drm_i915_private *dev_priv, | |
951 | const struct tv_mode *tv_mode, | |
952 | bool burst_ena) | |
953 | { | |
954 | u32 hctl1, hctl2, hctl3; | |
955 | u32 vctl1, vctl2, vctl3, vctl4, vctl5, vctl6, vctl7; | |
956 | ||
957 | hctl1 = (tv_mode->hsync_end << TV_HSYNC_END_SHIFT) | | |
958 | (tv_mode->htotal << TV_HTOTAL_SHIFT); | |
959 | ||
960 | hctl2 = (tv_mode->hburst_start << 16) | | |
961 | (tv_mode->hburst_len << TV_HBURST_LEN_SHIFT); | |
962 | ||
963 | if (burst_ena) | |
964 | hctl2 |= TV_BURST_ENA; | |
965 | ||
966 | hctl3 = (tv_mode->hblank_start << TV_HBLANK_START_SHIFT) | | |
967 | (tv_mode->hblank_end << TV_HBLANK_END_SHIFT); | |
968 | ||
969 | vctl1 = (tv_mode->nbr_end << TV_NBR_END_SHIFT) | | |
970 | (tv_mode->vi_end_f1 << TV_VI_END_F1_SHIFT) | | |
971 | (tv_mode->vi_end_f2 << TV_VI_END_F2_SHIFT); | |
972 | ||
973 | vctl2 = (tv_mode->vsync_len << TV_VSYNC_LEN_SHIFT) | | |
974 | (tv_mode->vsync_start_f1 << TV_VSYNC_START_F1_SHIFT) | | |
975 | (tv_mode->vsync_start_f2 << TV_VSYNC_START_F2_SHIFT); | |
976 | ||
977 | vctl3 = (tv_mode->veq_len << TV_VEQ_LEN_SHIFT) | | |
978 | (tv_mode->veq_start_f1 << TV_VEQ_START_F1_SHIFT) | | |
979 | (tv_mode->veq_start_f2 << TV_VEQ_START_F2_SHIFT); | |
980 | ||
981 | if (tv_mode->veq_ena) | |
982 | vctl3 |= TV_EQUAL_ENA; | |
983 | ||
984 | vctl4 = (tv_mode->vburst_start_f1 << TV_VBURST_START_F1_SHIFT) | | |
985 | (tv_mode->vburst_end_f1 << TV_VBURST_END_F1_SHIFT); | |
986 | ||
987 | vctl5 = (tv_mode->vburst_start_f2 << TV_VBURST_START_F2_SHIFT) | | |
988 | (tv_mode->vburst_end_f2 << TV_VBURST_END_F2_SHIFT); | |
989 | ||
990 | vctl6 = (tv_mode->vburst_start_f3 << TV_VBURST_START_F3_SHIFT) | | |
991 | (tv_mode->vburst_end_f3 << TV_VBURST_END_F3_SHIFT); | |
992 | ||
993 | vctl7 = (tv_mode->vburst_start_f4 << TV_VBURST_START_F4_SHIFT) | | |
994 | (tv_mode->vburst_end_f4 << TV_VBURST_END_F4_SHIFT); | |
995 | ||
996 | I915_WRITE(TV_H_CTL_1, hctl1); | |
997 | I915_WRITE(TV_H_CTL_2, hctl2); | |
998 | I915_WRITE(TV_H_CTL_3, hctl3); | |
999 | I915_WRITE(TV_V_CTL_1, vctl1); | |
1000 | I915_WRITE(TV_V_CTL_2, vctl2); | |
1001 | I915_WRITE(TV_V_CTL_3, vctl3); | |
1002 | I915_WRITE(TV_V_CTL_4, vctl4); | |
1003 | I915_WRITE(TV_V_CTL_5, vctl5); | |
1004 | I915_WRITE(TV_V_CTL_6, vctl6); | |
1005 | I915_WRITE(TV_V_CTL_7, vctl7); | |
1006 | } | |
1007 | ||
b8866ef8 DV |
1008 | static void set_color_conversion(struct drm_i915_private *dev_priv, |
1009 | const struct color_conversion *color_conversion) | |
1010 | { | |
1011 | if (!color_conversion) | |
1012 | return; | |
1013 | ||
1014 | I915_WRITE(TV_CSC_Y, (color_conversion->ry << 16) | | |
1015 | color_conversion->gy); | |
1016 | I915_WRITE(TV_CSC_Y2, (color_conversion->by << 16) | | |
1017 | color_conversion->ay); | |
1018 | I915_WRITE(TV_CSC_U, (color_conversion->ru << 16) | | |
1019 | color_conversion->gu); | |
1020 | I915_WRITE(TV_CSC_U2, (color_conversion->bu << 16) | | |
1021 | color_conversion->au); | |
1022 | I915_WRITE(TV_CSC_V, (color_conversion->rv << 16) | | |
1023 | color_conversion->gv); | |
1024 | I915_WRITE(TV_CSC_V2, (color_conversion->bv << 16) | | |
1025 | color_conversion->av); | |
1026 | } | |
1027 | ||
fd6bbda9 ML |
1028 | static void intel_tv_pre_enable(struct intel_encoder *encoder, |
1029 | struct intel_crtc_state *pipe_config, | |
1030 | struct drm_connector_state *conn_state) | |
79e53945 | 1031 | { |
cd91ef23 | 1032 | struct drm_device *dev = encoder->base.dev; |
fac5e23e | 1033 | struct drm_i915_private *dev_priv = to_i915(dev); |
cd91ef23 DV |
1034 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc); |
1035 | struct intel_tv *intel_tv = enc_to_tv(encoder); | |
ea5b213a | 1036 | const struct tv_mode *tv_mode = intel_tv_mode_find(intel_tv); |
79e53945 | 1037 | u32 tv_ctl; |
79e53945 JB |
1038 | u32 scctl1, scctl2, scctl3; |
1039 | int i, j; | |
1040 | const struct video_levels *video_levels; | |
1041 | const struct color_conversion *color_conversion; | |
1042 | bool burst_ena; | |
3fa2dd14 DV |
1043 | int xpos = 0x0, ypos = 0x0; |
1044 | unsigned int xsize, ysize; | |
79e53945 JB |
1045 | |
1046 | if (!tv_mode) | |
1047 | return; /* can't happen (mode_prepare prevents this) */ | |
1048 | ||
d2d9f232 ZW |
1049 | tv_ctl = I915_READ(TV_CTL); |
1050 | tv_ctl &= TV_CTL_SAVE; | |
79e53945 | 1051 | |
ea5b213a | 1052 | switch (intel_tv->type) { |
79e53945 JB |
1053 | default: |
1054 | case DRM_MODE_CONNECTOR_Unknown: | |
1055 | case DRM_MODE_CONNECTOR_Composite: | |
1056 | tv_ctl |= TV_ENC_OUTPUT_COMPOSITE; | |
1057 | video_levels = tv_mode->composite_levels; | |
1058 | color_conversion = tv_mode->composite_color; | |
1059 | burst_ena = tv_mode->burst_ena; | |
1060 | break; | |
1061 | case DRM_MODE_CONNECTOR_Component: | |
1062 | tv_ctl |= TV_ENC_OUTPUT_COMPONENT; | |
1063 | video_levels = &component_levels; | |
1064 | if (tv_mode->burst_ena) | |
1065 | color_conversion = &sdtv_csc_yprpb; | |
1066 | else | |
1067 | color_conversion = &hdtv_csc_yprpb; | |
1068 | burst_ena = false; | |
1069 | break; | |
1070 | case DRM_MODE_CONNECTOR_SVIDEO: | |
1071 | tv_ctl |= TV_ENC_OUTPUT_SVIDEO; | |
1072 | video_levels = tv_mode->svideo_levels; | |
1073 | color_conversion = tv_mode->svideo_color; | |
1074 | burst_ena = tv_mode->burst_ena; | |
1075 | break; | |
1076 | } | |
79e53945 JB |
1077 | |
1078 | if (intel_crtc->pipe == 1) | |
1079 | tv_ctl |= TV_ENC_PIPEB_SELECT; | |
1080 | tv_ctl |= tv_mode->oversample; | |
1081 | ||
1082 | if (tv_mode->progressive) | |
1083 | tv_ctl |= TV_PROGRESSIVE; | |
1084 | if (tv_mode->trilevel_sync) | |
1085 | tv_ctl |= TV_TRILEVEL_SYNC; | |
1086 | if (tv_mode->pal_burst) | |
1087 | tv_ctl |= TV_PAL_BURST; | |
d271817b | 1088 | |
79e53945 | 1089 | scctl1 = 0; |
d271817b | 1090 | if (tv_mode->dda1_inc) |
79e53945 | 1091 | scctl1 |= TV_SC_DDA1_EN; |
79e53945 JB |
1092 | if (tv_mode->dda2_inc) |
1093 | scctl1 |= TV_SC_DDA2_EN; | |
79e53945 JB |
1094 | if (tv_mode->dda3_inc) |
1095 | scctl1 |= TV_SC_DDA3_EN; | |
79e53945 | 1096 | scctl1 |= tv_mode->sc_reset; |
d271817b CW |
1097 | if (video_levels) |
1098 | scctl1 |= video_levels->burst << TV_BURST_LEVEL_SHIFT; | |
79e53945 JB |
1099 | scctl1 |= tv_mode->dda1_inc << TV_SCDDA1_INC_SHIFT; |
1100 | ||
1101 | scctl2 = tv_mode->dda2_size << TV_SCDDA2_SIZE_SHIFT | | |
1102 | tv_mode->dda2_inc << TV_SCDDA2_INC_SHIFT; | |
1103 | ||
1104 | scctl3 = tv_mode->dda3_size << TV_SCDDA3_SIZE_SHIFT | | |
1105 | tv_mode->dda3_inc << TV_SCDDA3_INC_SHIFT; | |
1106 | ||
1107 | /* Enable two fixes for the chips that need them. */ | |
5da92eef | 1108 | if (IS_I915GM(dev)) |
79e53945 JB |
1109 | tv_ctl |= TV_ENC_C0_FIX | TV_ENC_SDP_FIX; |
1110 | ||
8cb92203 DV |
1111 | set_tv_mode_timings(dev_priv, tv_mode, burst_ena); |
1112 | ||
79e53945 JB |
1113 | I915_WRITE(TV_SC_CTL_1, scctl1); |
1114 | I915_WRITE(TV_SC_CTL_2, scctl2); | |
1115 | I915_WRITE(TV_SC_CTL_3, scctl3); | |
1116 | ||
b8866ef8 | 1117 | set_color_conversion(dev_priv, color_conversion); |
79e53945 | 1118 | |
a6c45cf0 | 1119 | if (INTEL_INFO(dev)->gen >= 4) |
d2d9f232 ZW |
1120 | I915_WRITE(TV_CLR_KNOBS, 0x00404000); |
1121 | else | |
1122 | I915_WRITE(TV_CLR_KNOBS, 0x00606000); | |
1123 | ||
79e53945 JB |
1124 | if (video_levels) |
1125 | I915_WRITE(TV_CLR_LEVEL, | |
1126 | ((video_levels->black << TV_BLACK_LEVEL_SHIFT) | | |
1127 | (video_levels->blank << TV_BLANK_LEVEL_SHIFT))); | |
3fa2dd14 DV |
1128 | |
1129 | assert_pipe_disabled(dev_priv, intel_crtc->pipe); | |
1130 | ||
1131 | /* Filter ctl must be set before TV_WIN_SIZE */ | |
1132 | I915_WRITE(TV_FILTER_CTL_1, TV_AUTO_SCALE); | |
1133 | xsize = tv_mode->hblank_start - tv_mode->hblank_end; | |
1134 | if (tv_mode->progressive) | |
1135 | ysize = tv_mode->nbr_end + 1; | |
1136 | else | |
1137 | ysize = 2*tv_mode->nbr_end + 1; | |
1138 | ||
1139 | xpos += intel_tv->margin[TV_MARGIN_LEFT]; | |
1140 | ypos += intel_tv->margin[TV_MARGIN_TOP]; | |
1141 | xsize -= (intel_tv->margin[TV_MARGIN_LEFT] + | |
1142 | intel_tv->margin[TV_MARGIN_RIGHT]); | |
1143 | ysize -= (intel_tv->margin[TV_MARGIN_TOP] + | |
1144 | intel_tv->margin[TV_MARGIN_BOTTOM]); | |
1145 | I915_WRITE(TV_WIN_POS, (xpos<<16)|ypos); | |
1146 | I915_WRITE(TV_WIN_SIZE, (xsize<<16)|ysize); | |
79e53945 JB |
1147 | |
1148 | j = 0; | |
1149 | for (i = 0; i < 60; i++) | |
184d7c06 | 1150 | I915_WRITE(TV_H_LUMA(i), tv_mode->filter_table[j++]); |
79e53945 | 1151 | for (i = 0; i < 60; i++) |
184d7c06 | 1152 | I915_WRITE(TV_H_CHROMA(i), tv_mode->filter_table[j++]); |
79e53945 | 1153 | for (i = 0; i < 43; i++) |
184d7c06 | 1154 | I915_WRITE(TV_V_LUMA(i), tv_mode->filter_table[j++]); |
79e53945 | 1155 | for (i = 0; i < 43; i++) |
184d7c06 | 1156 | I915_WRITE(TV_V_CHROMA(i), tv_mode->filter_table[j++]); |
b8ed2a4f | 1157 | I915_WRITE(TV_DAC, I915_READ(TV_DAC) & TV_DAC_SAVE); |
79e53945 JB |
1158 | I915_WRITE(TV_CTL, tv_ctl); |
1159 | } | |
1160 | ||
1161 | static const struct drm_display_mode reported_modes[] = { | |
1162 | { | |
1163 | .name = "NTSC 480i", | |
1164 | .clock = 107520, | |
1165 | .hdisplay = 1280, | |
1166 | .hsync_start = 1368, | |
1167 | .hsync_end = 1496, | |
1168 | .htotal = 1712, | |
1169 | ||
1170 | .vdisplay = 1024, | |
1171 | .vsync_start = 1027, | |
1172 | .vsync_end = 1034, | |
1173 | .vtotal = 1104, | |
1174 | .type = DRM_MODE_TYPE_DRIVER, | |
1175 | }, | |
1176 | }; | |
1177 | ||
1178 | /** | |
1179 | * Detects TV presence by checking for load. | |
1180 | * | |
1181 | * Requires that the current pipe's DPLL is active. | |
1182 | ||
1183 | * \return true if TV is connected. | |
1184 | * \return false if TV is disconnected. | |
1185 | */ | |
1186 | static int | |
0206e353 | 1187 | intel_tv_detect_type(struct intel_tv *intel_tv, |
8102e126 | 1188 | struct drm_connector *connector) |
79e53945 | 1189 | { |
0eadc624 | 1190 | struct drm_crtc *crtc = connector->state->crtc; |
835bff7e | 1191 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
0eadc624 | 1192 | struct drm_device *dev = connector->dev; |
fac5e23e | 1193 | struct drm_i915_private *dev_priv = to_i915(dev); |
79e53945 JB |
1194 | u32 tv_ctl, save_tv_ctl; |
1195 | u32 tv_dac, save_tv_dac; | |
974b9331 | 1196 | int type; |
79e53945 JB |
1197 | |
1198 | /* Disable TV interrupts around load detect or we'll recurse */ | |
8102e126 | 1199 | if (connector->polled & DRM_CONNECTOR_POLL_HPD) { |
2795aa48 | 1200 | spin_lock_irq(&dev_priv->irq_lock); |
8102e126 | 1201 | i915_disable_pipestat(dev_priv, 0, |
755e9019 ID |
1202 | PIPE_HOTPLUG_INTERRUPT_STATUS | |
1203 | PIPE_HOTPLUG_TV_INTERRUPT_STATUS); | |
2795aa48 | 1204 | spin_unlock_irq(&dev_priv->irq_lock); |
8102e126 | 1205 | } |
79e53945 | 1206 | |
974b9331 CW |
1207 | save_tv_dac = tv_dac = I915_READ(TV_DAC); |
1208 | save_tv_ctl = tv_ctl = I915_READ(TV_CTL); | |
1209 | ||
1210 | /* Poll for TV detection */ | |
1211 | tv_ctl &= ~(TV_ENC_ENABLE | TV_TEST_MODE_MASK); | |
8ed9a5bc | 1212 | tv_ctl |= TV_TEST_MODE_MONITOR_DETECT; |
835bff7e KP |
1213 | if (intel_crtc->pipe == 1) |
1214 | tv_ctl |= TV_ENC_PIPEB_SELECT; | |
1215 | else | |
1216 | tv_ctl &= ~TV_ENC_PIPEB_SELECT; | |
974b9331 CW |
1217 | |
1218 | tv_dac &= ~(TVDAC_SENSE_MASK | DAC_A_MASK | DAC_B_MASK | DAC_C_MASK); | |
8ed9a5bc | 1219 | tv_dac |= (TVDAC_STATE_CHG_EN | |
1220 | TVDAC_A_SENSE_CTL | | |
1221 | TVDAC_B_SENSE_CTL | | |
1222 | TVDAC_C_SENSE_CTL | | |
1223 | DAC_CTL_OVERRIDE | | |
1224 | DAC_A_0_7_V | | |
1225 | DAC_B_0_7_V | | |
1226 | DAC_C_0_7_V); | |
974b9331 | 1227 | |
d42c9e2c DV |
1228 | |
1229 | /* | |
1230 | * The TV sense state should be cleared to zero on cantiga platform. Otherwise | |
1231 | * the TV is misdetected. This is hardware requirement. | |
1232 | */ | |
1233 | if (IS_GM45(dev)) | |
1234 | tv_dac &= ~(TVDAC_STATE_CHG_EN | TVDAC_A_SENSE_CTL | | |
1235 | TVDAC_B_SENSE_CTL | TVDAC_C_SENSE_CTL); | |
1236 | ||
8ed9a5bc | 1237 | I915_WRITE(TV_CTL, tv_ctl); |
1238 | I915_WRITE(TV_DAC, tv_dac); | |
4f233eff | 1239 | POSTING_READ(TV_DAC); |
4f233eff | 1240 | |
0eadc624 | 1241 | intel_wait_for_vblank(dev, intel_crtc->pipe); |
29e1316a | 1242 | |
974b9331 | 1243 | type = -1; |
2bf71160 KP |
1244 | tv_dac = I915_READ(TV_DAC); |
1245 | DRM_DEBUG_KMS("TV detected: %x, %x\n", tv_ctl, tv_dac); | |
1246 | /* | |
1247 | * A B C | |
1248 | * 0 1 1 Composite | |
1249 | * 1 0 X svideo | |
1250 | * 0 0 0 Component | |
1251 | */ | |
1252 | if ((tv_dac & TVDAC_SENSE_MASK) == (TVDAC_B_SENSE | TVDAC_C_SENSE)) { | |
1253 | DRM_DEBUG_KMS("Detected Composite TV connection\n"); | |
1254 | type = DRM_MODE_CONNECTOR_Composite; | |
1255 | } else if ((tv_dac & (TVDAC_A_SENSE|TVDAC_B_SENSE)) == TVDAC_A_SENSE) { | |
1256 | DRM_DEBUG_KMS("Detected S-Video TV connection\n"); | |
1257 | type = DRM_MODE_CONNECTOR_SVIDEO; | |
1258 | } else if ((tv_dac & TVDAC_SENSE_MASK) == 0) { | |
1259 | DRM_DEBUG_KMS("Detected Component TV connection\n"); | |
1260 | type = DRM_MODE_CONNECTOR_Component; | |
1261 | } else { | |
1262 | DRM_DEBUG_KMS("Unrecognised TV connection\n"); | |
1263 | type = -1; | |
79e53945 JB |
1264 | } |
1265 | ||
974b9331 CW |
1266 | I915_WRITE(TV_DAC, save_tv_dac & ~TVDAC_STATE_CHG_EN); |
1267 | I915_WRITE(TV_CTL, save_tv_ctl); | |
bf2125e2 DV |
1268 | POSTING_READ(TV_CTL); |
1269 | ||
1270 | /* For unknown reasons the hw barfs if we don't do this vblank wait. */ | |
0eadc624 | 1271 | intel_wait_for_vblank(dev, intel_crtc->pipe); |
974b9331 | 1272 | |
79e53945 | 1273 | /* Restore interrupt config */ |
8102e126 | 1274 | if (connector->polled & DRM_CONNECTOR_POLL_HPD) { |
2795aa48 | 1275 | spin_lock_irq(&dev_priv->irq_lock); |
8102e126 | 1276 | i915_enable_pipestat(dev_priv, 0, |
755e9019 ID |
1277 | PIPE_HOTPLUG_INTERRUPT_STATUS | |
1278 | PIPE_HOTPLUG_TV_INTERRUPT_STATUS); | |
2795aa48 | 1279 | spin_unlock_irq(&dev_priv->irq_lock); |
8102e126 | 1280 | } |
79e53945 JB |
1281 | |
1282 | return type; | |
1283 | } | |
1284 | ||
213c2e64 ML |
1285 | /* |
1286 | * Here we set accurate tv format according to connector type | |
1287 | * i.e Component TV should not be assigned by NTSC or PAL | |
1288 | */ | |
1289 | static void intel_tv_find_better_format(struct drm_connector *connector) | |
1290 | { | |
df0e9248 | 1291 | struct intel_tv *intel_tv = intel_attached_tv(connector); |
ea5b213a | 1292 | const struct tv_mode *tv_mode = intel_tv_mode_find(intel_tv); |
213c2e64 ML |
1293 | int i; |
1294 | ||
ea5b213a | 1295 | if ((intel_tv->type == DRM_MODE_CONNECTOR_Component) == |
213c2e64 ML |
1296 | tv_mode->component_only) |
1297 | return; | |
1298 | ||
1299 | ||
53abb679 | 1300 | for (i = 0; i < ARRAY_SIZE(tv_modes); i++) { |
213c2e64 ML |
1301 | tv_mode = tv_modes + i; |
1302 | ||
ea5b213a | 1303 | if ((intel_tv->type == DRM_MODE_CONNECTOR_Component) == |
213c2e64 ML |
1304 | tv_mode->component_only) |
1305 | break; | |
1306 | } | |
1307 | ||
ea5b213a | 1308 | intel_tv->tv_format = tv_mode->name; |
662595df | 1309 | drm_object_property_set_value(&connector->base, |
213c2e64 ML |
1310 | connector->dev->mode_config.tv_mode_property, i); |
1311 | } | |
1312 | ||
79e53945 JB |
1313 | /** |
1314 | * Detect the TV connection. | |
1315 | * | |
1316 | * Currently this always returns CONNECTOR_STATUS_UNKNOWN, as we need to be sure | |
1317 | * we have a pipe programmed in order to probe the TV. | |
1318 | */ | |
1319 | static enum drm_connector_status | |
930a9e28 | 1320 | intel_tv_detect(struct drm_connector *connector, bool force) |
79e53945 | 1321 | { |
79e53945 | 1322 | struct drm_display_mode mode; |
df0e9248 | 1323 | struct intel_tv *intel_tv = intel_attached_tv(connector); |
bbfb44e8 | 1324 | enum drm_connector_status status; |
ea5b213a | 1325 | int type; |
79e53945 | 1326 | |
164c8598 | 1327 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s] force=%d\n", |
c23cc417 | 1328 | connector->base.id, connector->name, |
164c8598 CW |
1329 | force); |
1330 | ||
79e53945 | 1331 | mode = reported_modes[0]; |
79e53945 | 1332 | |
38de45c5 | 1333 | if (force) { |
8261b191 | 1334 | struct intel_load_detect_pipe tmp; |
51fd371b | 1335 | struct drm_modeset_acquire_ctx ctx; |
ea5b213a | 1336 | |
208bf9fd VS |
1337 | drm_modeset_acquire_init(&ctx, 0); |
1338 | ||
51fd371b | 1339 | if (intel_get_load_detect_pipe(connector, &mode, &tmp, &ctx)) { |
8102e126 | 1340 | type = intel_tv_detect_type(intel_tv, connector); |
49172fee | 1341 | intel_release_load_detect_pipe(connector, &tmp, &ctx); |
bbfb44e8 VS |
1342 | status = type < 0 ? |
1343 | connector_status_disconnected : | |
1344 | connector_status_connected; | |
79e53945 | 1345 | } else |
bbfb44e8 | 1346 | status = connector_status_unknown; |
208bf9fd VS |
1347 | |
1348 | drm_modeset_drop_locks(&ctx); | |
1349 | drm_modeset_acquire_fini(&ctx); | |
7b334fcb CW |
1350 | } else |
1351 | return connector->status; | |
bf5a269a | 1352 | |
bbfb44e8 VS |
1353 | if (status != connector_status_connected) |
1354 | return status; | |
79e53945 | 1355 | |
d5627663 | 1356 | intel_tv->type = type; |
213c2e64 | 1357 | intel_tv_find_better_format(connector); |
d5627663 | 1358 | |
79e53945 JB |
1359 | return connector_status_connected; |
1360 | } | |
1361 | ||
763a4a01 CW |
1362 | static const struct input_res { |
1363 | const char *name; | |
79e53945 | 1364 | int w, h; |
763a4a01 | 1365 | } input_res_table[] = { |
79e53945 JB |
1366 | {"640x480", 640, 480}, |
1367 | {"800x600", 800, 600}, | |
1368 | {"1024x768", 1024, 768}, | |
1369 | {"1280x1024", 1280, 1024}, | |
1370 | {"848x480", 848, 480}, | |
1371 | {"1280x720", 1280, 720}, | |
1372 | {"1920x1080", 1920, 1080}, | |
1373 | }; | |
1374 | ||
bcae2ca8 | 1375 | /* |
1376 | * Chose preferred mode according to line number of TV format | |
1377 | */ | |
1378 | static void | |
1379 | intel_tv_chose_preferred_modes(struct drm_connector *connector, | |
1380 | struct drm_display_mode *mode_ptr) | |
1381 | { | |
df0e9248 | 1382 | struct intel_tv *intel_tv = intel_attached_tv(connector); |
ea5b213a | 1383 | const struct tv_mode *tv_mode = intel_tv_mode_find(intel_tv); |
bcae2ca8 | 1384 | |
1385 | if (tv_mode->nbr_end < 480 && mode_ptr->vdisplay == 480) | |
1386 | mode_ptr->type |= DRM_MODE_TYPE_PREFERRED; | |
1387 | else if (tv_mode->nbr_end > 480) { | |
1388 | if (tv_mode->progressive == true && tv_mode->nbr_end < 720) { | |
1389 | if (mode_ptr->vdisplay == 720) | |
1390 | mode_ptr->type |= DRM_MODE_TYPE_PREFERRED; | |
1391 | } else if (mode_ptr->vdisplay == 1080) | |
1392 | mode_ptr->type |= DRM_MODE_TYPE_PREFERRED; | |
1393 | } | |
1394 | } | |
1395 | ||
79e53945 JB |
1396 | /** |
1397 | * Stub get_modes function. | |
1398 | * | |
1399 | * This should probably return a set of fixed modes, unless we can figure out | |
1400 | * how to probe modes off of TV connections. | |
1401 | */ | |
1402 | ||
1403 | static int | |
1404 | intel_tv_get_modes(struct drm_connector *connector) | |
1405 | { | |
1406 | struct drm_display_mode *mode_ptr; | |
df0e9248 | 1407 | struct intel_tv *intel_tv = intel_attached_tv(connector); |
ea5b213a | 1408 | const struct tv_mode *tv_mode = intel_tv_mode_find(intel_tv); |
02c5dd98 ZW |
1409 | int j, count = 0; |
1410 | u64 tmp; | |
79e53945 | 1411 | |
04ad327f | 1412 | for (j = 0; j < ARRAY_SIZE(input_res_table); |
79e53945 | 1413 | j++) { |
763a4a01 | 1414 | const struct input_res *input = &input_res_table[j]; |
79e53945 JB |
1415 | unsigned int hactive_s = input->w; |
1416 | unsigned int vactive_s = input->h; | |
1417 | ||
1418 | if (tv_mode->max_srcw && input->w > tv_mode->max_srcw) | |
1419 | continue; | |
1420 | ||
1421 | if (input->w > 1024 && (!tv_mode->progressive | |
1422 | && !tv_mode->component_only)) | |
1423 | continue; | |
1424 | ||
02c5dd98 ZW |
1425 | mode_ptr = drm_mode_create(connector->dev); |
1426 | if (!mode_ptr) | |
1427 | continue; | |
79e53945 | 1428 | strncpy(mode_ptr->name, input->name, DRM_DISPLAY_MODE_LEN); |
05d25214 | 1429 | mode_ptr->name[DRM_DISPLAY_MODE_LEN - 1] = '\0'; |
79e53945 JB |
1430 | |
1431 | mode_ptr->hdisplay = hactive_s; | |
1432 | mode_ptr->hsync_start = hactive_s + 1; | |
1433 | mode_ptr->hsync_end = hactive_s + 64; | |
1434 | if (mode_ptr->hsync_end <= mode_ptr->hsync_start) | |
1435 | mode_ptr->hsync_end = mode_ptr->hsync_start + 1; | |
1436 | mode_ptr->htotal = hactive_s + 96; | |
1437 | ||
1438 | mode_ptr->vdisplay = vactive_s; | |
1439 | mode_ptr->vsync_start = vactive_s + 1; | |
1440 | mode_ptr->vsync_end = vactive_s + 32; | |
1441 | if (mode_ptr->vsync_end <= mode_ptr->vsync_start) | |
1442 | mode_ptr->vsync_end = mode_ptr->vsync_start + 1; | |
1443 | mode_ptr->vtotal = vactive_s + 33; | |
1444 | ||
02c5dd98 ZW |
1445 | tmp = (u64) tv_mode->refresh * mode_ptr->vtotal; |
1446 | tmp *= mode_ptr->htotal; | |
1447 | tmp = div_u64(tmp, 1000000); | |
1448 | mode_ptr->clock = (int) tmp; | |
79e53945 JB |
1449 | |
1450 | mode_ptr->type = DRM_MODE_TYPE_DRIVER; | |
bcae2ca8 | 1451 | intel_tv_chose_preferred_modes(connector, mode_ptr); |
79e53945 | 1452 | drm_mode_probed_add(connector, mode_ptr); |
02c5dd98 | 1453 | count++; |
79e53945 JB |
1454 | } |
1455 | ||
02c5dd98 | 1456 | return count; |
79e53945 JB |
1457 | } |
1458 | ||
1459 | static void | |
0206e353 | 1460 | intel_tv_destroy(struct drm_connector *connector) |
79e53945 | 1461 | { |
79e53945 | 1462 | drm_connector_cleanup(connector); |
0c41ee2b | 1463 | kfree(connector); |
79e53945 JB |
1464 | } |
1465 | ||
1466 | ||
1467 | static int | |
1468 | intel_tv_set_property(struct drm_connector *connector, struct drm_property *property, | |
1469 | uint64_t val) | |
1470 | { | |
1471 | struct drm_device *dev = connector->dev; | |
df0e9248 CW |
1472 | struct intel_tv *intel_tv = intel_attached_tv(connector); |
1473 | struct drm_crtc *crtc = intel_tv->base.base.crtc; | |
79e53945 | 1474 | int ret = 0; |
ebcc8f2e | 1475 | bool changed = false; |
79e53945 | 1476 | |
662595df | 1477 | ret = drm_object_property_set_value(&connector->base, property, val); |
79e53945 JB |
1478 | if (ret < 0) |
1479 | goto out; | |
1480 | ||
ebcc8f2e | 1481 | if (property == dev->mode_config.tv_left_margin_property && |
ea5b213a CW |
1482 | intel_tv->margin[TV_MARGIN_LEFT] != val) { |
1483 | intel_tv->margin[TV_MARGIN_LEFT] = val; | |
ebcc8f2e ZW |
1484 | changed = true; |
1485 | } else if (property == dev->mode_config.tv_right_margin_property && | |
ea5b213a CW |
1486 | intel_tv->margin[TV_MARGIN_RIGHT] != val) { |
1487 | intel_tv->margin[TV_MARGIN_RIGHT] = val; | |
ebcc8f2e ZW |
1488 | changed = true; |
1489 | } else if (property == dev->mode_config.tv_top_margin_property && | |
ea5b213a CW |
1490 | intel_tv->margin[TV_MARGIN_TOP] != val) { |
1491 | intel_tv->margin[TV_MARGIN_TOP] = val; | |
ebcc8f2e ZW |
1492 | changed = true; |
1493 | } else if (property == dev->mode_config.tv_bottom_margin_property && | |
ea5b213a CW |
1494 | intel_tv->margin[TV_MARGIN_BOTTOM] != val) { |
1495 | intel_tv->margin[TV_MARGIN_BOTTOM] = val; | |
ebcc8f2e ZW |
1496 | changed = true; |
1497 | } else if (property == dev->mode_config.tv_mode_property) { | |
2991196f | 1498 | if (val >= ARRAY_SIZE(tv_modes)) { |
79e53945 JB |
1499 | ret = -EINVAL; |
1500 | goto out; | |
1501 | } | |
ea5b213a | 1502 | if (!strcmp(intel_tv->tv_format, tv_modes[val].name)) |
ebcc8f2e ZW |
1503 | goto out; |
1504 | ||
ea5b213a | 1505 | intel_tv->tv_format = tv_modes[val].name; |
ebcc8f2e | 1506 | changed = true; |
79e53945 JB |
1507 | } else { |
1508 | ret = -EINVAL; | |
1509 | goto out; | |
1510 | } | |
1511 | ||
7d6ff785 | 1512 | if (changed && crtc) |
c0c36b94 | 1513 | intel_crtc_restore_mode(crtc); |
79e53945 JB |
1514 | out: |
1515 | return ret; | |
1516 | } | |
1517 | ||
79e53945 | 1518 | static const struct drm_connector_funcs intel_tv_connector_funcs = { |
4d688a2a | 1519 | .dpms = drm_atomic_helper_connector_dpms, |
79e53945 | 1520 | .detect = intel_tv_detect, |
1ebaa0b9 | 1521 | .late_register = intel_connector_register, |
c191eca1 | 1522 | .early_unregister = intel_connector_unregister, |
79e53945 JB |
1523 | .destroy = intel_tv_destroy, |
1524 | .set_property = intel_tv_set_property, | |
2545e4a6 | 1525 | .atomic_get_property = intel_connector_atomic_get_property, |
79e53945 | 1526 | .fill_modes = drm_helper_probe_single_connector_modes, |
c6f95f27 | 1527 | .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, |
98969725 | 1528 | .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state, |
79e53945 JB |
1529 | }; |
1530 | ||
1531 | static const struct drm_connector_helper_funcs intel_tv_connector_helper_funcs = { | |
1532 | .mode_valid = intel_tv_mode_valid, | |
1533 | .get_modes = intel_tv_get_modes, | |
79e53945 JB |
1534 | }; |
1535 | ||
79e53945 | 1536 | static const struct drm_encoder_funcs intel_tv_enc_funcs = { |
ea5b213a | 1537 | .destroy = intel_encoder_destroy, |
79e53945 JB |
1538 | }; |
1539 | ||
79e53945 JB |
1540 | void |
1541 | intel_tv_init(struct drm_device *dev) | |
1542 | { | |
fac5e23e | 1543 | struct drm_i915_private *dev_priv = to_i915(dev); |
79e53945 | 1544 | struct drm_connector *connector; |
ea5b213a | 1545 | struct intel_tv *intel_tv; |
21d40d37 | 1546 | struct intel_encoder *intel_encoder; |
0c41ee2b | 1547 | struct intel_connector *intel_connector; |
79e53945 | 1548 | u32 tv_dac_on, tv_dac_off, save_tv_dac; |
b7c914b3 | 1549 | const char *tv_format_names[ARRAY_SIZE(tv_modes)]; |
79e53945 JB |
1550 | int i, initial_mode = 0; |
1551 | ||
1552 | if ((I915_READ(TV_CTL) & TV_FUSE_STATE_MASK) == TV_FUSE_STATE_DISABLED) | |
1553 | return; | |
1554 | ||
3bdd14d5 | 1555 | if (!intel_bios_is_tv_present(dev_priv)) { |
c3561438 ZY |
1556 | DRM_DEBUG_KMS("Integrated TV is not present.\n"); |
1557 | return; | |
1558 | } | |
79e53945 JB |
1559 | |
1560 | /* | |
1561 | * Sanity check the TV output by checking to see if the | |
1562 | * DAC register holds a value | |
1563 | */ | |
1564 | save_tv_dac = I915_READ(TV_DAC); | |
1565 | ||
1566 | I915_WRITE(TV_DAC, save_tv_dac | TVDAC_STATE_CHG_EN); | |
1567 | tv_dac_on = I915_READ(TV_DAC); | |
1568 | ||
1569 | I915_WRITE(TV_DAC, save_tv_dac & ~TVDAC_STATE_CHG_EN); | |
1570 | tv_dac_off = I915_READ(TV_DAC); | |
1571 | ||
1572 | I915_WRITE(TV_DAC, save_tv_dac); | |
1573 | ||
1574 | /* | |
1575 | * If the register does not hold the state change enable | |
1576 | * bit, (either as a 0 or a 1), assume it doesn't really | |
1577 | * exist | |
1578 | */ | |
1579 | if ((tv_dac_on & TVDAC_STATE_CHG_EN) == 0 || | |
1580 | (tv_dac_off & TVDAC_STATE_CHG_EN) != 0) | |
1581 | return; | |
1582 | ||
b14c5679 | 1583 | intel_tv = kzalloc(sizeof(*intel_tv), GFP_KERNEL); |
ea5b213a | 1584 | if (!intel_tv) { |
79e53945 JB |
1585 | return; |
1586 | } | |
f8aed700 | 1587 | |
08d9bc92 | 1588 | intel_connector = intel_connector_alloc(); |
0c41ee2b | 1589 | if (!intel_connector) { |
ea5b213a | 1590 | kfree(intel_tv); |
0c41ee2b ZW |
1591 | return; |
1592 | } | |
1593 | ||
ea5b213a | 1594 | intel_encoder = &intel_tv->base; |
0c41ee2b | 1595 | connector = &intel_connector->base; |
79e53945 | 1596 | |
8102e126 CW |
1597 | /* The documentation, for the older chipsets at least, recommend |
1598 | * using a polling method rather than hotplug detection for TVs. | |
1599 | * This is because in order to perform the hotplug detection, the PLLs | |
1600 | * for the TV must be kept alive increasing power drain and starving | |
1601 | * bandwidth from other encoders. Notably for instance, it causes | |
1602 | * pipe underruns on Crestline when this encoder is supposedly idle. | |
1603 | * | |
1604 | * More recent chipsets favour HDMI rather than integrated S-Video. | |
1605 | */ | |
821450c6 | 1606 | intel_connector->polled = DRM_CONNECTOR_POLL_CONNECT; |
8102e126 | 1607 | |
79e53945 JB |
1608 | drm_connector_init(dev, connector, &intel_tv_connector_funcs, |
1609 | DRM_MODE_CONNECTOR_SVIDEO); | |
1610 | ||
4ef69c7a | 1611 | drm_encoder_init(dev, &intel_encoder->base, &intel_tv_enc_funcs, |
580d8ed5 | 1612 | DRM_MODE_ENCODER_TVDAC, "TV"); |
79e53945 | 1613 | |
5d2d38dd | 1614 | intel_encoder->compute_config = intel_tv_compute_config; |
7a495cfd | 1615 | intel_encoder->get_config = intel_tv_get_config; |
809a2a8b | 1616 | intel_encoder->pre_enable = intel_tv_pre_enable; |
6b5756a0 DV |
1617 | intel_encoder->enable = intel_enable_tv; |
1618 | intel_encoder->disable = intel_disable_tv; | |
9a8ee983 DV |
1619 | intel_encoder->get_hw_state = intel_tv_get_hw_state; |
1620 | intel_connector->get_hw_state = intel_connector_get_hw_state; | |
6b5756a0 | 1621 | |
df0e9248 | 1622 | intel_connector_attach_encoder(intel_connector, intel_encoder); |
03cdc1d4 | 1623 | |
21d40d37 | 1624 | intel_encoder->type = INTEL_OUTPUT_TVOUT; |
03cdc1d4 | 1625 | intel_encoder->port = PORT_NONE; |
21d40d37 | 1626 | intel_encoder->crtc_mask = (1 << 0) | (1 << 1); |
bc079e8b | 1627 | intel_encoder->cloneable = 0; |
4ef69c7a | 1628 | intel_encoder->base.possible_crtcs = ((1 << 0) | (1 << 1)); |
ea5b213a | 1629 | intel_tv->type = DRM_MODE_CONNECTOR_Unknown; |
79e53945 JB |
1630 | |
1631 | /* BIOS margin values */ | |
ea5b213a CW |
1632 | intel_tv->margin[TV_MARGIN_LEFT] = 54; |
1633 | intel_tv->margin[TV_MARGIN_TOP] = 36; | |
1634 | intel_tv->margin[TV_MARGIN_RIGHT] = 46; | |
1635 | intel_tv->margin[TV_MARGIN_BOTTOM] = 37; | |
79e53945 | 1636 | |
763a4a01 | 1637 | intel_tv->tv_format = tv_modes[initial_mode].name; |
79e53945 | 1638 | |
79e53945 JB |
1639 | drm_connector_helper_add(connector, &intel_tv_connector_helper_funcs); |
1640 | connector->interlace_allowed = false; | |
1641 | connector->doublescan_allowed = false; | |
1642 | ||
1643 | /* Create TV properties then attach current values */ | |
2991196f | 1644 | for (i = 0; i < ARRAY_SIZE(tv_modes); i++) |
b7c914b3 | 1645 | tv_format_names[i] = tv_modes[i].name; |
763a4a01 CW |
1646 | drm_mode_create_tv_properties(dev, |
1647 | ARRAY_SIZE(tv_modes), | |
1648 | tv_format_names); | |
79e53945 | 1649 | |
662595df | 1650 | drm_object_attach_property(&connector->base, dev->mode_config.tv_mode_property, |
79e53945 | 1651 | initial_mode); |
662595df | 1652 | drm_object_attach_property(&connector->base, |
79e53945 | 1653 | dev->mode_config.tv_left_margin_property, |
ea5b213a | 1654 | intel_tv->margin[TV_MARGIN_LEFT]); |
662595df | 1655 | drm_object_attach_property(&connector->base, |
79e53945 | 1656 | dev->mode_config.tv_top_margin_property, |
ea5b213a | 1657 | intel_tv->margin[TV_MARGIN_TOP]); |
662595df | 1658 | drm_object_attach_property(&connector->base, |
79e53945 | 1659 | dev->mode_config.tv_right_margin_property, |
ea5b213a | 1660 | intel_tv->margin[TV_MARGIN_RIGHT]); |
662595df | 1661 | drm_object_attach_property(&connector->base, |
79e53945 | 1662 | dev->mode_config.tv_bottom_margin_property, |
ea5b213a | 1663 | intel_tv->margin[TV_MARGIN_BOTTOM]); |
79e53945 | 1664 | } |