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7198e6b0 RC |
1 | /* |
2 | * Copyright (C) 2013 Red Hat | |
3 | * Author: Rob Clark <robdclark@gmail.com> | |
4 | * | |
5 | * This program is free software; you can redistribute it and/or modify it | |
6 | * under the terms of the GNU General Public License version 2 as published by | |
7 | * the Free Software Foundation. | |
8 | * | |
9 | * This program is distributed in the hope that it will be useful, but WITHOUT | |
10 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
11 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
12 | * more details. | |
13 | * | |
14 | * You should have received a copy of the GNU General Public License along with | |
15 | * this program. If not, see <http://www.gnu.org/licenses/>. | |
16 | */ | |
17 | ||
18 | #include "adreno_gpu.h" | |
19 | #include "msm_gem.h" | |
871d812a | 20 | #include "msm_mmu.h" |
7198e6b0 RC |
21 | |
22 | struct adreno_info { | |
23 | struct adreno_rev rev; | |
24 | uint32_t revn; | |
25 | const char *name; | |
26 | const char *pm4fw, *pfpfw; | |
27 | uint32_t gmem; | |
28 | }; | |
29 | ||
30 | #define ANY_ID 0xff | |
31 | ||
32 | static const struct adreno_info gpulist[] = { | |
33 | { | |
34 | .rev = ADRENO_REV(3, 0, 5, ANY_ID), | |
35 | .revn = 305, | |
36 | .name = "A305", | |
37 | .pm4fw = "a300_pm4.fw", | |
38 | .pfpfw = "a300_pfp.fw", | |
39 | .gmem = SZ_256K, | |
40 | }, { | |
41 | .rev = ADRENO_REV(3, 2, ANY_ID, ANY_ID), | |
42 | .revn = 320, | |
43 | .name = "A320", | |
44 | .pm4fw = "a300_pm4.fw", | |
45 | .pfpfw = "a300_pfp.fw", | |
46 | .gmem = SZ_512K, | |
47 | }, { | |
55459968 | 48 | .rev = ADRENO_REV(3, 3, 0, ANY_ID), |
7198e6b0 RC |
49 | .revn = 330, |
50 | .name = "A330", | |
51 | .pm4fw = "a330_pm4.fw", | |
52 | .pfpfw = "a330_pfp.fw", | |
53 | .gmem = SZ_1M, | |
54 | }, | |
55 | }; | |
56 | ||
3b57f23b RC |
57 | MODULE_FIRMWARE("a300_pm4.fw"); |
58 | MODULE_FIRMWARE("a300_pfp.fw"); | |
59 | MODULE_FIRMWARE("a330_pm4.fw"); | |
60 | MODULE_FIRMWARE("a330_pfp.fw"); | |
61 | ||
7198e6b0 RC |
62 | #define RB_SIZE SZ_32K |
63 | #define RB_BLKSIZE 16 | |
64 | ||
65 | int adreno_get_param(struct msm_gpu *gpu, uint32_t param, uint64_t *value) | |
66 | { | |
67 | struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); | |
68 | ||
69 | switch (param) { | |
70 | case MSM_PARAM_GPU_ID: | |
71 | *value = adreno_gpu->info->revn; | |
72 | return 0; | |
73 | case MSM_PARAM_GMEM_SIZE: | |
55459968 | 74 | *value = adreno_gpu->gmem; |
7198e6b0 RC |
75 | return 0; |
76 | default: | |
77 | DBG("%s: invalid param: %u", gpu->name, param); | |
78 | return -EINVAL; | |
79 | } | |
80 | } | |
81 | ||
82 | #define rbmemptr(adreno_gpu, member) \ | |
83 | ((adreno_gpu)->memptrs_iova + offsetof(struct adreno_rbmemptrs, member)) | |
84 | ||
85 | int adreno_hw_init(struct msm_gpu *gpu) | |
86 | { | |
87 | struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); | |
88 | ||
89 | DBG("%s", gpu->name); | |
90 | ||
91 | /* Setup REG_CP_RB_CNTL: */ | |
92 | gpu_write(gpu, REG_AXXX_CP_RB_CNTL, | |
93 | /* size is log2(quad-words): */ | |
94 | AXXX_CP_RB_CNTL_BUFSZ(ilog2(gpu->rb->size / 8)) | | |
55459968 | 95 | AXXX_CP_RB_CNTL_BLKSZ(ilog2(RB_BLKSIZE / 8))); |
7198e6b0 RC |
96 | |
97 | /* Setup ringbuffer address: */ | |
98 | gpu_write(gpu, REG_AXXX_CP_RB_BASE, gpu->rb_iova); | |
99 | gpu_write(gpu, REG_AXXX_CP_RB_RPTR_ADDR, rbmemptr(adreno_gpu, rptr)); | |
100 | ||
101 | /* Setup scratch/timestamp: */ | |
102 | gpu_write(gpu, REG_AXXX_SCRATCH_ADDR, rbmemptr(adreno_gpu, fence)); | |
103 | ||
104 | gpu_write(gpu, REG_AXXX_SCRATCH_UMSK, 0x1); | |
105 | ||
106 | return 0; | |
107 | } | |
108 | ||
109 | static uint32_t get_wptr(struct msm_ringbuffer *ring) | |
110 | { | |
111 | return ring->cur - ring->start; | |
112 | } | |
113 | ||
114 | uint32_t adreno_last_fence(struct msm_gpu *gpu) | |
115 | { | |
116 | struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); | |
117 | return adreno_gpu->memptrs->fence; | |
118 | } | |
119 | ||
bd6f82d8 RC |
120 | void adreno_recover(struct msm_gpu *gpu) |
121 | { | |
122 | struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); | |
123 | struct drm_device *dev = gpu->dev; | |
124 | int ret; | |
125 | ||
126 | gpu->funcs->pm_suspend(gpu); | |
127 | ||
128 | /* reset ringbuffer: */ | |
129 | gpu->rb->cur = gpu->rb->start; | |
130 | ||
131 | /* reset completed fence seqno, just discard anything pending: */ | |
132 | adreno_gpu->memptrs->fence = gpu->submitted_fence; | |
26791c48 RC |
133 | adreno_gpu->memptrs->rptr = 0; |
134 | adreno_gpu->memptrs->wptr = 0; | |
bd6f82d8 RC |
135 | |
136 | gpu->funcs->pm_resume(gpu); | |
137 | ret = gpu->funcs->hw_init(gpu); | |
138 | if (ret) { | |
139 | dev_err(dev->dev, "gpu hw init failed: %d\n", ret); | |
140 | /* hmm, oh well? */ | |
141 | } | |
142 | } | |
143 | ||
7198e6b0 RC |
144 | int adreno_submit(struct msm_gpu *gpu, struct msm_gem_submit *submit, |
145 | struct msm_file_private *ctx) | |
146 | { | |
147 | struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); | |
148 | struct msm_drm_private *priv = gpu->dev->dev_private; | |
149 | struct msm_ringbuffer *ring = gpu->rb; | |
150 | unsigned i, ibs = 0; | |
151 | ||
7198e6b0 RC |
152 | for (i = 0; i < submit->nr_cmds; i++) { |
153 | switch (submit->cmd[i].type) { | |
154 | case MSM_SUBMIT_CMD_IB_TARGET_BUF: | |
155 | /* ignore IB-targets */ | |
156 | break; | |
157 | case MSM_SUBMIT_CMD_CTX_RESTORE_BUF: | |
158 | /* ignore if there has not been a ctx switch: */ | |
159 | if (priv->lastctx == ctx) | |
160 | break; | |
161 | case MSM_SUBMIT_CMD_BUF: | |
162 | OUT_PKT3(ring, CP_INDIRECT_BUFFER_PFD, 2); | |
163 | OUT_RING(ring, submit->cmd[i].iova); | |
164 | OUT_RING(ring, submit->cmd[i].size); | |
165 | ibs++; | |
166 | break; | |
167 | } | |
168 | } | |
169 | ||
170 | /* on a320, at least, we seem to need to pad things out to an | |
171 | * even number of qwords to avoid issue w/ CP hanging on wrap- | |
172 | * around: | |
173 | */ | |
174 | if (ibs % 2) | |
175 | OUT_PKT2(ring); | |
176 | ||
177 | OUT_PKT0(ring, REG_AXXX_CP_SCRATCH_REG2, 1); | |
178 | OUT_RING(ring, submit->fence); | |
179 | ||
180 | if (adreno_is_a3xx(adreno_gpu)) { | |
181 | /* Flush HLSQ lazy updates to make sure there is nothing | |
182 | * pending for indirect loads after the timestamp has | |
183 | * passed: | |
184 | */ | |
185 | OUT_PKT3(ring, CP_EVENT_WRITE, 1); | |
186 | OUT_RING(ring, HLSQ_FLUSH); | |
187 | ||
188 | OUT_PKT3(ring, CP_WAIT_FOR_IDLE, 1); | |
189 | OUT_RING(ring, 0x00000000); | |
190 | } | |
191 | ||
192 | OUT_PKT3(ring, CP_EVENT_WRITE, 3); | |
193 | OUT_RING(ring, CACHE_FLUSH_TS); | |
194 | OUT_RING(ring, rbmemptr(adreno_gpu, fence)); | |
195 | OUT_RING(ring, submit->fence); | |
196 | ||
197 | /* we could maybe be clever and only CP_COND_EXEC the interrupt: */ | |
198 | OUT_PKT3(ring, CP_INTERRUPT, 1); | |
199 | OUT_RING(ring, 0x80000000); | |
200 | ||
201 | #if 0 | |
202 | if (adreno_is_a3xx(adreno_gpu)) { | |
203 | /* Dummy set-constant to trigger context rollover */ | |
204 | OUT_PKT3(ring, CP_SET_CONSTANT, 2); | |
205 | OUT_RING(ring, CP_REG(REG_A3XX_HLSQ_CL_KERNEL_GROUP_X_REG)); | |
206 | OUT_RING(ring, 0x00000000); | |
207 | } | |
208 | #endif | |
209 | ||
210 | gpu->funcs->flush(gpu); | |
211 | ||
212 | return 0; | |
213 | } | |
214 | ||
215 | void adreno_flush(struct msm_gpu *gpu) | |
216 | { | |
217 | uint32_t wptr = get_wptr(gpu->rb); | |
218 | ||
219 | /* ensure writes to ringbuffer have hit system memory: */ | |
220 | mb(); | |
221 | ||
222 | gpu_write(gpu, REG_AXXX_CP_RB_WPTR, wptr); | |
223 | } | |
224 | ||
225 | void adreno_idle(struct msm_gpu *gpu) | |
226 | { | |
227 | struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); | |
0963756f | 228 | uint32_t wptr = get_wptr(gpu->rb); |
7198e6b0 | 229 | |
0963756f RC |
230 | /* wait for CP to drain ringbuffer: */ |
231 | if (spin_until(adreno_gpu->memptrs->rptr == wptr)) | |
232 | DRM_ERROR("%s: timeout waiting to drain ringbuffer!\n", gpu->name); | |
7198e6b0 RC |
233 | |
234 | /* TODO maybe we need to reset GPU here to recover from hang? */ | |
235 | } | |
236 | ||
237 | #ifdef CONFIG_DEBUG_FS | |
238 | void adreno_show(struct msm_gpu *gpu, struct seq_file *m) | |
239 | { | |
240 | struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); | |
241 | ||
242 | seq_printf(m, "revision: %d (%d.%d.%d.%d)\n", | |
243 | adreno_gpu->info->revn, adreno_gpu->rev.core, | |
244 | adreno_gpu->rev.major, adreno_gpu->rev.minor, | |
245 | adreno_gpu->rev.patchid); | |
246 | ||
247 | seq_printf(m, "fence: %d/%d\n", adreno_gpu->memptrs->fence, | |
bd6f82d8 | 248 | gpu->submitted_fence); |
7198e6b0 RC |
249 | seq_printf(m, "rptr: %d\n", adreno_gpu->memptrs->rptr); |
250 | seq_printf(m, "wptr: %d\n", adreno_gpu->memptrs->wptr); | |
251 | seq_printf(m, "rb wptr: %d\n", get_wptr(gpu->rb)); | |
252 | } | |
253 | #endif | |
254 | ||
5b6ef08e RC |
255 | /* would be nice to not have to duplicate the _show() stuff with printk(): */ |
256 | void adreno_dump(struct msm_gpu *gpu) | |
257 | { | |
258 | struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); | |
259 | ||
260 | printk("revision: %d (%d.%d.%d.%d)\n", | |
261 | adreno_gpu->info->revn, adreno_gpu->rev.core, | |
262 | adreno_gpu->rev.major, adreno_gpu->rev.minor, | |
263 | adreno_gpu->rev.patchid); | |
264 | ||
265 | printk("fence: %d/%d\n", adreno_gpu->memptrs->fence, | |
266 | gpu->submitted_fence); | |
267 | printk("rptr: %d\n", adreno_gpu->memptrs->rptr); | |
268 | printk("wptr: %d\n", adreno_gpu->memptrs->wptr); | |
269 | printk("rb wptr: %d\n", get_wptr(gpu->rb)); | |
270 | ||
271 | } | |
272 | ||
0963756f | 273 | static uint32_t ring_freewords(struct msm_gpu *gpu) |
7198e6b0 RC |
274 | { |
275 | struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); | |
0963756f RC |
276 | uint32_t size = gpu->rb->size / 4; |
277 | uint32_t wptr = get_wptr(gpu->rb); | |
278 | uint32_t rptr = adreno_gpu->memptrs->rptr; | |
279 | return (rptr + (size - 1) - wptr) % size; | |
280 | } | |
281 | ||
282 | void adreno_wait_ring(struct msm_gpu *gpu, uint32_t ndwords) | |
283 | { | |
284 | if (spin_until(ring_freewords(gpu) >= ndwords)) | |
285 | DRM_ERROR("%s: timeout waiting for ringbuffer space\n", gpu->name); | |
7198e6b0 RC |
286 | } |
287 | ||
288 | static const char *iommu_ports[] = { | |
289 | "gfx3d_user", "gfx3d_priv", | |
290 | "gfx3d1_user", "gfx3d1_priv", | |
291 | }; | |
292 | ||
293 | static inline bool _rev_match(uint8_t entry, uint8_t id) | |
294 | { | |
295 | return (entry == ANY_ID) || (entry == id); | |
296 | } | |
297 | ||
298 | int adreno_gpu_init(struct drm_device *drm, struct platform_device *pdev, | |
299 | struct adreno_gpu *gpu, const struct adreno_gpu_funcs *funcs, | |
300 | struct adreno_rev rev) | |
301 | { | |
871d812a | 302 | struct msm_mmu *mmu; |
7198e6b0 RC |
303 | int i, ret; |
304 | ||
305 | /* identify gpu: */ | |
306 | for (i = 0; i < ARRAY_SIZE(gpulist); i++) { | |
307 | const struct adreno_info *info = &gpulist[i]; | |
308 | if (_rev_match(info->rev.core, rev.core) && | |
309 | _rev_match(info->rev.major, rev.major) && | |
310 | _rev_match(info->rev.minor, rev.minor) && | |
311 | _rev_match(info->rev.patchid, rev.patchid)) { | |
312 | gpu->info = info; | |
313 | gpu->revn = info->revn; | |
314 | break; | |
315 | } | |
316 | } | |
317 | ||
318 | if (i == ARRAY_SIZE(gpulist)) { | |
319 | dev_err(drm->dev, "Unknown GPU revision: %u.%u.%u.%u\n", | |
320 | rev.core, rev.major, rev.minor, rev.patchid); | |
321 | return -ENXIO; | |
322 | } | |
323 | ||
324 | DBG("Found GPU: %s (%u.%u.%u.%u)", gpu->info->name, | |
325 | rev.core, rev.major, rev.minor, rev.patchid); | |
326 | ||
327 | gpu->funcs = funcs; | |
55459968 | 328 | gpu->gmem = gpu->info->gmem; |
7198e6b0 RC |
329 | gpu->rev = rev; |
330 | ||
331 | ret = request_firmware(&gpu->pm4, gpu->info->pm4fw, drm->dev); | |
332 | if (ret) { | |
333 | dev_err(drm->dev, "failed to load %s PM4 firmware: %d\n", | |
334 | gpu->info->pm4fw, ret); | |
335 | return ret; | |
336 | } | |
337 | ||
338 | ret = request_firmware(&gpu->pfp, gpu->info->pfpfw, drm->dev); | |
339 | if (ret) { | |
340 | dev_err(drm->dev, "failed to load %s PFP firmware: %d\n", | |
341 | gpu->info->pfpfw, ret); | |
342 | return ret; | |
343 | } | |
344 | ||
345 | ret = msm_gpu_init(drm, pdev, &gpu->base, &funcs->base, | |
346 | gpu->info->name, "kgsl_3d0_reg_memory", "kgsl_3d0_irq", | |
347 | RB_SIZE); | |
348 | if (ret) | |
349 | return ret; | |
350 | ||
871d812a RC |
351 | mmu = gpu->base.mmu; |
352 | if (mmu) { | |
353 | ret = mmu->funcs->attach(mmu, iommu_ports, | |
354 | ARRAY_SIZE(iommu_ports)); | |
355 | if (ret) | |
356 | return ret; | |
357 | } | |
7198e6b0 RC |
358 | |
359 | gpu->memptrs_bo = msm_gem_new(drm, sizeof(*gpu->memptrs), | |
360 | MSM_BO_UNCACHED); | |
361 | if (IS_ERR(gpu->memptrs_bo)) { | |
362 | ret = PTR_ERR(gpu->memptrs_bo); | |
363 | gpu->memptrs_bo = NULL; | |
364 | dev_err(drm->dev, "could not allocate memptrs: %d\n", ret); | |
365 | return ret; | |
366 | } | |
367 | ||
368 | gpu->memptrs = msm_gem_vaddr_locked(gpu->memptrs_bo); | |
369 | if (!gpu->memptrs) { | |
370 | dev_err(drm->dev, "could not vmap memptrs\n"); | |
371 | return -ENOMEM; | |
372 | } | |
373 | ||
374 | ret = msm_gem_get_iova_locked(gpu->memptrs_bo, gpu->base.id, | |
375 | &gpu->memptrs_iova); | |
376 | if (ret) { | |
377 | dev_err(drm->dev, "could not map memptrs: %d\n", ret); | |
378 | return ret; | |
379 | } | |
380 | ||
381 | return 0; | |
382 | } | |
383 | ||
384 | void adreno_gpu_cleanup(struct adreno_gpu *gpu) | |
385 | { | |
386 | if (gpu->memptrs_bo) { | |
387 | if (gpu->memptrs_iova) | |
388 | msm_gem_put_iova(gpu->memptrs_bo, gpu->base.id); | |
389 | drm_gem_object_unreference(gpu->memptrs_bo); | |
390 | } | |
391 | if (gpu->pm4) | |
392 | release_firmware(gpu->pm4); | |
393 | if (gpu->pfp) | |
394 | release_firmware(gpu->pfp); | |
395 | msm_gpu_cleanup(&gpu->base); | |
396 | } |