]> git.proxmox.com Git - mirror_ubuntu-bionic-kernel.git/blame - drivers/gpu/drm/msm/mdp/mdp5/mdp5_plane.c
projects / mirror_ubuntu-bionic-kernel.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
drm: Nuke drm_atomic_helper_plane_set_property
[mirror_ubuntu-bionic-kernel.git] / drivers / gpu / drm / msm / mdp / mdp5 / mdp5_plane.c
CommitLineData
06c0dd96 1/*
bef799fb 2 * Copyright (C) 2014-2015 The Linux Foundation. All rights reserved.
06c0dd96
RC		 3 * Copyright (C) 2013 Red Hat
4 * Author: Rob Clark <robdclark@gmail.com>
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 as published by
8 * the Free Software Foundation.
9 *
10 * This program is distributed in the hope that it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * more details.
14 *
15 * You should have received a copy of the GNU General Public License along with
16 * this program. If not, see <http://www.gnu.org/licenses/>.
17 */
18
dd701ae9 19#include <drm/drm_print.h>
06c0dd96
RC		 20#include "mdp5_kms.h"
21
06c0dd96
RC		 22struct mdp5_plane {
23 struct drm_plane base;
06c0dd96 24
06c0dd96
RC		 25 uint32_t nformats;
26 uint32_t formats[32];
06c0dd96
RC		 27};
28#define to_mdp5_plane(x) container_of(x, struct mdp5_plane, base)
29
ed851963
RC		 30static int mdp5_plane_mode_set(struct drm_plane *plane,
31 struct drm_crtc *crtc, struct drm_framebuffer *fb,
3b6acf14 32 struct drm_rect *src, struct drm_rect *dest);
bef799fb 33
10967a06
AT		 34static int mdp5_update_cursor_plane_legacy(struct drm_plane *plane,
35 struct drm_crtc *crtc,
36 struct drm_framebuffer *fb,
37 int crtc_x, int crtc_y,
38 unsigned int crtc_w, unsigned int crtc_h,
39 uint32_t src_x, uint32_t src_y,
34a2ab5e
DV		 40 uint32_t src_w, uint32_t src_h,
41 struct drm_modeset_acquire_ctx *ctx);
10967a06 42
06c0dd96
RC		 43static struct mdp5_kms *get_kms(struct drm_plane *plane)
44{
45 struct msm_drm_private *priv = plane->dev->dev_private;
46 return to_mdp5_kms(to_mdp_kms(priv->kms));
47}
48
ed851963 49static bool plane_enabled(struct drm_plane_state *state)
06c0dd96 50{
3b6acf14 51 return state->visible;
06c0dd96
RC		 52}
53
06c0dd96
RC		 54static void mdp5_plane_destroy(struct drm_plane *plane)
55{
56 struct mdp5_plane *mdp5_plane = to_mdp5_plane(plane);
57
ed851963 58 drm_plane_helper_disable(plane);
06c0dd96
RC		 59 drm_plane_cleanup(plane);
60
61 kfree(mdp5_plane);
62}
63
8089082f 64static void mdp5_plane_install_rotation_property(struct drm_device *dev,
65 struct drm_plane *plane)
66{
5b560c3a 67 drm_plane_create_rotation_property(plane,
c2c446ad
RF		 68 DRM_MODE_ROTATE_0,
69 DRM_MODE_ROTATE_0 |
70 DRM_MODE_ROTATE_180 |
71 DRM_MODE_REFLECT_X |
72 DRM_MODE_REFLECT_Y);
8089082f 73}
74
06c0dd96 75/* helper to install properties which are common to planes and crtcs */
4ff696ea 76static void mdp5_plane_install_properties(struct drm_plane *plane,
06c0dd96
RC		 77 struct drm_mode_object *obj)
78{
12987781 79 struct drm_device *dev = plane->dev;
80 struct msm_drm_private *dev_priv = dev->dev_private;
81 struct drm_property *prop;
82
83#define INSTALL_PROPERTY(name, NAME, init_val, fnc, ...) do { \
84 prop = dev_priv->plane_property[PLANE_PROP_##NAME]; \
85 if (!prop) { \
86 prop = drm_property_##fnc(dev, 0, #name, \
87 ##__VA_ARGS__); \
88 if (!prop) { \
89 dev_warn(dev->dev, \
90 "Create property %s failed\n", \
91 #name); \
92 return; \
93 } \
94 dev_priv->plane_property[PLANE_PROP_##NAME] = prop; \
95 } \
96 drm_object_attach_property(&plane->base, prop, init_val); \
97 } while (0)
98
99#define INSTALL_RANGE_PROPERTY(name, NAME, min, max, init_val) \
100 INSTALL_PROPERTY(name, NAME, init_val, \
101 create_range, min, max)
102
103#define INSTALL_ENUM_PROPERTY(name, NAME, init_val) \
104 INSTALL_PROPERTY(name, NAME, init_val, \
105 create_enum, name##_prop_enum_list, \
106 ARRAY_SIZE(name##_prop_enum_list))
107
108 INSTALL_RANGE_PROPERTY(zpos, ZPOS, 1, 255, 1);
109
8089082f 110 mdp5_plane_install_rotation_property(dev, plane);
111
12987781 112#undef INSTALL_RANGE_PROPERTY
113#undef INSTALL_ENUM_PROPERTY
114#undef INSTALL_PROPERTY
06c0dd96
RC		 115}
116
12987781 117static int mdp5_plane_atomic_set_property(struct drm_plane *plane,
118 struct drm_plane_state *state, struct drm_property *property,
119 uint64_t val)
120{
121 struct drm_device *dev = plane->dev;
122 struct mdp5_plane_state *pstate;
123 struct msm_drm_private *dev_priv = dev->dev_private;
124 int ret = 0;
125
126 pstate = to_mdp5_plane_state(state);
127
128#define SET_PROPERTY(name, NAME, type) do { \
129 if (dev_priv->plane_property[PLANE_PROP_##NAME] == property) { \
130 pstate->name = (type)val; \
131 DBG("Set property %s %d", #name, (type)val); \
132 goto done; \
133 } \
134 } while (0)
135
136 SET_PROPERTY(zpos, ZPOS, uint8_t);
137
138 dev_err(dev->dev, "Invalid property\n");
139 ret = -EINVAL;
140done:
141 return ret;
142#undef SET_PROPERTY
143}
144
12987781 145static int mdp5_plane_atomic_get_property(struct drm_plane *plane,
146 const struct drm_plane_state *state,
147 struct drm_property *property, uint64_t *val)
148{
149 struct drm_device *dev = plane->dev;
150 struct mdp5_plane_state *pstate;
151 struct msm_drm_private *dev_priv = dev->dev_private;
152 int ret = 0;
153
154 pstate = to_mdp5_plane_state(state);
155
156#define GET_PROPERTY(name, NAME, type) do { \
157 if (dev_priv->plane_property[PLANE_PROP_##NAME] == property) { \
158 *val = pstate->name; \
159 DBG("Get property %s %lld", #name, *val); \
160 goto done; \
161 } \
162 } while (0)
163
164 GET_PROPERTY(zpos, ZPOS, uint8_t);
165
166 dev_err(dev->dev, "Invalid property\n");
167 ret = -EINVAL;
168done:
169 return ret;
170#undef SET_PROPERTY
06c0dd96
RC		 171}
172
dd701ae9
RC		 173static void
174mdp5_plane_atomic_print_state(struct drm_printer *p,
175 const struct drm_plane_state *state)
176{
177 struct mdp5_plane_state *pstate = to_mdp5_plane_state(state);
7a10ee9b 178 struct mdp5_kms *mdp5_kms = get_kms(state->plane);
dd701ae9 179
4a0f012d
RC		 180 drm_printf(p, "\thwpipe=%s\n", pstate->hwpipe ?
181 pstate->hwpipe->name : "(null)");
7a10ee9b
AT		 182 if (mdp5_kms->caps & MDP_CAP_SRC_SPLIT)
183 drm_printf(p, "\tright-hwpipe=%s\n",
184 pstate->r_hwpipe ? pstate->r_hwpipe->name :
185 "(null)");
dd701ae9
RC		 186 drm_printf(p, "\tpremultiplied=%u\n", pstate->premultiplied);
187 drm_printf(p, "\tzpos=%u\n", pstate->zpos);
188 drm_printf(p, "\talpha=%u\n", pstate->alpha);
189 drm_printf(p, "\tstage=%s\n", stage2name(pstate->stage));
dd701ae9
RC		 190}
191
ed851963
RC		 192static void mdp5_plane_reset(struct drm_plane *plane)
193{
194 struct mdp5_plane_state *mdp5_state;
195
196 if (plane->state && plane->state->fb)
197 drm_framebuffer_unreference(plane->state->fb);
198
199 kfree(to_mdp5_plane_state(plane->state));
200 mdp5_state = kzalloc(sizeof(*mdp5_state), GFP_KERNEL);
201
12987781 202 /* assign default blend parameters */
203 mdp5_state->alpha = 255;
204 mdp5_state->premultiplied = 0;
205
206 if (plane->type == DRM_PLANE_TYPE_PRIMARY)
207 mdp5_state->zpos = STAGE_BASE;
208 else
209 mdp5_state->zpos = STAGE0 + drm_plane_index(plane);
210
07cc0ef6 211 mdp5_state->base.plane = plane;
ed851963
RC		 212
213 plane->state = &mdp5_state->base;
214}
215
216static struct drm_plane_state *
217mdp5_plane_duplicate_state(struct drm_plane *plane)
218{
219 struct mdp5_plane_state *mdp5_state;
220
221 if (WARN_ON(!plane->state))
222 return NULL;
223
224 mdp5_state = kmemdup(to_mdp5_plane_state(plane->state),
225 sizeof(*mdp5_state), GFP_KERNEL);
786813c3
RC		 226 if (!mdp5_state)
227 return NULL;
ed851963 228
786813c3 229 __drm_atomic_helper_plane_duplicate_state(plane, &mdp5_state->base);
ed851963 230
ed851963
RC		 231 return &mdp5_state->base;
232}
233
234static void mdp5_plane_destroy_state(struct drm_plane *plane,
235 struct drm_plane_state *state)
236{
4a0f012d
RC		 237 struct mdp5_plane_state *pstate = to_mdp5_plane_state(state);
238
ed851963
RC		 239 if (state->fb)
240 drm_framebuffer_unreference(state->fb);
241
4a0f012d 242 kfree(pstate);
ed851963
RC		 243}
244
06c0dd96 245static const struct drm_plane_funcs mdp5_plane_funcs = {
ed851963
RC		 246 .update_plane = drm_atomic_helper_update_plane,
247 .disable_plane = drm_atomic_helper_disable_plane,
06c0dd96 248 .destroy = mdp5_plane_destroy,
12987781 249 .atomic_set_property = mdp5_plane_atomic_set_property,
250 .atomic_get_property = mdp5_plane_atomic_get_property,
ed851963
RC		 251 .reset = mdp5_plane_reset,
252 .atomic_duplicate_state = mdp5_plane_duplicate_state,
253 .atomic_destroy_state = mdp5_plane_destroy_state,
dd701ae9 254 .atomic_print_state = mdp5_plane_atomic_print_state,
06c0dd96
RC		 255};
256
10967a06
AT		 257static const struct drm_plane_funcs mdp5_cursor_plane_funcs = {
258 .update_plane = mdp5_update_cursor_plane_legacy,
259 .disable_plane = drm_atomic_helper_disable_plane,
260 .destroy = mdp5_plane_destroy,
10967a06
AT		 261 .atomic_set_property = mdp5_plane_atomic_set_property,
262 .atomic_get_property = mdp5_plane_atomic_get_property,
263 .reset = mdp5_plane_reset,
264 .atomic_duplicate_state = mdp5_plane_duplicate_state,
265 .atomic_destroy_state = mdp5_plane_destroy_state,
266 .atomic_print_state = mdp5_plane_atomic_print_state,
267};
268
ed851963 269static int mdp5_plane_prepare_fb(struct drm_plane *plane,
1832040d 270 struct drm_plane_state *new_state)
06c0dd96 271{
06c0dd96 272 struct mdp5_kms *mdp5_kms = get_kms(plane);
f59f62d5 273 struct msm_kms *kms = &mdp5_kms->base.base;
844f9111
ML		 274 struct drm_framebuffer *fb = new_state->fb;
275
276 if (!new_state->fb)
277 return 0;
06c0dd96 278
0002d30f 279 DBG("%s: prepare: FB[%u]", plane->name, fb->base.id);
8bdcd949 280 return msm_framebuffer_prepare(fb, kms->aspace);
0deed25b
SV		 281}
282
ed851963 283static void mdp5_plane_cleanup_fb(struct drm_plane *plane,
1832040d 284 struct drm_plane_state *old_state)
0deed25b 285{
0deed25b 286 struct mdp5_kms *mdp5_kms = get_kms(plane);
f59f62d5 287 struct msm_kms *kms = &mdp5_kms->base.base;
844f9111
ML		 288 struct drm_framebuffer *fb = old_state->fb;
289
290 if (!fb)
291 return;
0deed25b 292
0002d30f 293 DBG("%s: cleanup: FB[%u]", plane->name, fb->base.id);
8bdcd949 294 msm_framebuffer_cleanup(fb, kms->aspace);
ed851963 295}
0deed25b 296
3b6acf14 297#define FRAC_16_16(mult, div) (((mult) << 16) / (div))
9142364e
AT		 298static int mdp5_plane_atomic_check_with_state(struct drm_crtc_state *crtc_state,
299 struct drm_plane_state *state)
ed851963 300{
4a0f012d 301 struct mdp5_plane_state *mdp5_state = to_mdp5_plane_state(state);
9142364e 302 struct drm_plane *plane = state->plane;
ed851963 303 struct drm_plane_state *old_state = plane->state;
9708ebbe 304 struct mdp5_cfg *config = mdp5_cfg_get_config(get_kms(plane)->cfg);
4a0f012d 305 bool new_hwpipe = false;
7a10ee9b 306 bool need_right_hwpipe = false;
9708ebbe 307 uint32_t max_width, max_height;
7a10ee9b 308 bool out_of_bounds = false;
4a0f012d 309 uint32_t caps = 0;
3b6acf14
AT		 310 struct drm_rect clip;
311 int min_scale, max_scale;
312 int ret;
ed851963 313
0002d30f 314 DBG("%s: check (%d -> %d)", plane->name,
ed851963
RC		 315 plane_enabled(old_state), plane_enabled(state));
316
9708ebbe
RC		 317 max_width = config->hw->lm.max_width << 16;
318 max_height = config->hw->lm.max_height << 16;
319
320 /* Make sure source dimensions are within bounds. */
7a10ee9b
AT		 321 if (state->src_h > max_height)
322 out_of_bounds = true;
323
324 if (state->src_w > max_width) {
325 /* If source split is supported, we can go up to 2x
326 * the max LM width, but we'd need to stage another
327 * hwpipe to the right LM. So, the drm_plane would
328 * consist of 2 hwpipes.
329 */
330 if (config->hw->mdp.caps & MDP_CAP_SRC_SPLIT &&
331 (state->src_w <= 2 * max_width))
332 need_right_hwpipe = true;
333 else
334 out_of_bounds = true;
335 }
336
337 if (out_of_bounds) {
9708ebbe
RC		 338 struct drm_rect src = drm_plane_state_src(state);
339 DBG("Invalid source size "DRM_RECT_FP_FMT,
340 DRM_RECT_FP_ARG(&src));
341 return -ERANGE;
342 }
343
3b6acf14
AT		 344 clip.x1 = 0;
345 clip.y1 = 0;
346 clip.x2 = crtc_state->adjusted_mode.hdisplay;
347 clip.y2 = crtc_state->adjusted_mode.vdisplay;
348 min_scale = FRAC_16_16(1, 8);
349 max_scale = FRAC_16_16(8, 1);
350
351 ret = drm_plane_helper_check_state(state, &clip, min_scale,
352 max_scale, true, true);
353 if (ret)
354 return ret;
355
3498409f 356 if (plane_enabled(state)) {
574a37b1 357 unsigned int rotation;
4a0f012d 358 const struct mdp_format *format;
49ec5b2e
RC		 359 struct mdp5_kms *mdp5_kms = get_kms(plane);
360 uint32_t blkcfg = 0;
574a37b1 361
3498409f 362 format = to_mdp_format(msm_framebuffer_format(state->fb));
4a0f012d
RC		 363 if (MDP_FORMAT_IS_YUV(format))
364 caps |= MDP_PIPE_CAP_SCALE | MDP_PIPE_CAP_CSC;
3498409f 365
4a0f012d
RC		 366 if (((state->src_w >> 16) != state->crtc_w) ||
367 ((state->src_h >> 16) != state->crtc_h))
368 caps |= MDP_PIPE_CAP_SCALE;
8089082f 369
574a37b1 370 rotation = drm_rotation_simplify(state->rotation,
c2c446ad
RF		 371 DRM_MODE_ROTATE_0 |
372 DRM_MODE_REFLECT_X |
373 DRM_MODE_REFLECT_Y);
c056b55d 374
c2c446ad 375 if (rotation & DRM_MODE_REFLECT_X)
4a0f012d
RC		 376 caps |= MDP_PIPE_CAP_HFLIP;
377
c2c446ad 378 if (rotation & DRM_MODE_REFLECT_Y)
4a0f012d
RC		 379 caps |= MDP_PIPE_CAP_VFLIP;
380
5798c8e0
AT		 381 if (plane->type == DRM_PLANE_TYPE_CURSOR)
382 caps |= MDP_PIPE_CAP_CURSOR;
383
4a0f012d
RC		 384 /* (re)allocate hw pipe if we don't have one or caps-mismatch: */
385 if (!mdp5_state->hwpipe || (caps & ~mdp5_state->hwpipe->caps))
386 new_hwpipe = true;
387
7a10ee9b
AT		 388 /*
389 * (re)allocte hw pipe if we're either requesting for 2 hw pipes
390 * or we're switching from 2 hw pipes to 1 hw pipe because the
391 * new src_w can be supported by 1 hw pipe itself.
392 */
393 if ((need_right_hwpipe && !mdp5_state->r_hwpipe) ||
394 (!need_right_hwpipe && mdp5_state->r_hwpipe))
395 new_hwpipe = true;
396
49ec5b2e
RC		 397 if (mdp5_kms->smp) {
398 const struct mdp_format *format =
399 to_mdp_format(msm_framebuffer_format(state->fb));
400
401 blkcfg = mdp5_smp_calculate(mdp5_kms->smp, format,
402 state->src_w >> 16, false);
403
404 if (mdp5_state->hwpipe && (mdp5_state->hwpipe->blkcfg != blkcfg))
405 new_hwpipe = true;
8089082f 406 }
3498409f 407
4a0f012d
RC		 408 /* (re)assign hwpipe if needed, otherwise keep old one: */
409 if (new_hwpipe) {
410 /* TODO maybe we want to re-assign hwpipe sometimes
411 * in cases when we no-longer need some caps to make
412 * it available for other planes?
413 */
414 struct mdp5_hw_pipe *old_hwpipe = mdp5_state->hwpipe;
7a10ee9b
AT		 415 struct mdp5_hw_pipe *old_right_hwpipe =
416 mdp5_state->r_hwpipe;
417
49ec5b2e
RC		 418 mdp5_state->hwpipe = mdp5_pipe_assign(state->state,
419 plane, caps, blkcfg);
4a0f012d
RC		 420 if (IS_ERR(mdp5_state->hwpipe)) {
421 DBG("%s: failed to assign hwpipe!", plane->name);
422 return PTR_ERR(mdp5_state->hwpipe);
423 }
7a10ee9b
AT		 424
425 if (need_right_hwpipe) {
426 mdp5_state->r_hwpipe =
427 mdp5_pipe_assign(state->state, plane,
428 caps, blkcfg);
429 if (IS_ERR(mdp5_state->r_hwpipe)) {
430 DBG("%s: failed to assign right hwpipe",
431 plane->name);
432 return PTR_ERR(mdp5_state->r_hwpipe);
433 }
434 } else {
435 /*
436 * set it to NULL so that the driver knows we
437 * don't have a right hwpipe when committing a
438 * new state
439 */
440 mdp5_state->r_hwpipe = NULL;
441 }
442
4a0f012d 443 mdp5_pipe_release(state->state, old_hwpipe);
7a10ee9b 444 mdp5_pipe_release(state->state, old_right_hwpipe);
ed851963 445 }
adcbae31
RC		 446 } else {
447 mdp5_pipe_release(state->state, mdp5_state->hwpipe);
448 mdp5_pipe_release(state->state, mdp5_state->r_hwpipe);
449 mdp5_state->hwpipe = mdp5_state->r_hwpipe = NULL;
ed851963 450 }
06c0dd96 451
ed851963
RC		 452 return 0;
453}
454
9142364e
AT		 455static int mdp5_plane_atomic_check(struct drm_plane *plane,
456 struct drm_plane_state *state)
457{
458 struct drm_crtc *crtc;
459 struct drm_crtc_state *crtc_state;
460
461 crtc = state->crtc ? state->crtc : plane->state->crtc;
462 if (!crtc)
463 return 0;
464
465 crtc_state = drm_atomic_get_existing_crtc_state(state->state, crtc);
466 if (WARN_ON(!crtc_state))
467 return -EINVAL;
468
469 return mdp5_plane_atomic_check_with_state(crtc_state, state);
470}
471
f1c37e1a
TR		 472static void mdp5_plane_atomic_update(struct drm_plane *plane,
473 struct drm_plane_state *old_state)
ed851963 474{
ed851963
RC		 475 struct drm_plane_state *state = plane->state;
476
0002d30f 477 DBG("%s: update", plane->name);
0deed25b 478
f5903bad 479 if (plane_enabled(state)) {
ed851963 480 int ret;
f5903bad 481
ed851963
RC		 482 ret = mdp5_plane_mode_set(plane,
483 state->crtc, state->fb,
3b6acf14 484 &state->src, &state->dst);
ed851963
RC		 485 /* atomic_check should have ensured that this doesn't fail */
486 WARN_ON(ret < 0);
ed851963 487 }
0deed25b
SV		 488}
489
ed851963
RC		 490static const struct drm_plane_helper_funcs mdp5_plane_helper_funcs = {
491 .prepare_fb = mdp5_plane_prepare_fb,
492 .cleanup_fb = mdp5_plane_cleanup_fb,
493 .atomic_check = mdp5_plane_atomic_check,
494 .atomic_update = mdp5_plane_atomic_update,
495};
496
821be43f
AT		 497static void set_scanout_locked(struct mdp5_kms *mdp5_kms,
498 enum mdp5_pipe pipe,
499 struct drm_framebuffer *fb)
0deed25b 500{
f59f62d5
RC		 501 struct msm_kms *kms = &mdp5_kms->base.base;
502
ed851963
RC		 503 mdp5_write(mdp5_kms, REG_MDP5_PIPE_SRC_STRIDE_A(pipe),
504 MDP5_PIPE_SRC_STRIDE_A_P0(fb->pitches[0]) |
505 MDP5_PIPE_SRC_STRIDE_A_P1(fb->pitches[1]));
0deed25b 506
ed851963
RC		 507 mdp5_write(mdp5_kms, REG_MDP5_PIPE_SRC_STRIDE_B(pipe),
508 MDP5_PIPE_SRC_STRIDE_B_P2(fb->pitches[2]) |
509 MDP5_PIPE_SRC_STRIDE_B_P3(fb->pitches[3]));
510
511 mdp5_write(mdp5_kms, REG_MDP5_PIPE_SRC0_ADDR(pipe),
8bdcd949 512 msm_framebuffer_iova(fb, kms->aspace, 0));
ed851963 513 mdp5_write(mdp5_kms, REG_MDP5_PIPE_SRC1_ADDR(pipe),
8bdcd949 514 msm_framebuffer_iova(fb, kms->aspace, 1));
ed851963 515 mdp5_write(mdp5_kms, REG_MDP5_PIPE_SRC2_ADDR(pipe),
8bdcd949 516 msm_framebuffer_iova(fb, kms->aspace, 2));
ed851963 517 mdp5_write(mdp5_kms, REG_MDP5_PIPE_SRC3_ADDR(pipe),
8bdcd949 518 msm_framebuffer_iova(fb, kms->aspace, 3));
06c0dd96
RC		 519}
520
f8d9b515
SV		 521/* Note: mdp5_plane->pipe_lock must be locked */
522static void csc_disable(struct mdp5_kms *mdp5_kms, enum mdp5_pipe pipe)
523{
524 uint32_t value = mdp5_read(mdp5_kms, REG_MDP5_PIPE_OP_MODE(pipe)) &
525 ~MDP5_PIPE_OP_MODE_CSC_1_EN;
526
527 mdp5_write(mdp5_kms, REG_MDP5_PIPE_OP_MODE(pipe), value);
528}
529
530/* Note: mdp5_plane->pipe_lock must be locked */
531static void csc_enable(struct mdp5_kms *mdp5_kms, enum mdp5_pipe pipe,
532 struct csc_cfg *csc)
533{
534 uint32_t i, mode = 0; /* RGB, no CSC */
535 uint32_t *matrix;
536
537 if (unlikely(!csc))
538 return;
539
540 if ((csc->type == CSC_YUV2RGB) || (CSC_YUV2YUV == csc->type))
541 mode |= MDP5_PIPE_OP_MODE_CSC_SRC_DATA_FORMAT(DATA_FORMAT_YUV);
542 if ((csc->type == CSC_RGB2YUV) || (CSC_YUV2YUV == csc->type))
543 mode |= MDP5_PIPE_OP_MODE_CSC_DST_DATA_FORMAT(DATA_FORMAT_YUV);
544 mode |= MDP5_PIPE_OP_MODE_CSC_1_EN;
545 mdp5_write(mdp5_kms, REG_MDP5_PIPE_OP_MODE(pipe), mode);
546
547 matrix = csc->matrix;
548 mdp5_write(mdp5_kms, REG_MDP5_PIPE_CSC_1_MATRIX_COEFF_0(pipe),
549 MDP5_PIPE_CSC_1_MATRIX_COEFF_0_COEFF_11(matrix[0]) |
550 MDP5_PIPE_CSC_1_MATRIX_COEFF_0_COEFF_12(matrix[1]));
551 mdp5_write(mdp5_kms, REG_MDP5_PIPE_CSC_1_MATRIX_COEFF_1(pipe),
552 MDP5_PIPE_CSC_1_MATRIX_COEFF_1_COEFF_13(matrix[2]) |
553 MDP5_PIPE_CSC_1_MATRIX_COEFF_1_COEFF_21(matrix[3]));
554 mdp5_write(mdp5_kms, REG_MDP5_PIPE_CSC_1_MATRIX_COEFF_2(pipe),
555 MDP5_PIPE_CSC_1_MATRIX_COEFF_2_COEFF_22(matrix[4]) |
556 MDP5_PIPE_CSC_1_MATRIX_COEFF_2_COEFF_23(matrix[5]));
557 mdp5_write(mdp5_kms, REG_MDP5_PIPE_CSC_1_MATRIX_COEFF_3(pipe),
558 MDP5_PIPE_CSC_1_MATRIX_COEFF_3_COEFF_31(matrix[6]) |
559 MDP5_PIPE_CSC_1_MATRIX_COEFF_3_COEFF_32(matrix[7]));
560 mdp5_write(mdp5_kms, REG_MDP5_PIPE_CSC_1_MATRIX_COEFF_4(pipe),
561 MDP5_PIPE_CSC_1_MATRIX_COEFF_4_COEFF_33(matrix[8]));
562
563 for (i = 0; i < ARRAY_SIZE(csc->pre_bias); i++) {
564 uint32_t *pre_clamp = csc->pre_clamp;
565 uint32_t *post_clamp = csc->post_clamp;
566
567 mdp5_write(mdp5_kms, REG_MDP5_PIPE_CSC_1_PRE_CLAMP(pipe, i),
568 MDP5_PIPE_CSC_1_PRE_CLAMP_REG_HIGH(pre_clamp[2*i+1]) |
569 MDP5_PIPE_CSC_1_PRE_CLAMP_REG_LOW(pre_clamp[2*i]));
570
571 mdp5_write(mdp5_kms, REG_MDP5_PIPE_CSC_1_POST_CLAMP(pipe, i),
572 MDP5_PIPE_CSC_1_POST_CLAMP_REG_HIGH(post_clamp[2*i+1]) |
573 MDP5_PIPE_CSC_1_POST_CLAMP_REG_LOW(post_clamp[2*i]));
574
575 mdp5_write(mdp5_kms, REG_MDP5_PIPE_CSC_1_PRE_BIAS(pipe, i),
576 MDP5_PIPE_CSC_1_PRE_BIAS_REG_VALUE(csc->pre_bias[i]));
577
578 mdp5_write(mdp5_kms, REG_MDP5_PIPE_CSC_1_POST_BIAS(pipe, i),
579 MDP5_PIPE_CSC_1_POST_BIAS_REG_VALUE(csc->post_bias[i]));
580 }
581}
582
583#define PHASE_STEP_SHIFT 21
584#define DOWN_SCALE_RATIO_MAX 32 /* 2^(26-21) */
585
586static int calc_phase_step(uint32_t src, uint32_t dst, uint32_t *out_phase)
587{
588 uint32_t unit;
589
590 if (src == 0 || dst == 0)
591 return -EINVAL;
592
593 /*
594 * PHASE_STEP_X/Y is coded on 26 bits (25:0),
595 * where 2^21 represents the unity "1" in fixed-point hardware design.
596 * This leaves 5 bits for the integer part (downscale case):
597 * -> maximum downscale ratio = 0b1_1111 = 31
598 */
599 if (src > (dst * DOWN_SCALE_RATIO_MAX))
600 return -EOVERFLOW;
601
602 unit = 1 << PHASE_STEP_SHIFT;
603 *out_phase = mult_frac(unit, src, dst);
604
605 return 0;
606}
607
bef799fb
SV		 608static int calc_scalex_steps(struct drm_plane *plane,
609 uint32_t pixel_format, uint32_t src, uint32_t dest,
95651cd9 610 uint32_t phasex_steps[COMP_MAX])
f8d9b515 611{
bef799fb
SV		 612 struct mdp5_kms *mdp5_kms = get_kms(plane);
613 struct device *dev = mdp5_kms->dev->dev;
f8d9b515
SV		 614 uint32_t phasex_step;
615 unsigned int hsub;
616 int ret;
617
618 ret = calc_phase_step(src, dest, &phasex_step);
bef799fb
SV		 619 if (ret) {
620 dev_err(dev, "X scaling (%d->%d) failed: %d\n", src, dest, ret);
f8d9b515 621 return ret;
bef799fb 622 }
f8d9b515
SV		 623
624 hsub = drm_format_horz_chroma_subsampling(pixel_format);
625
95651cd9
SV		 626 phasex_steps[COMP_0] = phasex_step;
627 phasex_steps[COMP_3] = phasex_step;
628 phasex_steps[COMP_1_2] = phasex_step / hsub;
f8d9b515
SV		 629
630 return 0;
631}
632
bef799fb
SV		 633static int calc_scaley_steps(struct drm_plane *plane,
634 uint32_t pixel_format, uint32_t src, uint32_t dest,
95651cd9 635 uint32_t phasey_steps[COMP_MAX])
f8d9b515 636{
bef799fb
SV		 637 struct mdp5_kms *mdp5_kms = get_kms(plane);
638 struct device *dev = mdp5_kms->dev->dev;
f8d9b515
SV		 639 uint32_t phasey_step;
640 unsigned int vsub;
641 int ret;
642
643 ret = calc_phase_step(src, dest, &phasey_step);
bef799fb
SV		 644 if (ret) {
645 dev_err(dev, "Y scaling (%d->%d) failed: %d\n", src, dest, ret);
f8d9b515 646 return ret;
bef799fb 647 }
f8d9b515
SV		 648
649 vsub = drm_format_vert_chroma_subsampling(pixel_format);
650
95651cd9
SV		 651 phasey_steps[COMP_0] = phasey_step;
652 phasey_steps[COMP_3] = phasey_step;
653 phasey_steps[COMP_1_2] = phasey_step / vsub;
f8d9b515
SV		 654
655 return 0;
656}
657
8e2930c6
SV		 658static uint32_t get_scale_config(const struct mdp_format *format,
659 uint32_t src, uint32_t dst, bool horz)
f8d9b515 660{
8e2930c6
SV		 661 bool scaling = format->is_yuv ? true : (src != dst);
662 uint32_t sub, pix_fmt = format->base.pixel_format;
663 uint32_t ya_filter, uv_filter;
664 bool yuv = format->is_yuv;
665
666 if (!scaling)
667 return 0;
668
669 if (yuv) {
670 sub = horz ? drm_format_horz_chroma_subsampling(pix_fmt) :
671 drm_format_vert_chroma_subsampling(pix_fmt);
672 uv_filter = ((src / sub) <= dst) ?
673 SCALE_FILTER_BIL : SCALE_FILTER_PCMN;
674 }
675 ya_filter = (src <= dst) ? SCALE_FILTER_BIL : SCALE_FILTER_PCMN;
676
677 if (horz)
678 return MDP5_PIPE_SCALE_CONFIG_SCALEX_EN |
679 MDP5_PIPE_SCALE_CONFIG_SCALEX_FILTER_COMP_0(ya_filter) |
680 MDP5_PIPE_SCALE_CONFIG_SCALEX_FILTER_COMP_3(ya_filter) |
681 COND(yuv, MDP5_PIPE_SCALE_CONFIG_SCALEX_FILTER_COMP_1_2(uv_filter));
682 else
683 return MDP5_PIPE_SCALE_CONFIG_SCALEY_EN |
684 MDP5_PIPE_SCALE_CONFIG_SCALEY_FILTER_COMP_0(ya_filter) |
685 MDP5_PIPE_SCALE_CONFIG_SCALEY_FILTER_COMP_3(ya_filter) |
686 COND(yuv, MDP5_PIPE_SCALE_CONFIG_SCALEY_FILTER_COMP_1_2(uv_filter));
687}
688
689static void calc_pixel_ext(const struct mdp_format *format,
690 uint32_t src, uint32_t dst, uint32_t phase_step[2],
691 int pix_ext_edge1[COMP_MAX], int pix_ext_edge2[COMP_MAX],
692 bool horz)
693{
694 bool scaling = format->is_yuv ? true : (src != dst);
695 int i;
696
697 /*
698 * Note:
699 * We assume here that:
700 * 1. PCMN filter is used for downscale
701 * 2. bilinear filter is used for upscale
702 * 3. we are in a single pipe configuration
703 */
704
705 for (i = 0; i < COMP_MAX; i++) {
706 pix_ext_edge1[i] = 0;
707 pix_ext_edge2[i] = scaling ? 1 : 0;
bef799fb 708 }
8e2930c6
SV		 709}
710
711static void mdp5_write_pixel_ext(struct mdp5_kms *mdp5_kms, enum mdp5_pipe pipe,
712 const struct mdp_format *format,
713 uint32_t src_w, int pe_left[COMP_MAX], int pe_right[COMP_MAX],
714 uint32_t src_h, int pe_top[COMP_MAX], int pe_bottom[COMP_MAX])
715{
716 uint32_t pix_fmt = format->base.pixel_format;
717 uint32_t lr, tb, req;
718 int i;
719
720 for (i = 0; i < COMP_MAX; i++) {
721 uint32_t roi_w = src_w;
722 uint32_t roi_h = src_h;
723
724 if (format->is_yuv && i == COMP_1_2) {
725 roi_w /= drm_format_horz_chroma_subsampling(pix_fmt);
726 roi_h /= drm_format_vert_chroma_subsampling(pix_fmt);
727 }
f8d9b515 728
8e2930c6
SV		 729 lr = (pe_left[i] >= 0) ?
730 MDP5_PIPE_SW_PIX_EXT_LR_LEFT_RPT(pe_left[i]) :
731 MDP5_PIPE_SW_PIX_EXT_LR_LEFT_OVF(pe_left[i]);
732
733 lr |= (pe_right[i] >= 0) ?
734 MDP5_PIPE_SW_PIX_EXT_LR_RIGHT_RPT(pe_right[i]) :
735 MDP5_PIPE_SW_PIX_EXT_LR_RIGHT_OVF(pe_right[i]);
736
737 tb = (pe_top[i] >= 0) ?
738 MDP5_PIPE_SW_PIX_EXT_TB_TOP_RPT(pe_top[i]) :
739 MDP5_PIPE_SW_PIX_EXT_TB_TOP_OVF(pe_top[i]);
740
741 tb |= (pe_bottom[i] >= 0) ?
742 MDP5_PIPE_SW_PIX_EXT_TB_BOTTOM_RPT(pe_bottom[i]) :
743 MDP5_PIPE_SW_PIX_EXT_TB_BOTTOM_OVF(pe_bottom[i]);
744
745 req = MDP5_PIPE_SW_PIX_EXT_REQ_PIXELS_LEFT_RIGHT(roi_w +
746 pe_left[i] + pe_right[i]);
747
748 req |= MDP5_PIPE_SW_PIX_EXT_REQ_PIXELS_TOP_BOTTOM(roi_h +
749 pe_top[i] + pe_bottom[i]);
750
751 mdp5_write(mdp5_kms, REG_MDP5_PIPE_SW_PIX_EXT_LR(pipe, i), lr);
752 mdp5_write(mdp5_kms, REG_MDP5_PIPE_SW_PIX_EXT_TB(pipe, i), tb);
753 mdp5_write(mdp5_kms, REG_MDP5_PIPE_SW_PIX_EXT_REQ_PIXELS(pipe, i), req);
754
755 DBG("comp-%d (L/R): rpt=%d/%d, ovf=%d/%d, req=%d", i,
756 FIELD(lr, MDP5_PIPE_SW_PIX_EXT_LR_LEFT_RPT),
757 FIELD(lr, MDP5_PIPE_SW_PIX_EXT_LR_RIGHT_RPT),
758 FIELD(lr, MDP5_PIPE_SW_PIX_EXT_LR_LEFT_OVF),
759 FIELD(lr, MDP5_PIPE_SW_PIX_EXT_LR_RIGHT_OVF),
760 FIELD(req, MDP5_PIPE_SW_PIX_EXT_REQ_PIXELS_LEFT_RIGHT));
761
762 DBG("comp-%d (T/B): rpt=%d/%d, ovf=%d/%d, req=%d", i,
763 FIELD(tb, MDP5_PIPE_SW_PIX_EXT_TB_TOP_RPT),
764 FIELD(tb, MDP5_PIPE_SW_PIX_EXT_TB_BOTTOM_RPT),
765 FIELD(tb, MDP5_PIPE_SW_PIX_EXT_TB_TOP_OVF),
766 FIELD(tb, MDP5_PIPE_SW_PIX_EXT_TB_BOTTOM_OVF),
767 FIELD(req, MDP5_PIPE_SW_PIX_EXT_REQ_PIXELS_TOP_BOTTOM));
768 }
f8d9b515
SV		 769}
770
821be43f
AT		 771struct pixel_ext {
772 int left[COMP_MAX];
773 int right[COMP_MAX];
774 int top[COMP_MAX];
775 int bottom[COMP_MAX];
776};
777
778struct phase_step {
779 u32 x[COMP_MAX];
780 u32 y[COMP_MAX];
781};
782
783static void mdp5_hwpipe_mode_set(struct mdp5_kms *mdp5_kms,
784 struct mdp5_hw_pipe *hwpipe,
785 struct drm_framebuffer *fb,
786 struct phase_step *step,
787 struct pixel_ext *pe,
788 u32 scale_config, u32 hdecm, u32 vdecm,
789 bool hflip, bool vflip,
790 int crtc_x, int crtc_y,
791 unsigned int crtc_w, unsigned int crtc_h,
792 u32 src_img_w, u32 src_img_h,
793 u32 src_x, u32 src_y,
794 u32 src_w, u32 src_h)
795{
796 enum mdp5_pipe pipe = hwpipe->pipe;
797 bool has_pe = hwpipe->caps & MDP_PIPE_CAP_SW_PIX_EXT;
798 const struct mdp_format *format =
799 to_mdp_format(msm_framebuffer_format(fb));
800
801 mdp5_write(mdp5_kms, REG_MDP5_PIPE_SRC_IMG_SIZE(pipe),
802 MDP5_PIPE_SRC_IMG_SIZE_WIDTH(src_img_w) |
803 MDP5_PIPE_SRC_IMG_SIZE_HEIGHT(src_img_h));
804
805 mdp5_write(mdp5_kms, REG_MDP5_PIPE_SRC_SIZE(pipe),
806 MDP5_PIPE_SRC_SIZE_WIDTH(src_w) |
807 MDP5_PIPE_SRC_SIZE_HEIGHT(src_h));
808
809 mdp5_write(mdp5_kms, REG_MDP5_PIPE_SRC_XY(pipe),
810 MDP5_PIPE_SRC_XY_X(src_x) |
811 MDP5_PIPE_SRC_XY_Y(src_y));
812
813 mdp5_write(mdp5_kms, REG_MDP5_PIPE_OUT_SIZE(pipe),
814 MDP5_PIPE_OUT_SIZE_WIDTH(crtc_w) |
815 MDP5_PIPE_OUT_SIZE_HEIGHT(crtc_h));
816
817 mdp5_write(mdp5_kms, REG_MDP5_PIPE_OUT_XY(pipe),
818 MDP5_PIPE_OUT_XY_X(crtc_x) |
819 MDP5_PIPE_OUT_XY_Y(crtc_y));
820
821 mdp5_write(mdp5_kms, REG_MDP5_PIPE_SRC_FORMAT(pipe),
822 MDP5_PIPE_SRC_FORMAT_A_BPC(format->bpc_a) |
823 MDP5_PIPE_SRC_FORMAT_R_BPC(format->bpc_r) |
824 MDP5_PIPE_SRC_FORMAT_G_BPC(format->bpc_g) |
825 MDP5_PIPE_SRC_FORMAT_B_BPC(format->bpc_b) |
826 COND(format->alpha_enable, MDP5_PIPE_SRC_FORMAT_ALPHA_ENABLE) |
827 MDP5_PIPE_SRC_FORMAT_CPP(format->cpp - 1) |
828 MDP5_PIPE_SRC_FORMAT_UNPACK_COUNT(format->unpack_count - 1) |
829 COND(format->unpack_tight, MDP5_PIPE_SRC_FORMAT_UNPACK_TIGHT) |
830 MDP5_PIPE_SRC_FORMAT_FETCH_TYPE(format->fetch_type) |
831 MDP5_PIPE_SRC_FORMAT_CHROMA_SAMP(format->chroma_sample));
832
833 mdp5_write(mdp5_kms, REG_MDP5_PIPE_SRC_UNPACK(pipe),
834 MDP5_PIPE_SRC_UNPACK_ELEM0(format->unpack[0]) |
835 MDP5_PIPE_SRC_UNPACK_ELEM1(format->unpack[1]) |
836 MDP5_PIPE_SRC_UNPACK_ELEM2(format->unpack[2]) |
837 MDP5_PIPE_SRC_UNPACK_ELEM3(format->unpack[3]));
838
839 mdp5_write(mdp5_kms, REG_MDP5_PIPE_SRC_OP_MODE(pipe),
840 (hflip ? MDP5_PIPE_SRC_OP_MODE_FLIP_LR : 0) |
841 (vflip ? MDP5_PIPE_SRC_OP_MODE_FLIP_UD : 0) |
842 COND(has_pe, MDP5_PIPE_SRC_OP_MODE_SW_PIX_EXT_OVERRIDE) |
843 MDP5_PIPE_SRC_OP_MODE_BWC(BWC_LOSSLESS));
844
845 /* not using secure mode: */
846 mdp5_write(mdp5_kms, REG_MDP5_PIPE_SRC_ADDR_SW_STATUS(pipe), 0);
847
848 if (hwpipe->caps & MDP_PIPE_CAP_SW_PIX_EXT)
849 mdp5_write_pixel_ext(mdp5_kms, pipe, format,
850 src_w, pe->left, pe->right,
851 src_h, pe->top, pe->bottom);
852
853 if (hwpipe->caps & MDP_PIPE_CAP_SCALE) {
854 mdp5_write(mdp5_kms, REG_MDP5_PIPE_SCALE_PHASE_STEP_X(pipe),
855 step->x[COMP_0]);
856 mdp5_write(mdp5_kms, REG_MDP5_PIPE_SCALE_PHASE_STEP_Y(pipe),
857 step->y[COMP_0]);
858 mdp5_write(mdp5_kms, REG_MDP5_PIPE_SCALE_CR_PHASE_STEP_X(pipe),
859 step->x[COMP_1_2]);
860 mdp5_write(mdp5_kms, REG_MDP5_PIPE_SCALE_CR_PHASE_STEP_Y(pipe),
861 step->y[COMP_1_2]);
862 mdp5_write(mdp5_kms, REG_MDP5_PIPE_DECIMATION(pipe),
863 MDP5_PIPE_DECIMATION_VERT(vdecm) |
864 MDP5_PIPE_DECIMATION_HORZ(hdecm));
865 mdp5_write(mdp5_kms, REG_MDP5_PIPE_SCALE_CONFIG(pipe),
866 scale_config);
867 }
868
869 if (hwpipe->caps & MDP_PIPE_CAP_CSC) {
870 if (MDP_FORMAT_IS_YUV(format))
871 csc_enable(mdp5_kms, pipe,
872 mdp_get_default_csc_cfg(CSC_YUV2RGB));
873 else
874 csc_disable(mdp5_kms, pipe);
875 }
876
877 set_scanout_locked(mdp5_kms, pipe, fb);
878}
8e2930c6 879
ed851963 880static int mdp5_plane_mode_set(struct drm_plane *plane,
06c0dd96 881 struct drm_crtc *crtc, struct drm_framebuffer *fb,
3b6acf14 882 struct drm_rect *src, struct drm_rect *dest)
06c0dd96 883{
8089082f 884 struct drm_plane_state *pstate = plane->state;
4a0f012d 885 struct mdp5_hw_pipe *hwpipe = to_mdp5_plane_state(pstate)->hwpipe;
06c0dd96 886 struct mdp5_kms *mdp5_kms = get_kms(plane);
c056b55d 887 enum mdp5_pipe pipe = hwpipe->pipe;
c26b4f6c 888 struct mdp5_hw_pipe *right_hwpipe;
06c0dd96
RC		 889 const struct mdp_format *format;
890 uint32_t nplanes, config = 0;
821be43f
AT		 891 struct phase_step step = { 0 };
892 struct pixel_ext pe = { 0 };
06c0dd96 893 uint32_t hdecm = 0, vdecm = 0;
f8d9b515 894 uint32_t pix_format;
574a37b1 895 unsigned int rotation;
8089082f 896 bool vflip, hflip;
3b6acf14
AT		 897 int crtc_x, crtc_y;
898 unsigned int crtc_w, crtc_h;
899 uint32_t src_x, src_y;
900 uint32_t src_w, src_h;
821be43f 901 uint32_t src_img_w, src_img_h;
c26b4f6c
AT		 902 uint32_t src_x_r;
903 int crtc_x_r;
bfcdfb0e 904 int ret;
06c0dd96 905
bcb0b461 906 nplanes = fb->format->num_planes;
06c0dd96
RC		 907
908 /* bad formats should already be rejected: */
909 if (WARN_ON(nplanes > pipe2nclients(pipe)))
910 return -EINVAL;
911
f8d9b515
SV		 912 format = to_mdp_format(msm_framebuffer_format(fb));
913 pix_format = format->base.pixel_format;
914
3b6acf14
AT		 915 src_x = src->x1;
916 src_y = src->y1;
917 src_w = drm_rect_width(src);
918 src_h = drm_rect_height(src);
919
920 crtc_x = dest->x1;
921 crtc_y = dest->y1;
922 crtc_w = drm_rect_width(dest);
923 crtc_h = drm_rect_height(dest);
924
06c0dd96
RC		 925 /* src values are in Q16 fixed point, convert to integer: */
926 src_x = src_x >> 16;
927 src_y = src_y >> 16;
928 src_w = src_w >> 16;
929 src_h = src_h >> 16;
930
821be43f
AT		 931 src_img_w = min(fb->width, src_w);
932 src_img_h = min(fb->height, src_h);
933
0002d30f 934 DBG("%s: FB[%u] %u,%u,%u,%u -> CRTC[%u] %d,%d,%u,%u", plane->name,
06c0dd96
RC		 935 fb->base.id, src_x, src_y, src_w, src_h,
936 crtc->base.id, crtc_x, crtc_y, crtc_w, crtc_h);
937
c26b4f6c
AT		 938 right_hwpipe = to_mdp5_plane_state(pstate)->r_hwpipe;
939 if (right_hwpipe) {
940 /*
941 * if the plane comprises of 2 hw pipes, assume that the width
942 * is split equally across them. The only parameters that varies
943 * between the 2 pipes are src_x and crtc_x
944 */
945 crtc_w /= 2;
946 src_w /= 2;
947 src_img_w /= 2;
948
949 crtc_x_r = crtc_x + crtc_w;
950 src_x_r = src_x + src_w;
951 }
952
821be43f 953 ret = calc_scalex_steps(plane, pix_format, src_w, crtc_w, step.x);
bef799fb
SV		 954 if (ret)
955 return ret;
f8d9b515 956
821be43f 957 ret = calc_scaley_steps(plane, pix_format, src_h, crtc_h, step.y);
bef799fb
SV		 958 if (ret)
959 return ret;
06c0dd96 960
c056b55d 961 if (hwpipe->caps & MDP_PIPE_CAP_SW_PIX_EXT) {
821be43f
AT		 962 calc_pixel_ext(format, src_w, crtc_w, step.x,
963 pe.left, pe.right, true);
964 calc_pixel_ext(format, src_h, crtc_h, step.y,
965 pe.top, pe.bottom, false);
8e2930c6
SV		 966 }
967
bef799fb
SV		 968 /* TODO calc hdecm, vdecm */
969
970 /* SCALE is used to both scale and up-sample chroma components */
8e2930c6
SV		 971 config |= get_scale_config(format, src_w, crtc_w, true);
972 config |= get_scale_config(format, src_h, crtc_h, false);
bef799fb 973 DBG("scale config = %x", config);
06c0dd96 974
574a37b1 975 rotation = drm_rotation_simplify(pstate->rotation,
c2c446ad
RF		 976 DRM_MODE_ROTATE_0 |
977 DRM_MODE_REFLECT_X |
978 DRM_MODE_REFLECT_Y);
979 hflip = !!(rotation & DRM_MODE_REFLECT_X);
980 vflip = !!(rotation & DRM_MODE_REFLECT_Y);
8089082f 981
821be43f
AT		 982 mdp5_hwpipe_mode_set(mdp5_kms, hwpipe, fb, &step, &pe,
983 config, hdecm, vdecm, hflip, vflip,
984 crtc_x, crtc_y, crtc_w, crtc_h,
985 src_img_w, src_img_h,
986 src_x, src_y, src_w, src_h);
c26b4f6c
AT		 987 if (right_hwpipe)
988 mdp5_hwpipe_mode_set(mdp5_kms, right_hwpipe, fb, &step, &pe,
989 config, hdecm, vdecm, hflip, vflip,
990 crtc_x_r, crtc_y, crtc_w, crtc_h,
991 src_img_w, src_img_h,
992 src_x_r, src_y, src_w, src_h);
0deed25b 993
821be43f
AT		 994 plane->fb = fb;
995
0deed25b 996 return ret;
06c0dd96
RC		 997}
998
10967a06
AT		 999static int mdp5_update_cursor_plane_legacy(struct drm_plane *plane,
1000 struct drm_crtc *crtc, struct drm_framebuffer *fb,
1001 int crtc_x, int crtc_y,
1002 unsigned int crtc_w, unsigned int crtc_h,
1003 uint32_t src_x, uint32_t src_y,
34a2ab5e
DV		 1004 uint32_t src_w, uint32_t src_h,
1005 struct drm_modeset_acquire_ctx *ctx)
10967a06
AT		 1006{
1007 struct drm_plane_state *plane_state, *new_plane_state;
1008 struct mdp5_plane_state *mdp5_pstate;
1009 struct drm_crtc_state *crtc_state = crtc->state;
1010 int ret;
1011
1012 if (!crtc_state->active || drm_atomic_crtc_needs_modeset(crtc_state))
1013 goto slow;
1014
1015 plane_state = plane->state;
1016 mdp5_pstate = to_mdp5_plane_state(plane_state);
1017
1018 /* don't use fast path if we don't have a hwpipe allocated yet */
1019 if (!mdp5_pstate->hwpipe)
1020 goto slow;
1021
1022 /* only allow changing of position(crtc x/y or src x/y) in fast path */
1023 if (plane_state->crtc != crtc ||
1024 plane_state->src_w != src_w ||
1025 plane_state->src_h != src_h ||
1026 plane_state->crtc_w != crtc_w ||
1027 plane_state->crtc_h != crtc_h ||
1028 !plane_state->fb ||
1029 plane_state->fb != fb)
1030 goto slow;
1031
1032 new_plane_state = mdp5_plane_duplicate_state(plane);
1033 if (!new_plane_state)
1034 return -ENOMEM;
1035
1036 new_plane_state->src_x = src_x;
1037 new_plane_state->src_y = src_y;
1038 new_plane_state->src_w = src_w;
1039 new_plane_state->src_h = src_h;
1040 new_plane_state->crtc_x = crtc_x;
1041 new_plane_state->crtc_y = crtc_y;
1042 new_plane_state->crtc_w = crtc_w;
1043 new_plane_state->crtc_h = crtc_h;
1044
1045 ret = mdp5_plane_atomic_check_with_state(crtc_state, new_plane_state);
1046 if (ret)
1047 goto slow_free;
1048
1049 if (new_plane_state->visible) {
1050 struct mdp5_ctl *ctl;
f316b25a 1051 struct mdp5_pipeline *pipeline = mdp5_crtc_get_pipeline(crtc);
10967a06
AT		 1052
1053 ret = mdp5_plane_mode_set(plane, crtc, fb,
1054 &new_plane_state->src,
1055 &new_plane_state->dst);
1056 WARN_ON(ret < 0);
1057
1058 ctl = mdp5_crtc_get_ctl(crtc);
1059
f316b25a 1060 mdp5_ctl_commit(ctl, pipeline, mdp5_plane_get_flush(plane));
10967a06
AT		 1061 }
1062
1063 *to_mdp5_plane_state(plane_state) =
1064 *to_mdp5_plane_state(new_plane_state);
1065
1066 mdp5_plane_destroy_state(plane, new_plane_state);
1067
1068 return 0;
1069slow_free:
1070 mdp5_plane_destroy_state(plane, new_plane_state);
1071slow:
1072 return drm_atomic_helper_update_plane(plane, crtc, fb,
1073 crtc_x, crtc_y, crtc_w, crtc_h,
34a2ab5e 1074 src_x, src_y, src_w, src_h, ctx);
10967a06
AT		 1075}
1076
c26b4f6c
AT		 1077/*
1078 * Use this func and the one below only after the atomic state has been
1079 * successfully swapped
1080 */
06c0dd96
RC		 1081enum mdp5_pipe mdp5_plane_pipe(struct drm_plane *plane)
1082{
4a0f012d
RC		 1083 struct mdp5_plane_state *pstate = to_mdp5_plane_state(plane->state);
1084
1085 if (WARN_ON(!pstate->hwpipe))
106f9727 1086 return SSPP_NONE;
4a0f012d
RC		 1087
1088 return pstate->hwpipe->pipe;
06c0dd96
RC		 1089}
1090
c26b4f6c
AT		 1091enum mdp5_pipe mdp5_plane_right_pipe(struct drm_plane *plane)
1092{
1093 struct mdp5_plane_state *pstate = to_mdp5_plane_state(plane->state);
1094
1095 if (!pstate->r_hwpipe)
1096 return SSPP_NONE;
1097
1098 return pstate->r_hwpipe->pipe;
1099}
1100
0deed25b
SV		 1101uint32_t mdp5_plane_get_flush(struct drm_plane *plane)
1102{
4a0f012d 1103 struct mdp5_plane_state *pstate = to_mdp5_plane_state(plane->state);
c26b4f6c 1104 u32 mask;
4a0f012d
RC		 1105
1106 if (WARN_ON(!pstate->hwpipe))
1107 return 0;
0deed25b 1108
c26b4f6c
AT		 1109 mask = pstate->hwpipe->flush_mask;
1110
1111 if (pstate->r_hwpipe)
1112 mask |= pstate->r_hwpipe->flush_mask;
1113
1114 return mask;
0deed25b
SV		 1115}
1116
06c0dd96 1117/* initialize plane */
5798c8e0
AT		 1118struct drm_plane *mdp5_plane_init(struct drm_device *dev,
1119 enum drm_plane_type type)
06c0dd96
RC		 1120{
1121 struct drm_plane *plane = NULL;
1122 struct mdp5_plane *mdp5_plane;
1123 int ret;
1124
1125 mdp5_plane = kzalloc(sizeof(*mdp5_plane), GFP_KERNEL);
1126 if (!mdp5_plane) {
1127 ret = -ENOMEM;
1128 goto fail;
1129 }
1130
1131 plane = &mdp5_plane->base;
1132
3498409f 1133 mdp5_plane->nformats = mdp_get_formats(mdp5_plane->formats,
4a0f012d 1134 ARRAY_SIZE(mdp5_plane->formats), false);
0deed25b 1135
10967a06
AT		 1136 if (type == DRM_PLANE_TYPE_CURSOR)
1137 ret = drm_universal_plane_init(dev, plane, 0xff,
1138 &mdp5_cursor_plane_funcs,
1139 mdp5_plane->formats, mdp5_plane->nformats,
e6fc3b68 1140 NULL, type, NULL);
10967a06
AT		 1141 else
1142 ret = drm_universal_plane_init(dev, plane, 0xff,
1143 &mdp5_plane_funcs,
1144 mdp5_plane->formats, mdp5_plane->nformats,
e6fc3b68 1145 NULL, type, NULL);
ed851963
RC		 1146 if (ret)
1147 goto fail;
1148
1149 drm_plane_helper_add(plane, &mdp5_plane_helper_funcs);
06c0dd96
RC		 1150
1151 mdp5_plane_install_properties(plane, &plane->base);
1152
1153 return plane;
1154
1155fail:
1156 if (plane)
1157 mdp5_plane_destroy(plane);
1158
1159 return ERR_PTR(ret);
1160}
ubuntu-bionic-kernel mirror