]> git.proxmox.com Git - mirror_ubuntu-artful-kernel.git/blame - drivers/gpu/drm/msm/msm_drv.c
drm: Remove unused drm_device from drm_gem_object_lookup()
[mirror_ubuntu-artful-kernel.git] / drivers / gpu / drm / msm / msm_drv.c
CommitLineData
c8afe684
RC
1/*
2 * Copyright (C) 2013 Red Hat
3 * Author: Rob Clark <robdclark@gmail.com>
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 as published by
7 * the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program. If not, see <http://www.gnu.org/licenses/>.
16 */
17
18#include "msm_drv.h"
edcd60ce 19#include "msm_debugfs.h"
fde5de6c 20#include "msm_fence.h"
7198e6b0 21#include "msm_gpu.h"
dd2da6e3 22#include "msm_kms.h"
c8afe684 23
c8afe684
RC
24static void msm_fb_output_poll_changed(struct drm_device *dev)
25{
26 struct msm_drm_private *priv = dev->dev_private;
27 if (priv->fbdev)
28 drm_fb_helper_hotplug_event(priv->fbdev);
29}
30
31static const struct drm_mode_config_funcs mode_config_funcs = {
32 .fb_create = msm_framebuffer_create,
33 .output_poll_changed = msm_fb_output_poll_changed,
b4274fbe 34 .atomic_check = msm_atomic_check,
cf3a7e4c 35 .atomic_commit = msm_atomic_commit,
c8afe684
RC
36};
37
871d812a 38int msm_register_mmu(struct drm_device *dev, struct msm_mmu *mmu)
c8afe684
RC
39{
40 struct msm_drm_private *priv = dev->dev_private;
871d812a 41 int idx = priv->num_mmus++;
c8afe684 42
871d812a 43 if (WARN_ON(idx >= ARRAY_SIZE(priv->mmus)))
c8afe684
RC
44 return -EINVAL;
45
871d812a 46 priv->mmus[idx] = mmu;
c8afe684
RC
47
48 return idx;
49}
50
c8afe684
RC
51#ifdef CONFIG_DRM_MSM_REGISTER_LOGGING
52static bool reglog = false;
53MODULE_PARM_DESC(reglog, "Enable register read/write logging");
54module_param(reglog, bool, 0600);
55#else
56#define reglog 0
57#endif
58
a9ee34b7 59#ifdef CONFIG_DRM_FBDEV_EMULATION
e90dfec7
RC
60static bool fbdev = true;
61MODULE_PARM_DESC(fbdev, "Enable fbdev compat layer");
62module_param(fbdev, bool, 0600);
63#endif
64
3a10ba8c 65static char *vram = "16m";
4313c744 66MODULE_PARM_DESC(vram, "Configure VRAM size (for devices without IOMMU/GPUMMU)");
871d812a
RC
67module_param(vram, charp, 0);
68
060530f1
RC
69/*
70 * Util/helpers:
71 */
72
c8afe684
RC
73void __iomem *msm_ioremap(struct platform_device *pdev, const char *name,
74 const char *dbgname)
75{
76 struct resource *res;
77 unsigned long size;
78 void __iomem *ptr;
79
80 if (name)
81 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, name);
82 else
83 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
84
85 if (!res) {
86 dev_err(&pdev->dev, "failed to get memory resource: %s\n", name);
87 return ERR_PTR(-EINVAL);
88 }
89
90 size = resource_size(res);
91
92 ptr = devm_ioremap_nocache(&pdev->dev, res->start, size);
93 if (!ptr) {
94 dev_err(&pdev->dev, "failed to ioremap: %s\n", name);
95 return ERR_PTR(-ENOMEM);
96 }
97
98 if (reglog)
fc99f97a 99 printk(KERN_DEBUG "IO:region %s %p %08lx\n", dbgname, ptr, size);
c8afe684
RC
100
101 return ptr;
102}
103
104void msm_writel(u32 data, void __iomem *addr)
105{
106 if (reglog)
fc99f97a 107 printk(KERN_DEBUG "IO:W %p %08x\n", addr, data);
c8afe684
RC
108 writel(data, addr);
109}
110
111u32 msm_readl(const void __iomem *addr)
112{
113 u32 val = readl(addr);
114 if (reglog)
fc99f97a 115 printk(KERN_ERR "IO:R %p %08x\n", addr, val);
c8afe684
RC
116 return val;
117}
118
78b1d470
HL
119struct vblank_event {
120 struct list_head node;
121 int crtc_id;
122 bool enable;
123};
124
125static void vblank_ctrl_worker(struct work_struct *work)
126{
127 struct msm_vblank_ctrl *vbl_ctrl = container_of(work,
128 struct msm_vblank_ctrl, work);
129 struct msm_drm_private *priv = container_of(vbl_ctrl,
130 struct msm_drm_private, vblank_ctrl);
131 struct msm_kms *kms = priv->kms;
132 struct vblank_event *vbl_ev, *tmp;
133 unsigned long flags;
134
135 spin_lock_irqsave(&vbl_ctrl->lock, flags);
136 list_for_each_entry_safe(vbl_ev, tmp, &vbl_ctrl->event_list, node) {
137 list_del(&vbl_ev->node);
138 spin_unlock_irqrestore(&vbl_ctrl->lock, flags);
139
140 if (vbl_ev->enable)
141 kms->funcs->enable_vblank(kms,
142 priv->crtcs[vbl_ev->crtc_id]);
143 else
144 kms->funcs->disable_vblank(kms,
145 priv->crtcs[vbl_ev->crtc_id]);
146
147 kfree(vbl_ev);
148
149 spin_lock_irqsave(&vbl_ctrl->lock, flags);
150 }
151
152 spin_unlock_irqrestore(&vbl_ctrl->lock, flags);
153}
154
155static int vblank_ctrl_queue_work(struct msm_drm_private *priv,
156 int crtc_id, bool enable)
157{
158 struct msm_vblank_ctrl *vbl_ctrl = &priv->vblank_ctrl;
159 struct vblank_event *vbl_ev;
160 unsigned long flags;
161
162 vbl_ev = kzalloc(sizeof(*vbl_ev), GFP_ATOMIC);
163 if (!vbl_ev)
164 return -ENOMEM;
165
166 vbl_ev->crtc_id = crtc_id;
167 vbl_ev->enable = enable;
168
169 spin_lock_irqsave(&vbl_ctrl->lock, flags);
170 list_add_tail(&vbl_ev->node, &vbl_ctrl->event_list);
171 spin_unlock_irqrestore(&vbl_ctrl->lock, flags);
172
173 queue_work(priv->wq, &vbl_ctrl->work);
174
175 return 0;
176}
177
2b669875 178static int msm_drm_uninit(struct device *dev)
c8afe684 179{
2b669875
AT
180 struct platform_device *pdev = to_platform_device(dev);
181 struct drm_device *ddev = platform_get_drvdata(pdev);
182 struct msm_drm_private *priv = ddev->dev_private;
c8afe684 183 struct msm_kms *kms = priv->kms;
7198e6b0 184 struct msm_gpu *gpu = priv->gpu;
78b1d470
HL
185 struct msm_vblank_ctrl *vbl_ctrl = &priv->vblank_ctrl;
186 struct vblank_event *vbl_ev, *tmp;
187
188 /* We must cancel and cleanup any pending vblank enable/disable
189 * work before drm_irq_uninstall() to avoid work re-enabling an
190 * irq after uninstall has disabled it.
191 */
192 cancel_work_sync(&vbl_ctrl->work);
193 list_for_each_entry_safe(vbl_ev, tmp, &vbl_ctrl->event_list, node) {
194 list_del(&vbl_ev->node);
195 kfree(vbl_ev);
196 }
c8afe684 197
2b669875
AT
198 drm_kms_helper_poll_fini(ddev);
199
200 drm_connector_unregister_all(ddev);
1aaa57f5 201
2b669875 202 drm_dev_unregister(ddev);
8208ed93 203
1aaa57f5
AT
204#ifdef CONFIG_DRM_FBDEV_EMULATION
205 if (fbdev && priv->fbdev)
2b669875 206 msm_fbdev_free(ddev);
1aaa57f5 207#endif
2b669875 208 drm_mode_config_cleanup(ddev);
c8afe684 209
2b669875
AT
210 pm_runtime_get_sync(dev);
211 drm_irq_uninstall(ddev);
212 pm_runtime_put_sync(dev);
c8afe684
RC
213
214 flush_workqueue(priv->wq);
215 destroy_workqueue(priv->wq);
216
ba00c3f2
RC
217 flush_workqueue(priv->atomic_wq);
218 destroy_workqueue(priv->atomic_wq);
219
c8afe684 220 if (kms) {
2b669875 221 pm_runtime_disable(dev);
c8afe684
RC
222 kms->funcs->destroy(kms);
223 }
224
7198e6b0 225 if (gpu) {
2b669875 226 mutex_lock(&ddev->struct_mutex);
7198e6b0 227 gpu->funcs->pm_suspend(gpu);
2b669875 228 mutex_unlock(&ddev->struct_mutex);
774449eb 229 gpu->funcs->destroy(gpu);
7198e6b0 230 }
c8afe684 231
871d812a
RC
232 if (priv->vram.paddr) {
233 DEFINE_DMA_ATTRS(attrs);
234 dma_set_attr(DMA_ATTR_NO_KERNEL_MAPPING, &attrs);
235 drm_mm_takedown(&priv->vram.mm);
2b669875
AT
236 dma_free_attrs(dev, priv->vram.size, NULL,
237 priv->vram.paddr, &attrs);
871d812a
RC
238 }
239
2b669875 240 component_unbind_all(dev, ddev);
060530f1 241
2b669875
AT
242 ddev->dev_private = NULL;
243 drm_dev_unref(ddev);
c8afe684
RC
244
245 kfree(priv);
246
247 return 0;
248}
249
06c0dd96
RC
250static int get_mdp_ver(struct platform_device *pdev)
251{
06c0dd96 252 struct device *dev = &pdev->dev;
e9fbdaf2
AT
253
254 return (int) (unsigned long) of_device_get_match_data(dev);
06c0dd96
RC
255}
256
072f1f91
RC
257#include <linux/of_address.h>
258
5bf9c0b6 259static int msm_init_vram(struct drm_device *dev)
c8afe684 260{
5bf9c0b6 261 struct msm_drm_private *priv = dev->dev_private;
e9fbdaf2 262 struct device_node *node;
072f1f91
RC
263 unsigned long size = 0;
264 int ret = 0;
265
072f1f91
RC
266 /* In the device-tree world, we could have a 'memory-region'
267 * phandle, which gives us a link to our "vram". Allocating
268 * is all nicely abstracted behind the dma api, but we need
269 * to know the entire size to allocate it all in one go. There
270 * are two cases:
271 * 1) device with no IOMMU, in which case we need exclusive
272 * access to a VRAM carveout big enough for all gpu
273 * buffers
274 * 2) device with IOMMU, but where the bootloader puts up
275 * a splash screen. In this case, the VRAM carveout
276 * need only be large enough for fbdev fb. But we need
277 * exclusive access to the buffer to avoid the kernel
278 * using those pages for other purposes (which appears
279 * as corruption on screen before we have a chance to
280 * load and do initial modeset)
281 */
072f1f91
RC
282
283 node = of_parse_phandle(dev->dev->of_node, "memory-region", 0);
284 if (node) {
285 struct resource r;
286 ret = of_address_to_resource(node, 0, &r);
287 if (ret)
288 return ret;
289 size = r.end - r.start;
fc99f97a 290 DRM_INFO("using VRAM carveout: %lx@%pa\n", size, &r.start);
c8afe684 291
e9fbdaf2
AT
292 /* if we have no IOMMU, then we need to use carveout allocator.
293 * Grab the entire CMA chunk carved out in early startup in
294 * mach-msm:
295 */
296 } else if (!iommu_present(&platform_bus_type)) {
072f1f91
RC
297 DRM_INFO("using %s VRAM carveout\n", vram);
298 size = memparse(vram, NULL);
299 }
300
301 if (size) {
871d812a 302 DEFINE_DMA_ATTRS(attrs);
871d812a
RC
303 void *p;
304
871d812a
RC
305 priv->vram.size = size;
306
307 drm_mm_init(&priv->vram.mm, 0, (size >> PAGE_SHIFT) - 1);
308
309 dma_set_attr(DMA_ATTR_NO_KERNEL_MAPPING, &attrs);
310 dma_set_attr(DMA_ATTR_WRITE_COMBINE, &attrs);
311
312 /* note that for no-kernel-mapping, the vaddr returned
313 * is bogus, but non-null if allocation succeeded:
314 */
315 p = dma_alloc_attrs(dev->dev, size,
543d3011 316 &priv->vram.paddr, GFP_KERNEL, &attrs);
871d812a
RC
317 if (!p) {
318 dev_err(dev->dev, "failed to allocate VRAM\n");
319 priv->vram.paddr = 0;
5bf9c0b6 320 return -ENOMEM;
871d812a
RC
321 }
322
323 dev_info(dev->dev, "VRAM: %08x->%08x\n",
324 (uint32_t)priv->vram.paddr,
325 (uint32_t)(priv->vram.paddr + size));
326 }
327
072f1f91 328 return ret;
5bf9c0b6
RC
329}
330
2b669875 331static int msm_drm_init(struct device *dev, struct drm_driver *drv)
5bf9c0b6 332{
2b669875
AT
333 struct platform_device *pdev = to_platform_device(dev);
334 struct drm_device *ddev;
5bf9c0b6
RC
335 struct msm_drm_private *priv;
336 struct msm_kms *kms;
337 int ret;
338
2b669875
AT
339 ddev = drm_dev_alloc(drv, dev);
340 if (!ddev) {
341 dev_err(dev, "failed to allocate drm_device\n");
342 return -ENOMEM;
343 }
344
345 platform_set_drvdata(pdev, ddev);
346 ddev->platformdev = pdev;
347
5bf9c0b6
RC
348 priv = kzalloc(sizeof(*priv), GFP_KERNEL);
349 if (!priv) {
2b669875 350 drm_dev_unref(ddev);
5bf9c0b6
RC
351 return -ENOMEM;
352 }
353
2b669875 354 ddev->dev_private = priv;
5bf9c0b6
RC
355
356 priv->wq = alloc_ordered_workqueue("msm", 0);
ba00c3f2 357 priv->atomic_wq = alloc_ordered_workqueue("msm:atomic", 0);
5bf9c0b6
RC
358 init_waitqueue_head(&priv->pending_crtcs_event);
359
360 INIT_LIST_HEAD(&priv->inactive_list);
78b1d470
HL
361 INIT_LIST_HEAD(&priv->vblank_ctrl.event_list);
362 INIT_WORK(&priv->vblank_ctrl.work, vblank_ctrl_worker);
363 spin_lock_init(&priv->vblank_ctrl.lock);
5bf9c0b6 364
2b669875 365 drm_mode_config_init(ddev);
060530f1
RC
366
367 /* Bind all our sub-components: */
2b669875
AT
368 ret = component_bind_all(dev, ddev);
369 if (ret) {
370 kfree(priv);
371 drm_dev_unref(ddev);
060530f1 372 return ret;
2b669875 373 }
060530f1 374
2b669875 375 ret = msm_init_vram(ddev);
13f15565
RC
376 if (ret)
377 goto fail;
378
06c0dd96
RC
379 switch (get_mdp_ver(pdev)) {
380 case 4:
2b669875 381 kms = mdp4_kms_init(ddev);
06c0dd96
RC
382 break;
383 case 5:
2b669875 384 kms = mdp5_kms_init(ddev);
06c0dd96
RC
385 break;
386 default:
387 kms = ERR_PTR(-ENODEV);
388 break;
389 }
390
c8afe684
RC
391 if (IS_ERR(kms)) {
392 /*
393 * NOTE: once we have GPU support, having no kms should not
394 * be considered fatal.. ideally we would still support gpu
395 * and (for example) use dmabuf/prime to share buffers with
396 * imx drm driver on iMX5
397 */
2b669875 398 dev_err(dev, "failed to load kms\n");
e4826a94 399 ret = PTR_ERR(kms);
c8afe684
RC
400 goto fail;
401 }
402
403 priv->kms = kms;
404
405 if (kms) {
2b669875 406 pm_runtime_enable(dev);
c8afe684
RC
407 ret = kms->funcs->hw_init(kms);
408 if (ret) {
2b669875 409 dev_err(dev, "kms hw init failed: %d\n", ret);
c8afe684
RC
410 goto fail;
411 }
412 }
413
2b669875 414 ddev->mode_config.funcs = &mode_config_funcs;
c8afe684 415
2b669875 416 ret = drm_vblank_init(ddev, priv->num_crtcs);
c8afe684 417 if (ret < 0) {
2b669875 418 dev_err(dev, "failed to initialize vblank\n");
c8afe684
RC
419 goto fail;
420 }
421
2b669875
AT
422 pm_runtime_get_sync(dev);
423 ret = drm_irq_install(ddev, platform_get_irq(pdev, 0));
424 pm_runtime_put_sync(dev);
c8afe684 425 if (ret < 0) {
2b669875 426 dev_err(dev, "failed to install IRQ handler\n");
c8afe684
RC
427 goto fail;
428 }
429
2b669875
AT
430 ret = drm_dev_register(ddev, 0);
431 if (ret)
432 goto fail;
433
434 ret = drm_connector_register_all(ddev);
8208ed93 435 if (ret) {
2b669875 436 dev_err(dev, "failed to register connectors\n");
8208ed93
AT
437 goto fail;
438 }
439
2b669875 440 drm_mode_config_reset(ddev);
cf3a7e4c 441
a9ee34b7 442#ifdef CONFIG_DRM_FBDEV_EMULATION
e90dfec7 443 if (fbdev)
2b669875 444 priv->fbdev = msm_fbdev_init(ddev);
c8afe684
RC
445#endif
446
2b669875 447 ret = msm_debugfs_late_init(ddev);
a7d3c950
RC
448 if (ret)
449 goto fail;
450
2b669875 451 drm_kms_helper_poll_init(ddev);
c8afe684
RC
452
453 return 0;
454
455fail:
2b669875 456 msm_drm_uninit(dev);
c8afe684
RC
457 return ret;
458}
459
2b669875
AT
460/*
461 * DRM operations:
462 */
463
7198e6b0
RC
464static void load_gpu(struct drm_device *dev)
465{
a1ad3523 466 static DEFINE_MUTEX(init_lock);
7198e6b0 467 struct msm_drm_private *priv = dev->dev_private;
7198e6b0 468
a1ad3523
RC
469 mutex_lock(&init_lock);
470
e2550b7a
RC
471 if (!priv->gpu)
472 priv->gpu = adreno_load_gpu(dev);
7198e6b0 473
a1ad3523 474 mutex_unlock(&init_lock);
7198e6b0
RC
475}
476
477static int msm_open(struct drm_device *dev, struct drm_file *file)
478{
479 struct msm_file_private *ctx;
480
481 /* For now, load gpu on open.. to avoid the requirement of having
482 * firmware in the initrd.
483 */
484 load_gpu(dev);
485
486 ctx = kzalloc(sizeof(*ctx), GFP_KERNEL);
487 if (!ctx)
488 return -ENOMEM;
489
490 file->driver_priv = ctx;
491
492 return 0;
493}
494
c8afe684
RC
495static void msm_preclose(struct drm_device *dev, struct drm_file *file)
496{
497 struct msm_drm_private *priv = dev->dev_private;
7198e6b0 498 struct msm_file_private *ctx = file->driver_priv;
7198e6b0 499
7198e6b0
RC
500 mutex_lock(&dev->struct_mutex);
501 if (ctx == priv->lastctx)
502 priv->lastctx = NULL;
503 mutex_unlock(&dev->struct_mutex);
504
505 kfree(ctx);
c8afe684
RC
506}
507
508static void msm_lastclose(struct drm_device *dev)
509{
510 struct msm_drm_private *priv = dev->dev_private;
5ea1f752
RC
511 if (priv->fbdev)
512 drm_fb_helper_restore_fbdev_mode_unlocked(priv->fbdev);
c8afe684
RC
513}
514
e9f0d76f 515static irqreturn_t msm_irq(int irq, void *arg)
c8afe684
RC
516{
517 struct drm_device *dev = arg;
518 struct msm_drm_private *priv = dev->dev_private;
519 struct msm_kms *kms = priv->kms;
520 BUG_ON(!kms);
521 return kms->funcs->irq(kms);
522}
523
524static void msm_irq_preinstall(struct drm_device *dev)
525{
526 struct msm_drm_private *priv = dev->dev_private;
527 struct msm_kms *kms = priv->kms;
528 BUG_ON(!kms);
529 kms->funcs->irq_preinstall(kms);
530}
531
532static int msm_irq_postinstall(struct drm_device *dev)
533{
534 struct msm_drm_private *priv = dev->dev_private;
535 struct msm_kms *kms = priv->kms;
536 BUG_ON(!kms);
537 return kms->funcs->irq_postinstall(kms);
538}
539
540static void msm_irq_uninstall(struct drm_device *dev)
541{
542 struct msm_drm_private *priv = dev->dev_private;
543 struct msm_kms *kms = priv->kms;
544 BUG_ON(!kms);
545 kms->funcs->irq_uninstall(kms);
546}
547
88e72717 548static int msm_enable_vblank(struct drm_device *dev, unsigned int pipe)
c8afe684
RC
549{
550 struct msm_drm_private *priv = dev->dev_private;
551 struct msm_kms *kms = priv->kms;
552 if (!kms)
553 return -ENXIO;
88e72717
TR
554 DBG("dev=%p, crtc=%u", dev, pipe);
555 return vblank_ctrl_queue_work(priv, pipe, true);
c8afe684
RC
556}
557
88e72717 558static void msm_disable_vblank(struct drm_device *dev, unsigned int pipe)
c8afe684
RC
559{
560 struct msm_drm_private *priv = dev->dev_private;
561 struct msm_kms *kms = priv->kms;
562 if (!kms)
563 return;
88e72717
TR
564 DBG("dev=%p, crtc=%u", dev, pipe);
565 vblank_ctrl_queue_work(priv, pipe, false);
c8afe684
RC
566}
567
7198e6b0
RC
568/*
569 * DRM ioctls:
570 */
571
572static int msm_ioctl_get_param(struct drm_device *dev, void *data,
573 struct drm_file *file)
574{
575 struct msm_drm_private *priv = dev->dev_private;
576 struct drm_msm_param *args = data;
577 struct msm_gpu *gpu;
578
579 /* for now, we just have 3d pipe.. eventually this would need to
580 * be more clever to dispatch to appropriate gpu module:
581 */
582 if (args->pipe != MSM_PIPE_3D0)
583 return -EINVAL;
584
585 gpu = priv->gpu;
586
587 if (!gpu)
588 return -ENXIO;
589
590 return gpu->funcs->get_param(gpu, args->param, &args->value);
591}
592
593static int msm_ioctl_gem_new(struct drm_device *dev, void *data,
594 struct drm_file *file)
595{
596 struct drm_msm_gem_new *args = data;
93ddb0d3
RC
597
598 if (args->flags & ~MSM_BO_FLAGS) {
599 DRM_ERROR("invalid flags: %08x\n", args->flags);
600 return -EINVAL;
601 }
602
7198e6b0
RC
603 return msm_gem_new_handle(dev, file, args->size,
604 args->flags, &args->handle);
605}
606
56c2da83
RC
607static inline ktime_t to_ktime(struct drm_msm_timespec timeout)
608{
609 return ktime_set(timeout.tv_sec, timeout.tv_nsec);
610}
7198e6b0
RC
611
612static int msm_ioctl_gem_cpu_prep(struct drm_device *dev, void *data,
613 struct drm_file *file)
614{
615 struct drm_msm_gem_cpu_prep *args = data;
616 struct drm_gem_object *obj;
56c2da83 617 ktime_t timeout = to_ktime(args->timeout);
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618 int ret;
619
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620 if (args->op & ~MSM_PREP_FLAGS) {
621 DRM_ERROR("invalid op: %08x\n", args->op);
622 return -EINVAL;
623 }
624
a8ad0bd8 625 obj = drm_gem_object_lookup(file, args->handle);
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626 if (!obj)
627 return -ENOENT;
628
56c2da83 629 ret = msm_gem_cpu_prep(obj, args->op, &timeout);
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630
631 drm_gem_object_unreference_unlocked(obj);
632
633 return ret;
634}
635
636static int msm_ioctl_gem_cpu_fini(struct drm_device *dev, void *data,
637 struct drm_file *file)
638{
639 struct drm_msm_gem_cpu_fini *args = data;
640 struct drm_gem_object *obj;
641 int ret;
642
a8ad0bd8 643 obj = drm_gem_object_lookup(file, args->handle);
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644 if (!obj)
645 return -ENOENT;
646
647 ret = msm_gem_cpu_fini(obj);
648
649 drm_gem_object_unreference_unlocked(obj);
650
651 return ret;
652}
653
654static int msm_ioctl_gem_info(struct drm_device *dev, void *data,
655 struct drm_file *file)
656{
657 struct drm_msm_gem_info *args = data;
658 struct drm_gem_object *obj;
659 int ret = 0;
660
661 if (args->pad)
662 return -EINVAL;
663
a8ad0bd8 664 obj = drm_gem_object_lookup(file, args->handle);
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665 if (!obj)
666 return -ENOENT;
667
668 args->offset = msm_gem_mmap_offset(obj);
669
670 drm_gem_object_unreference_unlocked(obj);
671
672 return ret;
673}
674
675static int msm_ioctl_wait_fence(struct drm_device *dev, void *data,
676 struct drm_file *file)
677{
ca762a8a 678 struct msm_drm_private *priv = dev->dev_private;
7198e6b0 679 struct drm_msm_wait_fence *args = data;
56c2da83 680 ktime_t timeout = to_ktime(args->timeout);
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681
682 if (args->pad) {
683 DRM_ERROR("invalid pad: %08x\n", args->pad);
684 return -EINVAL;
685 }
686
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687 if (!priv->gpu)
688 return 0;
689
690 return msm_wait_fence(priv->gpu->fctx, args->fence, &timeout, true);
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691}
692
693static const struct drm_ioctl_desc msm_ioctls[] = {
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694 DRM_IOCTL_DEF_DRV(MSM_GET_PARAM, msm_ioctl_get_param, DRM_AUTH|DRM_RENDER_ALLOW),
695 DRM_IOCTL_DEF_DRV(MSM_GEM_NEW, msm_ioctl_gem_new, DRM_AUTH|DRM_RENDER_ALLOW),
696 DRM_IOCTL_DEF_DRV(MSM_GEM_INFO, msm_ioctl_gem_info, DRM_AUTH|DRM_RENDER_ALLOW),
697 DRM_IOCTL_DEF_DRV(MSM_GEM_CPU_PREP, msm_ioctl_gem_cpu_prep, DRM_AUTH|DRM_RENDER_ALLOW),
698 DRM_IOCTL_DEF_DRV(MSM_GEM_CPU_FINI, msm_ioctl_gem_cpu_fini, DRM_AUTH|DRM_RENDER_ALLOW),
699 DRM_IOCTL_DEF_DRV(MSM_GEM_SUBMIT, msm_ioctl_gem_submit, DRM_AUTH|DRM_RENDER_ALLOW),
700 DRM_IOCTL_DEF_DRV(MSM_WAIT_FENCE, msm_ioctl_wait_fence, DRM_AUTH|DRM_RENDER_ALLOW),
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701};
702
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703static const struct vm_operations_struct vm_ops = {
704 .fault = msm_gem_fault,
705 .open = drm_gem_vm_open,
706 .close = drm_gem_vm_close,
707};
708
709static const struct file_operations fops = {
710 .owner = THIS_MODULE,
711 .open = drm_open,
712 .release = drm_release,
713 .unlocked_ioctl = drm_ioctl,
714#ifdef CONFIG_COMPAT
715 .compat_ioctl = drm_compat_ioctl,
716#endif
717 .poll = drm_poll,
718 .read = drm_read,
719 .llseek = no_llseek,
720 .mmap = msm_gem_mmap,
721};
722
723static struct drm_driver msm_driver = {
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724 .driver_features = DRIVER_HAVE_IRQ |
725 DRIVER_GEM |
726 DRIVER_PRIME |
b4b15c86 727 DRIVER_RENDER |
a5436e1d 728 DRIVER_ATOMIC |
05b84911 729 DRIVER_MODESET,
7198e6b0 730 .open = msm_open,
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731 .preclose = msm_preclose,
732 .lastclose = msm_lastclose,
915b4d11 733 .set_busid = drm_platform_set_busid,
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734 .irq_handler = msm_irq,
735 .irq_preinstall = msm_irq_preinstall,
736 .irq_postinstall = msm_irq_postinstall,
737 .irq_uninstall = msm_irq_uninstall,
b44f8408 738 .get_vblank_counter = drm_vblank_no_hw_counter,
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739 .enable_vblank = msm_enable_vblank,
740 .disable_vblank = msm_disable_vblank,
741 .gem_free_object = msm_gem_free_object,
742 .gem_vm_ops = &vm_ops,
743 .dumb_create = msm_gem_dumb_create,
744 .dumb_map_offset = msm_gem_dumb_map_offset,
30600a90 745 .dumb_destroy = drm_gem_dumb_destroy,
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746 .prime_handle_to_fd = drm_gem_prime_handle_to_fd,
747 .prime_fd_to_handle = drm_gem_prime_fd_to_handle,
748 .gem_prime_export = drm_gem_prime_export,
749 .gem_prime_import = drm_gem_prime_import,
750 .gem_prime_pin = msm_gem_prime_pin,
751 .gem_prime_unpin = msm_gem_prime_unpin,
752 .gem_prime_get_sg_table = msm_gem_prime_get_sg_table,
753 .gem_prime_import_sg_table = msm_gem_prime_import_sg_table,
754 .gem_prime_vmap = msm_gem_prime_vmap,
755 .gem_prime_vunmap = msm_gem_prime_vunmap,
77a147e7 756 .gem_prime_mmap = msm_gem_prime_mmap,
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757#ifdef CONFIG_DEBUG_FS
758 .debugfs_init = msm_debugfs_init,
759 .debugfs_cleanup = msm_debugfs_cleanup,
760#endif
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761 .ioctls = msm_ioctls,
762 .num_ioctls = DRM_MSM_NUM_IOCTLS,
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763 .fops = &fops,
764 .name = "msm",
765 .desc = "MSM Snapdragon DRM",
766 .date = "20130625",
767 .major = 1,
768 .minor = 0,
769};
770
771#ifdef CONFIG_PM_SLEEP
772static int msm_pm_suspend(struct device *dev)
773{
774 struct drm_device *ddev = dev_get_drvdata(dev);
775
776 drm_kms_helper_poll_disable(ddev);
777
778 return 0;
779}
780
781static int msm_pm_resume(struct device *dev)
782{
783 struct drm_device *ddev = dev_get_drvdata(dev);
784
785 drm_kms_helper_poll_enable(ddev);
786
787 return 0;
788}
789#endif
790
791static const struct dev_pm_ops msm_pm_ops = {
792 SET_SYSTEM_SLEEP_PM_OPS(msm_pm_suspend, msm_pm_resume)
793};
794
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795/*
796 * Componentized driver support:
797 */
798
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799/*
800 * NOTE: duplication of the same code as exynos or imx (or probably any other).
801 * so probably some room for some helpers
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802 */
803static int compare_of(struct device *dev, void *data)
804{
805 return dev->of_node == data;
806}
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807
808static int add_components(struct device *dev, struct component_match **matchptr,
809 const char *name)
810{
811 struct device_node *np = dev->of_node;
812 unsigned i;
813
814 for (i = 0; ; i++) {
815 struct device_node *node;
816
817 node = of_parse_phandle(np, name, i);
818 if (!node)
819 break;
820
821 component_match_add(dev, matchptr, compare_of, node);
822 }
823
824 return 0;
825}
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826
827static int msm_drm_bind(struct device *dev)
828{
2b669875 829 return msm_drm_init(dev, &msm_driver);
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830}
831
832static void msm_drm_unbind(struct device *dev)
833{
2b669875 834 msm_drm_uninit(dev);
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835}
836
837static const struct component_master_ops msm_drm_ops = {
838 .bind = msm_drm_bind,
839 .unbind = msm_drm_unbind,
840};
841
842/*
843 * Platform driver:
844 */
060530f1 845
84448288 846static int msm_pdev_probe(struct platform_device *pdev)
060530f1 847{
84448288 848 struct component_match *match = NULL;
e9fbdaf2 849
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850 add_components(&pdev->dev, &match, "connectors");
851 add_components(&pdev->dev, &match, "gpus");
060530f1 852
871d812a 853 pdev->dev.coherent_dma_mask = DMA_BIT_MASK(32);
84448288 854 return component_master_add_with_match(&pdev->dev, &msm_drm_ops, match);
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855}
856
857static int msm_pdev_remove(struct platform_device *pdev)
858{
060530f1 859 component_master_del(&pdev->dev, &msm_drm_ops);
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860
861 return 0;
862}
863
864static const struct platform_device_id msm_id[] = {
865 { "mdp", 0 },
866 { }
867};
868
06c0dd96 869static const struct of_device_id dt_match[] = {
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870 { .compatible = "qcom,mdp4", .data = (void *) 4 }, /* mdp4 */
871 { .compatible = "qcom,mdp5", .data = (void *) 5 }, /* mdp5 */
872 /* to support downstream DT files */
873 { .compatible = "qcom,mdss_mdp", .data = (void *) 5 }, /* mdp5 */
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874 {}
875};
876MODULE_DEVICE_TABLE(of, dt_match);
877
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878static struct platform_driver msm_platform_driver = {
879 .probe = msm_pdev_probe,
880 .remove = msm_pdev_remove,
881 .driver = {
c8afe684 882 .name = "msm",
06c0dd96 883 .of_match_table = dt_match,
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884 .pm = &msm_pm_ops,
885 },
886 .id_table = msm_id,
887};
888
889static int __init msm_drm_register(void)
890{
891 DBG("init");
d5af49c9 892 msm_dsi_register();
00453981 893 msm_edp_register();
fcda50c8 894 msm_hdmi_register();
bfd28b13 895 adreno_register();
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896 return platform_driver_register(&msm_platform_driver);
897}
898
899static void __exit msm_drm_unregister(void)
900{
901 DBG("fini");
902 platform_driver_unregister(&msm_platform_driver);
fcda50c8 903 msm_hdmi_unregister();
bfd28b13 904 adreno_unregister();
00453981 905 msm_edp_unregister();
d5af49c9 906 msm_dsi_unregister();
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907}
908
909module_init(msm_drm_register);
910module_exit(msm_drm_unregister);
911
912MODULE_AUTHOR("Rob Clark <robdclark@gmail.com");
913MODULE_DESCRIPTION("MSM DRM Driver");
914MODULE_LICENSE("GPL");