]> git.proxmox.com Git - mirror_ubuntu-artful-kernel.git/blame - drivers/gpu/drm/nouveau/core/engine/disp/nva3.c
drm/nv50-/kms: remove unnecessary wait-for-completion points
[mirror_ubuntu-artful-kernel.git] / drivers / gpu / drm / nouveau / core / engine / disp / nva3.c
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1/*
2 * Copyright 2012 Red Hat Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: Ben Skeggs
23 */
24
25#include <engine/software.h>
26#include <engine/disp.h>
27
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28#include <core/class.h>
29
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30#include "nv50.h"
31
32static struct nouveau_oclass
33nva3_disp_sclass[] = {
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34 { NVA3_DISP_MAST_CLASS, &nv50_disp_mast_ofuncs },
35 { NVA3_DISP_SYNC_CLASS, &nv50_disp_sync_ofuncs },
36 { NVA3_DISP_OVLY_CLASS, &nv50_disp_ovly_ofuncs },
37 { NVA3_DISP_OIMM_CLASS, &nv50_disp_oimm_ofuncs },
38 { NVA3_DISP_CURS_CLASS, &nv50_disp_curs_ofuncs },
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39 {}
40};
41
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42struct nouveau_omthds
43nva3_disp_base_omthds[] = {
74b66850 44 { SOR_MTHD(NV50_DISP_SOR_PWR) , nv50_sor_mthd },
0a9e2b95 45 { SOR_MTHD(NVA3_DISP_SOR_HDA_ELD) , nv50_sor_mthd },
1c30cd09 46 { SOR_MTHD(NV84_DISP_SOR_HDMI_PWR) , nv50_sor_mthd },
4a230fa6 47 { SOR_MTHD(NV50_DISP_SOR_LVDS_SCRIPT) , nv50_sor_mthd },
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48 { DAC_MTHD(NV50_DISP_DAC_PWR) , nv50_dac_mthd },
49 { DAC_MTHD(NV50_DISP_DAC_LOAD) , nv50_dac_mthd },
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50 {},
51};
52
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53static struct nouveau_oclass
54nva3_disp_base_oclass[] = {
ef22c8bb 55 { NVA3_DISP_CLASS, &nv50_disp_base_ofuncs, nva3_disp_base_omthds },
370c00f9 56 {}
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57};
58
59static int
60nva3_disp_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
61 struct nouveau_oclass *oclass, void *data, u32 size,
62 struct nouveau_object **pobject)
63{
64 struct nv50_disp_priv *priv;
65 int ret;
66
1d7c71a3 67 ret = nouveau_disp_create(parent, engine, oclass, 2, "PDISP",
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68 "display", &priv);
69 *pobject = nv_object(priv);
70 if (ret)
71 return ret;
72
73 nv_engine(priv)->sclass = nva3_disp_base_oclass;
74 nv_engine(priv)->cclass = &nv50_disp_cclass;
75 nv_subdev(priv)->intr = nv50_disp_intr;
5cc027f6 76 INIT_WORK(&priv->supervisor, nv50_disp_intr_supervisor);
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77 priv->sclass = nva3_disp_sclass;
78 priv->head.nr = 2;
79 priv->dac.nr = 3;
80 priv->sor.nr = 4;
ef22c8bb 81 priv->dac.power = nv50_dac_power;
7ebb38b5 82 priv->dac.sense = nv50_dac_sense;
ef22c8bb 83 priv->sor.power = nv50_sor_power;
a4feaf4e 84 priv->sor.hda_eld = nva3_hda_eld;
8e9e3d2d 85 priv->sor.hdmi = nva3_hdmi_ctrl;
0a0afd28 86 priv->sor.dp = &nv94_sor_dp_func;
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87 return 0;
88}
89
90struct nouveau_oclass
91nva3_disp_oclass = {
92 .handle = NV_ENGINE(DISP, 0x85),
93 .ofuncs = &(struct nouveau_ofuncs) {
94 .ctor = nva3_disp_ctor,
95 .dtor = _nouveau_disp_dtor,
96 .init = _nouveau_disp_init,
97 .fini = _nouveau_disp_fini,
98 },
99};