[mirror_ubuntu-bionic-kernel.git] / drivers / gpu / drm / nouveau / core / subdev / fb / nv04.c

/*
 * Copyright 2012 Red Hat Inc.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 * OTHER DEALINGS IN THE SOFTWARE.
 *
 * Authors: Ben Skeggs
 */

#include <subdev/fb.h>

#define NV04_PFB_BOOT_0						0x00100000
#	define NV04_PFB_BOOT_0_RAM_AMOUNT			0x00000003
#	define NV04_PFB_BOOT_0_RAM_AMOUNT_32MB			0x00000000
#	define NV04_PFB_BOOT_0_RAM_AMOUNT_4MB			0x00000001
#	define NV04_PFB_BOOT_0_RAM_AMOUNT_8MB			0x00000002
#	define NV04_PFB_BOOT_0_RAM_AMOUNT_16MB			0x00000003
#	define NV04_PFB_BOOT_0_RAM_WIDTH_128			0x00000004
#	define NV04_PFB_BOOT_0_RAM_TYPE				0x00000028
#	define NV04_PFB_BOOT_0_RAM_TYPE_SGRAM_8MBIT		0x00000000
#	define NV04_PFB_BOOT_0_RAM_TYPE_SGRAM_16MBIT		0x00000008
#	define NV04_PFB_BOOT_0_RAM_TYPE_SGRAM_16MBIT_4BANK	0x00000010
#	define NV04_PFB_BOOT_0_RAM_TYPE_SDRAM_16MBIT		0x00000018
#	define NV04_PFB_BOOT_0_RAM_TYPE_SDRAM_64MBIT		0x00000020
#	define NV04_PFB_BOOT_0_RAM_TYPE_SDRAM_64MBITX16		0x00000028
#	define NV04_PFB_BOOT_0_UMA_ENABLE			0x00000100
#	define NV04_PFB_BOOT_0_UMA_SIZE				0x0000f000
#define NV04_PFB_CFG0						0x00100200

struct nv04_fb_priv {
	struct nouveau_fb base;
};

bool
nv04_fb_memtype_valid(struct nouveau_fb *pfb, u32 tile_flags)
{
	if (!(tile_flags & 0xff00))
		return true;

	return false;
}

static int
nv04_fb_init(struct nouveau_object *object)
{
	struct nv04_fb_priv *priv = (void *)object;
	int ret;

	ret = nouveau_fb_init(&priv->base);
	if (ret)
		return ret;

	/* This is what the DDX did for NV_ARCH_04, but a mmio-trace shows
	 * nvidia reading PFB_CFG_0, then writing back its original value.
	 * (which was 0x701114 in this case)
	 */
	nv_wr32(priv, NV04_PFB_CFG0, 0x1114);
	return 0;
}

static int
nv04_fb_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
	     struct nouveau_oclass *oclass, void *data, u32 size,
	     struct nouveau_object **pobject)
{
	struct nv04_fb_priv *priv;
	u32 boot0;
	int ret;

	ret = nouveau_fb_create(parent, engine, oclass, &priv);
	*pobject = nv_object(priv);
	if (ret)
		return ret;

	boot0 = nv_rd32(priv, NV04_PFB_BOOT_0);
	if (boot0 & 0x00000100) {
		priv->base.ram.size  = ((boot0 >> 12) & 0xf) * 2 + 2;
		priv->base.ram.size *= 1024 * 1024;
	} else {
		switch (boot0 & NV04_PFB_BOOT_0_RAM_AMOUNT) {
		case NV04_PFB_BOOT_0_RAM_AMOUNT_32MB:
			priv->base.ram.size = 32 * 1024 * 1024;
			break;
		case NV04_PFB_BOOT_0_RAM_AMOUNT_16MB:
			priv->base.ram.size = 16 * 1024 * 1024;
			break;
		case NV04_PFB_BOOT_0_RAM_AMOUNT_8MB:
			priv->base.ram.size = 8 * 1024 * 1024;
			break;
		case NV04_PFB_BOOT_0_RAM_AMOUNT_4MB:
			priv->base.ram.size = 4 * 1024 * 1024;
			break;
		}
	}

	if ((boot0 & 0x00000038) <= 0x10)
		priv->base.ram.type = NV_MEM_TYPE_SGRAM;
	else
		priv->base.ram.type = NV_MEM_TYPE_SDRAM;


	priv->base.memtype_valid = nv04_fb_memtype_valid;
	return nouveau_fb_created(&priv->base);
}

struct nouveau_oclass
nv04_fb_oclass = {
	.handle = NV_SUBDEV(FB, 0x04),
	.ofuncs = &(struct nouveau_ofuncs) {
		.ctor = nv04_fb_ctor,
		.dtor = _nouveau_fb_dtor,
		.init = nv04_fb_init,
		.fini = _nouveau_fb_fini,
	},
};
Commit	Line	Data
861d2107 BS	1	/*
	2	* Copyright 2012 Red Hat Inc.
	3	*
	4	* Permission is hereby granted, free of charge, to any person obtaining a
	5	* copy of this software and associated documentation files (the "Software"),
	6	* to deal in the Software without restriction, including without limitation
	7	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
	8	* and/or sell copies of the Software, and to permit persons to whom the
	9	* Software is furnished to do so, subject to the following conditions:
	10	*
	11	* The above copyright notice and this permission notice shall be included in
	12	* all copies or substantial portions of the Software.
	13	*
	14	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	15	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	16	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	17	* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
	18	* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
	19	* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
	20	* OTHER DEALINGS IN THE SOFTWARE.
	21	*
	22	* Authors: Ben Skeggs
	23	*/
6ee73861	24
861d2107 BS	25	#include <subdev/fb.h>
	26
	27	#define NV04_PFB_BOOT_0 0x00100000
	28	# define NV04_PFB_BOOT_0_RAM_AMOUNT 0x00000003
	29	# define NV04_PFB_BOOT_0_RAM_AMOUNT_32MB 0x00000000
	30	# define NV04_PFB_BOOT_0_RAM_AMOUNT_4MB 0x00000001
	31	# define NV04_PFB_BOOT_0_RAM_AMOUNT_8MB 0x00000002
	32	# define NV04_PFB_BOOT_0_RAM_AMOUNT_16MB 0x00000003
	33	# define NV04_PFB_BOOT_0_RAM_WIDTH_128 0x00000004
	34	# define NV04_PFB_BOOT_0_RAM_TYPE 0x00000028
	35	# define NV04_PFB_BOOT_0_RAM_TYPE_SGRAM_8MBIT 0x00000000
	36	# define NV04_PFB_BOOT_0_RAM_TYPE_SGRAM_16MBIT 0x00000008
	37	# define NV04_PFB_BOOT_0_RAM_TYPE_SGRAM_16MBIT_4BANK 0x00000010
	38	# define NV04_PFB_BOOT_0_RAM_TYPE_SDRAM_16MBIT 0x00000018
	39	# define NV04_PFB_BOOT_0_RAM_TYPE_SDRAM_64MBIT 0x00000020
	40	# define NV04_PFB_BOOT_0_RAM_TYPE_SDRAM_64MBITX16 0x00000028
	41	# define NV04_PFB_BOOT_0_UMA_ENABLE 0x00000100
	42	# define NV04_PFB_BOOT_0_UMA_SIZE 0x0000f000
	43	#define NV04_PFB_CFG0 0x00100200
	44
	45	struct nv04_fb_priv {
	46	struct nouveau_fb base;
	47	};
	48
	49	bool
	50	nv04_fb_memtype_valid(struct nouveau_fb *pfb, u32 tile_flags)
	51	{
	52	if (!(tile_flags & 0xff00))
	53	return true;
	54
	55	return false;
	56	}
	57
	58	static int
	59	nv04_fb_init(struct nouveau_object *object)
7ad2d31c	60	{
861d2107 BS	61	struct nv04_fb_priv priv = (void )object;
	62	int ret;
	63
	64	ret = nouveau_fb_init(&priv->base);
	65	if (ret)
	66	return ret;
	67
	68	/* This is what the DDX did for NV_ARCH_04, but a mmio-trace shows
	69	* nvidia reading PFB_CFG_0, then writing back its original value.
	70	* (which was 0x701114 in this case)
	71	*/
	72	nv_wr32(priv, NV04_PFB_CFG0, 0x1114);
	73	return 0;
	74	}
7ad2d31c	75
861d2107 BS	76	static int
	77	nv04_fb_ctor(struct nouveau_object parent, struct nouveau_object engine,
	78	struct nouveau_oclass oclass, void data, u32 size,
	79	struct nouveau_object **pobject)
	80	{
	81	struct nv04_fb_priv *priv;
	82	u32 boot0;
	83	int ret;
	84
	85	ret = nouveau_fb_create(parent, engine, oclass, &priv);
	86	*pobject = nv_object(priv);
	87	if (ret)
	88	return ret;
	89
	90	boot0 = nv_rd32(priv, NV04_PFB_BOOT_0);
7ad2d31c	91	if (boot0 & 0x00000100) {
861d2107 BS	92	priv->base.ram.size = ((boot0 >> 12) & 0xf) * 2 + 2;
861d2107 BS	93	priv->base.ram.size = 1024 1024;
7ad2d31c BS	94	} else {
	95	switch (boot0 & NV04_PFB_BOOT_0_RAM_AMOUNT) {
	96	case NV04_PFB_BOOT_0_RAM_AMOUNT_32MB:
861d2107	97	priv->base.ram.size = 32 * 1024 * 1024;
7ad2d31c BS	98	break;
7ad2d31c BS	99	case NV04_PFB_BOOT_0_RAM_AMOUNT_16MB:
861d2107	100	priv->base.ram.size = 16 * 1024 * 1024;
7ad2d31c BS	101	break;
7ad2d31c BS	102	case NV04_PFB_BOOT_0_RAM_AMOUNT_8MB:
861d2107	103	priv->base.ram.size = 8 * 1024 * 1024;
7ad2d31c BS	104	break;
7ad2d31c BS	105	case NV04_PFB_BOOT_0_RAM_AMOUNT_4MB:
861d2107	106	priv->base.ram.size = 4 * 1024 * 1024;
7ad2d31c BS	107	break;
	108	}
	109	}
	110
ddfd2da4	111	if ((boot0 & 0x00000038) <= 0x10)
861d2107	112	priv->base.ram.type = NV_MEM_TYPE_SGRAM;
ddfd2da4	113	else
861d2107	114	priv->base.ram.type = NV_MEM_TYPE_SDRAM;
ddfd2da4	115
6ee73861	116
861d2107 BS	117	priv->base.memtype_valid = nv04_fb_memtype_valid;
861d2107 BS	118	return nouveau_fb_created(&priv->base);
6ee73861 BS	119	}
6ee73861 BS	120
861d2107 BS	121	struct nouveau_oclass
	122	nv04_fb_oclass = {
	123	.handle = NV_SUBDEV(FB, 0x04),
	124	.ofuncs = &(struct nouveau_ofuncs) {
	125	.ctor = nv04_fb_ctor,
	126	.dtor = _nouveau_fb_dtor,
	127	.init = nv04_fb_init,
	128	.fini = _nouveau_fb_fini,
	129	},
	130	};