[mirror_ubuntu-bionic-kernel.git] / drivers / gpu / drm / nouveau / include / nvif / class.h

#ifndef __NVIF_CLASS_H__
#define __NVIF_CLASS_H__

/* these class numbers are made up by us, and not nvidia-assigned */
#define NVIF_CLASS_CLIENT                            /* if0000.h */ -0x00000000

#define NVIF_CLASS_CONTROL                           /* if0001.h */ -0x00000001

#define NVIF_CLASS_PERFMON                           /* if0002.h */ -0x00000002
#define NVIF_CLASS_PERFDOM                           /* if0003.h */ -0x00000003

#define NVIF_CLASS_SW_NV04                           /* if0004.h */ -0x00000004
#define NVIF_CLASS_SW_NV10                           /* if0005.h */ -0x00000005
#define NVIF_CLASS_SW_NV50                           /* if0005.h */ -0x00000006
#define NVIF_CLASS_SW_GF100                          /* if0005.h */ -0x00000007

#define NVIF_CLASS_VMM                               /* if000c.h */  0x8000000c
#define NVIF_CLASS_VMM_NV04                          /* if000d.h */  0x8000000d
#define NVIF_CLASS_VMM_NV50                          /* if500d.h */  0x8000500d
#define NVIF_CLASS_VMM_GF100                         /* if900d.h */  0x8000900d
#define NVIF_CLASS_VMM_GM200                         /* ifb00d.h */  0x8000b00d
#define NVIF_CLASS_VMM_GP100                         /* ifc00d.h */  0x8000c00d

/* the below match nvidia-assigned (either in hw, or sw) class numbers */
#define NV_NULL_CLASS                                                0x00000030

#define NV_DEVICE                                     /* cl0080.h */ 0x00000080

#define NV_DMA_FROM_MEMORY                            /* cl0002.h */ 0x00000002
#define NV_DMA_TO_MEMORY                              /* cl0002.h */ 0x00000003
#define NV_DMA_IN_MEMORY                              /* cl0002.h */ 0x0000003d

#define NV50_TWOD                                                    0x0000502d
#define FERMI_TWOD_A                                                 0x0000902d

#define NV50_MEMORY_TO_MEMORY_FORMAT                                 0x00005039
#define FERMI_MEMORY_TO_MEMORY_FORMAT_A                              0x00009039

#define KEPLER_INLINE_TO_MEMORY_A                                    0x0000a040
#define KEPLER_INLINE_TO_MEMORY_B                                    0x0000a140

#define NV04_DISP                                     /* cl0046.h */ 0x00000046

#define NV03_CHANNEL_DMA                              /* cl506b.h */ 0x0000006b
#define NV10_CHANNEL_DMA                              /* cl506b.h */ 0x0000006e
#define NV17_CHANNEL_DMA                              /* cl506b.h */ 0x0000176e
#define NV40_CHANNEL_DMA                              /* cl506b.h */ 0x0000406e
#define NV50_CHANNEL_DMA                              /* cl506e.h */ 0x0000506e
#define G82_CHANNEL_DMA                               /* cl826e.h */ 0x0000826e

#define NV50_CHANNEL_GPFIFO                           /* cl506f.h */ 0x0000506f
#define G82_CHANNEL_GPFIFO                            /* cl826f.h */ 0x0000826f
#define FERMI_CHANNEL_GPFIFO                          /* cl906f.h */ 0x0000906f
#define KEPLER_CHANNEL_GPFIFO_A                       /* cla06f.h */ 0x0000a06f
#define KEPLER_CHANNEL_GPFIFO_B                       /* cla06f.h */ 0x0000a16f
#define MAXWELL_CHANNEL_GPFIFO_A                      /* cla06f.h */ 0x0000b06f
#define PASCAL_CHANNEL_GPFIFO_A                       /* cla06f.h */ 0x0000c06f

#define NV50_DISP                                     /* cl5070.h */ 0x00005070
#define G82_DISP                                      /* cl5070.h */ 0x00008270
#define GT200_DISP                                    /* cl5070.h */ 0x00008370
#define GT214_DISP                                    /* cl5070.h */ 0x00008570
#define GT206_DISP                                    /* cl5070.h */ 0x00008870
#define GF110_DISP                                    /* cl5070.h */ 0x00009070
#define GK104_DISP                                    /* cl5070.h */ 0x00009170
#define GK110_DISP                                    /* cl5070.h */ 0x00009270
#define GM107_DISP                                    /* cl5070.h */ 0x00009470
#define GM200_DISP                                    /* cl5070.h */ 0x00009570
#define GP100_DISP                                    /* cl5070.h */ 0x00009770
#define GP102_DISP                                    /* cl5070.h */ 0x00009870

#define NV31_MPEG                                                    0x00003174
#define G82_MPEG                                                     0x00008274

#define NV74_VP2                                                     0x00007476

#define NV50_DISP_CURSOR                              /* cl507a.h */ 0x0000507a
#define G82_DISP_CURSOR                               /* cl507a.h */ 0x0000827a
#define GT214_DISP_CURSOR                             /* cl507a.h */ 0x0000857a
#define GF110_DISP_CURSOR                             /* cl507a.h */ 0x0000907a
#define GK104_DISP_CURSOR                             /* cl507a.h */ 0x0000917a

#define NV50_DISP_OVERLAY                             /* cl507b.h */ 0x0000507b
#define G82_DISP_OVERLAY                              /* cl507b.h */ 0x0000827b
#define GT214_DISP_OVERLAY                            /* cl507b.h */ 0x0000857b
#define GF110_DISP_OVERLAY                            /* cl507b.h */ 0x0000907b
#define GK104_DISP_OVERLAY                            /* cl507b.h */ 0x0000917b

#define NV50_DISP_BASE_CHANNEL_DMA                    /* cl507c.h */ 0x0000507c
#define G82_DISP_BASE_CHANNEL_DMA                     /* cl507c.h */ 0x0000827c
#define GT200_DISP_BASE_CHANNEL_DMA                   /* cl507c.h */ 0x0000837c
#define GT214_DISP_BASE_CHANNEL_DMA                   /* cl507c.h */ 0x0000857c
#define GF110_DISP_BASE_CHANNEL_DMA                   /* cl507c.h */ 0x0000907c
#define GK104_DISP_BASE_CHANNEL_DMA                   /* cl507c.h */ 0x0000917c
#define GK110_DISP_BASE_CHANNEL_DMA                   /* cl507c.h */ 0x0000927c

#define NV50_DISP_CORE_CHANNEL_DMA                    /* cl507d.h */ 0x0000507d
#define G82_DISP_CORE_CHANNEL_DMA                     /* cl507d.h */ 0x0000827d
#define GT200_DISP_CORE_CHANNEL_DMA                   /* cl507d.h */ 0x0000837d
#define GT214_DISP_CORE_CHANNEL_DMA                   /* cl507d.h */ 0x0000857d
#define GT206_DISP_CORE_CHANNEL_DMA                   /* cl507d.h */ 0x0000887d
#define GF110_DISP_CORE_CHANNEL_DMA                   /* cl507d.h */ 0x0000907d
#define GK104_DISP_CORE_CHANNEL_DMA                   /* cl507d.h */ 0x0000917d
#define GK110_DISP_CORE_CHANNEL_DMA                   /* cl507d.h */ 0x0000927d
#define GM107_DISP_CORE_CHANNEL_DMA                   /* cl507d.h */ 0x0000947d
#define GM200_DISP_CORE_CHANNEL_DMA                   /* cl507d.h */ 0x0000957d
#define GP100_DISP_CORE_CHANNEL_DMA                   /* cl507d.h */ 0x0000977d
#define GP102_DISP_CORE_CHANNEL_DMA                   /* cl507d.h */ 0x0000987d

#define NV50_DISP_OVERLAY_CHANNEL_DMA                 /* cl507e.h */ 0x0000507e
#define G82_DISP_OVERLAY_CHANNEL_DMA                  /* cl507e.h */ 0x0000827e
#define GT200_DISP_OVERLAY_CHANNEL_DMA                /* cl507e.h */ 0x0000837e
#define GT214_DISP_OVERLAY_CHANNEL_DMA                /* cl507e.h */ 0x0000857e
#define GF110_DISP_OVERLAY_CONTROL_DMA                /* cl507e.h */ 0x0000907e
#define GK104_DISP_OVERLAY_CONTROL_DMA                /* cl507e.h */ 0x0000917e

#define NV50_TESLA                                                   0x00005097
#define G82_TESLA                                                    0x00008297
#define GT200_TESLA                                                  0x00008397
#define GT214_TESLA                                                  0x00008597
#define GT21A_TESLA                                                  0x00008697

#define FERMI_A                                       /* cl9097.h */ 0x00009097
#define FERMI_B                                       /* cl9097.h */ 0x00009197
#define FERMI_C                                       /* cl9097.h */ 0x00009297

#define KEPLER_A                                      /* cl9097.h */ 0x0000a097
#define KEPLER_B                                      /* cl9097.h */ 0x0000a197
#define KEPLER_C                                      /* cl9097.h */ 0x0000a297

#define MAXWELL_A                                     /* cl9097.h */ 0x0000b097
#define MAXWELL_B                                     /* cl9097.h */ 0x0000b197

#define PASCAL_A                                      /* cl9097.h */ 0x0000c097
#define PASCAL_B                                      /* cl9097.h */ 0x0000c197

#define NV74_BSP                                                     0x000074b0

#define GT212_MSVLD                                                  0x000085b1
#define IGT21A_MSVLD                                                 0x000086b1
#define G98_MSVLD                                                    0x000088b1
#define GF100_MSVLD                                                  0x000090b1
#define GK104_MSVLD                                                  0x000095b1

#define GT212_MSPDEC                                                 0x000085b2
#define G98_MSPDEC                                                   0x000088b2
#define GF100_MSPDEC                                                 0x000090b2
#define GK104_MSPDEC                                                 0x000095b2

#define GT212_MSPPP                                                  0x000085b3
#define G98_MSPPP                                                    0x000088b3
#define GF100_MSPPP                                                  0x000090b3

#define G98_SEC                                                      0x000088b4

#define GT212_DMA                                                    0x000085b5
#define FERMI_DMA                                                    0x000090b5
#define KEPLER_DMA_COPY_A                                            0x0000a0b5
#define MAXWELL_DMA_COPY_A                                           0x0000b0b5
#define PASCAL_DMA_COPY_A                                            0x0000c0b5
#define PASCAL_DMA_COPY_B                                            0x0000c1b5

#define FERMI_DECOMPRESS                                             0x000090b8

#define NV50_COMPUTE                                                 0x000050c0
#define GT214_COMPUTE                                                0x000085c0
#define FERMI_COMPUTE_A                                              0x000090c0
#define FERMI_COMPUTE_B                                              0x000091c0
#define KEPLER_COMPUTE_A                                             0x0000a0c0
#define KEPLER_COMPUTE_B                                             0x0000a1c0
#define MAXWELL_COMPUTE_A                                            0x0000b0c0
#define MAXWELL_COMPUTE_B                                            0x0000b1c0
#define PASCAL_COMPUTE_A                                             0x0000c0c0
#define PASCAL_COMPUTE_B                                             0x0000c1c0

#define NV74_CIPHER                                                  0x000074c1
#endif
Commit	Line	Data
d01c3092 BS	1	#ifndef __NVIF_CLASS_H__
	2	#define __NVIF_CLASS_H__
	3
08f7633c	4	/* these class numbers are made up by us, and not nvidia-assigned */
03295eab BS	5	#define NVIF_CLASS_CLIENT /* if0000.h */ -0x00000000
	6
	7	#define NVIF_CLASS_CONTROL /* if0001.h */ -0x00000001
	8
	9	#define NVIF_CLASS_PERFMON /* if0002.h */ -0x00000002
	10	#define NVIF_CLASS_PERFDOM /* if0003.h */ -0x00000003
	11
	12	#define NVIF_CLASS_SW_NV04 /* if0004.h */ -0x00000004
	13	#define NVIF_CLASS_SW_NV10 /* if0005.h */ -0x00000005
	14	#define NVIF_CLASS_SW_NV50 /* if0005.h */ -0x00000006
	15	#define NVIF_CLASS_SW_GF100 /* if0005.h */ -0x00000007
d01c3092	16
5b17f362 BS	17	#define NVIF_CLASS_VMM /* if000c.h */ 0x8000000c
5b17f362 BS	18	#define NVIF_CLASS_VMM_NV04 /* if000d.h */ 0x8000000d
9f6219fd	19	#define NVIF_CLASS_VMM_NV50 /* if500d.h */ 0x8000500d
540a1dde	20	#define NVIF_CLASS_VMM_GF100 /* if900d.h */ 0x8000900d
5f300fed	21	#define NVIF_CLASS_VMM_GM200 /* ifb00d.h */ 0x8000b00d
8e39abff	22	#define NVIF_CLASS_VMM_GP100 /* ifc00d.h */ 0x8000c00d
806a7335	23
d01c3092	24	/* the below match nvidia-assigned (either in hw, or sw) class numbers */
0233a9f4 BS	25	#define NV_NULL_CLASS 0x00000030
0233a9f4 BS	26
923bc416	27	#define NV_DEVICE /* cl0080.h */ 0x00000080
d01c3092	28
845f2725 BS	29	#define NV_DMA_FROM_MEMORY /* cl0002.h */ 0x00000002
	30	#define NV_DMA_TO_MEMORY /* cl0002.h */ 0x00000003
	31	#define NV_DMA_IN_MEMORY /* cl0002.h */ 0x0000003d
4acfd707	32
0233a9f4	33	#define NV50_TWOD 0x0000502d
3740c825 BS	34	#define FERMI_TWOD_A 0x0000902d
3740c825 BS	35
0233a9f4	36	#define NV50_MEMORY_TO_MEMORY_FORMAT 0x00005039
9ee971a0	37	#define FERMI_MEMORY_TO_MEMORY_FORMAT_A 0x00009039
3740c825 BS	38
	39	#define KEPLER_INLINE_TO_MEMORY_A 0x0000a040
	40	#define KEPLER_INLINE_TO_MEMORY_B 0x0000a140
	41
7568b106	42	#define NV04_DISP /* cl0046.h */ 0x00000046
648d4dfd	43
8ed1730c BS	44	#define NV03_CHANNEL_DMA /* cl506b.h */ 0x0000006b
	45	#define NV10_CHANNEL_DMA /* cl506b.h */ 0x0000006e
	46	#define NV17_CHANNEL_DMA /* cl506b.h */ 0x0000176e
	47	#define NV40_CHANNEL_DMA /* cl506b.h */ 0x0000406e
	48	#define NV50_CHANNEL_DMA /* cl506e.h */ 0x0000506e
	49	#define G82_CHANNEL_DMA /* cl826e.h */ 0x0000826e
	50
	51	#define NV50_CHANNEL_GPFIFO /* cl506f.h */ 0x0000506f
	52	#define G82_CHANNEL_GPFIFO /* cl826f.h */ 0x0000826f
	53	#define FERMI_CHANNEL_GPFIFO /* cl906f.h */ 0x0000906f
	54	#define KEPLER_CHANNEL_GPFIFO_A /* cla06f.h */ 0x0000a06f
63f8c9b7	55	#define KEPLER_CHANNEL_GPFIFO_B /* cla06f.h */ 0x0000a16f
8ed1730c	56	#define MAXWELL_CHANNEL_GPFIFO_A /* cla06f.h */ 0x0000b06f
e8ff9794	57	#define PASCAL_CHANNEL_GPFIFO_A /* cla06f.h */ 0x0000c06f
bbf8906b	58
7568b106 BS	59	#define NV50_DISP /* cl5070.h */ 0x00005070
	60	#define G82_DISP /* cl5070.h */ 0x00008270
	61	#define GT200_DISP /* cl5070.h */ 0x00008370
	62	#define GT214_DISP /* cl5070.h */ 0x00008570
	63	#define GT206_DISP /* cl5070.h */ 0x00008870
	64	#define GF110_DISP /* cl5070.h */ 0x00009070
	65	#define GK104_DISP /* cl5070.h */ 0x00009170
	66	#define GK110_DISP /* cl5070.h */ 0x00009270
	67	#define GM107_DISP /* cl5070.h */ 0x00009470
db1eb528	68	#define GM200_DISP /* cl5070.h */ 0x00009570
f9d5cbb3	69	#define GP100_DISP /* cl5070.h */ 0x00009770
ed828666	70	#define GP102_DISP /* cl5070.h */ 0x00009870
648d4dfd	71
218f978d BS	72	#define NV31_MPEG 0x00003174
	73	#define G82_MPEG 0x00008274
	74
c79a191b BS	75	#define NV74_VP2 0x00007476
c79a191b BS	76
7568b106 BS	77	#define NV50_DISP_CURSOR /* cl507a.h */ 0x0000507a
	78	#define G82_DISP_CURSOR /* cl507a.h */ 0x0000827a
	79	#define GT214_DISP_CURSOR /* cl507a.h */ 0x0000857a
	80	#define GF110_DISP_CURSOR /* cl507a.h */ 0x0000907a
	81	#define GK104_DISP_CURSOR /* cl507a.h */ 0x0000917a
	82
	83	#define NV50_DISP_OVERLAY /* cl507b.h */ 0x0000507b
	84	#define G82_DISP_OVERLAY /* cl507b.h */ 0x0000827b
	85	#define GT214_DISP_OVERLAY /* cl507b.h */ 0x0000857b
	86	#define GF110_DISP_OVERLAY /* cl507b.h */ 0x0000907b
	87	#define GK104_DISP_OVERLAY /* cl507b.h */ 0x0000917b
	88
	89	#define NV50_DISP_BASE_CHANNEL_DMA /* cl507c.h */ 0x0000507c
	90	#define G82_DISP_BASE_CHANNEL_DMA /* cl507c.h */ 0x0000827c
	91	#define GT200_DISP_BASE_CHANNEL_DMA /* cl507c.h */ 0x0000837c
	92	#define GT214_DISP_BASE_CHANNEL_DMA /* cl507c.h */ 0x0000857c
	93	#define GF110_DISP_BASE_CHANNEL_DMA /* cl507c.h */ 0x0000907c
	94	#define GK104_DISP_BASE_CHANNEL_DMA /* cl507c.h */ 0x0000917c
	95	#define GK110_DISP_BASE_CHANNEL_DMA /* cl507c.h */ 0x0000927c
	96
	97	#define NV50_DISP_CORE_CHANNEL_DMA /* cl507d.h */ 0x0000507d
	98	#define G82_DISP_CORE_CHANNEL_DMA /* cl507d.h */ 0x0000827d
	99	#define GT200_DISP_CORE_CHANNEL_DMA /* cl507d.h */ 0x0000837d
	100	#define GT214_DISP_CORE_CHANNEL_DMA /* cl507d.h */ 0x0000857d
	101	#define GT206_DISP_CORE_CHANNEL_DMA /* cl507d.h */ 0x0000887d
	102	#define GF110_DISP_CORE_CHANNEL_DMA /* cl507d.h */ 0x0000907d
	103	#define GK104_DISP_CORE_CHANNEL_DMA /* cl507d.h */ 0x0000917d
	104	#define GK110_DISP_CORE_CHANNEL_DMA /* cl507d.h */ 0x0000927d
	105	#define GM107_DISP_CORE_CHANNEL_DMA /* cl507d.h */ 0x0000947d
db1eb528	106	#define GM200_DISP_CORE_CHANNEL_DMA /* cl507d.h */ 0x0000957d
f9d5cbb3	107	#define GP100_DISP_CORE_CHANNEL_DMA /* cl507d.h */ 0x0000977d
ed828666	108	#define GP102_DISP_CORE_CHANNEL_DMA /* cl507d.h */ 0x0000987d
7568b106 BS	109
	110	#define NV50_DISP_OVERLAY_CHANNEL_DMA /* cl507e.h */ 0x0000507e
	111	#define G82_DISP_OVERLAY_CHANNEL_DMA /* cl507e.h */ 0x0000827e
	112	#define GT200_DISP_OVERLAY_CHANNEL_DMA /* cl507e.h */ 0x0000837e
	113	#define GT214_DISP_OVERLAY_CHANNEL_DMA /* cl507e.h */ 0x0000857e
	114	#define GF110_DISP_OVERLAY_CONTROL_DMA /* cl507e.h */ 0x0000907e
	115	#define GK104_DISP_OVERLAY_CONTROL_DMA /* cl507e.h */ 0x0000917e
648d4dfd	116
0233a9f4 BS	117	#define NV50_TESLA 0x00005097
	118	#define G82_TESLA 0x00008297
	119	#define GT200_TESLA 0x00008397
	120	#define GT214_TESLA 0x00008597
	121	#define GT21A_TESLA 0x00008697
	122
53a6df77 BS	123	#define FERMI_A /* cl9097.h */ 0x00009097
	124	#define FERMI_B /* cl9097.h */ 0x00009197
	125	#define FERMI_C /* cl9097.h */ 0x00009297
ac9738bb	126
53a6df77 BS	127	#define KEPLER_A /* cl9097.h */ 0x0000a097
	128	#define KEPLER_B /* cl9097.h */ 0x0000a197
	129	#define KEPLER_C /* cl9097.h */ 0x0000a297
ac9738bb	130
53a6df77 BS	131	#define MAXWELL_A /* cl9097.h */ 0x0000b097
53a6df77 BS	132	#define MAXWELL_B /* cl9097.h */ 0x0000b197
ac9738bb	133
52fa0866	134	#define PASCAL_A /* cl9097.h */ 0x0000c097
424321be	135	#define PASCAL_B /* cl9097.h */ 0x0000c197
52fa0866	136
c79a191b BS	137	#define NV74_BSP 0x000074b0
c79a191b BS	138
9d498e0f BS	139	#define GT212_MSVLD 0x000085b1
	140	#define IGT21A_MSVLD 0x000086b1
	141	#define G98_MSVLD 0x000088b1
	142	#define GF100_MSVLD 0x000090b1
	143	#define GK104_MSVLD 0x000095b1
	144
	145	#define GT212_MSPDEC 0x000085b2
	146	#define G98_MSPDEC 0x000088b2
	147	#define GF100_MSPDEC 0x000090b2
	148	#define GK104_MSPDEC 0x000095b2
	149
	150	#define GT212_MSPPP 0x000085b3
	151	#define G98_MSPPP 0x000088b3
	152	#define GF100_MSPPP 0x000090b3
	153
	154	#define G98_SEC 0x000088b4
	155
	156	#define GT212_DMA 0x000085b5
	157	#define FERMI_DMA 0x000090b5
e5ff1127 BS	158	#define KEPLER_DMA_COPY_A 0x0000a0b5
e5ff1127 BS	159	#define MAXWELL_DMA_COPY_A 0x0000b0b5
8e7e1586	160	#define PASCAL_DMA_COPY_A 0x0000c0b5
146cfe24	161	#define PASCAL_DMA_COPY_B 0x0000c1b5
9d498e0f BS	162
	163	#define FERMI_DECOMPRESS 0x000090b8
	164
0233a9f4 BS	165	#define NV50_COMPUTE 0x000050c0
0233a9f4 BS	166	#define GT214_COMPUTE 0x000085c0
d6bd3803 BS	167	#define FERMI_COMPUTE_A 0x000090c0
d6bd3803 BS	168	#define FERMI_COMPUTE_B 0x000091c0
d6bd3803 BS	169	#define KEPLER_COMPUTE_A 0x0000a0c0
d6bd3803 BS	170	#define KEPLER_COMPUTE_B 0x0000a1c0
d6bd3803	171	#define MAXWELL_COMPUTE_A 0x0000b0c0
3fed3ea9	172	#define MAXWELL_COMPUTE_B 0x0000b1c0
52fa0866	173	#define PASCAL_COMPUTE_A 0x0000c0c0
424321be	174	#define PASCAL_COMPUTE_B 0x0000c1c0
d6bd3803	175
b3c98150	176	#define NV74_CIPHER 0x000074c1
d01c3092	177	#endif