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d01c3092 BS |
1 | #ifndef __NVIF_CLASS_H__ |
2 | #define __NVIF_CLASS_H__ | |
3 | ||
08f7633c | 4 | /* these class numbers are made up by us, and not nvidia-assigned */ |
03295eab BS |
5 | #define NVIF_CLASS_CLIENT /* if0000.h */ -0x00000000 |
6 | ||
7 | #define NVIF_CLASS_CONTROL /* if0001.h */ -0x00000001 | |
8 | ||
9 | #define NVIF_CLASS_PERFMON /* if0002.h */ -0x00000002 | |
10 | #define NVIF_CLASS_PERFDOM /* if0003.h */ -0x00000003 | |
11 | ||
12 | #define NVIF_CLASS_SW_NV04 /* if0004.h */ -0x00000004 | |
13 | #define NVIF_CLASS_SW_NV10 /* if0005.h */ -0x00000005 | |
14 | #define NVIF_CLASS_SW_NV50 /* if0005.h */ -0x00000006 | |
15 | #define NVIF_CLASS_SW_GF100 /* if0005.h */ -0x00000007 | |
d01c3092 | 16 | |
5b17f362 BS |
17 | #define NVIF_CLASS_VMM /* if000c.h */ 0x8000000c |
18 | #define NVIF_CLASS_VMM_NV04 /* if000d.h */ 0x8000000d | |
9f6219fd | 19 | #define NVIF_CLASS_VMM_NV50 /* if500d.h */ 0x8000500d |
540a1dde | 20 | #define NVIF_CLASS_VMM_GF100 /* if900d.h */ 0x8000900d |
806a7335 | 21 | |
d01c3092 | 22 | /* the below match nvidia-assigned (either in hw, or sw) class numbers */ |
0233a9f4 BS |
23 | #define NV_NULL_CLASS 0x00000030 |
24 | ||
923bc416 | 25 | #define NV_DEVICE /* cl0080.h */ 0x00000080 |
d01c3092 | 26 | |
845f2725 BS |
27 | #define NV_DMA_FROM_MEMORY /* cl0002.h */ 0x00000002 |
28 | #define NV_DMA_TO_MEMORY /* cl0002.h */ 0x00000003 | |
29 | #define NV_DMA_IN_MEMORY /* cl0002.h */ 0x0000003d | |
4acfd707 | 30 | |
0233a9f4 | 31 | #define NV50_TWOD 0x0000502d |
3740c825 BS |
32 | #define FERMI_TWOD_A 0x0000902d |
33 | ||
0233a9f4 | 34 | #define NV50_MEMORY_TO_MEMORY_FORMAT 0x00005039 |
9ee971a0 | 35 | #define FERMI_MEMORY_TO_MEMORY_FORMAT_A 0x00009039 |
3740c825 BS |
36 | |
37 | #define KEPLER_INLINE_TO_MEMORY_A 0x0000a040 | |
38 | #define KEPLER_INLINE_TO_MEMORY_B 0x0000a140 | |
39 | ||
7568b106 | 40 | #define NV04_DISP /* cl0046.h */ 0x00000046 |
648d4dfd | 41 | |
8ed1730c BS |
42 | #define NV03_CHANNEL_DMA /* cl506b.h */ 0x0000006b |
43 | #define NV10_CHANNEL_DMA /* cl506b.h */ 0x0000006e | |
44 | #define NV17_CHANNEL_DMA /* cl506b.h */ 0x0000176e | |
45 | #define NV40_CHANNEL_DMA /* cl506b.h */ 0x0000406e | |
46 | #define NV50_CHANNEL_DMA /* cl506e.h */ 0x0000506e | |
47 | #define G82_CHANNEL_DMA /* cl826e.h */ 0x0000826e | |
48 | ||
49 | #define NV50_CHANNEL_GPFIFO /* cl506f.h */ 0x0000506f | |
50 | #define G82_CHANNEL_GPFIFO /* cl826f.h */ 0x0000826f | |
51 | #define FERMI_CHANNEL_GPFIFO /* cl906f.h */ 0x0000906f | |
52 | #define KEPLER_CHANNEL_GPFIFO_A /* cla06f.h */ 0x0000a06f | |
63f8c9b7 | 53 | #define KEPLER_CHANNEL_GPFIFO_B /* cla06f.h */ 0x0000a16f |
8ed1730c | 54 | #define MAXWELL_CHANNEL_GPFIFO_A /* cla06f.h */ 0x0000b06f |
e8ff9794 | 55 | #define PASCAL_CHANNEL_GPFIFO_A /* cla06f.h */ 0x0000c06f |
bbf8906b | 56 | |
7568b106 BS |
57 | #define NV50_DISP /* cl5070.h */ 0x00005070 |
58 | #define G82_DISP /* cl5070.h */ 0x00008270 | |
59 | #define GT200_DISP /* cl5070.h */ 0x00008370 | |
60 | #define GT214_DISP /* cl5070.h */ 0x00008570 | |
61 | #define GT206_DISP /* cl5070.h */ 0x00008870 | |
62 | #define GF110_DISP /* cl5070.h */ 0x00009070 | |
63 | #define GK104_DISP /* cl5070.h */ 0x00009170 | |
64 | #define GK110_DISP /* cl5070.h */ 0x00009270 | |
65 | #define GM107_DISP /* cl5070.h */ 0x00009470 | |
db1eb528 | 66 | #define GM200_DISP /* cl5070.h */ 0x00009570 |
f9d5cbb3 | 67 | #define GP100_DISP /* cl5070.h */ 0x00009770 |
ed828666 | 68 | #define GP102_DISP /* cl5070.h */ 0x00009870 |
648d4dfd | 69 | |
218f978d BS |
70 | #define NV31_MPEG 0x00003174 |
71 | #define G82_MPEG 0x00008274 | |
72 | ||
c79a191b BS |
73 | #define NV74_VP2 0x00007476 |
74 | ||
7568b106 BS |
75 | #define NV50_DISP_CURSOR /* cl507a.h */ 0x0000507a |
76 | #define G82_DISP_CURSOR /* cl507a.h */ 0x0000827a | |
77 | #define GT214_DISP_CURSOR /* cl507a.h */ 0x0000857a | |
78 | #define GF110_DISP_CURSOR /* cl507a.h */ 0x0000907a | |
79 | #define GK104_DISP_CURSOR /* cl507a.h */ 0x0000917a | |
80 | ||
81 | #define NV50_DISP_OVERLAY /* cl507b.h */ 0x0000507b | |
82 | #define G82_DISP_OVERLAY /* cl507b.h */ 0x0000827b | |
83 | #define GT214_DISP_OVERLAY /* cl507b.h */ 0x0000857b | |
84 | #define GF110_DISP_OVERLAY /* cl507b.h */ 0x0000907b | |
85 | #define GK104_DISP_OVERLAY /* cl507b.h */ 0x0000917b | |
86 | ||
87 | #define NV50_DISP_BASE_CHANNEL_DMA /* cl507c.h */ 0x0000507c | |
88 | #define G82_DISP_BASE_CHANNEL_DMA /* cl507c.h */ 0x0000827c | |
89 | #define GT200_DISP_BASE_CHANNEL_DMA /* cl507c.h */ 0x0000837c | |
90 | #define GT214_DISP_BASE_CHANNEL_DMA /* cl507c.h */ 0x0000857c | |
91 | #define GF110_DISP_BASE_CHANNEL_DMA /* cl507c.h */ 0x0000907c | |
92 | #define GK104_DISP_BASE_CHANNEL_DMA /* cl507c.h */ 0x0000917c | |
93 | #define GK110_DISP_BASE_CHANNEL_DMA /* cl507c.h */ 0x0000927c | |
94 | ||
95 | #define NV50_DISP_CORE_CHANNEL_DMA /* cl507d.h */ 0x0000507d | |
96 | #define G82_DISP_CORE_CHANNEL_DMA /* cl507d.h */ 0x0000827d | |
97 | #define GT200_DISP_CORE_CHANNEL_DMA /* cl507d.h */ 0x0000837d | |
98 | #define GT214_DISP_CORE_CHANNEL_DMA /* cl507d.h */ 0x0000857d | |
99 | #define GT206_DISP_CORE_CHANNEL_DMA /* cl507d.h */ 0x0000887d | |
100 | #define GF110_DISP_CORE_CHANNEL_DMA /* cl507d.h */ 0x0000907d | |
101 | #define GK104_DISP_CORE_CHANNEL_DMA /* cl507d.h */ 0x0000917d | |
102 | #define GK110_DISP_CORE_CHANNEL_DMA /* cl507d.h */ 0x0000927d | |
103 | #define GM107_DISP_CORE_CHANNEL_DMA /* cl507d.h */ 0x0000947d | |
db1eb528 | 104 | #define GM200_DISP_CORE_CHANNEL_DMA /* cl507d.h */ 0x0000957d |
f9d5cbb3 | 105 | #define GP100_DISP_CORE_CHANNEL_DMA /* cl507d.h */ 0x0000977d |
ed828666 | 106 | #define GP102_DISP_CORE_CHANNEL_DMA /* cl507d.h */ 0x0000987d |
7568b106 BS |
107 | |
108 | #define NV50_DISP_OVERLAY_CHANNEL_DMA /* cl507e.h */ 0x0000507e | |
109 | #define G82_DISP_OVERLAY_CHANNEL_DMA /* cl507e.h */ 0x0000827e | |
110 | #define GT200_DISP_OVERLAY_CHANNEL_DMA /* cl507e.h */ 0x0000837e | |
111 | #define GT214_DISP_OVERLAY_CHANNEL_DMA /* cl507e.h */ 0x0000857e | |
112 | #define GF110_DISP_OVERLAY_CONTROL_DMA /* cl507e.h */ 0x0000907e | |
113 | #define GK104_DISP_OVERLAY_CONTROL_DMA /* cl507e.h */ 0x0000917e | |
648d4dfd | 114 | |
0233a9f4 BS |
115 | #define NV50_TESLA 0x00005097 |
116 | #define G82_TESLA 0x00008297 | |
117 | #define GT200_TESLA 0x00008397 | |
118 | #define GT214_TESLA 0x00008597 | |
119 | #define GT21A_TESLA 0x00008697 | |
120 | ||
53a6df77 BS |
121 | #define FERMI_A /* cl9097.h */ 0x00009097 |
122 | #define FERMI_B /* cl9097.h */ 0x00009197 | |
123 | #define FERMI_C /* cl9097.h */ 0x00009297 | |
ac9738bb | 124 | |
53a6df77 BS |
125 | #define KEPLER_A /* cl9097.h */ 0x0000a097 |
126 | #define KEPLER_B /* cl9097.h */ 0x0000a197 | |
127 | #define KEPLER_C /* cl9097.h */ 0x0000a297 | |
ac9738bb | 128 | |
53a6df77 BS |
129 | #define MAXWELL_A /* cl9097.h */ 0x0000b097 |
130 | #define MAXWELL_B /* cl9097.h */ 0x0000b197 | |
ac9738bb | 131 | |
52fa0866 | 132 | #define PASCAL_A /* cl9097.h */ 0x0000c097 |
424321be | 133 | #define PASCAL_B /* cl9097.h */ 0x0000c197 |
52fa0866 | 134 | |
c79a191b BS |
135 | #define NV74_BSP 0x000074b0 |
136 | ||
9d498e0f BS |
137 | #define GT212_MSVLD 0x000085b1 |
138 | #define IGT21A_MSVLD 0x000086b1 | |
139 | #define G98_MSVLD 0x000088b1 | |
140 | #define GF100_MSVLD 0x000090b1 | |
141 | #define GK104_MSVLD 0x000095b1 | |
142 | ||
143 | #define GT212_MSPDEC 0x000085b2 | |
144 | #define G98_MSPDEC 0x000088b2 | |
145 | #define GF100_MSPDEC 0x000090b2 | |
146 | #define GK104_MSPDEC 0x000095b2 | |
147 | ||
148 | #define GT212_MSPPP 0x000085b3 | |
149 | #define G98_MSPPP 0x000088b3 | |
150 | #define GF100_MSPPP 0x000090b3 | |
151 | ||
152 | #define G98_SEC 0x000088b4 | |
153 | ||
154 | #define GT212_DMA 0x000085b5 | |
155 | #define FERMI_DMA 0x000090b5 | |
e5ff1127 BS |
156 | #define KEPLER_DMA_COPY_A 0x0000a0b5 |
157 | #define MAXWELL_DMA_COPY_A 0x0000b0b5 | |
8e7e1586 | 158 | #define PASCAL_DMA_COPY_A 0x0000c0b5 |
146cfe24 | 159 | #define PASCAL_DMA_COPY_B 0x0000c1b5 |
9d498e0f BS |
160 | |
161 | #define FERMI_DECOMPRESS 0x000090b8 | |
162 | ||
0233a9f4 BS |
163 | #define NV50_COMPUTE 0x000050c0 |
164 | #define GT214_COMPUTE 0x000085c0 | |
d6bd3803 BS |
165 | #define FERMI_COMPUTE_A 0x000090c0 |
166 | #define FERMI_COMPUTE_B 0x000091c0 | |
d6bd3803 BS |
167 | #define KEPLER_COMPUTE_A 0x0000a0c0 |
168 | #define KEPLER_COMPUTE_B 0x0000a1c0 | |
d6bd3803 | 169 | #define MAXWELL_COMPUTE_A 0x0000b0c0 |
3fed3ea9 | 170 | #define MAXWELL_COMPUTE_B 0x0000b1c0 |
52fa0866 | 171 | #define PASCAL_COMPUTE_A 0x0000c0c0 |
424321be | 172 | #define PASCAL_COMPUTE_B 0x0000c1c0 |
d6bd3803 | 173 | |
b3c98150 | 174 | #define NV74_CIPHER 0x000074c1 |
d01c3092 | 175 | #endif |