[mirror_ubuntu-bionic-kernel.git] / drivers / gpu / drm / nouveau / include / nvif / class.h

#ifndef __NVIF_CLASS_H__
#define __NVIF_CLASS_H__

/*******************************************************************************
 * class identifiers
 ******************************************************************************/

/* the below match nvidia-assigned (either in hw, or sw) class numbers */
#define NV_DEVICE                                                    0x00000080

#define NV_DMA_FROM_MEMORY                                           0x00000002
#define NV_DMA_TO_MEMORY                                             0x00000003
#define NV_DMA_IN_MEMORY                                             0x0000003d

#define FERMI_TWOD_A                                                 0x0000902d

#define FERMI_MEMORY_TO_MEMORY_FORMAT_A                              0x00009039

#define KEPLER_INLINE_TO_MEMORY_A                                    0x0000a040
#define KEPLER_INLINE_TO_MEMORY_B                                    0x0000a140

#define NV04_DISP                                                    0x00000046

#define NV03_CHANNEL_DMA                                             0x0000006b
#define NV10_CHANNEL_DMA                                             0x0000006e
#define NV17_CHANNEL_DMA                                             0x0000176e
#define NV40_CHANNEL_DMA                                             0x0000406e
#define NV50_CHANNEL_DMA                                             0x0000506e
#define G82_CHANNEL_DMA                                              0x0000826e

#define NV50_CHANNEL_GPFIFO                                          0x0000506f
#define G82_CHANNEL_GPFIFO                                           0x0000826f
#define FERMI_CHANNEL_GPFIFO                                         0x0000906f
#define KEPLER_CHANNEL_GPFIFO_A                                      0x0000a06f
#define MAXWELL_CHANNEL_GPFIFO_A                                     0x0000b06f

#define NV50_DISP                                                    0x00005070
#define G82_DISP                                                     0x00008270
#define GT200_DISP                                                   0x00008370
#define GT214_DISP                                                   0x00008570
#define GT206_DISP                                                   0x00008870
#define GF110_DISP                                                   0x00009070
#define GK104_DISP                                                   0x00009170
#define GK110_DISP                                                   0x00009270
#define GM107_DISP                                                   0x00009470
#define GM204_DISP                                                   0x00009570

#define NV50_DISP_CURSOR                                             0x0000507a
#define G82_DISP_CURSOR                                              0x0000827a
#define GT214_DISP_CURSOR                                            0x0000857a
#define GF110_DISP_CURSOR                                            0x0000907a
#define GK104_DISP_CURSOR                                            0x0000917a

#define NV50_DISP_OVERLAY                                            0x0000507b
#define G82_DISP_OVERLAY                                             0x0000827b
#define GT214_DISP_OVERLAY                                           0x0000857b
#define GF110_DISP_OVERLAY                                           0x0000907b
#define GK104_DISP_OVERLAY                                           0x0000917b

#define NV50_DISP_BASE_CHANNEL_DMA                                   0x0000507c
#define G82_DISP_BASE_CHANNEL_DMA                                    0x0000827c
#define GT200_DISP_BASE_CHANNEL_DMA                                  0x0000837c
#define GT214_DISP_BASE_CHANNEL_DMA                                  0x0000857c
#define GF110_DISP_BASE_CHANNEL_DMA                                  0x0000907c
#define GK104_DISP_BASE_CHANNEL_DMA                                  0x0000917c
#define GK110_DISP_BASE_CHANNEL_DMA                                  0x0000927c

#define NV50_DISP_CORE_CHANNEL_DMA                                   0x0000507d
#define G82_DISP_CORE_CHANNEL_DMA                                    0x0000827d
#define GT200_DISP_CORE_CHANNEL_DMA                                  0x0000837d
#define GT214_DISP_CORE_CHANNEL_DMA                                  0x0000857d
#define GT206_DISP_CORE_CHANNEL_DMA                                  0x0000887d
#define GF110_DISP_CORE_CHANNEL_DMA                                  0x0000907d
#define GK104_DISP_CORE_CHANNEL_DMA                                  0x0000917d
#define GK110_DISP_CORE_CHANNEL_DMA                                  0x0000927d
#define GM107_DISP_CORE_CHANNEL_DMA                                  0x0000947d
#define GM204_DISP_CORE_CHANNEL_DMA                                  0x0000957d

#define NV50_DISP_OVERLAY_CHANNEL_DMA                                0x0000507e
#define G82_DISP_OVERLAY_CHANNEL_DMA                                 0x0000827e
#define GT200_DISP_OVERLAY_CHANNEL_DMA                               0x0000837e
#define GT214_DISP_OVERLAY_CHANNEL_DMA                               0x0000857e
#define GF110_DISP_OVERLAY_CONTROL_DMA                               0x0000907e
#define GK104_DISP_OVERLAY_CONTROL_DMA                               0x0000917e

#define FERMI_A                                                      0x00009097
#define FERMI_B                                                      0x00009197
#define FERMI_C                                                      0x00009297

#define KEPLER_A                                                     0x0000a097
#define KEPLER_B                                                     0x0000a197
#define KEPLER_C                                                     0x0000a297

#define MAXWELL_A                                                    0x0000b097
#define MAXWELL_B                                                    0x0000b197

#define FERMI_COMPUTE_A                                              0x000090c0
#define FERMI_COMPUTE_B                                              0x000091c0

#define KEPLER_COMPUTE_A                                             0x0000a0c0
#define KEPLER_COMPUTE_B                                             0x0000a1c0

#define MAXWELL_COMPUTE_A                                            0x0000b0c0
#define MAXWELL_COMPUTE_B                                            0x0000b1c0


/*******************************************************************************
 * client
 ******************************************************************************/

#define NV_CLIENT_DEVLIST                                                  0x00

struct nv_client_devlist_v0 {
	__u8  version;
	__u8  count;
	__u8  pad02[6];
	__u64 device[];
};


/*******************************************************************************
 * device
 ******************************************************************************/

struct nv_device_v0 {
	__u8  version;
	__u8  pad01[7];
	__u64 device;	/* device identifier, ~0 for client default */
#define NV_DEVICE_V0_DISABLE_IDENTIFY                     0x0000000000000001ULL
#define NV_DEVICE_V0_DISABLE_MMIO                         0x0000000000000002ULL
#define NV_DEVICE_V0_DISABLE_VBIOS                        0x0000000000000004ULL
#define NV_DEVICE_V0_DISABLE_CORE                         0x0000000000000008ULL
#define NV_DEVICE_V0_DISABLE_DISP                         0x0000000000010000ULL
#define NV_DEVICE_V0_DISABLE_FIFO                         0x0000000000020000ULL
#define NV_DEVICE_V0_DISABLE_GR                           0x0000000100000000ULL
#define NV_DEVICE_V0_DISABLE_MPEG                         0x0000000200000000ULL
#define NV_DEVICE_V0_DISABLE_ME                           0x0000000400000000ULL
#define NV_DEVICE_V0_DISABLE_VP                           0x0000000800000000ULL
#define NV_DEVICE_V0_DISABLE_CIPHER                       0x0000001000000000ULL
#define NV_DEVICE_V0_DISABLE_BSP                          0x0000002000000000ULL
#define NV_DEVICE_V0_DISABLE_MSPPP                        0x0000004000000000ULL
#define NV_DEVICE_V0_DISABLE_CE0                          0x0000008000000000ULL
#define NV_DEVICE_V0_DISABLE_CE1                          0x0000010000000000ULL
#define NV_DEVICE_V0_DISABLE_VIC                          0x0000020000000000ULL
#define NV_DEVICE_V0_DISABLE_MSENC                        0x0000040000000000ULL
#define NV_DEVICE_V0_DISABLE_CE2                          0x0000080000000000ULL
#define NV_DEVICE_V0_DISABLE_MSVLD                        0x0000100000000000ULL
#define NV_DEVICE_V0_DISABLE_SEC                          0x0000200000000000ULL
#define NV_DEVICE_V0_DISABLE_MSPDEC                       0x0000400000000000ULL
	__u64 disable;	/* disable particular subsystems */
	__u64 debug0;	/* as above, but *internal* ids, and *NOT* ABI */
};

#define NV_DEVICE_V0_INFO                                                  0x00

struct nv_device_info_v0 {
	__u8  version;
#define NV_DEVICE_INFO_V0_IGP                                              0x00
#define NV_DEVICE_INFO_V0_PCI                                              0x01
#define NV_DEVICE_INFO_V0_AGP                                              0x02
#define NV_DEVICE_INFO_V0_PCIE                                             0x03
#define NV_DEVICE_INFO_V0_SOC                                              0x04
	__u8  platform;
	__u16 chipset;	/* from NV_PMC_BOOT_0 */
	__u8  revision;	/* from NV_PMC_BOOT_0 */
#define NV_DEVICE_INFO_V0_TNT                                              0x01
#define NV_DEVICE_INFO_V0_CELSIUS                                          0x02
#define NV_DEVICE_INFO_V0_KELVIN                                           0x03
#define NV_DEVICE_INFO_V0_RANKINE                                          0x04
#define NV_DEVICE_INFO_V0_CURIE                                            0x05
#define NV_DEVICE_INFO_V0_TESLA                                            0x06
#define NV_DEVICE_INFO_V0_FERMI                                            0x07
#define NV_DEVICE_INFO_V0_KEPLER                                           0x08
#define NV_DEVICE_INFO_V0_MAXWELL                                          0x09
	__u8  family;
	__u8  pad06[2];
	__u64 ram_size;
	__u64 ram_user;
};


/*******************************************************************************
 * context dma
 ******************************************************************************/

struct nv_dma_v0 {
	__u8  version;
#define NV_DMA_V0_TARGET_VM                                                0x00
#define NV_DMA_V0_TARGET_VRAM                                              0x01
#define NV_DMA_V0_TARGET_PCI                                               0x02
#define NV_DMA_V0_TARGET_PCI_US                                            0x03
#define NV_DMA_V0_TARGET_AGP                                               0x04
	__u8  target;
#define NV_DMA_V0_ACCESS_VM                                                0x00
#define NV_DMA_V0_ACCESS_RD                                                0x01
#define NV_DMA_V0_ACCESS_WR                                                0x02
#define NV_DMA_V0_ACCESS_RDWR                 (NV_DMA_V0_ACCESS_RD | NV_DMA_V0_ACCESS_WR)
	__u8  access;
	__u8  pad03[5];
	__u64 start;
	__u64 limit;
	/* ... chipset-specific class data */
};

struct nv50_dma_v0 {
	__u8  version;
#define NV50_DMA_V0_PRIV_VM                                                0x00
#define NV50_DMA_V0_PRIV_US                                                0x01
#define NV50_DMA_V0_PRIV__S                                                0x02
	__u8  priv;
#define NV50_DMA_V0_PART_VM                                                0x00
#define NV50_DMA_V0_PART_256                                               0x01
#define NV50_DMA_V0_PART_1KB                                               0x02
	__u8  part;
#define NV50_DMA_V0_COMP_NONE                                              0x00
#define NV50_DMA_V0_COMP_1                                                 0x01
#define NV50_DMA_V0_COMP_2                                                 0x02
#define NV50_DMA_V0_COMP_VM                                                0x03
	__u8  comp;
#define NV50_DMA_V0_KIND_PITCH                                             0x00
#define NV50_DMA_V0_KIND_VM                                                0x7f
	__u8  kind;
	__u8  pad05[3];
};

struct gf100_dma_v0 {
	__u8  version;
#define GF100_DMA_V0_PRIV_VM                                               0x00
#define GF100_DMA_V0_PRIV_US                                               0x01
#define GF100_DMA_V0_PRIV__S                                               0x02
	__u8  priv;
#define GF100_DMA_V0_KIND_PITCH                                            0x00
#define GF100_DMA_V0_KIND_VM                                               0xff
	__u8  kind;
	__u8  pad03[5];
};

struct gf110_dma_v0 {
	__u8  version;
#define GF110_DMA_V0_PAGE_LP                                               0x00
#define GF110_DMA_V0_PAGE_SP                                               0x01
	__u8  page;
#define GF110_DMA_V0_KIND_PITCH                                            0x00
#define GF110_DMA_V0_KIND_VM                                               0xff
	__u8  kind;
	__u8  pad03[5];
};


/*******************************************************************************
 * perfmon
 ******************************************************************************/

#define NVIF_PERFMON_V0_QUERY_DOMAIN                                       0x00
#define NVIF_PERFMON_V0_QUERY_SIGNAL                                       0x01
#define NVIF_PERFMON_V0_QUERY_SOURCE                                       0x02

struct nvif_perfmon_query_domain_v0 {
	__u8  version;
	__u8  id;
	__u8  counter_nr;
	__u8  iter;
	__u16 signal_nr;
	__u8  pad05[2];
};

struct nvif_perfmon_query_signal_v0 {
	__u8  version;
	__u8  domain;
	__u16 iter;
	__u8  signal;
	__u8  source_nr;
	__u8  pad05[2];
	char  name[64];
};

struct nvif_perfmon_query_source_v0 {
	__u8  version;
	__u8  domain;
	__u8  signal;
	__u8  iter;
	__u8  pad04[4];
	__u32 source;
	__u32 mask;
	char  name[64];
};


/*******************************************************************************
 * perfdom
 ******************************************************************************/

struct nvif_perfdom_v0 {
	__u8  version;
	__u8  domain;
	__u8  mode;
	__u8  pad03[1];
	struct {
		__u8  signal[4];
		__u64 source[4][8];
		__u16 logic_op;
	} ctr[4];
};

#define NVIF_PERFDOM_V0_INIT                                               0x00
#define NVIF_PERFDOM_V0_SAMPLE                                             0x01
#define NVIF_PERFDOM_V0_READ                                               0x02

struct nvif_perfdom_init {
};

struct nvif_perfdom_sample {
};

struct nvif_perfdom_read_v0 {
	__u8  version;
	__u8  pad01[7];
	__u32 ctr[4];
	__u32 clk;
	__u8  pad04[4];
};


/*******************************************************************************
 * device control
 ******************************************************************************/

#define NVIF_CONTROL_PSTATE_INFO                                           0x00
#define NVIF_CONTROL_PSTATE_ATTR                                           0x01
#define NVIF_CONTROL_PSTATE_USER                                           0x02

struct nvif_control_pstate_info_v0 {
	__u8  version;
	__u8  count; /* out: number of power states */
#define NVIF_CONTROL_PSTATE_INFO_V0_USTATE_DISABLE                         (-1)
#define NVIF_CONTROL_PSTATE_INFO_V0_USTATE_PERFMON                         (-2)
	__s8  ustate_ac; /* out: target pstate index */
	__s8  ustate_dc; /* out: target pstate index */
	__s8  pwrsrc; /* out: current power source */
#define NVIF_CONTROL_PSTATE_INFO_V0_PSTATE_UNKNOWN                         (-1)
#define NVIF_CONTROL_PSTATE_INFO_V0_PSTATE_PERFMON                         (-2)
	__s8  pstate; /* out: current pstate index */
	__u8  pad06[2];
};

struct nvif_control_pstate_attr_v0 {
	__u8  version;
#define NVIF_CONTROL_PSTATE_ATTR_V0_STATE_CURRENT                          (-1)
	__s8  state; /*  in: index of pstate to query
		      * out: pstate identifier
		      */
	__u8  index; /*  in: index of attribute to query
		      * out: index of next attribute, or 0 if no more
		      */
	__u8  pad03[5];
	__u32 min;
	__u32 max;
	char  name[32];
	char  unit[16];
};

struct nvif_control_pstate_user_v0 {
	__u8  version;
#define NVIF_CONTROL_PSTATE_USER_V0_STATE_UNKNOWN                          (-1)
#define NVIF_CONTROL_PSTATE_USER_V0_STATE_PERFMON                          (-2)
	__s8  ustate; /*  in: pstate identifier */
	__s8  pwrsrc; /*  in: target power source */
	__u8  pad03[5];
};


/*******************************************************************************
 * DMA FIFO channels
 ******************************************************************************/

struct nv03_channel_dma_v0 {
	__u8  version;
	__u8  chid;
	__u8  pad02[2];
	__u32 pushbuf;
	__u64 offset;
};

#define G82_CHANNEL_DMA_V0_NTFY_UEVENT                                     0x00

/*******************************************************************************
 * GPFIFO channels
 ******************************************************************************/

struct nv50_channel_gpfifo_v0 {
	__u8  version;
	__u8  chid;
	__u8  pad01[6];
	__u32 pushbuf;
	__u32 ilength;
	__u64 ioffset;
};

struct kepler_channel_gpfifo_a_v0 {
	__u8  version;
#define KEPLER_CHANNEL_GPFIFO_A_V0_ENGINE_GR                               0x01
#define KEPLER_CHANNEL_GPFIFO_A_V0_ENGINE_MSPDEC                           0x02
#define KEPLER_CHANNEL_GPFIFO_A_V0_ENGINE_MSPPP                            0x04
#define KEPLER_CHANNEL_GPFIFO_A_V0_ENGINE_MSVLD                            0x08
#define KEPLER_CHANNEL_GPFIFO_A_V0_ENGINE_CE0                              0x10
#define KEPLER_CHANNEL_GPFIFO_A_V0_ENGINE_CE1                              0x20
#define KEPLER_CHANNEL_GPFIFO_A_V0_ENGINE_ENC                              0x40
	__u8  engine;
	__u16 chid;
	__u8  pad04[4];
	__u32 pushbuf;
	__u32 ilength;
	__u64 ioffset;
};

/*******************************************************************************
 * legacy display
 ******************************************************************************/

#define NV04_DISP_NTFY_VBLANK                                              0x00
#define NV04_DISP_NTFY_CONN                                                0x01

struct nv04_disp_mthd_v0 {
	__u8  version;
#define NV04_DISP_SCANOUTPOS                                               0x00
	__u8  method;
	__u8  head;
	__u8  pad03[5];
};

struct nv04_disp_scanoutpos_v0 {
	__u8  version;
	__u8  pad01[7];
	__s64 time[2];
	__u16 vblanks;
	__u16 vblanke;
	__u16 vtotal;
	__u16 vline;
	__u16 hblanks;
	__u16 hblanke;
	__u16 htotal;
	__u16 hline;
};

/*******************************************************************************
 * display
 ******************************************************************************/

#define NV50_DISP_MTHD                                                     0x00

struct nv50_disp_mthd_v0 {
	__u8  version;
#define NV50_DISP_SCANOUTPOS                                               0x00
	__u8  method;
	__u8  head;
	__u8  pad03[5];
};

struct nv50_disp_mthd_v1 {
	__u8  version;
#define NV50_DISP_MTHD_V1_DAC_PWR                                          0x10
#define NV50_DISP_MTHD_V1_DAC_LOAD                                         0x11
#define NV50_DISP_MTHD_V1_SOR_PWR                                          0x20
#define NV50_DISP_MTHD_V1_SOR_HDA_ELD                                      0x21
#define NV50_DISP_MTHD_V1_SOR_HDMI_PWR                                     0x22
#define NV50_DISP_MTHD_V1_SOR_LVDS_SCRIPT                                  0x23
#define NV50_DISP_MTHD_V1_SOR_DP_PWR                                       0x24
#define NV50_DISP_MTHD_V1_PIOR_PWR                                         0x30
	__u8  method;
	__u16 hasht;
	__u16 hashm;
	__u8  pad06[2];
};

struct nv50_disp_dac_pwr_v0 {
	__u8  version;
	__u8  state;
	__u8  data;
	__u8  vsync;
	__u8  hsync;
	__u8  pad05[3];
};

struct nv50_disp_dac_load_v0 {
	__u8  version;
	__u8  load;
	__u8  pad02[2];
	__u32 data;
};

struct nv50_disp_sor_pwr_v0 {
	__u8  version;
	__u8  state;
	__u8  pad02[6];
};

struct nv50_disp_sor_hda_eld_v0 {
	__u8  version;
	__u8  pad01[7];
	__u8  data[];
};

struct nv50_disp_sor_hdmi_pwr_v0 {
	__u8  version;
	__u8  state;
	__u8  max_ac_packet;
	__u8  rekey;
	__u8  pad04[4];
};

struct nv50_disp_sor_lvds_script_v0 {
	__u8  version;
	__u8  pad01[1];
	__u16 script;
	__u8  pad04[4];
};

struct nv50_disp_sor_dp_pwr_v0 {
	__u8  version;
	__u8  state;
	__u8  pad02[6];
};

struct nv50_disp_pior_pwr_v0 {
	__u8  version;
	__u8  state;
	__u8  type;
	__u8  pad03[5];
};

/* core */
struct nv50_disp_core_channel_dma_v0 {
	__u8  version;
	__u8  pad01[3];
	__u32 pushbuf;
};

#define NV50_DISP_CORE_CHANNEL_DMA_V0_NTFY_UEVENT                          0x00

/* cursor immediate */
struct nv50_disp_cursor_v0 {
	__u8  version;
	__u8  head;
	__u8  pad02[6];
};

#define NV50_DISP_CURSOR_V0_NTFY_UEVENT                                    0x00

/* base */
struct nv50_disp_base_channel_dma_v0 {
	__u8  version;
	__u8  pad01[2];
	__u8  head;
	__u32 pushbuf;
};

#define NV50_DISP_BASE_CHANNEL_DMA_V0_NTFY_UEVENT                          0x00

/* overlay */
struct nv50_disp_overlay_channel_dma_v0 {
	__u8  version;
	__u8  pad01[2];
	__u8  head;
	__u32 pushbuf;
};

#define NV50_DISP_OVERLAY_CHANNEL_DMA_V0_NTFY_UEVENT                       0x00

/* overlay immediate */
struct nv50_disp_overlay_v0 {
	__u8  version;
	__u8  head;
	__u8  pad02[6];
};

#define NV50_DISP_OVERLAY_V0_NTFY_UEVENT                                   0x00

/*******************************************************************************
 * fermi
 ******************************************************************************/

#define FERMI_A_ZBC_COLOR                                                  0x00
#define FERMI_A_ZBC_DEPTH                                                  0x01

struct fermi_a_zbc_color_v0 {
	__u8  version;
#define FERMI_A_ZBC_COLOR_V0_FMT_ZERO                                      0x01
#define FERMI_A_ZBC_COLOR_V0_FMT_UNORM_ONE                                 0x02
#define FERMI_A_ZBC_COLOR_V0_FMT_RF32_GF32_BF32_AF32                       0x04
#define FERMI_A_ZBC_COLOR_V0_FMT_R16_G16_B16_A16                           0x08
#define FERMI_A_ZBC_COLOR_V0_FMT_RN16_GN16_BN16_AN16                       0x0c
#define FERMI_A_ZBC_COLOR_V0_FMT_RS16_GS16_BS16_AS16                       0x10
#define FERMI_A_ZBC_COLOR_V0_FMT_RU16_GU16_BU16_AU16                       0x14
#define FERMI_A_ZBC_COLOR_V0_FMT_RF16_GF16_BF16_AF16                       0x16
#define FERMI_A_ZBC_COLOR_V0_FMT_A8R8G8B8                                  0x18
#define FERMI_A_ZBC_COLOR_V0_FMT_A8RL8GL8BL8                               0x1c
#define FERMI_A_ZBC_COLOR_V0_FMT_A2B10G10R10                               0x20
#define FERMI_A_ZBC_COLOR_V0_FMT_AU2BU10GU10RU10                           0x24
#define FERMI_A_ZBC_COLOR_V0_FMT_A8B8G8R8                                  0x28
#define FERMI_A_ZBC_COLOR_V0_FMT_A8BL8GL8RL8                               0x2c
#define FERMI_A_ZBC_COLOR_V0_FMT_AN8BN8GN8RN8                              0x30
#define FERMI_A_ZBC_COLOR_V0_FMT_AS8BS8GS8RS8                              0x34
#define FERMI_A_ZBC_COLOR_V0_FMT_AU8BU8GU8RU8                              0x38
#define FERMI_A_ZBC_COLOR_V0_FMT_A2R10G10B10                               0x3c
#define FERMI_A_ZBC_COLOR_V0_FMT_BF10GF11RF11                              0x40
	__u8  format;
	__u8  index;
	__u8  pad03[5];
	__u32 ds[4];
	__u32 l2[4];
};

struct fermi_a_zbc_depth_v0 {
	__u8  version;
#define FERMI_A_ZBC_DEPTH_V0_FMT_FP32                                      0x01
	__u8  format;
	__u8  index;
	__u8  pad03[5];
	__u32 ds;
	__u32 l2;
};

#endif
Commit	Line	Data
d01c3092 BS	1	#ifndef __NVIF_CLASS_H__
	2	#define __NVIF_CLASS_H__
	3
	4	/*******************************************************************************
	5	* class identifiers
	6	******************************************************************************/
	7
	8	/* the below match nvidia-assigned (either in hw, or sw) class numbers */
	9	#define NV_DEVICE 0x00000080
	10
4acfd707 BS	11	#define NV_DMA_FROM_MEMORY 0x00000002
	12	#define NV_DMA_TO_MEMORY 0x00000003
	13	#define NV_DMA_IN_MEMORY 0x0000003d
	14
3740c825 BS	15	#define FERMI_TWOD_A 0x0000902d
3740c825 BS	16
9ee971a0	17	#define FERMI_MEMORY_TO_MEMORY_FORMAT_A 0x00009039
3740c825 BS	18
	19	#define KEPLER_INLINE_TO_MEMORY_A 0x0000a040
	20	#define KEPLER_INLINE_TO_MEMORY_B 0x0000a140
	21
648d4dfd BS	22	#define NV04_DISP 0x00000046
648d4dfd BS	23
bbf8906b BS	24	#define NV03_CHANNEL_DMA 0x0000006b
	25	#define NV10_CHANNEL_DMA 0x0000006e
	26	#define NV17_CHANNEL_DMA 0x0000176e
	27	#define NV40_CHANNEL_DMA 0x0000406e
	28	#define NV50_CHANNEL_DMA 0x0000506e
	29	#define G82_CHANNEL_DMA 0x0000826e
	30
	31	#define NV50_CHANNEL_GPFIFO 0x0000506f
	32	#define G82_CHANNEL_GPFIFO 0x0000826f
	33	#define FERMI_CHANNEL_GPFIFO 0x0000906f
	34	#define KEPLER_CHANNEL_GPFIFO_A 0x0000a06f
89025bd4	35	#define MAXWELL_CHANNEL_GPFIFO_A 0x0000b06f
bbf8906b	36
648d4dfd BS	37	#define NV50_DISP 0x00005070
	38	#define G82_DISP 0x00008270
	39	#define GT200_DISP 0x00008370
	40	#define GT214_DISP 0x00008570
	41	#define GT206_DISP 0x00008870
	42	#define GF110_DISP 0x00009070
	43	#define GK104_DISP 0x00009170
	44	#define GK110_DISP 0x00009270
	45	#define GM107_DISP 0x00009470
1f89b475	46	#define GM204_DISP 0x00009570
648d4dfd BS	47
	48	#define NV50_DISP_CURSOR 0x0000507a
	49	#define G82_DISP_CURSOR 0x0000827a
	50	#define GT214_DISP_CURSOR 0x0000857a
	51	#define GF110_DISP_CURSOR 0x0000907a
	52	#define GK104_DISP_CURSOR 0x0000917a
	53
	54	#define NV50_DISP_OVERLAY 0x0000507b
	55	#define G82_DISP_OVERLAY 0x0000827b
	56	#define GT214_DISP_OVERLAY 0x0000857b
	57	#define GF110_DISP_OVERLAY 0x0000907b
	58	#define GK104_DISP_OVERLAY 0x0000917b
	59
	60	#define NV50_DISP_BASE_CHANNEL_DMA 0x0000507c
	61	#define G82_DISP_BASE_CHANNEL_DMA 0x0000827c
	62	#define GT200_DISP_BASE_CHANNEL_DMA 0x0000837c
	63	#define GT214_DISP_BASE_CHANNEL_DMA 0x0000857c
	64	#define GF110_DISP_BASE_CHANNEL_DMA 0x0000907c
	65	#define GK104_DISP_BASE_CHANNEL_DMA 0x0000917c
	66	#define GK110_DISP_BASE_CHANNEL_DMA 0x0000927c
	67
	68	#define NV50_DISP_CORE_CHANNEL_DMA 0x0000507d
	69	#define G82_DISP_CORE_CHANNEL_DMA 0x0000827d
	70	#define GT200_DISP_CORE_CHANNEL_DMA 0x0000837d
	71	#define GT214_DISP_CORE_CHANNEL_DMA 0x0000857d
	72	#define GT206_DISP_CORE_CHANNEL_DMA 0x0000887d
	73	#define GF110_DISP_CORE_CHANNEL_DMA 0x0000907d
	74	#define GK104_DISP_CORE_CHANNEL_DMA 0x0000917d
	75	#define GK110_DISP_CORE_CHANNEL_DMA 0x0000927d
	76	#define GM107_DISP_CORE_CHANNEL_DMA 0x0000947d
1f89b475	77	#define GM204_DISP_CORE_CHANNEL_DMA 0x0000957d
648d4dfd BS	78
	79	#define NV50_DISP_OVERLAY_CHANNEL_DMA 0x0000507e
	80	#define G82_DISP_OVERLAY_CHANNEL_DMA 0x0000827e
	81	#define GT200_DISP_OVERLAY_CHANNEL_DMA 0x0000837e
	82	#define GT214_DISP_OVERLAY_CHANNEL_DMA 0x0000857e
	83	#define GF110_DISP_OVERLAY_CONTROL_DMA 0x0000907e
	84	#define GK104_DISP_OVERLAY_CONTROL_DMA 0x0000917e
	85
ac9738bb BS	86	#define FERMI_A 0x00009097
	87	#define FERMI_B 0x00009197
	88	#define FERMI_C 0x00009297
	89
	90	#define KEPLER_A 0x0000a097
	91	#define KEPLER_B 0x0000a197
	92	#define KEPLER_C 0x0000a297
	93
	94	#define MAXWELL_A 0x0000b097
3fed3ea9	95	#define MAXWELL_B 0x0000b197
ac9738bb	96
d6bd3803 BS	97	#define FERMI_COMPUTE_A 0x000090c0
	98	#define FERMI_COMPUTE_B 0x000091c0
	99
	100	#define KEPLER_COMPUTE_A 0x0000a0c0
	101	#define KEPLER_COMPUTE_B 0x0000a1c0
	102
	103	#define MAXWELL_COMPUTE_A 0x0000b0c0
3fed3ea9	104	#define MAXWELL_COMPUTE_B 0x0000b1c0
d6bd3803	105
d01c3092	106
803c1787 BS	107	/*******************************************************************************
	108	* client
	109	******************************************************************************/
	110
	111	#define NV_CLIENT_DEVLIST 0x00
	112
	113	struct nv_client_devlist_v0 {
	114	__u8 version;
	115	__u8 count;
	116	__u8 pad02[6];
	117	__u64 device[];
	118	};
	119
	120
d01c3092 BS	121	/*******************************************************************************
	122	* device
	123	******************************************************************************/
	124
586491e6 BS	125	struct nv_device_v0 {
	126	__u8 version;
	127	__u8 pad01[7];
	128	__u64 device; /* device identifier, ~0 for client default */
	129	#define NV_DEVICE_V0_DISABLE_IDENTIFY 0x0000000000000001ULL
	130	#define NV_DEVICE_V0_DISABLE_MMIO 0x0000000000000002ULL
	131	#define NV_DEVICE_V0_DISABLE_VBIOS 0x0000000000000004ULL
	132	#define NV_DEVICE_V0_DISABLE_CORE 0x0000000000000008ULL
	133	#define NV_DEVICE_V0_DISABLE_DISP 0x0000000000010000ULL
	134	#define NV_DEVICE_V0_DISABLE_FIFO 0x0000000000020000ULL
b8bf04e1	135	#define NV_DEVICE_V0_DISABLE_GR 0x0000000100000000ULL
586491e6 BS	136	#define NV_DEVICE_V0_DISABLE_MPEG 0x0000000200000000ULL
	137	#define NV_DEVICE_V0_DISABLE_ME 0x0000000400000000ULL
	138	#define NV_DEVICE_V0_DISABLE_VP 0x0000000800000000ULL
93d90ad7	139	#define NV_DEVICE_V0_DISABLE_CIPHER 0x0000001000000000ULL
586491e6	140	#define NV_DEVICE_V0_DISABLE_BSP 0x0000002000000000ULL
fd8666f7	141	#define NV_DEVICE_V0_DISABLE_MSPPP 0x0000004000000000ULL
aedf24ff BS	142	#define NV_DEVICE_V0_DISABLE_CE0 0x0000008000000000ULL
aedf24ff BS	143	#define NV_DEVICE_V0_DISABLE_CE1 0x0000010000000000ULL
586491e6	144	#define NV_DEVICE_V0_DISABLE_VIC 0x0000020000000000ULL
bd8369ec	145	#define NV_DEVICE_V0_DISABLE_MSENC 0x0000040000000000ULL
aedf24ff	146	#define NV_DEVICE_V0_DISABLE_CE2 0x0000080000000000ULL
eccf7e8a	147	#define NV_DEVICE_V0_DISABLE_MSVLD 0x0000100000000000ULL
93d90ad7	148	#define NV_DEVICE_V0_DISABLE_SEC 0x0000200000000000ULL
37a5d028	149	#define NV_DEVICE_V0_DISABLE_MSPDEC 0x0000400000000000ULL
586491e6 BS	150	__u64 disable; /* disable particular subsystems */
	151	__u64 debug0; /* as above, but internal ids, and NOT ABI */
	152	};
	153
d01c3092 BS	154	#define NV_DEVICE_V0_INFO 0x00
	155
	156	struct nv_device_info_v0 {
	157	__u8 version;
	158	#define NV_DEVICE_INFO_V0_IGP 0x00
	159	#define NV_DEVICE_INFO_V0_PCI 0x01
	160	#define NV_DEVICE_INFO_V0_AGP 0x02
	161	#define NV_DEVICE_INFO_V0_PCIE 0x03
	162	#define NV_DEVICE_INFO_V0_SOC 0x04
	163	__u8 platform;
	164	__u16 chipset; /* from NV_PMC_BOOT_0 */
	165	__u8 revision; /* from NV_PMC_BOOT_0 */
	166	#define NV_DEVICE_INFO_V0_TNT 0x01
	167	#define NV_DEVICE_INFO_V0_CELSIUS 0x02
	168	#define NV_DEVICE_INFO_V0_KELVIN 0x03
	169	#define NV_DEVICE_INFO_V0_RANKINE 0x04
	170	#define NV_DEVICE_INFO_V0_CURIE 0x05
	171	#define NV_DEVICE_INFO_V0_TESLA 0x06
	172	#define NV_DEVICE_INFO_V0_FERMI 0x07
	173	#define NV_DEVICE_INFO_V0_KEPLER 0x08
	174	#define NV_DEVICE_INFO_V0_MAXWELL 0x09
	175	__u8 family;
	176	__u8 pad06[2];
	177	__u64 ram_size;
	178	__u64 ram_user;
	179	};
	180
4acfd707 BS	181
	182	/*******************************************************************************
	183	* context dma
	184	******************************************************************************/
	185
	186	struct nv_dma_v0 {
	187	__u8 version;
	188	#define NV_DMA_V0_TARGET_VM 0x00
	189	#define NV_DMA_V0_TARGET_VRAM 0x01
	190	#define NV_DMA_V0_TARGET_PCI 0x02
	191	#define NV_DMA_V0_TARGET_PCI_US 0x03
	192	#define NV_DMA_V0_TARGET_AGP 0x04
	193	__u8 target;
	194	#define NV_DMA_V0_ACCESS_VM 0x00
	195	#define NV_DMA_V0_ACCESS_RD 0x01
	196	#define NV_DMA_V0_ACCESS_WR 0x02
	197	#define NV_DMA_V0_ACCESS_RDWR (NV_DMA_V0_ACCESS_RD \| NV_DMA_V0_ACCESS_WR)
	198	__u8 access;
	199	__u8 pad03[5];
	200	__u64 start;
	201	__u64 limit;
	202	/* ... chipset-specific class data */
	203	};
	204
	205	struct nv50_dma_v0 {
	206	__u8 version;
	207	#define NV50_DMA_V0_PRIV_VM 0x00
	208	#define NV50_DMA_V0_PRIV_US 0x01
	209	#define NV50_DMA_V0_PRIV__S 0x02
	210	__u8 priv;
	211	#define NV50_DMA_V0_PART_VM 0x00
	212	#define NV50_DMA_V0_PART_256 0x01
	213	#define NV50_DMA_V0_PART_1KB 0x02
	214	__u8 part;
	215	#define NV50_DMA_V0_COMP_NONE 0x00
	216	#define NV50_DMA_V0_COMP_1 0x01
	217	#define NV50_DMA_V0_COMP_2 0x02
	218	#define NV50_DMA_V0_COMP_VM 0x03
	219	__u8 comp;
	220	#define NV50_DMA_V0_KIND_PITCH 0x00
	221	#define NV50_DMA_V0_KIND_VM 0x7f
	222	__u8 kind;
	223	__u8 pad05[3];
	224	};
	225
	226	struct gf100_dma_v0 {
	227	__u8 version;
	228	#define GF100_DMA_V0_PRIV_VM 0x00
	229	#define GF100_DMA_V0_PRIV_US 0x01
	230	#define GF100_DMA_V0_PRIV__S 0x02
	231	__u8 priv;
	232	#define GF100_DMA_V0_KIND_PITCH 0x00
	233	#define GF100_DMA_V0_KIND_VM 0xff
	234	__u8 kind;
	235	__u8 pad03[5];
	236	};
	237
	238	struct gf110_dma_v0 {
	239	__u8 version;
	240	#define GF110_DMA_V0_PAGE_LP 0x00
	241	#define GF110_DMA_V0_PAGE_SP 0x01
	242	__u8 page;
	243	#define GF110_DMA_V0_KIND_PITCH 0x00
	244	#define GF110_DMA_V0_KIND_VM 0xff
245	__u8 kind;
246	__u8 pad03[5];
247	};
248
96af8222 BS	249
	250	/*******************************************************************************
	251	* perfmon
	252	******************************************************************************/
	253
45f0f94d SP	254	#define NVIF_PERFMON_V0_QUERY_DOMAIN 0x00
45f0f94d SP	255	#define NVIF_PERFMON_V0_QUERY_SIGNAL 0x01
6f99c848	256	#define NVIF_PERFMON_V0_QUERY_SOURCE 0x02
45f0f94d SP	257
	258	struct nvif_perfmon_query_domain_v0 {
	259	__u8 version;
	260	__u8 id;
	261	__u8 counter_nr;
	262	__u8 iter;
e4047599 SP	263	__u16 signal_nr;
e4047599 SP	264	__u8 pad05[2];
45f0f94d	265	};
5a0bc4b5 SP	266
	267	struct nvif_perfmon_query_signal_v0 {
	268	__u8 version;
3e1b3357	269	__u8 domain;
e4047599	270	__u16 iter;
10a4d2b2	271	__u8 signal;
50d138d7 SP	272	__u8 source_nr;
50d138d7 SP	273	__u8 pad05[2];
5a0bc4b5 SP	274	char name[64];
	275	};
	276
6f99c848 SP	277	struct nvif_perfmon_query_source_v0 {
	278	__u8 version;
	279	__u8 domain;
	280	__u8 signal;
	281	__u8 iter;
	282	__u8 pad04[4];
	283	__u32 source;
	284	__u32 mask;
	285	char name[64];
	286	};
	287
5a0bc4b5 SP	288
5a0bc4b5 SP	289	/*******************************************************************************
0f380436	290	* perfdom
5a0bc4b5 SP	291	******************************************************************************/
5a0bc4b5 SP	292
0f380436	293	struct nvif_perfdom_v0 {
96af8222	294	__u8 version;
10a4d2b2	295	__u8 domain;
0f380436 SP	296	__u8 mode;
	297	__u8 pad03[1];
	298	struct {
	299	__u8 signal[4];
6137b5a7	300	__u64 source[4][8];
0f380436 SP	301	__u16 logic_op;
0f380436 SP	302	} ctr[4];
96af8222 BS	303	};
96af8222 BS	304
0f380436 SP	305	#define NVIF_PERFDOM_V0_INIT 0x00
	306	#define NVIF_PERFDOM_V0_SAMPLE 0x01
	307	#define NVIF_PERFDOM_V0_READ 0x02
3bfdde17	308
0f380436	309	struct nvif_perfdom_init {
3bfdde17	310	};
96af8222	311
0f380436	312	struct nvif_perfdom_sample {
96af8222 BS	313	};
96af8222 BS	314
0f380436	315	struct nvif_perfdom_read_v0 {
96af8222 BS	316	__u8 version;
96af8222 BS	317	__u8 pad01[7];
0f380436	318	__u32 ctr[4];
96af8222	319	__u32 clk;
0f380436	320	__u8 pad04[4];
96af8222 BS	321	};
96af8222 BS	322
a532da97 BS	323
	324	/*******************************************************************************
	325	* device control
	326	******************************************************************************/
	327
	328	#define NVIF_CONTROL_PSTATE_INFO 0x00
	329	#define NVIF_CONTROL_PSTATE_ATTR 0x01
	330	#define NVIF_CONTROL_PSTATE_USER 0x02
	331
	332	struct nvif_control_pstate_info_v0 {
	333	__u8 version;
	334	__u8 count; /* out: number of power states */
	335	#define NVIF_CONTROL_PSTATE_INFO_V0_USTATE_DISABLE (-1)
	336	#define NVIF_CONTROL_PSTATE_INFO_V0_USTATE_PERFMON (-2)
	337	__s8 ustate_ac; /* out: target pstate index */
	338	__s8 ustate_dc; /* out: target pstate index */
	339	__s8 pwrsrc; /* out: current power source */
	340	#define NVIF_CONTROL_PSTATE_INFO_V0_PSTATE_UNKNOWN (-1)
	341	#define NVIF_CONTROL_PSTATE_INFO_V0_PSTATE_PERFMON (-2)
	342	__s8 pstate; /* out: current pstate index */
	343	__u8 pad06[2];
	344	};
	345
	346	struct nvif_control_pstate_attr_v0 {
	347	__u8 version;
	348	#define NVIF_CONTROL_PSTATE_ATTR_V0_STATE_CURRENT (-1)
	349	__s8 state; /* in: index of pstate to query
	350	* out: pstate identifier
	351	*/
	352	__u8 index; /* in: index of attribute to query
	353	* out: index of next attribute, or 0 if no more
	354	*/
	355	__u8 pad03[5];
	356	__u32 min;
	357	__u32 max;
	358	char name[32];
	359	char unit[16];
	360	};
	361
	362	struct nvif_control_pstate_user_v0 {
	363	__u8 version;
	364	#define NVIF_CONTROL_PSTATE_USER_V0_STATE_UNKNOWN (-1)
	365	#define NVIF_CONTROL_PSTATE_USER_V0_STATE_PERFMON (-2)
	366	__s8 ustate; /* in: pstate identifier */
	367	__s8 pwrsrc; /* in: target power source */
	368	__u8 pad03[5];
	369	};
	370
bbf8906b BS	371
	372	/*******************************************************************************
	373	* DMA FIFO channels
	374	******************************************************************************/
	375
	376	struct nv03_channel_dma_v0 {
	377	__u8 version;
	378	__u8 chid;
	379	__u8 pad02[2];
	380	__u32 pushbuf;
	381	__u64 offset;
	382	};
	383
867920f8	384	#define G82_CHANNEL_DMA_V0_NTFY_UEVENT 0x00
bbf8906b BS	385
	386	/*******************************************************************************
	387	* GPFIFO channels
	388	******************************************************************************/
	389
	390	struct nv50_channel_gpfifo_v0 {
	391	__u8 version;
	392	__u8 chid;
	393	__u8 pad01[6];
	394	__u32 pushbuf;
	395	__u32 ilength;
	396	__u64 ioffset;
	397	};
	398
	399	struct kepler_channel_gpfifo_a_v0 {
	400	__u8 version;
	401	#define KEPLER_CHANNEL_GPFIFO_A_V0_ENGINE_GR 0x01
37a5d028	402	#define KEPLER_CHANNEL_GPFIFO_A_V0_ENGINE_MSPDEC 0x02
fd8666f7	403	#define KEPLER_CHANNEL_GPFIFO_A_V0_ENGINE_MSPPP 0x04
eccf7e8a	404	#define KEPLER_CHANNEL_GPFIFO_A_V0_ENGINE_MSVLD 0x08
bbf8906b BS	405	#define KEPLER_CHANNEL_GPFIFO_A_V0_ENGINE_CE0 0x10
	406	#define KEPLER_CHANNEL_GPFIFO_A_V0_ENGINE_CE1 0x20
	407	#define KEPLER_CHANNEL_GPFIFO_A_V0_ENGINE_ENC 0x40
	408	__u8 engine;
	409	__u16 chid;
	410	__u8 pad04[4];
	411	__u32 pushbuf;
	412	__u32 ilength;
	413	__u64 ioffset;
	414	};
	415
bf0eb898 BS	416	/*******************************************************************************
	417	* legacy display
	418	******************************************************************************/
	419
80bc340b BS	420	#define NV04_DISP_NTFY_VBLANK 0x00
	421	#define NV04_DISP_NTFY_CONN 0x01
	422
4952b4d3 BS	423	struct nv04_disp_mthd_v0 {
	424	__u8 version;
	425	#define NV04_DISP_SCANOUTPOS 0x00
	426	__u8 method;
	427	__u8 head;
	428	__u8 pad03[5];
	429	};
	430
	431	struct nv04_disp_scanoutpos_v0 {
	432	__u8 version;
	433	__u8 pad01[7];
	434	__s64 time[2];
	435	__u16 vblanks;
	436	__u16 vblanke;
	437	__u16 vtotal;
	438	__u16 vline;
	439	__u16 hblanks;
	440	__u16 hblanke;
	441	__u16 htotal;
	442	__u16 hline;
	443	};
	444
bf0eb898 BS	445	/*******************************************************************************
	446	* display
	447	******************************************************************************/
	448
	449	#define NV50_DISP_MTHD 0x00
	450
	451	struct nv50_disp_mthd_v0 {
	452	__u8 version;
4952b4d3	453	#define NV50_DISP_SCANOUTPOS 0x00
bf0eb898 BS	454	__u8 method;
	455	__u8 head;
	456	__u8 pad03[5];
	457	};
	458
	459	struct nv50_disp_mthd_v1 {
	460	__u8 version;
	461	#define NV50_DISP_MTHD_V1_DAC_PWR 0x10
	462	#define NV50_DISP_MTHD_V1_DAC_LOAD 0x11
	463	#define NV50_DISP_MTHD_V1_SOR_PWR 0x20
	464	#define NV50_DISP_MTHD_V1_SOR_HDA_ELD 0x21
	465	#define NV50_DISP_MTHD_V1_SOR_HDMI_PWR 0x22
	466	#define NV50_DISP_MTHD_V1_SOR_LVDS_SCRIPT 0x23
	467	#define NV50_DISP_MTHD_V1_SOR_DP_PWR 0x24
	468	#define NV50_DISP_MTHD_V1_PIOR_PWR 0x30
	469	__u8 method;
	470	__u16 hasht;
	471	__u16 hashm;
	472	__u8 pad06[2];
	473	};
	474
	475	struct nv50_disp_dac_pwr_v0 {
	476	__u8 version;
	477	__u8 state;
	478	__u8 data;
	479	__u8 vsync;
	480	__u8 hsync;
	481	__u8 pad05[3];
	482	};
	483
c4abd317 BS	484	struct nv50_disp_dac_load_v0 {
	485	__u8 version;
	486	__u8 load;
8bd62a83 BS	487	__u8 pad02[2];
8bd62a83 BS	488	__u32 data;
c4abd317 BS	489	};
c4abd317 BS	490
d55b4af9 BS	491	struct nv50_disp_sor_pwr_v0 {
	492	__u8 version;
	493	__u8 state;
	494	__u8 pad02[6];
	495	};
	496
120b0c39 BS	497	struct nv50_disp_sor_hda_eld_v0 {
	498	__u8 version;
	499	__u8 pad01[7];
	500	__u8 data[];
	501	};
	502
e00f2235 BS	503	struct nv50_disp_sor_hdmi_pwr_v0 {
	504	__u8 version;
	505	__u8 state;
	506	__u8 max_ac_packet;
	507	__u8 rekey;
	508	__u8 pad04[4];
	509	};
	510
a3761fa2 BS	511	struct nv50_disp_sor_lvds_script_v0 {
	512	__u8 version;
	513	__u8 pad01[1];
	514	__u16 script;
	515	__u8 pad04[4];
	516	};
	517
c02ed2bf BS	518	struct nv50_disp_sor_dp_pwr_v0 {
	519	__u8 version;
	520	__u8 state;
	521	__u8 pad02[6];
	522	};
	523
67cb49c4 BS	524	struct nv50_disp_pior_pwr_v0 {
	525	__u8 version;
	526	__u8 state;
	527	__u8 type;
	528	__u8 pad03[5];
	529	};
	530
648d4dfd BS	531	/* core */
	532	struct nv50_disp_core_channel_dma_v0 {
	533	__u8 version;
	534	__u8 pad01[3];
	535	__u32 pushbuf;
	536	};
	537
b38a2322 BS	538	#define NV50_DISP_CORE_CHANNEL_DMA_V0_NTFY_UEVENT 0x00
b38a2322 BS	539
648d4dfd BS	540	/* cursor immediate */
	541	struct nv50_disp_cursor_v0 {
	542	__u8 version;
	543	__u8 head;
	544	__u8 pad02[6];
	545	};
	546
b38a2322 BS	547	#define NV50_DISP_CURSOR_V0_NTFY_UEVENT 0x00
b38a2322 BS	548
648d4dfd BS	549	/* base */
	550	struct nv50_disp_base_channel_dma_v0 {
	551	__u8 version;
	552	__u8 pad01[2];
	553	__u8 head;
	554	__u32 pushbuf;
	555	};
	556
b38a2322 BS	557	#define NV50_DISP_BASE_CHANNEL_DMA_V0_NTFY_UEVENT 0x00
b38a2322 BS	558
648d4dfd BS	559	/* overlay */
	560	struct nv50_disp_overlay_channel_dma_v0 {
	561	__u8 version;
	562	__u8 pad01[2];
	563	__u8 head;
	564	__u32 pushbuf;
	565	};
	566
b38a2322 BS	567	#define NV50_DISP_OVERLAY_CHANNEL_DMA_V0_NTFY_UEVENT 0x00
b38a2322 BS	568
648d4dfd BS	569	/* overlay immediate */
	570	struct nv50_disp_overlay_v0 {
	571	__u8 version;
	572	__u8 head;
	573	__u8 pad02[6];
	574	};
	575
b38a2322	576	#define NV50_DISP_OVERLAY_V0_NTFY_UEVENT 0x00
ac9738bb BS	577
	578	/*******************************************************************************
	579	* fermi
	580	******************************************************************************/
	581
	582	#define FERMI_A_ZBC_COLOR 0x00
	583	#define FERMI_A_ZBC_DEPTH 0x01
	584
	585	struct fermi_a_zbc_color_v0 {
	586	__u8 version;
	587	#define FERMI_A_ZBC_COLOR_V0_FMT_ZERO 0x01
	588	#define FERMI_A_ZBC_COLOR_V0_FMT_UNORM_ONE 0x02
	589	#define FERMI_A_ZBC_COLOR_V0_FMT_RF32_GF32_BF32_AF32 0x04
	590	#define FERMI_A_ZBC_COLOR_V0_FMT_R16_G16_B16_A16 0x08
	591	#define FERMI_A_ZBC_COLOR_V0_FMT_RN16_GN16_BN16_AN16 0x0c
	592	#define FERMI_A_ZBC_COLOR_V0_FMT_RS16_GS16_BS16_AS16 0x10
	593	#define FERMI_A_ZBC_COLOR_V0_FMT_RU16_GU16_BU16_AU16 0x14
	594	#define FERMI_A_ZBC_COLOR_V0_FMT_RF16_GF16_BF16_AF16 0x16
	595	#define FERMI_A_ZBC_COLOR_V0_FMT_A8R8G8B8 0x18
	596	#define FERMI_A_ZBC_COLOR_V0_FMT_A8RL8GL8BL8 0x1c
	597	#define FERMI_A_ZBC_COLOR_V0_FMT_A2B10G10R10 0x20
	598	#define FERMI_A_ZBC_COLOR_V0_FMT_AU2BU10GU10RU10 0x24
	599	#define FERMI_A_ZBC_COLOR_V0_FMT_A8B8G8R8 0x28
	600	#define FERMI_A_ZBC_COLOR_V0_FMT_A8BL8GL8RL8 0x2c
	601	#define FERMI_A_ZBC_COLOR_V0_FMT_AN8BN8GN8RN8 0x30
	602	#define FERMI_A_ZBC_COLOR_V0_FMT_AS8BS8GS8RS8 0x34
	603	#define FERMI_A_ZBC_COLOR_V0_FMT_AU8BU8GU8RU8 0x38
	604	#define FERMI_A_ZBC_COLOR_V0_FMT_A2R10G10B10 0x3c
	605	#define FERMI_A_ZBC_COLOR_V0_FMT_BF10GF11RF11 0x40
	606	__u8 format;
	607	__u8 index;
	608	__u8 pad03[5];
	609	__u32 ds[4];
	610	__u32 l2[4];
	611	};
	612
	613	struct fermi_a_zbc_depth_v0 {
	614	__u8 version;
	615	#define FERMI_A_ZBC_DEPTH_V0_FMT_FP32 0x01
	616	__u8 format;
	617	__u8 index;
	618	__u8 pad03[5];
	619	__u32 ds;
	620	__u32 l2;
	621	};
	622
d01c3092	623	#endif