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6ee73861 BS |
1 | /* |
2 | * Copyright 2007 Dave Airlied | |
3 | * All Rights Reserved. | |
4 | * | |
5 | * Permission is hereby granted, free of charge, to any person obtaining a | |
6 | * copy of this software and associated documentation files (the "Software"), | |
7 | * to deal in the Software without restriction, including without limitation | |
8 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
9 | * and/or sell copies of the Software, and to permit persons to whom the | |
10 | * Software is furnished to do so, subject to the following conditions: | |
11 | * | |
12 | * The above copyright notice and this permission notice (including the next | |
13 | * paragraph) shall be included in all copies or substantial portions of the | |
14 | * Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
20 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
21 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
22 | * OTHER DEALINGS IN THE SOFTWARE. | |
23 | */ | |
24 | /* | |
25 | * Authors: Dave Airlied <airlied@linux.ie> | |
26 | * Ben Skeggs <darktama@iinet.net.au> | |
27 | * Jeremy Kolb <jkolb@brandeis.edu> | |
28 | */ | |
29 | ||
30 | #include "drmP.h" | |
31 | ||
32 | #include "nouveau_drm.h" | |
33 | #include "nouveau_drv.h" | |
34 | #include "nouveau_dma.h" | |
35 | ||
a510604d | 36 | #include <linux/log2.h> |
5a0e3ad6 | 37 | #include <linux/slab.h> |
a510604d | 38 | |
6ee73861 BS |
39 | static void |
40 | nouveau_bo_del_ttm(struct ttm_buffer_object *bo) | |
41 | { | |
42 | struct drm_nouveau_private *dev_priv = nouveau_bdev(bo->bdev); | |
a0af9add | 43 | struct drm_device *dev = dev_priv->dev; |
6ee73861 BS |
44 | struct nouveau_bo *nvbo = nouveau_bo(bo); |
45 | ||
6ee73861 BS |
46 | if (unlikely(nvbo->gem)) |
47 | DRM_ERROR("bo %p still attached to GEM object\n", bo); | |
48 | ||
a0af9add FJ |
49 | if (nvbo->tile) |
50 | nv10_mem_expire_tiling(dev, nvbo->tile, NULL); | |
51 | ||
6ee73861 BS |
52 | kfree(nvbo); |
53 | } | |
54 | ||
a0af9add FJ |
55 | static void |
56 | nouveau_bo_fixup_align(struct drm_device *dev, | |
57 | uint32_t tile_mode, uint32_t tile_flags, | |
58 | int *align, int *size) | |
59 | { | |
60 | struct drm_nouveau_private *dev_priv = dev->dev_private; | |
61 | ||
62 | /* | |
63 | * Some of the tile_flags have a periodic structure of N*4096 bytes, | |
eb1dba0e MM |
64 | * align to to that as well as the page size. Align the size to the |
65 | * appropriate boundaries. This does imply that sizes are rounded up | |
66 | * 3-7 pages, so be aware of this and do not waste memory by allocating | |
67 | * many small buffers. | |
a0af9add FJ |
68 | */ |
69 | if (dev_priv->card_type == NV_50) { | |
a76fb4e8 | 70 | uint32_t block_size = dev_priv->vram_size >> 15; |
a510604d MM |
71 | int i; |
72 | ||
a0af9add FJ |
73 | switch (tile_flags) { |
74 | case 0x1800: | |
75 | case 0x2800: | |
76 | case 0x4800: | |
77 | case 0x7a00: | |
a510604d | 78 | if (is_power_of_2(block_size)) { |
a510604d MM |
79 | for (i = 1; i < 10; i++) { |
80 | *align = 12 * i * block_size; | |
81 | if (!(*align % 65536)) | |
82 | break; | |
83 | } | |
a0af9add | 84 | } else { |
a510604d MM |
85 | for (i = 1; i < 10; i++) { |
86 | *align = 8 * i * block_size; | |
87 | if (!(*align % 65536)) | |
88 | break; | |
89 | } | |
a0af9add | 90 | } |
eb1dba0e | 91 | *size = roundup(*size, *align); |
a0af9add FJ |
92 | break; |
93 | default: | |
94 | break; | |
95 | } | |
96 | ||
97 | } else { | |
98 | if (tile_mode) { | |
99 | if (dev_priv->chipset >= 0x40) { | |
100 | *align = 65536; | |
101 | *size = roundup(*size, 64 * tile_mode); | |
102 | ||
103 | } else if (dev_priv->chipset >= 0x30) { | |
104 | *align = 32768; | |
105 | *size = roundup(*size, 64 * tile_mode); | |
106 | ||
107 | } else if (dev_priv->chipset >= 0x20) { | |
108 | *align = 16384; | |
109 | *size = roundup(*size, 64 * tile_mode); | |
110 | ||
111 | } else if (dev_priv->chipset >= 0x10) { | |
112 | *align = 16384; | |
113 | *size = roundup(*size, 32 * tile_mode); | |
114 | } | |
115 | } | |
116 | } | |
117 | ||
1c7059e4 MM |
118 | /* ALIGN works only on powers of two. */ |
119 | *size = roundup(*size, PAGE_SIZE); | |
a0af9add FJ |
120 | |
121 | if (dev_priv->card_type == NV_50) { | |
1c7059e4 | 122 | *size = roundup(*size, 65536); |
a0af9add FJ |
123 | *align = max(65536, *align); |
124 | } | |
125 | } | |
126 | ||
6ee73861 BS |
127 | int |
128 | nouveau_bo_new(struct drm_device *dev, struct nouveau_channel *chan, | |
129 | int size, int align, uint32_t flags, uint32_t tile_mode, | |
130 | uint32_t tile_flags, bool no_vm, bool mappable, | |
131 | struct nouveau_bo **pnvbo) | |
132 | { | |
133 | struct drm_nouveau_private *dev_priv = dev->dev_private; | |
134 | struct nouveau_bo *nvbo; | |
8dea4a19 | 135 | int ret = 0; |
6ee73861 BS |
136 | |
137 | nvbo = kzalloc(sizeof(struct nouveau_bo), GFP_KERNEL); | |
138 | if (!nvbo) | |
139 | return -ENOMEM; | |
140 | INIT_LIST_HEAD(&nvbo->head); | |
141 | INIT_LIST_HEAD(&nvbo->entry); | |
142 | nvbo->mappable = mappable; | |
143 | nvbo->no_vm = no_vm; | |
144 | nvbo->tile_mode = tile_mode; | |
145 | nvbo->tile_flags = tile_flags; | |
699ddfd9 | 146 | nvbo->bo.bdev = &dev_priv->ttm.bdev; |
6ee73861 | 147 | |
f13b3263 FJ |
148 | nouveau_bo_fixup_align(dev, tile_mode, nouveau_bo_tile_layout(nvbo), |
149 | &align, &size); | |
6ee73861 BS |
150 | align >>= PAGE_SHIFT; |
151 | ||
78ad0f7b | 152 | nouveau_bo_placement_set(nvbo, flags, 0); |
6ee73861 BS |
153 | |
154 | nvbo->channel = chan; | |
6ee73861 BS |
155 | ret = ttm_bo_init(&dev_priv->ttm.bdev, &nvbo->bo, size, |
156 | ttm_bo_type_device, &nvbo->placement, align, 0, | |
157 | false, NULL, size, nouveau_bo_del_ttm); | |
6ee73861 BS |
158 | if (ret) { |
159 | /* ttm will call nouveau_bo_del_ttm if it fails.. */ | |
160 | return ret; | |
161 | } | |
90af89b9 | 162 | nvbo->channel = NULL; |
6ee73861 | 163 | |
6ee73861 BS |
164 | *pnvbo = nvbo; |
165 | return 0; | |
166 | } | |
167 | ||
78ad0f7b FJ |
168 | static void |
169 | set_placement_list(uint32_t *pl, unsigned *n, uint32_t type, uint32_t flags) | |
170 | { | |
171 | *n = 0; | |
172 | ||
173 | if (type & TTM_PL_FLAG_VRAM) | |
174 | pl[(*n)++] = TTM_PL_FLAG_VRAM | flags; | |
175 | if (type & TTM_PL_FLAG_TT) | |
176 | pl[(*n)++] = TTM_PL_FLAG_TT | flags; | |
177 | if (type & TTM_PL_FLAG_SYSTEM) | |
178 | pl[(*n)++] = TTM_PL_FLAG_SYSTEM | flags; | |
179 | } | |
180 | ||
699ddfd9 FJ |
181 | static void |
182 | set_placement_range(struct nouveau_bo *nvbo, uint32_t type) | |
183 | { | |
184 | struct drm_nouveau_private *dev_priv = nouveau_bdev(nvbo->bo.bdev); | |
185 | ||
186 | if (dev_priv->card_type == NV_10 && | |
187 | nvbo->tile_mode && (type & TTM_PL_FLAG_VRAM)) { | |
188 | /* | |
189 | * Make sure that the color and depth buffers are handled | |
190 | * by independent memory controller units. Up to a 9x | |
191 | * speed up when alpha-blending and depth-test are enabled | |
192 | * at the same time. | |
193 | */ | |
194 | int vram_pages = dev_priv->vram_size >> PAGE_SHIFT; | |
195 | ||
196 | if (nvbo->tile_flags & NOUVEAU_GEM_TILE_ZETA) { | |
197 | nvbo->placement.fpfn = vram_pages / 2; | |
198 | nvbo->placement.lpfn = ~0; | |
199 | } else { | |
200 | nvbo->placement.fpfn = 0; | |
201 | nvbo->placement.lpfn = vram_pages / 2; | |
202 | } | |
203 | } | |
204 | } | |
205 | ||
6ee73861 | 206 | void |
78ad0f7b | 207 | nouveau_bo_placement_set(struct nouveau_bo *nvbo, uint32_t type, uint32_t busy) |
6ee73861 | 208 | { |
78ad0f7b FJ |
209 | struct ttm_placement *pl = &nvbo->placement; |
210 | uint32_t flags = TTM_PL_MASK_CACHING | | |
211 | (nvbo->pin_refcnt ? TTM_PL_FLAG_NO_EVICT : 0); | |
212 | ||
213 | pl->placement = nvbo->placements; | |
214 | set_placement_list(nvbo->placements, &pl->num_placement, | |
215 | type, flags); | |
216 | ||
217 | pl->busy_placement = nvbo->busy_placements; | |
218 | set_placement_list(nvbo->busy_placements, &pl->num_busy_placement, | |
219 | type | busy, flags); | |
699ddfd9 FJ |
220 | |
221 | set_placement_range(nvbo, type); | |
6ee73861 BS |
222 | } |
223 | ||
224 | int | |
225 | nouveau_bo_pin(struct nouveau_bo *nvbo, uint32_t memtype) | |
226 | { | |
227 | struct drm_nouveau_private *dev_priv = nouveau_bdev(nvbo->bo.bdev); | |
228 | struct ttm_buffer_object *bo = &nvbo->bo; | |
78ad0f7b | 229 | int ret; |
6ee73861 BS |
230 | |
231 | if (nvbo->pin_refcnt && !(memtype & (1 << bo->mem.mem_type))) { | |
232 | NV_ERROR(nouveau_bdev(bo->bdev)->dev, | |
233 | "bo %p pinned elsewhere: 0x%08x vs 0x%08x\n", bo, | |
234 | 1 << bo->mem.mem_type, memtype); | |
235 | return -EINVAL; | |
236 | } | |
237 | ||
238 | if (nvbo->pin_refcnt++) | |
239 | return 0; | |
240 | ||
241 | ret = ttm_bo_reserve(bo, false, false, false, 0); | |
242 | if (ret) | |
243 | goto out; | |
244 | ||
78ad0f7b | 245 | nouveau_bo_placement_set(nvbo, memtype, 0); |
6ee73861 | 246 | |
9d87fa21 | 247 | ret = ttm_bo_validate(bo, &nvbo->placement, false, false, false); |
6ee73861 BS |
248 | if (ret == 0) { |
249 | switch (bo->mem.mem_type) { | |
250 | case TTM_PL_VRAM: | |
251 | dev_priv->fb_aper_free -= bo->mem.size; | |
252 | break; | |
253 | case TTM_PL_TT: | |
254 | dev_priv->gart_info.aper_free -= bo->mem.size; | |
255 | break; | |
256 | default: | |
257 | break; | |
258 | } | |
259 | } | |
260 | ttm_bo_unreserve(bo); | |
261 | out: | |
262 | if (unlikely(ret)) | |
263 | nvbo->pin_refcnt--; | |
264 | return ret; | |
265 | } | |
266 | ||
267 | int | |
268 | nouveau_bo_unpin(struct nouveau_bo *nvbo) | |
269 | { | |
270 | struct drm_nouveau_private *dev_priv = nouveau_bdev(nvbo->bo.bdev); | |
271 | struct ttm_buffer_object *bo = &nvbo->bo; | |
78ad0f7b | 272 | int ret; |
6ee73861 BS |
273 | |
274 | if (--nvbo->pin_refcnt) | |
275 | return 0; | |
276 | ||
277 | ret = ttm_bo_reserve(bo, false, false, false, 0); | |
278 | if (ret) | |
279 | return ret; | |
280 | ||
78ad0f7b | 281 | nouveau_bo_placement_set(nvbo, bo->mem.placement, 0); |
6ee73861 | 282 | |
9d87fa21 | 283 | ret = ttm_bo_validate(bo, &nvbo->placement, false, false, false); |
6ee73861 BS |
284 | if (ret == 0) { |
285 | switch (bo->mem.mem_type) { | |
286 | case TTM_PL_VRAM: | |
287 | dev_priv->fb_aper_free += bo->mem.size; | |
288 | break; | |
289 | case TTM_PL_TT: | |
290 | dev_priv->gart_info.aper_free += bo->mem.size; | |
291 | break; | |
292 | default: | |
293 | break; | |
294 | } | |
295 | } | |
296 | ||
297 | ttm_bo_unreserve(bo); | |
298 | return ret; | |
299 | } | |
300 | ||
301 | int | |
302 | nouveau_bo_map(struct nouveau_bo *nvbo) | |
303 | { | |
304 | int ret; | |
305 | ||
306 | ret = ttm_bo_reserve(&nvbo->bo, false, false, false, 0); | |
307 | if (ret) | |
308 | return ret; | |
309 | ||
310 | ret = ttm_bo_kmap(&nvbo->bo, 0, nvbo->bo.mem.num_pages, &nvbo->kmap); | |
311 | ttm_bo_unreserve(&nvbo->bo); | |
312 | return ret; | |
313 | } | |
314 | ||
315 | void | |
316 | nouveau_bo_unmap(struct nouveau_bo *nvbo) | |
317 | { | |
9d59e8a1 BS |
318 | if (nvbo) |
319 | ttm_bo_kunmap(&nvbo->kmap); | |
6ee73861 BS |
320 | } |
321 | ||
322 | u16 | |
323 | nouveau_bo_rd16(struct nouveau_bo *nvbo, unsigned index) | |
324 | { | |
325 | bool is_iomem; | |
326 | u16 *mem = ttm_kmap_obj_virtual(&nvbo->kmap, &is_iomem); | |
327 | mem = &mem[index]; | |
328 | if (is_iomem) | |
329 | return ioread16_native((void __force __iomem *)mem); | |
330 | else | |
331 | return *mem; | |
332 | } | |
333 | ||
334 | void | |
335 | nouveau_bo_wr16(struct nouveau_bo *nvbo, unsigned index, u16 val) | |
336 | { | |
337 | bool is_iomem; | |
338 | u16 *mem = ttm_kmap_obj_virtual(&nvbo->kmap, &is_iomem); | |
339 | mem = &mem[index]; | |
340 | if (is_iomem) | |
341 | iowrite16_native(val, (void __force __iomem *)mem); | |
342 | else | |
343 | *mem = val; | |
344 | } | |
345 | ||
346 | u32 | |
347 | nouveau_bo_rd32(struct nouveau_bo *nvbo, unsigned index) | |
348 | { | |
349 | bool is_iomem; | |
350 | u32 *mem = ttm_kmap_obj_virtual(&nvbo->kmap, &is_iomem); | |
351 | mem = &mem[index]; | |
352 | if (is_iomem) | |
353 | return ioread32_native((void __force __iomem *)mem); | |
354 | else | |
355 | return *mem; | |
356 | } | |
357 | ||
358 | void | |
359 | nouveau_bo_wr32(struct nouveau_bo *nvbo, unsigned index, u32 val) | |
360 | { | |
361 | bool is_iomem; | |
362 | u32 *mem = ttm_kmap_obj_virtual(&nvbo->kmap, &is_iomem); | |
363 | mem = &mem[index]; | |
364 | if (is_iomem) | |
365 | iowrite32_native(val, (void __force __iomem *)mem); | |
366 | else | |
367 | *mem = val; | |
368 | } | |
369 | ||
370 | static struct ttm_backend * | |
371 | nouveau_bo_create_ttm_backend_entry(struct ttm_bo_device *bdev) | |
372 | { | |
373 | struct drm_nouveau_private *dev_priv = nouveau_bdev(bdev); | |
374 | struct drm_device *dev = dev_priv->dev; | |
375 | ||
376 | switch (dev_priv->gart_info.type) { | |
b694dfb2 | 377 | #if __OS_HAS_AGP |
6ee73861 BS |
378 | case NOUVEAU_GART_AGP: |
379 | return ttm_agp_backend_init(bdev, dev->agp->bridge); | |
b694dfb2 | 380 | #endif |
6ee73861 BS |
381 | case NOUVEAU_GART_SGDMA: |
382 | return nouveau_sgdma_init_ttm(dev); | |
383 | default: | |
384 | NV_ERROR(dev, "Unknown GART type %d\n", | |
385 | dev_priv->gart_info.type); | |
386 | break; | |
387 | } | |
388 | ||
389 | return NULL; | |
390 | } | |
391 | ||
392 | static int | |
393 | nouveau_bo_invalidate_caches(struct ttm_bo_device *bdev, uint32_t flags) | |
394 | { | |
395 | /* We'll do this from user space. */ | |
396 | return 0; | |
397 | } | |
398 | ||
399 | static int | |
400 | nouveau_bo_init_mem_type(struct ttm_bo_device *bdev, uint32_t type, | |
401 | struct ttm_mem_type_manager *man) | |
402 | { | |
403 | struct drm_nouveau_private *dev_priv = nouveau_bdev(bdev); | |
404 | struct drm_device *dev = dev_priv->dev; | |
405 | ||
406 | switch (type) { | |
407 | case TTM_PL_SYSTEM: | |
408 | man->flags = TTM_MEMTYPE_FLAG_MAPPABLE; | |
409 | man->available_caching = TTM_PL_MASK_CACHING; | |
410 | man->default_caching = TTM_PL_FLAG_CACHED; | |
411 | break; | |
412 | case TTM_PL_VRAM: | |
d961db75 | 413 | man->func = &ttm_bo_manager_func; |
6ee73861 | 414 | man->flags = TTM_MEMTYPE_FLAG_FIXED | |
f32f02fd | 415 | TTM_MEMTYPE_FLAG_MAPPABLE; |
6ee73861 BS |
416 | man->available_caching = TTM_PL_FLAG_UNCACHED | |
417 | TTM_PL_FLAG_WC; | |
418 | man->default_caching = TTM_PL_FLAG_WC; | |
fbd2895e BS |
419 | if (dev_priv->card_type == NV_50) |
420 | man->gpu_offset = 0x40000000; | |
421 | else | |
422 | man->gpu_offset = 0; | |
6ee73861 BS |
423 | break; |
424 | case TTM_PL_TT: | |
d961db75 | 425 | man->func = &ttm_bo_manager_func; |
6ee73861 BS |
426 | switch (dev_priv->gart_info.type) { |
427 | case NOUVEAU_GART_AGP: | |
f32f02fd | 428 | man->flags = TTM_MEMTYPE_FLAG_MAPPABLE; |
6ee73861 BS |
429 | man->available_caching = TTM_PL_FLAG_UNCACHED; |
430 | man->default_caching = TTM_PL_FLAG_UNCACHED; | |
431 | break; | |
432 | case NOUVEAU_GART_SGDMA: | |
433 | man->flags = TTM_MEMTYPE_FLAG_MAPPABLE | | |
434 | TTM_MEMTYPE_FLAG_CMA; | |
435 | man->available_caching = TTM_PL_MASK_CACHING; | |
436 | man->default_caching = TTM_PL_FLAG_CACHED; | |
437 | break; | |
438 | default: | |
439 | NV_ERROR(dev, "Unknown GART type: %d\n", | |
440 | dev_priv->gart_info.type); | |
441 | return -EINVAL; | |
442 | } | |
6ee73861 BS |
443 | man->gpu_offset = dev_priv->vm_gart_base; |
444 | break; | |
445 | default: | |
446 | NV_ERROR(dev, "Unsupported memory type %u\n", (unsigned)type); | |
447 | return -EINVAL; | |
448 | } | |
449 | return 0; | |
450 | } | |
451 | ||
452 | static void | |
453 | nouveau_bo_evict_flags(struct ttm_buffer_object *bo, struct ttm_placement *pl) | |
454 | { | |
455 | struct nouveau_bo *nvbo = nouveau_bo(bo); | |
456 | ||
457 | switch (bo->mem.mem_type) { | |
22fbd538 | 458 | case TTM_PL_VRAM: |
78ad0f7b FJ |
459 | nouveau_bo_placement_set(nvbo, TTM_PL_FLAG_TT, |
460 | TTM_PL_FLAG_SYSTEM); | |
22fbd538 | 461 | break; |
6ee73861 | 462 | default: |
78ad0f7b | 463 | nouveau_bo_placement_set(nvbo, TTM_PL_FLAG_SYSTEM, 0); |
6ee73861 BS |
464 | break; |
465 | } | |
22fbd538 FJ |
466 | |
467 | *pl = nvbo->placement; | |
6ee73861 BS |
468 | } |
469 | ||
470 | ||
471 | /* GPU-assisted copy using NV_MEMORY_TO_MEMORY_FORMAT, can access | |
472 | * TTM_PL_{VRAM,TT} directly. | |
473 | */ | |
a0af9add | 474 | |
6ee73861 BS |
475 | static int |
476 | nouveau_bo_move_accel_cleanup(struct nouveau_channel *chan, | |
9d87fa21 JG |
477 | struct nouveau_bo *nvbo, bool evict, |
478 | bool no_wait_reserve, bool no_wait_gpu, | |
6ee73861 BS |
479 | struct ttm_mem_reg *new_mem) |
480 | { | |
481 | struct nouveau_fence *fence = NULL; | |
482 | int ret; | |
483 | ||
484 | ret = nouveau_fence_new(chan, &fence, true); | |
485 | if (ret) | |
486 | return ret; | |
487 | ||
64798817 | 488 | ret = ttm_bo_move_accel_cleanup(&nvbo->bo, fence, NULL, evict, |
311ab694 | 489 | no_wait_reserve, no_wait_gpu, new_mem); |
382d62e5 | 490 | nouveau_fence_unref(&fence); |
6ee73861 BS |
491 | return ret; |
492 | } | |
493 | ||
494 | static inline uint32_t | |
f1ab0cc9 BS |
495 | nouveau_bo_mem_ctxdma(struct ttm_buffer_object *bo, |
496 | struct nouveau_channel *chan, struct ttm_mem_reg *mem) | |
6ee73861 | 497 | { |
f1ab0cc9 BS |
498 | struct nouveau_bo *nvbo = nouveau_bo(bo); |
499 | ||
500 | if (nvbo->no_vm) { | |
6ee73861 BS |
501 | if (mem->mem_type == TTM_PL_TT) |
502 | return NvDmaGART; | |
503 | return NvDmaVRAM; | |
504 | } | |
505 | ||
506 | if (mem->mem_type == TTM_PL_TT) | |
507 | return chan->gart_handle; | |
508 | return chan->vram_handle; | |
509 | } | |
510 | ||
511 | static int | |
f1ab0cc9 BS |
512 | nv50_bo_move_m2mf(struct nouveau_channel *chan, struct ttm_buffer_object *bo, |
513 | struct ttm_mem_reg *old_mem, struct ttm_mem_reg *new_mem) | |
6ee73861 | 514 | { |
6ee73861 | 515 | struct drm_nouveau_private *dev_priv = nouveau_bdev(bo->bdev); |
f1ab0cc9 BS |
516 | struct nouveau_bo *nvbo = nouveau_bo(bo); |
517 | u64 length = (new_mem->num_pages << PAGE_SHIFT); | |
518 | u64 src_offset, dst_offset; | |
6ee73861 BS |
519 | int ret; |
520 | ||
d961db75 BS |
521 | src_offset = old_mem->start << PAGE_SHIFT; |
522 | dst_offset = new_mem->start << PAGE_SHIFT; | |
f1ab0cc9 BS |
523 | if (!nvbo->no_vm) { |
524 | if (old_mem->mem_type == TTM_PL_VRAM) | |
6ee73861 | 525 | src_offset += dev_priv->vm_vram_base; |
6ee73861 | 526 | else |
f1ab0cc9 BS |
527 | src_offset += dev_priv->vm_gart_base; |
528 | ||
529 | if (new_mem->mem_type == TTM_PL_VRAM) | |
6ee73861 | 530 | dst_offset += dev_priv->vm_vram_base; |
f1ab0cc9 BS |
531 | else |
532 | dst_offset += dev_priv->vm_gart_base; | |
6ee73861 BS |
533 | } |
534 | ||
535 | ret = RING_SPACE(chan, 3); | |
536 | if (ret) | |
537 | return ret; | |
6ee73861 | 538 | |
f1ab0cc9 BS |
539 | BEGIN_RING(chan, NvSubM2MF, 0x0184, 2); |
540 | OUT_RING (chan, nouveau_bo_mem_ctxdma(bo, chan, old_mem)); | |
541 | OUT_RING (chan, nouveau_bo_mem_ctxdma(bo, chan, new_mem)); | |
542 | ||
543 | while (length) { | |
544 | u32 amount, stride, height; | |
545 | ||
5220b3c1 BS |
546 | amount = min(length, (u64)(4 * 1024 * 1024)); |
547 | stride = 16 * 4; | |
f1ab0cc9 BS |
548 | height = amount / stride; |
549 | ||
f13b3263 FJ |
550 | if (new_mem->mem_type == TTM_PL_VRAM && |
551 | nouveau_bo_tile_layout(nvbo)) { | |
f1ab0cc9 BS |
552 | ret = RING_SPACE(chan, 8); |
553 | if (ret) | |
554 | return ret; | |
555 | ||
556 | BEGIN_RING(chan, NvSubM2MF, 0x0200, 7); | |
557 | OUT_RING (chan, 0); | |
5220b3c1 | 558 | OUT_RING (chan, 0); |
f1ab0cc9 BS |
559 | OUT_RING (chan, stride); |
560 | OUT_RING (chan, height); | |
561 | OUT_RING (chan, 1); | |
562 | OUT_RING (chan, 0); | |
563 | OUT_RING (chan, 0); | |
564 | } else { | |
565 | ret = RING_SPACE(chan, 2); | |
566 | if (ret) | |
567 | return ret; | |
568 | ||
569 | BEGIN_RING(chan, NvSubM2MF, 0x0200, 1); | |
570 | OUT_RING (chan, 1); | |
571 | } | |
f13b3263 FJ |
572 | if (old_mem->mem_type == TTM_PL_VRAM && |
573 | nouveau_bo_tile_layout(nvbo)) { | |
f1ab0cc9 BS |
574 | ret = RING_SPACE(chan, 8); |
575 | if (ret) | |
576 | return ret; | |
577 | ||
578 | BEGIN_RING(chan, NvSubM2MF, 0x021c, 7); | |
579 | OUT_RING (chan, 0); | |
5220b3c1 | 580 | OUT_RING (chan, 0); |
f1ab0cc9 BS |
581 | OUT_RING (chan, stride); |
582 | OUT_RING (chan, height); | |
583 | OUT_RING (chan, 1); | |
584 | OUT_RING (chan, 0); | |
585 | OUT_RING (chan, 0); | |
586 | } else { | |
587 | ret = RING_SPACE(chan, 2); | |
588 | if (ret) | |
589 | return ret; | |
590 | ||
591 | BEGIN_RING(chan, NvSubM2MF, 0x021c, 1); | |
592 | OUT_RING (chan, 1); | |
593 | } | |
594 | ||
595 | ret = RING_SPACE(chan, 14); | |
6ee73861 BS |
596 | if (ret) |
597 | return ret; | |
f1ab0cc9 BS |
598 | |
599 | BEGIN_RING(chan, NvSubM2MF, 0x0238, 2); | |
600 | OUT_RING (chan, upper_32_bits(src_offset)); | |
601 | OUT_RING (chan, upper_32_bits(dst_offset)); | |
602 | BEGIN_RING(chan, NvSubM2MF, 0x030c, 8); | |
603 | OUT_RING (chan, lower_32_bits(src_offset)); | |
604 | OUT_RING (chan, lower_32_bits(dst_offset)); | |
605 | OUT_RING (chan, stride); | |
606 | OUT_RING (chan, stride); | |
607 | OUT_RING (chan, stride); | |
608 | OUT_RING (chan, height); | |
609 | OUT_RING (chan, 0x00000101); | |
610 | OUT_RING (chan, 0x00000000); | |
611 | BEGIN_RING(chan, NvSubM2MF, NV_MEMORY_TO_MEMORY_FORMAT_NOP, 1); | |
612 | OUT_RING (chan, 0); | |
613 | ||
614 | length -= amount; | |
615 | src_offset += amount; | |
616 | dst_offset += amount; | |
6ee73861 BS |
617 | } |
618 | ||
f1ab0cc9 BS |
619 | return 0; |
620 | } | |
621 | ||
622 | static int | |
623 | nv04_bo_move_m2mf(struct nouveau_channel *chan, struct ttm_buffer_object *bo, | |
624 | struct ttm_mem_reg *old_mem, struct ttm_mem_reg *new_mem) | |
625 | { | |
d961db75 BS |
626 | u32 src_offset = old_mem->start << PAGE_SHIFT; |
627 | u32 dst_offset = new_mem->start << PAGE_SHIFT; | |
f1ab0cc9 BS |
628 | u32 page_count = new_mem->num_pages; |
629 | int ret; | |
630 | ||
631 | ret = RING_SPACE(chan, 3); | |
632 | if (ret) | |
633 | return ret; | |
634 | ||
635 | BEGIN_RING(chan, NvSubM2MF, NV_MEMORY_TO_MEMORY_FORMAT_DMA_SOURCE, 2); | |
636 | OUT_RING (chan, nouveau_bo_mem_ctxdma(bo, chan, old_mem)); | |
637 | OUT_RING (chan, nouveau_bo_mem_ctxdma(bo, chan, new_mem)); | |
638 | ||
6ee73861 BS |
639 | page_count = new_mem->num_pages; |
640 | while (page_count) { | |
641 | int line_count = (page_count > 2047) ? 2047 : page_count; | |
642 | ||
6ee73861 BS |
643 | ret = RING_SPACE(chan, 11); |
644 | if (ret) | |
645 | return ret; | |
f1ab0cc9 | 646 | |
6ee73861 BS |
647 | BEGIN_RING(chan, NvSubM2MF, |
648 | NV_MEMORY_TO_MEMORY_FORMAT_OFFSET_IN, 8); | |
f1ab0cc9 BS |
649 | OUT_RING (chan, src_offset); |
650 | OUT_RING (chan, dst_offset); | |
651 | OUT_RING (chan, PAGE_SIZE); /* src_pitch */ | |
652 | OUT_RING (chan, PAGE_SIZE); /* dst_pitch */ | |
653 | OUT_RING (chan, PAGE_SIZE); /* line_length */ | |
654 | OUT_RING (chan, line_count); | |
655 | OUT_RING (chan, 0x00000101); | |
656 | OUT_RING (chan, 0x00000000); | |
6ee73861 | 657 | BEGIN_RING(chan, NvSubM2MF, NV_MEMORY_TO_MEMORY_FORMAT_NOP, 1); |
f1ab0cc9 | 658 | OUT_RING (chan, 0); |
6ee73861 BS |
659 | |
660 | page_count -= line_count; | |
661 | src_offset += (PAGE_SIZE * line_count); | |
662 | dst_offset += (PAGE_SIZE * line_count); | |
663 | } | |
664 | ||
f1ab0cc9 BS |
665 | return 0; |
666 | } | |
667 | ||
668 | static int | |
669 | nouveau_bo_move_m2mf(struct ttm_buffer_object *bo, int evict, bool intr, | |
670 | bool no_wait_reserve, bool no_wait_gpu, | |
671 | struct ttm_mem_reg *new_mem) | |
672 | { | |
673 | struct drm_nouveau_private *dev_priv = nouveau_bdev(bo->bdev); | |
674 | struct nouveau_bo *nvbo = nouveau_bo(bo); | |
675 | struct nouveau_channel *chan; | |
676 | int ret; | |
677 | ||
678 | chan = nvbo->channel; | |
6a6b73f2 | 679 | if (!chan || nvbo->no_vm) { |
f1ab0cc9 | 680 | chan = dev_priv->channel; |
6a6b73f2 BS |
681 | mutex_lock(&chan->mutex); |
682 | } | |
f1ab0cc9 BS |
683 | |
684 | if (dev_priv->card_type < NV_50) | |
685 | ret = nv04_bo_move_m2mf(chan, bo, &bo->mem, new_mem); | |
686 | else | |
687 | ret = nv50_bo_move_m2mf(chan, bo, &bo->mem, new_mem); | |
6a6b73f2 BS |
688 | if (ret == 0) { |
689 | ret = nouveau_bo_move_accel_cleanup(chan, nvbo, evict, | |
690 | no_wait_reserve, | |
691 | no_wait_gpu, new_mem); | |
692 | } | |
f1ab0cc9 | 693 | |
6a6b73f2 BS |
694 | if (chan == dev_priv->channel) |
695 | mutex_unlock(&chan->mutex); | |
696 | return ret; | |
6ee73861 BS |
697 | } |
698 | ||
699 | static int | |
700 | nouveau_bo_move_flipd(struct ttm_buffer_object *bo, bool evict, bool intr, | |
9d87fa21 JG |
701 | bool no_wait_reserve, bool no_wait_gpu, |
702 | struct ttm_mem_reg *new_mem) | |
6ee73861 BS |
703 | { |
704 | u32 placement_memtype = TTM_PL_FLAG_TT | TTM_PL_MASK_CACHING; | |
705 | struct ttm_placement placement; | |
706 | struct ttm_mem_reg tmp_mem; | |
707 | int ret; | |
708 | ||
709 | placement.fpfn = placement.lpfn = 0; | |
710 | placement.num_placement = placement.num_busy_placement = 1; | |
77e2b5ed | 711 | placement.placement = placement.busy_placement = &placement_memtype; |
6ee73861 BS |
712 | |
713 | tmp_mem = *new_mem; | |
714 | tmp_mem.mm_node = NULL; | |
9d87fa21 | 715 | ret = ttm_bo_mem_space(bo, &placement, &tmp_mem, intr, no_wait_reserve, no_wait_gpu); |
6ee73861 BS |
716 | if (ret) |
717 | return ret; | |
718 | ||
719 | ret = ttm_tt_bind(bo->ttm, &tmp_mem); | |
720 | if (ret) | |
721 | goto out; | |
722 | ||
9d87fa21 | 723 | ret = nouveau_bo_move_m2mf(bo, true, intr, no_wait_reserve, no_wait_gpu, &tmp_mem); |
6ee73861 BS |
724 | if (ret) |
725 | goto out; | |
726 | ||
9d87fa21 | 727 | ret = ttm_bo_move_ttm(bo, evict, no_wait_reserve, no_wait_gpu, new_mem); |
6ee73861 | 728 | out: |
42311ff9 | 729 | ttm_bo_mem_put(bo, &tmp_mem); |
6ee73861 BS |
730 | return ret; |
731 | } | |
732 | ||
733 | static int | |
734 | nouveau_bo_move_flips(struct ttm_buffer_object *bo, bool evict, bool intr, | |
9d87fa21 JG |
735 | bool no_wait_reserve, bool no_wait_gpu, |
736 | struct ttm_mem_reg *new_mem) | |
6ee73861 BS |
737 | { |
738 | u32 placement_memtype = TTM_PL_FLAG_TT | TTM_PL_MASK_CACHING; | |
739 | struct ttm_placement placement; | |
740 | struct ttm_mem_reg tmp_mem; | |
741 | int ret; | |
742 | ||
743 | placement.fpfn = placement.lpfn = 0; | |
744 | placement.num_placement = placement.num_busy_placement = 1; | |
77e2b5ed | 745 | placement.placement = placement.busy_placement = &placement_memtype; |
6ee73861 BS |
746 | |
747 | tmp_mem = *new_mem; | |
748 | tmp_mem.mm_node = NULL; | |
9d87fa21 | 749 | ret = ttm_bo_mem_space(bo, &placement, &tmp_mem, intr, no_wait_reserve, no_wait_gpu); |
6ee73861 BS |
750 | if (ret) |
751 | return ret; | |
752 | ||
9d87fa21 | 753 | ret = ttm_bo_move_ttm(bo, evict, no_wait_reserve, no_wait_gpu, &tmp_mem); |
6ee73861 BS |
754 | if (ret) |
755 | goto out; | |
756 | ||
9d87fa21 | 757 | ret = nouveau_bo_move_m2mf(bo, evict, intr, no_wait_reserve, no_wait_gpu, new_mem); |
6ee73861 BS |
758 | if (ret) |
759 | goto out; | |
760 | ||
761 | out: | |
42311ff9 | 762 | ttm_bo_mem_put(bo, &tmp_mem); |
6ee73861 BS |
763 | return ret; |
764 | } | |
765 | ||
766 | static int | |
a0af9add FJ |
767 | nouveau_bo_vm_bind(struct ttm_buffer_object *bo, struct ttm_mem_reg *new_mem, |
768 | struct nouveau_tile_reg **new_tile) | |
6ee73861 BS |
769 | { |
770 | struct drm_nouveau_private *dev_priv = nouveau_bdev(bo->bdev); | |
6ee73861 | 771 | struct drm_device *dev = dev_priv->dev; |
a0af9add FJ |
772 | struct nouveau_bo *nvbo = nouveau_bo(bo); |
773 | uint64_t offset; | |
6ee73861 BS |
774 | int ret; |
775 | ||
a0af9add FJ |
776 | if (nvbo->no_vm || new_mem->mem_type != TTM_PL_VRAM) { |
777 | /* Nothing to do. */ | |
778 | *new_tile = NULL; | |
779 | return 0; | |
780 | } | |
781 | ||
d961db75 | 782 | offset = new_mem->start << PAGE_SHIFT; |
6ee73861 | 783 | |
a0af9add | 784 | if (dev_priv->card_type == NV_50) { |
6ee73861 BS |
785 | ret = nv50_mem_vm_bind_linear(dev, |
786 | offset + dev_priv->vm_vram_base, | |
f13b3263 FJ |
787 | new_mem->size, |
788 | nouveau_bo_tile_layout(nvbo), | |
6ee73861 BS |
789 | offset); |
790 | if (ret) | |
791 | return ret; | |
a0af9add FJ |
792 | |
793 | } else if (dev_priv->card_type >= NV_10) { | |
794 | *new_tile = nv10_mem_set_tiling(dev, offset, new_mem->size, | |
795 | nvbo->tile_mode); | |
6ee73861 BS |
796 | } |
797 | ||
a0af9add FJ |
798 | return 0; |
799 | } | |
800 | ||
801 | static void | |
802 | nouveau_bo_vm_cleanup(struct ttm_buffer_object *bo, | |
803 | struct nouveau_tile_reg *new_tile, | |
804 | struct nouveau_tile_reg **old_tile) | |
805 | { | |
806 | struct drm_nouveau_private *dev_priv = nouveau_bdev(bo->bdev); | |
807 | struct drm_device *dev = dev_priv->dev; | |
808 | ||
809 | if (dev_priv->card_type >= NV_10 && | |
810 | dev_priv->card_type < NV_50) { | |
811 | if (*old_tile) | |
812 | nv10_mem_expire_tiling(dev, *old_tile, bo->sync_obj); | |
813 | ||
814 | *old_tile = new_tile; | |
815 | } | |
816 | } | |
817 | ||
818 | static int | |
819 | nouveau_bo_move(struct ttm_buffer_object *bo, bool evict, bool intr, | |
9d87fa21 JG |
820 | bool no_wait_reserve, bool no_wait_gpu, |
821 | struct ttm_mem_reg *new_mem) | |
a0af9add FJ |
822 | { |
823 | struct drm_nouveau_private *dev_priv = nouveau_bdev(bo->bdev); | |
824 | struct nouveau_bo *nvbo = nouveau_bo(bo); | |
825 | struct ttm_mem_reg *old_mem = &bo->mem; | |
826 | struct nouveau_tile_reg *new_tile = NULL; | |
827 | int ret = 0; | |
828 | ||
829 | ret = nouveau_bo_vm_bind(bo, new_mem, &new_tile); | |
830 | if (ret) | |
831 | return ret; | |
832 | ||
a0af9add | 833 | /* Fake bo copy. */ |
6ee73861 BS |
834 | if (old_mem->mem_type == TTM_PL_SYSTEM && !bo->ttm) { |
835 | BUG_ON(bo->mem.mm_node != NULL); | |
836 | bo->mem = *new_mem; | |
837 | new_mem->mm_node = NULL; | |
a0af9add | 838 | goto out; |
6ee73861 BS |
839 | } |
840 | ||
b8a6a804 BS |
841 | /* Software copy if the card isn't up and running yet. */ |
842 | if (!dev_priv->channel) { | |
843 | ret = ttm_bo_move_memcpy(bo, evict, no_wait_reserve, no_wait_gpu, new_mem); | |
844 | goto out; | |
845 | } | |
846 | ||
a0af9add FJ |
847 | /* Hardware assisted copy. */ |
848 | if (new_mem->mem_type == TTM_PL_SYSTEM) | |
9d87fa21 | 849 | ret = nouveau_bo_move_flipd(bo, evict, intr, no_wait_reserve, no_wait_gpu, new_mem); |
a0af9add | 850 | else if (old_mem->mem_type == TTM_PL_SYSTEM) |
9d87fa21 | 851 | ret = nouveau_bo_move_flips(bo, evict, intr, no_wait_reserve, no_wait_gpu, new_mem); |
a0af9add | 852 | else |
9d87fa21 | 853 | ret = nouveau_bo_move_m2mf(bo, evict, intr, no_wait_reserve, no_wait_gpu, new_mem); |
6ee73861 | 854 | |
a0af9add FJ |
855 | if (!ret) |
856 | goto out; | |
857 | ||
858 | /* Fallback to software copy. */ | |
9d87fa21 | 859 | ret = ttm_bo_move_memcpy(bo, evict, no_wait_reserve, no_wait_gpu, new_mem); |
a0af9add FJ |
860 | |
861 | out: | |
862 | if (ret) | |
863 | nouveau_bo_vm_cleanup(bo, NULL, &new_tile); | |
864 | else | |
865 | nouveau_bo_vm_cleanup(bo, new_tile, &nvbo->tile); | |
866 | ||
867 | return ret; | |
6ee73861 BS |
868 | } |
869 | ||
870 | static int | |
871 | nouveau_bo_verify_access(struct ttm_buffer_object *bo, struct file *filp) | |
872 | { | |
873 | return 0; | |
874 | } | |
875 | ||
f32f02fd JG |
876 | static int |
877 | nouveau_ttm_io_mem_reserve(struct ttm_bo_device *bdev, struct ttm_mem_reg *mem) | |
878 | { | |
879 | struct ttm_mem_type_manager *man = &bdev->man[mem->mem_type]; | |
880 | struct drm_nouveau_private *dev_priv = nouveau_bdev(bdev); | |
881 | struct drm_device *dev = dev_priv->dev; | |
882 | ||
883 | mem->bus.addr = NULL; | |
884 | mem->bus.offset = 0; | |
885 | mem->bus.size = mem->num_pages << PAGE_SHIFT; | |
886 | mem->bus.base = 0; | |
887 | mem->bus.is_iomem = false; | |
888 | if (!(man->flags & TTM_MEMTYPE_FLAG_MAPPABLE)) | |
889 | return -EINVAL; | |
890 | switch (mem->mem_type) { | |
891 | case TTM_PL_SYSTEM: | |
892 | /* System memory */ | |
893 | return 0; | |
894 | case TTM_PL_TT: | |
895 | #if __OS_HAS_AGP | |
896 | if (dev_priv->gart_info.type == NOUVEAU_GART_AGP) { | |
d961db75 | 897 | mem->bus.offset = mem->start << PAGE_SHIFT; |
f32f02fd JG |
898 | mem->bus.base = dev_priv->gart_info.aper_base; |
899 | mem->bus.is_iomem = true; | |
900 | } | |
901 | #endif | |
902 | break; | |
903 | case TTM_PL_VRAM: | |
d961db75 | 904 | mem->bus.offset = mem->start << PAGE_SHIFT; |
01d73a69 | 905 | mem->bus.base = pci_resource_start(dev->pdev, 1); |
f32f02fd JG |
906 | mem->bus.is_iomem = true; |
907 | break; | |
908 | default: | |
909 | return -EINVAL; | |
910 | } | |
911 | return 0; | |
912 | } | |
913 | ||
914 | static void | |
915 | nouveau_ttm_io_mem_free(struct ttm_bo_device *bdev, struct ttm_mem_reg *mem) | |
916 | { | |
917 | } | |
918 | ||
919 | static int | |
920 | nouveau_ttm_fault_reserve_notify(struct ttm_buffer_object *bo) | |
921 | { | |
e1429b4c BS |
922 | struct drm_nouveau_private *dev_priv = nouveau_bdev(bo->bdev); |
923 | struct nouveau_bo *nvbo = nouveau_bo(bo); | |
924 | ||
925 | /* as long as the bo isn't in vram, and isn't tiled, we've got | |
926 | * nothing to do here. | |
927 | */ | |
928 | if (bo->mem.mem_type != TTM_PL_VRAM) { | |
f13b3263 FJ |
929 | if (dev_priv->card_type < NV_50 || |
930 | !nouveau_bo_tile_layout(nvbo)) | |
e1429b4c BS |
931 | return 0; |
932 | } | |
933 | ||
934 | /* make sure bo is in mappable vram */ | |
d961db75 | 935 | if (bo->mem.start + bo->mem.num_pages < dev_priv->fb_mappable_pages) |
e1429b4c BS |
936 | return 0; |
937 | ||
938 | ||
939 | nvbo->placement.fpfn = 0; | |
940 | nvbo->placement.lpfn = dev_priv->fb_mappable_pages; | |
941 | nouveau_bo_placement_set(nvbo, TTM_PL_VRAM, 0); | |
942 | return ttm_bo_validate(bo, &nvbo->placement, false, true, false); | |
f32f02fd JG |
943 | } |
944 | ||
332b242f FJ |
945 | void |
946 | nouveau_bo_fence(struct nouveau_bo *nvbo, struct nouveau_fence *fence) | |
947 | { | |
948 | spin_lock(&nvbo->bo.bdev->fence_lock); | |
949 | __nouveau_fence_unref(&nvbo->bo.sync_obj); | |
950 | ||
951 | if (likely(fence)) | |
952 | nvbo->bo.sync_obj = nouveau_fence_ref(fence); | |
953 | ||
954 | spin_unlock(&nvbo->bo.bdev->fence_lock); | |
955 | } | |
956 | ||
6ee73861 BS |
957 | struct ttm_bo_driver nouveau_bo_driver = { |
958 | .create_ttm_backend_entry = nouveau_bo_create_ttm_backend_entry, | |
959 | .invalidate_caches = nouveau_bo_invalidate_caches, | |
960 | .init_mem_type = nouveau_bo_init_mem_type, | |
961 | .evict_flags = nouveau_bo_evict_flags, | |
962 | .move = nouveau_bo_move, | |
963 | .verify_access = nouveau_bo_verify_access, | |
382d62e5 MS |
964 | .sync_obj_signaled = __nouveau_fence_signalled, |
965 | .sync_obj_wait = __nouveau_fence_wait, | |
966 | .sync_obj_flush = __nouveau_fence_flush, | |
967 | .sync_obj_unref = __nouveau_fence_unref, | |
968 | .sync_obj_ref = __nouveau_fence_ref, | |
f32f02fd JG |
969 | .fault_reserve_notify = &nouveau_ttm_fault_reserve_notify, |
970 | .io_mem_reserve = &nouveau_ttm_io_mem_reserve, | |
971 | .io_mem_free = &nouveau_ttm_io_mem_free, | |
6ee73861 BS |
972 | }; |
973 |