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6ee73861 BS |
1 | /* |
2 | * Copyright 2007 Dave Airlied | |
3 | * All Rights Reserved. | |
4 | * | |
5 | * Permission is hereby granted, free of charge, to any person obtaining a | |
6 | * copy of this software and associated documentation files (the "Software"), | |
7 | * to deal in the Software without restriction, including without limitation | |
8 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
9 | * and/or sell copies of the Software, and to permit persons to whom the | |
10 | * Software is furnished to do so, subject to the following conditions: | |
11 | * | |
12 | * The above copyright notice and this permission notice (including the next | |
13 | * paragraph) shall be included in all copies or substantial portions of the | |
14 | * Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
20 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
21 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
22 | * OTHER DEALINGS IN THE SOFTWARE. | |
23 | */ | |
24 | /* | |
25 | * Authors: Dave Airlied <airlied@linux.ie> | |
26 | * Ben Skeggs <darktama@iinet.net.au> | |
27 | * Jeremy Kolb <jkolb@brandeis.edu> | |
28 | */ | |
29 | ||
fdb751ef | 30 | #include <linux/dma-mapping.h> |
3e2b756b | 31 | #include <linux/swiotlb.h> |
6ee73861 | 32 | |
4dc28134 | 33 | #include "nouveau_drv.h" |
6ee73861 | 34 | #include "nouveau_dma.h" |
d375e7d5 | 35 | #include "nouveau_fence.h" |
6ee73861 | 36 | |
ebb945a9 BS |
37 | #include "nouveau_bo.h" |
38 | #include "nouveau_ttm.h" | |
39 | #include "nouveau_gem.h" | |
9ce523cc | 40 | #include "nouveau_mem.h" |
24e8375b | 41 | #include "nouveau_vmm.h" |
a510604d | 42 | |
bc9e7b9a BS |
43 | /* |
44 | * NV10-NV40 tiling helpers | |
45 | */ | |
46 | ||
47 | static void | |
ebb945a9 BS |
48 | nv10_bo_update_tile_region(struct drm_device *dev, struct nouveau_drm_tile *reg, |
49 | u32 addr, u32 size, u32 pitch, u32 flags) | |
bc9e7b9a | 50 | { |
77145f1c | 51 | struct nouveau_drm *drm = nouveau_drm(dev); |
ebb945a9 | 52 | int i = reg - drm->tile.reg; |
1167c6bc | 53 | struct nvkm_device *device = nvxx_device(&drm->client.device); |
c85ee6ca | 54 | struct nvkm_fb *fb = device->fb; |
b1e4553c | 55 | struct nvkm_fb_tile *tile = &fb->tile.region[i]; |
bc9e7b9a | 56 | |
ebb945a9 | 57 | nouveau_fence_unref(®->fence); |
bc9e7b9a BS |
58 | |
59 | if (tile->pitch) | |
03c8952f | 60 | nvkm_fb_tile_fini(fb, i, tile); |
bc9e7b9a BS |
61 | |
62 | if (pitch) | |
03c8952f | 63 | nvkm_fb_tile_init(fb, i, addr, size, pitch, flags, tile); |
bc9e7b9a | 64 | |
03c8952f | 65 | nvkm_fb_tile_prog(fb, i, tile); |
bc9e7b9a BS |
66 | } |
67 | ||
ebb945a9 | 68 | static struct nouveau_drm_tile * |
bc9e7b9a BS |
69 | nv10_bo_get_tile_region(struct drm_device *dev, int i) |
70 | { | |
77145f1c | 71 | struct nouveau_drm *drm = nouveau_drm(dev); |
ebb945a9 | 72 | struct nouveau_drm_tile *tile = &drm->tile.reg[i]; |
bc9e7b9a | 73 | |
ebb945a9 | 74 | spin_lock(&drm->tile.lock); |
bc9e7b9a BS |
75 | |
76 | if (!tile->used && | |
77 | (!tile->fence || nouveau_fence_done(tile->fence))) | |
78 | tile->used = true; | |
79 | else | |
80 | tile = NULL; | |
81 | ||
ebb945a9 | 82 | spin_unlock(&drm->tile.lock); |
bc9e7b9a BS |
83 | return tile; |
84 | } | |
85 | ||
86 | static void | |
ebb945a9 | 87 | nv10_bo_put_tile_region(struct drm_device *dev, struct nouveau_drm_tile *tile, |
f54d1867 | 88 | struct dma_fence *fence) |
bc9e7b9a | 89 | { |
77145f1c | 90 | struct nouveau_drm *drm = nouveau_drm(dev); |
bc9e7b9a BS |
91 | |
92 | if (tile) { | |
ebb945a9 | 93 | spin_lock(&drm->tile.lock); |
f54d1867 | 94 | tile->fence = (struct nouveau_fence *)dma_fence_get(fence); |
bc9e7b9a | 95 | tile->used = false; |
ebb945a9 | 96 | spin_unlock(&drm->tile.lock); |
bc9e7b9a BS |
97 | } |
98 | } | |
99 | ||
ebb945a9 BS |
100 | static struct nouveau_drm_tile * |
101 | nv10_bo_set_tiling(struct drm_device *dev, u32 addr, | |
7760a2e3 | 102 | u32 size, u32 pitch, u32 zeta) |
bc9e7b9a | 103 | { |
77145f1c | 104 | struct nouveau_drm *drm = nouveau_drm(dev); |
1167c6bc | 105 | struct nvkm_fb *fb = nvxx_fb(&drm->client.device); |
ebb945a9 | 106 | struct nouveau_drm_tile *tile, *found = NULL; |
bc9e7b9a BS |
107 | int i; |
108 | ||
b1e4553c | 109 | for (i = 0; i < fb->tile.regions; i++) { |
bc9e7b9a BS |
110 | tile = nv10_bo_get_tile_region(dev, i); |
111 | ||
112 | if (pitch && !found) { | |
113 | found = tile; | |
114 | continue; | |
115 | ||
b1e4553c | 116 | } else if (tile && fb->tile.region[i].pitch) { |
bc9e7b9a BS |
117 | /* Kill an unused tile region. */ |
118 | nv10_bo_update_tile_region(dev, tile, 0, 0, 0, 0); | |
119 | } | |
120 | ||
121 | nv10_bo_put_tile_region(dev, tile, NULL); | |
122 | } | |
123 | ||
124 | if (found) | |
7760a2e3 | 125 | nv10_bo_update_tile_region(dev, found, addr, size, pitch, zeta); |
bc9e7b9a BS |
126 | return found; |
127 | } | |
128 | ||
6ee73861 BS |
129 | static void |
130 | nouveau_bo_del_ttm(struct ttm_buffer_object *bo) | |
131 | { | |
ebb945a9 BS |
132 | struct nouveau_drm *drm = nouveau_bdev(bo->bdev); |
133 | struct drm_device *dev = drm->dev; | |
6ee73861 BS |
134 | struct nouveau_bo *nvbo = nouveau_bo(bo); |
135 | ||
55fb74ad | 136 | if (unlikely(nvbo->gem.filp)) |
6ee73861 | 137 | DRM_ERROR("bo %p still attached to GEM object\n", bo); |
4f385599 | 138 | WARN_ON(nvbo->pin_refcnt > 0); |
bc9e7b9a | 139 | nv10_bo_put_tile_region(dev, nvbo->tile, NULL); |
6ee73861 BS |
140 | kfree(nvbo); |
141 | } | |
142 | ||
4d8b3d34 BS |
143 | static inline u64 |
144 | roundup_64(u64 x, u32 y) | |
145 | { | |
146 | x += y - 1; | |
147 | do_div(x, y); | |
148 | return x * y; | |
149 | } | |
150 | ||
a0af9add | 151 | static void |
db5c8e29 | 152 | nouveau_bo_fixup_align(struct nouveau_bo *nvbo, u32 flags, |
4d8b3d34 | 153 | int *align, u64 *size) |
a0af9add | 154 | { |
ebb945a9 | 155 | struct nouveau_drm *drm = nouveau_bdev(nvbo->bo.bdev); |
1167c6bc | 156 | struct nvif_device *device = &drm->client.device; |
a0af9add | 157 | |
967e7bde | 158 | if (device->info.family < NV_DEVICE_INFO_V0_TESLA) { |
7760a2e3 | 159 | if (nvbo->mode) { |
967e7bde | 160 | if (device->info.chipset >= 0x40) { |
a0af9add | 161 | *align = 65536; |
7760a2e3 | 162 | *size = roundup_64(*size, 64 * nvbo->mode); |
a0af9add | 163 | |
967e7bde | 164 | } else if (device->info.chipset >= 0x30) { |
a0af9add | 165 | *align = 32768; |
7760a2e3 | 166 | *size = roundup_64(*size, 64 * nvbo->mode); |
a0af9add | 167 | |
967e7bde | 168 | } else if (device->info.chipset >= 0x20) { |
a0af9add | 169 | *align = 16384; |
7760a2e3 | 170 | *size = roundup_64(*size, 64 * nvbo->mode); |
a0af9add | 171 | |
967e7bde | 172 | } else if (device->info.chipset >= 0x10) { |
a0af9add | 173 | *align = 16384; |
7760a2e3 | 174 | *size = roundup_64(*size, 32 * nvbo->mode); |
a0af9add FJ |
175 | } |
176 | } | |
bfd83aca | 177 | } else { |
7760a2e3 BS |
178 | *size = roundup_64(*size, (1 << nvbo->page)); |
179 | *align = max((1 << nvbo->page), *align); | |
a0af9add FJ |
180 | } |
181 | ||
4d8b3d34 | 182 | *size = roundup_64(*size, PAGE_SIZE); |
a0af9add FJ |
183 | } |
184 | ||
6ee73861 | 185 | int |
4d8b3d34 | 186 | nouveau_bo_new(struct nouveau_cli *cli, u64 size, int align, |
7375c95b | 187 | uint32_t flags, uint32_t tile_mode, uint32_t tile_flags, |
bb6178b0 | 188 | struct sg_table *sg, struct reservation_object *robj, |
7375c95b | 189 | struct nouveau_bo **pnvbo) |
6ee73861 | 190 | { |
e75c091b | 191 | struct nouveau_drm *drm = cli->drm; |
6ee73861 | 192 | struct nouveau_bo *nvbo; |
57de4ba9 | 193 | size_t acc_size; |
f91bac5b | 194 | int ret; |
22b33e8e | 195 | int type = ttm_bo_type_device; |
0108bc80 | 196 | |
4d8b3d34 BS |
197 | if (!size) { |
198 | NV_WARN(drm, "skipped size %016llx\n", size); | |
0108bc80 ML |
199 | return -EINVAL; |
200 | } | |
22b33e8e DA |
201 | |
202 | if (sg) | |
203 | type = ttm_bo_type_sg; | |
6ee73861 BS |
204 | |
205 | nvbo = kzalloc(sizeof(struct nouveau_bo), GFP_KERNEL); | |
206 | if (!nvbo) | |
207 | return -ENOMEM; | |
208 | INIT_LIST_HEAD(&nvbo->head); | |
209 | INIT_LIST_HEAD(&nvbo->entry); | |
fd2871af | 210 | INIT_LIST_HEAD(&nvbo->vma_list); |
ebb945a9 | 211 | nvbo->bo.bdev = &drm->ttm.bdev; |
bab7cc18 | 212 | nvbo->cli = cli; |
6ee73861 | 213 | |
1167c6bc | 214 | if (!nvxx_device(&drm->client.device)->func->cpu_coherent) |
bad3d80f | 215 | nvbo->force_coherent = flags & TTM_PL_FLAG_UNCACHED; |
c3a0c771 | 216 | |
7760a2e3 BS |
217 | if (cli->device.info.family >= NV_DEVICE_INFO_V0_FERMI) { |
218 | nvbo->kind = (tile_flags & 0x0000ff00) >> 8; | |
219 | nvbo->comp = gf100_pte_storage_type_map[nvbo->kind] != nvbo->kind; | |
220 | } else | |
221 | if (cli->device.info.family >= NV_DEVICE_INFO_V0_TESLA) { | |
222 | nvbo->kind = (tile_flags & 0x00007f00) >> 8; | |
223 | nvbo->comp = (tile_flags & 0x00030000) >> 16; | |
224 | } else { | |
225 | nvbo->zeta = (tile_flags & 0x00000007); | |
226 | } | |
227 | nvbo->mode = tile_mode; | |
228 | nvbo->contig = !(tile_flags & NOUVEAU_GEM_TILE_NONCONTIG); | |
229 | ||
230 | nvbo->page = 12; | |
3ee6f5b5 | 231 | if (drm->client.vm) { |
f91bac5b | 232 | if (!(flags & TTM_PL_FLAG_TT) && size > 256 * 1024) |
7760a2e3 BS |
233 | nvbo->page = drm->client.vm->mmu->lpg_shift; |
234 | else { | |
235 | if (cli->device.info.family >= NV_DEVICE_INFO_V0_FERMI) | |
236 | nvbo->kind = gf100_pte_storage_type_map[nvbo->kind]; | |
237 | nvbo->comp = 0; | |
238 | } | |
f91bac5b BS |
239 | } |
240 | ||
241 | nouveau_bo_fixup_align(nvbo, flags, &align, &size); | |
fd2871af BS |
242 | nvbo->bo.mem.num_pages = size >> PAGE_SHIFT; |
243 | nouveau_bo_placement_set(nvbo, flags, 0); | |
6ee73861 | 244 | |
ebb945a9 | 245 | acc_size = ttm_bo_dma_acc_size(&drm->ttm.bdev, size, |
57de4ba9 JG |
246 | sizeof(struct nouveau_bo)); |
247 | ||
ebb945a9 | 248 | ret = ttm_bo_init(&drm->ttm.bdev, &nvbo->bo, size, |
22b33e8e | 249 | type, &nvbo->placement, |
0b91c4a1 | 250 | align >> PAGE_SHIFT, false, NULL, acc_size, sg, |
bb6178b0 | 251 | robj, nouveau_bo_del_ttm); |
6ee73861 BS |
252 | if (ret) { |
253 | /* ttm will call nouveau_bo_del_ttm if it fails.. */ | |
254 | return ret; | |
255 | } | |
256 | ||
6ee73861 BS |
257 | *pnvbo = nvbo; |
258 | return 0; | |
259 | } | |
260 | ||
78ad0f7b | 261 | static void |
f1217ed0 | 262 | set_placement_list(struct ttm_place *pl, unsigned *n, uint32_t type, uint32_t flags) |
78ad0f7b FJ |
263 | { |
264 | *n = 0; | |
265 | ||
266 | if (type & TTM_PL_FLAG_VRAM) | |
f1217ed0 | 267 | pl[(*n)++].flags = TTM_PL_FLAG_VRAM | flags; |
78ad0f7b | 268 | if (type & TTM_PL_FLAG_TT) |
f1217ed0 | 269 | pl[(*n)++].flags = TTM_PL_FLAG_TT | flags; |
78ad0f7b | 270 | if (type & TTM_PL_FLAG_SYSTEM) |
f1217ed0 | 271 | pl[(*n)++].flags = TTM_PL_FLAG_SYSTEM | flags; |
78ad0f7b FJ |
272 | } |
273 | ||
699ddfd9 FJ |
274 | static void |
275 | set_placement_range(struct nouveau_bo *nvbo, uint32_t type) | |
276 | { | |
ebb945a9 | 277 | struct nouveau_drm *drm = nouveau_bdev(nvbo->bo.bdev); |
1167c6bc | 278 | u32 vram_pages = drm->client.device.info.ram_size >> PAGE_SHIFT; |
f1217ed0 | 279 | unsigned i, fpfn, lpfn; |
699ddfd9 | 280 | |
1167c6bc | 281 | if (drm->client.device.info.family == NV_DEVICE_INFO_V0_CELSIUS && |
7760a2e3 | 282 | nvbo->mode && (type & TTM_PL_FLAG_VRAM) && |
4beb116a | 283 | nvbo->bo.mem.num_pages < vram_pages / 4) { |
699ddfd9 FJ |
284 | /* |
285 | * Make sure that the color and depth buffers are handled | |
286 | * by independent memory controller units. Up to a 9x | |
287 | * speed up when alpha-blending and depth-test are enabled | |
288 | * at the same time. | |
289 | */ | |
7760a2e3 | 290 | if (nvbo->zeta) { |
f1217ed0 CK |
291 | fpfn = vram_pages / 2; |
292 | lpfn = ~0; | |
699ddfd9 | 293 | } else { |
f1217ed0 CK |
294 | fpfn = 0; |
295 | lpfn = vram_pages / 2; | |
296 | } | |
297 | for (i = 0; i < nvbo->placement.num_placement; ++i) { | |
298 | nvbo->placements[i].fpfn = fpfn; | |
299 | nvbo->placements[i].lpfn = lpfn; | |
300 | } | |
301 | for (i = 0; i < nvbo->placement.num_busy_placement; ++i) { | |
302 | nvbo->busy_placements[i].fpfn = fpfn; | |
303 | nvbo->busy_placements[i].lpfn = lpfn; | |
699ddfd9 FJ |
304 | } |
305 | } | |
306 | } | |
307 | ||
6ee73861 | 308 | void |
78ad0f7b | 309 | nouveau_bo_placement_set(struct nouveau_bo *nvbo, uint32_t type, uint32_t busy) |
6ee73861 | 310 | { |
78ad0f7b | 311 | struct ttm_placement *pl = &nvbo->placement; |
c3a0c771 AC |
312 | uint32_t flags = (nvbo->force_coherent ? TTM_PL_FLAG_UNCACHED : |
313 | TTM_PL_MASK_CACHING) | | |
314 | (nvbo->pin_refcnt ? TTM_PL_FLAG_NO_EVICT : 0); | |
78ad0f7b FJ |
315 | |
316 | pl->placement = nvbo->placements; | |
317 | set_placement_list(nvbo->placements, &pl->num_placement, | |
318 | type, flags); | |
319 | ||
320 | pl->busy_placement = nvbo->busy_placements; | |
321 | set_placement_list(nvbo->busy_placements, &pl->num_busy_placement, | |
322 | type | busy, flags); | |
699ddfd9 FJ |
323 | |
324 | set_placement_range(nvbo, type); | |
6ee73861 BS |
325 | } |
326 | ||
327 | int | |
ad76b3f7 | 328 | nouveau_bo_pin(struct nouveau_bo *nvbo, uint32_t memtype, bool contig) |
6ee73861 | 329 | { |
ebb945a9 | 330 | struct nouveau_drm *drm = nouveau_bdev(nvbo->bo.bdev); |
6ee73861 | 331 | struct ttm_buffer_object *bo = &nvbo->bo; |
ad76b3f7 | 332 | bool force = false, evict = false; |
78ad0f7b | 333 | int ret; |
6ee73861 | 334 | |
dfd5e50e | 335 | ret = ttm_bo_reserve(bo, false, false, NULL); |
0ae6d7bc | 336 | if (ret) |
50ab2e52 | 337 | return ret; |
0ae6d7bc | 338 | |
1167c6bc | 339 | if (drm->client.device.info.family >= NV_DEVICE_INFO_V0_TESLA && |
ad76b3f7 | 340 | memtype == TTM_PL_FLAG_VRAM && contig) { |
7760a2e3 BS |
341 | if (!nvbo->contig) { |
342 | nvbo->contig = true; | |
ad76b3f7 | 343 | force = true; |
7760a2e3 | 344 | evict = true; |
ad76b3f7 | 345 | } |
6ee73861 BS |
346 | } |
347 | ||
ad76b3f7 BS |
348 | if (nvbo->pin_refcnt) { |
349 | if (!(memtype & (1 << bo->mem.mem_type)) || evict) { | |
350 | NV_ERROR(drm, "bo %p pinned elsewhere: " | |
351 | "0x%08x vs 0x%08x\n", bo, | |
352 | 1 << bo->mem.mem_type, memtype); | |
353 | ret = -EBUSY; | |
354 | } | |
355 | nvbo->pin_refcnt++; | |
50ab2e52 | 356 | goto out; |
ad76b3f7 BS |
357 | } |
358 | ||
359 | if (evict) { | |
360 | nouveau_bo_placement_set(nvbo, TTM_PL_FLAG_TT, 0); | |
361 | ret = nouveau_bo_validate(nvbo, false, false); | |
362 | if (ret) | |
363 | goto out; | |
364 | } | |
6ee73861 | 365 | |
ad76b3f7 | 366 | nvbo->pin_refcnt++; |
78ad0f7b | 367 | nouveau_bo_placement_set(nvbo, memtype, 0); |
6ee73861 | 368 | |
50ab2e52 BS |
369 | /* drop pin_refcnt temporarily, so we don't trip the assertion |
370 | * in nouveau_bo_move() that makes sure we're not trying to | |
371 | * move a pinned buffer | |
372 | */ | |
373 | nvbo->pin_refcnt--; | |
97a875cb | 374 | ret = nouveau_bo_validate(nvbo, false, false); |
6aac6ced BS |
375 | if (ret) |
376 | goto out; | |
50ab2e52 | 377 | nvbo->pin_refcnt++; |
6aac6ced BS |
378 | |
379 | switch (bo->mem.mem_type) { | |
380 | case TTM_PL_VRAM: | |
381 | drm->gem.vram_available -= bo->mem.size; | |
382 | break; | |
383 | case TTM_PL_TT: | |
384 | drm->gem.gart_available -= bo->mem.size; | |
385 | break; | |
386 | default: | |
387 | break; | |
6ee73861 | 388 | } |
5be5a15a | 389 | |
6ee73861 | 390 | out: |
ad76b3f7 | 391 | if (force && ret) |
7760a2e3 | 392 | nvbo->contig = false; |
0ae6d7bc | 393 | ttm_bo_unreserve(bo); |
6ee73861 BS |
394 | return ret; |
395 | } | |
396 | ||
397 | int | |
398 | nouveau_bo_unpin(struct nouveau_bo *nvbo) | |
399 | { | |
ebb945a9 | 400 | struct nouveau_drm *drm = nouveau_bdev(nvbo->bo.bdev); |
6ee73861 | 401 | struct ttm_buffer_object *bo = &nvbo->bo; |
4f385599 | 402 | int ret, ref; |
6ee73861 | 403 | |
dfd5e50e | 404 | ret = ttm_bo_reserve(bo, false, false, NULL); |
6ee73861 BS |
405 | if (ret) |
406 | return ret; | |
407 | ||
4f385599 ML |
408 | ref = --nvbo->pin_refcnt; |
409 | WARN_ON_ONCE(ref < 0); | |
410 | if (ref) | |
0ae6d7bc DV |
411 | goto out; |
412 | ||
78ad0f7b | 413 | nouveau_bo_placement_set(nvbo, bo->mem.placement, 0); |
6ee73861 | 414 | |
97a875cb | 415 | ret = nouveau_bo_validate(nvbo, false, false); |
6ee73861 BS |
416 | if (ret == 0) { |
417 | switch (bo->mem.mem_type) { | |
418 | case TTM_PL_VRAM: | |
ebb945a9 | 419 | drm->gem.vram_available += bo->mem.size; |
6ee73861 BS |
420 | break; |
421 | case TTM_PL_TT: | |
ebb945a9 | 422 | drm->gem.gart_available += bo->mem.size; |
6ee73861 BS |
423 | break; |
424 | default: | |
425 | break; | |
426 | } | |
427 | } | |
428 | ||
0ae6d7bc | 429 | out: |
6ee73861 BS |
430 | ttm_bo_unreserve(bo); |
431 | return ret; | |
432 | } | |
433 | ||
434 | int | |
435 | nouveau_bo_map(struct nouveau_bo *nvbo) | |
436 | { | |
437 | int ret; | |
438 | ||
dfd5e50e | 439 | ret = ttm_bo_reserve(&nvbo->bo, false, false, NULL); |
6ee73861 BS |
440 | if (ret) |
441 | return ret; | |
442 | ||
36a471ba | 443 | ret = ttm_bo_kmap(&nvbo->bo, 0, nvbo->bo.mem.num_pages, &nvbo->kmap); |
c3a0c771 | 444 | |
6ee73861 BS |
445 | ttm_bo_unreserve(&nvbo->bo); |
446 | return ret; | |
447 | } | |
448 | ||
449 | void | |
450 | nouveau_bo_unmap(struct nouveau_bo *nvbo) | |
451 | { | |
c3a0c771 AC |
452 | if (!nvbo) |
453 | return; | |
454 | ||
36a471ba | 455 | ttm_bo_kunmap(&nvbo->kmap); |
6ee73861 BS |
456 | } |
457 | ||
b22870ba AC |
458 | void |
459 | nouveau_bo_sync_for_device(struct nouveau_bo *nvbo) | |
460 | { | |
461 | struct nouveau_drm *drm = nouveau_bdev(nvbo->bo.bdev); | |
1167c6bc | 462 | struct nvkm_device *device = nvxx_device(&drm->client.device); |
b22870ba AC |
463 | struct ttm_dma_tt *ttm_dma = (struct ttm_dma_tt *)nvbo->bo.ttm; |
464 | int i; | |
465 | ||
466 | if (!ttm_dma) | |
467 | return; | |
468 | ||
469 | /* Don't waste time looping if the object is coherent */ | |
470 | if (nvbo->force_coherent) | |
471 | return; | |
472 | ||
473 | for (i = 0; i < ttm_dma->ttm.num_pages; i++) | |
26c9e8ef BS |
474 | dma_sync_single_for_device(device->dev, ttm_dma->dma_address[i], |
475 | PAGE_SIZE, DMA_TO_DEVICE); | |
b22870ba AC |
476 | } |
477 | ||
478 | void | |
479 | nouveau_bo_sync_for_cpu(struct nouveau_bo *nvbo) | |
480 | { | |
481 | struct nouveau_drm *drm = nouveau_bdev(nvbo->bo.bdev); | |
1167c6bc | 482 | struct nvkm_device *device = nvxx_device(&drm->client.device); |
b22870ba AC |
483 | struct ttm_dma_tt *ttm_dma = (struct ttm_dma_tt *)nvbo->bo.ttm; |
484 | int i; | |
485 | ||
486 | if (!ttm_dma) | |
487 | return; | |
488 | ||
489 | /* Don't waste time looping if the object is coherent */ | |
490 | if (nvbo->force_coherent) | |
491 | return; | |
492 | ||
493 | for (i = 0; i < ttm_dma->ttm.num_pages; i++) | |
26c9e8ef BS |
494 | dma_sync_single_for_cpu(device->dev, ttm_dma->dma_address[i], |
495 | PAGE_SIZE, DMA_FROM_DEVICE); | |
b22870ba AC |
496 | } |
497 | ||
7a45d764 BS |
498 | int |
499 | nouveau_bo_validate(struct nouveau_bo *nvbo, bool interruptible, | |
97a875cb | 500 | bool no_wait_gpu) |
7a45d764 BS |
501 | { |
502 | int ret; | |
503 | ||
97a875cb ML |
504 | ret = ttm_bo_validate(&nvbo->bo, &nvbo->placement, |
505 | interruptible, no_wait_gpu); | |
7a45d764 BS |
506 | if (ret) |
507 | return ret; | |
508 | ||
b22870ba AC |
509 | nouveau_bo_sync_for_device(nvbo); |
510 | ||
7a45d764 BS |
511 | return 0; |
512 | } | |
513 | ||
6ee73861 BS |
514 | void |
515 | nouveau_bo_wr16(struct nouveau_bo *nvbo, unsigned index, u16 val) | |
516 | { | |
517 | bool is_iomem; | |
518 | u16 *mem = ttm_kmap_obj_virtual(&nvbo->kmap, &is_iomem); | |
c3a0c771 | 519 | |
36a471ba | 520 | mem += index; |
c3a0c771 | 521 | |
6ee73861 BS |
522 | if (is_iomem) |
523 | iowrite16_native(val, (void __force __iomem *)mem); | |
524 | else | |
525 | *mem = val; | |
526 | } | |
527 | ||
528 | u32 | |
529 | nouveau_bo_rd32(struct nouveau_bo *nvbo, unsigned index) | |
530 | { | |
531 | bool is_iomem; | |
532 | u32 *mem = ttm_kmap_obj_virtual(&nvbo->kmap, &is_iomem); | |
c3a0c771 | 533 | |
36a471ba | 534 | mem += index; |
c3a0c771 | 535 | |
6ee73861 BS |
536 | if (is_iomem) |
537 | return ioread32_native((void __force __iomem *)mem); | |
538 | else | |
539 | return *mem; | |
540 | } | |
541 | ||
542 | void | |
543 | nouveau_bo_wr32(struct nouveau_bo *nvbo, unsigned index, u32 val) | |
544 | { | |
545 | bool is_iomem; | |
546 | u32 *mem = ttm_kmap_obj_virtual(&nvbo->kmap, &is_iomem); | |
c3a0c771 | 547 | |
36a471ba | 548 | mem += index; |
c3a0c771 | 549 | |
6ee73861 BS |
550 | if (is_iomem) |
551 | iowrite32_native(val, (void __force __iomem *)mem); | |
552 | else | |
553 | *mem = val; | |
554 | } | |
555 | ||
649bf3ca | 556 | static struct ttm_tt * |
ebb945a9 BS |
557 | nouveau_ttm_tt_create(struct ttm_bo_device *bdev, unsigned long size, |
558 | uint32_t page_flags, struct page *dummy_read) | |
6ee73861 | 559 | { |
a7fb8a23 | 560 | #if IS_ENABLED(CONFIG_AGP) |
ebb945a9 | 561 | struct nouveau_drm *drm = nouveau_bdev(bdev); |
6ee73861 | 562 | |
340b0e7c BS |
563 | if (drm->agp.bridge) { |
564 | return ttm_agp_tt_create(bdev, drm->agp.bridge, size, | |
ebb945a9 | 565 | page_flags, dummy_read); |
6ee73861 | 566 | } |
df1b4b91 | 567 | #endif |
6ee73861 | 568 | |
ebb945a9 | 569 | return nouveau_sgdma_create_ttm(bdev, size, page_flags, dummy_read); |
6ee73861 BS |
570 | } |
571 | ||
572 | static int | |
573 | nouveau_bo_invalidate_caches(struct ttm_bo_device *bdev, uint32_t flags) | |
574 | { | |
575 | /* We'll do this from user space. */ | |
576 | return 0; | |
577 | } | |
578 | ||
579 | static int | |
580 | nouveau_bo_init_mem_type(struct ttm_bo_device *bdev, uint32_t type, | |
581 | struct ttm_mem_type_manager *man) | |
582 | { | |
ebb945a9 | 583 | struct nouveau_drm *drm = nouveau_bdev(bdev); |
6ee73861 BS |
584 | |
585 | switch (type) { | |
586 | case TTM_PL_SYSTEM: | |
587 | man->flags = TTM_MEMTYPE_FLAG_MAPPABLE; | |
588 | man->available_caching = TTM_PL_MASK_CACHING; | |
589 | man->default_caching = TTM_PL_FLAG_CACHED; | |
590 | break; | |
591 | case TTM_PL_VRAM: | |
e2a4e78c AC |
592 | man->flags = TTM_MEMTYPE_FLAG_FIXED | |
593 | TTM_MEMTYPE_FLAG_MAPPABLE; | |
594 | man->available_caching = TTM_PL_FLAG_UNCACHED | | |
595 | TTM_PL_FLAG_WC; | |
596 | man->default_caching = TTM_PL_FLAG_WC; | |
597 | ||
1167c6bc | 598 | if (drm->client.device.info.family >= NV_DEVICE_INFO_V0_TESLA) { |
e2a4e78c | 599 | /* Some BARs do not support being ioremapped WC */ |
1167c6bc | 600 | if (nvxx_bar(&drm->client.device)->iomap_uncached) { |
e2a4e78c AC |
601 | man->available_caching = TTM_PL_FLAG_UNCACHED; |
602 | man->default_caching = TTM_PL_FLAG_UNCACHED; | |
603 | } | |
604 | ||
573a2a37 | 605 | man->func = &nouveau_vram_manager; |
f869ef88 BS |
606 | man->io_reserve_fastpath = false; |
607 | man->use_io_reserve_lru = true; | |
608 | } else { | |
573a2a37 | 609 | man->func = &ttm_bo_manager_func; |
f869ef88 | 610 | } |
6ee73861 BS |
611 | break; |
612 | case TTM_PL_TT: | |
1167c6bc | 613 | if (drm->client.device.info.family >= NV_DEVICE_INFO_V0_TESLA) |
26c0c9e3 | 614 | man->func = &nouveau_gart_manager; |
3863c9bc | 615 | else |
340b0e7c | 616 | if (!drm->agp.bridge) |
3863c9bc | 617 | man->func = &nv04_gart_manager; |
26c0c9e3 BS |
618 | else |
619 | man->func = &ttm_bo_manager_func; | |
ebb945a9 | 620 | |
340b0e7c | 621 | if (drm->agp.bridge) { |
f32f02fd | 622 | man->flags = TTM_MEMTYPE_FLAG_MAPPABLE; |
a3d487ea FJ |
623 | man->available_caching = TTM_PL_FLAG_UNCACHED | |
624 | TTM_PL_FLAG_WC; | |
625 | man->default_caching = TTM_PL_FLAG_WC; | |
ebb945a9 | 626 | } else { |
6ee73861 BS |
627 | man->flags = TTM_MEMTYPE_FLAG_MAPPABLE | |
628 | TTM_MEMTYPE_FLAG_CMA; | |
629 | man->available_caching = TTM_PL_MASK_CACHING; | |
630 | man->default_caching = TTM_PL_FLAG_CACHED; | |
6ee73861 | 631 | } |
ebb945a9 | 632 | |
6ee73861 BS |
633 | break; |
634 | default: | |
6ee73861 BS |
635 | return -EINVAL; |
636 | } | |
637 | return 0; | |
638 | } | |
639 | ||
640 | static void | |
641 | nouveau_bo_evict_flags(struct ttm_buffer_object *bo, struct ttm_placement *pl) | |
642 | { | |
643 | struct nouveau_bo *nvbo = nouveau_bo(bo); | |
644 | ||
645 | switch (bo->mem.mem_type) { | |
22fbd538 | 646 | case TTM_PL_VRAM: |
78ad0f7b FJ |
647 | nouveau_bo_placement_set(nvbo, TTM_PL_FLAG_TT, |
648 | TTM_PL_FLAG_SYSTEM); | |
22fbd538 | 649 | break; |
6ee73861 | 650 | default: |
78ad0f7b | 651 | nouveau_bo_placement_set(nvbo, TTM_PL_FLAG_SYSTEM, 0); |
6ee73861 BS |
652 | break; |
653 | } | |
22fbd538 FJ |
654 | |
655 | *pl = nvbo->placement; | |
6ee73861 BS |
656 | } |
657 | ||
658 | ||
49981046 BS |
659 | static int |
660 | nve0_bo_move_init(struct nouveau_channel *chan, u32 handle) | |
661 | { | |
662 | int ret = RING_SPACE(chan, 2); | |
663 | if (ret == 0) { | |
664 | BEGIN_NVC0(chan, NvSubCopy, 0x0000, 1); | |
00fc6f6f | 665 | OUT_RING (chan, handle & 0x0000ffff); |
49981046 BS |
666 | FIRE_RING (chan); |
667 | } | |
668 | return ret; | |
669 | } | |
670 | ||
c6b7e895 BS |
671 | static int |
672 | nve0_bo_move_copy(struct nouveau_channel *chan, struct ttm_buffer_object *bo, | |
605f9ccd | 673 | struct ttm_mem_reg *old_reg, struct ttm_mem_reg *new_reg) |
c6b7e895 | 674 | { |
9ce523cc | 675 | struct nouveau_mem *mem = nouveau_mem(old_reg); |
c6b7e895 BS |
676 | int ret = RING_SPACE(chan, 10); |
677 | if (ret == 0) { | |
6d597027 | 678 | BEGIN_NVC0(chan, NvSubCopy, 0x0400, 8); |
9ce523cc BS |
679 | OUT_RING (chan, upper_32_bits(mem->vma[0].addr)); |
680 | OUT_RING (chan, lower_32_bits(mem->vma[0].addr)); | |
681 | OUT_RING (chan, upper_32_bits(mem->vma[1].addr)); | |
682 | OUT_RING (chan, lower_32_bits(mem->vma[1].addr)); | |
c6b7e895 BS |
683 | OUT_RING (chan, PAGE_SIZE); |
684 | OUT_RING (chan, PAGE_SIZE); | |
685 | OUT_RING (chan, PAGE_SIZE); | |
605f9ccd | 686 | OUT_RING (chan, new_reg->num_pages); |
6d597027 | 687 | BEGIN_IMC0(chan, NvSubCopy, 0x0300, 0x0386); |
c6b7e895 BS |
688 | } |
689 | return ret; | |
690 | } | |
691 | ||
d1b167e1 BS |
692 | static int |
693 | nvc0_bo_move_init(struct nouveau_channel *chan, u32 handle) | |
694 | { | |
695 | int ret = RING_SPACE(chan, 2); | |
696 | if (ret == 0) { | |
697 | BEGIN_NVC0(chan, NvSubCopy, 0x0000, 1); | |
698 | OUT_RING (chan, handle); | |
699 | } | |
700 | return ret; | |
701 | } | |
702 | ||
1a46098e BS |
703 | static int |
704 | nvc0_bo_move_copy(struct nouveau_channel *chan, struct ttm_buffer_object *bo, | |
605f9ccd | 705 | struct ttm_mem_reg *old_reg, struct ttm_mem_reg *new_reg) |
1a46098e | 706 | { |
9ce523cc BS |
707 | struct nouveau_mem *mem = nouveau_mem(old_reg); |
708 | u64 src_offset = mem->vma[0].addr; | |
709 | u64 dst_offset = mem->vma[1].addr; | |
605f9ccd | 710 | u32 page_count = new_reg->num_pages; |
1a46098e BS |
711 | int ret; |
712 | ||
605f9ccd | 713 | page_count = new_reg->num_pages; |
1a46098e BS |
714 | while (page_count) { |
715 | int line_count = (page_count > 8191) ? 8191 : page_count; | |
716 | ||
717 | ret = RING_SPACE(chan, 11); | |
718 | if (ret) | |
719 | return ret; | |
720 | ||
721 | BEGIN_NVC0(chan, NvSubCopy, 0x030c, 8); | |
722 | OUT_RING (chan, upper_32_bits(src_offset)); | |
723 | OUT_RING (chan, lower_32_bits(src_offset)); | |
724 | OUT_RING (chan, upper_32_bits(dst_offset)); | |
725 | OUT_RING (chan, lower_32_bits(dst_offset)); | |
726 | OUT_RING (chan, PAGE_SIZE); | |
727 | OUT_RING (chan, PAGE_SIZE); | |
728 | OUT_RING (chan, PAGE_SIZE); | |
729 | OUT_RING (chan, line_count); | |
730 | BEGIN_NVC0(chan, NvSubCopy, 0x0300, 1); | |
731 | OUT_RING (chan, 0x00000110); | |
732 | ||
733 | page_count -= line_count; | |
734 | src_offset += (PAGE_SIZE * line_count); | |
735 | dst_offset += (PAGE_SIZE * line_count); | |
736 | } | |
737 | ||
738 | return 0; | |
739 | } | |
740 | ||
183720b8 BS |
741 | static int |
742 | nvc0_bo_move_m2mf(struct nouveau_channel *chan, struct ttm_buffer_object *bo, | |
605f9ccd | 743 | struct ttm_mem_reg *old_reg, struct ttm_mem_reg *new_reg) |
183720b8 | 744 | { |
9ce523cc BS |
745 | struct nouveau_mem *mem = nouveau_mem(old_reg); |
746 | u64 src_offset = mem->vma[0].addr; | |
747 | u64 dst_offset = mem->vma[1].addr; | |
605f9ccd | 748 | u32 page_count = new_reg->num_pages; |
183720b8 BS |
749 | int ret; |
750 | ||
605f9ccd | 751 | page_count = new_reg->num_pages; |
183720b8 BS |
752 | while (page_count) { |
753 | int line_count = (page_count > 2047) ? 2047 : page_count; | |
754 | ||
755 | ret = RING_SPACE(chan, 12); | |
756 | if (ret) | |
757 | return ret; | |
758 | ||
d1b167e1 | 759 | BEGIN_NVC0(chan, NvSubCopy, 0x0238, 2); |
183720b8 BS |
760 | OUT_RING (chan, upper_32_bits(dst_offset)); |
761 | OUT_RING (chan, lower_32_bits(dst_offset)); | |
d1b167e1 | 762 | BEGIN_NVC0(chan, NvSubCopy, 0x030c, 6); |
183720b8 BS |
763 | OUT_RING (chan, upper_32_bits(src_offset)); |
764 | OUT_RING (chan, lower_32_bits(src_offset)); | |
765 | OUT_RING (chan, PAGE_SIZE); /* src_pitch */ | |
766 | OUT_RING (chan, PAGE_SIZE); /* dst_pitch */ | |
767 | OUT_RING (chan, PAGE_SIZE); /* line_length */ | |
768 | OUT_RING (chan, line_count); | |
d1b167e1 | 769 | BEGIN_NVC0(chan, NvSubCopy, 0x0300, 1); |
183720b8 BS |
770 | OUT_RING (chan, 0x00100110); |
771 | ||
772 | page_count -= line_count; | |
773 | src_offset += (PAGE_SIZE * line_count); | |
774 | dst_offset += (PAGE_SIZE * line_count); | |
775 | } | |
776 | ||
777 | return 0; | |
778 | } | |
779 | ||
fdf53241 BS |
780 | static int |
781 | nva3_bo_move_copy(struct nouveau_channel *chan, struct ttm_buffer_object *bo, | |
605f9ccd | 782 | struct ttm_mem_reg *old_reg, struct ttm_mem_reg *new_reg) |
fdf53241 | 783 | { |
9ce523cc BS |
784 | struct nouveau_mem *mem = nouveau_mem(old_reg); |
785 | u64 src_offset = mem->vma[0].addr; | |
786 | u64 dst_offset = mem->vma[1].addr; | |
605f9ccd | 787 | u32 page_count = new_reg->num_pages; |
fdf53241 BS |
788 | int ret; |
789 | ||
605f9ccd | 790 | page_count = new_reg->num_pages; |
fdf53241 BS |
791 | while (page_count) { |
792 | int line_count = (page_count > 8191) ? 8191 : page_count; | |
793 | ||
794 | ret = RING_SPACE(chan, 11); | |
795 | if (ret) | |
796 | return ret; | |
797 | ||
798 | BEGIN_NV04(chan, NvSubCopy, 0x030c, 8); | |
799 | OUT_RING (chan, upper_32_bits(src_offset)); | |
800 | OUT_RING (chan, lower_32_bits(src_offset)); | |
801 | OUT_RING (chan, upper_32_bits(dst_offset)); | |
802 | OUT_RING (chan, lower_32_bits(dst_offset)); | |
803 | OUT_RING (chan, PAGE_SIZE); | |
804 | OUT_RING (chan, PAGE_SIZE); | |
805 | OUT_RING (chan, PAGE_SIZE); | |
806 | OUT_RING (chan, line_count); | |
807 | BEGIN_NV04(chan, NvSubCopy, 0x0300, 1); | |
808 | OUT_RING (chan, 0x00000110); | |
809 | ||
810 | page_count -= line_count; | |
811 | src_offset += (PAGE_SIZE * line_count); | |
812 | dst_offset += (PAGE_SIZE * line_count); | |
813 | } | |
814 | ||
815 | return 0; | |
816 | } | |
817 | ||
5490e5df BS |
818 | static int |
819 | nv98_bo_move_exec(struct nouveau_channel *chan, struct ttm_buffer_object *bo, | |
605f9ccd | 820 | struct ttm_mem_reg *old_reg, struct ttm_mem_reg *new_reg) |
5490e5df | 821 | { |
9ce523cc | 822 | struct nouveau_mem *mem = nouveau_mem(old_reg); |
5490e5df BS |
823 | int ret = RING_SPACE(chan, 7); |
824 | if (ret == 0) { | |
825 | BEGIN_NV04(chan, NvSubCopy, 0x0320, 6); | |
9ce523cc BS |
826 | OUT_RING (chan, upper_32_bits(mem->vma[0].addr)); |
827 | OUT_RING (chan, lower_32_bits(mem->vma[0].addr)); | |
828 | OUT_RING (chan, upper_32_bits(mem->vma[1].addr)); | |
829 | OUT_RING (chan, lower_32_bits(mem->vma[1].addr)); | |
5490e5df | 830 | OUT_RING (chan, 0x00000000 /* COPY */); |
605f9ccd | 831 | OUT_RING (chan, new_reg->num_pages << PAGE_SHIFT); |
5490e5df BS |
832 | } |
833 | return ret; | |
834 | } | |
835 | ||
4c193d25 BS |
836 | static int |
837 | nv84_bo_move_exec(struct nouveau_channel *chan, struct ttm_buffer_object *bo, | |
605f9ccd | 838 | struct ttm_mem_reg *old_reg, struct ttm_mem_reg *new_reg) |
4c193d25 | 839 | { |
9ce523cc | 840 | struct nouveau_mem *mem = nouveau_mem(old_reg); |
4c193d25 BS |
841 | int ret = RING_SPACE(chan, 7); |
842 | if (ret == 0) { | |
843 | BEGIN_NV04(chan, NvSubCopy, 0x0304, 6); | |
605f9ccd | 844 | OUT_RING (chan, new_reg->num_pages << PAGE_SHIFT); |
9ce523cc BS |
845 | OUT_RING (chan, upper_32_bits(mem->vma[0].addr)); |
846 | OUT_RING (chan, lower_32_bits(mem->vma[0].addr)); | |
847 | OUT_RING (chan, upper_32_bits(mem->vma[1].addr)); | |
848 | OUT_RING (chan, lower_32_bits(mem->vma[1].addr)); | |
4c193d25 BS |
849 | OUT_RING (chan, 0x00000000 /* MODE_COPY, QUERY_NONE */); |
850 | } | |
851 | return ret; | |
852 | } | |
853 | ||
d1b167e1 BS |
854 | static int |
855 | nv50_bo_move_init(struct nouveau_channel *chan, u32 handle) | |
856 | { | |
ebb945a9 | 857 | int ret = RING_SPACE(chan, 6); |
d1b167e1 | 858 | if (ret == 0) { |
ebb945a9 BS |
859 | BEGIN_NV04(chan, NvSubCopy, 0x0000, 1); |
860 | OUT_RING (chan, handle); | |
861 | BEGIN_NV04(chan, NvSubCopy, 0x0180, 3); | |
f45f55c4 BS |
862 | OUT_RING (chan, chan->drm->ntfy.handle); |
863 | OUT_RING (chan, chan->vram.handle); | |
864 | OUT_RING (chan, chan->vram.handle); | |
d1b167e1 BS |
865 | } |
866 | ||
867 | return ret; | |
868 | } | |
869 | ||
6ee73861 | 870 | static int |
f1ab0cc9 | 871 | nv50_bo_move_m2mf(struct nouveau_channel *chan, struct ttm_buffer_object *bo, |
605f9ccd | 872 | struct ttm_mem_reg *old_reg, struct ttm_mem_reg *new_reg) |
6ee73861 | 873 | { |
9ce523cc | 874 | struct nouveau_mem *mem = nouveau_mem(old_reg); |
605f9ccd | 875 | u64 length = (new_reg->num_pages << PAGE_SHIFT); |
9ce523cc BS |
876 | u64 src_offset = mem->vma[0].addr; |
877 | u64 dst_offset = mem->vma[1].addr; | |
878 | int src_tiled = !!mem->kind; | |
879 | int dst_tiled = !!nouveau_mem(new_reg)->kind; | |
6ee73861 BS |
880 | int ret; |
881 | ||
f1ab0cc9 BS |
882 | while (length) { |
883 | u32 amount, stride, height; | |
884 | ||
ce8f7699 ML |
885 | ret = RING_SPACE(chan, 18 + 6 * (src_tiled + dst_tiled)); |
886 | if (ret) | |
887 | return ret; | |
888 | ||
5220b3c1 BS |
889 | amount = min(length, (u64)(4 * 1024 * 1024)); |
890 | stride = 16 * 4; | |
f1ab0cc9 BS |
891 | height = amount / stride; |
892 | ||
ce8f7699 | 893 | if (src_tiled) { |
d1b167e1 | 894 | BEGIN_NV04(chan, NvSubCopy, 0x0200, 7); |
f1ab0cc9 | 895 | OUT_RING (chan, 0); |
5220b3c1 | 896 | OUT_RING (chan, 0); |
f1ab0cc9 BS |
897 | OUT_RING (chan, stride); |
898 | OUT_RING (chan, height); | |
899 | OUT_RING (chan, 1); | |
900 | OUT_RING (chan, 0); | |
901 | OUT_RING (chan, 0); | |
902 | } else { | |
d1b167e1 | 903 | BEGIN_NV04(chan, NvSubCopy, 0x0200, 1); |
f1ab0cc9 BS |
904 | OUT_RING (chan, 1); |
905 | } | |
ce8f7699 | 906 | if (dst_tiled) { |
d1b167e1 | 907 | BEGIN_NV04(chan, NvSubCopy, 0x021c, 7); |
f1ab0cc9 | 908 | OUT_RING (chan, 0); |
5220b3c1 | 909 | OUT_RING (chan, 0); |
f1ab0cc9 BS |
910 | OUT_RING (chan, stride); |
911 | OUT_RING (chan, height); | |
912 | OUT_RING (chan, 1); | |
913 | OUT_RING (chan, 0); | |
914 | OUT_RING (chan, 0); | |
915 | } else { | |
d1b167e1 | 916 | BEGIN_NV04(chan, NvSubCopy, 0x021c, 1); |
f1ab0cc9 BS |
917 | OUT_RING (chan, 1); |
918 | } | |
919 | ||
d1b167e1 | 920 | BEGIN_NV04(chan, NvSubCopy, 0x0238, 2); |
f1ab0cc9 BS |
921 | OUT_RING (chan, upper_32_bits(src_offset)); |
922 | OUT_RING (chan, upper_32_bits(dst_offset)); | |
d1b167e1 | 923 | BEGIN_NV04(chan, NvSubCopy, 0x030c, 8); |
f1ab0cc9 BS |
924 | OUT_RING (chan, lower_32_bits(src_offset)); |
925 | OUT_RING (chan, lower_32_bits(dst_offset)); | |
926 | OUT_RING (chan, stride); | |
927 | OUT_RING (chan, stride); | |
928 | OUT_RING (chan, stride); | |
929 | OUT_RING (chan, height); | |
930 | OUT_RING (chan, 0x00000101); | |
931 | OUT_RING (chan, 0x00000000); | |
d1b167e1 | 932 | BEGIN_NV04(chan, NvSubCopy, NV_MEMORY_TO_MEMORY_FORMAT_NOP, 1); |
f1ab0cc9 BS |
933 | OUT_RING (chan, 0); |
934 | ||
935 | length -= amount; | |
936 | src_offset += amount; | |
937 | dst_offset += amount; | |
6ee73861 BS |
938 | } |
939 | ||
f1ab0cc9 BS |
940 | return 0; |
941 | } | |
942 | ||
d1b167e1 BS |
943 | static int |
944 | nv04_bo_move_init(struct nouveau_channel *chan, u32 handle) | |
945 | { | |
ebb945a9 | 946 | int ret = RING_SPACE(chan, 4); |
d1b167e1 | 947 | if (ret == 0) { |
ebb945a9 BS |
948 | BEGIN_NV04(chan, NvSubCopy, 0x0000, 1); |
949 | OUT_RING (chan, handle); | |
950 | BEGIN_NV04(chan, NvSubCopy, 0x0180, 1); | |
f45f55c4 | 951 | OUT_RING (chan, chan->drm->ntfy.handle); |
d1b167e1 BS |
952 | } |
953 | ||
954 | return ret; | |
955 | } | |
956 | ||
a6704788 BS |
957 | static inline uint32_t |
958 | nouveau_bo_mem_ctxdma(struct ttm_buffer_object *bo, | |
605f9ccd | 959 | struct nouveau_channel *chan, struct ttm_mem_reg *reg) |
a6704788 | 960 | { |
605f9ccd | 961 | if (reg->mem_type == TTM_PL_TT) |
ebb945a9 | 962 | return NvDmaTT; |
f45f55c4 | 963 | return chan->vram.handle; |
a6704788 BS |
964 | } |
965 | ||
f1ab0cc9 BS |
966 | static int |
967 | nv04_bo_move_m2mf(struct nouveau_channel *chan, struct ttm_buffer_object *bo, | |
605f9ccd | 968 | struct ttm_mem_reg *old_reg, struct ttm_mem_reg *new_reg) |
f1ab0cc9 | 969 | { |
605f9ccd BS |
970 | u32 src_offset = old_reg->start << PAGE_SHIFT; |
971 | u32 dst_offset = new_reg->start << PAGE_SHIFT; | |
972 | u32 page_count = new_reg->num_pages; | |
f1ab0cc9 BS |
973 | int ret; |
974 | ||
975 | ret = RING_SPACE(chan, 3); | |
976 | if (ret) | |
977 | return ret; | |
978 | ||
d1b167e1 | 979 | BEGIN_NV04(chan, NvSubCopy, NV_MEMORY_TO_MEMORY_FORMAT_DMA_SOURCE, 2); |
605f9ccd BS |
980 | OUT_RING (chan, nouveau_bo_mem_ctxdma(bo, chan, old_reg)); |
981 | OUT_RING (chan, nouveau_bo_mem_ctxdma(bo, chan, new_reg)); | |
f1ab0cc9 | 982 | |
605f9ccd | 983 | page_count = new_reg->num_pages; |
6ee73861 BS |
984 | while (page_count) { |
985 | int line_count = (page_count > 2047) ? 2047 : page_count; | |
986 | ||
6ee73861 BS |
987 | ret = RING_SPACE(chan, 11); |
988 | if (ret) | |
989 | return ret; | |
f1ab0cc9 | 990 | |
d1b167e1 | 991 | BEGIN_NV04(chan, NvSubCopy, |
6ee73861 | 992 | NV_MEMORY_TO_MEMORY_FORMAT_OFFSET_IN, 8); |
f1ab0cc9 BS |
993 | OUT_RING (chan, src_offset); |
994 | OUT_RING (chan, dst_offset); | |
995 | OUT_RING (chan, PAGE_SIZE); /* src_pitch */ | |
996 | OUT_RING (chan, PAGE_SIZE); /* dst_pitch */ | |
997 | OUT_RING (chan, PAGE_SIZE); /* line_length */ | |
998 | OUT_RING (chan, line_count); | |
999 | OUT_RING (chan, 0x00000101); | |
1000 | OUT_RING (chan, 0x00000000); | |
d1b167e1 | 1001 | BEGIN_NV04(chan, NvSubCopy, NV_MEMORY_TO_MEMORY_FORMAT_NOP, 1); |
f1ab0cc9 | 1002 | OUT_RING (chan, 0); |
6ee73861 BS |
1003 | |
1004 | page_count -= line_count; | |
1005 | src_offset += (PAGE_SIZE * line_count); | |
1006 | dst_offset += (PAGE_SIZE * line_count); | |
1007 | } | |
1008 | ||
f1ab0cc9 BS |
1009 | return 0; |
1010 | } | |
1011 | ||
d2f96666 | 1012 | static int |
3c57d85d | 1013 | nouveau_bo_move_prep(struct nouveau_drm *drm, struct ttm_buffer_object *bo, |
605f9ccd | 1014 | struct ttm_mem_reg *reg) |
d2f96666 | 1015 | { |
9ce523cc BS |
1016 | struct nouveau_mem *old_mem = nouveau_mem(&bo->mem); |
1017 | struct nouveau_mem *new_mem = nouveau_mem(reg); | |
1018 | struct nvkm_vm *vmm = drm->client.vm; | |
605f9ccd | 1019 | u64 size = (u64)reg->num_pages << PAGE_SHIFT; |
d2f96666 BS |
1020 | int ret; |
1021 | ||
9ce523cc BS |
1022 | ret = nvkm_vm_get(vmm, size, old_mem->mem.page, NV_MEM_ACCESS_RW, |
1023 | &old_mem->vma[0]); | |
d2f96666 BS |
1024 | if (ret) |
1025 | return ret; | |
1026 | ||
9ce523cc BS |
1027 | ret = nvkm_vm_get(vmm, size, new_mem->mem.page, NV_MEM_ACCESS_RW, |
1028 | &old_mem->vma[1]); | |
3c57d85d | 1029 | if (ret) { |
605f9ccd | 1030 | nvkm_vm_put(&old_mem->vma[0]); |
3c57d85d BS |
1031 | return ret; |
1032 | } | |
1033 | ||
9ce523cc BS |
1034 | ret = nouveau_mem_map(old_mem, vmm, &old_mem->vma[0]); |
1035 | if (ret) | |
1036 | goto done; | |
1037 | ||
1038 | ret = nouveau_mem_map(new_mem, vmm, &old_mem->vma[1]); | |
1039 | done: | |
1040 | if (ret) { | |
1041 | nvkm_vm_put(&old_mem->vma[1]); | |
1042 | nvkm_vm_put(&old_mem->vma[0]); | |
1043 | } | |
d2f96666 BS |
1044 | return 0; |
1045 | } | |
1046 | ||
f1ab0cc9 BS |
1047 | static int |
1048 | nouveau_bo_move_m2mf(struct ttm_buffer_object *bo, int evict, bool intr, | |
605f9ccd | 1049 | bool no_wait_gpu, struct ttm_mem_reg *new_reg) |
f1ab0cc9 | 1050 | { |
ebb945a9 | 1051 | struct nouveau_drm *drm = nouveau_bdev(bo->bdev); |
1934a2ad | 1052 | struct nouveau_channel *chan = drm->ttm.chan; |
a01ca78c | 1053 | struct nouveau_cli *cli = (void *)chan->user.client; |
35b8141b | 1054 | struct nouveau_fence *fence; |
f1ab0cc9 BS |
1055 | int ret; |
1056 | ||
d2f96666 | 1057 | /* create temporary vmas for the transfer and attach them to the |
be83cd4e | 1058 | * old nvkm_mem node, these will get cleaned up after ttm has |
d2f96666 | 1059 | * destroyed the ttm_mem_reg |
3425df48 | 1060 | */ |
1167c6bc | 1061 | if (drm->client.device.info.family >= NV_DEVICE_INFO_V0_TESLA) { |
605f9ccd | 1062 | ret = nouveau_bo_move_prep(drm, bo, new_reg); |
d2f96666 | 1063 | if (ret) |
3c57d85d | 1064 | return ret; |
3425df48 BS |
1065 | } |
1066 | ||
0ad72863 | 1067 | mutex_lock_nested(&cli->mutex, SINGLE_DEPTH_NESTING); |
e3be4c23 | 1068 | ret = nouveau_fence_sync(nouveau_bo(bo), chan, true, intr); |
6a6b73f2 | 1069 | if (ret == 0) { |
605f9ccd | 1070 | ret = drm->ttm.move(chan, bo, &bo->mem, new_reg); |
35b8141b BS |
1071 | if (ret == 0) { |
1072 | ret = nouveau_fence_new(chan, false, &fence); | |
1073 | if (ret == 0) { | |
f2c24b83 ML |
1074 | ret = ttm_bo_move_accel_cleanup(bo, |
1075 | &fence->base, | |
35b8141b | 1076 | evict, |
605f9ccd | 1077 | new_reg); |
35b8141b BS |
1078 | nouveau_fence_unref(&fence); |
1079 | } | |
1080 | } | |
6a6b73f2 | 1081 | } |
0ad72863 | 1082 | mutex_unlock(&cli->mutex); |
6a6b73f2 | 1083 | return ret; |
6ee73861 BS |
1084 | } |
1085 | ||
d1b167e1 | 1086 | void |
49981046 | 1087 | nouveau_bo_move_init(struct nouveau_drm *drm) |
d1b167e1 | 1088 | { |
d1b167e1 BS |
1089 | static const struct { |
1090 | const char *name; | |
1a46098e | 1091 | int engine; |
315a8b2e | 1092 | s32 oclass; |
d1b167e1 BS |
1093 | int (*exec)(struct nouveau_channel *, |
1094 | struct ttm_buffer_object *, | |
1095 | struct ttm_mem_reg *, struct ttm_mem_reg *); | |
1096 | int (*init)(struct nouveau_channel *, u32 handle); | |
1097 | } _methods[] = { | |
146cfe24 BS |
1098 | { "COPY", 4, 0xc1b5, nve0_bo_move_copy, nve0_bo_move_init }, |
1099 | { "GRCE", 0, 0xc1b5, nve0_bo_move_copy, nvc0_bo_move_init }, | |
8e7e1586 BS |
1100 | { "COPY", 4, 0xc0b5, nve0_bo_move_copy, nve0_bo_move_init }, |
1101 | { "GRCE", 0, 0xc0b5, nve0_bo_move_copy, nvc0_bo_move_init }, | |
990b4547 BS |
1102 | { "COPY", 4, 0xb0b5, nve0_bo_move_copy, nve0_bo_move_init }, |
1103 | { "GRCE", 0, 0xb0b5, nve0_bo_move_copy, nvc0_bo_move_init }, | |
00fc6f6f | 1104 | { "COPY", 4, 0xa0b5, nve0_bo_move_copy, nve0_bo_move_init }, |
49981046 | 1105 | { "GRCE", 0, 0xa0b5, nve0_bo_move_copy, nvc0_bo_move_init }, |
1a46098e BS |
1106 | { "COPY1", 5, 0x90b8, nvc0_bo_move_copy, nvc0_bo_move_init }, |
1107 | { "COPY0", 4, 0x90b5, nvc0_bo_move_copy, nvc0_bo_move_init }, | |
1108 | { "COPY", 0, 0x85b5, nva3_bo_move_copy, nv50_bo_move_init }, | |
1109 | { "CRYPT", 0, 0x74c1, nv84_bo_move_exec, nv50_bo_move_init }, | |
1110 | { "M2MF", 0, 0x9039, nvc0_bo_move_m2mf, nvc0_bo_move_init }, | |
1111 | { "M2MF", 0, 0x5039, nv50_bo_move_m2mf, nv50_bo_move_init }, | |
1112 | { "M2MF", 0, 0x0039, nv04_bo_move_m2mf, nv04_bo_move_init }, | |
5490e5df | 1113 | {}, |
1a46098e | 1114 | { "CRYPT", 0, 0x88b4, nv98_bo_move_exec, nv50_bo_move_init }, |
d1b167e1 BS |
1115 | }, *mthd = _methods; |
1116 | const char *name = "CPU"; | |
1117 | int ret; | |
1118 | ||
1119 | do { | |
49981046 | 1120 | struct nouveau_channel *chan; |
ebb945a9 | 1121 | |
00fc6f6f | 1122 | if (mthd->engine) |
49981046 BS |
1123 | chan = drm->cechan; |
1124 | else | |
1125 | chan = drm->channel; | |
1126 | if (chan == NULL) | |
1127 | continue; | |
1128 | ||
a01ca78c | 1129 | ret = nvif_object_init(&chan->user, |
0ad72863 BS |
1130 | mthd->oclass | (mthd->engine << 16), |
1131 | mthd->oclass, NULL, 0, | |
1132 | &drm->ttm.copy); | |
d1b167e1 | 1133 | if (ret == 0) { |
0ad72863 | 1134 | ret = mthd->init(chan, drm->ttm.copy.handle); |
ebb945a9 | 1135 | if (ret) { |
0ad72863 | 1136 | nvif_object_fini(&drm->ttm.copy); |
ebb945a9 | 1137 | continue; |
d1b167e1 | 1138 | } |
ebb945a9 BS |
1139 | |
1140 | drm->ttm.move = mthd->exec; | |
1bb3f6a2 | 1141 | drm->ttm.chan = chan; |
ebb945a9 BS |
1142 | name = mthd->name; |
1143 | break; | |
d1b167e1 BS |
1144 | } |
1145 | } while ((++mthd)->exec); | |
1146 | ||
ebb945a9 | 1147 | NV_INFO(drm, "MM: using %s for buffer copies\n", name); |
d1b167e1 BS |
1148 | } |
1149 | ||
6ee73861 BS |
1150 | static int |
1151 | nouveau_bo_move_flipd(struct ttm_buffer_object *bo, bool evict, bool intr, | |
605f9ccd | 1152 | bool no_wait_gpu, struct ttm_mem_reg *new_reg) |
6ee73861 | 1153 | { |
f1217ed0 CK |
1154 | struct ttm_place placement_memtype = { |
1155 | .fpfn = 0, | |
1156 | .lpfn = 0, | |
1157 | .flags = TTM_PL_FLAG_TT | TTM_PL_MASK_CACHING | |
1158 | }; | |
6ee73861 | 1159 | struct ttm_placement placement; |
605f9ccd | 1160 | struct ttm_mem_reg tmp_reg; |
6ee73861 BS |
1161 | int ret; |
1162 | ||
6ee73861 | 1163 | placement.num_placement = placement.num_busy_placement = 1; |
77e2b5ed | 1164 | placement.placement = placement.busy_placement = &placement_memtype; |
6ee73861 | 1165 | |
605f9ccd BS |
1166 | tmp_reg = *new_reg; |
1167 | tmp_reg.mm_node = NULL; | |
1168 | ret = ttm_bo_mem_space(bo, &placement, &tmp_reg, intr, no_wait_gpu); | |
6ee73861 BS |
1169 | if (ret) |
1170 | return ret; | |
1171 | ||
605f9ccd | 1172 | ret = ttm_tt_bind(bo->ttm, &tmp_reg); |
6ee73861 BS |
1173 | if (ret) |
1174 | goto out; | |
1175 | ||
605f9ccd | 1176 | ret = nouveau_bo_move_m2mf(bo, true, intr, no_wait_gpu, &tmp_reg); |
6ee73861 BS |
1177 | if (ret) |
1178 | goto out; | |
1179 | ||
605f9ccd | 1180 | ret = ttm_bo_move_ttm(bo, intr, no_wait_gpu, new_reg); |
6ee73861 | 1181 | out: |
605f9ccd | 1182 | ttm_bo_mem_put(bo, &tmp_reg); |
6ee73861 BS |
1183 | return ret; |
1184 | } | |
1185 | ||
1186 | static int | |
1187 | nouveau_bo_move_flips(struct ttm_buffer_object *bo, bool evict, bool intr, | |
605f9ccd | 1188 | bool no_wait_gpu, struct ttm_mem_reg *new_reg) |
6ee73861 | 1189 | { |
f1217ed0 CK |
1190 | struct ttm_place placement_memtype = { |
1191 | .fpfn = 0, | |
1192 | .lpfn = 0, | |
1193 | .flags = TTM_PL_FLAG_TT | TTM_PL_MASK_CACHING | |
1194 | }; | |
6ee73861 | 1195 | struct ttm_placement placement; |
605f9ccd | 1196 | struct ttm_mem_reg tmp_reg; |
6ee73861 BS |
1197 | int ret; |
1198 | ||
6ee73861 | 1199 | placement.num_placement = placement.num_busy_placement = 1; |
77e2b5ed | 1200 | placement.placement = placement.busy_placement = &placement_memtype; |
6ee73861 | 1201 | |
605f9ccd BS |
1202 | tmp_reg = *new_reg; |
1203 | tmp_reg.mm_node = NULL; | |
1204 | ret = ttm_bo_mem_space(bo, &placement, &tmp_reg, intr, no_wait_gpu); | |
6ee73861 BS |
1205 | if (ret) |
1206 | return ret; | |
1207 | ||
605f9ccd | 1208 | ret = ttm_bo_move_ttm(bo, intr, no_wait_gpu, &tmp_reg); |
6ee73861 BS |
1209 | if (ret) |
1210 | goto out; | |
1211 | ||
605f9ccd | 1212 | ret = nouveau_bo_move_m2mf(bo, true, intr, no_wait_gpu, new_reg); |
6ee73861 BS |
1213 | if (ret) |
1214 | goto out; | |
1215 | ||
1216 | out: | |
605f9ccd | 1217 | ttm_bo_mem_put(bo, &tmp_reg); |
6ee73861 BS |
1218 | return ret; |
1219 | } | |
1220 | ||
a4154bbf | 1221 | static void |
66257db7 | 1222 | nouveau_bo_move_ntfy(struct ttm_buffer_object *bo, bool evict, |
605f9ccd | 1223 | struct ttm_mem_reg *new_reg) |
a4154bbf | 1224 | { |
9ce523cc | 1225 | struct nouveau_mem *mem = new_reg ? nouveau_mem(new_reg) : NULL; |
a4154bbf | 1226 | struct nouveau_bo *nvbo = nouveau_bo(bo); |
24e8375b | 1227 | struct nouveau_vma *vma; |
fd2871af | 1228 | |
9f1feed2 BS |
1229 | /* ttm can now (stupidly) pass the driver bos it didn't create... */ |
1230 | if (bo->destroy != nouveau_bo_del_ttm) | |
1231 | return; | |
1232 | ||
a48296ab | 1233 | if (mem && new_reg->mem_type != TTM_PL_SYSTEM && |
9ce523cc | 1234 | mem->mem.page == nvbo->page) { |
a48296ab | 1235 | list_for_each_entry(vma, &nvbo->vma_list, head) { |
24e8375b | 1236 | nouveau_vma_map(vma, mem); |
a48296ab BS |
1237 | } |
1238 | } else { | |
1239 | list_for_each_entry(vma, &nvbo->vma_list, head) { | |
10dcab3e | 1240 | WARN_ON(ttm_bo_wait(bo, false, false)); |
24e8375b | 1241 | nouveau_vma_unmap(vma); |
fd2871af | 1242 | } |
a4154bbf BS |
1243 | } |
1244 | } | |
1245 | ||
6ee73861 | 1246 | static int |
605f9ccd | 1247 | nouveau_bo_vm_bind(struct ttm_buffer_object *bo, struct ttm_mem_reg *new_reg, |
ebb945a9 | 1248 | struct nouveau_drm_tile **new_tile) |
6ee73861 | 1249 | { |
ebb945a9 BS |
1250 | struct nouveau_drm *drm = nouveau_bdev(bo->bdev); |
1251 | struct drm_device *dev = drm->dev; | |
a0af9add | 1252 | struct nouveau_bo *nvbo = nouveau_bo(bo); |
605f9ccd | 1253 | u64 offset = new_reg->start << PAGE_SHIFT; |
6ee73861 | 1254 | |
a4154bbf | 1255 | *new_tile = NULL; |
605f9ccd | 1256 | if (new_reg->mem_type != TTM_PL_VRAM) |
a0af9add | 1257 | return 0; |
a0af9add | 1258 | |
1167c6bc | 1259 | if (drm->client.device.info.family >= NV_DEVICE_INFO_V0_CELSIUS) { |
605f9ccd | 1260 | *new_tile = nv10_bo_set_tiling(dev, offset, new_reg->size, |
7760a2e3 | 1261 | nvbo->mode, nvbo->zeta); |
6ee73861 BS |
1262 | } |
1263 | ||
a0af9add FJ |
1264 | return 0; |
1265 | } | |
1266 | ||
1267 | static void | |
1268 | nouveau_bo_vm_cleanup(struct ttm_buffer_object *bo, | |
ebb945a9 BS |
1269 | struct nouveau_drm_tile *new_tile, |
1270 | struct nouveau_drm_tile **old_tile) | |
a0af9add | 1271 | { |
ebb945a9 BS |
1272 | struct nouveau_drm *drm = nouveau_bdev(bo->bdev); |
1273 | struct drm_device *dev = drm->dev; | |
f54d1867 | 1274 | struct dma_fence *fence = reservation_object_get_excl(bo->resv); |
a0af9add | 1275 | |
f2c24b83 | 1276 | nv10_bo_put_tile_region(dev, *old_tile, fence); |
a4154bbf | 1277 | *old_tile = new_tile; |
a0af9add FJ |
1278 | } |
1279 | ||
1280 | static int | |
1281 | nouveau_bo_move(struct ttm_buffer_object *bo, bool evict, bool intr, | |
605f9ccd | 1282 | bool no_wait_gpu, struct ttm_mem_reg *new_reg) |
a0af9add | 1283 | { |
ebb945a9 | 1284 | struct nouveau_drm *drm = nouveau_bdev(bo->bdev); |
a0af9add | 1285 | struct nouveau_bo *nvbo = nouveau_bo(bo); |
605f9ccd | 1286 | struct ttm_mem_reg *old_reg = &bo->mem; |
ebb945a9 | 1287 | struct nouveau_drm_tile *new_tile = NULL; |
a0af9add FJ |
1288 | int ret = 0; |
1289 | ||
88932a7b CK |
1290 | ret = ttm_bo_wait(bo, intr, no_wait_gpu); |
1291 | if (ret) | |
1292 | return ret; | |
1293 | ||
5be5a15a AC |
1294 | if (nvbo->pin_refcnt) |
1295 | NV_WARN(drm, "Moving pinned object %p!\n", nvbo); | |
1296 | ||
1167c6bc | 1297 | if (drm->client.device.info.family < NV_DEVICE_INFO_V0_TESLA) { |
605f9ccd | 1298 | ret = nouveau_bo_vm_bind(bo, new_reg, &new_tile); |
a4154bbf BS |
1299 | if (ret) |
1300 | return ret; | |
1301 | } | |
a0af9add | 1302 | |
a0af9add | 1303 | /* Fake bo copy. */ |
605f9ccd | 1304 | if (old_reg->mem_type == TTM_PL_SYSTEM && !bo->ttm) { |
6ee73861 | 1305 | BUG_ON(bo->mem.mm_node != NULL); |
605f9ccd BS |
1306 | bo->mem = *new_reg; |
1307 | new_reg->mm_node = NULL; | |
a0af9add | 1308 | goto out; |
6ee73861 BS |
1309 | } |
1310 | ||
a0af9add | 1311 | /* Hardware assisted copy. */ |
cef9e99e | 1312 | if (drm->ttm.move) { |
605f9ccd | 1313 | if (new_reg->mem_type == TTM_PL_SYSTEM) |
cef9e99e | 1314 | ret = nouveau_bo_move_flipd(bo, evict, intr, |
605f9ccd BS |
1315 | no_wait_gpu, new_reg); |
1316 | else if (old_reg->mem_type == TTM_PL_SYSTEM) | |
cef9e99e | 1317 | ret = nouveau_bo_move_flips(bo, evict, intr, |
605f9ccd | 1318 | no_wait_gpu, new_reg); |
cef9e99e BS |
1319 | else |
1320 | ret = nouveau_bo_move_m2mf(bo, evict, intr, | |
605f9ccd | 1321 | no_wait_gpu, new_reg); |
cef9e99e BS |
1322 | if (!ret) |
1323 | goto out; | |
1324 | } | |
a0af9add FJ |
1325 | |
1326 | /* Fallback to software copy. */ | |
8aa6d4fc | 1327 | ret = ttm_bo_wait(bo, intr, no_wait_gpu); |
cef9e99e | 1328 | if (ret == 0) |
605f9ccd | 1329 | ret = ttm_bo_move_memcpy(bo, intr, no_wait_gpu, new_reg); |
a0af9add FJ |
1330 | |
1331 | out: | |
1167c6bc | 1332 | if (drm->client.device.info.family < NV_DEVICE_INFO_V0_TESLA) { |
a4154bbf BS |
1333 | if (ret) |
1334 | nouveau_bo_vm_cleanup(bo, NULL, &new_tile); | |
1335 | else | |
1336 | nouveau_bo_vm_cleanup(bo, new_tile, &nvbo->tile); | |
1337 | } | |
a0af9add FJ |
1338 | |
1339 | return ret; | |
6ee73861 BS |
1340 | } |
1341 | ||
1342 | static int | |
1343 | nouveau_bo_verify_access(struct ttm_buffer_object *bo, struct file *filp) | |
1344 | { | |
acb46527 DH |
1345 | struct nouveau_bo *nvbo = nouveau_bo(bo); |
1346 | ||
d9a1f0b4 DH |
1347 | return drm_vma_node_verify_access(&nvbo->gem.vma_node, |
1348 | filp->private_data); | |
6ee73861 BS |
1349 | } |
1350 | ||
f32f02fd | 1351 | static int |
605f9ccd | 1352 | nouveau_ttm_io_mem_reserve(struct ttm_bo_device *bdev, struct ttm_mem_reg *reg) |
f32f02fd | 1353 | { |
605f9ccd | 1354 | struct ttm_mem_type_manager *man = &bdev->man[reg->mem_type]; |
ebb945a9 | 1355 | struct nouveau_drm *drm = nouveau_bdev(bdev); |
1167c6bc | 1356 | struct nvkm_device *device = nvxx_device(&drm->client.device); |
9ce523cc | 1357 | struct nouveau_mem *mem = nouveau_mem(reg); |
f869ef88 | 1358 | int ret; |
f32f02fd | 1359 | |
605f9ccd BS |
1360 | reg->bus.addr = NULL; |
1361 | reg->bus.offset = 0; | |
1362 | reg->bus.size = reg->num_pages << PAGE_SHIFT; | |
1363 | reg->bus.base = 0; | |
1364 | reg->bus.is_iomem = false; | |
f32f02fd JG |
1365 | if (!(man->flags & TTM_MEMTYPE_FLAG_MAPPABLE)) |
1366 | return -EINVAL; | |
605f9ccd | 1367 | switch (reg->mem_type) { |
f32f02fd JG |
1368 | case TTM_PL_SYSTEM: |
1369 | /* System memory */ | |
1370 | return 0; | |
1371 | case TTM_PL_TT: | |
a7fb8a23 | 1372 | #if IS_ENABLED(CONFIG_AGP) |
340b0e7c | 1373 | if (drm->agp.bridge) { |
605f9ccd BS |
1374 | reg->bus.offset = reg->start << PAGE_SHIFT; |
1375 | reg->bus.base = drm->agp.base; | |
1376 | reg->bus.is_iomem = !drm->agp.cma; | |
f32f02fd JG |
1377 | } |
1378 | #endif | |
9ce523cc | 1379 | if (drm->client.device.info.family < NV_DEVICE_INFO_V0_TESLA || !mem->kind) |
a5540906 ML |
1380 | /* untiled */ |
1381 | break; | |
1382 | /* fallthrough, tiled memory */ | |
f32f02fd | 1383 | case TTM_PL_VRAM: |
605f9ccd BS |
1384 | reg->bus.offset = reg->start << PAGE_SHIFT; |
1385 | reg->bus.base = device->func->resource_addr(device, 1); | |
1386 | reg->bus.is_iomem = true; | |
1167c6bc | 1387 | if (drm->client.device.info.family >= NV_DEVICE_INFO_V0_TESLA) { |
570889dc | 1388 | struct nvkm_vmm *bar = nvkm_bar_bar1_vmm(device); |
d8e83994 | 1389 | int page_shift = 12; |
1167c6bc | 1390 | if (drm->client.device.info.family >= NV_DEVICE_INFO_V0_FERMI) |
9ce523cc | 1391 | page_shift = mem->mem.page; |
8984e046 | 1392 | |
9ce523cc BS |
1393 | ret = nvkm_vm_get(bar, mem->_mem->size << 12, |
1394 | page_shift, NV_MEM_ACCESS_RW, | |
1395 | &mem->bar_vma); | |
3863c9bc BS |
1396 | if (ret) |
1397 | return ret; | |
f869ef88 | 1398 | |
9ce523cc | 1399 | nvkm_vm_map(&mem->bar_vma, mem->_mem); |
605f9ccd | 1400 | reg->bus.offset = mem->bar_vma.offset; |
f869ef88 | 1401 | } |
f32f02fd JG |
1402 | break; |
1403 | default: | |
1404 | return -EINVAL; | |
1405 | } | |
1406 | return 0; | |
1407 | } | |
1408 | ||
1409 | static void | |
605f9ccd | 1410 | nouveau_ttm_io_mem_free(struct ttm_bo_device *bdev, struct ttm_mem_reg *reg) |
f32f02fd | 1411 | { |
9ce523cc | 1412 | struct nouveau_mem *mem = nouveau_mem(reg); |
f869ef88 | 1413 | |
605f9ccd | 1414 | if (!mem->bar_vma.node) |
f869ef88 BS |
1415 | return; |
1416 | ||
605f9ccd BS |
1417 | nvkm_vm_unmap(&mem->bar_vma); |
1418 | nvkm_vm_put(&mem->bar_vma); | |
f32f02fd JG |
1419 | } |
1420 | ||
1421 | static int | |
1422 | nouveau_ttm_fault_reserve_notify(struct ttm_buffer_object *bo) | |
1423 | { | |
ebb945a9 | 1424 | struct nouveau_drm *drm = nouveau_bdev(bo->bdev); |
e1429b4c | 1425 | struct nouveau_bo *nvbo = nouveau_bo(bo); |
1167c6bc | 1426 | struct nvkm_device *device = nvxx_device(&drm->client.device); |
7e8820fe | 1427 | u32 mappable = device->func->resource_size(device, 1) >> PAGE_SHIFT; |
f1217ed0 | 1428 | int i, ret; |
e1429b4c BS |
1429 | |
1430 | /* as long as the bo isn't in vram, and isn't tiled, we've got | |
1431 | * nothing to do here. | |
1432 | */ | |
1433 | if (bo->mem.mem_type != TTM_PL_VRAM) { | |
1167c6bc | 1434 | if (drm->client.device.info.family < NV_DEVICE_INFO_V0_TESLA || |
7760a2e3 | 1435 | !nvbo->kind) |
e1429b4c | 1436 | return 0; |
a5540906 ML |
1437 | |
1438 | if (bo->mem.mem_type == TTM_PL_SYSTEM) { | |
1439 | nouveau_bo_placement_set(nvbo, TTM_PL_TT, 0); | |
1440 | ||
1441 | ret = nouveau_bo_validate(nvbo, false, false); | |
1442 | if (ret) | |
1443 | return ret; | |
1444 | } | |
1445 | return 0; | |
e1429b4c BS |
1446 | } |
1447 | ||
1448 | /* make sure bo is in mappable vram */ | |
1167c6bc | 1449 | if (drm->client.device.info.family >= NV_DEVICE_INFO_V0_TESLA || |
a5540906 | 1450 | bo->mem.start + bo->mem.num_pages < mappable) |
e1429b4c BS |
1451 | return 0; |
1452 | ||
f1217ed0 CK |
1453 | for (i = 0; i < nvbo->placement.num_placement; ++i) { |
1454 | nvbo->placements[i].fpfn = 0; | |
1455 | nvbo->placements[i].lpfn = mappable; | |
1456 | } | |
1457 | ||
1458 | for (i = 0; i < nvbo->placement.num_busy_placement; ++i) { | |
1459 | nvbo->busy_placements[i].fpfn = 0; | |
1460 | nvbo->busy_placements[i].lpfn = mappable; | |
1461 | } | |
e1429b4c | 1462 | |
c284815d | 1463 | nouveau_bo_placement_set(nvbo, TTM_PL_FLAG_VRAM, 0); |
97a875cb | 1464 | return nouveau_bo_validate(nvbo, false, false); |
f32f02fd JG |
1465 | } |
1466 | ||
3230cfc3 KRW |
1467 | static int |
1468 | nouveau_ttm_tt_populate(struct ttm_tt *ttm) | |
1469 | { | |
8e7e7052 | 1470 | struct ttm_dma_tt *ttm_dma = (void *)ttm; |
ebb945a9 | 1471 | struct nouveau_drm *drm; |
be83cd4e | 1472 | struct nvkm_device *device; |
3230cfc3 | 1473 | struct drm_device *dev; |
fd1496a0 | 1474 | struct device *pdev; |
3230cfc3 KRW |
1475 | unsigned i; |
1476 | int r; | |
22b33e8e | 1477 | bool slave = !!(ttm->page_flags & TTM_PAGE_FLAG_SG); |
3230cfc3 KRW |
1478 | |
1479 | if (ttm->state != tt_unpopulated) | |
1480 | return 0; | |
1481 | ||
22b33e8e DA |
1482 | if (slave && ttm->sg) { |
1483 | /* make userspace faulting work */ | |
1484 | drm_prime_sg_to_page_addr_arrays(ttm->sg, ttm->pages, | |
1485 | ttm_dma->dma_address, ttm->num_pages); | |
1486 | ttm->state = tt_unbound; | |
1487 | return 0; | |
1488 | } | |
1489 | ||
ebb945a9 | 1490 | drm = nouveau_bdev(ttm->bdev); |
1167c6bc | 1491 | device = nvxx_device(&drm->client.device); |
ebb945a9 | 1492 | dev = drm->dev; |
26c9e8ef | 1493 | pdev = device->dev; |
3230cfc3 | 1494 | |
a7fb8a23 | 1495 | #if IS_ENABLED(CONFIG_AGP) |
340b0e7c | 1496 | if (drm->agp.bridge) { |
dea7e0ac JG |
1497 | return ttm_agp_tt_populate(ttm); |
1498 | } | |
1499 | #endif | |
1500 | ||
9bcd38de | 1501 | #if IS_ENABLED(CONFIG_SWIOTLB) && IS_ENABLED(CONFIG_X86) |
3230cfc3 | 1502 | if (swiotlb_nr_tbl()) { |
8e7e7052 | 1503 | return ttm_dma_populate((void *)ttm, dev->dev); |
3230cfc3 KRW |
1504 | } |
1505 | #endif | |
1506 | ||
1507 | r = ttm_pool_populate(ttm); | |
1508 | if (r) { | |
1509 | return r; | |
1510 | } | |
1511 | ||
1512 | for (i = 0; i < ttm->num_pages; i++) { | |
fd1496a0 AC |
1513 | dma_addr_t addr; |
1514 | ||
1515 | addr = dma_map_page(pdev, ttm->pages[i], 0, PAGE_SIZE, | |
1516 | DMA_BIDIRECTIONAL); | |
1517 | ||
1518 | if (dma_mapping_error(pdev, addr)) { | |
4fbbed46 | 1519 | while (i--) { |
fd1496a0 AC |
1520 | dma_unmap_page(pdev, ttm_dma->dma_address[i], |
1521 | PAGE_SIZE, DMA_BIDIRECTIONAL); | |
8e7e7052 | 1522 | ttm_dma->dma_address[i] = 0; |
3230cfc3 KRW |
1523 | } |
1524 | ttm_pool_unpopulate(ttm); | |
1525 | return -EFAULT; | |
1526 | } | |
fd1496a0 AC |
1527 | |
1528 | ttm_dma->dma_address[i] = addr; | |
3230cfc3 KRW |
1529 | } |
1530 | return 0; | |
1531 | } | |
1532 | ||
1533 | static void | |
1534 | nouveau_ttm_tt_unpopulate(struct ttm_tt *ttm) | |
1535 | { | |
8e7e7052 | 1536 | struct ttm_dma_tt *ttm_dma = (void *)ttm; |
ebb945a9 | 1537 | struct nouveau_drm *drm; |
be83cd4e | 1538 | struct nvkm_device *device; |
3230cfc3 | 1539 | struct drm_device *dev; |
fd1496a0 | 1540 | struct device *pdev; |
3230cfc3 | 1541 | unsigned i; |
22b33e8e DA |
1542 | bool slave = !!(ttm->page_flags & TTM_PAGE_FLAG_SG); |
1543 | ||
1544 | if (slave) | |
1545 | return; | |
3230cfc3 | 1546 | |
ebb945a9 | 1547 | drm = nouveau_bdev(ttm->bdev); |
1167c6bc | 1548 | device = nvxx_device(&drm->client.device); |
ebb945a9 | 1549 | dev = drm->dev; |
26c9e8ef | 1550 | pdev = device->dev; |
3230cfc3 | 1551 | |
a7fb8a23 | 1552 | #if IS_ENABLED(CONFIG_AGP) |
340b0e7c | 1553 | if (drm->agp.bridge) { |
dea7e0ac JG |
1554 | ttm_agp_tt_unpopulate(ttm); |
1555 | return; | |
1556 | } | |
1557 | #endif | |
1558 | ||
9bcd38de | 1559 | #if IS_ENABLED(CONFIG_SWIOTLB) && IS_ENABLED(CONFIG_X86) |
3230cfc3 | 1560 | if (swiotlb_nr_tbl()) { |
8e7e7052 | 1561 | ttm_dma_unpopulate((void *)ttm, dev->dev); |
3230cfc3 KRW |
1562 | return; |
1563 | } | |
1564 | #endif | |
1565 | ||
1566 | for (i = 0; i < ttm->num_pages; i++) { | |
8e7e7052 | 1567 | if (ttm_dma->dma_address[i]) { |
fd1496a0 AC |
1568 | dma_unmap_page(pdev, ttm_dma->dma_address[i], PAGE_SIZE, |
1569 | DMA_BIDIRECTIONAL); | |
3230cfc3 KRW |
1570 | } |
1571 | } | |
1572 | ||
1573 | ttm_pool_unpopulate(ttm); | |
1574 | } | |
1575 | ||
875ac34a | 1576 | void |
809e9447 | 1577 | nouveau_bo_fence(struct nouveau_bo *nvbo, struct nouveau_fence *fence, bool exclusive) |
875ac34a | 1578 | { |
29ba89b2 | 1579 | struct reservation_object *resv = nvbo->bo.resv; |
bdaf7ddf | 1580 | |
809e9447 ML |
1581 | if (exclusive) |
1582 | reservation_object_add_excl_fence(resv, &fence->base); | |
1583 | else if (fence) | |
1584 | reservation_object_add_shared_fence(resv, &fence->base); | |
875ac34a BS |
1585 | } |
1586 | ||
6ee73861 | 1587 | struct ttm_bo_driver nouveau_bo_driver = { |
649bf3ca | 1588 | .ttm_tt_create = &nouveau_ttm_tt_create, |
3230cfc3 KRW |
1589 | .ttm_tt_populate = &nouveau_ttm_tt_populate, |
1590 | .ttm_tt_unpopulate = &nouveau_ttm_tt_unpopulate, | |
6ee73861 BS |
1591 | .invalidate_caches = nouveau_bo_invalidate_caches, |
1592 | .init_mem_type = nouveau_bo_init_mem_type, | |
a2ab19fe | 1593 | .eviction_valuable = ttm_bo_eviction_valuable, |
6ee73861 | 1594 | .evict_flags = nouveau_bo_evict_flags, |
a4154bbf | 1595 | .move_notify = nouveau_bo_move_ntfy, |
6ee73861 BS |
1596 | .move = nouveau_bo_move, |
1597 | .verify_access = nouveau_bo_verify_access, | |
f32f02fd JG |
1598 | .fault_reserve_notify = &nouveau_ttm_fault_reserve_notify, |
1599 | .io_mem_reserve = &nouveau_ttm_io_mem_reserve, | |
1600 | .io_mem_free = &nouveau_ttm_io_mem_free, | |
ea642c32 | 1601 | .io_mem_pfn = ttm_bo_default_io_mem_pfn, |
6ee73861 | 1602 | }; |