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6ee73861 BS |
1 | /* |
2 | * Copyright 2007 Dave Airlied | |
3 | * All Rights Reserved. | |
4 | * | |
5 | * Permission is hereby granted, free of charge, to any person obtaining a | |
6 | * copy of this software and associated documentation files (the "Software"), | |
7 | * to deal in the Software without restriction, including without limitation | |
8 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
9 | * and/or sell copies of the Software, and to permit persons to whom the | |
10 | * Software is furnished to do so, subject to the following conditions: | |
11 | * | |
12 | * The above copyright notice and this permission notice (including the next | |
13 | * paragraph) shall be included in all copies or substantial portions of the | |
14 | * Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
20 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
21 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
22 | * OTHER DEALINGS IN THE SOFTWARE. | |
23 | */ | |
24 | /* | |
25 | * Authors: Dave Airlied <airlied@linux.ie> | |
26 | * Ben Skeggs <darktama@iinet.net.au> | |
27 | * Jeremy Kolb <jkolb@brandeis.edu> | |
28 | */ | |
29 | ||
30 | #include "drmP.h" | |
31 | ||
32 | #include "nouveau_drm.h" | |
33 | #include "nouveau_drv.h" | |
34 | #include "nouveau_dma.h" | |
35 | ||
a510604d | 36 | #include <linux/log2.h> |
5a0e3ad6 | 37 | #include <linux/slab.h> |
a510604d | 38 | |
6ee73861 BS |
39 | static void |
40 | nouveau_bo_del_ttm(struct ttm_buffer_object *bo) | |
41 | { | |
42 | struct drm_nouveau_private *dev_priv = nouveau_bdev(bo->bdev); | |
a0af9add | 43 | struct drm_device *dev = dev_priv->dev; |
6ee73861 BS |
44 | struct nouveau_bo *nvbo = nouveau_bo(bo); |
45 | ||
6ee73861 BS |
46 | if (unlikely(nvbo->gem)) |
47 | DRM_ERROR("bo %p still attached to GEM object\n", bo); | |
48 | ||
a5cf68b0 | 49 | nv10_mem_put_tile_region(dev, nvbo->tile, NULL); |
6ee73861 BS |
50 | kfree(nvbo); |
51 | } | |
52 | ||
a0af9add FJ |
53 | static void |
54 | nouveau_bo_fixup_align(struct drm_device *dev, | |
55 | uint32_t tile_mode, uint32_t tile_flags, | |
56 | int *align, int *size) | |
57 | { | |
58 | struct drm_nouveau_private *dev_priv = dev->dev_private; | |
59 | ||
60 | /* | |
61 | * Some of the tile_flags have a periodic structure of N*4096 bytes, | |
eb1dba0e MM |
62 | * align to to that as well as the page size. Align the size to the |
63 | * appropriate boundaries. This does imply that sizes are rounded up | |
64 | * 3-7 pages, so be aware of this and do not waste memory by allocating | |
65 | * many small buffers. | |
a0af9add FJ |
66 | */ |
67 | if (dev_priv->card_type == NV_50) { | |
a76fb4e8 | 68 | uint32_t block_size = dev_priv->vram_size >> 15; |
a510604d MM |
69 | int i; |
70 | ||
a0af9add FJ |
71 | switch (tile_flags) { |
72 | case 0x1800: | |
73 | case 0x2800: | |
74 | case 0x4800: | |
75 | case 0x7a00: | |
a510604d | 76 | if (is_power_of_2(block_size)) { |
a510604d MM |
77 | for (i = 1; i < 10; i++) { |
78 | *align = 12 * i * block_size; | |
79 | if (!(*align % 65536)) | |
80 | break; | |
81 | } | |
a0af9add | 82 | } else { |
a510604d MM |
83 | for (i = 1; i < 10; i++) { |
84 | *align = 8 * i * block_size; | |
85 | if (!(*align % 65536)) | |
86 | break; | |
87 | } | |
a0af9add | 88 | } |
eb1dba0e | 89 | *size = roundup(*size, *align); |
a0af9add FJ |
90 | break; |
91 | default: | |
92 | break; | |
93 | } | |
94 | ||
95 | } else { | |
96 | if (tile_mode) { | |
97 | if (dev_priv->chipset >= 0x40) { | |
98 | *align = 65536; | |
99 | *size = roundup(*size, 64 * tile_mode); | |
100 | ||
101 | } else if (dev_priv->chipset >= 0x30) { | |
102 | *align = 32768; | |
103 | *size = roundup(*size, 64 * tile_mode); | |
104 | ||
105 | } else if (dev_priv->chipset >= 0x20) { | |
106 | *align = 16384; | |
107 | *size = roundup(*size, 64 * tile_mode); | |
108 | ||
109 | } else if (dev_priv->chipset >= 0x10) { | |
110 | *align = 16384; | |
111 | *size = roundup(*size, 32 * tile_mode); | |
112 | } | |
113 | } | |
114 | } | |
115 | ||
1c7059e4 MM |
116 | /* ALIGN works only on powers of two. */ |
117 | *size = roundup(*size, PAGE_SIZE); | |
a0af9add FJ |
118 | |
119 | if (dev_priv->card_type == NV_50) { | |
1c7059e4 | 120 | *size = roundup(*size, 65536); |
a0af9add FJ |
121 | *align = max(65536, *align); |
122 | } | |
123 | } | |
124 | ||
6ee73861 BS |
125 | int |
126 | nouveau_bo_new(struct drm_device *dev, struct nouveau_channel *chan, | |
127 | int size, int align, uint32_t flags, uint32_t tile_mode, | |
128 | uint32_t tile_flags, bool no_vm, bool mappable, | |
129 | struct nouveau_bo **pnvbo) | |
130 | { | |
131 | struct drm_nouveau_private *dev_priv = dev->dev_private; | |
132 | struct nouveau_bo *nvbo; | |
8dea4a19 | 133 | int ret = 0; |
6ee73861 BS |
134 | |
135 | nvbo = kzalloc(sizeof(struct nouveau_bo), GFP_KERNEL); | |
136 | if (!nvbo) | |
137 | return -ENOMEM; | |
138 | INIT_LIST_HEAD(&nvbo->head); | |
139 | INIT_LIST_HEAD(&nvbo->entry); | |
140 | nvbo->mappable = mappable; | |
141 | nvbo->no_vm = no_vm; | |
142 | nvbo->tile_mode = tile_mode; | |
143 | nvbo->tile_flags = tile_flags; | |
699ddfd9 | 144 | nvbo->bo.bdev = &dev_priv->ttm.bdev; |
6ee73861 | 145 | |
f13b3263 FJ |
146 | nouveau_bo_fixup_align(dev, tile_mode, nouveau_bo_tile_layout(nvbo), |
147 | &align, &size); | |
6ee73861 BS |
148 | align >>= PAGE_SHIFT; |
149 | ||
78ad0f7b | 150 | nouveau_bo_placement_set(nvbo, flags, 0); |
6ee73861 BS |
151 | |
152 | nvbo->channel = chan; | |
6ee73861 BS |
153 | ret = ttm_bo_init(&dev_priv->ttm.bdev, &nvbo->bo, size, |
154 | ttm_bo_type_device, &nvbo->placement, align, 0, | |
155 | false, NULL, size, nouveau_bo_del_ttm); | |
6ee73861 BS |
156 | if (ret) { |
157 | /* ttm will call nouveau_bo_del_ttm if it fails.. */ | |
158 | return ret; | |
159 | } | |
90af89b9 | 160 | nvbo->channel = NULL; |
6ee73861 | 161 | |
6ee73861 BS |
162 | *pnvbo = nvbo; |
163 | return 0; | |
164 | } | |
165 | ||
78ad0f7b FJ |
166 | static void |
167 | set_placement_list(uint32_t *pl, unsigned *n, uint32_t type, uint32_t flags) | |
168 | { | |
169 | *n = 0; | |
170 | ||
171 | if (type & TTM_PL_FLAG_VRAM) | |
172 | pl[(*n)++] = TTM_PL_FLAG_VRAM | flags; | |
173 | if (type & TTM_PL_FLAG_TT) | |
174 | pl[(*n)++] = TTM_PL_FLAG_TT | flags; | |
175 | if (type & TTM_PL_FLAG_SYSTEM) | |
176 | pl[(*n)++] = TTM_PL_FLAG_SYSTEM | flags; | |
177 | } | |
178 | ||
699ddfd9 FJ |
179 | static void |
180 | set_placement_range(struct nouveau_bo *nvbo, uint32_t type) | |
181 | { | |
182 | struct drm_nouveau_private *dev_priv = nouveau_bdev(nvbo->bo.bdev); | |
183 | ||
184 | if (dev_priv->card_type == NV_10 && | |
185 | nvbo->tile_mode && (type & TTM_PL_FLAG_VRAM)) { | |
186 | /* | |
187 | * Make sure that the color and depth buffers are handled | |
188 | * by independent memory controller units. Up to a 9x | |
189 | * speed up when alpha-blending and depth-test are enabled | |
190 | * at the same time. | |
191 | */ | |
192 | int vram_pages = dev_priv->vram_size >> PAGE_SHIFT; | |
193 | ||
194 | if (nvbo->tile_flags & NOUVEAU_GEM_TILE_ZETA) { | |
195 | nvbo->placement.fpfn = vram_pages / 2; | |
196 | nvbo->placement.lpfn = ~0; | |
197 | } else { | |
198 | nvbo->placement.fpfn = 0; | |
199 | nvbo->placement.lpfn = vram_pages / 2; | |
200 | } | |
201 | } | |
202 | } | |
203 | ||
6ee73861 | 204 | void |
78ad0f7b | 205 | nouveau_bo_placement_set(struct nouveau_bo *nvbo, uint32_t type, uint32_t busy) |
6ee73861 | 206 | { |
78ad0f7b FJ |
207 | struct ttm_placement *pl = &nvbo->placement; |
208 | uint32_t flags = TTM_PL_MASK_CACHING | | |
209 | (nvbo->pin_refcnt ? TTM_PL_FLAG_NO_EVICT : 0); | |
210 | ||
211 | pl->placement = nvbo->placements; | |
212 | set_placement_list(nvbo->placements, &pl->num_placement, | |
213 | type, flags); | |
214 | ||
215 | pl->busy_placement = nvbo->busy_placements; | |
216 | set_placement_list(nvbo->busy_placements, &pl->num_busy_placement, | |
217 | type | busy, flags); | |
699ddfd9 FJ |
218 | |
219 | set_placement_range(nvbo, type); | |
6ee73861 BS |
220 | } |
221 | ||
222 | int | |
223 | nouveau_bo_pin(struct nouveau_bo *nvbo, uint32_t memtype) | |
224 | { | |
225 | struct drm_nouveau_private *dev_priv = nouveau_bdev(nvbo->bo.bdev); | |
226 | struct ttm_buffer_object *bo = &nvbo->bo; | |
78ad0f7b | 227 | int ret; |
6ee73861 BS |
228 | |
229 | if (nvbo->pin_refcnt && !(memtype & (1 << bo->mem.mem_type))) { | |
230 | NV_ERROR(nouveau_bdev(bo->bdev)->dev, | |
231 | "bo %p pinned elsewhere: 0x%08x vs 0x%08x\n", bo, | |
232 | 1 << bo->mem.mem_type, memtype); | |
233 | return -EINVAL; | |
234 | } | |
235 | ||
236 | if (nvbo->pin_refcnt++) | |
237 | return 0; | |
238 | ||
239 | ret = ttm_bo_reserve(bo, false, false, false, 0); | |
240 | if (ret) | |
241 | goto out; | |
242 | ||
78ad0f7b | 243 | nouveau_bo_placement_set(nvbo, memtype, 0); |
6ee73861 | 244 | |
9d87fa21 | 245 | ret = ttm_bo_validate(bo, &nvbo->placement, false, false, false); |
6ee73861 BS |
246 | if (ret == 0) { |
247 | switch (bo->mem.mem_type) { | |
248 | case TTM_PL_VRAM: | |
249 | dev_priv->fb_aper_free -= bo->mem.size; | |
250 | break; | |
251 | case TTM_PL_TT: | |
252 | dev_priv->gart_info.aper_free -= bo->mem.size; | |
253 | break; | |
254 | default: | |
255 | break; | |
256 | } | |
257 | } | |
258 | ttm_bo_unreserve(bo); | |
259 | out: | |
260 | if (unlikely(ret)) | |
261 | nvbo->pin_refcnt--; | |
262 | return ret; | |
263 | } | |
264 | ||
265 | int | |
266 | nouveau_bo_unpin(struct nouveau_bo *nvbo) | |
267 | { | |
268 | struct drm_nouveau_private *dev_priv = nouveau_bdev(nvbo->bo.bdev); | |
269 | struct ttm_buffer_object *bo = &nvbo->bo; | |
78ad0f7b | 270 | int ret; |
6ee73861 BS |
271 | |
272 | if (--nvbo->pin_refcnt) | |
273 | return 0; | |
274 | ||
275 | ret = ttm_bo_reserve(bo, false, false, false, 0); | |
276 | if (ret) | |
277 | return ret; | |
278 | ||
78ad0f7b | 279 | nouveau_bo_placement_set(nvbo, bo->mem.placement, 0); |
6ee73861 | 280 | |
9d87fa21 | 281 | ret = ttm_bo_validate(bo, &nvbo->placement, false, false, false); |
6ee73861 BS |
282 | if (ret == 0) { |
283 | switch (bo->mem.mem_type) { | |
284 | case TTM_PL_VRAM: | |
285 | dev_priv->fb_aper_free += bo->mem.size; | |
286 | break; | |
287 | case TTM_PL_TT: | |
288 | dev_priv->gart_info.aper_free += bo->mem.size; | |
289 | break; | |
290 | default: | |
291 | break; | |
292 | } | |
293 | } | |
294 | ||
295 | ttm_bo_unreserve(bo); | |
296 | return ret; | |
297 | } | |
298 | ||
299 | int | |
300 | nouveau_bo_map(struct nouveau_bo *nvbo) | |
301 | { | |
302 | int ret; | |
303 | ||
304 | ret = ttm_bo_reserve(&nvbo->bo, false, false, false, 0); | |
305 | if (ret) | |
306 | return ret; | |
307 | ||
308 | ret = ttm_bo_kmap(&nvbo->bo, 0, nvbo->bo.mem.num_pages, &nvbo->kmap); | |
309 | ttm_bo_unreserve(&nvbo->bo); | |
310 | return ret; | |
311 | } | |
312 | ||
313 | void | |
314 | nouveau_bo_unmap(struct nouveau_bo *nvbo) | |
315 | { | |
9d59e8a1 BS |
316 | if (nvbo) |
317 | ttm_bo_kunmap(&nvbo->kmap); | |
6ee73861 BS |
318 | } |
319 | ||
320 | u16 | |
321 | nouveau_bo_rd16(struct nouveau_bo *nvbo, unsigned index) | |
322 | { | |
323 | bool is_iomem; | |
324 | u16 *mem = ttm_kmap_obj_virtual(&nvbo->kmap, &is_iomem); | |
325 | mem = &mem[index]; | |
326 | if (is_iomem) | |
327 | return ioread16_native((void __force __iomem *)mem); | |
328 | else | |
329 | return *mem; | |
330 | } | |
331 | ||
332 | void | |
333 | nouveau_bo_wr16(struct nouveau_bo *nvbo, unsigned index, u16 val) | |
334 | { | |
335 | bool is_iomem; | |
336 | u16 *mem = ttm_kmap_obj_virtual(&nvbo->kmap, &is_iomem); | |
337 | mem = &mem[index]; | |
338 | if (is_iomem) | |
339 | iowrite16_native(val, (void __force __iomem *)mem); | |
340 | else | |
341 | *mem = val; | |
342 | } | |
343 | ||
344 | u32 | |
345 | nouveau_bo_rd32(struct nouveau_bo *nvbo, unsigned index) | |
346 | { | |
347 | bool is_iomem; | |
348 | u32 *mem = ttm_kmap_obj_virtual(&nvbo->kmap, &is_iomem); | |
349 | mem = &mem[index]; | |
350 | if (is_iomem) | |
351 | return ioread32_native((void __force __iomem *)mem); | |
352 | else | |
353 | return *mem; | |
354 | } | |
355 | ||
356 | void | |
357 | nouveau_bo_wr32(struct nouveau_bo *nvbo, unsigned index, u32 val) | |
358 | { | |
359 | bool is_iomem; | |
360 | u32 *mem = ttm_kmap_obj_virtual(&nvbo->kmap, &is_iomem); | |
361 | mem = &mem[index]; | |
362 | if (is_iomem) | |
363 | iowrite32_native(val, (void __force __iomem *)mem); | |
364 | else | |
365 | *mem = val; | |
366 | } | |
367 | ||
368 | static struct ttm_backend * | |
369 | nouveau_bo_create_ttm_backend_entry(struct ttm_bo_device *bdev) | |
370 | { | |
371 | struct drm_nouveau_private *dev_priv = nouveau_bdev(bdev); | |
372 | struct drm_device *dev = dev_priv->dev; | |
373 | ||
374 | switch (dev_priv->gart_info.type) { | |
b694dfb2 | 375 | #if __OS_HAS_AGP |
6ee73861 BS |
376 | case NOUVEAU_GART_AGP: |
377 | return ttm_agp_backend_init(bdev, dev->agp->bridge); | |
b694dfb2 | 378 | #endif |
6ee73861 BS |
379 | case NOUVEAU_GART_SGDMA: |
380 | return nouveau_sgdma_init_ttm(dev); | |
381 | default: | |
382 | NV_ERROR(dev, "Unknown GART type %d\n", | |
383 | dev_priv->gart_info.type); | |
384 | break; | |
385 | } | |
386 | ||
387 | return NULL; | |
388 | } | |
389 | ||
390 | static int | |
391 | nouveau_bo_invalidate_caches(struct ttm_bo_device *bdev, uint32_t flags) | |
392 | { | |
393 | /* We'll do this from user space. */ | |
394 | return 0; | |
395 | } | |
396 | ||
397 | static int | |
398 | nouveau_bo_init_mem_type(struct ttm_bo_device *bdev, uint32_t type, | |
399 | struct ttm_mem_type_manager *man) | |
400 | { | |
401 | struct drm_nouveau_private *dev_priv = nouveau_bdev(bdev); | |
402 | struct drm_device *dev = dev_priv->dev; | |
403 | ||
404 | switch (type) { | |
405 | case TTM_PL_SYSTEM: | |
406 | man->flags = TTM_MEMTYPE_FLAG_MAPPABLE; | |
407 | man->available_caching = TTM_PL_MASK_CACHING; | |
408 | man->default_caching = TTM_PL_FLAG_CACHED; | |
409 | break; | |
410 | case TTM_PL_VRAM: | |
d961db75 | 411 | man->func = &ttm_bo_manager_func; |
6ee73861 | 412 | man->flags = TTM_MEMTYPE_FLAG_FIXED | |
f32f02fd | 413 | TTM_MEMTYPE_FLAG_MAPPABLE; |
6ee73861 BS |
414 | man->available_caching = TTM_PL_FLAG_UNCACHED | |
415 | TTM_PL_FLAG_WC; | |
416 | man->default_caching = TTM_PL_FLAG_WC; | |
fbd2895e BS |
417 | if (dev_priv->card_type == NV_50) |
418 | man->gpu_offset = 0x40000000; | |
419 | else | |
420 | man->gpu_offset = 0; | |
6ee73861 BS |
421 | break; |
422 | case TTM_PL_TT: | |
d961db75 | 423 | man->func = &ttm_bo_manager_func; |
6ee73861 BS |
424 | switch (dev_priv->gart_info.type) { |
425 | case NOUVEAU_GART_AGP: | |
f32f02fd | 426 | man->flags = TTM_MEMTYPE_FLAG_MAPPABLE; |
6ee73861 BS |
427 | man->available_caching = TTM_PL_FLAG_UNCACHED; |
428 | man->default_caching = TTM_PL_FLAG_UNCACHED; | |
429 | break; | |
430 | case NOUVEAU_GART_SGDMA: | |
431 | man->flags = TTM_MEMTYPE_FLAG_MAPPABLE | | |
432 | TTM_MEMTYPE_FLAG_CMA; | |
433 | man->available_caching = TTM_PL_MASK_CACHING; | |
434 | man->default_caching = TTM_PL_FLAG_CACHED; | |
435 | break; | |
436 | default: | |
437 | NV_ERROR(dev, "Unknown GART type: %d\n", | |
438 | dev_priv->gart_info.type); | |
439 | return -EINVAL; | |
440 | } | |
6ee73861 BS |
441 | man->gpu_offset = dev_priv->vm_gart_base; |
442 | break; | |
443 | default: | |
444 | NV_ERROR(dev, "Unsupported memory type %u\n", (unsigned)type); | |
445 | return -EINVAL; | |
446 | } | |
447 | return 0; | |
448 | } | |
449 | ||
450 | static void | |
451 | nouveau_bo_evict_flags(struct ttm_buffer_object *bo, struct ttm_placement *pl) | |
452 | { | |
453 | struct nouveau_bo *nvbo = nouveau_bo(bo); | |
454 | ||
455 | switch (bo->mem.mem_type) { | |
22fbd538 | 456 | case TTM_PL_VRAM: |
78ad0f7b FJ |
457 | nouveau_bo_placement_set(nvbo, TTM_PL_FLAG_TT, |
458 | TTM_PL_FLAG_SYSTEM); | |
22fbd538 | 459 | break; |
6ee73861 | 460 | default: |
78ad0f7b | 461 | nouveau_bo_placement_set(nvbo, TTM_PL_FLAG_SYSTEM, 0); |
6ee73861 BS |
462 | break; |
463 | } | |
22fbd538 FJ |
464 | |
465 | *pl = nvbo->placement; | |
6ee73861 BS |
466 | } |
467 | ||
468 | ||
469 | /* GPU-assisted copy using NV_MEMORY_TO_MEMORY_FORMAT, can access | |
470 | * TTM_PL_{VRAM,TT} directly. | |
471 | */ | |
a0af9add | 472 | |
6ee73861 BS |
473 | static int |
474 | nouveau_bo_move_accel_cleanup(struct nouveau_channel *chan, | |
9d87fa21 JG |
475 | struct nouveau_bo *nvbo, bool evict, |
476 | bool no_wait_reserve, bool no_wait_gpu, | |
6ee73861 BS |
477 | struct ttm_mem_reg *new_mem) |
478 | { | |
479 | struct nouveau_fence *fence = NULL; | |
480 | int ret; | |
481 | ||
482 | ret = nouveau_fence_new(chan, &fence, true); | |
483 | if (ret) | |
484 | return ret; | |
485 | ||
64798817 | 486 | ret = ttm_bo_move_accel_cleanup(&nvbo->bo, fence, NULL, evict, |
311ab694 | 487 | no_wait_reserve, no_wait_gpu, new_mem); |
382d62e5 | 488 | nouveau_fence_unref(&fence); |
6ee73861 BS |
489 | return ret; |
490 | } | |
491 | ||
492 | static inline uint32_t | |
f1ab0cc9 BS |
493 | nouveau_bo_mem_ctxdma(struct ttm_buffer_object *bo, |
494 | struct nouveau_channel *chan, struct ttm_mem_reg *mem) | |
6ee73861 | 495 | { |
f1ab0cc9 BS |
496 | struct nouveau_bo *nvbo = nouveau_bo(bo); |
497 | ||
498 | if (nvbo->no_vm) { | |
6ee73861 BS |
499 | if (mem->mem_type == TTM_PL_TT) |
500 | return NvDmaGART; | |
501 | return NvDmaVRAM; | |
502 | } | |
503 | ||
504 | if (mem->mem_type == TTM_PL_TT) | |
505 | return chan->gart_handle; | |
506 | return chan->vram_handle; | |
507 | } | |
508 | ||
509 | static int | |
f1ab0cc9 BS |
510 | nv50_bo_move_m2mf(struct nouveau_channel *chan, struct ttm_buffer_object *bo, |
511 | struct ttm_mem_reg *old_mem, struct ttm_mem_reg *new_mem) | |
6ee73861 | 512 | { |
6ee73861 | 513 | struct drm_nouveau_private *dev_priv = nouveau_bdev(bo->bdev); |
f1ab0cc9 BS |
514 | struct nouveau_bo *nvbo = nouveau_bo(bo); |
515 | u64 length = (new_mem->num_pages << PAGE_SHIFT); | |
516 | u64 src_offset, dst_offset; | |
6ee73861 BS |
517 | int ret; |
518 | ||
d961db75 BS |
519 | src_offset = old_mem->start << PAGE_SHIFT; |
520 | dst_offset = new_mem->start << PAGE_SHIFT; | |
f1ab0cc9 BS |
521 | if (!nvbo->no_vm) { |
522 | if (old_mem->mem_type == TTM_PL_VRAM) | |
6ee73861 | 523 | src_offset += dev_priv->vm_vram_base; |
6ee73861 | 524 | else |
f1ab0cc9 BS |
525 | src_offset += dev_priv->vm_gart_base; |
526 | ||
527 | if (new_mem->mem_type == TTM_PL_VRAM) | |
6ee73861 | 528 | dst_offset += dev_priv->vm_vram_base; |
f1ab0cc9 BS |
529 | else |
530 | dst_offset += dev_priv->vm_gart_base; | |
6ee73861 BS |
531 | } |
532 | ||
533 | ret = RING_SPACE(chan, 3); | |
534 | if (ret) | |
535 | return ret; | |
6ee73861 | 536 | |
f1ab0cc9 BS |
537 | BEGIN_RING(chan, NvSubM2MF, 0x0184, 2); |
538 | OUT_RING (chan, nouveau_bo_mem_ctxdma(bo, chan, old_mem)); | |
539 | OUT_RING (chan, nouveau_bo_mem_ctxdma(bo, chan, new_mem)); | |
540 | ||
541 | while (length) { | |
542 | u32 amount, stride, height; | |
543 | ||
5220b3c1 BS |
544 | amount = min(length, (u64)(4 * 1024 * 1024)); |
545 | stride = 16 * 4; | |
f1ab0cc9 BS |
546 | height = amount / stride; |
547 | ||
f13b3263 FJ |
548 | if (new_mem->mem_type == TTM_PL_VRAM && |
549 | nouveau_bo_tile_layout(nvbo)) { | |
f1ab0cc9 BS |
550 | ret = RING_SPACE(chan, 8); |
551 | if (ret) | |
552 | return ret; | |
553 | ||
554 | BEGIN_RING(chan, NvSubM2MF, 0x0200, 7); | |
555 | OUT_RING (chan, 0); | |
5220b3c1 | 556 | OUT_RING (chan, 0); |
f1ab0cc9 BS |
557 | OUT_RING (chan, stride); |
558 | OUT_RING (chan, height); | |
559 | OUT_RING (chan, 1); | |
560 | OUT_RING (chan, 0); | |
561 | OUT_RING (chan, 0); | |
562 | } else { | |
563 | ret = RING_SPACE(chan, 2); | |
564 | if (ret) | |
565 | return ret; | |
566 | ||
567 | BEGIN_RING(chan, NvSubM2MF, 0x0200, 1); | |
568 | OUT_RING (chan, 1); | |
569 | } | |
f13b3263 FJ |
570 | if (old_mem->mem_type == TTM_PL_VRAM && |
571 | nouveau_bo_tile_layout(nvbo)) { | |
f1ab0cc9 BS |
572 | ret = RING_SPACE(chan, 8); |
573 | if (ret) | |
574 | return ret; | |
575 | ||
576 | BEGIN_RING(chan, NvSubM2MF, 0x021c, 7); | |
577 | OUT_RING (chan, 0); | |
5220b3c1 | 578 | OUT_RING (chan, 0); |
f1ab0cc9 BS |
579 | OUT_RING (chan, stride); |
580 | OUT_RING (chan, height); | |
581 | OUT_RING (chan, 1); | |
582 | OUT_RING (chan, 0); | |
583 | OUT_RING (chan, 0); | |
584 | } else { | |
585 | ret = RING_SPACE(chan, 2); | |
586 | if (ret) | |
587 | return ret; | |
588 | ||
589 | BEGIN_RING(chan, NvSubM2MF, 0x021c, 1); | |
590 | OUT_RING (chan, 1); | |
591 | } | |
592 | ||
593 | ret = RING_SPACE(chan, 14); | |
6ee73861 BS |
594 | if (ret) |
595 | return ret; | |
f1ab0cc9 BS |
596 | |
597 | BEGIN_RING(chan, NvSubM2MF, 0x0238, 2); | |
598 | OUT_RING (chan, upper_32_bits(src_offset)); | |
599 | OUT_RING (chan, upper_32_bits(dst_offset)); | |
600 | BEGIN_RING(chan, NvSubM2MF, 0x030c, 8); | |
601 | OUT_RING (chan, lower_32_bits(src_offset)); | |
602 | OUT_RING (chan, lower_32_bits(dst_offset)); | |
603 | OUT_RING (chan, stride); | |
604 | OUT_RING (chan, stride); | |
605 | OUT_RING (chan, stride); | |
606 | OUT_RING (chan, height); | |
607 | OUT_RING (chan, 0x00000101); | |
608 | OUT_RING (chan, 0x00000000); | |
609 | BEGIN_RING(chan, NvSubM2MF, NV_MEMORY_TO_MEMORY_FORMAT_NOP, 1); | |
610 | OUT_RING (chan, 0); | |
611 | ||
612 | length -= amount; | |
613 | src_offset += amount; | |
614 | dst_offset += amount; | |
6ee73861 BS |
615 | } |
616 | ||
f1ab0cc9 BS |
617 | return 0; |
618 | } | |
619 | ||
620 | static int | |
621 | nv04_bo_move_m2mf(struct nouveau_channel *chan, struct ttm_buffer_object *bo, | |
622 | struct ttm_mem_reg *old_mem, struct ttm_mem_reg *new_mem) | |
623 | { | |
d961db75 BS |
624 | u32 src_offset = old_mem->start << PAGE_SHIFT; |
625 | u32 dst_offset = new_mem->start << PAGE_SHIFT; | |
f1ab0cc9 BS |
626 | u32 page_count = new_mem->num_pages; |
627 | int ret; | |
628 | ||
629 | ret = RING_SPACE(chan, 3); | |
630 | if (ret) | |
631 | return ret; | |
632 | ||
633 | BEGIN_RING(chan, NvSubM2MF, NV_MEMORY_TO_MEMORY_FORMAT_DMA_SOURCE, 2); | |
634 | OUT_RING (chan, nouveau_bo_mem_ctxdma(bo, chan, old_mem)); | |
635 | OUT_RING (chan, nouveau_bo_mem_ctxdma(bo, chan, new_mem)); | |
636 | ||
6ee73861 BS |
637 | page_count = new_mem->num_pages; |
638 | while (page_count) { | |
639 | int line_count = (page_count > 2047) ? 2047 : page_count; | |
640 | ||
6ee73861 BS |
641 | ret = RING_SPACE(chan, 11); |
642 | if (ret) | |
643 | return ret; | |
f1ab0cc9 | 644 | |
6ee73861 BS |
645 | BEGIN_RING(chan, NvSubM2MF, |
646 | NV_MEMORY_TO_MEMORY_FORMAT_OFFSET_IN, 8); | |
f1ab0cc9 BS |
647 | OUT_RING (chan, src_offset); |
648 | OUT_RING (chan, dst_offset); | |
649 | OUT_RING (chan, PAGE_SIZE); /* src_pitch */ | |
650 | OUT_RING (chan, PAGE_SIZE); /* dst_pitch */ | |
651 | OUT_RING (chan, PAGE_SIZE); /* line_length */ | |
652 | OUT_RING (chan, line_count); | |
653 | OUT_RING (chan, 0x00000101); | |
654 | OUT_RING (chan, 0x00000000); | |
6ee73861 | 655 | BEGIN_RING(chan, NvSubM2MF, NV_MEMORY_TO_MEMORY_FORMAT_NOP, 1); |
f1ab0cc9 | 656 | OUT_RING (chan, 0); |
6ee73861 BS |
657 | |
658 | page_count -= line_count; | |
659 | src_offset += (PAGE_SIZE * line_count); | |
660 | dst_offset += (PAGE_SIZE * line_count); | |
661 | } | |
662 | ||
f1ab0cc9 BS |
663 | return 0; |
664 | } | |
665 | ||
666 | static int | |
667 | nouveau_bo_move_m2mf(struct ttm_buffer_object *bo, int evict, bool intr, | |
668 | bool no_wait_reserve, bool no_wait_gpu, | |
669 | struct ttm_mem_reg *new_mem) | |
670 | { | |
671 | struct drm_nouveau_private *dev_priv = nouveau_bdev(bo->bdev); | |
672 | struct nouveau_bo *nvbo = nouveau_bo(bo); | |
673 | struct nouveau_channel *chan; | |
674 | int ret; | |
675 | ||
676 | chan = nvbo->channel; | |
6a6b73f2 | 677 | if (!chan || nvbo->no_vm) { |
f1ab0cc9 | 678 | chan = dev_priv->channel; |
e419cf09 | 679 | mutex_lock_nested(&chan->mutex, NOUVEAU_KCHANNEL_MUTEX); |
6a6b73f2 | 680 | } |
f1ab0cc9 BS |
681 | |
682 | if (dev_priv->card_type < NV_50) | |
683 | ret = nv04_bo_move_m2mf(chan, bo, &bo->mem, new_mem); | |
684 | else | |
685 | ret = nv50_bo_move_m2mf(chan, bo, &bo->mem, new_mem); | |
6a6b73f2 BS |
686 | if (ret == 0) { |
687 | ret = nouveau_bo_move_accel_cleanup(chan, nvbo, evict, | |
688 | no_wait_reserve, | |
689 | no_wait_gpu, new_mem); | |
690 | } | |
f1ab0cc9 | 691 | |
6a6b73f2 BS |
692 | if (chan == dev_priv->channel) |
693 | mutex_unlock(&chan->mutex); | |
694 | return ret; | |
6ee73861 BS |
695 | } |
696 | ||
697 | static int | |
698 | nouveau_bo_move_flipd(struct ttm_buffer_object *bo, bool evict, bool intr, | |
9d87fa21 JG |
699 | bool no_wait_reserve, bool no_wait_gpu, |
700 | struct ttm_mem_reg *new_mem) | |
6ee73861 BS |
701 | { |
702 | u32 placement_memtype = TTM_PL_FLAG_TT | TTM_PL_MASK_CACHING; | |
703 | struct ttm_placement placement; | |
704 | struct ttm_mem_reg tmp_mem; | |
705 | int ret; | |
706 | ||
707 | placement.fpfn = placement.lpfn = 0; | |
708 | placement.num_placement = placement.num_busy_placement = 1; | |
77e2b5ed | 709 | placement.placement = placement.busy_placement = &placement_memtype; |
6ee73861 BS |
710 | |
711 | tmp_mem = *new_mem; | |
712 | tmp_mem.mm_node = NULL; | |
9d87fa21 | 713 | ret = ttm_bo_mem_space(bo, &placement, &tmp_mem, intr, no_wait_reserve, no_wait_gpu); |
6ee73861 BS |
714 | if (ret) |
715 | return ret; | |
716 | ||
717 | ret = ttm_tt_bind(bo->ttm, &tmp_mem); | |
718 | if (ret) | |
719 | goto out; | |
720 | ||
9d87fa21 | 721 | ret = nouveau_bo_move_m2mf(bo, true, intr, no_wait_reserve, no_wait_gpu, &tmp_mem); |
6ee73861 BS |
722 | if (ret) |
723 | goto out; | |
724 | ||
9d87fa21 | 725 | ret = ttm_bo_move_ttm(bo, evict, no_wait_reserve, no_wait_gpu, new_mem); |
6ee73861 | 726 | out: |
42311ff9 | 727 | ttm_bo_mem_put(bo, &tmp_mem); |
6ee73861 BS |
728 | return ret; |
729 | } | |
730 | ||
731 | static int | |
732 | nouveau_bo_move_flips(struct ttm_buffer_object *bo, bool evict, bool intr, | |
9d87fa21 JG |
733 | bool no_wait_reserve, bool no_wait_gpu, |
734 | struct ttm_mem_reg *new_mem) | |
6ee73861 BS |
735 | { |
736 | u32 placement_memtype = TTM_PL_FLAG_TT | TTM_PL_MASK_CACHING; | |
737 | struct ttm_placement placement; | |
738 | struct ttm_mem_reg tmp_mem; | |
739 | int ret; | |
740 | ||
741 | placement.fpfn = placement.lpfn = 0; | |
742 | placement.num_placement = placement.num_busy_placement = 1; | |
77e2b5ed | 743 | placement.placement = placement.busy_placement = &placement_memtype; |
6ee73861 BS |
744 | |
745 | tmp_mem = *new_mem; | |
746 | tmp_mem.mm_node = NULL; | |
9d87fa21 | 747 | ret = ttm_bo_mem_space(bo, &placement, &tmp_mem, intr, no_wait_reserve, no_wait_gpu); |
6ee73861 BS |
748 | if (ret) |
749 | return ret; | |
750 | ||
9d87fa21 | 751 | ret = ttm_bo_move_ttm(bo, evict, no_wait_reserve, no_wait_gpu, &tmp_mem); |
6ee73861 BS |
752 | if (ret) |
753 | goto out; | |
754 | ||
9d87fa21 | 755 | ret = nouveau_bo_move_m2mf(bo, evict, intr, no_wait_reserve, no_wait_gpu, new_mem); |
6ee73861 BS |
756 | if (ret) |
757 | goto out; | |
758 | ||
759 | out: | |
42311ff9 | 760 | ttm_bo_mem_put(bo, &tmp_mem); |
6ee73861 BS |
761 | return ret; |
762 | } | |
763 | ||
764 | static int | |
a0af9add FJ |
765 | nouveau_bo_vm_bind(struct ttm_buffer_object *bo, struct ttm_mem_reg *new_mem, |
766 | struct nouveau_tile_reg **new_tile) | |
6ee73861 BS |
767 | { |
768 | struct drm_nouveau_private *dev_priv = nouveau_bdev(bo->bdev); | |
6ee73861 | 769 | struct drm_device *dev = dev_priv->dev; |
a0af9add FJ |
770 | struct nouveau_bo *nvbo = nouveau_bo(bo); |
771 | uint64_t offset; | |
6ee73861 BS |
772 | int ret; |
773 | ||
a0af9add FJ |
774 | if (nvbo->no_vm || new_mem->mem_type != TTM_PL_VRAM) { |
775 | /* Nothing to do. */ | |
776 | *new_tile = NULL; | |
777 | return 0; | |
778 | } | |
779 | ||
d961db75 | 780 | offset = new_mem->start << PAGE_SHIFT; |
6ee73861 | 781 | |
a0af9add | 782 | if (dev_priv->card_type == NV_50) { |
6ee73861 BS |
783 | ret = nv50_mem_vm_bind_linear(dev, |
784 | offset + dev_priv->vm_vram_base, | |
f13b3263 FJ |
785 | new_mem->size, |
786 | nouveau_bo_tile_layout(nvbo), | |
6ee73861 BS |
787 | offset); |
788 | if (ret) | |
789 | return ret; | |
a0af9add FJ |
790 | |
791 | } else if (dev_priv->card_type >= NV_10) { | |
792 | *new_tile = nv10_mem_set_tiling(dev, offset, new_mem->size, | |
a5cf68b0 FJ |
793 | nvbo->tile_mode, |
794 | nvbo->tile_flags); | |
6ee73861 BS |
795 | } |
796 | ||
a0af9add FJ |
797 | return 0; |
798 | } | |
799 | ||
800 | static void | |
801 | nouveau_bo_vm_cleanup(struct ttm_buffer_object *bo, | |
802 | struct nouveau_tile_reg *new_tile, | |
803 | struct nouveau_tile_reg **old_tile) | |
804 | { | |
805 | struct drm_nouveau_private *dev_priv = nouveau_bdev(bo->bdev); | |
806 | struct drm_device *dev = dev_priv->dev; | |
807 | ||
808 | if (dev_priv->card_type >= NV_10 && | |
809 | dev_priv->card_type < NV_50) { | |
a5cf68b0 | 810 | nv10_mem_put_tile_region(dev, *old_tile, bo->sync_obj); |
a0af9add FJ |
811 | *old_tile = new_tile; |
812 | } | |
813 | } | |
814 | ||
815 | static int | |
816 | nouveau_bo_move(struct ttm_buffer_object *bo, bool evict, bool intr, | |
9d87fa21 JG |
817 | bool no_wait_reserve, bool no_wait_gpu, |
818 | struct ttm_mem_reg *new_mem) | |
a0af9add FJ |
819 | { |
820 | struct drm_nouveau_private *dev_priv = nouveau_bdev(bo->bdev); | |
821 | struct nouveau_bo *nvbo = nouveau_bo(bo); | |
822 | struct ttm_mem_reg *old_mem = &bo->mem; | |
823 | struct nouveau_tile_reg *new_tile = NULL; | |
824 | int ret = 0; | |
825 | ||
826 | ret = nouveau_bo_vm_bind(bo, new_mem, &new_tile); | |
827 | if (ret) | |
828 | return ret; | |
829 | ||
a0af9add | 830 | /* Fake bo copy. */ |
6ee73861 BS |
831 | if (old_mem->mem_type == TTM_PL_SYSTEM && !bo->ttm) { |
832 | BUG_ON(bo->mem.mm_node != NULL); | |
833 | bo->mem = *new_mem; | |
834 | new_mem->mm_node = NULL; | |
a0af9add | 835 | goto out; |
6ee73861 BS |
836 | } |
837 | ||
b8a6a804 BS |
838 | /* Software copy if the card isn't up and running yet. */ |
839 | if (!dev_priv->channel) { | |
840 | ret = ttm_bo_move_memcpy(bo, evict, no_wait_reserve, no_wait_gpu, new_mem); | |
841 | goto out; | |
842 | } | |
843 | ||
a0af9add FJ |
844 | /* Hardware assisted copy. */ |
845 | if (new_mem->mem_type == TTM_PL_SYSTEM) | |
9d87fa21 | 846 | ret = nouveau_bo_move_flipd(bo, evict, intr, no_wait_reserve, no_wait_gpu, new_mem); |
a0af9add | 847 | else if (old_mem->mem_type == TTM_PL_SYSTEM) |
9d87fa21 | 848 | ret = nouveau_bo_move_flips(bo, evict, intr, no_wait_reserve, no_wait_gpu, new_mem); |
a0af9add | 849 | else |
9d87fa21 | 850 | ret = nouveau_bo_move_m2mf(bo, evict, intr, no_wait_reserve, no_wait_gpu, new_mem); |
6ee73861 | 851 | |
a0af9add FJ |
852 | if (!ret) |
853 | goto out; | |
854 | ||
855 | /* Fallback to software copy. */ | |
9d87fa21 | 856 | ret = ttm_bo_move_memcpy(bo, evict, no_wait_reserve, no_wait_gpu, new_mem); |
a0af9add FJ |
857 | |
858 | out: | |
859 | if (ret) | |
860 | nouveau_bo_vm_cleanup(bo, NULL, &new_tile); | |
861 | else | |
862 | nouveau_bo_vm_cleanup(bo, new_tile, &nvbo->tile); | |
863 | ||
864 | return ret; | |
6ee73861 BS |
865 | } |
866 | ||
867 | static int | |
868 | nouveau_bo_verify_access(struct ttm_buffer_object *bo, struct file *filp) | |
869 | { | |
870 | return 0; | |
871 | } | |
872 | ||
f32f02fd JG |
873 | static int |
874 | nouveau_ttm_io_mem_reserve(struct ttm_bo_device *bdev, struct ttm_mem_reg *mem) | |
875 | { | |
876 | struct ttm_mem_type_manager *man = &bdev->man[mem->mem_type]; | |
877 | struct drm_nouveau_private *dev_priv = nouveau_bdev(bdev); | |
878 | struct drm_device *dev = dev_priv->dev; | |
879 | ||
880 | mem->bus.addr = NULL; | |
881 | mem->bus.offset = 0; | |
882 | mem->bus.size = mem->num_pages << PAGE_SHIFT; | |
883 | mem->bus.base = 0; | |
884 | mem->bus.is_iomem = false; | |
885 | if (!(man->flags & TTM_MEMTYPE_FLAG_MAPPABLE)) | |
886 | return -EINVAL; | |
887 | switch (mem->mem_type) { | |
888 | case TTM_PL_SYSTEM: | |
889 | /* System memory */ | |
890 | return 0; | |
891 | case TTM_PL_TT: | |
892 | #if __OS_HAS_AGP | |
893 | if (dev_priv->gart_info.type == NOUVEAU_GART_AGP) { | |
d961db75 | 894 | mem->bus.offset = mem->start << PAGE_SHIFT; |
f32f02fd JG |
895 | mem->bus.base = dev_priv->gart_info.aper_base; |
896 | mem->bus.is_iomem = true; | |
897 | } | |
898 | #endif | |
899 | break; | |
900 | case TTM_PL_VRAM: | |
d961db75 | 901 | mem->bus.offset = mem->start << PAGE_SHIFT; |
01d73a69 | 902 | mem->bus.base = pci_resource_start(dev->pdev, 1); |
f32f02fd JG |
903 | mem->bus.is_iomem = true; |
904 | break; | |
905 | default: | |
906 | return -EINVAL; | |
907 | } | |
908 | return 0; | |
909 | } | |
910 | ||
911 | static void | |
912 | nouveau_ttm_io_mem_free(struct ttm_bo_device *bdev, struct ttm_mem_reg *mem) | |
913 | { | |
914 | } | |
915 | ||
916 | static int | |
917 | nouveau_ttm_fault_reserve_notify(struct ttm_buffer_object *bo) | |
918 | { | |
e1429b4c BS |
919 | struct drm_nouveau_private *dev_priv = nouveau_bdev(bo->bdev); |
920 | struct nouveau_bo *nvbo = nouveau_bo(bo); | |
921 | ||
922 | /* as long as the bo isn't in vram, and isn't tiled, we've got | |
923 | * nothing to do here. | |
924 | */ | |
925 | if (bo->mem.mem_type != TTM_PL_VRAM) { | |
f13b3263 FJ |
926 | if (dev_priv->card_type < NV_50 || |
927 | !nouveau_bo_tile_layout(nvbo)) | |
e1429b4c BS |
928 | return 0; |
929 | } | |
930 | ||
931 | /* make sure bo is in mappable vram */ | |
d961db75 | 932 | if (bo->mem.start + bo->mem.num_pages < dev_priv->fb_mappable_pages) |
e1429b4c BS |
933 | return 0; |
934 | ||
935 | ||
936 | nvbo->placement.fpfn = 0; | |
937 | nvbo->placement.lpfn = dev_priv->fb_mappable_pages; | |
938 | nouveau_bo_placement_set(nvbo, TTM_PL_VRAM, 0); | |
939 | return ttm_bo_validate(bo, &nvbo->placement, false, true, false); | |
f32f02fd JG |
940 | } |
941 | ||
332b242f FJ |
942 | void |
943 | nouveau_bo_fence(struct nouveau_bo *nvbo, struct nouveau_fence *fence) | |
944 | { | |
945 | spin_lock(&nvbo->bo.bdev->fence_lock); | |
946 | __nouveau_fence_unref(&nvbo->bo.sync_obj); | |
947 | ||
948 | if (likely(fence)) | |
949 | nvbo->bo.sync_obj = nouveau_fence_ref(fence); | |
950 | ||
951 | spin_unlock(&nvbo->bo.bdev->fence_lock); | |
952 | } | |
953 | ||
6ee73861 BS |
954 | struct ttm_bo_driver nouveau_bo_driver = { |
955 | .create_ttm_backend_entry = nouveau_bo_create_ttm_backend_entry, | |
956 | .invalidate_caches = nouveau_bo_invalidate_caches, | |
957 | .init_mem_type = nouveau_bo_init_mem_type, | |
958 | .evict_flags = nouveau_bo_evict_flags, | |
959 | .move = nouveau_bo_move, | |
960 | .verify_access = nouveau_bo_verify_access, | |
382d62e5 MS |
961 | .sync_obj_signaled = __nouveau_fence_signalled, |
962 | .sync_obj_wait = __nouveau_fence_wait, | |
963 | .sync_obj_flush = __nouveau_fence_flush, | |
964 | .sync_obj_unref = __nouveau_fence_unref, | |
965 | .sync_obj_ref = __nouveau_fence_ref, | |
f32f02fd JG |
966 | .fault_reserve_notify = &nouveau_ttm_fault_reserve_notify, |
967 | .io_mem_reserve = &nouveau_ttm_io_mem_reserve, | |
968 | .io_mem_free = &nouveau_ttm_io_mem_free, | |
6ee73861 BS |
969 | }; |
970 |