]> git.proxmox.com Git - mirror_ubuntu-bionic-kernel.git/blame - drivers/gpu/drm/nouveau/nouveau_drm.c
Merge branch 'drm-uapi-extern-c-fixes' of https://github.com/evelikov/linux into...
[mirror_ubuntu-bionic-kernel.git] / drivers / gpu / drm / nouveau / nouveau_drm.c
CommitLineData
94580299
BS
1/*
2 * Copyright 2012 Red Hat Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: Ben Skeggs
23 */
24
98b3a340 25#include <linux/apple-gmux.h>
77145f1c 26#include <linux/console.h>
c5fd936e 27#include <linux/delay.h>
94580299
BS
28#include <linux/module.h>
29#include <linux/pci.h>
5addcf0a 30#include <linux/pm_runtime.h>
98b3a340 31#include <linux/vgaarb.h>
5addcf0a 32#include <linux/vga_switcheroo.h>
fdb751ef 33
5addcf0a
DA
34#include "drmP.h"
35#include "drm_crtc_helper.h"
fdb751ef 36
ebb945a9 37#include <core/gpuobj.h>
c33e05a1 38#include <core/option.h>
7974dd1b
BS
39#include <core/pci.h>
40#include <core/tegra.h>
94580299 41
923bc416 42#include <nvif/class.h>
845f2725 43#include <nvif/cl0002.h>
8ed1730c 44#include <nvif/cla06f.h>
538b269b
BS
45#include <nvif/if0004.h>
46
94580299 47#include "nouveau_drm.h"
ebb945a9 48#include "nouveau_dma.h"
77145f1c
BS
49#include "nouveau_ttm.h"
50#include "nouveau_gem.h"
77145f1c 51#include "nouveau_vga.h"
b9ed919f 52#include "nouveau_hwmon.h"
77145f1c
BS
53#include "nouveau_acpi.h"
54#include "nouveau_bios.h"
55#include "nouveau_ioctl.h"
ebb945a9
BS
56#include "nouveau_abi16.h"
57#include "nouveau_fbcon.h"
58#include "nouveau_fence.h"
33b903e8 59#include "nouveau_debugfs.h"
27111a23 60#include "nouveau_usif.h"
703fa264 61#include "nouveau_connector.h"
055a65d5 62#include "nouveau_platform.h"
ebb945a9 63
94580299
BS
64MODULE_PARM_DESC(config, "option string to pass to driver core");
65static char *nouveau_config;
66module_param_named(config, nouveau_config, charp, 0400);
67
68MODULE_PARM_DESC(debug, "debug string to pass to driver core");
69static char *nouveau_debug;
70module_param_named(debug, nouveau_debug, charp, 0400);
71
ebb945a9
BS
72MODULE_PARM_DESC(noaccel, "disable kernel/abi16 acceleration");
73static int nouveau_noaccel = 0;
74module_param_named(noaccel, nouveau_noaccel, int, 0400);
75
9430738d
BS
76MODULE_PARM_DESC(modeset, "enable driver (default: auto, "
77 "0 = disabled, 1 = enabled, 2 = headless)");
78int nouveau_modeset = -1;
77145f1c
BS
79module_param_named(modeset, nouveau_modeset, int, 0400);
80
5addcf0a
DA
81MODULE_PARM_DESC(runpm, "disable (0), force enable (1), optimus only default (-1)");
82int nouveau_runtime_pm = -1;
83module_param_named(runpm, nouveau_runtime_pm, int, 0400);
84
915b4d11
DH
85static struct drm_driver driver_stub;
86static struct drm_driver driver_pci;
87static struct drm_driver driver_platform;
77145f1c 88
94580299 89static u64
420b9469 90nouveau_pci_name(struct pci_dev *pdev)
94580299
BS
91{
92 u64 name = (u64)pci_domain_nr(pdev->bus) << 32;
93 name |= pdev->bus->number << 16;
94 name |= PCI_SLOT(pdev->devfn) << 8;
95 return name | PCI_FUNC(pdev->devfn);
96}
97
420b9469
AC
98static u64
99nouveau_platform_name(struct platform_device *platformdev)
100{
101 return platformdev->id;
102}
103
104static u64
105nouveau_name(struct drm_device *dev)
106{
107 if (dev->pdev)
108 return nouveau_pci_name(dev->pdev);
109 else
110 return nouveau_platform_name(dev->platformdev);
111}
112
94580299 113static int
9ad97ede 114nouveau_cli_create(struct drm_device *dev, const char *sname,
fa6df8c1 115 int size, void **pcli)
94580299 116{
0ad72863 117 struct nouveau_cli *cli = *pcli = kzalloc(size, GFP_KERNEL);
9ad97ede 118 int ret;
0ad72863 119 if (cli) {
9ad97ede
BS
120 snprintf(cli->name, sizeof(cli->name), "%s", sname);
121 cli->dev = dev;
122
a01ca78c 123 ret = nvif_client_init(NULL, cli->name, nouveau_name(dev),
9ad97ede
BS
124 nouveau_config, nouveau_debug,
125 &cli->base);
27111a23 126 if (ret == 0) {
0ad72863 127 mutex_init(&cli->mutex);
27111a23
BS
128 usif_client_init(cli);
129 }
94580299 130 return ret;
dd5700ea 131 }
0ad72863 132 return -ENOMEM;
94580299
BS
133}
134
135static void
136nouveau_cli_destroy(struct nouveau_cli *cli)
137{
be83cd4e 138 nvkm_vm_ref(NULL, &nvxx_client(&cli->base)->vm, NULL);
0ad72863 139 nvif_client_fini(&cli->base);
27111a23 140 usif_client_fini(cli);
f5654d95 141 kfree(cli);
94580299
BS
142}
143
ebb945a9
BS
144static void
145nouveau_accel_fini(struct nouveau_drm *drm)
146{
fbd58ebd 147 nouveau_channel_idle(drm->channel);
0ad72863 148 nvif_object_fini(&drm->ntfy);
f027f491 149 nvkm_gpuobj_del(&drm->notify);
fbd58ebd 150 nvif_notify_fini(&drm->flip);
0ad72863 151 nvif_object_fini(&drm->nvsw);
fbd58ebd
BS
152 nouveau_channel_del(&drm->channel);
153
154 nouveau_channel_idle(drm->cechan);
0ad72863 155 nvif_object_fini(&drm->ttm.copy);
fbd58ebd
BS
156 nouveau_channel_del(&drm->cechan);
157
ebb945a9
BS
158 if (drm->fence)
159 nouveau_fence(drm)->dtor(drm);
160}
161
162static void
163nouveau_accel_init(struct nouveau_drm *drm)
164{
967e7bde 165 struct nvif_device *device = &drm->device;
41a63406 166 struct nvif_sclass *sclass;
49981046 167 u32 arg0, arg1;
41a63406 168 int ret, i, n;
ebb945a9 169
967e7bde 170 if (nouveau_noaccel)
ebb945a9
BS
171 return;
172
173 /* initialise synchronisation routines */
967e7bde
BS
174 /*XXX: this is crap, but the fence/channel stuff is a little
175 * backwards in some places. this will be fixed.
176 */
41a63406 177 ret = n = nvif_object_sclass_get(&device->object, &sclass);
967e7bde
BS
178 if (ret < 0)
179 return;
180
41a63406
BS
181 for (ret = -ENOSYS, i = 0; i < n; i++) {
182 switch (sclass[i].oclass) {
bbf8906b 183 case NV03_CHANNEL_DMA:
967e7bde
BS
184 ret = nv04_fence_create(drm);
185 break;
bbf8906b 186 case NV10_CHANNEL_DMA:
967e7bde
BS
187 ret = nv10_fence_create(drm);
188 break;
bbf8906b
BS
189 case NV17_CHANNEL_DMA:
190 case NV40_CHANNEL_DMA:
967e7bde
BS
191 ret = nv17_fence_create(drm);
192 break;
bbf8906b 193 case NV50_CHANNEL_GPFIFO:
967e7bde
BS
194 ret = nv50_fence_create(drm);
195 break;
bbf8906b 196 case G82_CHANNEL_GPFIFO:
967e7bde
BS
197 ret = nv84_fence_create(drm);
198 break;
bbf8906b
BS
199 case FERMI_CHANNEL_GPFIFO:
200 case KEPLER_CHANNEL_GPFIFO_A:
63f8c9b7 201 case KEPLER_CHANNEL_GPFIFO_B:
a1020afe 202 case MAXWELL_CHANNEL_GPFIFO_A:
967e7bde
BS
203 ret = nvc0_fence_create(drm);
204 break;
205 default:
206 break;
207 }
208 }
209
41a63406 210 nvif_object_sclass_put(&sclass);
ebb945a9
BS
211 if (ret) {
212 NV_ERROR(drm, "failed to initialise sync subsystem, %d\n", ret);
213 nouveau_accel_fini(drm);
214 return;
215 }
216
967e7bde 217 if (device->info.family >= NV_DEVICE_INFO_V0_KEPLER) {
fcf3f91c 218 ret = nouveau_channel_new(drm, &drm->device,
1f5ff7f5
BS
219 NVA06F_V0_ENGINE_CE0 |
220 NVA06F_V0_ENGINE_CE1,
bbf8906b 221 0, &drm->cechan);
49981046
BS
222 if (ret)
223 NV_ERROR(drm, "failed to create ce channel, %d\n", ret);
224
1f5ff7f5 225 arg0 = NVA06F_V0_ENGINE_GR;
49469800 226 arg1 = 1;
00fc6f6f 227 } else
967e7bde
BS
228 if (device->info.chipset >= 0xa3 &&
229 device->info.chipset != 0xaa &&
230 device->info.chipset != 0xac) {
fcf3f91c 231 ret = nouveau_channel_new(drm, &drm->device,
0ad72863 232 NvDmaFB, NvDmaTT, &drm->cechan);
00fc6f6f
BS
233 if (ret)
234 NV_ERROR(drm, "failed to create ce channel, %d\n", ret);
235
236 arg0 = NvDmaFB;
237 arg1 = NvDmaTT;
49981046
BS
238 } else {
239 arg0 = NvDmaFB;
240 arg1 = NvDmaTT;
241 }
242
fcf3f91c 243 ret = nouveau_channel_new(drm, &drm->device, arg0, arg1, &drm->channel);
ebb945a9
BS
244 if (ret) {
245 NV_ERROR(drm, "failed to create kernel channel, %d\n", ret);
246 nouveau_accel_fini(drm);
247 return;
248 }
249
a01ca78c 250 ret = nvif_object_init(&drm->channel->user, NVDRM_NVSW,
0ad72863 251 nouveau_abi16_swclass(drm), NULL, 0, &drm->nvsw);
69a6146d 252 if (ret == 0) {
69a6146d
BS
253 ret = RING_SPACE(drm->channel, 2);
254 if (ret == 0) {
967e7bde 255 if (device->info.family < NV_DEVICE_INFO_V0_FERMI) {
69a6146d
BS
256 BEGIN_NV04(drm->channel, NvSubSw, 0, 1);
257 OUT_RING (drm->channel, NVDRM_NVSW);
258 } else
967e7bde 259 if (device->info.family < NV_DEVICE_INFO_V0_KEPLER) {
69a6146d
BS
260 BEGIN_NVC0(drm->channel, FermiSw, 0, 1);
261 OUT_RING (drm->channel, 0x001f0000);
262 }
263 }
898a2b32
BS
264
265 ret = nvif_notify_init(&drm->nvsw, nouveau_flip_complete,
538b269b
BS
266 false, NV04_NVSW_NTFY_UEVENT,
267 NULL, 0, 0, &drm->flip);
898a2b32
BS
268 if (ret == 0)
269 ret = nvif_notify_get(&drm->flip);
270 if (ret) {
271 nouveau_accel_fini(drm);
272 return;
273 }
69a6146d
BS
274 }
275
276 if (ret) {
277 NV_ERROR(drm, "failed to allocate software object, %d\n", ret);
278 nouveau_accel_fini(drm);
279 return;
280 }
281
967e7bde 282 if (device->info.family < NV_DEVICE_INFO_V0_FERMI) {
f027f491
BS
283 ret = nvkm_gpuobj_new(nvxx_device(&drm->device), 32, 0, false,
284 NULL, &drm->notify);
ebb945a9
BS
285 if (ret) {
286 NV_ERROR(drm, "failed to allocate notifier, %d\n", ret);
287 nouveau_accel_fini(drm);
288 return;
289 }
290
a01ca78c 291 ret = nvif_object_init(&drm->channel->user, NvNotify0,
4acfd707
BS
292 NV_DMA_IN_MEMORY,
293 &(struct nv_dma_v0) {
294 .target = NV_DMA_V0_TARGET_VRAM,
295 .access = NV_DMA_V0_ACCESS_RDWR,
ebb945a9
BS
296 .start = drm->notify->addr,
297 .limit = drm->notify->addr + 31
4acfd707 298 }, sizeof(struct nv_dma_v0),
0ad72863 299 &drm->ntfy);
ebb945a9
BS
300 if (ret) {
301 nouveau_accel_fini(drm);
302 return;
303 }
304 }
305
306
49981046 307 nouveau_bo_move_init(drm);
ebb945a9
BS
308}
309
56550d94
GKH
310static int nouveau_drm_probe(struct pci_dev *pdev,
311 const struct pci_device_id *pent)
94580299 312{
be83cd4e 313 struct nvkm_device *device;
ebb945a9
BS
314 struct apertures_struct *aper;
315 bool boot = false;
94580299
BS
316 int ret;
317
98b3a340
LW
318 /*
319 * apple-gmux is needed on dual GPU MacBook Pro
320 * to probe the panel if we're the inactive GPU.
321 */
322 if (IS_ENABLED(CONFIG_VGA_ARB) && IS_ENABLED(CONFIG_VGA_SWITCHEROO) &&
323 apple_gmux_present() && pdev != vga_default_device() &&
324 !vga_switcheroo_handler_flags())
325 return -EPROBE_DEFER;
326
ebb945a9
BS
327 /* remove conflicting drivers (vesafb, efifb etc) */
328 aper = alloc_apertures(3);
329 if (!aper)
330 return -ENOMEM;
331
332 aper->ranges[0].base = pci_resource_start(pdev, 1);
333 aper->ranges[0].size = pci_resource_len(pdev, 1);
334 aper->count = 1;
335
336 if (pci_resource_len(pdev, 2)) {
337 aper->ranges[aper->count].base = pci_resource_start(pdev, 2);
338 aper->ranges[aper->count].size = pci_resource_len(pdev, 2);
339 aper->count++;
340 }
341
342 if (pci_resource_len(pdev, 3)) {
343 aper->ranges[aper->count].base = pci_resource_start(pdev, 3);
344 aper->ranges[aper->count].size = pci_resource_len(pdev, 3);
345 aper->count++;
346 }
347
348#ifdef CONFIG_X86
349 boot = pdev->resource[PCI_ROM_RESOURCE].flags & IORESOURCE_ROM_SHADOW;
350#endif
771fa0e4
BS
351 if (nouveau_modeset != 2)
352 remove_conflicting_framebuffers(aper, "nouveaufb", boot);
83ef7777 353 kfree(aper);
ebb945a9 354
7974dd1b
BS
355 ret = nvkm_device_pci_new(pdev, nouveau_config, nouveau_debug,
356 true, true, ~0ULL, &device);
94580299
BS
357 if (ret)
358 return ret;
359
360 pci_set_master(pdev);
361
915b4d11 362 ret = drm_get_pci_dev(pdev, pent, &driver_pci);
94580299 363 if (ret) {
e781dc8f 364 nvkm_device_del(&device);
94580299
BS
365 return ret;
366 }
367
368 return 0;
369}
370
5addcf0a
DA
371#define PCI_CLASS_MULTIMEDIA_HD_AUDIO 0x0403
372
373static void
46941b0f 374nouveau_get_hdmi_dev(struct nouveau_drm *drm)
5addcf0a 375{
46941b0f 376 struct pci_dev *pdev = drm->dev->pdev;
5addcf0a 377
420b9469 378 if (!pdev) {
f2a0adad 379 NV_DEBUG(drm, "not a PCI device; no HDMI\n");
420b9469
AC
380 drm->hdmi_device = NULL;
381 return;
382 }
383
5addcf0a
DA
384 /* subfunction one is a hdmi audio device? */
385 drm->hdmi_device = pci_get_bus_and_slot((unsigned int)pdev->bus->number,
386 PCI_DEVFN(PCI_SLOT(pdev->devfn), 1));
387
388 if (!drm->hdmi_device) {
46941b0f 389 NV_DEBUG(drm, "hdmi device not found %d %d %d\n", pdev->bus->number, PCI_SLOT(pdev->devfn), 1);
5addcf0a
DA
390 return;
391 }
392
393 if ((drm->hdmi_device->class >> 8) != PCI_CLASS_MULTIMEDIA_HD_AUDIO) {
46941b0f 394 NV_DEBUG(drm, "possible hdmi device not audio %d\n", drm->hdmi_device->class);
5addcf0a
DA
395 pci_dev_put(drm->hdmi_device);
396 drm->hdmi_device = NULL;
397 return;
398 }
399}
400
5b8a43ae 401static int
94580299
BS
402nouveau_drm_load(struct drm_device *dev, unsigned long flags)
403{
94580299
BS
404 struct nouveau_drm *drm;
405 int ret;
406
9ad97ede 407 ret = nouveau_cli_create(dev, "DRM", sizeof(*drm), (void **)&drm);
94580299
BS
408 if (ret)
409 return ret;
410
77145f1c
BS
411 dev->dev_private = drm;
412 drm->dev = dev;
989aa5b7 413 nvxx_client(&drm->client.base)->debug =
be83cd4e 414 nvkm_dbgopt(nouveau_debug, "DRM");
77145f1c 415
94580299 416 INIT_LIST_HEAD(&drm->clients);
ebb945a9 417 spin_lock_init(&drm->tile.lock);
94580299 418
46941b0f 419 nouveau_get_hdmi_dev(drm);
5addcf0a 420
fcf3f91c 421 ret = nvif_device_init(&drm->client.base.object, 0, NV_DEVICE,
586491e6 422 &(struct nv_device_v0) {
94580299 423 .device = ~0,
586491e6 424 }, sizeof(struct nv_device_v0),
0ad72863 425 &drm->device);
94580299
BS
426 if (ret)
427 goto fail_device;
428
7d3428cd
IM
429 dev->irq_enabled = true;
430
77145f1c
BS
431 /* workaround an odd issue on nvc1 by disabling the device's
432 * nosnoop capability. hopefully won't cause issues until a
433 * better fix is found - assuming there is one...
434 */
967e7bde 435 if (drm->device.info.chipset == 0xc1)
a01ca78c 436 nvif_mask(&drm->device.object, 0x00088080, 0x00000800, 0x00000000);
ebb945a9 437
77145f1c 438 nouveau_vga_init(drm);
cb75d97e 439
967e7bde 440 if (drm->device.info.family >= NV_DEVICE_INFO_V0_TESLA) {
be83cd4e 441 ret = nvkm_vm_new(nvxx_device(&drm->device), 0, (1ULL << 40),
1de68568 442 0x1000, NULL, &drm->client.vm);
ebb945a9
BS
443 if (ret)
444 goto fail_device;
3ee6f5b5 445
989aa5b7 446 nvxx_client(&drm->client.base)->vm = drm->client.vm;
ebb945a9
BS
447 }
448
449 ret = nouveau_ttm_init(drm);
94580299 450 if (ret)
77145f1c
BS
451 goto fail_ttm;
452
453 ret = nouveau_bios_init(dev);
454 if (ret)
455 goto fail_bios;
456
77145f1c 457 ret = nouveau_display_create(dev);
ebb945a9 458 if (ret)
77145f1c
BS
459 goto fail_dispctor;
460
461 if (dev->mode_config.num_crtc) {
462 ret = nouveau_display_init(dev);
463 if (ret)
464 goto fail_dispinit;
465 }
466
b126a200 467 nouveau_debugfs_init(drm);
b9ed919f 468 nouveau_hwmon_init(dev);
ebb945a9
BS
469 nouveau_accel_init(drm);
470 nouveau_fbcon_init(dev);
5addcf0a
DA
471
472 if (nouveau_runtime_pm != 0) {
473 pm_runtime_use_autosuspend(dev->dev);
474 pm_runtime_set_autosuspend_delay(dev->dev, 5000);
475 pm_runtime_set_active(dev->dev);
476 pm_runtime_allow(dev->dev);
477 pm_runtime_mark_last_busy(dev->dev);
478 pm_runtime_put(dev->dev);
479 }
94580299
BS
480 return 0;
481
77145f1c
BS
482fail_dispinit:
483 nouveau_display_destroy(dev);
484fail_dispctor:
77145f1c
BS
485 nouveau_bios_takedown(dev);
486fail_bios:
ebb945a9 487 nouveau_ttm_fini(drm);
77145f1c 488fail_ttm:
77145f1c 489 nouveau_vga_fini(drm);
94580299 490fail_device:
0ad72863 491 nvif_device_fini(&drm->device);
94580299
BS
492 nouveau_cli_destroy(&drm->client);
493 return ret;
494}
495
5b8a43ae 496static int
94580299
BS
497nouveau_drm_unload(struct drm_device *dev)
498{
77145f1c 499 struct nouveau_drm *drm = nouveau_drm(dev);
94580299 500
5addcf0a 501 pm_runtime_get_sync(dev->dev);
ebb945a9
BS
502 nouveau_fbcon_fini(dev);
503 nouveau_accel_fini(drm);
b9ed919f 504 nouveau_hwmon_fini(dev);
b126a200 505 nouveau_debugfs_fini(drm);
77145f1c 506
9430738d
BS
507 if (dev->mode_config.num_crtc)
508 nouveau_display_fini(dev);
77145f1c
BS
509 nouveau_display_destroy(dev);
510
77145f1c 511 nouveau_bios_takedown(dev);
94580299 512
ebb945a9 513 nouveau_ttm_fini(drm);
77145f1c 514 nouveau_vga_fini(drm);
cb75d97e 515
0ad72863 516 nvif_device_fini(&drm->device);
5addcf0a
DA
517 if (drm->hdmi_device)
518 pci_dev_put(drm->hdmi_device);
94580299
BS
519 nouveau_cli_destroy(&drm->client);
520 return 0;
521}
522
8ba9ff11
AC
523void
524nouveau_drm_device_remove(struct drm_device *dev)
94580299 525{
77145f1c 526 struct nouveau_drm *drm = nouveau_drm(dev);
be83cd4e 527 struct nvkm_client *client;
76ecea5b 528 struct nvkm_device *device;
77145f1c 529
7d3428cd 530 dev->irq_enabled = false;
989aa5b7 531 client = nvxx_client(&drm->client.base);
4e7e62d6 532 device = nvkm_device_find(client->device);
77145f1c
BS
533 drm_put_dev(dev);
534
e781dc8f 535 nvkm_device_del(&device);
94580299 536}
8ba9ff11
AC
537
538static void
539nouveau_drm_remove(struct pci_dev *pdev)
540{
541 struct drm_device *dev = pci_get_drvdata(pdev);
542
543 nouveau_drm_device_remove(dev);
544}
94580299 545
cd897837 546static int
05c63c2f 547nouveau_do_suspend(struct drm_device *dev, bool runtime)
94580299 548{
77145f1c 549 struct nouveau_drm *drm = nouveau_drm(dev);
94580299
BS
550 struct nouveau_cli *cli;
551 int ret;
552
6fbb702e
BS
553 if (dev->mode_config.num_crtc) {
554 NV_INFO(drm, "suspending console...\n");
555 nouveau_fbcon_set_suspend(dev, 1);
c52f4fa6 556 NV_INFO(drm, "suspending display...\n");
6fbb702e 557 ret = nouveau_display_suspend(dev, runtime);
9430738d
BS
558 if (ret)
559 return ret;
560 }
94580299 561
c52f4fa6 562 NV_INFO(drm, "evicting buffers...\n");
ebb945a9
BS
563 ttm_bo_evict_mm(&drm->ttm.bdev, TTM_PL_VRAM);
564
c52f4fa6 565 NV_INFO(drm, "waiting for kernel channels to go idle...\n");
81dff21b
BS
566 if (drm->cechan) {
567 ret = nouveau_channel_idle(drm->cechan);
568 if (ret)
f3980dc5 569 goto fail_display;
81dff21b
BS
570 }
571
572 if (drm->channel) {
573 ret = nouveau_channel_idle(drm->channel);
574 if (ret)
f3980dc5 575 goto fail_display;
81dff21b
BS
576 }
577
c52f4fa6 578 NV_INFO(drm, "suspending client object trees...\n");
ebb945a9 579 if (drm->fence && nouveau_fence(drm)->suspend) {
f3980dc5
IM
580 if (!nouveau_fence(drm)->suspend(drm)) {
581 ret = -ENOMEM;
582 goto fail_display;
583 }
ebb945a9
BS
584 }
585
94580299 586 list_for_each_entry(cli, &drm->clients, head) {
0ad72863 587 ret = nvif_client_suspend(&cli->base);
94580299
BS
588 if (ret)
589 goto fail_client;
590 }
591
c52f4fa6 592 NV_INFO(drm, "suspending kernel object tree...\n");
0ad72863 593 ret = nvif_client_suspend(&drm->client.base);
94580299
BS
594 if (ret)
595 goto fail_client;
596
94580299
BS
597 return 0;
598
599fail_client:
600 list_for_each_entry_continue_reverse(cli, &drm->clients, head) {
0ad72863 601 nvif_client_resume(&cli->base);
94580299
BS
602 }
603
f3980dc5
IM
604 if (drm->fence && nouveau_fence(drm)->resume)
605 nouveau_fence(drm)->resume(drm);
606
607fail_display:
9430738d 608 if (dev->mode_config.num_crtc) {
c52f4fa6 609 NV_INFO(drm, "resuming display...\n");
6fbb702e 610 nouveau_display_resume(dev, runtime);
9430738d 611 }
94580299
BS
612 return ret;
613}
614
cd897837 615static int
6fbb702e 616nouveau_do_resume(struct drm_device *dev, bool runtime)
2d8b9ccb
DA
617{
618 struct nouveau_drm *drm = nouveau_drm(dev);
619 struct nouveau_cli *cli;
620
c52f4fa6 621 NV_INFO(drm, "resuming kernel object tree...\n");
0ad72863 622 nvif_client_resume(&drm->client.base);
94580299 623
c52f4fa6 624 NV_INFO(drm, "resuming client object trees...\n");
81dff21b
BS
625 if (drm->fence && nouveau_fence(drm)->resume)
626 nouveau_fence(drm)->resume(drm);
627
94580299 628 list_for_each_entry(cli, &drm->clients, head) {
0ad72863 629 nvif_client_resume(&cli->base);
94580299 630 }
cb75d97e 631
77145f1c 632 nouveau_run_vbios_init(dev);
77145f1c 633
9430738d 634 if (dev->mode_config.num_crtc) {
c52f4fa6 635 NV_INFO(drm, "resuming display...\n");
6fbb702e
BS
636 nouveau_display_resume(dev, runtime);
637 NV_INFO(drm, "resuming console...\n");
638 nouveau_fbcon_set_suspend(dev, 0);
9430738d 639 }
5addcf0a 640
77145f1c 641 return 0;
94580299
BS
642}
643
7bb6d442
BS
644int
645nouveau_pmops_suspend(struct device *dev)
646{
647 struct pci_dev *pdev = to_pci_dev(dev);
648 struct drm_device *drm_dev = pci_get_drvdata(pdev);
649 int ret;
650
651 if (drm_dev->switch_power_state == DRM_SWITCH_POWER_OFF ||
652 drm_dev->switch_power_state == DRM_SWITCH_POWER_DYNAMIC_OFF)
653 return 0;
654
655 ret = nouveau_do_suspend(drm_dev, false);
656 if (ret)
657 return ret;
658
659 pci_save_state(pdev);
660 pci_disable_device(pdev);
7bb6d442 661 pci_set_power_state(pdev, PCI_D3hot);
c5fd936e 662 udelay(200);
7bb6d442
BS
663 return 0;
664}
665
666int
667nouveau_pmops_resume(struct device *dev)
2d8b9ccb
DA
668{
669 struct pci_dev *pdev = to_pci_dev(dev);
670 struct drm_device *drm_dev = pci_get_drvdata(pdev);
671 int ret;
672
5addcf0a
DA
673 if (drm_dev->switch_power_state == DRM_SWITCH_POWER_OFF ||
674 drm_dev->switch_power_state == DRM_SWITCH_POWER_DYNAMIC_OFF)
2d8b9ccb
DA
675 return 0;
676
677 pci_set_power_state(pdev, PCI_D0);
678 pci_restore_state(pdev);
679 ret = pci_enable_device(pdev);
680 if (ret)
681 return ret;
682 pci_set_master(pdev);
683
6fbb702e 684 return nouveau_do_resume(drm_dev, false);
2d8b9ccb
DA
685}
686
7bb6d442
BS
687static int
688nouveau_pmops_freeze(struct device *dev)
2d8b9ccb
DA
689{
690 struct pci_dev *pdev = to_pci_dev(dev);
691 struct drm_device *drm_dev = pci_get_drvdata(pdev);
6fbb702e 692 return nouveau_do_suspend(drm_dev, false);
2d8b9ccb
DA
693}
694
7bb6d442
BS
695static int
696nouveau_pmops_thaw(struct device *dev)
2d8b9ccb
DA
697{
698 struct pci_dev *pdev = to_pci_dev(dev);
699 struct drm_device *drm_dev = pci_get_drvdata(pdev);
6fbb702e 700 return nouveau_do_resume(drm_dev, false);
2d8b9ccb
DA
701}
702
7bb6d442
BS
703static int
704nouveau_pmops_runtime_suspend(struct device *dev)
705{
706 struct pci_dev *pdev = to_pci_dev(dev);
707 struct drm_device *drm_dev = pci_get_drvdata(pdev);
708 int ret;
709
710 if (nouveau_runtime_pm == 0) {
711 pm_runtime_forbid(dev);
712 return -EBUSY;
713 }
714
715 /* are we optimus enabled? */
716 if (nouveau_runtime_pm == -1 && !nouveau_is_optimus() && !nouveau_is_v1_dsm()) {
717 DRM_DEBUG_DRIVER("failing to power off - not optimus\n");
718 pm_runtime_forbid(dev);
719 return -EBUSY;
720 }
721
7bb6d442
BS
722 drm_kms_helper_poll_disable(drm_dev);
723 vga_switcheroo_set_dynamic_switch(pdev, VGA_SWITCHEROO_OFF);
724 nouveau_switcheroo_optimus_dsm();
725 ret = nouveau_do_suspend(drm_dev, true);
726 pci_save_state(pdev);
727 pci_disable_device(pdev);
8c863944 728 pci_ignore_hotplug(pdev);
7bb6d442
BS
729 pci_set_power_state(pdev, PCI_D3cold);
730 drm_dev->switch_power_state = DRM_SWITCH_POWER_DYNAMIC_OFF;
731 return ret;
732}
733
734static int
735nouveau_pmops_runtime_resume(struct device *dev)
736{
737 struct pci_dev *pdev = to_pci_dev(dev);
738 struct drm_device *drm_dev = pci_get_drvdata(pdev);
739 struct nvif_device *device = &nouveau_drm(drm_dev)->device;
740 int ret;
741
742 if (nouveau_runtime_pm == 0)
743 return -EINVAL;
744
745 pci_set_power_state(pdev, PCI_D0);
746 pci_restore_state(pdev);
747 ret = pci_enable_device(pdev);
748 if (ret)
749 return ret;
750 pci_set_master(pdev);
751
752 ret = nouveau_do_resume(drm_dev, true);
753 drm_kms_helper_poll_enable(drm_dev);
754 /* do magic */
a01ca78c 755 nvif_mask(&device->object, 0x088488, (1 << 25), (1 << 25));
7bb6d442
BS
756 vga_switcheroo_set_dynamic_switch(pdev, VGA_SWITCHEROO_ON);
757 drm_dev->switch_power_state = DRM_SWITCH_POWER_ON;
7bb6d442
BS
758 return ret;
759}
760
761static int
762nouveau_pmops_runtime_idle(struct device *dev)
763{
764 struct pci_dev *pdev = to_pci_dev(dev);
765 struct drm_device *drm_dev = pci_get_drvdata(pdev);
766 struct nouveau_drm *drm = nouveau_drm(drm_dev);
767 struct drm_crtc *crtc;
768
769 if (nouveau_runtime_pm == 0) {
770 pm_runtime_forbid(dev);
771 return -EBUSY;
772 }
773
774 /* are we optimus enabled? */
775 if (nouveau_runtime_pm == -1 && !nouveau_is_optimus() && !nouveau_is_v1_dsm()) {
776 DRM_DEBUG_DRIVER("failing to power off - not optimus\n");
777 pm_runtime_forbid(dev);
778 return -EBUSY;
779 }
780
781 /* if we have a hdmi audio device - make sure it has a driver loaded */
782 if (drm->hdmi_device) {
783 if (!drm->hdmi_device->driver) {
784 DRM_DEBUG_DRIVER("failing to power off - no HDMI audio driver loaded\n");
785 pm_runtime_mark_last_busy(dev);
786 return -EBUSY;
787 }
788 }
789
790 list_for_each_entry(crtc, &drm->dev->mode_config.crtc_list, head) {
791 if (crtc->enabled) {
792 DRM_DEBUG_DRIVER("failing to power off - crtc active\n");
793 return -EBUSY;
794 }
795 }
796 pm_runtime_mark_last_busy(dev);
797 pm_runtime_autosuspend(dev);
798 /* we don't want the main rpm_idle to call suspend - we want to autosuspend */
799 return 1;
800}
2d8b9ccb 801
5b8a43ae 802static int
ebb945a9
BS
803nouveau_drm_open(struct drm_device *dev, struct drm_file *fpriv)
804{
ebb945a9
BS
805 struct nouveau_drm *drm = nouveau_drm(dev);
806 struct nouveau_cli *cli;
a2896ced 807 char name[32], tmpname[TASK_COMM_LEN];
ebb945a9
BS
808 int ret;
809
5addcf0a
DA
810 /* need to bring up power immediately if opening device */
811 ret = pm_runtime_get_sync(dev->dev);
b6c4285a 812 if (ret < 0 && ret != -EACCES)
5addcf0a
DA
813 return ret;
814
a2896ced
MS
815 get_task_comm(tmpname, current);
816 snprintf(name, sizeof(name), "%s[%d]", tmpname, pid_nr(fpriv->pid));
fa6df8c1 817
9ad97ede 818 ret = nouveau_cli_create(dev, name, sizeof(*cli), (void **)&cli);
420b9469 819
ebb945a9 820 if (ret)
5addcf0a 821 goto out_suspend;
ebb945a9 822
0ad72863
BS
823 cli->base.super = false;
824
967e7bde 825 if (drm->device.info.family >= NV_DEVICE_INFO_V0_TESLA) {
be83cd4e 826 ret = nvkm_vm_new(nvxx_device(&drm->device), 0, (1ULL << 40),
1de68568 827 0x1000, NULL, &cli->vm);
ebb945a9
BS
828 if (ret) {
829 nouveau_cli_destroy(cli);
5addcf0a 830 goto out_suspend;
ebb945a9 831 }
3ee6f5b5 832
989aa5b7 833 nvxx_client(&cli->base)->vm = cli->vm;
ebb945a9
BS
834 }
835
836 fpriv->driver_priv = cli;
837
838 mutex_lock(&drm->client.mutex);
839 list_add(&cli->head, &drm->clients);
840 mutex_unlock(&drm->client.mutex);
5addcf0a
DA
841
842out_suspend:
843 pm_runtime_mark_last_busy(dev->dev);
844 pm_runtime_put_autosuspend(dev->dev);
845
846 return ret;
ebb945a9
BS
847}
848
5b8a43ae 849static void
ebb945a9
BS
850nouveau_drm_preclose(struct drm_device *dev, struct drm_file *fpriv)
851{
852 struct nouveau_cli *cli = nouveau_cli(fpriv);
853 struct nouveau_drm *drm = nouveau_drm(dev);
854
5addcf0a
DA
855 pm_runtime_get_sync(dev->dev);
856
ac8c7930 857 mutex_lock(&cli->mutex);
ebb945a9
BS
858 if (cli->abi16)
859 nouveau_abi16_fini(cli->abi16);
ac8c7930 860 mutex_unlock(&cli->mutex);
ebb945a9
BS
861
862 mutex_lock(&drm->client.mutex);
863 list_del(&cli->head);
864 mutex_unlock(&drm->client.mutex);
5addcf0a 865
ebb945a9
BS
866}
867
5b8a43ae 868static void
ebb945a9
BS
869nouveau_drm_postclose(struct drm_device *dev, struct drm_file *fpriv)
870{
871 struct nouveau_cli *cli = nouveau_cli(fpriv);
872 nouveau_cli_destroy(cli);
5addcf0a
DA
873 pm_runtime_mark_last_busy(dev->dev);
874 pm_runtime_put_autosuspend(dev->dev);
ebb945a9
BS
875}
876
baa70943 877static const struct drm_ioctl_desc
77145f1c 878nouveau_ioctls[] = {
f8c47144
DV
879 DRM_IOCTL_DEF_DRV(NOUVEAU_GETPARAM, nouveau_abi16_ioctl_getparam, DRM_AUTH|DRM_RENDER_ALLOW),
880 DRM_IOCTL_DEF_DRV(NOUVEAU_SETPARAM, nouveau_abi16_ioctl_setparam, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
881 DRM_IOCTL_DEF_DRV(NOUVEAU_CHANNEL_ALLOC, nouveau_abi16_ioctl_channel_alloc, DRM_AUTH|DRM_RENDER_ALLOW),
882 DRM_IOCTL_DEF_DRV(NOUVEAU_CHANNEL_FREE, nouveau_abi16_ioctl_channel_free, DRM_AUTH|DRM_RENDER_ALLOW),
883 DRM_IOCTL_DEF_DRV(NOUVEAU_GROBJ_ALLOC, nouveau_abi16_ioctl_grobj_alloc, DRM_AUTH|DRM_RENDER_ALLOW),
884 DRM_IOCTL_DEF_DRV(NOUVEAU_NOTIFIEROBJ_ALLOC, nouveau_abi16_ioctl_notifierobj_alloc, DRM_AUTH|DRM_RENDER_ALLOW),
885 DRM_IOCTL_DEF_DRV(NOUVEAU_GPUOBJ_FREE, nouveau_abi16_ioctl_gpuobj_free, DRM_AUTH|DRM_RENDER_ALLOW),
886 DRM_IOCTL_DEF_DRV(NOUVEAU_GEM_NEW, nouveau_gem_ioctl_new, DRM_AUTH|DRM_RENDER_ALLOW),
887 DRM_IOCTL_DEF_DRV(NOUVEAU_GEM_PUSHBUF, nouveau_gem_ioctl_pushbuf, DRM_AUTH|DRM_RENDER_ALLOW),
888 DRM_IOCTL_DEF_DRV(NOUVEAU_GEM_CPU_PREP, nouveau_gem_ioctl_cpu_prep, DRM_AUTH|DRM_RENDER_ALLOW),
889 DRM_IOCTL_DEF_DRV(NOUVEAU_GEM_CPU_FINI, nouveau_gem_ioctl_cpu_fini, DRM_AUTH|DRM_RENDER_ALLOW),
890 DRM_IOCTL_DEF_DRV(NOUVEAU_GEM_INFO, nouveau_gem_ioctl_info, DRM_AUTH|DRM_RENDER_ALLOW),
77145f1c
BS
891};
892
27111a23
BS
893long
894nouveau_drm_ioctl(struct file *file, unsigned int cmd, unsigned long arg)
5addcf0a 895{
27111a23
BS
896 struct drm_file *filp = file->private_data;
897 struct drm_device *dev = filp->minor->dev;
5addcf0a 898 long ret;
5addcf0a
DA
899
900 ret = pm_runtime_get_sync(dev->dev);
b6c4285a 901 if (ret < 0 && ret != -EACCES)
5addcf0a
DA
902 return ret;
903
27111a23
BS
904 switch (_IOC_NR(cmd) - DRM_COMMAND_BASE) {
905 case DRM_NOUVEAU_NVIF:
906 ret = usif_ioctl(filp, (void __user *)arg, _IOC_SIZE(cmd));
907 break;
908 default:
909 ret = drm_ioctl(file, cmd, arg);
910 break;
911 }
5addcf0a
DA
912
913 pm_runtime_mark_last_busy(dev->dev);
914 pm_runtime_put_autosuspend(dev->dev);
915 return ret;
916}
27111a23 917
77145f1c
BS
918static const struct file_operations
919nouveau_driver_fops = {
920 .owner = THIS_MODULE,
921 .open = drm_open,
922 .release = drm_release,
5addcf0a 923 .unlocked_ioctl = nouveau_drm_ioctl,
77145f1c
BS
924 .mmap = nouveau_ttm_mmap,
925 .poll = drm_poll,
77145f1c
BS
926 .read = drm_read,
927#if defined(CONFIG_COMPAT)
928 .compat_ioctl = nouveau_compat_ioctl,
929#endif
930 .llseek = noop_llseek,
931};
932
933static struct drm_driver
915b4d11 934driver_stub = {
77145f1c 935 .driver_features =
0e975980
PA
936 DRIVER_GEM | DRIVER_MODESET | DRIVER_PRIME | DRIVER_RENDER |
937 DRIVER_KMS_LEGACY_CONTEXT,
77145f1c
BS
938
939 .load = nouveau_drm_load,
940 .unload = nouveau_drm_unload,
941 .open = nouveau_drm_open,
942 .preclose = nouveau_drm_preclose,
943 .postclose = nouveau_drm_postclose,
944 .lastclose = nouveau_vga_lastclose,
945
33b903e8 946#if defined(CONFIG_DEBUG_FS)
56c101af
KH
947 .debugfs_init = nouveau_drm_debugfs_init,
948 .debugfs_cleanup = nouveau_drm_debugfs_cleanup,
33b903e8
MS
949#endif
950
b44f8408 951 .get_vblank_counter = drm_vblank_no_hw_counter,
51cb4b39
BS
952 .enable_vblank = nouveau_display_vblank_enable,
953 .disable_vblank = nouveau_display_vblank_disable,
d83ef853
BS
954 .get_scanout_position = nouveau_display_scanoutpos,
955 .get_vblank_timestamp = nouveau_display_vblstamp,
77145f1c
BS
956
957 .ioctls = nouveau_ioctls,
baa70943 958 .num_ioctls = ARRAY_SIZE(nouveau_ioctls),
77145f1c
BS
959 .fops = &nouveau_driver_fops,
960
961 .prime_handle_to_fd = drm_gem_prime_handle_to_fd,
962 .prime_fd_to_handle = drm_gem_prime_fd_to_handle,
ab9ccb96
AP
963 .gem_prime_export = drm_gem_prime_export,
964 .gem_prime_import = drm_gem_prime_import,
965 .gem_prime_pin = nouveau_gem_prime_pin,
3aac4502 966 .gem_prime_res_obj = nouveau_gem_prime_res_obj,
1af7c7dd 967 .gem_prime_unpin = nouveau_gem_prime_unpin,
ab9ccb96
AP
968 .gem_prime_get_sg_table = nouveau_gem_prime_get_sg_table,
969 .gem_prime_import_sg_table = nouveau_gem_prime_import_sg_table,
970 .gem_prime_vmap = nouveau_gem_prime_vmap,
971 .gem_prime_vunmap = nouveau_gem_prime_vunmap,
77145f1c 972
77145f1c
BS
973 .gem_free_object = nouveau_gem_object_del,
974 .gem_open_object = nouveau_gem_object_open,
975 .gem_close_object = nouveau_gem_object_close,
976
977 .dumb_create = nouveau_display_dumb_create,
978 .dumb_map_offset = nouveau_display_dumb_map_offset,
43387b37 979 .dumb_destroy = drm_gem_dumb_destroy,
77145f1c
BS
980
981 .name = DRIVER_NAME,
982 .desc = DRIVER_DESC,
983#ifdef GIT_REVISION
984 .date = GIT_REVISION,
985#else
986 .date = DRIVER_DATE,
987#endif
988 .major = DRIVER_MAJOR,
989 .minor = DRIVER_MINOR,
990 .patchlevel = DRIVER_PATCHLEVEL,
991};
992
94580299
BS
993static struct pci_device_id
994nouveau_drm_pci_table[] = {
995 {
996 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID),
997 .class = PCI_BASE_CLASS_DISPLAY << 16,
998 .class_mask = 0xff << 16,
999 },
1000 {
1001 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA_SGS, PCI_ANY_ID),
1002 .class = PCI_BASE_CLASS_DISPLAY << 16,
1003 .class_mask = 0xff << 16,
1004 },
1005 {}
1006};
1007
703fa264
PM
1008static void nouveau_display_options(void)
1009{
1010 DRM_DEBUG_DRIVER("Loading Nouveau with parameters:\n");
1011
1012 DRM_DEBUG_DRIVER("... tv_disable : %d\n", nouveau_tv_disable);
1013 DRM_DEBUG_DRIVER("... ignorelid : %d\n", nouveau_ignorelid);
1014 DRM_DEBUG_DRIVER("... duallink : %d\n", nouveau_duallink);
1015 DRM_DEBUG_DRIVER("... nofbaccel : %d\n", nouveau_nofbaccel);
1016 DRM_DEBUG_DRIVER("... config : %s\n", nouveau_config);
1017 DRM_DEBUG_DRIVER("... debug : %s\n", nouveau_debug);
1018 DRM_DEBUG_DRIVER("... noaccel : %d\n", nouveau_noaccel);
1019 DRM_DEBUG_DRIVER("... modeset : %d\n", nouveau_modeset);
1020 DRM_DEBUG_DRIVER("... runpm : %d\n", nouveau_runtime_pm);
1021 DRM_DEBUG_DRIVER("... vram_pushbuf : %d\n", nouveau_vram_pushbuf);
703fa264
PM
1022}
1023
2d8b9ccb
DA
1024static const struct dev_pm_ops nouveau_pm_ops = {
1025 .suspend = nouveau_pmops_suspend,
1026 .resume = nouveau_pmops_resume,
1027 .freeze = nouveau_pmops_freeze,
1028 .thaw = nouveau_pmops_thaw,
1029 .poweroff = nouveau_pmops_freeze,
1030 .restore = nouveau_pmops_resume,
5addcf0a
DA
1031 .runtime_suspend = nouveau_pmops_runtime_suspend,
1032 .runtime_resume = nouveau_pmops_runtime_resume,
1033 .runtime_idle = nouveau_pmops_runtime_idle,
2d8b9ccb
DA
1034};
1035
94580299
BS
1036static struct pci_driver
1037nouveau_drm_pci_driver = {
1038 .name = "nouveau",
1039 .id_table = nouveau_drm_pci_table,
1040 .probe = nouveau_drm_probe,
1041 .remove = nouveau_drm_remove,
2d8b9ccb 1042 .driver.pm = &nouveau_pm_ops,
94580299
BS
1043};
1044
8ba9ff11 1045struct drm_device *
e396ecd1
AC
1046nouveau_platform_device_create(const struct nvkm_device_tegra_func *func,
1047 struct platform_device *pdev,
47b2505e 1048 struct nvkm_device **pdevice)
420b9469 1049{
8ba9ff11
AC
1050 struct drm_device *drm;
1051 int err;
420b9469 1052
e396ecd1 1053 err = nvkm_device_tegra_new(func, pdev, nouveau_config, nouveau_debug,
7974dd1b 1054 true, true, ~0ULL, pdevice);
8ba9ff11 1055 if (err)
e781dc8f 1056 goto err_free;
8ba9ff11 1057
915b4d11 1058 drm = drm_dev_alloc(&driver_platform, &pdev->dev);
8ba9ff11
AC
1059 if (!drm) {
1060 err = -ENOMEM;
1061 goto err_free;
420b9469
AC
1062 }
1063
8ba9ff11
AC
1064 drm->platformdev = pdev;
1065 platform_set_drvdata(pdev, drm);
1066
1067 return drm;
1068
1069err_free:
e781dc8f 1070 nvkm_device_del(pdevice);
8ba9ff11
AC
1071
1072 return ERR_PTR(err);
420b9469
AC
1073}
1074
94580299
BS
1075static int __init
1076nouveau_drm_init(void)
1077{
915b4d11
DH
1078 driver_pci = driver_stub;
1079 driver_pci.set_busid = drm_pci_set_busid;
1080 driver_platform = driver_stub;
1081 driver_platform.set_busid = drm_platform_set_busid;
1082
703fa264
PM
1083 nouveau_display_options();
1084
77145f1c 1085 if (nouveau_modeset == -1) {
77145f1c
BS
1086 if (vgacon_text_force())
1087 nouveau_modeset = 0;
77145f1c
BS
1088 }
1089
1090 if (!nouveau_modeset)
1091 return 0;
1092
055a65d5
AC
1093#ifdef CONFIG_NOUVEAU_PLATFORM_DRIVER
1094 platform_driver_register(&nouveau_platform_driver);
1095#endif
1096
77145f1c 1097 nouveau_register_dsm_handler();
915b4d11 1098 return drm_pci_init(&driver_pci, &nouveau_drm_pci_driver);
94580299
BS
1099}
1100
1101static void __exit
1102nouveau_drm_exit(void)
1103{
77145f1c
BS
1104 if (!nouveau_modeset)
1105 return;
1106
915b4d11 1107 drm_pci_exit(&driver_pci, &nouveau_drm_pci_driver);
77145f1c 1108 nouveau_unregister_dsm_handler();
055a65d5
AC
1109
1110#ifdef CONFIG_NOUVEAU_PLATFORM_DRIVER
1111 platform_driver_unregister(&nouveau_platform_driver);
1112#endif
94580299
BS
1113}
1114
1115module_init(nouveau_drm_init);
1116module_exit(nouveau_drm_exit);
1117
1118MODULE_DEVICE_TABLE(pci, nouveau_drm_pci_table);
77145f1c
BS
1119MODULE_AUTHOR(DRIVER_AUTHOR);
1120MODULE_DESCRIPTION(DRIVER_DESC);
94580299 1121MODULE_LICENSE("GPL and additional rights");