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94580299 BS |
1 | /* |
2 | * Copyright 2012 Red Hat Inc. | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice shall be included in | |
12 | * all copies or substantial portions of the Software. | |
13 | * | |
14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
17 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
18 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
19 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
20 | * OTHER DEALINGS IN THE SOFTWARE. | |
21 | * | |
22 | * Authors: Ben Skeggs | |
23 | */ | |
24 | ||
77145f1c | 25 | #include <linux/console.h> |
94580299 BS |
26 | #include <linux/module.h> |
27 | #include <linux/pci.h> | |
5addcf0a DA |
28 | #include <linux/pm_runtime.h> |
29 | #include <linux/vga_switcheroo.h> | |
30 | #include "drmP.h" | |
31 | #include "drm_crtc_helper.h" | |
94580299 BS |
32 | #include <core/device.h> |
33 | #include <core/client.h> | |
ebb945a9 | 34 | #include <core/gpuobj.h> |
94580299 BS |
35 | #include <core/class.h> |
36 | ||
dded35de | 37 | #include <engine/device.h> |
1d7c71a3 | 38 | #include <engine/disp.h> |
9fe72f9e | 39 | #include <engine/fifo.h> |
69a6146d | 40 | #include <engine/software.h> |
1d7c71a3 | 41 | |
dded35de BS |
42 | #include <subdev/vm.h> |
43 | ||
94580299 | 44 | #include "nouveau_drm.h" |
ebb945a9 | 45 | #include "nouveau_dma.h" |
77145f1c BS |
46 | #include "nouveau_ttm.h" |
47 | #include "nouveau_gem.h" | |
cb75d97e | 48 | #include "nouveau_agp.h" |
77145f1c | 49 | #include "nouveau_vga.h" |
26fdd78c | 50 | #include "nouveau_sysfs.h" |
b9ed919f | 51 | #include "nouveau_hwmon.h" |
77145f1c BS |
52 | #include "nouveau_acpi.h" |
53 | #include "nouveau_bios.h" | |
54 | #include "nouveau_ioctl.h" | |
ebb945a9 BS |
55 | #include "nouveau_abi16.h" |
56 | #include "nouveau_fbcon.h" | |
57 | #include "nouveau_fence.h" | |
33b903e8 | 58 | #include "nouveau_debugfs.h" |
ebb945a9 | 59 | |
94580299 BS |
60 | MODULE_PARM_DESC(config, "option string to pass to driver core"); |
61 | static char *nouveau_config; | |
62 | module_param_named(config, nouveau_config, charp, 0400); | |
63 | ||
64 | MODULE_PARM_DESC(debug, "debug string to pass to driver core"); | |
65 | static char *nouveau_debug; | |
66 | module_param_named(debug, nouveau_debug, charp, 0400); | |
67 | ||
ebb945a9 BS |
68 | MODULE_PARM_DESC(noaccel, "disable kernel/abi16 acceleration"); |
69 | static int nouveau_noaccel = 0; | |
70 | module_param_named(noaccel, nouveau_noaccel, int, 0400); | |
71 | ||
9430738d BS |
72 | MODULE_PARM_DESC(modeset, "enable driver (default: auto, " |
73 | "0 = disabled, 1 = enabled, 2 = headless)"); | |
74 | int nouveau_modeset = -1; | |
77145f1c BS |
75 | module_param_named(modeset, nouveau_modeset, int, 0400); |
76 | ||
5addcf0a DA |
77 | MODULE_PARM_DESC(runpm, "disable (0), force enable (1), optimus only default (-1)"); |
78 | int nouveau_runtime_pm = -1; | |
79 | module_param_named(runpm, nouveau_runtime_pm, int, 0400); | |
80 | ||
77145f1c BS |
81 | static struct drm_driver driver; |
82 | ||
94580299 BS |
83 | static u64 |
84 | nouveau_name(struct pci_dev *pdev) | |
85 | { | |
86 | u64 name = (u64)pci_domain_nr(pdev->bus) << 32; | |
87 | name |= pdev->bus->number << 16; | |
88 | name |= PCI_SLOT(pdev->devfn) << 8; | |
89 | return name | PCI_FUNC(pdev->devfn); | |
90 | } | |
91 | ||
92 | static int | |
fa6df8c1 BS |
93 | nouveau_cli_create(struct pci_dev *pdev, const char *name, |
94 | int size, void **pcli) | |
94580299 BS |
95 | { |
96 | struct nouveau_cli *cli; | |
97 | int ret; | |
98 | ||
dd5700ea | 99 | *pcli = NULL; |
94580299 BS |
100 | ret = nouveau_client_create_(name, nouveau_name(pdev), nouveau_config, |
101 | nouveau_debug, size, pcli); | |
102 | cli = *pcli; | |
dd5700ea MS |
103 | if (ret) { |
104 | if (cli) | |
105 | nouveau_client_destroy(&cli->base); | |
106 | *pcli = NULL; | |
94580299 | 107 | return ret; |
dd5700ea | 108 | } |
94580299 BS |
109 | |
110 | mutex_init(&cli->mutex); | |
111 | return 0; | |
112 | } | |
113 | ||
114 | static void | |
115 | nouveau_cli_destroy(struct nouveau_cli *cli) | |
116 | { | |
117 | struct nouveau_object *client = nv_object(cli); | |
ebb945a9 | 118 | nouveau_vm_ref(NULL, &cli->base.vm, NULL); |
94580299 BS |
119 | nouveau_client_fini(&cli->base, false); |
120 | atomic_set(&client->refcount, 1); | |
121 | nouveau_object_ref(NULL, &client); | |
122 | } | |
123 | ||
ebb945a9 BS |
124 | static void |
125 | nouveau_accel_fini(struct nouveau_drm *drm) | |
126 | { | |
127 | nouveau_gpuobj_ref(NULL, &drm->notify); | |
128 | nouveau_channel_del(&drm->channel); | |
49981046 | 129 | nouveau_channel_del(&drm->cechan); |
ebb945a9 BS |
130 | if (drm->fence) |
131 | nouveau_fence(drm)->dtor(drm); | |
132 | } | |
133 | ||
134 | static void | |
135 | nouveau_accel_init(struct nouveau_drm *drm) | |
136 | { | |
137 | struct nouveau_device *device = nv_device(drm->device); | |
138 | struct nouveau_object *object; | |
49981046 | 139 | u32 arg0, arg1; |
ebb945a9 BS |
140 | int ret; |
141 | ||
9fe72f9e | 142 | if (nouveau_noaccel || !nouveau_fifo(device) /*XXX*/) |
ebb945a9 BS |
143 | return; |
144 | ||
145 | /* initialise synchronisation routines */ | |
146 | if (device->card_type < NV_10) ret = nv04_fence_create(drm); | |
8aa816b0 IM |
147 | else if (device->card_type < NV_11 || |
148 | device->chipset < 0x17) ret = nv10_fence_create(drm); | |
60e5cb79 | 149 | else if (device->card_type < NV_50) ret = nv17_fence_create(drm); |
ace5a9b8 | 150 | else if (device->chipset < 0x84) ret = nv50_fence_create(drm); |
ebb945a9 BS |
151 | else if (device->card_type < NV_C0) ret = nv84_fence_create(drm); |
152 | else ret = nvc0_fence_create(drm); | |
153 | if (ret) { | |
154 | NV_ERROR(drm, "failed to initialise sync subsystem, %d\n", ret); | |
155 | nouveau_accel_fini(drm); | |
156 | return; | |
157 | } | |
158 | ||
49981046 BS |
159 | if (device->card_type >= NV_E0) { |
160 | ret = nouveau_channel_new(drm, &drm->client, NVDRM_DEVICE, | |
161 | NVDRM_CHAN + 1, | |
162 | NVE0_CHANNEL_IND_ENGINE_CE0 | | |
163 | NVE0_CHANNEL_IND_ENGINE_CE1, 0, | |
164 | &drm->cechan); | |
165 | if (ret) | |
166 | NV_ERROR(drm, "failed to create ce channel, %d\n", ret); | |
167 | ||
168 | arg0 = NVE0_CHANNEL_IND_ENGINE_GR; | |
49469800 | 169 | arg1 = 1; |
00fc6f6f BS |
170 | } else |
171 | if (device->chipset >= 0xa3 && | |
172 | device->chipset != 0xaa && | |
173 | device->chipset != 0xac) { | |
174 | ret = nouveau_channel_new(drm, &drm->client, NVDRM_DEVICE, | |
175 | NVDRM_CHAN + 1, NvDmaFB, NvDmaTT, | |
176 | &drm->cechan); | |
177 | if (ret) | |
178 | NV_ERROR(drm, "failed to create ce channel, %d\n", ret); | |
179 | ||
180 | arg0 = NvDmaFB; | |
181 | arg1 = NvDmaTT; | |
49981046 BS |
182 | } else { |
183 | arg0 = NvDmaFB; | |
184 | arg1 = NvDmaTT; | |
185 | } | |
186 | ||
ebb945a9 | 187 | ret = nouveau_channel_new(drm, &drm->client, NVDRM_DEVICE, NVDRM_CHAN, |
49981046 | 188 | arg0, arg1, &drm->channel); |
ebb945a9 BS |
189 | if (ret) { |
190 | NV_ERROR(drm, "failed to create kernel channel, %d\n", ret); | |
191 | nouveau_accel_fini(drm); | |
192 | return; | |
193 | } | |
194 | ||
69a6146d BS |
195 | ret = nouveau_object_new(nv_object(drm), NVDRM_CHAN, NVDRM_NVSW, |
196 | nouveau_abi16_swclass(drm), NULL, 0, &object); | |
197 | if (ret == 0) { | |
198 | struct nouveau_software_chan *swch = (void *)object->parent; | |
199 | ret = RING_SPACE(drm->channel, 2); | |
200 | if (ret == 0) { | |
201 | if (device->card_type < NV_C0) { | |
202 | BEGIN_NV04(drm->channel, NvSubSw, 0, 1); | |
203 | OUT_RING (drm->channel, NVDRM_NVSW); | |
204 | } else | |
205 | if (device->card_type < NV_E0) { | |
206 | BEGIN_NVC0(drm->channel, FermiSw, 0, 1); | |
207 | OUT_RING (drm->channel, 0x001f0000); | |
208 | } | |
209 | } | |
210 | swch = (void *)object->parent; | |
211 | swch->flip = nouveau_flip_complete; | |
212 | swch->flip_data = drm->channel; | |
213 | } | |
214 | ||
215 | if (ret) { | |
216 | NV_ERROR(drm, "failed to allocate software object, %d\n", ret); | |
217 | nouveau_accel_fini(drm); | |
218 | return; | |
219 | } | |
220 | ||
ebb945a9 BS |
221 | if (device->card_type < NV_C0) { |
222 | ret = nouveau_gpuobj_new(drm->device, NULL, 32, 0, 0, | |
223 | &drm->notify); | |
224 | if (ret) { | |
225 | NV_ERROR(drm, "failed to allocate notifier, %d\n", ret); | |
226 | nouveau_accel_fini(drm); | |
227 | return; | |
228 | } | |
229 | ||
230 | ret = nouveau_object_new(nv_object(drm), | |
231 | drm->channel->handle, NvNotify0, | |
232 | 0x003d, &(struct nv_dma_class) { | |
233 | .flags = NV_DMA_TARGET_VRAM | | |
234 | NV_DMA_ACCESS_RDWR, | |
235 | .start = drm->notify->addr, | |
236 | .limit = drm->notify->addr + 31 | |
237 | }, sizeof(struct nv_dma_class), | |
238 | &object); | |
239 | if (ret) { | |
240 | nouveau_accel_fini(drm); | |
241 | return; | |
242 | } | |
243 | } | |
244 | ||
245 | ||
49981046 | 246 | nouveau_bo_move_init(drm); |
ebb945a9 BS |
247 | } |
248 | ||
56550d94 GKH |
249 | static int nouveau_drm_probe(struct pci_dev *pdev, |
250 | const struct pci_device_id *pent) | |
94580299 BS |
251 | { |
252 | struct nouveau_device *device; | |
ebb945a9 BS |
253 | struct apertures_struct *aper; |
254 | bool boot = false; | |
94580299 BS |
255 | int ret; |
256 | ||
ebb945a9 BS |
257 | /* remove conflicting drivers (vesafb, efifb etc) */ |
258 | aper = alloc_apertures(3); | |
259 | if (!aper) | |
260 | return -ENOMEM; | |
261 | ||
262 | aper->ranges[0].base = pci_resource_start(pdev, 1); | |
263 | aper->ranges[0].size = pci_resource_len(pdev, 1); | |
264 | aper->count = 1; | |
265 | ||
266 | if (pci_resource_len(pdev, 2)) { | |
267 | aper->ranges[aper->count].base = pci_resource_start(pdev, 2); | |
268 | aper->ranges[aper->count].size = pci_resource_len(pdev, 2); | |
269 | aper->count++; | |
270 | } | |
271 | ||
272 | if (pci_resource_len(pdev, 3)) { | |
273 | aper->ranges[aper->count].base = pci_resource_start(pdev, 3); | |
274 | aper->ranges[aper->count].size = pci_resource_len(pdev, 3); | |
275 | aper->count++; | |
276 | } | |
277 | ||
278 | #ifdef CONFIG_X86 | |
279 | boot = pdev->resource[PCI_ROM_RESOURCE].flags & IORESOURCE_ROM_SHADOW; | |
280 | #endif | |
281 | remove_conflicting_framebuffers(aper, "nouveaufb", boot); | |
83ef7777 | 282 | kfree(aper); |
ebb945a9 | 283 | |
94580299 BS |
284 | ret = nouveau_device_create(pdev, nouveau_name(pdev), pci_name(pdev), |
285 | nouveau_config, nouveau_debug, &device); | |
286 | if (ret) | |
287 | return ret; | |
288 | ||
289 | pci_set_master(pdev); | |
290 | ||
77145f1c | 291 | ret = drm_get_pci_dev(pdev, pent, &driver); |
94580299 | 292 | if (ret) { |
ebb945a9 | 293 | nouveau_object_ref(NULL, (struct nouveau_object **)&device); |
94580299 BS |
294 | return ret; |
295 | } | |
296 | ||
297 | return 0; | |
298 | } | |
299 | ||
5addcf0a DA |
300 | #define PCI_CLASS_MULTIMEDIA_HD_AUDIO 0x0403 |
301 | ||
302 | static void | |
303 | nouveau_get_hdmi_dev(struct drm_device *dev) | |
304 | { | |
305 | struct nouveau_drm *drm = dev->dev_private; | |
306 | struct pci_dev *pdev = dev->pdev; | |
307 | ||
308 | /* subfunction one is a hdmi audio device? */ | |
309 | drm->hdmi_device = pci_get_bus_and_slot((unsigned int)pdev->bus->number, | |
310 | PCI_DEVFN(PCI_SLOT(pdev->devfn), 1)); | |
311 | ||
312 | if (!drm->hdmi_device) { | |
313 | DRM_INFO("hdmi device not found %d %d %d\n", pdev->bus->number, PCI_SLOT(pdev->devfn), 1); | |
314 | return; | |
315 | } | |
316 | ||
317 | if ((drm->hdmi_device->class >> 8) != PCI_CLASS_MULTIMEDIA_HD_AUDIO) { | |
318 | DRM_INFO("possible hdmi device not audio %d\n", drm->hdmi_device->class); | |
319 | pci_dev_put(drm->hdmi_device); | |
320 | drm->hdmi_device = NULL; | |
321 | return; | |
322 | } | |
323 | } | |
324 | ||
5b8a43ae | 325 | static int |
94580299 BS |
326 | nouveau_drm_load(struct drm_device *dev, unsigned long flags) |
327 | { | |
328 | struct pci_dev *pdev = dev->pdev; | |
ebb945a9 | 329 | struct nouveau_device *device; |
94580299 BS |
330 | struct nouveau_drm *drm; |
331 | int ret; | |
332 | ||
fa6df8c1 | 333 | ret = nouveau_cli_create(pdev, "DRM", sizeof(*drm), (void**)&drm); |
94580299 BS |
334 | if (ret) |
335 | return ret; | |
336 | ||
77145f1c BS |
337 | dev->dev_private = drm; |
338 | drm->dev = dev; | |
339 | ||
94580299 | 340 | INIT_LIST_HEAD(&drm->clients); |
ebb945a9 | 341 | spin_lock_init(&drm->tile.lock); |
94580299 | 342 | |
5addcf0a DA |
343 | nouveau_get_hdmi_dev(dev); |
344 | ||
cb75d97e BS |
345 | /* make sure AGP controller is in a consistent state before we |
346 | * (possibly) execute vbios init tables (see nouveau_agp.h) | |
347 | */ | |
348 | if (drm_pci_device_is_agp(dev) && dev->agp) { | |
349 | /* dummy device object, doesn't init anything, but allows | |
350 | * agp code access to registers | |
351 | */ | |
352 | ret = nouveau_object_new(nv_object(drm), NVDRM_CLIENT, | |
353 | NVDRM_DEVICE, 0x0080, | |
354 | &(struct nv_device_class) { | |
355 | .device = ~0, | |
356 | .disable = | |
357 | ~(NV_DEVICE_DISABLE_MMIO | | |
358 | NV_DEVICE_DISABLE_IDENTIFY), | |
359 | .debug0 = ~0, | |
360 | }, sizeof(struct nv_device_class), | |
361 | &drm->device); | |
362 | if (ret) | |
ebb945a9 | 363 | goto fail_device; |
cb75d97e BS |
364 | |
365 | nouveau_agp_reset(drm); | |
366 | nouveau_object_del(nv_object(drm), NVDRM_CLIENT, NVDRM_DEVICE); | |
367 | } | |
368 | ||
94580299 BS |
369 | ret = nouveau_object_new(nv_object(drm), NVDRM_CLIENT, NVDRM_DEVICE, |
370 | 0x0080, &(struct nv_device_class) { | |
371 | .device = ~0, | |
372 | .disable = 0, | |
373 | .debug0 = 0, | |
374 | }, sizeof(struct nv_device_class), | |
375 | &drm->device); | |
376 | if (ret) | |
377 | goto fail_device; | |
378 | ||
7d3428cd IM |
379 | dev->irq_enabled = true; |
380 | ||
77145f1c BS |
381 | /* workaround an odd issue on nvc1 by disabling the device's |
382 | * nosnoop capability. hopefully won't cause issues until a | |
383 | * better fix is found - assuming there is one... | |
384 | */ | |
ebb945a9 | 385 | device = nv_device(drm->device); |
77145f1c BS |
386 | if (nv_device(drm->device)->chipset == 0xc1) |
387 | nv_mask(device, 0x00088080, 0x00000800, 0x00000000); | |
ebb945a9 | 388 | |
77145f1c | 389 | nouveau_vga_init(drm); |
cb75d97e BS |
390 | nouveau_agp_init(drm); |
391 | ||
ebb945a9 BS |
392 | if (device->card_type >= NV_50) { |
393 | ret = nouveau_vm_new(nv_device(drm->device), 0, (1ULL << 40), | |
394 | 0x1000, &drm->client.base.vm); | |
395 | if (ret) | |
396 | goto fail_device; | |
397 | } | |
398 | ||
399 | ret = nouveau_ttm_init(drm); | |
94580299 | 400 | if (ret) |
77145f1c BS |
401 | goto fail_ttm; |
402 | ||
403 | ret = nouveau_bios_init(dev); | |
404 | if (ret) | |
405 | goto fail_bios; | |
406 | ||
77145f1c | 407 | ret = nouveau_display_create(dev); |
ebb945a9 | 408 | if (ret) |
77145f1c BS |
409 | goto fail_dispctor; |
410 | ||
411 | if (dev->mode_config.num_crtc) { | |
412 | ret = nouveau_display_init(dev); | |
413 | if (ret) | |
414 | goto fail_dispinit; | |
415 | } | |
416 | ||
26fdd78c | 417 | nouveau_sysfs_init(dev); |
b9ed919f | 418 | nouveau_hwmon_init(dev); |
ebb945a9 BS |
419 | nouveau_accel_init(drm); |
420 | nouveau_fbcon_init(dev); | |
5addcf0a DA |
421 | |
422 | if (nouveau_runtime_pm != 0) { | |
423 | pm_runtime_use_autosuspend(dev->dev); | |
424 | pm_runtime_set_autosuspend_delay(dev->dev, 5000); | |
425 | pm_runtime_set_active(dev->dev); | |
426 | pm_runtime_allow(dev->dev); | |
427 | pm_runtime_mark_last_busy(dev->dev); | |
428 | pm_runtime_put(dev->dev); | |
429 | } | |
94580299 BS |
430 | return 0; |
431 | ||
77145f1c BS |
432 | fail_dispinit: |
433 | nouveau_display_destroy(dev); | |
434 | fail_dispctor: | |
77145f1c BS |
435 | nouveau_bios_takedown(dev); |
436 | fail_bios: | |
ebb945a9 | 437 | nouveau_ttm_fini(drm); |
77145f1c BS |
438 | fail_ttm: |
439 | nouveau_agp_fini(drm); | |
440 | nouveau_vga_fini(drm); | |
94580299 BS |
441 | fail_device: |
442 | nouveau_cli_destroy(&drm->client); | |
443 | return ret; | |
444 | } | |
445 | ||
5b8a43ae | 446 | static int |
94580299 BS |
447 | nouveau_drm_unload(struct drm_device *dev) |
448 | { | |
77145f1c | 449 | struct nouveau_drm *drm = nouveau_drm(dev); |
94580299 | 450 | |
5addcf0a | 451 | pm_runtime_get_sync(dev->dev); |
ebb945a9 BS |
452 | nouveau_fbcon_fini(dev); |
453 | nouveau_accel_fini(drm); | |
b9ed919f | 454 | nouveau_hwmon_fini(dev); |
26fdd78c | 455 | nouveau_sysfs_fini(dev); |
77145f1c | 456 | |
9430738d BS |
457 | if (dev->mode_config.num_crtc) |
458 | nouveau_display_fini(dev); | |
77145f1c BS |
459 | nouveau_display_destroy(dev); |
460 | ||
77145f1c | 461 | nouveau_bios_takedown(dev); |
94580299 | 462 | |
ebb945a9 | 463 | nouveau_ttm_fini(drm); |
cb75d97e | 464 | nouveau_agp_fini(drm); |
77145f1c | 465 | nouveau_vga_fini(drm); |
cb75d97e | 466 | |
5addcf0a DA |
467 | if (drm->hdmi_device) |
468 | pci_dev_put(drm->hdmi_device); | |
94580299 BS |
469 | nouveau_cli_destroy(&drm->client); |
470 | return 0; | |
471 | } | |
472 | ||
473 | static void | |
474 | nouveau_drm_remove(struct pci_dev *pdev) | |
475 | { | |
77145f1c BS |
476 | struct drm_device *dev = pci_get_drvdata(pdev); |
477 | struct nouveau_drm *drm = nouveau_drm(dev); | |
ebb945a9 | 478 | struct nouveau_object *device; |
77145f1c | 479 | |
7d3428cd | 480 | dev->irq_enabled = false; |
77145f1c BS |
481 | device = drm->client.base.device; |
482 | drm_put_dev(dev); | |
483 | ||
ebb945a9 BS |
484 | nouveau_object_ref(NULL, &device); |
485 | nouveau_object_debug(); | |
94580299 BS |
486 | } |
487 | ||
cd897837 | 488 | static int |
2d8b9ccb | 489 | nouveau_do_suspend(struct drm_device *dev) |
94580299 | 490 | { |
77145f1c | 491 | struct nouveau_drm *drm = nouveau_drm(dev); |
94580299 BS |
492 | struct nouveau_cli *cli; |
493 | int ret; | |
494 | ||
9430738d | 495 | if (dev->mode_config.num_crtc) { |
c52f4fa6 | 496 | NV_INFO(drm, "suspending display...\n"); |
9430738d BS |
497 | ret = nouveau_display_suspend(dev); |
498 | if (ret) | |
499 | return ret; | |
500 | } | |
94580299 | 501 | |
c52f4fa6 | 502 | NV_INFO(drm, "evicting buffers...\n"); |
ebb945a9 BS |
503 | ttm_bo_evict_mm(&drm->ttm.bdev, TTM_PL_VRAM); |
504 | ||
c52f4fa6 | 505 | NV_INFO(drm, "waiting for kernel channels to go idle...\n"); |
81dff21b BS |
506 | if (drm->cechan) { |
507 | ret = nouveau_channel_idle(drm->cechan); | |
508 | if (ret) | |
f3980dc5 | 509 | goto fail_display; |
81dff21b BS |
510 | } |
511 | ||
512 | if (drm->channel) { | |
513 | ret = nouveau_channel_idle(drm->channel); | |
514 | if (ret) | |
f3980dc5 | 515 | goto fail_display; |
81dff21b BS |
516 | } |
517 | ||
c52f4fa6 | 518 | NV_INFO(drm, "suspending client object trees...\n"); |
ebb945a9 | 519 | if (drm->fence && nouveau_fence(drm)->suspend) { |
f3980dc5 IM |
520 | if (!nouveau_fence(drm)->suspend(drm)) { |
521 | ret = -ENOMEM; | |
522 | goto fail_display; | |
523 | } | |
ebb945a9 BS |
524 | } |
525 | ||
94580299 BS |
526 | list_for_each_entry(cli, &drm->clients, head) { |
527 | ret = nouveau_client_fini(&cli->base, true); | |
528 | if (ret) | |
529 | goto fail_client; | |
530 | } | |
531 | ||
c52f4fa6 | 532 | NV_INFO(drm, "suspending kernel object tree...\n"); |
94580299 BS |
533 | ret = nouveau_client_fini(&drm->client.base, true); |
534 | if (ret) | |
535 | goto fail_client; | |
536 | ||
cb75d97e | 537 | nouveau_agp_fini(drm); |
94580299 BS |
538 | return 0; |
539 | ||
540 | fail_client: | |
541 | list_for_each_entry_continue_reverse(cli, &drm->clients, head) { | |
542 | nouveau_client_init(&cli->base); | |
543 | } | |
544 | ||
f3980dc5 IM |
545 | if (drm->fence && nouveau_fence(drm)->resume) |
546 | nouveau_fence(drm)->resume(drm); | |
547 | ||
548 | fail_display: | |
9430738d | 549 | if (dev->mode_config.num_crtc) { |
c52f4fa6 | 550 | NV_INFO(drm, "resuming display...\n"); |
9430738d BS |
551 | nouveau_display_resume(dev); |
552 | } | |
94580299 BS |
553 | return ret; |
554 | } | |
555 | ||
2d8b9ccb | 556 | int nouveau_pmops_suspend(struct device *dev) |
94580299 | 557 | { |
2d8b9ccb DA |
558 | struct pci_dev *pdev = to_pci_dev(dev); |
559 | struct drm_device *drm_dev = pci_get_drvdata(pdev); | |
94580299 BS |
560 | int ret; |
561 | ||
5addcf0a DA |
562 | if (drm_dev->switch_power_state == DRM_SWITCH_POWER_OFF || |
563 | drm_dev->switch_power_state == DRM_SWITCH_POWER_DYNAMIC_OFF) | |
94580299 BS |
564 | return 0; |
565 | ||
5addcf0a DA |
566 | if (drm_dev->mode_config.num_crtc) |
567 | nouveau_fbcon_set_suspend(drm_dev, 1); | |
568 | ||
2d8b9ccb | 569 | ret = nouveau_do_suspend(drm_dev); |
94580299 BS |
570 | if (ret) |
571 | return ret; | |
2d8b9ccb DA |
572 | |
573 | pci_save_state(pdev); | |
574 | pci_disable_device(pdev); | |
575 | pci_set_power_state(pdev, PCI_D3hot); | |
2d8b9ccb DA |
576 | return 0; |
577 | } | |
578 | ||
cd897837 | 579 | static int |
2d8b9ccb DA |
580 | nouveau_do_resume(struct drm_device *dev) |
581 | { | |
582 | struct nouveau_drm *drm = nouveau_drm(dev); | |
583 | struct nouveau_cli *cli; | |
584 | ||
c52f4fa6 | 585 | NV_INFO(drm, "re-enabling device...\n"); |
94580299 | 586 | |
cb75d97e BS |
587 | nouveau_agp_reset(drm); |
588 | ||
c52f4fa6 | 589 | NV_INFO(drm, "resuming kernel object tree...\n"); |
94580299 | 590 | nouveau_client_init(&drm->client.base); |
ebb945a9 | 591 | nouveau_agp_init(drm); |
94580299 | 592 | |
c52f4fa6 | 593 | NV_INFO(drm, "resuming client object trees...\n"); |
81dff21b BS |
594 | if (drm->fence && nouveau_fence(drm)->resume) |
595 | nouveau_fence(drm)->resume(drm); | |
596 | ||
94580299 BS |
597 | list_for_each_entry(cli, &drm->clients, head) { |
598 | nouveau_client_init(&cli->base); | |
599 | } | |
cb75d97e | 600 | |
77145f1c | 601 | nouveau_run_vbios_init(dev); |
77145f1c | 602 | |
9430738d | 603 | if (dev->mode_config.num_crtc) { |
c52f4fa6 | 604 | NV_INFO(drm, "resuming display...\n"); |
5addcf0a | 605 | nouveau_display_repin(dev); |
9430738d | 606 | } |
5addcf0a | 607 | |
77145f1c | 608 | return 0; |
94580299 BS |
609 | } |
610 | ||
2d8b9ccb DA |
611 | int nouveau_pmops_resume(struct device *dev) |
612 | { | |
613 | struct pci_dev *pdev = to_pci_dev(dev); | |
614 | struct drm_device *drm_dev = pci_get_drvdata(pdev); | |
615 | int ret; | |
616 | ||
5addcf0a DA |
617 | if (drm_dev->switch_power_state == DRM_SWITCH_POWER_OFF || |
618 | drm_dev->switch_power_state == DRM_SWITCH_POWER_DYNAMIC_OFF) | |
2d8b9ccb DA |
619 | return 0; |
620 | ||
621 | pci_set_power_state(pdev, PCI_D0); | |
622 | pci_restore_state(pdev); | |
623 | ret = pci_enable_device(pdev); | |
624 | if (ret) | |
625 | return ret; | |
626 | pci_set_master(pdev); | |
627 | ||
5addcf0a | 628 | ret = nouveau_do_resume(drm_dev); |
c52f4fa6 | 629 | if (ret) |
5addcf0a | 630 | return ret; |
5addcf0a DA |
631 | if (drm_dev->mode_config.num_crtc) |
632 | nouveau_fbcon_set_suspend(drm_dev, 0); | |
633 | ||
634 | nouveau_fbcon_zfill_all(drm_dev); | |
01172772 DA |
635 | if (drm_dev->mode_config.num_crtc) |
636 | nouveau_display_resume(drm_dev); | |
5addcf0a | 637 | return 0; |
2d8b9ccb DA |
638 | } |
639 | ||
640 | static int nouveau_pmops_freeze(struct device *dev) | |
641 | { | |
642 | struct pci_dev *pdev = to_pci_dev(dev); | |
643 | struct drm_device *drm_dev = pci_get_drvdata(pdev); | |
5addcf0a DA |
644 | int ret; |
645 | ||
5addcf0a DA |
646 | if (drm_dev->mode_config.num_crtc) |
647 | nouveau_fbcon_set_suspend(drm_dev, 1); | |
2d8b9ccb | 648 | |
5addcf0a | 649 | ret = nouveau_do_suspend(drm_dev); |
5addcf0a | 650 | return ret; |
2d8b9ccb DA |
651 | } |
652 | ||
653 | static int nouveau_pmops_thaw(struct device *dev) | |
654 | { | |
655 | struct pci_dev *pdev = to_pci_dev(dev); | |
656 | struct drm_device *drm_dev = pci_get_drvdata(pdev); | |
5addcf0a | 657 | int ret; |
2d8b9ccb | 658 | |
5addcf0a | 659 | ret = nouveau_do_resume(drm_dev); |
c52f4fa6 | 660 | if (ret) |
5addcf0a | 661 | return ret; |
5addcf0a DA |
662 | if (drm_dev->mode_config.num_crtc) |
663 | nouveau_fbcon_set_suspend(drm_dev, 0); | |
664 | nouveau_fbcon_zfill_all(drm_dev); | |
01172772 DA |
665 | if (drm_dev->mode_config.num_crtc) |
666 | nouveau_display_resume(drm_dev); | |
5addcf0a | 667 | return 0; |
2d8b9ccb DA |
668 | } |
669 | ||
670 | ||
5b8a43ae | 671 | static int |
ebb945a9 BS |
672 | nouveau_drm_open(struct drm_device *dev, struct drm_file *fpriv) |
673 | { | |
674 | struct pci_dev *pdev = dev->pdev; | |
675 | struct nouveau_drm *drm = nouveau_drm(dev); | |
676 | struct nouveau_cli *cli; | |
a2896ced | 677 | char name[32], tmpname[TASK_COMM_LEN]; |
ebb945a9 BS |
678 | int ret; |
679 | ||
5addcf0a DA |
680 | /* need to bring up power immediately if opening device */ |
681 | ret = pm_runtime_get_sync(dev->dev); | |
682 | if (ret < 0) | |
683 | return ret; | |
684 | ||
a2896ced MS |
685 | get_task_comm(tmpname, current); |
686 | snprintf(name, sizeof(name), "%s[%d]", tmpname, pid_nr(fpriv->pid)); | |
fa6df8c1 BS |
687 | |
688 | ret = nouveau_cli_create(pdev, name, sizeof(*cli), (void **)&cli); | |
ebb945a9 | 689 | if (ret) |
5addcf0a | 690 | goto out_suspend; |
ebb945a9 BS |
691 | |
692 | if (nv_device(drm->device)->card_type >= NV_50) { | |
693 | ret = nouveau_vm_new(nv_device(drm->device), 0, (1ULL << 40), | |
694 | 0x1000, &cli->base.vm); | |
695 | if (ret) { | |
696 | nouveau_cli_destroy(cli); | |
5addcf0a | 697 | goto out_suspend; |
ebb945a9 BS |
698 | } |
699 | } | |
700 | ||
701 | fpriv->driver_priv = cli; | |
702 | ||
703 | mutex_lock(&drm->client.mutex); | |
704 | list_add(&cli->head, &drm->clients); | |
705 | mutex_unlock(&drm->client.mutex); | |
5addcf0a DA |
706 | |
707 | out_suspend: | |
708 | pm_runtime_mark_last_busy(dev->dev); | |
709 | pm_runtime_put_autosuspend(dev->dev); | |
710 | ||
711 | return ret; | |
ebb945a9 BS |
712 | } |
713 | ||
5b8a43ae | 714 | static void |
ebb945a9 BS |
715 | nouveau_drm_preclose(struct drm_device *dev, struct drm_file *fpriv) |
716 | { | |
717 | struct nouveau_cli *cli = nouveau_cli(fpriv); | |
718 | struct nouveau_drm *drm = nouveau_drm(dev); | |
719 | ||
5addcf0a DA |
720 | pm_runtime_get_sync(dev->dev); |
721 | ||
ebb945a9 BS |
722 | if (cli->abi16) |
723 | nouveau_abi16_fini(cli->abi16); | |
724 | ||
725 | mutex_lock(&drm->client.mutex); | |
726 | list_del(&cli->head); | |
727 | mutex_unlock(&drm->client.mutex); | |
5addcf0a | 728 | |
ebb945a9 BS |
729 | } |
730 | ||
5b8a43ae | 731 | static void |
ebb945a9 BS |
732 | nouveau_drm_postclose(struct drm_device *dev, struct drm_file *fpriv) |
733 | { | |
734 | struct nouveau_cli *cli = nouveau_cli(fpriv); | |
735 | nouveau_cli_destroy(cli); | |
5addcf0a DA |
736 | pm_runtime_mark_last_busy(dev->dev); |
737 | pm_runtime_put_autosuspend(dev->dev); | |
ebb945a9 BS |
738 | } |
739 | ||
baa70943 | 740 | static const struct drm_ioctl_desc |
77145f1c | 741 | nouveau_ioctls[] = { |
7d761258 | 742 | DRM_IOCTL_DEF_DRV(NOUVEAU_GETPARAM, nouveau_abi16_ioctl_getparam, DRM_UNLOCKED|DRM_AUTH|DRM_RENDER_ALLOW), |
77145f1c | 743 | DRM_IOCTL_DEF_DRV(NOUVEAU_SETPARAM, nouveau_abi16_ioctl_setparam, DRM_UNLOCKED|DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), |
7d761258 MP |
744 | DRM_IOCTL_DEF_DRV(NOUVEAU_CHANNEL_ALLOC, nouveau_abi16_ioctl_channel_alloc, DRM_UNLOCKED|DRM_AUTH|DRM_RENDER_ALLOW), |
745 | DRM_IOCTL_DEF_DRV(NOUVEAU_CHANNEL_FREE, nouveau_abi16_ioctl_channel_free, DRM_UNLOCKED|DRM_AUTH|DRM_RENDER_ALLOW), | |
746 | DRM_IOCTL_DEF_DRV(NOUVEAU_GROBJ_ALLOC, nouveau_abi16_ioctl_grobj_alloc, DRM_UNLOCKED|DRM_AUTH|DRM_RENDER_ALLOW), | |
747 | DRM_IOCTL_DEF_DRV(NOUVEAU_NOTIFIEROBJ_ALLOC, nouveau_abi16_ioctl_notifierobj_alloc, DRM_UNLOCKED|DRM_AUTH|DRM_RENDER_ALLOW), | |
748 | DRM_IOCTL_DEF_DRV(NOUVEAU_GPUOBJ_FREE, nouveau_abi16_ioctl_gpuobj_free, DRM_UNLOCKED|DRM_AUTH|DRM_RENDER_ALLOW), | |
749 | DRM_IOCTL_DEF_DRV(NOUVEAU_GEM_NEW, nouveau_gem_ioctl_new, DRM_UNLOCKED|DRM_AUTH|DRM_RENDER_ALLOW), | |
750 | DRM_IOCTL_DEF_DRV(NOUVEAU_GEM_PUSHBUF, nouveau_gem_ioctl_pushbuf, DRM_UNLOCKED|DRM_AUTH|DRM_RENDER_ALLOW), | |
751 | DRM_IOCTL_DEF_DRV(NOUVEAU_GEM_CPU_PREP, nouveau_gem_ioctl_cpu_prep, DRM_UNLOCKED|DRM_AUTH|DRM_RENDER_ALLOW), | |
752 | DRM_IOCTL_DEF_DRV(NOUVEAU_GEM_CPU_FINI, nouveau_gem_ioctl_cpu_fini, DRM_UNLOCKED|DRM_AUTH|DRM_RENDER_ALLOW), | |
753 | DRM_IOCTL_DEF_DRV(NOUVEAU_GEM_INFO, nouveau_gem_ioctl_info, DRM_UNLOCKED|DRM_AUTH|DRM_RENDER_ALLOW), | |
77145f1c BS |
754 | }; |
755 | ||
5addcf0a DA |
756 | long nouveau_drm_ioctl(struct file *filp, |
757 | unsigned int cmd, unsigned long arg) | |
758 | { | |
759 | struct drm_file *file_priv = filp->private_data; | |
760 | struct drm_device *dev; | |
761 | long ret; | |
762 | dev = file_priv->minor->dev; | |
763 | ||
764 | ret = pm_runtime_get_sync(dev->dev); | |
765 | if (ret < 0) | |
766 | return ret; | |
767 | ||
768 | ret = drm_ioctl(filp, cmd, arg); | |
769 | ||
770 | pm_runtime_mark_last_busy(dev->dev); | |
771 | pm_runtime_put_autosuspend(dev->dev); | |
772 | return ret; | |
773 | } | |
77145f1c BS |
774 | static const struct file_operations |
775 | nouveau_driver_fops = { | |
776 | .owner = THIS_MODULE, | |
777 | .open = drm_open, | |
778 | .release = drm_release, | |
5addcf0a | 779 | .unlocked_ioctl = nouveau_drm_ioctl, |
77145f1c BS |
780 | .mmap = nouveau_ttm_mmap, |
781 | .poll = drm_poll, | |
77145f1c BS |
782 | .read = drm_read, |
783 | #if defined(CONFIG_COMPAT) | |
784 | .compat_ioctl = nouveau_compat_ioctl, | |
785 | #endif | |
786 | .llseek = noop_llseek, | |
787 | }; | |
788 | ||
789 | static struct drm_driver | |
790 | driver = { | |
791 | .driver_features = | |
4cb4ea39 | 792 | DRIVER_USE_AGP | |
7d761258 | 793 | DRIVER_GEM | DRIVER_MODESET | DRIVER_PRIME | DRIVER_RENDER, |
77145f1c BS |
794 | |
795 | .load = nouveau_drm_load, | |
796 | .unload = nouveau_drm_unload, | |
797 | .open = nouveau_drm_open, | |
798 | .preclose = nouveau_drm_preclose, | |
799 | .postclose = nouveau_drm_postclose, | |
800 | .lastclose = nouveau_vga_lastclose, | |
801 | ||
33b903e8 MS |
802 | #if defined(CONFIG_DEBUG_FS) |
803 | .debugfs_init = nouveau_debugfs_init, | |
804 | .debugfs_cleanup = nouveau_debugfs_takedown, | |
805 | #endif | |
806 | ||
77145f1c | 807 | .get_vblank_counter = drm_vblank_count, |
51cb4b39 BS |
808 | .enable_vblank = nouveau_display_vblank_enable, |
809 | .disable_vblank = nouveau_display_vblank_disable, | |
d83ef853 BS |
810 | .get_scanout_position = nouveau_display_scanoutpos, |
811 | .get_vblank_timestamp = nouveau_display_vblstamp, | |
77145f1c BS |
812 | |
813 | .ioctls = nouveau_ioctls, | |
baa70943 | 814 | .num_ioctls = ARRAY_SIZE(nouveau_ioctls), |
77145f1c BS |
815 | .fops = &nouveau_driver_fops, |
816 | ||
817 | .prime_handle_to_fd = drm_gem_prime_handle_to_fd, | |
818 | .prime_fd_to_handle = drm_gem_prime_fd_to_handle, | |
ab9ccb96 AP |
819 | .gem_prime_export = drm_gem_prime_export, |
820 | .gem_prime_import = drm_gem_prime_import, | |
821 | .gem_prime_pin = nouveau_gem_prime_pin, | |
1af7c7dd | 822 | .gem_prime_unpin = nouveau_gem_prime_unpin, |
ab9ccb96 AP |
823 | .gem_prime_get_sg_table = nouveau_gem_prime_get_sg_table, |
824 | .gem_prime_import_sg_table = nouveau_gem_prime_import_sg_table, | |
825 | .gem_prime_vmap = nouveau_gem_prime_vmap, | |
826 | .gem_prime_vunmap = nouveau_gem_prime_vunmap, | |
77145f1c | 827 | |
77145f1c BS |
828 | .gem_free_object = nouveau_gem_object_del, |
829 | .gem_open_object = nouveau_gem_object_open, | |
830 | .gem_close_object = nouveau_gem_object_close, | |
831 | ||
832 | .dumb_create = nouveau_display_dumb_create, | |
833 | .dumb_map_offset = nouveau_display_dumb_map_offset, | |
43387b37 | 834 | .dumb_destroy = drm_gem_dumb_destroy, |
77145f1c BS |
835 | |
836 | .name = DRIVER_NAME, | |
837 | .desc = DRIVER_DESC, | |
838 | #ifdef GIT_REVISION | |
839 | .date = GIT_REVISION, | |
840 | #else | |
841 | .date = DRIVER_DATE, | |
842 | #endif | |
843 | .major = DRIVER_MAJOR, | |
844 | .minor = DRIVER_MINOR, | |
845 | .patchlevel = DRIVER_PATCHLEVEL, | |
846 | }; | |
847 | ||
94580299 BS |
848 | static struct pci_device_id |
849 | nouveau_drm_pci_table[] = { | |
850 | { | |
851 | PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID), | |
852 | .class = PCI_BASE_CLASS_DISPLAY << 16, | |
853 | .class_mask = 0xff << 16, | |
854 | }, | |
855 | { | |
856 | PCI_DEVICE(PCI_VENDOR_ID_NVIDIA_SGS, PCI_ANY_ID), | |
857 | .class = PCI_BASE_CLASS_DISPLAY << 16, | |
858 | .class_mask = 0xff << 16, | |
859 | }, | |
860 | {} | |
861 | }; | |
862 | ||
5addcf0a DA |
863 | static int nouveau_pmops_runtime_suspend(struct device *dev) |
864 | { | |
865 | struct pci_dev *pdev = to_pci_dev(dev); | |
866 | struct drm_device *drm_dev = pci_get_drvdata(pdev); | |
867 | int ret; | |
868 | ||
869 | if (nouveau_runtime_pm == 0) | |
870 | return -EINVAL; | |
871 | ||
b25b4427 IM |
872 | /* are we optimus enabled? */ |
873 | if (nouveau_runtime_pm == -1 && !nouveau_is_optimus() && !nouveau_is_v1_dsm()) { | |
874 | DRM_DEBUG_DRIVER("failing to power off - not optimus\n"); | |
875 | return -EINVAL; | |
876 | } | |
877 | ||
c52f4fa6 | 878 | nv_debug_level(SILENT); |
5addcf0a DA |
879 | drm_kms_helper_poll_disable(drm_dev); |
880 | vga_switcheroo_set_dynamic_switch(pdev, VGA_SWITCHEROO_OFF); | |
881 | nouveau_switcheroo_optimus_dsm(); | |
882 | ret = nouveau_do_suspend(drm_dev); | |
883 | pci_save_state(pdev); | |
884 | pci_disable_device(pdev); | |
885 | pci_set_power_state(pdev, PCI_D3cold); | |
886 | drm_dev->switch_power_state = DRM_SWITCH_POWER_DYNAMIC_OFF; | |
887 | return ret; | |
888 | } | |
889 | ||
890 | static int nouveau_pmops_runtime_resume(struct device *dev) | |
891 | { | |
892 | struct pci_dev *pdev = to_pci_dev(dev); | |
893 | struct drm_device *drm_dev = pci_get_drvdata(pdev); | |
894 | struct nouveau_device *device = nouveau_dev(drm_dev); | |
895 | int ret; | |
896 | ||
897 | if (nouveau_runtime_pm == 0) | |
898 | return -EINVAL; | |
899 | ||
900 | pci_set_power_state(pdev, PCI_D0); | |
901 | pci_restore_state(pdev); | |
902 | ret = pci_enable_device(pdev); | |
903 | if (ret) | |
904 | return ret; | |
905 | pci_set_master(pdev); | |
906 | ||
907 | ret = nouveau_do_resume(drm_dev); | |
01172772 DA |
908 | if (drm_dev->mode_config.num_crtc) |
909 | nouveau_display_resume(drm_dev); | |
5addcf0a DA |
910 | drm_kms_helper_poll_enable(drm_dev); |
911 | /* do magic */ | |
912 | nv_mask(device, 0x88488, (1 << 25), (1 << 25)); | |
913 | vga_switcheroo_set_dynamic_switch(pdev, VGA_SWITCHEROO_ON); | |
914 | drm_dev->switch_power_state = DRM_SWITCH_POWER_ON; | |
c52f4fa6 | 915 | nv_debug_level(NORMAL); |
5addcf0a DA |
916 | return ret; |
917 | } | |
918 | ||
919 | static int nouveau_pmops_runtime_idle(struct device *dev) | |
920 | { | |
921 | struct pci_dev *pdev = to_pci_dev(dev); | |
922 | struct drm_device *drm_dev = pci_get_drvdata(pdev); | |
923 | struct nouveau_drm *drm = nouveau_drm(drm_dev); | |
924 | struct drm_crtc *crtc; | |
925 | ||
926 | if (nouveau_runtime_pm == 0) | |
927 | return -EBUSY; | |
928 | ||
929 | /* are we optimus enabled? */ | |
930 | if (nouveau_runtime_pm == -1 && !nouveau_is_optimus() && !nouveau_is_v1_dsm()) { | |
931 | DRM_DEBUG_DRIVER("failing to power off - not optimus\n"); | |
932 | return -EBUSY; | |
933 | } | |
934 | ||
935 | /* if we have a hdmi audio device - make sure it has a driver loaded */ | |
936 | if (drm->hdmi_device) { | |
937 | if (!drm->hdmi_device->driver) { | |
938 | DRM_DEBUG_DRIVER("failing to power off - no HDMI audio driver loaded\n"); | |
939 | pm_runtime_mark_last_busy(dev); | |
940 | return -EBUSY; | |
941 | } | |
942 | } | |
943 | ||
944 | list_for_each_entry(crtc, &drm->dev->mode_config.crtc_list, head) { | |
945 | if (crtc->enabled) { | |
946 | DRM_DEBUG_DRIVER("failing to power off - crtc active\n"); | |
947 | return -EBUSY; | |
948 | } | |
949 | } | |
950 | pm_runtime_mark_last_busy(dev); | |
951 | pm_runtime_autosuspend(dev); | |
952 | /* we don't want the main rpm_idle to call suspend - we want to autosuspend */ | |
953 | return 1; | |
954 | } | |
955 | ||
2d8b9ccb DA |
956 | static const struct dev_pm_ops nouveau_pm_ops = { |
957 | .suspend = nouveau_pmops_suspend, | |
958 | .resume = nouveau_pmops_resume, | |
959 | .freeze = nouveau_pmops_freeze, | |
960 | .thaw = nouveau_pmops_thaw, | |
961 | .poweroff = nouveau_pmops_freeze, | |
962 | .restore = nouveau_pmops_resume, | |
5addcf0a DA |
963 | .runtime_suspend = nouveau_pmops_runtime_suspend, |
964 | .runtime_resume = nouveau_pmops_runtime_resume, | |
965 | .runtime_idle = nouveau_pmops_runtime_idle, | |
2d8b9ccb DA |
966 | }; |
967 | ||
94580299 BS |
968 | static struct pci_driver |
969 | nouveau_drm_pci_driver = { | |
970 | .name = "nouveau", | |
971 | .id_table = nouveau_drm_pci_table, | |
972 | .probe = nouveau_drm_probe, | |
973 | .remove = nouveau_drm_remove, | |
2d8b9ccb | 974 | .driver.pm = &nouveau_pm_ops, |
94580299 BS |
975 | }; |
976 | ||
977 | static int __init | |
978 | nouveau_drm_init(void) | |
979 | { | |
77145f1c BS |
980 | if (nouveau_modeset == -1) { |
981 | #ifdef CONFIG_VGA_CONSOLE | |
982 | if (vgacon_text_force()) | |
983 | nouveau_modeset = 0; | |
77145f1c | 984 | #endif |
77145f1c BS |
985 | } |
986 | ||
987 | if (!nouveau_modeset) | |
988 | return 0; | |
989 | ||
990 | nouveau_register_dsm_handler(); | |
991 | return drm_pci_init(&driver, &nouveau_drm_pci_driver); | |
94580299 BS |
992 | } |
993 | ||
994 | static void __exit | |
995 | nouveau_drm_exit(void) | |
996 | { | |
77145f1c BS |
997 | if (!nouveau_modeset) |
998 | return; | |
999 | ||
1000 | drm_pci_exit(&driver, &nouveau_drm_pci_driver); | |
1001 | nouveau_unregister_dsm_handler(); | |
94580299 BS |
1002 | } |
1003 | ||
1004 | module_init(nouveau_drm_init); | |
1005 | module_exit(nouveau_drm_exit); | |
1006 | ||
1007 | MODULE_DEVICE_TABLE(pci, nouveau_drm_pci_table); | |
77145f1c BS |
1008 | MODULE_AUTHOR(DRIVER_AUTHOR); |
1009 | MODULE_DESCRIPTION(DRIVER_DESC); | |
94580299 | 1010 | MODULE_LICENSE("GPL and additional rights"); |