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drm/nv50: allow gpuobjs that aren't mapped into aperture
[mirror_ubuntu-artful-kernel.git] / drivers / gpu / drm / nouveau / nouveau_drv.h
CommitLineData
6ee73861
BS		 1/*
2 * Copyright 2005 Stephane Marchesin.
3 * All Rights Reserved.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 */
24
25#ifndef __NOUVEAU_DRV_H__
26#define __NOUVEAU_DRV_H__
27
28#define DRIVER_AUTHOR "Stephane Marchesin"
29#define DRIVER_EMAIL "dri-devel@lists.sourceforge.net"
30
31#define DRIVER_NAME "nouveau"
32#define DRIVER_DESC "nVidia Riva/TNT/GeForce"
33#define DRIVER_DATE "20090420"
34
35#define DRIVER_MAJOR 0
36#define DRIVER_MINOR 0
a1606a95 37#define DRIVER_PATCHLEVEL 16
6ee73861
BS		 38
39#define NOUVEAU_FAMILY 0x0000FFFF
40#define NOUVEAU_FLAGS 0xFFFF0000
41
42#include "ttm/ttm_bo_api.h"
43#include "ttm/ttm_bo_driver.h"
44#include "ttm/ttm_placement.h"
45#include "ttm/ttm_memory.h"
46#include "ttm/ttm_module.h"
47
48struct nouveau_fpriv {
49 struct ttm_object_file *tfile;
50};
51
52#define DRM_FILE_PAGE_OFFSET (0x100000000ULL >> PAGE_SHIFT)
53
54#include "nouveau_drm.h"
55#include "nouveau_reg.h"
56#include "nouveau_bios.h"
054b93e4 57struct nouveau_grctx;
6ee73861
BS		 58
59#define MAX_NUM_DCB_ENTRIES 16
60
61#define NOUVEAU_MAX_CHANNEL_NR 128
a0af9add 62#define NOUVEAU_MAX_TILE_NR 15
6ee73861
BS		 63
64#define NV50_VM_MAX_VRAM (2*1024*1024*1024ULL)
65#define NV50_VM_BLOCK (512*1024*1024ULL)
66#define NV50_VM_VRAM_NR (NV50_VM_MAX_VRAM / NV50_VM_BLOCK)
67
a0af9add
FJ		 68struct nouveau_tile_reg {
69 struct nouveau_fence *fence;
70 uint32_t addr;
71 uint32_t size;
72 bool used;
73};
74
6ee73861
BS		 75struct nouveau_bo {
76 struct ttm_buffer_object bo;
77 struct ttm_placement placement;
78 u32 placements[3];
78ad0f7b 79 u32 busy_placements[3];
6ee73861
BS		 80 struct ttm_bo_kmap_obj kmap;
81 struct list_head head;
82
83 /* protected by ttm_bo_reserve() */
84 struct drm_file *reserved_by;
85 struct list_head entry;
86 int pbbo_index;
a1606a95 87 bool validate_mapped;
6ee73861
BS		 88
89 struct nouveau_channel *channel;
90
91 bool mappable;
92 bool no_vm;
93
94 uint32_t tile_mode;
95 uint32_t tile_flags;
a0af9add 96 struct nouveau_tile_reg *tile;
6ee73861
BS		 97
98 struct drm_gem_object *gem;
99 struct drm_file *cpu_filp;
100 int pin_refcnt;
101};
102
103static inline struct nouveau_bo *
104nouveau_bo(struct ttm_buffer_object *bo)
105{
106 return container_of(bo, struct nouveau_bo, bo);
107}
108
109static inline struct nouveau_bo *
110nouveau_gem_object(struct drm_gem_object *gem)
111{
112 return gem ? gem->driver_private : NULL;
113}
114
115/* TODO: submit equivalent to TTM generic API upstream? */
116static inline void __iomem *
117nvbo_kmap_obj_iovirtual(struct nouveau_bo *nvbo)
118{
119 bool is_iomem;
120 void __iomem *ioptr = (void __force __iomem *)ttm_kmap_obj_virtual(
121 &nvbo->kmap, &is_iomem);
122 WARN_ON_ONCE(ioptr && !is_iomem);
123 return ioptr;
124}
125
6ee73861
BS		 126enum nouveau_flags {
127 NV_NFORCE = 0x10000000,
128 NV_NFORCE2 = 0x20000000
129};
130
131#define NVOBJ_ENGINE_SW 0
132#define NVOBJ_ENGINE_GR 1
133#define NVOBJ_ENGINE_DISPLAY 2
134#define NVOBJ_ENGINE_INT 0xdeadbeef
135
6ee73861
BS		 136#define NVOBJ_FLAG_ZERO_ALLOC (1 << 1)
137#define NVOBJ_FLAG_ZERO_FREE (1 << 2)
6ee73861 138struct nouveau_gpuobj {
b3beb167 139 struct drm_device *dev;
6ee73861
BS		 140 struct list_head list;
141
b833ac26 142 struct drm_mm_node *im_pramin;
6ee73861 143 struct nouveau_bo *im_backing;
6ee73861
BS		 144 uint32_t *im_backing_suspend;
145 int im_bound;
146
147 uint32_t flags;
148 int refcount;
149
43efc9ce 150 u32 size;
de3a6c0a
BS		 151 u32 pinst;
152 u32 cinst;
153 u64 vinst;
154
6ee73861
BS		 155 uint32_t engine;
156 uint32_t class;
157
158 void (*dtor)(struct drm_device *, struct nouveau_gpuobj *);
159 void *priv;
160};
161
6ee73861
BS		 162struct nouveau_channel {
163 struct drm_device *dev;
164 int id;
165
166 /* owner of this fifo */
167 struct drm_file *file_priv;
168 /* mapping of the fifo itself */
169 struct drm_local_map *map;
170
171 /* mapping of the regs controling the fifo */
172 void __iomem *user;
173 uint32_t user_get;
174 uint32_t user_put;
175
176 /* Fencing */
177 struct {
178 /* lock protects the pending list only */
179 spinlock_t lock;
180 struct list_head pending;
181 uint32_t sequence;
182 uint32_t sequence_ack;
047d1d3c 183 atomic_t last_sequence_irq;
6ee73861
BS		 184 } fence;
185
186 /* DMA push buffer */
a8eaebc6
BS		 187 struct nouveau_gpuobj *pushbuf;
188 struct nouveau_bo *pushbuf_bo;
189 uint32_t pushbuf_base;
6ee73861
BS		 190
191 /* Notifier memory */
192 struct nouveau_bo *notifier_bo;
b833ac26 193 struct drm_mm notifier_heap;
6ee73861
BS		 194
195 /* PFIFO context */
a8eaebc6
BS		 196 struct nouveau_gpuobj *ramfc;
197 struct nouveau_gpuobj *cache;
6ee73861
BS		 198
199 /* PGRAPH context */
200 /* XXX may be merge 2 pointers as private data ??? */
a8eaebc6 201 struct nouveau_gpuobj *ramin_grctx;
6ee73861
BS		 202 void *pgraph_ctx;
203
204 /* NV50 VM */
a8eaebc6
BS		 205 struct nouveau_gpuobj *vm_pd;
206 struct nouveau_gpuobj *vm_gart_pt;
207 struct nouveau_gpuobj *vm_vram_pt[NV50_VM_VRAM_NR];
6ee73861
BS		 208
209 /* Objects */
a8eaebc6
BS		 210 struct nouveau_gpuobj *ramin; /* Private instmem */
211 struct drm_mm ramin_heap; /* Private PRAMIN heap */
212 struct nouveau_ramht *ramht; /* Hash table */
6ee73861
BS		 213
214 /* GPU object info for stuff used in-kernel (mm_enabled) */
215 uint32_t m2mf_ntfy;
216 uint32_t vram_handle;
217 uint32_t gart_handle;
218 bool accel_done;
219
220 /* Push buffer state (only for drm's channel on !mm_enabled) */
221 struct {
222 int max;
223 int free;
224 int cur;
225 int put;
226 /* access via pushbuf_bo */
9a391ad8
BS		 227
228 int ib_base;
229 int ib_max;
230 int ib_free;
231 int ib_put;
6ee73861
BS		 232 } dma;
233
234 uint32_t sw_subchannel[8];
235
236 struct {
237 struct nouveau_gpuobj *vblsem;
238 uint32_t vblsem_offset;
239 uint32_t vblsem_rval;
240 struct list_head vbl_wait;
241 } nvsw;
242
243 struct {
244 bool active;
245 char name[32];
246 struct drm_info_list info;
247 } debugfs;
248};
249
250struct nouveau_instmem_engine {
251 void *priv;
252
253 int (*init)(struct drm_device *dev);
254 void (*takedown)(struct drm_device *dev);
255 int (*suspend)(struct drm_device *dev);
256 void (*resume)(struct drm_device *dev);
257
258 int (*populate)(struct drm_device *, struct nouveau_gpuobj *,
259 uint32_t *size);
260 void (*clear)(struct drm_device *, struct nouveau_gpuobj *);
261 int (*bind)(struct drm_device *, struct nouveau_gpuobj *);
262 int (*unbind)(struct drm_device *, struct nouveau_gpuobj *);
f56cb86f 263 void (*flush)(struct drm_device *);
6ee73861
BS		 264};
265
266struct nouveau_mc_engine {
267 int (*init)(struct drm_device *dev);
268 void (*takedown)(struct drm_device *dev);
269};
270
271struct nouveau_timer_engine {
272 int (*init)(struct drm_device *dev);
273 void (*takedown)(struct drm_device *dev);
274 uint64_t (*read)(struct drm_device *dev);
275};
276
277struct nouveau_fb_engine {
cb00f7c1
FJ		 278 int num_tiles;
279
6ee73861
BS		 280 int (*init)(struct drm_device *dev);
281 void (*takedown)(struct drm_device *dev);
cb00f7c1
FJ		 282
283 void (*set_region_tiling)(struct drm_device *dev, int i, uint32_t addr,
284 uint32_t size, uint32_t pitch);
6ee73861
BS		 285};
286
287struct nouveau_fifo_engine {
6ee73861
BS		 288 int channels;
289
a8eaebc6 290 struct nouveau_gpuobj *playlist[2];
ac94a343
BS		 291 int cur_playlist;
292
6ee73861
BS		 293 int (*init)(struct drm_device *);
294 void (*takedown)(struct drm_device *);
295
296 void (*disable)(struct drm_device *);
297 void (*enable)(struct drm_device *);
298 bool (*reassign)(struct drm_device *, bool enable);
588d7d12
FJ		 299 bool (*cache_flush)(struct drm_device *dev);
300 bool (*cache_pull)(struct drm_device *dev, bool enable);
6ee73861
BS		 301
302 int (*channel_id)(struct drm_device *);
303
304 int (*create_context)(struct nouveau_channel *);
305 void (*destroy_context)(struct nouveau_channel *);
306 int (*load_context)(struct nouveau_channel *);
307 int (*unload_context)(struct drm_device *);
308};
309
310struct nouveau_pgraph_object_method {
311 int id;
312 int (*exec)(struct nouveau_channel *chan, int grclass, int mthd,
313 uint32_t data);
314};
315
316struct nouveau_pgraph_object_class {
317 int id;
318 bool software;
319 struct nouveau_pgraph_object_method *methods;
320};
321
322struct nouveau_pgraph_engine {
323 struct nouveau_pgraph_object_class *grclass;
324 bool accel_blocked;
054b93e4 325 int grctx_size;
6ee73861 326
c50a5681 327 /* NV2x/NV3x context table (0x400780) */
a8eaebc6 328 struct nouveau_gpuobj *ctx_table;
c50a5681 329
6ee73861
BS		 330 int (*init)(struct drm_device *);
331 void (*takedown)(struct drm_device *);
332
333 void (*fifo_access)(struct drm_device *, bool);
334
335 struct nouveau_channel *(*channel)(struct drm_device *);
336 int (*create_context)(struct nouveau_channel *);
337 void (*destroy_context)(struct nouveau_channel *);
338 int (*load_context)(struct nouveau_channel *);
339 int (*unload_context)(struct drm_device *);
cb00f7c1
FJ		 340
341 void (*set_region_tiling)(struct drm_device *dev, int i, uint32_t addr,
342 uint32_t size, uint32_t pitch);
6ee73861
BS		 343};
344
c88c2e06
FJ		 345struct nouveau_display_engine {
346 int (*early_init)(struct drm_device *);
347 void (*late_takedown)(struct drm_device *);
348 int (*create)(struct drm_device *);
349 int (*init)(struct drm_device *);
350 void (*destroy)(struct drm_device *);
351};
352
ee2e0131
BS		 353struct nouveau_gpio_engine {
354 int (*init)(struct drm_device *);
355 void (*takedown)(struct drm_device *);
356
357 int (*get)(struct drm_device *, enum dcb_gpio_tag);
358 int (*set)(struct drm_device *, enum dcb_gpio_tag, int state);
359
360 void (*irq_enable)(struct drm_device *, enum dcb_gpio_tag, bool on);
361};
362
6ee73861
BS		 363struct nouveau_engine {
364 struct nouveau_instmem_engine instmem;
365 struct nouveau_mc_engine mc;
366 struct nouveau_timer_engine timer;
367 struct nouveau_fb_engine fb;
368 struct nouveau_pgraph_engine graph;
369 struct nouveau_fifo_engine fifo;
c88c2e06 370 struct nouveau_display_engine display;
ee2e0131 371 struct nouveau_gpio_engine gpio;
6ee73861
BS		 372};
373
374struct nouveau_pll_vals {
375 union {
376 struct {
377#ifdef __BIG_ENDIAN
378 uint8_t N1, M1, N2, M2;
379#else
380 uint8_t M1, N1, M2, N2;
381#endif
382 };
383 struct {
384 uint16_t NM1, NM2;
385 } __attribute__((packed));
386 };
387 int log2P;
388
389 int refclk;
390};
391
392enum nv04_fp_display_regs {
393 FP_DISPLAY_END,
394 FP_TOTAL,
395 FP_CRTC,
396 FP_SYNC_START,
397 FP_SYNC_END,
398 FP_VALID_START,
399 FP_VALID_END
400};
401
402struct nv04_crtc_reg {
403 unsigned char MiscOutReg; /* */
4a9f822f 404 uint8_t CRTC[0xa0];
6ee73861
BS		 405 uint8_t CR58[0x10];
406 uint8_t Sequencer[5];
407 uint8_t Graphics[9];
408 uint8_t Attribute[21];
409 unsigned char DAC[768]; /* Internal Colorlookuptable */
410
411 /* PCRTC regs */
412 uint32_t fb_start;
413 uint32_t crtc_cfg;
414 uint32_t cursor_cfg;
415 uint32_t gpio_ext;
416 uint32_t crtc_830;
417 uint32_t crtc_834;
418 uint32_t crtc_850;
419 uint32_t crtc_eng_ctrl;
420
421 /* PRAMDAC regs */
422 uint32_t nv10_cursync;
423 struct nouveau_pll_vals pllvals;
424 uint32_t ramdac_gen_ctrl;
425 uint32_t ramdac_630;
426 uint32_t ramdac_634;
427 uint32_t tv_setup;
428 uint32_t tv_vtotal;
429 uint32_t tv_vskew;
430 uint32_t tv_vsync_delay;
431 uint32_t tv_htotal;
432 uint32_t tv_hskew;
433 uint32_t tv_hsync_delay;
434 uint32_t tv_hsync_delay2;
435 uint32_t fp_horiz_regs[7];
436 uint32_t fp_vert_regs[7];
437 uint32_t dither;
438 uint32_t fp_control;
439 uint32_t dither_regs[6];
440 uint32_t fp_debug_0;
441 uint32_t fp_debug_1;
442 uint32_t fp_debug_2;
443 uint32_t fp_margin_color;
444 uint32_t ramdac_8c0;
445 uint32_t ramdac_a20;
446 uint32_t ramdac_a24;
447 uint32_t ramdac_a34;
448 uint32_t ctv_regs[38];
449};
450
451struct nv04_output_reg {
452 uint32_t output;
453 int head;
454};
455
456struct nv04_mode_state {
457 uint32_t bpp;
458 uint32_t width;
459 uint32_t height;
460 uint32_t interlace;
461 uint32_t repaint0;
462 uint32_t repaint1;
463 uint32_t screen;
464 uint32_t scale;
465 uint32_t dither;
466 uint32_t extra;
467 uint32_t fifo;
468 uint32_t pixel;
469 uint32_t horiz;
470 int arbitration0;
471 int arbitration1;
472 uint32_t pll;
473 uint32_t pllB;
474 uint32_t vpll;
475 uint32_t vpll2;
476 uint32_t vpllB;
477 uint32_t vpll2B;
478 uint32_t pllsel;
479 uint32_t sel_clk;
480 uint32_t general;
481 uint32_t crtcOwner;
482 uint32_t head;
483 uint32_t head2;
484 uint32_t cursorConfig;
485 uint32_t cursor0;
486 uint32_t cursor1;
487 uint32_t cursor2;
488 uint32_t timingH;
489 uint32_t timingV;
490 uint32_t displayV;
491 uint32_t crtcSync;
492
493 struct nv04_crtc_reg crtc_reg[2];
494};
495
496enum nouveau_card_type {
497 NV_04 = 0x00,
498 NV_10 = 0x10,
499 NV_20 = 0x20,
500 NV_30 = 0x30,
501 NV_40 = 0x40,
502 NV_50 = 0x50,
4b223eef 503 NV_C0 = 0xc0,
6ee73861
BS		 504};
505
506struct drm_nouveau_private {
507 struct drm_device *dev;
6ee73861
BS		 508
509 /* the card type, takes NV_* as values */
510 enum nouveau_card_type card_type;
511 /* exact chipset, derived from NV_PMC_BOOT_0 */
512 int chipset;
513 int flags;
514
515 void __iomem *mmio;
5125bfd8 516
6ee73861 517 void __iomem *ramin;
5125bfd8
BS		 518 u32 ramin_size;
519 u32 ramin_base;
520 bool ramin_available;
521 spinlock_t ramin_lock;
6ee73861 522
ac8fb975
BS		 523 struct nouveau_bo *vga_ram;
524
6ee73861
BS		 525 struct workqueue_struct *wq;
526 struct work_struct irq_work;
a5acac66 527 struct work_struct hpd_work;
6ee73861
BS		 528
529 struct list_head vbl_waiting;
530
531 struct {
ba4420c2 532 struct drm_global_reference mem_global_ref;
6ee73861
BS		 533 struct ttm_bo_global_ref bo_global_ref;
534 struct ttm_bo_device bdev;
6ee73861
BS		 535 atomic_t validate_sequence;
536 } ttm;
537
6ee73861
BS		 538 int fifo_alloc_count;
539 struct nouveau_channel *fifos[NOUVEAU_MAX_CHANNEL_NR];
540
541 struct nouveau_engine engine;
542 struct nouveau_channel *channel;
543
ff9e5279
MM		 544 /* For PFIFO and PGRAPH. */
545 spinlock_t context_switch_lock;
546
6ee73861 547 /* RAMIN configuration, RAMFC, RAMHT and RAMRO offsets */
a8eaebc6 548 struct nouveau_ramht *ramht;
6ee73861
BS		 549 uint32_t ramin_rsvd_vram;
550 uint32_t ramht_offset;
551 uint32_t ramht_size;
552 uint32_t ramht_bits;
553 uint32_t ramfc_offset;
554 uint32_t ramfc_size;
555 uint32_t ramro_offset;
556 uint32_t ramro_size;
557
6ee73861
BS		 558 struct {
559 enum {
560 NOUVEAU_GART_NONE = 0,
561 NOUVEAU_GART_AGP,
562 NOUVEAU_GART_SGDMA
563 } type;
564 uint64_t aper_base;
565 uint64_t aper_size;
566 uint64_t aper_free;
567
568 struct nouveau_gpuobj *sg_ctxdma;
569 struct page *sg_dummy_page;
570 dma_addr_t sg_dummy_bus;
6ee73861
BS		 571 } gart_info;
572
a0af9add
FJ		 573 /* nv10-nv40 tiling regions */
574 struct {
575 struct nouveau_tile_reg reg[NOUVEAU_MAX_TILE_NR];
576 spinlock_t lock;
577 } tile;
578
a76fb4e8
BS		 579 /* VRAM/fb configuration */
580 uint64_t vram_size;
581 uint64_t vram_sys_base;
582
583 uint64_t fb_phys;
584 uint64_t fb_available_size;
585 uint64_t fb_mappable_pages;
586 uint64_t fb_aper_free;
587 int fb_mtrr;
588
6ee73861
BS		 589 /* G8x/G9x virtual address space */
590 uint64_t vm_gart_base;
591 uint64_t vm_gart_size;
592 uint64_t vm_vram_base;
593 uint64_t vm_vram_size;
594 uint64_t vm_end;
595 struct nouveau_gpuobj *vm_vram_pt[NV50_VM_VRAM_NR];
596 int vm_vram_pt_nr;
6ee73861 597
b833ac26 598 struct drm_mm ramin_heap;
6ee73861 599
6ee73861
BS		 600 struct list_head gpuobj_list;
601
04a39c57 602 struct nvbios vbios;
6ee73861
BS		 603
604 struct nv04_mode_state mode_reg;
605 struct nv04_mode_state saved_reg;
606 uint32_t saved_vga_font[4][16384];
607 uint32_t crtc_owner;
608 uint32_t dac_users[4];
609
610 struct nouveau_suspend_resume {
6ee73861 611 uint32_t *ramin_copy;
6ee73861
BS		 612 } susres;
613
614 struct backlight_device *backlight;
6ee73861
BS		 615
616 struct nouveau_channel *evo;
87c0e0e5
BS		 617 struct {
618 struct dcb_entry *dcb;
619 u16 script;
620 u32 pclk;
621 } evo_irq;
6ee73861
BS		 622
623 struct {
624 struct dentry *channel_root;
625 } debugfs;
38651674 626
8be48d92 627 struct nouveau_fbdev *nfbdev;
06415c56 628 struct apertures_struct *apertures;
6ee73861
BS		 629};
630
631static inline struct drm_nouveau_private *
632nouveau_bdev(struct ttm_bo_device *bd)
633{
634 return container_of(bd, struct drm_nouveau_private, ttm.bdev);
635}
636
637static inline int
638nouveau_bo_ref(struct nouveau_bo *ref, struct nouveau_bo **pnvbo)
639{
640 struct nouveau_bo *prev;
641
642 if (!pnvbo)
643 return -EINVAL;
644 prev = *pnvbo;
645
646 *pnvbo = ref ? nouveau_bo(ttm_bo_reference(&ref->bo)) : NULL;
647 if (prev) {
648 struct ttm_buffer_object *bo = &prev->bo;
649
650 ttm_bo_unref(&bo);
651 }
652
653 return 0;
654}
655
6ee73861
BS		 656#define NOUVEAU_GET_USER_CHANNEL_WITH_RETURN(id, cl, ch) do { \
657 struct drm_nouveau_private *nv = dev->dev_private; \
658 if (!nouveau_channel_owner(dev, (cl), (id))) { \
659 NV_ERROR(dev, "pid %d doesn't own channel %d\n", \
660 DRM_CURRENTPID, (id)); \
661 return -EPERM; \
662 } \
663 (ch) = nv->fifos[(id)]; \
664} while (0)
665
666/* nouveau_drv.c */
667extern int nouveau_noagp;
668extern int nouveau_duallink;
669extern int nouveau_uscript_lvds;
670extern int nouveau_uscript_tmds;
671extern int nouveau_vram_pushbuf;
672extern int nouveau_vram_notify;
673extern int nouveau_fbpercrtc;
f4053509 674extern int nouveau_tv_disable;
6ee73861
BS		 675extern char *nouveau_tv_norm;
676extern int nouveau_reg_debug;
677extern char *nouveau_vbios;
a1470890 678extern int nouveau_ignorelid;
a32ed69d
MK		 679extern int nouveau_nofbaccel;
680extern int nouveau_noaccel;
da647d5b 681extern int nouveau_override_conntype;
6ee73861 682
6a9ee8af
DA		 683extern int nouveau_pci_suspend(struct pci_dev *pdev, pm_message_t pm_state);
684extern int nouveau_pci_resume(struct pci_dev *pdev);
685
6ee73861
BS		 686/* nouveau_state.c */
687extern void nouveau_preclose(struct drm_device *dev, struct drm_file *);
688extern int nouveau_load(struct drm_device *, unsigned long flags);
689extern int nouveau_firstopen(struct drm_device *);
690extern void nouveau_lastclose(struct drm_device *);
691extern int nouveau_unload(struct drm_device *);
692extern int nouveau_ioctl_getparam(struct drm_device *, void *data,
693 struct drm_file *);
694extern int nouveau_ioctl_setparam(struct drm_device *, void *data,
695 struct drm_file *);
696extern bool nouveau_wait_until(struct drm_device *, uint64_t timeout,
697 uint32_t reg, uint32_t mask, uint32_t val);
698extern bool nouveau_wait_for_idle(struct drm_device *);
699extern int nouveau_card_init(struct drm_device *);
6ee73861
BS		 700
701/* nouveau_mem.c */
a76fb4e8 702extern int nouveau_mem_detect(struct drm_device *dev);
6ee73861
BS		 703extern int nouveau_mem_init(struct drm_device *);
704extern int nouveau_mem_init_agp(struct drm_device *);
e04d8e82 705extern int nouveau_mem_reset_agp(struct drm_device *);
6ee73861 706extern void nouveau_mem_close(struct drm_device *);
a0af9add
FJ		 707extern struct nouveau_tile_reg *nv10_mem_set_tiling(struct drm_device *dev,
708 uint32_t addr,
709 uint32_t size,
710 uint32_t pitch);
711extern void nv10_mem_expire_tiling(struct drm_device *dev,
712 struct nouveau_tile_reg *tile,
713 struct nouveau_fence *fence);
6ee73861
BS		 714extern int nv50_mem_vm_bind_linear(struct drm_device *, uint64_t virt,
715 uint32_t size, uint32_t flags,
716 uint64_t phys);
717extern void nv50_mem_vm_unbind(struct drm_device *, uint64_t virt,
718 uint32_t size);
719
720/* nouveau_notifier.c */
721extern int nouveau_notifier_init_channel(struct nouveau_channel *);
722extern void nouveau_notifier_takedown_channel(struct nouveau_channel *);
723extern int nouveau_notifier_alloc(struct nouveau_channel *, uint32_t handle,
724 int cout, uint32_t *offset);
725extern int nouveau_notifier_offset(struct nouveau_gpuobj *, uint32_t *);
726extern int nouveau_ioctl_notifier_alloc(struct drm_device *, void *data,
727 struct drm_file *);
728extern int nouveau_ioctl_notifier_free(struct drm_device *, void *data,
729 struct drm_file *);
730
731/* nouveau_channel.c */
732extern struct drm_ioctl_desc nouveau_ioctls[];
733extern int nouveau_max_ioctl;
734extern void nouveau_channel_cleanup(struct drm_device *, struct drm_file *);
735extern int nouveau_channel_owner(struct drm_device *, struct drm_file *,
736 int channel);
737extern int nouveau_channel_alloc(struct drm_device *dev,
738 struct nouveau_channel **chan,
739 struct drm_file *file_priv,
740 uint32_t fb_ctxdma, uint32_t tt_ctxdma);
741extern void nouveau_channel_free(struct nouveau_channel *);
6ee73861
BS		 742
743/* nouveau_object.c */
744extern int nouveau_gpuobj_early_init(struct drm_device *);
745extern int nouveau_gpuobj_init(struct drm_device *);
746extern void nouveau_gpuobj_takedown(struct drm_device *);
747extern void nouveau_gpuobj_late_takedown(struct drm_device *);
748extern int nouveau_gpuobj_suspend(struct drm_device *dev);
749extern void nouveau_gpuobj_suspend_cleanup(struct drm_device *dev);
750extern void nouveau_gpuobj_resume(struct drm_device *dev);
751extern int nouveau_gpuobj_channel_init(struct nouveau_channel *,
752 uint32_t vram_h, uint32_t tt_h);
753extern void nouveau_gpuobj_channel_takedown(struct nouveau_channel *);
754extern int nouveau_gpuobj_new(struct drm_device *, struct nouveau_channel *,
755 uint32_t size, int align, uint32_t flags,
756 struct nouveau_gpuobj **);
a8eaebc6
BS		 757extern void nouveau_gpuobj_ref(struct nouveau_gpuobj *,
758 struct nouveau_gpuobj **);
43efc9ce
BS		 759extern int nouveau_gpuobj_new_fake(struct drm_device *, u32 pinst, u64 vinst,
760 u32 size, u32 flags,
a8eaebc6 761 struct nouveau_gpuobj **);
6ee73861
BS		 762extern int nouveau_gpuobj_dma_new(struct nouveau_channel *, int class,
763 uint64_t offset, uint64_t size, int access,
764 int target, struct nouveau_gpuobj **);
765extern int nouveau_gpuobj_gart_dma_new(struct nouveau_channel *,
766 uint64_t offset, uint64_t size,
767 int access, struct nouveau_gpuobj **,
768 uint32_t *o_ret);
769extern int nouveau_gpuobj_gr_new(struct nouveau_channel *, int class,
770 struct nouveau_gpuobj **);
f03a314b
FJ		 771extern int nouveau_gpuobj_sw_new(struct nouveau_channel *, int class,
772 struct nouveau_gpuobj **);
6ee73861
BS		 773extern int nouveau_ioctl_grobj_alloc(struct drm_device *, void *data,
774 struct drm_file *);
775extern int nouveau_ioctl_gpuobj_free(struct drm_device *, void *data,
776 struct drm_file *);
777
778/* nouveau_irq.c */
779extern irqreturn_t nouveau_irq_handler(DRM_IRQ_ARGS);
780extern void nouveau_irq_preinstall(struct drm_device *);
781extern int nouveau_irq_postinstall(struct drm_device *);
782extern void nouveau_irq_uninstall(struct drm_device *);
783
784/* nouveau_sgdma.c */
785extern int nouveau_sgdma_init(struct drm_device *);
786extern void nouveau_sgdma_takedown(struct drm_device *);
787extern int nouveau_sgdma_get_page(struct drm_device *, uint32_t offset,
788 uint32_t *page);
789extern struct ttm_backend *nouveau_sgdma_init_ttm(struct drm_device *);
790
791/* nouveau_debugfs.c */
792#if defined(CONFIG_DRM_NOUVEAU_DEBUG)
793extern int nouveau_debugfs_init(struct drm_minor *);
794extern void nouveau_debugfs_takedown(struct drm_minor *);
795extern int nouveau_debugfs_channel_init(struct nouveau_channel *);
796extern void nouveau_debugfs_channel_fini(struct nouveau_channel *);
797#else
798static inline int
799nouveau_debugfs_init(struct drm_minor *minor)
800{
801 return 0;
802}
803
804static inline void nouveau_debugfs_takedown(struct drm_minor *minor)
805{
806}
807
808static inline int
809nouveau_debugfs_channel_init(struct nouveau_channel *chan)
810{
811 return 0;
812}
813
814static inline void
815nouveau_debugfs_channel_fini(struct nouveau_channel *chan)
816{
817}
818#endif
819
820/* nouveau_dma.c */
75c99da6 821extern void nouveau_dma_pre_init(struct nouveau_channel *);
6ee73861 822extern int nouveau_dma_init(struct nouveau_channel *);
9a391ad8 823extern int nouveau_dma_wait(struct nouveau_channel *, int slots, int size);
6ee73861
BS		 824
825/* nouveau_acpi.c */
afeb3e11 826#define ROM_BIOS_PAGE 4096
2f41a7f1 827#if defined(CONFIG_ACPI)
6a9ee8af
DA		 828void nouveau_register_dsm_handler(void);
829void nouveau_unregister_dsm_handler(void);
afeb3e11
DA		 830int nouveau_acpi_get_bios_chunk(uint8_t *bios, int offset, int len);
831bool nouveau_acpi_rom_supported(struct pci_dev *pdev);
a6ed76d7 832int nouveau_acpi_edid(struct drm_device *, struct drm_connector *);
8edb381d
DA		 833#else
834static inline void nouveau_register_dsm_handler(void) {}
835static inline void nouveau_unregister_dsm_handler(void) {}
afeb3e11
DA		 836static inline bool nouveau_acpi_rom_supported(struct pci_dev *pdev) { return false; }
837static inline int nouveau_acpi_get_bios_chunk(uint8_t *bios, int offset, int len) { return -EINVAL; }
5620ba46 838static inline int nouveau_acpi_edid(struct drm_device *dev, struct drm_connector *connector) { return -EINVAL; }
8edb381d 839#endif
6ee73861
BS		 840
841/* nouveau_backlight.c */
842#ifdef CONFIG_DRM_NOUVEAU_BACKLIGHT
843extern int nouveau_backlight_init(struct drm_device *);
844extern void nouveau_backlight_exit(struct drm_device *);
845#else
846static inline int nouveau_backlight_init(struct drm_device *dev)
847{
848 return 0;
849}
850
851static inline void nouveau_backlight_exit(struct drm_device *dev) { }
852#endif
853
854/* nouveau_bios.c */
855extern int nouveau_bios_init(struct drm_device *);
856extern void nouveau_bios_takedown(struct drm_device *dev);
857extern int nouveau_run_vbios_init(struct drm_device *);
858extern void nouveau_bios_run_init_table(struct drm_device *, uint16_t table,
859 struct dcb_entry *);
860extern struct dcb_gpio_entry *nouveau_bios_gpio_entry(struct drm_device *,
861 enum dcb_gpio_tag);
862extern struct dcb_connector_table_entry *
863nouveau_bios_connector_entry(struct drm_device *, int index);
864extern int get_pll_limits(struct drm_device *, uint32_t limit_match,
865 struct pll_lims *);
866extern int nouveau_bios_run_display_table(struct drm_device *,
867 struct dcb_entry *,
868 uint32_t script, int pxclk);
869extern void *nouveau_bios_dp_table(struct drm_device *, struct dcb_entry *,
870 int *length);
871extern bool nouveau_bios_fp_mode(struct drm_device *, struct drm_display_mode *);
872extern uint8_t *nouveau_bios_embedded_edid(struct drm_device *);
873extern int nouveau_bios_parse_lvds_table(struct drm_device *, int pxclk,
874 bool *dl, bool *if_is_24bit);
875extern int run_tmds_table(struct drm_device *, struct dcb_entry *,
876 int head, int pxclk);
877extern int call_lvds_script(struct drm_device *, struct dcb_entry *, int head,
878 enum LVDS_script, int pxclk);
879
880/* nouveau_ttm.c */
881int nouveau_ttm_global_init(struct drm_nouveau_private *);
882void nouveau_ttm_global_release(struct drm_nouveau_private *);
883int nouveau_ttm_mmap(struct file *, struct vm_area_struct *);
884
885/* nouveau_dp.c */
886int nouveau_dp_auxch(struct nouveau_i2c_chan *auxch, int cmd, int addr,
887 uint8_t *data, int data_nr);
888bool nouveau_dp_detect(struct drm_encoder *);
889bool nouveau_dp_link_train(struct drm_encoder *);
890
891/* nv04_fb.c */
892extern int nv04_fb_init(struct drm_device *);
893extern void nv04_fb_takedown(struct drm_device *);
894
895/* nv10_fb.c */
896extern int nv10_fb_init(struct drm_device *);
897extern void nv10_fb_takedown(struct drm_device *);
cb00f7c1
FJ		 898extern void nv10_fb_set_region_tiling(struct drm_device *, int, uint32_t,
899 uint32_t, uint32_t);
6ee73861 900
8bded189
FJ		 901/* nv30_fb.c */
902extern int nv30_fb_init(struct drm_device *);
903extern void nv30_fb_takedown(struct drm_device *);
904
6ee73861
BS		 905/* nv40_fb.c */
906extern int nv40_fb_init(struct drm_device *);
907extern void nv40_fb_takedown(struct drm_device *);
cb00f7c1
FJ		 908extern void nv40_fb_set_region_tiling(struct drm_device *, int, uint32_t,
909 uint32_t, uint32_t);
6ee73861 910
304424e1
MK		 911/* nv50_fb.c */
912extern int nv50_fb_init(struct drm_device *);
913extern void nv50_fb_takedown(struct drm_device *);
914
4b223eef
BS		 915/* nvc0_fb.c */
916extern int nvc0_fb_init(struct drm_device *);
917extern void nvc0_fb_takedown(struct drm_device *);
918
6ee73861
BS		 919/* nv04_fifo.c */
920extern int nv04_fifo_init(struct drm_device *);
921extern void nv04_fifo_disable(struct drm_device *);
922extern void nv04_fifo_enable(struct drm_device *);
923extern bool nv04_fifo_reassign(struct drm_device *, bool);
588d7d12
FJ		 924extern bool nv04_fifo_cache_flush(struct drm_device *);
925extern bool nv04_fifo_cache_pull(struct drm_device *, bool);
6ee73861
BS		 926extern int nv04_fifo_channel_id(struct drm_device *);
927extern int nv04_fifo_create_context(struct nouveau_channel *);
928extern void nv04_fifo_destroy_context(struct nouveau_channel *);
929extern int nv04_fifo_load_context(struct nouveau_channel *);
930extern int nv04_fifo_unload_context(struct drm_device *);
931
932/* nv10_fifo.c */
933extern int nv10_fifo_init(struct drm_device *);
934extern int nv10_fifo_channel_id(struct drm_device *);
935extern int nv10_fifo_create_context(struct nouveau_channel *);
936extern void nv10_fifo_destroy_context(struct nouveau_channel *);
937extern int nv10_fifo_load_context(struct nouveau_channel *);
938extern int nv10_fifo_unload_context(struct drm_device *);
939
940/* nv40_fifo.c */
941extern int nv40_fifo_init(struct drm_device *);
942extern int nv40_fifo_create_context(struct nouveau_channel *);
943extern void nv40_fifo_destroy_context(struct nouveau_channel *);
944extern int nv40_fifo_load_context(struct nouveau_channel *);
945extern int nv40_fifo_unload_context(struct drm_device *);
946
947/* nv50_fifo.c */
948extern int nv50_fifo_init(struct drm_device *);
949extern void nv50_fifo_takedown(struct drm_device *);
950extern int nv50_fifo_channel_id(struct drm_device *);
951extern int nv50_fifo_create_context(struct nouveau_channel *);
952extern void nv50_fifo_destroy_context(struct nouveau_channel *);
953extern int nv50_fifo_load_context(struct nouveau_channel *);
954extern int nv50_fifo_unload_context(struct drm_device *);
955
4b223eef
BS		 956/* nvc0_fifo.c */
957extern int nvc0_fifo_init(struct drm_device *);
958extern void nvc0_fifo_takedown(struct drm_device *);
959extern void nvc0_fifo_disable(struct drm_device *);
960extern void nvc0_fifo_enable(struct drm_device *);
961extern bool nvc0_fifo_reassign(struct drm_device *, bool);
962extern bool nvc0_fifo_cache_flush(struct drm_device *);
963extern bool nvc0_fifo_cache_pull(struct drm_device *, bool);
964extern int nvc0_fifo_channel_id(struct drm_device *);
965extern int nvc0_fifo_create_context(struct nouveau_channel *);
966extern void nvc0_fifo_destroy_context(struct nouveau_channel *);
967extern int nvc0_fifo_load_context(struct nouveau_channel *);
968extern int nvc0_fifo_unload_context(struct drm_device *);
969
6ee73861
BS		 970/* nv04_graph.c */
971extern struct nouveau_pgraph_object_class nv04_graph_grclass[];
972extern int nv04_graph_init(struct drm_device *);
973extern void nv04_graph_takedown(struct drm_device *);
974extern void nv04_graph_fifo_access(struct drm_device *, bool);
975extern struct nouveau_channel *nv04_graph_channel(struct drm_device *);
976extern int nv04_graph_create_context(struct nouveau_channel *);
977extern void nv04_graph_destroy_context(struct nouveau_channel *);
978extern int nv04_graph_load_context(struct nouveau_channel *);
979extern int nv04_graph_unload_context(struct drm_device *);
980extern void nv04_graph_context_switch(struct drm_device *);
981
982/* nv10_graph.c */
983extern struct nouveau_pgraph_object_class nv10_graph_grclass[];
984extern int nv10_graph_init(struct drm_device *);
985extern void nv10_graph_takedown(struct drm_device *);
986extern struct nouveau_channel *nv10_graph_channel(struct drm_device *);
987extern int nv10_graph_create_context(struct nouveau_channel *);
988extern void nv10_graph_destroy_context(struct nouveau_channel *);
989extern int nv10_graph_load_context(struct nouveau_channel *);
990extern int nv10_graph_unload_context(struct drm_device *);
991extern void nv10_graph_context_switch(struct drm_device *);
cb00f7c1
FJ		 992extern void nv10_graph_set_region_tiling(struct drm_device *, int, uint32_t,
993 uint32_t, uint32_t);
6ee73861
BS		 994
995/* nv20_graph.c */
996extern struct nouveau_pgraph_object_class nv20_graph_grclass[];
997extern struct nouveau_pgraph_object_class nv30_graph_grclass[];
998extern int nv20_graph_create_context(struct nouveau_channel *);
999extern void nv20_graph_destroy_context(struct nouveau_channel *);
1000extern int nv20_graph_load_context(struct nouveau_channel *);
1001extern int nv20_graph_unload_context(struct drm_device *);
1002extern int nv20_graph_init(struct drm_device *);
1003extern void nv20_graph_takedown(struct drm_device *);
1004extern int nv30_graph_init(struct drm_device *);
cb00f7c1
FJ		 1005extern void nv20_graph_set_region_tiling(struct drm_device *, int, uint32_t,
1006 uint32_t, uint32_t);
6ee73861
BS		 1007
1008/* nv40_graph.c */
1009extern struct nouveau_pgraph_object_class nv40_graph_grclass[];
1010extern int nv40_graph_init(struct drm_device *);
1011extern void nv40_graph_takedown(struct drm_device *);
1012extern struct nouveau_channel *nv40_graph_channel(struct drm_device *);
1013extern int nv40_graph_create_context(struct nouveau_channel *);
1014extern void nv40_graph_destroy_context(struct nouveau_channel *);
1015extern int nv40_graph_load_context(struct nouveau_channel *);
1016extern int nv40_graph_unload_context(struct drm_device *);
054b93e4 1017extern void nv40_grctx_init(struct nouveau_grctx *);
cb00f7c1
FJ		 1018extern void nv40_graph_set_region_tiling(struct drm_device *, int, uint32_t,
1019 uint32_t, uint32_t);
6ee73861
BS		 1020
1021/* nv50_graph.c */
1022extern struct nouveau_pgraph_object_class nv50_graph_grclass[];
1023extern int nv50_graph_init(struct drm_device *);
1024extern void nv50_graph_takedown(struct drm_device *);
1025extern void nv50_graph_fifo_access(struct drm_device *, bool);
1026extern struct nouveau_channel *nv50_graph_channel(struct drm_device *);
1027extern int nv50_graph_create_context(struct nouveau_channel *);
1028extern void nv50_graph_destroy_context(struct nouveau_channel *);
1029extern int nv50_graph_load_context(struct nouveau_channel *);
1030extern int nv50_graph_unload_context(struct drm_device *);
1031extern void nv50_graph_context_switch(struct drm_device *);
d5f3c90d 1032extern int nv50_grctx_init(struct nouveau_grctx *);
6ee73861 1033
4b223eef
BS		 1034/* nvc0_graph.c */
1035extern int nvc0_graph_init(struct drm_device *);
1036extern void nvc0_graph_takedown(struct drm_device *);
1037extern void nvc0_graph_fifo_access(struct drm_device *, bool);
1038extern struct nouveau_channel *nvc0_graph_channel(struct drm_device *);
1039extern int nvc0_graph_create_context(struct nouveau_channel *);
1040extern void nvc0_graph_destroy_context(struct nouveau_channel *);
1041extern int nvc0_graph_load_context(struct nouveau_channel *);
1042extern int nvc0_graph_unload_context(struct drm_device *);
1043
6ee73861
BS		 1044/* nv04_instmem.c */
1045extern int nv04_instmem_init(struct drm_device *);
1046extern void nv04_instmem_takedown(struct drm_device *);
1047extern int nv04_instmem_suspend(struct drm_device *);
1048extern void nv04_instmem_resume(struct drm_device *);
1049extern int nv04_instmem_populate(struct drm_device *, struct nouveau_gpuobj *,
1050 uint32_t *size);
1051extern void nv04_instmem_clear(struct drm_device *, struct nouveau_gpuobj *);
1052extern int nv04_instmem_bind(struct drm_device *, struct nouveau_gpuobj *);
1053extern int nv04_instmem_unbind(struct drm_device *, struct nouveau_gpuobj *);
f56cb86f 1054extern void nv04_instmem_flush(struct drm_device *);
6ee73861
BS		 1055
1056/* nv50_instmem.c */
1057extern int nv50_instmem_init(struct drm_device *);
1058extern void nv50_instmem_takedown(struct drm_device *);
1059extern int nv50_instmem_suspend(struct drm_device *);
1060extern void nv50_instmem_resume(struct drm_device *);
1061extern int nv50_instmem_populate(struct drm_device *, struct nouveau_gpuobj *,
1062 uint32_t *size);
1063extern void nv50_instmem_clear(struct drm_device *, struct nouveau_gpuobj *);
1064extern int nv50_instmem_bind(struct drm_device *, struct nouveau_gpuobj *);
1065extern int nv50_instmem_unbind(struct drm_device *, struct nouveau_gpuobj *);
f56cb86f 1066extern void nv50_instmem_flush(struct drm_device *);
734ee835 1067extern void nv84_instmem_flush(struct drm_device *);
63187215 1068extern void nv50_vm_flush(struct drm_device *, int engine);
6ee73861 1069
4b223eef
BS		 1070/* nvc0_instmem.c */
1071extern int nvc0_instmem_init(struct drm_device *);
1072extern void nvc0_instmem_takedown(struct drm_device *);
1073extern int nvc0_instmem_suspend(struct drm_device *);
1074extern void nvc0_instmem_resume(struct drm_device *);
1075extern int nvc0_instmem_populate(struct drm_device *, struct nouveau_gpuobj *,
1076 uint32_t *size);
1077extern void nvc0_instmem_clear(struct drm_device *, struct nouveau_gpuobj *);
1078extern int nvc0_instmem_bind(struct drm_device *, struct nouveau_gpuobj *);
1079extern int nvc0_instmem_unbind(struct drm_device *, struct nouveau_gpuobj *);
1080extern void nvc0_instmem_flush(struct drm_device *);
1081
6ee73861
BS		 1082/* nv04_mc.c */
1083extern int nv04_mc_init(struct drm_device *);
1084extern void nv04_mc_takedown(struct drm_device *);
1085
1086/* nv40_mc.c */
1087extern int nv40_mc_init(struct drm_device *);
1088extern void nv40_mc_takedown(struct drm_device *);
1089
1090/* nv50_mc.c */
1091extern int nv50_mc_init(struct drm_device *);
1092extern void nv50_mc_takedown(struct drm_device *);
1093
1094/* nv04_timer.c */
1095extern int nv04_timer_init(struct drm_device *);
1096extern uint64_t nv04_timer_read(struct drm_device *);
1097extern void nv04_timer_takedown(struct drm_device *);
1098
1099extern long nouveau_compat_ioctl(struct file *file, unsigned int cmd,
1100 unsigned long arg);
1101
1102/* nv04_dac.c */
8f1a6086 1103extern int nv04_dac_create(struct drm_connector *, struct dcb_entry *);
11d6eb2a 1104extern uint32_t nv17_dac_sample_load(struct drm_encoder *encoder);
6ee73861
BS		 1105extern int nv04_dac_output_offset(struct drm_encoder *encoder);
1106extern void nv04_dac_update_dacclk(struct drm_encoder *encoder, bool enable);
8ccfe9e0 1107extern bool nv04_dac_in_use(struct drm_encoder *encoder);
6ee73861
BS		 1108
1109/* nv04_dfp.c */
8f1a6086 1110extern int nv04_dfp_create(struct drm_connector *, struct dcb_entry *);
6ee73861
BS		 1111extern int nv04_dfp_get_bound_head(struct drm_device *dev, struct dcb_entry *dcbent);
1112extern void nv04_dfp_bind_head(struct drm_device *dev, struct dcb_entry *dcbent,
1113 int head, bool dl);
1114extern void nv04_dfp_disable(struct drm_device *dev, int head);
1115extern void nv04_dfp_update_fp_control(struct drm_encoder *encoder, int mode);
1116
1117/* nv04_tv.c */
1118extern int nv04_tv_identify(struct drm_device *dev, int i2c_index);
8f1a6086 1119extern int nv04_tv_create(struct drm_connector *, struct dcb_entry *);
6ee73861
BS		 1120
1121/* nv17_tv.c */
8f1a6086 1122extern int nv17_tv_create(struct drm_connector *, struct dcb_entry *);
6ee73861
BS		 1123
1124/* nv04_display.c */
c88c2e06
FJ		 1125extern int nv04_display_early_init(struct drm_device *);
1126extern void nv04_display_late_takedown(struct drm_device *);
6ee73861 1127extern int nv04_display_create(struct drm_device *);
c88c2e06 1128extern int nv04_display_init(struct drm_device *);
6ee73861 1129extern void nv04_display_destroy(struct drm_device *);
6ee73861
BS		 1130
1131/* nv04_crtc.c */
1132extern int nv04_crtc_create(struct drm_device *, int index);
1133
1134/* nouveau_bo.c */
1135extern struct ttm_bo_driver nouveau_bo_driver;
1136extern int nouveau_bo_new(struct drm_device *, struct nouveau_channel *,
1137 int size, int align, uint32_t flags,
1138 uint32_t tile_mode, uint32_t tile_flags,
1139 bool no_vm, bool mappable, struct nouveau_bo **);
1140extern int nouveau_bo_pin(struct nouveau_bo *, uint32_t flags);
1141extern int nouveau_bo_unpin(struct nouveau_bo *);
1142extern int nouveau_bo_map(struct nouveau_bo *);
1143extern void nouveau_bo_unmap(struct nouveau_bo *);
78ad0f7b
FJ		 1144extern void nouveau_bo_placement_set(struct nouveau_bo *, uint32_t type,
1145 uint32_t busy);
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BS		 1146extern u16 nouveau_bo_rd16(struct nouveau_bo *nvbo, unsigned index);
1147extern void nouveau_bo_wr16(struct nouveau_bo *nvbo, unsigned index, u16 val);
1148extern u32 nouveau_bo_rd32(struct nouveau_bo *nvbo, unsigned index);
1149extern void nouveau_bo_wr32(struct nouveau_bo *nvbo, unsigned index, u32 val);
415e6186 1150extern int nouveau_bo_sync_gpu(struct nouveau_bo *, struct nouveau_channel *);
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BS		 1151
1152/* nouveau_fence.c */
1153struct nouveau_fence;
1154extern int nouveau_fence_init(struct nouveau_channel *);
1155extern void nouveau_fence_fini(struct nouveau_channel *);
1156extern void nouveau_fence_update(struct nouveau_channel *);
1157extern int nouveau_fence_new(struct nouveau_channel *, struct nouveau_fence **,
1158 bool emit);
1159extern int nouveau_fence_emit(struct nouveau_fence *);
1160struct nouveau_channel *nouveau_fence_channel(struct nouveau_fence *);
1161extern bool nouveau_fence_signalled(void *obj, void *arg);
1162extern int nouveau_fence_wait(void *obj, void *arg, bool lazy, bool intr);
1163extern int nouveau_fence_flush(void *obj, void *arg);
1164extern void nouveau_fence_unref(void **obj);
1165extern void *nouveau_fence_ref(void *obj);
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BS		 1166
1167/* nouveau_gem.c */
1168extern int nouveau_gem_new(struct drm_device *, struct nouveau_channel *,
1169 int size, int align, uint32_t flags,
1170 uint32_t tile_mode, uint32_t tile_flags,
1171 bool no_vm, bool mappable, struct nouveau_bo **);
1172extern int nouveau_gem_object_new(struct drm_gem_object *);
1173extern void nouveau_gem_object_del(struct drm_gem_object *);
1174extern int nouveau_gem_ioctl_new(struct drm_device *, void *,
1175 struct drm_file *);
1176extern int nouveau_gem_ioctl_pushbuf(struct drm_device *, void *,
1177 struct drm_file *);
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BS		 1178extern int nouveau_gem_ioctl_cpu_prep(struct drm_device *, void *,
1179 struct drm_file *);
1180extern int nouveau_gem_ioctl_cpu_fini(struct drm_device *, void *,
1181 struct drm_file *);
1182extern int nouveau_gem_ioctl_info(struct drm_device *, void *,
1183 struct drm_file *);
1184
ee2e0131
BS		 1185/* nv10_gpio.c */
1186int nv10_gpio_get(struct drm_device *dev, enum dcb_gpio_tag tag);
1187int nv10_gpio_set(struct drm_device *dev, enum dcb_gpio_tag tag, int state);
6ee73861 1188
45284162 1189/* nv50_gpio.c */
ee2e0131 1190int nv50_gpio_init(struct drm_device *dev);
45284162
BS		 1191int nv50_gpio_get(struct drm_device *dev, enum dcb_gpio_tag tag);
1192int nv50_gpio_set(struct drm_device *dev, enum dcb_gpio_tag tag, int state);
d0875edd 1193void nv50_gpio_irq_enable(struct drm_device *, enum dcb_gpio_tag, bool on);
45284162 1194
e9ebb68b
BS		 1195/* nv50_calc. */
1196int nv50_calc_pll(struct drm_device *, struct pll_lims *, int clk,
1197 int *N1, int *M1, int *N2, int *M2, int *P);
1198int nv50_calc_pll2(struct drm_device *, struct pll_lims *,
1199 int clk, int *N, int *fN, int *M, int *P);
1200
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BS		 1201#ifndef ioread32_native
1202#ifdef __BIG_ENDIAN
1203#define ioread16_native ioread16be
1204#define iowrite16_native iowrite16be
1205#define ioread32_native ioread32be
1206#define iowrite32_native iowrite32be
1207#else /* def __BIG_ENDIAN */
1208#define ioread16_native ioread16
1209#define iowrite16_native iowrite16
1210#define ioread32_native ioread32
1211#define iowrite32_native iowrite32
1212#endif /* def __BIG_ENDIAN else */
1213#endif /* !ioread32_native */
1214
1215/* channel control reg access */
1216static inline u32 nvchan_rd32(struct nouveau_channel *chan, unsigned reg)
1217{
1218 return ioread32_native(chan->user + reg);
1219}
1220
1221static inline void nvchan_wr32(struct nouveau_channel *chan,
1222 unsigned reg, u32 val)
1223{
1224 iowrite32_native(val, chan->user + reg);
1225}
1226
1227/* register access */
1228static inline u32 nv_rd32(struct drm_device *dev, unsigned reg)
1229{
1230 struct drm_nouveau_private *dev_priv = dev->dev_private;
1231 return ioread32_native(dev_priv->mmio + reg);
1232}
1233
1234static inline void nv_wr32(struct drm_device *dev, unsigned reg, u32 val)
1235{
1236 struct drm_nouveau_private *dev_priv = dev->dev_private;
1237 iowrite32_native(val, dev_priv->mmio + reg);
1238}
1239
2a7fdb2b 1240static inline u32 nv_mask(struct drm_device *dev, u32 reg, u32 mask, u32 val)
49eed80a
BS		 1241{
1242 u32 tmp = nv_rd32(dev, reg);
2a7fdb2b
BS		 1243 nv_wr32(dev, reg, (tmp & ~mask) | val);
1244 return tmp;
49eed80a
BS		 1245}
1246
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BS		 1247static inline u8 nv_rd08(struct drm_device *dev, unsigned reg)
1248{
1249 struct drm_nouveau_private *dev_priv = dev->dev_private;
1250 return ioread8(dev_priv->mmio + reg);
1251}
1252
1253static inline void nv_wr08(struct drm_device *dev, unsigned reg, u8 val)
1254{
1255 struct drm_nouveau_private *dev_priv = dev->dev_private;
1256 iowrite8(val, dev_priv->mmio + reg);
1257}
1258
1259#define nv_wait(reg, mask, val) \
1260 nouveau_wait_until(dev, 2000000000ULL, (reg), (mask), (val))
1261
1262/* PRAMIN access */
1263static inline u32 nv_ri32(struct drm_device *dev, unsigned offset)
1264{
1265 struct drm_nouveau_private *dev_priv = dev->dev_private;
1266 return ioread32_native(dev_priv->ramin + offset);
1267}
1268
1269static inline void nv_wi32(struct drm_device *dev, unsigned offset, u32 val)
1270{
1271 struct drm_nouveau_private *dev_priv = dev->dev_private;
1272 iowrite32_native(val, dev_priv->ramin + offset);
1273}
1274
1275/* object access */
b3beb167
BS		 1276extern u32 nv_ro32(struct nouveau_gpuobj *, u32 offset);
1277extern void nv_wo32(struct nouveau_gpuobj *, u32 offset, u32 val);
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BS		 1278
1279/*
1280 * Logging
1281 * Argument d is (struct drm_device *).
1282 */
1283#define NV_PRINTK(level, d, fmt, arg...) \
1284 printk(level "[" DRM_NAME "] " DRIVER_NAME " %s: " fmt, \
1285 pci_name(d->pdev), ##arg)
1286#ifndef NV_DEBUG_NOTRACE
1287#define NV_DEBUG(d, fmt, arg...) do { \
ef2bb506
MM		 1288 if (drm_debug & DRM_UT_DRIVER) { \
1289 NV_PRINTK(KERN_DEBUG, d, "%s:%d - " fmt, __func__, \
1290 __LINE__, ##arg); \
1291 } \
1292} while (0)
1293#define NV_DEBUG_KMS(d, fmt, arg...) do { \
1294 if (drm_debug & DRM_UT_KMS) { \
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BS		 1295 NV_PRINTK(KERN_DEBUG, d, "%s:%d - " fmt, __func__, \
1296 __LINE__, ##arg); \
1297 } \
1298} while (0)
1299#else
1300#define NV_DEBUG(d, fmt, arg...) do { \
ef2bb506
MM		 1301 if (drm_debug & DRM_UT_DRIVER) \
1302 NV_PRINTK(KERN_DEBUG, d, fmt, ##arg); \
1303} while (0)
1304#define NV_DEBUG_KMS(d, fmt, arg...) do { \
1305 if (drm_debug & DRM_UT_KMS) \
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BS		 1306 NV_PRINTK(KERN_DEBUG, d, fmt, ##arg); \
1307} while (0)
1308#endif
1309#define NV_ERROR(d, fmt, arg...) NV_PRINTK(KERN_ERR, d, fmt, ##arg)
1310#define NV_INFO(d, fmt, arg...) NV_PRINTK(KERN_INFO, d, fmt, ##arg)
1311#define NV_TRACEWARN(d, fmt, arg...) NV_PRINTK(KERN_NOTICE, d, fmt, ##arg)
1312#define NV_TRACE(d, fmt, arg...) NV_PRINTK(KERN_INFO, d, fmt, ##arg)
1313#define NV_WARN(d, fmt, arg...) NV_PRINTK(KERN_WARNING, d, fmt, ##arg)
1314
1315/* nouveau_reg_debug bitmask */
1316enum {
1317 NOUVEAU_REG_DEBUG_MC = 0x1,
1318 NOUVEAU_REG_DEBUG_VIDEO = 0x2,
1319 NOUVEAU_REG_DEBUG_FB = 0x4,
1320 NOUVEAU_REG_DEBUG_EXTDEV = 0x8,
1321 NOUVEAU_REG_DEBUG_CRTC = 0x10,
1322 NOUVEAU_REG_DEBUG_RAMDAC = 0x20,
1323 NOUVEAU_REG_DEBUG_VGACRTC = 0x40,
1324 NOUVEAU_REG_DEBUG_RMVIO = 0x80,
1325 NOUVEAU_REG_DEBUG_VGAATTR = 0x100,
1326 NOUVEAU_REG_DEBUG_EVO = 0x200,
1327};
1328
1329#define NV_REG_DEBUG(type, dev, fmt, arg...) do { \
1330 if (nouveau_reg_debug & NOUVEAU_REG_DEBUG_##type) \
1331 NV_PRINTK(KERN_DEBUG, dev, "%s: " fmt, __func__, ##arg); \
1332} while (0)
1333
1334static inline bool
1335nv_two_heads(struct drm_device *dev)
1336{
1337 struct drm_nouveau_private *dev_priv = dev->dev_private;
1338 const int impl = dev->pci_device & 0x0ff0;
1339
1340 if (dev_priv->card_type >= NV_10 && impl != 0x0100 &&
1341 impl != 0x0150 && impl != 0x01a0 && impl != 0x0200)
1342 return true;
1343
1344 return false;
1345}
1346
1347static inline bool
1348nv_gf4_disp_arch(struct drm_device *dev)
1349{
1350 return nv_two_heads(dev) && (dev->pci_device & 0x0ff0) != 0x0110;
1351}
1352
1353static inline bool
1354nv_two_reg_pll(struct drm_device *dev)
1355{
1356 struct drm_nouveau_private *dev_priv = dev->dev_private;
1357 const int impl = dev->pci_device & 0x0ff0;
1358
1359 if (impl == 0x0310 || impl == 0x0340 || dev_priv->card_type >= NV_40)
1360 return true;
1361 return false;
1362}
1363
acae116c
FJ		 1364static inline bool
1365nv_match_device(struct drm_device *dev, unsigned device,
1366 unsigned sub_vendor, unsigned sub_device)
1367{
1368 return dev->pdev->device == device &&
1369 dev->pdev->subsystem_vendor == sub_vendor &&
1370 dev->pdev->subsystem_device == sub_device;
1371}
1372
f03a314b
FJ		 1373#define NV_SW 0x0000506e
1374#define NV_SW_DMA_SEMAPHORE 0x00000060
1375#define NV_SW_SEMAPHORE_OFFSET 0x00000064
1376#define NV_SW_SEMAPHORE_ACQUIRE 0x00000068
1377#define NV_SW_SEMAPHORE_RELEASE 0x0000006c
1378#define NV_SW_DMA_VBLSEM 0x0000018c
1379#define NV_SW_VBLSEM_OFFSET 0x00000400
1380#define NV_SW_VBLSEM_RELEASE_VALUE 0x00000404
1381#define NV_SW_VBLSEM_RELEASE 0x00000408
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BS		 1382
1383#endif /* __NOUVEAU_DRV_H__ */
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