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drm/gf100-/gr: remove some broken ltc bashing, for now
[mirror_ubuntu-bionic-kernel.git] / drivers / gpu / drm / nouveau / nvif / class.h
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d01c3092
BS		 1#ifndef __NVIF_CLASS_H__
2#define __NVIF_CLASS_H__
3
4/*******************************************************************************
5 * class identifiers
6 ******************************************************************************/
7
8/* the below match nvidia-assigned (either in hw, or sw) class numbers */
9#define NV_DEVICE 0x00000080
10
4acfd707
BS		 11#define NV_DMA_FROM_MEMORY 0x00000002
12#define NV_DMA_TO_MEMORY 0x00000003
13#define NV_DMA_IN_MEMORY 0x0000003d
14
648d4dfd
BS		 15#define NV04_DISP 0x00000046
16
bbf8906b
BS		 17#define NV03_CHANNEL_DMA 0x0000006b
18#define NV10_CHANNEL_DMA 0x0000006e
19#define NV17_CHANNEL_DMA 0x0000176e
20#define NV40_CHANNEL_DMA 0x0000406e
21#define NV50_CHANNEL_DMA 0x0000506e
22#define G82_CHANNEL_DMA 0x0000826e
23
24#define NV50_CHANNEL_GPFIFO 0x0000506f
25#define G82_CHANNEL_GPFIFO 0x0000826f
26#define FERMI_CHANNEL_GPFIFO 0x0000906f
27#define KEPLER_CHANNEL_GPFIFO_A 0x0000a06f
28
648d4dfd
BS		 29#define NV50_DISP 0x00005070
30#define G82_DISP 0x00008270
31#define GT200_DISP 0x00008370
32#define GT214_DISP 0x00008570
33#define GT206_DISP 0x00008870
34#define GF110_DISP 0x00009070
35#define GK104_DISP 0x00009170
36#define GK110_DISP 0x00009270
37#define GM107_DISP 0x00009470
38
39#define NV50_DISP_CURSOR 0x0000507a
40#define G82_DISP_CURSOR 0x0000827a
41#define GT214_DISP_CURSOR 0x0000857a
42#define GF110_DISP_CURSOR 0x0000907a
43#define GK104_DISP_CURSOR 0x0000917a
44
45#define NV50_DISP_OVERLAY 0x0000507b
46#define G82_DISP_OVERLAY 0x0000827b
47#define GT214_DISP_OVERLAY 0x0000857b
48#define GF110_DISP_OVERLAY 0x0000907b
49#define GK104_DISP_OVERLAY 0x0000917b
50
51#define NV50_DISP_BASE_CHANNEL_DMA 0x0000507c
52#define G82_DISP_BASE_CHANNEL_DMA 0x0000827c
53#define GT200_DISP_BASE_CHANNEL_DMA 0x0000837c
54#define GT214_DISP_BASE_CHANNEL_DMA 0x0000857c
55#define GF110_DISP_BASE_CHANNEL_DMA 0x0000907c
56#define GK104_DISP_BASE_CHANNEL_DMA 0x0000917c
57#define GK110_DISP_BASE_CHANNEL_DMA 0x0000927c
58
59#define NV50_DISP_CORE_CHANNEL_DMA 0x0000507d
60#define G82_DISP_CORE_CHANNEL_DMA 0x0000827d
61#define GT200_DISP_CORE_CHANNEL_DMA 0x0000837d
62#define GT214_DISP_CORE_CHANNEL_DMA 0x0000857d
63#define GT206_DISP_CORE_CHANNEL_DMA 0x0000887d
64#define GF110_DISP_CORE_CHANNEL_DMA 0x0000907d
65#define GK104_DISP_CORE_CHANNEL_DMA 0x0000917d
66#define GK110_DISP_CORE_CHANNEL_DMA 0x0000927d
67#define GM107_DISP_CORE_CHANNEL_DMA 0x0000947d
68
69#define NV50_DISP_OVERLAY_CHANNEL_DMA 0x0000507e
70#define G82_DISP_OVERLAY_CHANNEL_DMA 0x0000827e
71#define GT200_DISP_OVERLAY_CHANNEL_DMA 0x0000837e
72#define GT214_DISP_OVERLAY_CHANNEL_DMA 0x0000857e
73#define GF110_DISP_OVERLAY_CONTROL_DMA 0x0000907e
74#define GK104_DISP_OVERLAY_CONTROL_DMA 0x0000917e
75
ac9738bb
BS		 76#define FERMI_A 0x00009097
77#define FERMI_B 0x00009197
78#define FERMI_C 0x00009297
79
80#define KEPLER_A 0x0000a097
81#define KEPLER_B 0x0000a197
82#define KEPLER_C 0x0000a297
83
84#define MAXWELL_A 0x0000b097
85
d01c3092 86
803c1787
BS		 87/*******************************************************************************
88 * client
89 ******************************************************************************/
90
91#define NV_CLIENT_DEVLIST 0x00
92
93struct nv_client_devlist_v0 {
94 __u8 version;
95 __u8 count;
96 __u8 pad02[6];
97 __u64 device[];
98};
99
100
d01c3092
BS		 101/*******************************************************************************
102 * device
103 ******************************************************************************/
104
586491e6
BS		 105struct nv_device_v0 {
106 __u8 version;
107 __u8 pad01[7];
108 __u64 device; /* device identifier, ~0 for client default */
109#define NV_DEVICE_V0_DISABLE_IDENTIFY 0x0000000000000001ULL
110#define NV_DEVICE_V0_DISABLE_MMIO 0x0000000000000002ULL
111#define NV_DEVICE_V0_DISABLE_VBIOS 0x0000000000000004ULL
112#define NV_DEVICE_V0_DISABLE_CORE 0x0000000000000008ULL
113#define NV_DEVICE_V0_DISABLE_DISP 0x0000000000010000ULL
114#define NV_DEVICE_V0_DISABLE_FIFO 0x0000000000020000ULL
115#define NV_DEVICE_V0_DISABLE_GRAPH 0x0000000100000000ULL
116#define NV_DEVICE_V0_DISABLE_MPEG 0x0000000200000000ULL
117#define NV_DEVICE_V0_DISABLE_ME 0x0000000400000000ULL
118#define NV_DEVICE_V0_DISABLE_VP 0x0000000800000000ULL
119#define NV_DEVICE_V0_DISABLE_CRYPT 0x0000001000000000ULL
120#define NV_DEVICE_V0_DISABLE_BSP 0x0000002000000000ULL
121#define NV_DEVICE_V0_DISABLE_PPP 0x0000004000000000ULL
122#define NV_DEVICE_V0_DISABLE_COPY0 0x0000008000000000ULL
123#define NV_DEVICE_V0_DISABLE_COPY1 0x0000010000000000ULL
124#define NV_DEVICE_V0_DISABLE_VIC 0x0000020000000000ULL
125#define NV_DEVICE_V0_DISABLE_VENC 0x0000040000000000ULL
126 __u64 disable; /* disable particular subsystems */
127 __u64 debug0; /* as above, but *internal* ids, and *NOT* ABI */
128};
129
d01c3092
BS		 130#define NV_DEVICE_V0_INFO 0x00
131
132struct nv_device_info_v0 {
133 __u8 version;
134#define NV_DEVICE_INFO_V0_IGP 0x00
135#define NV_DEVICE_INFO_V0_PCI 0x01
136#define NV_DEVICE_INFO_V0_AGP 0x02
137#define NV_DEVICE_INFO_V0_PCIE 0x03
138#define NV_DEVICE_INFO_V0_SOC 0x04
139 __u8 platform;
140 __u16 chipset; /* from NV_PMC_BOOT_0 */
141 __u8 revision; /* from NV_PMC_BOOT_0 */
142#define NV_DEVICE_INFO_V0_TNT 0x01
143#define NV_DEVICE_INFO_V0_CELSIUS 0x02
144#define NV_DEVICE_INFO_V0_KELVIN 0x03
145#define NV_DEVICE_INFO_V0_RANKINE 0x04
146#define NV_DEVICE_INFO_V0_CURIE 0x05
147#define NV_DEVICE_INFO_V0_TESLA 0x06
148#define NV_DEVICE_INFO_V0_FERMI 0x07
149#define NV_DEVICE_INFO_V0_KEPLER 0x08
150#define NV_DEVICE_INFO_V0_MAXWELL 0x09
151 __u8 family;
152 __u8 pad06[2];
153 __u64 ram_size;
154 __u64 ram_user;
155};
156
4acfd707
BS		 157
158/*******************************************************************************
159 * context dma
160 ******************************************************************************/
161
162struct nv_dma_v0 {
163 __u8 version;
164#define NV_DMA_V0_TARGET_VM 0x00
165#define NV_DMA_V0_TARGET_VRAM 0x01
166#define NV_DMA_V0_TARGET_PCI 0x02
167#define NV_DMA_V0_TARGET_PCI_US 0x03
168#define NV_DMA_V0_TARGET_AGP 0x04
169 __u8 target;
170#define NV_DMA_V0_ACCESS_VM 0x00
171#define NV_DMA_V0_ACCESS_RD 0x01
172#define NV_DMA_V0_ACCESS_WR 0x02
173#define NV_DMA_V0_ACCESS_RDWR (NV_DMA_V0_ACCESS_RD | NV_DMA_V0_ACCESS_WR)
174 __u8 access;
175 __u8 pad03[5];
176 __u64 start;
177 __u64 limit;
178 /* ... chipset-specific class data */
179};
180
181struct nv50_dma_v0 {
182 __u8 version;
183#define NV50_DMA_V0_PRIV_VM 0x00
184#define NV50_DMA_V0_PRIV_US 0x01
185#define NV50_DMA_V0_PRIV__S 0x02
186 __u8 priv;
187#define NV50_DMA_V0_PART_VM 0x00
188#define NV50_DMA_V0_PART_256 0x01
189#define NV50_DMA_V0_PART_1KB 0x02
190 __u8 part;
191#define NV50_DMA_V0_COMP_NONE 0x00
192#define NV50_DMA_V0_COMP_1 0x01
193#define NV50_DMA_V0_COMP_2 0x02
194#define NV50_DMA_V0_COMP_VM 0x03
195 __u8 comp;
196#define NV50_DMA_V0_KIND_PITCH 0x00
197#define NV50_DMA_V0_KIND_VM 0x7f
198 __u8 kind;
199 __u8 pad05[3];
200};
201
202struct gf100_dma_v0 {
203 __u8 version;
204#define GF100_DMA_V0_PRIV_VM 0x00
205#define GF100_DMA_V0_PRIV_US 0x01
206#define GF100_DMA_V0_PRIV__S 0x02
207 __u8 priv;
208#define GF100_DMA_V0_KIND_PITCH 0x00
209#define GF100_DMA_V0_KIND_VM 0xff
210 __u8 kind;
211 __u8 pad03[5];
212};
213
214struct gf110_dma_v0 {
215 __u8 version;
216#define GF110_DMA_V0_PAGE_LP 0x00
217#define GF110_DMA_V0_PAGE_SP 0x01
218 __u8 page;
219#define GF110_DMA_V0_KIND_PITCH 0x00
220#define GF110_DMA_V0_KIND_VM 0xff
221 __u8 kind;
222 __u8 pad03[5];
223};
224
96af8222
BS		 225
226/*******************************************************************************
227 * perfmon
228 ******************************************************************************/
229
230struct nvif_perfctr_v0 {
231 __u8 version;
232 __u8 pad01[1];
233 __u16 logic_op;
234 __u8 pad04[4];
235 char name[4][64];
236};
237
238#define NVIF_PERFCTR_V0_QUERY 0x00
239#define NVIF_PERFCTR_V0_SAMPLE 0x01
240#define NVIF_PERFCTR_V0_READ 0x02
241
242struct nvif_perfctr_query_v0 {
243 __u8 version;
244 __u8 pad01[3];
245 __u32 iter;
246 char name[64];
247};
248
249struct nvif_perfctr_sample {
250};
251
252struct nvif_perfctr_read_v0 {
253 __u8 version;
254 __u8 pad01[7];
255 __u32 ctr;
256 __u32 clk;
257};
258
a532da97
BS		 259
260/*******************************************************************************
261 * device control
262 ******************************************************************************/
263
264#define NVIF_CONTROL_PSTATE_INFO 0x00
265#define NVIF_CONTROL_PSTATE_ATTR 0x01
266#define NVIF_CONTROL_PSTATE_USER 0x02
267
268struct nvif_control_pstate_info_v0 {
269 __u8 version;
270 __u8 count; /* out: number of power states */
271#define NVIF_CONTROL_PSTATE_INFO_V0_USTATE_DISABLE (-1)
272#define NVIF_CONTROL_PSTATE_INFO_V0_USTATE_PERFMON (-2)
273 __s8 ustate_ac; /* out: target pstate index */
274 __s8 ustate_dc; /* out: target pstate index */
275 __s8 pwrsrc; /* out: current power source */
276#define NVIF_CONTROL_PSTATE_INFO_V0_PSTATE_UNKNOWN (-1)
277#define NVIF_CONTROL_PSTATE_INFO_V0_PSTATE_PERFMON (-2)
278 __s8 pstate; /* out: current pstate index */
279 __u8 pad06[2];
280};
281
282struct nvif_control_pstate_attr_v0 {
283 __u8 version;
284#define NVIF_CONTROL_PSTATE_ATTR_V0_STATE_CURRENT (-1)
285 __s8 state; /* in: index of pstate to query
286 * out: pstate identifier
287 */
288 __u8 index; /* in: index of attribute to query
289 * out: index of next attribute, or 0 if no more
290 */
291 __u8 pad03[5];
292 __u32 min;
293 __u32 max;
294 char name[32];
295 char unit[16];
296};
297
298struct nvif_control_pstate_user_v0 {
299 __u8 version;
300#define NVIF_CONTROL_PSTATE_USER_V0_STATE_UNKNOWN (-1)
301#define NVIF_CONTROL_PSTATE_USER_V0_STATE_PERFMON (-2)
302 __s8 ustate; /* in: pstate identifier */
303 __s8 pwrsrc; /* in: target power source */
304 __u8 pad03[5];
305};
306
bbf8906b
BS		 307
308/*******************************************************************************
309 * DMA FIFO channels
310 ******************************************************************************/
311
312struct nv03_channel_dma_v0 {
313 __u8 version;
314 __u8 chid;
315 __u8 pad02[2];
316 __u32 pushbuf;
317 __u64 offset;
318};
319
867920f8 320#define G82_CHANNEL_DMA_V0_NTFY_UEVENT 0x00
bbf8906b
BS		 321
322/*******************************************************************************
323 * GPFIFO channels
324 ******************************************************************************/
325
326struct nv50_channel_gpfifo_v0 {
327 __u8 version;
328 __u8 chid;
329 __u8 pad01[6];
330 __u32 pushbuf;
331 __u32 ilength;
332 __u64 ioffset;
333};
334
335struct kepler_channel_gpfifo_a_v0 {
336 __u8 version;
337#define KEPLER_CHANNEL_GPFIFO_A_V0_ENGINE_GR 0x01
338#define KEPLER_CHANNEL_GPFIFO_A_V0_ENGINE_VP 0x02
339#define KEPLER_CHANNEL_GPFIFO_A_V0_ENGINE_PPP 0x04
340#define KEPLER_CHANNEL_GPFIFO_A_V0_ENGINE_BSP 0x08
341#define KEPLER_CHANNEL_GPFIFO_A_V0_ENGINE_CE0 0x10
342#define KEPLER_CHANNEL_GPFIFO_A_V0_ENGINE_CE1 0x20
343#define KEPLER_CHANNEL_GPFIFO_A_V0_ENGINE_ENC 0x40
344 __u8 engine;
345 __u16 chid;
346 __u8 pad04[4];
347 __u32 pushbuf;
348 __u32 ilength;
349 __u64 ioffset;
350};
351
bf0eb898
BS		 352/*******************************************************************************
353 * legacy display
354 ******************************************************************************/
355
80bc340b
BS		 356#define NV04_DISP_NTFY_VBLANK 0x00
357#define NV04_DISP_NTFY_CONN 0x01
358
4952b4d3
BS		 359struct nv04_disp_mthd_v0 {
360 __u8 version;
361#define NV04_DISP_SCANOUTPOS 0x00
362 __u8 method;
363 __u8 head;
364 __u8 pad03[5];
365};
366
367struct nv04_disp_scanoutpos_v0 {
368 __u8 version;
369 __u8 pad01[7];
370 __s64 time[2];
371 __u16 vblanks;
372 __u16 vblanke;
373 __u16 vtotal;
374 __u16 vline;
375 __u16 hblanks;
376 __u16 hblanke;
377 __u16 htotal;
378 __u16 hline;
379};
380
bf0eb898
BS		 381/*******************************************************************************
382 * display
383 ******************************************************************************/
384
385#define NV50_DISP_MTHD 0x00
386
387struct nv50_disp_mthd_v0 {
388 __u8 version;
4952b4d3 389#define NV50_DISP_SCANOUTPOS 0x00
bf0eb898
BS		 390 __u8 method;
391 __u8 head;
392 __u8 pad03[5];
393};
394
395struct nv50_disp_mthd_v1 {
396 __u8 version;
397#define NV50_DISP_MTHD_V1_DAC_PWR 0x10
398#define NV50_DISP_MTHD_V1_DAC_LOAD 0x11
399#define NV50_DISP_MTHD_V1_SOR_PWR 0x20
400#define NV50_DISP_MTHD_V1_SOR_HDA_ELD 0x21
401#define NV50_DISP_MTHD_V1_SOR_HDMI_PWR 0x22
402#define NV50_DISP_MTHD_V1_SOR_LVDS_SCRIPT 0x23
403#define NV50_DISP_MTHD_V1_SOR_DP_PWR 0x24
404#define NV50_DISP_MTHD_V1_PIOR_PWR 0x30
405 __u8 method;
406 __u16 hasht;
407 __u16 hashm;
408 __u8 pad06[2];
409};
410
411struct nv50_disp_dac_pwr_v0 {
412 __u8 version;
413 __u8 state;
414 __u8 data;
415 __u8 vsync;
416 __u8 hsync;
417 __u8 pad05[3];
418};
419
c4abd317
BS		 420struct nv50_disp_dac_load_v0 {
421 __u8 version;
422 __u8 load;
423 __u16 data;
424 __u8 pad04[4];
425};
426
d55b4af9
BS		 427struct nv50_disp_sor_pwr_v0 {
428 __u8 version;
429 __u8 state;
430 __u8 pad02[6];
431};
432
120b0c39
BS		 433struct nv50_disp_sor_hda_eld_v0 {
434 __u8 version;
435 __u8 pad01[7];
436 __u8 data[];
437};
438
e00f2235
BS		 439struct nv50_disp_sor_hdmi_pwr_v0 {
440 __u8 version;
441 __u8 state;
442 __u8 max_ac_packet;
443 __u8 rekey;
444 __u8 pad04[4];
445};
446
a3761fa2
BS		 447struct nv50_disp_sor_lvds_script_v0 {
448 __u8 version;
449 __u8 pad01[1];
450 __u16 script;
451 __u8 pad04[4];
452};
453
c02ed2bf
BS		 454struct nv50_disp_sor_dp_pwr_v0 {
455 __u8 version;
456 __u8 state;
457 __u8 pad02[6];
458};
459
67cb49c4
BS		 460struct nv50_disp_pior_pwr_v0 {
461 __u8 version;
462 __u8 state;
463 __u8 type;
464 __u8 pad03[5];
465};
466
648d4dfd
BS		 467/* core */
468struct nv50_disp_core_channel_dma_v0 {
469 __u8 version;
470 __u8 pad01[3];
471 __u32 pushbuf;
472};
473
474/* cursor immediate */
475struct nv50_disp_cursor_v0 {
476 __u8 version;
477 __u8 head;
478 __u8 pad02[6];
479};
480
481/* base */
482struct nv50_disp_base_channel_dma_v0 {
483 __u8 version;
484 __u8 pad01[2];
485 __u8 head;
486 __u32 pushbuf;
487};
488
489/* overlay */
490struct nv50_disp_overlay_channel_dma_v0 {
491 __u8 version;
492 __u8 pad01[2];
493 __u8 head;
494 __u32 pushbuf;
495};
496
497/* overlay immediate */
498struct nv50_disp_overlay_v0 {
499 __u8 version;
500 __u8 head;
501 __u8 pad02[6];
502};
503
ac9738bb
BS		 504
505/*******************************************************************************
506 * fermi
507 ******************************************************************************/
508
509#define FERMI_A_ZBC_COLOR 0x00
510#define FERMI_A_ZBC_DEPTH 0x01
511
512struct fermi_a_zbc_color_v0 {
513 __u8 version;
514#define FERMI_A_ZBC_COLOR_V0_FMT_ZERO 0x01
515#define FERMI_A_ZBC_COLOR_V0_FMT_UNORM_ONE 0x02
516#define FERMI_A_ZBC_COLOR_V0_FMT_RF32_GF32_BF32_AF32 0x04
517#define FERMI_A_ZBC_COLOR_V0_FMT_R16_G16_B16_A16 0x08
518#define FERMI_A_ZBC_COLOR_V0_FMT_RN16_GN16_BN16_AN16 0x0c
519#define FERMI_A_ZBC_COLOR_V0_FMT_RS16_GS16_BS16_AS16 0x10
520#define FERMI_A_ZBC_COLOR_V0_FMT_RU16_GU16_BU16_AU16 0x14
521#define FERMI_A_ZBC_COLOR_V0_FMT_RF16_GF16_BF16_AF16 0x16
522#define FERMI_A_ZBC_COLOR_V0_FMT_A8R8G8B8 0x18
523#define FERMI_A_ZBC_COLOR_V0_FMT_A8RL8GL8BL8 0x1c
524#define FERMI_A_ZBC_COLOR_V0_FMT_A2B10G10R10 0x20
525#define FERMI_A_ZBC_COLOR_V0_FMT_AU2BU10GU10RU10 0x24
526#define FERMI_A_ZBC_COLOR_V0_FMT_A8B8G8R8 0x28
527#define FERMI_A_ZBC_COLOR_V0_FMT_A8BL8GL8RL8 0x2c
528#define FERMI_A_ZBC_COLOR_V0_FMT_AN8BN8GN8RN8 0x30
529#define FERMI_A_ZBC_COLOR_V0_FMT_AS8BS8GS8RS8 0x34
530#define FERMI_A_ZBC_COLOR_V0_FMT_AU8BU8GU8RU8 0x38
531#define FERMI_A_ZBC_COLOR_V0_FMT_A2R10G10B10 0x3c
532#define FERMI_A_ZBC_COLOR_V0_FMT_BF10GF11RF11 0x40
533 __u8 format;
534 __u8 index;
535 __u8 pad03[5];
536 __u32 ds[4];
537 __u32 l2[4];
538};
539
540struct fermi_a_zbc_depth_v0 {
541 __u8 version;
542#define FERMI_A_ZBC_DEPTH_V0_FMT_FP32 0x01
543 __u8 format;
544 __u8 index;
545 __u8 pad03[5];
546 __u32 ds;
547 __u32 l2;
548};
549
d01c3092 550#endif
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