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drm/radeon/kms: add dynamic engine reclocking (V9)
[mirror_ubuntu-artful-kernel.git] / drivers / gpu / drm / radeon / radeon.h
CommitLineData
771fe6b9
JG		 1/*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 * Jerome Glisse
27 */
28#ifndef __RADEON_H__
29#define __RADEON_H__
30
771fe6b9
JG		 31/* TODO: Here are things that needs to be done :
32 * - surface allocator & initializer : (bit like scratch reg) should
33 * initialize HDP_ stuff on RS600, R600, R700 hw, well anythings
34 * related to surface
35 * - WB : write back stuff (do it bit like scratch reg things)
36 * - Vblank : look at Jesse's rework and what we should do
37 * - r600/r700: gart & cp
38 * - cs : clean cs ioctl use bitmap & things like that.
39 * - power management stuff
40 * - Barrier in gart code
41 * - Unmappabled vram ?
42 * - TESTING, TESTING, TESTING
43 */
44
d39c3b89
JG		 45/* Initialization path:
46 * We expect that acceleration initialization might fail for various
47 * reasons even thought we work hard to make it works on most
48 * configurations. In order to still have a working userspace in such
49 * situation the init path must succeed up to the memory controller
50 * initialization point. Failure before this point are considered as
51 * fatal error. Here is the init callchain :
52 * radeon_device_init perform common structure, mutex initialization
53 * asic_init setup the GPU memory layout and perform all
54 * one time initialization (failure in this
55 * function are considered fatal)
56 * asic_startup setup the GPU acceleration, in order to
57 * follow guideline the first thing this
58 * function should do is setting the GPU
59 * memory controller (only MC setup failure
60 * are considered as fatal)
61 */
62
771fe6b9
JG		 63#include <asm/atomic.h>
64#include <linux/wait.h>
65#include <linux/list.h>
66#include <linux/kref.h>
67
4c788679
JG		 68#include <ttm/ttm_bo_api.h>
69#include <ttm/ttm_bo_driver.h>
70#include <ttm/ttm_placement.h>
71#include <ttm/ttm_module.h>
72
c2142715 73#include "radeon_family.h"
771fe6b9
JG		 74#include "radeon_mode.h"
75#include "radeon_reg.h"
771fe6b9
JG		 76
77/*
78 * Modules parameters.
79 */
80extern int radeon_no_wb;
81extern int radeon_modeset;
82extern int radeon_dynclks;
83extern int radeon_r4xx_atom;
84extern int radeon_agpmode;
85extern int radeon_vram_limit;
86extern int radeon_gart_size;
87extern int radeon_benchmarking;
ecc0b326 88extern int radeon_testing;
771fe6b9 89extern int radeon_connector_table;
4ce001ab 90extern int radeon_tv;
b27b6375 91extern int radeon_new_pll;
c913e23a 92extern int radeon_dynpm;
dafc3bd5 93extern int radeon_audio;
771fe6b9
JG		 94
95/*
96 * Copy from radeon_drv.h so we don't have to include both and have conflicting
97 * symbol;
98 */
99#define RADEON_MAX_USEC_TIMEOUT 100000 /* 100 ms */
100#define RADEON_IB_POOL_SIZE 16
101#define RADEON_DEBUGFS_MAX_NUM_FILES 32
102#define RADEONFB_CONN_LIMIT 4
f657c2a7 103#define RADEON_BIOS_NUM_SCRATCH 8
771fe6b9 104
771fe6b9
JG		 105/*
106 * Errata workarounds.
107 */
108enum radeon_pll_errata {
109 CHIP_ERRATA_R300_CG = 0x00000001,
110 CHIP_ERRATA_PLL_DUMMYREADS = 0x00000002,
111 CHIP_ERRATA_PLL_DELAY = 0x00000004
112};
113
114
115struct radeon_device;
116
117
118/*
119 * BIOS.
120 */
121bool radeon_get_bios(struct radeon_device *rdev);
122
3ce0a23d 123
771fe6b9 124/*
3ce0a23d 125 * Dummy page
771fe6b9 126 */
3ce0a23d
JG		 127struct radeon_dummy_page {
128 struct page *page;
129 dma_addr_t addr;
130};
131int radeon_dummy_page_init(struct radeon_device *rdev);
132void radeon_dummy_page_fini(struct radeon_device *rdev);
133
771fe6b9 134
3ce0a23d
JG		 135/*
136 * Clocks
137 */
771fe6b9
JG		 138struct radeon_clock {
139 struct radeon_pll p1pll;
140 struct radeon_pll p2pll;
141 struct radeon_pll spll;
142 struct radeon_pll mpll;
143 /* 10 Khz units */
144 uint32_t default_mclk;
145 uint32_t default_sclk;
146};
147
7433874e
RM		 148/*
149 * Power management
150 */
151int radeon_pm_init(struct radeon_device *rdev);
c913e23a 152void radeon_pm_compute_clocks(struct radeon_device *rdev);
3ce0a23d 153
771fe6b9
JG		 154/*
155 * Fences.
156 */
157struct radeon_fence_driver {
158 uint32_t scratch_reg;
159 atomic_t seq;
160 uint32_t last_seq;
161 unsigned long count_timeout;
162 wait_queue_head_t queue;
163 rwlock_t lock;
164 struct list_head created;
165 struct list_head emited;
166 struct list_head signaled;
0a0c7596 167 bool initialized;
771fe6b9
JG		 168};
169
170struct radeon_fence {
171 struct radeon_device *rdev;
172 struct kref kref;
173 struct list_head list;
174 /* protected by radeon_fence.lock */
175 uint32_t seq;
176 unsigned long timeout;
177 bool emited;
178 bool signaled;
179};
180
181int radeon_fence_driver_init(struct radeon_device *rdev);
182void radeon_fence_driver_fini(struct radeon_device *rdev);
183int radeon_fence_create(struct radeon_device *rdev, struct radeon_fence **fence);
184int radeon_fence_emit(struct radeon_device *rdev, struct radeon_fence *fence);
185void radeon_fence_process(struct radeon_device *rdev);
186bool radeon_fence_signaled(struct radeon_fence *fence);
187int radeon_fence_wait(struct radeon_fence *fence, bool interruptible);
188int radeon_fence_wait_next(struct radeon_device *rdev);
189int radeon_fence_wait_last(struct radeon_device *rdev);
190struct radeon_fence *radeon_fence_ref(struct radeon_fence *fence);
191void radeon_fence_unref(struct radeon_fence **fence);
192
e024e110
DA		 193/*
194 * Tiling registers
195 */
196struct radeon_surface_reg {
4c788679 197 struct radeon_bo *bo;
e024e110
DA		 198};
199
200#define RADEON_GEM_MAX_SURFACES 8
771fe6b9
JG		 201
202/*
4c788679 203 * TTM.
771fe6b9 204 */
4c788679
JG		 205struct radeon_mman {
206 struct ttm_bo_global_ref bo_global_ref;
207 struct ttm_global_reference mem_global_ref;
4c788679 208 struct ttm_bo_device bdev;
0a0c7596
JG		 209 bool mem_global_referenced;
210 bool initialized;
4c788679
JG		 211};
212
213struct radeon_bo {
214 /* Protected by gem.mutex */
215 struct list_head list;
216 /* Protected by tbo.reserved */
312ea8da
JG		 217 u32 placements[3];
218 struct ttm_placement placement;
4c788679
JG		 219 struct ttm_buffer_object tbo;
220 struct ttm_bo_kmap_obj kmap;
221 unsigned pin_count;
222 void *kptr;
223 u32 tiling_flags;
224 u32 pitch;
225 int surface_reg;
226 /* Constant after initialization */
227 struct radeon_device *rdev;
228 struct drm_gem_object *gobj;
229};
771fe6b9 230
4c788679 231struct radeon_bo_list {
771fe6b9 232 struct list_head list;
4c788679 233 struct radeon_bo *bo;
771fe6b9
JG		 234 uint64_t gpu_offset;
235 unsigned rdomain;
236 unsigned wdomain;
4c788679 237 u32 tiling_flags;
771fe6b9
JG		 238};
239
771fe6b9
JG		 240/*
241 * GEM objects.
242 */
243struct radeon_gem {
4c788679 244 struct mutex mutex;
771fe6b9
JG		 245 struct list_head objects;
246};
247
248int radeon_gem_init(struct radeon_device *rdev);
249void radeon_gem_fini(struct radeon_device *rdev);
250int radeon_gem_object_create(struct radeon_device *rdev, int size,
4c788679
JG		 251 int alignment, int initial_domain,
252 bool discardable, bool kernel,
253 struct drm_gem_object **obj);
771fe6b9
JG		 254int radeon_gem_object_pin(struct drm_gem_object *obj, uint32_t pin_domain,
255 uint64_t *gpu_addr);
256void radeon_gem_object_unpin(struct drm_gem_object *obj);
257
258
259/*
260 * GART structures, functions & helpers
261 */
262struct radeon_mc;
263
264struct radeon_gart_table_ram {
265 volatile uint32_t *ptr;
266};
267
268struct radeon_gart_table_vram {
4c788679 269 struct radeon_bo *robj;
771fe6b9
JG		 270 volatile uint32_t *ptr;
271};
272
273union radeon_gart_table {
274 struct radeon_gart_table_ram ram;
275 struct radeon_gart_table_vram vram;
276};
277
a77f1718
MT		 278#define RADEON_GPU_PAGE_SIZE 4096
279
771fe6b9
JG		 280struct radeon_gart {
281 dma_addr_t table_addr;
282 unsigned num_gpu_pages;
283 unsigned num_cpu_pages;
284 unsigned table_size;
285 union radeon_gart_table table;
286 struct page **pages;
287 dma_addr_t *pages_addr;
288 bool ready;
289};
290
291int radeon_gart_table_ram_alloc(struct radeon_device *rdev);
292void radeon_gart_table_ram_free(struct radeon_device *rdev);
293int radeon_gart_table_vram_alloc(struct radeon_device *rdev);
294void radeon_gart_table_vram_free(struct radeon_device *rdev);
295int radeon_gart_init(struct radeon_device *rdev);
296void radeon_gart_fini(struct radeon_device *rdev);
297void radeon_gart_unbind(struct radeon_device *rdev, unsigned offset,
298 int pages);
299int radeon_gart_bind(struct radeon_device *rdev, unsigned offset,
300 int pages, struct page **pagelist);
301
302
303/*
304 * GPU MC structures, functions & helpers
305 */
306struct radeon_mc {
307 resource_size_t aper_size;
308 resource_size_t aper_base;
309 resource_size_t agp_base;
7a50f01a
DA		 310 /* for some chips with <= 32MB we need to lie
311 * about vram size near mc fb location */
3ce0a23d
JG		 312 u64 mc_vram_size;
313 u64 gtt_location;
314 u64 gtt_size;
315 u64 gtt_start;
316 u64 gtt_end;
317 u64 vram_location;
318 u64 vram_start;
319 u64 vram_end;
771fe6b9 320 unsigned vram_width;
3ce0a23d 321 u64 real_vram_size;
771fe6b9
JG		 322 int vram_mtrr;
323 bool vram_is_ddr;
06b6476d 324 bool igp_sideport_enabled;
771fe6b9
JG		 325};
326
327int radeon_mc_setup(struct radeon_device *rdev);
06b6476d
AD		 328bool radeon_combios_sideport_present(struct radeon_device *rdev);
329bool radeon_atombios_sideport_present(struct radeon_device *rdev);
771fe6b9
JG		 330
331/*
332 * GPU scratch registers structures, functions & helpers
333 */
334struct radeon_scratch {
335 unsigned num_reg;
336 bool free[32];
337 uint32_t reg[32];
338};
339
340int radeon_scratch_get(struct radeon_device *rdev, uint32_t *reg);
341void radeon_scratch_free(struct radeon_device *rdev, uint32_t reg);
342
343
344/*
345 * IRQS.
346 */
347struct radeon_irq {
348 bool installed;
349 bool sw_int;
350 /* FIXME: use a define max crtc rather than hardcode it */
351 bool crtc_vblank_int[2];
b500f680
AD		 352 /* FIXME: use defines for max hpd/dacs */
353 bool hpd[6];
1614f8b1
DA		 354 spinlock_t sw_lock;
355 int sw_refcount;
771fe6b9
JG		 356};
357
358int radeon_irq_kms_init(struct radeon_device *rdev);
359void radeon_irq_kms_fini(struct radeon_device *rdev);
1614f8b1
DA		 360void radeon_irq_kms_sw_irq_get(struct radeon_device *rdev);
361void radeon_irq_kms_sw_irq_put(struct radeon_device *rdev);
771fe6b9
JG		 362
363/*
364 * CP & ring.
365 */
366struct radeon_ib {
367 struct list_head list;
368 unsigned long idx;
369 uint64_t gpu_addr;
370 struct radeon_fence *fence;
513bcb46 371 uint32_t *ptr;
771fe6b9
JG		 372 uint32_t length_dw;
373};
374
ecb114a1
DA		 375/*
376 * locking -
377 * mutex protects scheduled_ibs, ready, alloc_bm
378 */
771fe6b9
JG		 379struct radeon_ib_pool {
380 struct mutex mutex;
4c788679 381 struct radeon_bo *robj;
771fe6b9
JG		 382 struct list_head scheduled_ibs;
383 struct radeon_ib ibs[RADEON_IB_POOL_SIZE];
384 bool ready;
385 DECLARE_BITMAP(alloc_bm, RADEON_IB_POOL_SIZE);
386};
387
388struct radeon_cp {
4c788679 389 struct radeon_bo *ring_obj;
771fe6b9
JG		 390 volatile uint32_t *ring;
391 unsigned rptr;
392 unsigned wptr;
393 unsigned wptr_old;
394 unsigned ring_size;
395 unsigned ring_free_dw;
396 int count_dw;
397 uint64_t gpu_addr;
398 uint32_t align_mask;
399 uint32_t ptr_mask;
400 struct mutex mutex;
401 bool ready;
402};
403
d8f60cfc
AD		 404/*
405 * R6xx+ IH ring
406 */
407struct r600_ih {
4c788679 408 struct radeon_bo *ring_obj;
d8f60cfc
AD		 409 volatile uint32_t *ring;
410 unsigned rptr;
411 unsigned wptr;
412 unsigned wptr_old;
413 unsigned ring_size;
414 uint64_t gpu_addr;
d8f60cfc
AD		 415 uint32_t ptr_mask;
416 spinlock_t lock;
417 bool enabled;
418};
419
3ce0a23d 420struct r600_blit {
ff82f052 421 struct mutex mutex;
4c788679 422 struct radeon_bo *shader_obj;
3ce0a23d
JG		 423 u64 shader_gpu_addr;
424 u32 vs_offset, ps_offset;
425 u32 state_offset;
426 u32 state_len;
427 u32 vb_used, vb_total;
428 struct radeon_ib *vb_ib;
429};
430
771fe6b9
JG		 431int radeon_ib_get(struct radeon_device *rdev, struct radeon_ib **ib);
432void radeon_ib_free(struct radeon_device *rdev, struct radeon_ib **ib);
433int radeon_ib_schedule(struct radeon_device *rdev, struct radeon_ib *ib);
434int radeon_ib_pool_init(struct radeon_device *rdev);
435void radeon_ib_pool_fini(struct radeon_device *rdev);
436int radeon_ib_test(struct radeon_device *rdev);
437/* Ring access between begin & end cannot sleep */
438void radeon_ring_free_size(struct radeon_device *rdev);
439int radeon_ring_lock(struct radeon_device *rdev, unsigned ndw);
440void radeon_ring_unlock_commit(struct radeon_device *rdev);
441void radeon_ring_unlock_undo(struct radeon_device *rdev);
442int radeon_ring_test(struct radeon_device *rdev);
443int radeon_ring_init(struct radeon_device *rdev, unsigned ring_size);
444void radeon_ring_fini(struct radeon_device *rdev);
445
446
447/*
448 * CS.
449 */
450struct radeon_cs_reloc {
451 struct drm_gem_object *gobj;
4c788679
JG		 452 struct radeon_bo *robj;
453 struct radeon_bo_list lobj;
771fe6b9
JG		 454 uint32_t handle;
455 uint32_t flags;
456};
457
458struct radeon_cs_chunk {
459 uint32_t chunk_id;
460 uint32_t length_dw;
513bcb46
DA		 461 int kpage_idx[2];
462 uint32_t *kpage[2];
771fe6b9 463 uint32_t *kdata;
513bcb46
DA		 464 void __user *user_ptr;
465 int last_copied_page;
466 int last_page_index;
771fe6b9
JG		 467};
468
469struct radeon_cs_parser {
c8c15ff1 470 struct device *dev;
771fe6b9
JG		 471 struct radeon_device *rdev;
472 struct drm_file *filp;
473 /* chunks */
474 unsigned nchunks;
475 struct radeon_cs_chunk *chunks;
476 uint64_t *chunks_array;
477 /* IB */
478 unsigned idx;
479 /* relocations */
480 unsigned nrelocs;
481 struct radeon_cs_reloc *relocs;
482 struct radeon_cs_reloc **relocs_ptr;
483 struct list_head validated;
484 /* indices of various chunks */
485 int chunk_ib_idx;
486 int chunk_relocs_idx;
487 struct radeon_ib *ib;
488 void *track;
3ce0a23d 489 unsigned family;
513bcb46 490 int parser_error;
771fe6b9
JG		 491};
492
513bcb46
DA		 493extern int radeon_cs_update_pages(struct radeon_cs_parser *p, int pg_idx);
494extern int radeon_cs_finish_pages(struct radeon_cs_parser *p);
495
496
497static inline u32 radeon_get_ib_value(struct radeon_cs_parser *p, int idx)
498{
499 struct radeon_cs_chunk *ibc = &p->chunks[p->chunk_ib_idx];
500 u32 pg_idx, pg_offset;
501 u32 idx_value = 0;
502 int new_page;
503
504 pg_idx = (idx * 4) / PAGE_SIZE;
505 pg_offset = (idx * 4) % PAGE_SIZE;
506
507 if (ibc->kpage_idx[0] == pg_idx)
508 return ibc->kpage[0][pg_offset/4];
509 if (ibc->kpage_idx[1] == pg_idx)
510 return ibc->kpage[1][pg_offset/4];
511
512 new_page = radeon_cs_update_pages(p, pg_idx);
513 if (new_page < 0) {
514 p->parser_error = new_page;
515 return 0;
516 }
517
518 idx_value = ibc->kpage[new_page][pg_offset/4];
519 return idx_value;
520}
521
771fe6b9
JG		 522struct radeon_cs_packet {
523 unsigned idx;
524 unsigned type;
525 unsigned reg;
526 unsigned opcode;
527 int count;
528 unsigned one_reg_wr;
529};
530
531typedef int (*radeon_packet0_check_t)(struct radeon_cs_parser *p,
532 struct radeon_cs_packet *pkt,
533 unsigned idx, unsigned reg);
534typedef int (*radeon_packet3_check_t)(struct radeon_cs_parser *p,
535 struct radeon_cs_packet *pkt);
536
537
538/*
539 * AGP
540 */
541int radeon_agp_init(struct radeon_device *rdev);
0ebf1717 542void radeon_agp_resume(struct radeon_device *rdev);
771fe6b9
JG		 543void radeon_agp_fini(struct radeon_device *rdev);
544
545
546/*
547 * Writeback
548 */
549struct radeon_wb {
4c788679 550 struct radeon_bo *wb_obj;
771fe6b9
JG		 551 volatile uint32_t *wb;
552 uint64_t gpu_addr;
553};
554
c93bb85b
JG		 555/**
556 * struct radeon_pm - power management datas
557 * @max_bandwidth: maximum bandwidth the gpu has (MByte/s)
558 * @igp_sideport_mclk: sideport memory clock Mhz (rs690,rs740,rs780,rs880)
559 * @igp_system_mclk: system clock Mhz (rs690,rs740,rs780,rs880)
560 * @igp_ht_link_clk: ht link clock Mhz (rs690,rs740,rs780,rs880)
561 * @igp_ht_link_width: ht link width in bits (rs690,rs740,rs780,rs880)
562 * @k8_bandwidth: k8 bandwidth the gpu has (MByte/s) (IGP)
563 * @sideport_bandwidth: sideport bandwidth the gpu has (MByte/s) (IGP)
564 * @ht_bandwidth: ht bandwidth the gpu has (MByte/s) (IGP)
565 * @core_bandwidth: core GPU bandwidth the gpu has (MByte/s) (IGP)
566 * @sclk: GPU clock Mhz (core bandwith depends of this clock)
567 * @needed_bandwidth: current bandwidth needs
568 *
569 * It keeps track of various data needed to take powermanagement decision.
570 * Bandwith need is used to determine minimun clock of the GPU and memory.
571 * Equation between gpu/memory clock and available bandwidth is hw dependent
572 * (type of memory, bus size, efficiency, ...)
573 */
c913e23a
RM		 574enum radeon_pm_state {
575 PM_STATE_DISABLED,
576 PM_STATE_MINIMUM,
577 PM_STATE_PAUSED,
578 PM_STATE_ACTIVE
579};
580enum radeon_pm_action {
581 PM_ACTION_NONE,
582 PM_ACTION_MINIMUM,
583 PM_ACTION_DOWNCLOCK,
584 PM_ACTION_UPCLOCK
585};
c93bb85b 586struct radeon_pm {
c913e23a
RM		 587 struct mutex mutex;
588 struct work_struct reclock_work;
589 struct delayed_work idle_work;
590 enum radeon_pm_state state;
591 enum radeon_pm_action planned_action;
592 unsigned long action_timeout;
593 bool downclocked;
594 bool vblank_callback;
595 int active_crtcs;
596 int req_vblank;
597 uint32_t min_gpu_engine_clock;
598 uint32_t min_gpu_memory_clock;
599 uint32_t min_mode_engine_clock;
600 uint32_t min_mode_memory_clock;
c93bb85b
JG		 601 fixed20_12 max_bandwidth;
602 fixed20_12 igp_sideport_mclk;
603 fixed20_12 igp_system_mclk;
604 fixed20_12 igp_ht_link_clk;
605 fixed20_12 igp_ht_link_width;
606 fixed20_12 k8_bandwidth;
607 fixed20_12 sideport_bandwidth;
608 fixed20_12 ht_bandwidth;
609 fixed20_12 core_bandwidth;
610 fixed20_12 sclk;
611 fixed20_12 needed_bandwidth;
612};
613
771fe6b9
JG		 614
615/*
616 * Benchmarking
617 */
618void radeon_benchmark(struct radeon_device *rdev);
619
620
ecc0b326
MD		 621/*
622 * Testing
623 */
624void radeon_test_moves(struct radeon_device *rdev);
625
626
771fe6b9
JG		 627/*
628 * Debugfs
629 */
630int radeon_debugfs_add_files(struct radeon_device *rdev,
631 struct drm_info_list *files,
632 unsigned nfiles);
633int radeon_debugfs_fence_init(struct radeon_device *rdev);
634int r100_debugfs_rbbm_init(struct radeon_device *rdev);
635int r100_debugfs_cp_init(struct radeon_device *rdev);
636
637
638/*
639 * ASIC specific functions.
640 */
641struct radeon_asic {
068a117c 642 int (*init)(struct radeon_device *rdev);
3ce0a23d
JG		 643 void (*fini)(struct radeon_device *rdev);
644 int (*resume)(struct radeon_device *rdev);
645 int (*suspend)(struct radeon_device *rdev);
28d52043 646 void (*vga_set_state)(struct radeon_device *rdev, bool state);
771fe6b9 647 int (*gpu_reset)(struct radeon_device *rdev);
771fe6b9
JG		 648 void (*gart_tlb_flush)(struct radeon_device *rdev);
649 int (*gart_set_page)(struct radeon_device *rdev, int i, uint64_t addr);
650 int (*cp_init)(struct radeon_device *rdev, unsigned ring_size);
651 void (*cp_fini)(struct radeon_device *rdev);
652 void (*cp_disable)(struct radeon_device *rdev);
3ce0a23d 653 void (*cp_commit)(struct radeon_device *rdev);
771fe6b9 654 void (*ring_start)(struct radeon_device *rdev);
3ce0a23d
JG		 655 int (*ring_test)(struct radeon_device *rdev);
656 void (*ring_ib_execute)(struct radeon_device *rdev, struct radeon_ib *ib);
771fe6b9
JG		 657 int (*irq_set)(struct radeon_device *rdev);
658 int (*irq_process)(struct radeon_device *rdev);
7ed220d7 659 u32 (*get_vblank_counter)(struct radeon_device *rdev, int crtc);
771fe6b9
JG		 660 void (*fence_ring_emit)(struct radeon_device *rdev, struct radeon_fence *fence);
661 int (*cs_parse)(struct radeon_cs_parser *p);
662 int (*copy_blit)(struct radeon_device *rdev,
663 uint64_t src_offset,
664 uint64_t dst_offset,
665 unsigned num_pages,
666 struct radeon_fence *fence);
667 int (*copy_dma)(struct radeon_device *rdev,
668 uint64_t src_offset,
669 uint64_t dst_offset,
670 unsigned num_pages,
671 struct radeon_fence *fence);
672 int (*copy)(struct radeon_device *rdev,
673 uint64_t src_offset,
674 uint64_t dst_offset,
675 unsigned num_pages,
676 struct radeon_fence *fence);
7433874e 677 uint32_t (*get_engine_clock)(struct radeon_device *rdev);
771fe6b9 678 void (*set_engine_clock)(struct radeon_device *rdev, uint32_t eng_clock);
7433874e 679 uint32_t (*get_memory_clock)(struct radeon_device *rdev);
771fe6b9
JG		 680 void (*set_memory_clock)(struct radeon_device *rdev, uint32_t mem_clock);
681 void (*set_pcie_lanes)(struct radeon_device *rdev, int lanes);
682 void (*set_clock_gating)(struct radeon_device *rdev, int enable);
e024e110
DA		 683 int (*set_surface_reg)(struct radeon_device *rdev, int reg,
684 uint32_t tiling_flags, uint32_t pitch,
685 uint32_t offset, uint32_t obj_size);
686 int (*clear_surface_reg)(struct radeon_device *rdev, int reg);
c93bb85b 687 void (*bandwidth_update)(struct radeon_device *rdev);
429770b3
AD		 688 void (*hpd_init)(struct radeon_device *rdev);
689 void (*hpd_fini)(struct radeon_device *rdev);
690 bool (*hpd_sense)(struct radeon_device *rdev, enum radeon_hpd_id hpd);
691 void (*hpd_set_polarity)(struct radeon_device *rdev, enum radeon_hpd_id hpd);
062b389c
JG		 692 /* ioctl hw specific callback. Some hw might want to perform special
693 * operation on specific ioctl. For instance on wait idle some hw
694 * might want to perform and HDP flush through MMIO as it seems that
695 * some R6XX/R7XX hw doesn't take HDP flush into account if programmed
696 * through ring.
697 */
698 void (*ioctl_wait_idle)(struct radeon_device *rdev, struct radeon_bo *bo);
771fe6b9
JG		 699};
700
21f9a437
JG		 701/*
702 * Asic structures
703 */
551ebd83
DA		 704struct r100_asic {
705 const unsigned *reg_safe_bm;
706 unsigned reg_safe_bm_size;
cafe6609 707 u32 hdp_cntl;
551ebd83
DA		 708};
709
21f9a437
JG		 710struct r300_asic {
711 const unsigned *reg_safe_bm;
712 unsigned reg_safe_bm_size;
62cdc0c2 713 u32 resync_scratch;
cafe6609 714 u32 hdp_cntl;
21f9a437
JG		 715};
716
717struct r600_asic {
718 unsigned max_pipes;
719 unsigned max_tile_pipes;
720 unsigned max_simds;
721 unsigned max_backends;
722 unsigned max_gprs;
723 unsigned max_threads;
724 unsigned max_stack_entries;
725 unsigned max_hw_contexts;
726 unsigned max_gs_threads;
727 unsigned sx_max_export_size;
728 unsigned sx_max_export_pos_size;
729 unsigned sx_max_export_smx_size;
730 unsigned sq_num_cf_insts;
731};
732
733struct rv770_asic {
734 unsigned max_pipes;
735 unsigned max_tile_pipes;
736 unsigned max_simds;
737 unsigned max_backends;
738 unsigned max_gprs;
739 unsigned max_threads;
740 unsigned max_stack_entries;
741 unsigned max_hw_contexts;
742 unsigned max_gs_threads;
743 unsigned sx_max_export_size;
744 unsigned sx_max_export_pos_size;
745 unsigned sx_max_export_smx_size;
746 unsigned sq_num_cf_insts;
747 unsigned sx_num_of_sets;
748 unsigned sc_prim_fifo_size;
749 unsigned sc_hiz_tile_fifo_size;
750 unsigned sc_earlyz_tile_fifo_fize;
751};
752
068a117c
JG		 753union radeon_asic_config {
754 struct r300_asic r300;
551ebd83 755 struct r100_asic r100;
3ce0a23d
JG		 756 struct r600_asic r600;
757 struct rv770_asic rv770;
068a117c
JG		 758};
759
771fe6b9
JG		 760
761/*
762 * IOCTL.
763 */
764int radeon_gem_info_ioctl(struct drm_device *dev, void *data,
765 struct drm_file *filp);
766int radeon_gem_create_ioctl(struct drm_device *dev, void *data,
767 struct drm_file *filp);
768int radeon_gem_pin_ioctl(struct drm_device *dev, void *data,
769 struct drm_file *file_priv);
770int radeon_gem_unpin_ioctl(struct drm_device *dev, void *data,
771 struct drm_file *file_priv);
772int radeon_gem_pwrite_ioctl(struct drm_device *dev, void *data,
773 struct drm_file *file_priv);
774int radeon_gem_pread_ioctl(struct drm_device *dev, void *data,
775 struct drm_file *file_priv);
776int radeon_gem_set_domain_ioctl(struct drm_device *dev, void *data,
777 struct drm_file *filp);
778int radeon_gem_mmap_ioctl(struct drm_device *dev, void *data,
779 struct drm_file *filp);
780int radeon_gem_busy_ioctl(struct drm_device *dev, void *data,
781 struct drm_file *filp);
782int radeon_gem_wait_idle_ioctl(struct drm_device *dev, void *data,
783 struct drm_file *filp);
784int radeon_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp);
e024e110
DA		 785int radeon_gem_set_tiling_ioctl(struct drm_device *dev, void *data,
786 struct drm_file *filp);
787int radeon_gem_get_tiling_ioctl(struct drm_device *dev, void *data,
788 struct drm_file *filp);
771fe6b9
JG		 789
790
791/*
792 * Core structure, functions and helpers.
793 */
794typedef uint32_t (*radeon_rreg_t)(struct radeon_device*, uint32_t);
795typedef void (*radeon_wreg_t)(struct radeon_device*, uint32_t, uint32_t);
796
797struct radeon_device {
9f022ddf 798 struct device *dev;
771fe6b9
JG		 799 struct drm_device *ddev;
800 struct pci_dev *pdev;
801 /* ASIC */
068a117c 802 union radeon_asic_config config;
771fe6b9
JG		 803 enum radeon_family family;
804 unsigned long flags;
805 int usec_timeout;
806 enum radeon_pll_errata pll_errata;
807 int num_gb_pipes;
f779b3e5 808 int num_z_pipes;
771fe6b9
JG		 809 int disp_priority;
810 /* BIOS */
811 uint8_t *bios;
812 bool is_atom_bios;
813 uint16_t bios_header_start;
4c788679 814 struct radeon_bo *stollen_vga_memory;
771fe6b9 815 struct fb_info *fbdev_info;
4c788679 816 struct radeon_bo *fbdev_rbo;
771fe6b9
JG		 817 struct radeon_framebuffer *fbdev_rfb;
818 /* Register mmio */
4c9bc75c
DA		 819 resource_size_t rmmio_base;
820 resource_size_t rmmio_size;
771fe6b9 821 void *rmmio;
771fe6b9
JG		 822 radeon_rreg_t mc_rreg;
823 radeon_wreg_t mc_wreg;
824 radeon_rreg_t pll_rreg;
825 radeon_wreg_t pll_wreg;
de1b2898 826 uint32_t pcie_reg_mask;
771fe6b9
JG		 827 radeon_rreg_t pciep_rreg;
828 radeon_wreg_t pciep_wreg;
829 struct radeon_clock clock;
830 struct radeon_mc mc;
831 struct radeon_gart gart;
832 struct radeon_mode_info mode_info;
833 struct radeon_scratch scratch;
834 struct radeon_mman mman;
835 struct radeon_fence_driver fence_drv;
836 struct radeon_cp cp;
837 struct radeon_ib_pool ib_pool;
838 struct radeon_irq irq;
839 struct radeon_asic *asic;
840 struct radeon_gem gem;
c93bb85b 841 struct radeon_pm pm;
f657c2a7 842 uint32_t bios_scratch[RADEON_BIOS_NUM_SCRATCH];
771fe6b9
JG		 843 struct mutex cs_mutex;
844 struct radeon_wb wb;
3ce0a23d 845 struct radeon_dummy_page dummy_page;
771fe6b9
JG		 846 bool gpu_lockup;
847 bool shutdown;
848 bool suspend;
ad49f501 849 bool need_dma32;
733289c2 850 bool accel_working;
e024e110 851 struct radeon_surface_reg surface_regs[RADEON_GEM_MAX_SURFACES];
3ce0a23d
JG		 852 const struct firmware *me_fw; /* all family ME firmware */
853 const struct firmware *pfp_fw; /* r6/700 PFP firmware */
d8f60cfc 854 const struct firmware *rlc_fw; /* r6/700 RLC firmware */
3ce0a23d 855 struct r600_blit r600_blit;
3e5cb98d 856 int msi_enabled; /* msi enabled */
d8f60cfc 857 struct r600_ih ih; /* r6/700 interrupt ring */
d4877cf2
AD		 858 struct workqueue_struct *wq;
859 struct work_struct hotplug_work;
18917b60 860 int num_crtc; /* number of crtcs */
40bacf16 861 struct mutex dc_hw_i2c_mutex; /* display controller hw i2c mutex */
dafc3bd5
CK		 862
863 /* audio stuff */
864 struct timer_list audio_timer;
865 int audio_channels;
866 int audio_rate;
867 int audio_bits_per_sample;
868 uint8_t audio_status_bits;
869 uint8_t audio_category_code;
771fe6b9
JG		 870};
871
872int radeon_device_init(struct radeon_device *rdev,
873 struct drm_device *ddev,
874 struct pci_dev *pdev,
875 uint32_t flags);
876void radeon_device_fini(struct radeon_device *rdev);
877int radeon_gpu_wait_for_idle(struct radeon_device *rdev);
878
3ce0a23d
JG		 879/* r600 blit */
880int r600_blit_prepare_copy(struct radeon_device *rdev, int size_bytes);
881void r600_blit_done_copy(struct radeon_device *rdev, struct radeon_fence *fence);
882void r600_kms_blit_copy(struct radeon_device *rdev,
883 u64 src_gpu_addr, u64 dst_gpu_addr,
884 int size_bytes);
885
de1b2898
DA		 886static inline uint32_t r100_mm_rreg(struct radeon_device *rdev, uint32_t reg)
887{
07bec2df 888 if (reg < rdev->rmmio_size)
de1b2898
DA		 889 return readl(((void __iomem *)rdev->rmmio) + reg);
890 else {
891 writel(reg, ((void __iomem *)rdev->rmmio) + RADEON_MM_INDEX);
892 return readl(((void __iomem *)rdev->rmmio) + RADEON_MM_DATA);
893 }
894}
895
896static inline void r100_mm_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
897{
07bec2df 898 if (reg < rdev->rmmio_size)
de1b2898
DA		 899 writel(v, ((void __iomem *)rdev->rmmio) + reg);
900 else {
901 writel(reg, ((void __iomem *)rdev->rmmio) + RADEON_MM_INDEX);
902 writel(v, ((void __iomem *)rdev->rmmio) + RADEON_MM_DATA);
903 }
904}
905
4c788679
JG		 906/*
907 * Cast helper
908 */
909#define to_radeon_fence(p) ((struct radeon_fence *)(p))
771fe6b9
JG		 910
911/*
912 * Registers read & write functions.
913 */
914#define RREG8(reg) readb(((void __iomem *)rdev->rmmio) + (reg))
915#define WREG8(reg, v) writeb(v, ((void __iomem *)rdev->rmmio) + (reg))
de1b2898 916#define RREG32(reg) r100_mm_rreg(rdev, (reg))
3ce0a23d 917#define DREG32(reg) printk(KERN_INFO "REGISTER: " #reg " : 0x%08X\n", r100_mm_rreg(rdev, (reg)))
de1b2898 918#define WREG32(reg, v) r100_mm_wreg(rdev, (reg), (v))
771fe6b9
JG		 919#define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
920#define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
921#define RREG32_PLL(reg) rdev->pll_rreg(rdev, (reg))
922#define WREG32_PLL(reg, v) rdev->pll_wreg(rdev, (reg), (v))
923#define RREG32_MC(reg) rdev->mc_rreg(rdev, (reg))
924#define WREG32_MC(reg, v) rdev->mc_wreg(rdev, (reg), (v))
de1b2898
DA		 925#define RREG32_PCIE(reg) rv370_pcie_rreg(rdev, (reg))
926#define WREG32_PCIE(reg, v) rv370_pcie_wreg(rdev, (reg), (v))
771fe6b9
JG		 927#define WREG32_P(reg, val, mask) \
928 do { \
929 uint32_t tmp_ = RREG32(reg); \
930 tmp_ &= (mask); \
931 tmp_ |= ((val) & ~(mask)); \
932 WREG32(reg, tmp_); \
933 } while (0)
934#define WREG32_PLL_P(reg, val, mask) \
935 do { \
936 uint32_t tmp_ = RREG32_PLL(reg); \
937 tmp_ &= (mask); \
938 tmp_ |= ((val) & ~(mask)); \
939 WREG32_PLL(reg, tmp_); \
940 } while (0)
3ce0a23d 941#define DREG32_SYS(sqf, rdev, reg) seq_printf((sqf), #reg " : 0x%08X\n", r100_mm_rreg((rdev), (reg)))
771fe6b9 942
de1b2898
DA		 943/*
944 * Indirect registers accessor
945 */
946static inline uint32_t rv370_pcie_rreg(struct radeon_device *rdev, uint32_t reg)
947{
948 uint32_t r;
949
950 WREG32(RADEON_PCIE_INDEX, ((reg) & rdev->pcie_reg_mask));
951 r = RREG32(RADEON_PCIE_DATA);
952 return r;
953}
954
955static inline void rv370_pcie_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
956{
957 WREG32(RADEON_PCIE_INDEX, ((reg) & rdev->pcie_reg_mask));
958 WREG32(RADEON_PCIE_DATA, (v));
959}
960
771fe6b9
JG		 961void r100_pll_errata_after_index(struct radeon_device *rdev);
962
963
964/*
965 * ASICs helpers.
966 */
b995e433
DA		 967#define ASIC_IS_RN50(rdev) ((rdev->pdev->device == 0x515e) || \
968 (rdev->pdev->device == 0x5969))
771fe6b9
JG		 969#define ASIC_IS_RV100(rdev) ((rdev->family == CHIP_RV100) || \
970 (rdev->family == CHIP_RV200) || \
971 (rdev->family == CHIP_RS100) || \
972 (rdev->family == CHIP_RS200) || \
973 (rdev->family == CHIP_RV250) || \
974 (rdev->family == CHIP_RV280) || \
975 (rdev->family == CHIP_RS300))
976#define ASIC_IS_R300(rdev) ((rdev->family == CHIP_R300) || \
977 (rdev->family == CHIP_RV350) || \
978 (rdev->family == CHIP_R350) || \
979 (rdev->family == CHIP_RV380) || \
980 (rdev->family == CHIP_R420) || \
981 (rdev->family == CHIP_R423) || \
982 (rdev->family == CHIP_RV410) || \
983 (rdev->family == CHIP_RS400) || \
984 (rdev->family == CHIP_RS480))
985#define ASIC_IS_AVIVO(rdev) ((rdev->family >= CHIP_RS600))
986#define ASIC_IS_DCE3(rdev) ((rdev->family >= CHIP_RV620))
987#define ASIC_IS_DCE32(rdev) ((rdev->family >= CHIP_RV730))
988
989
990/*
991 * BIOS helpers.
992 */
993#define RBIOS8(i) (rdev->bios[i])
994#define RBIOS16(i) (RBIOS8(i) | (RBIOS8((i)+1) << 8))
995#define RBIOS32(i) ((RBIOS16(i)) | (RBIOS16((i)+2) << 16))
996
997int radeon_combios_init(struct radeon_device *rdev);
998void radeon_combios_fini(struct radeon_device *rdev);
999int radeon_atombios_init(struct radeon_device *rdev);
1000void radeon_atombios_fini(struct radeon_device *rdev);
1001
1002
1003/*
1004 * RING helpers.
1005 */
771fe6b9
JG		 1006static inline void radeon_ring_write(struct radeon_device *rdev, uint32_t v)
1007{
1008#if DRM_DEBUG_CODE
1009 if (rdev->cp.count_dw <= 0) {
1010 DRM_ERROR("radeon: writting more dword to ring than expected !\n");
1011 }
1012#endif
1013 rdev->cp.ring[rdev->cp.wptr++] = v;
1014 rdev->cp.wptr &= rdev->cp.ptr_mask;
1015 rdev->cp.count_dw--;
1016 rdev->cp.ring_free_dw--;
1017}
1018
1019
1020/*
1021 * ASICs macro.
1022 */
068a117c 1023#define radeon_init(rdev) (rdev)->asic->init((rdev))
3ce0a23d
JG		 1024#define radeon_fini(rdev) (rdev)->asic->fini((rdev))
1025#define radeon_resume(rdev) (rdev)->asic->resume((rdev))
1026#define radeon_suspend(rdev) (rdev)->asic->suspend((rdev))
771fe6b9 1027#define radeon_cs_parse(p) rdev->asic->cs_parse((p))
28d52043 1028#define radeon_vga_set_state(rdev, state) (rdev)->asic->vga_set_state((rdev), (state))
771fe6b9 1029#define radeon_gpu_reset(rdev) (rdev)->asic->gpu_reset((rdev))
771fe6b9
JG		 1030#define radeon_gart_tlb_flush(rdev) (rdev)->asic->gart_tlb_flush((rdev))
1031#define radeon_gart_set_page(rdev, i, p) (rdev)->asic->gart_set_page((rdev), (i), (p))
3ce0a23d 1032#define radeon_cp_commit(rdev) (rdev)->asic->cp_commit((rdev))
771fe6b9 1033#define radeon_ring_start(rdev) (rdev)->asic->ring_start((rdev))
3ce0a23d
JG		 1034#define radeon_ring_test(rdev) (rdev)->asic->ring_test((rdev))
1035#define radeon_ring_ib_execute(rdev, ib) (rdev)->asic->ring_ib_execute((rdev), (ib))
771fe6b9
JG		 1036#define radeon_irq_set(rdev) (rdev)->asic->irq_set((rdev))
1037#define radeon_irq_process(rdev) (rdev)->asic->irq_process((rdev))
7ed220d7 1038#define radeon_get_vblank_counter(rdev, crtc) (rdev)->asic->get_vblank_counter((rdev), (crtc))
771fe6b9
JG		 1039#define radeon_fence_ring_emit(rdev, fence) (rdev)->asic->fence_ring_emit((rdev), (fence))
1040#define radeon_copy_blit(rdev, s, d, np, f) (rdev)->asic->copy_blit((rdev), (s), (d), (np), (f))
1041#define radeon_copy_dma(rdev, s, d, np, f) (rdev)->asic->copy_dma((rdev), (s), (d), (np), (f))
1042#define radeon_copy(rdev, s, d, np, f) (rdev)->asic->copy((rdev), (s), (d), (np), (f))
7433874e 1043#define radeon_get_engine_clock(rdev) (rdev)->asic->get_engine_clock((rdev))
771fe6b9 1044#define radeon_set_engine_clock(rdev, e) (rdev)->asic->set_engine_clock((rdev), (e))
7433874e 1045#define radeon_get_memory_clock(rdev) (rdev)->asic->get_memory_clock((rdev))
93e7de7b 1046#define radeon_set_memory_clock(rdev, e) (rdev)->asic->set_memory_clock((rdev), (e))
771fe6b9
JG		 1047#define radeon_set_pcie_lanes(rdev, l) (rdev)->asic->set_pcie_lanes((rdev), (l))
1048#define radeon_set_clock_gating(rdev, e) (rdev)->asic->set_clock_gating((rdev), (e))
e024e110
DA		 1049#define radeon_set_surface_reg(rdev, r, f, p, o, s) ((rdev)->asic->set_surface_reg((rdev), (r), (f), (p), (o), (s)))
1050#define radeon_clear_surface_reg(rdev, r) ((rdev)->asic->clear_surface_reg((rdev), (r)))
c93bb85b 1051#define radeon_bandwidth_update(rdev) (rdev)->asic->bandwidth_update((rdev))
429770b3
AD		 1052#define radeon_hpd_init(rdev) (rdev)->asic->hpd_init((rdev))
1053#define radeon_hpd_fini(rdev) (rdev)->asic->hpd_fini((rdev))
1054#define radeon_hpd_sense(rdev, hpd) (rdev)->asic->hpd_sense((rdev), (hpd))
1055#define radeon_hpd_set_polarity(rdev, hpd) (rdev)->asic->hpd_set_polarity((rdev), (hpd))
771fe6b9 1056
6cf8a3f5 1057/* Common functions */
700a0cc0
JG		 1058/* AGP */
1059extern void radeon_agp_disable(struct radeon_device *rdev);
4aac0473 1060extern int radeon_gart_table_vram_pin(struct radeon_device *rdev);
21f9a437
JG		 1061extern int radeon_modeset_init(struct radeon_device *rdev);
1062extern void radeon_modeset_fini(struct radeon_device *rdev);
9f022ddf 1063extern bool radeon_card_posted(struct radeon_device *rdev);
72542d77 1064extern bool radeon_boot_test_post_card(struct radeon_device *rdev);
21f9a437
JG		 1065extern int radeon_clocks_init(struct radeon_device *rdev);
1066extern void radeon_clocks_fini(struct radeon_device *rdev);
1067extern void radeon_scratch_init(struct radeon_device *rdev);
1068extern void radeon_surface_init(struct radeon_device *rdev);
1069extern int radeon_cs_parser_init(struct radeon_cs_parser *p, void *data);
ca6ffc64 1070extern void radeon_legacy_set_clock_gating(struct radeon_device *rdev, int enable);
d39c3b89 1071extern void radeon_atom_set_clock_gating(struct radeon_device *rdev, int enable);
312ea8da 1072extern void radeon_ttm_placement_from_domain(struct radeon_bo *rbo, u32 domain);
d03d8589 1073extern bool radeon_ttm_bo_is_radeon_bo(struct ttm_buffer_object *bo);
6cf8a3f5 1074
a18d7ea1 1075/* r100,rv100,rs100,rv200,rs200,r200,rv250,rs300,rv280 */
9f022ddf
JG		 1076struct r100_mc_save {
1077 u32 GENMO_WT;
1078 u32 CRTC_EXT_CNTL;
1079 u32 CRTC_GEN_CNTL;
1080 u32 CRTC2_GEN_CNTL;
1081 u32 CUR_OFFSET;
1082 u32 CUR2_OFFSET;
1083};
1084extern void r100_cp_disable(struct radeon_device *rdev);
1085extern int r100_cp_init(struct radeon_device *rdev, unsigned ring_size);
1086extern void r100_cp_fini(struct radeon_device *rdev);
21f9a437 1087extern void r100_pci_gart_tlb_flush(struct radeon_device *rdev);
4aac0473
JG		 1088extern int r100_pci_gart_init(struct radeon_device *rdev);
1089extern void r100_pci_gart_fini(struct radeon_device *rdev);
21f9a437
JG		 1090extern int r100_pci_gart_enable(struct radeon_device *rdev);
1091extern void r100_pci_gart_disable(struct radeon_device *rdev);
1092extern int r100_pci_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr);
9f022ddf
JG		 1093extern int r100_debugfs_mc_info_init(struct radeon_device *rdev);
1094extern int r100_gui_wait_for_idle(struct radeon_device *rdev);
1095extern void r100_ib_fini(struct radeon_device *rdev);
1096extern int r100_ib_init(struct radeon_device *rdev);
1097extern void r100_irq_disable(struct radeon_device *rdev);
1098extern int r100_irq_set(struct radeon_device *rdev);
1099extern void r100_mc_stop(struct radeon_device *rdev, struct r100_mc_save *save);
1100extern void r100_mc_resume(struct radeon_device *rdev, struct r100_mc_save *save);
21f9a437 1101extern void r100_vram_init_sizes(struct radeon_device *rdev);
9f022ddf
JG		 1102extern void r100_wb_disable(struct radeon_device *rdev);
1103extern void r100_wb_fini(struct radeon_device *rdev);
1104extern int r100_wb_init(struct radeon_device *rdev);
d39c3b89
JG		 1105extern void r100_hdp_reset(struct radeon_device *rdev);
1106extern int r100_rb2d_reset(struct radeon_device *rdev);
1107extern int r100_cp_reset(struct radeon_device *rdev);
ca6ffc64 1108extern void r100_vga_render_disable(struct radeon_device *rdev);
207bf9e9
JG		 1109extern int r100_cs_track_check_pkt3_indx_buffer(struct radeon_cs_parser *p,
1110 struct radeon_cs_packet *pkt,
4c788679 1111 struct radeon_bo *robj);
207bf9e9
JG		 1112extern int r100_cs_parse_packet0(struct radeon_cs_parser *p,
1113 struct radeon_cs_packet *pkt,
1114 const unsigned *auth, unsigned n,
1115 radeon_packet0_check_t check);
1116extern int r100_cs_packet_parse(struct radeon_cs_parser *p,
1117 struct radeon_cs_packet *pkt,
1118 unsigned idx);
17e15b0c 1119extern void r100_enable_bm(struct radeon_device *rdev);
92cde00c 1120extern void r100_set_common_regs(struct radeon_device *rdev);
9f022ddf 1121
d4550907
JG		 1122/* rv200,rv250,rv280 */
1123extern void r200_set_safe_registers(struct radeon_device *rdev);
9f022ddf
JG		 1124
1125/* r300,r350,rv350,rv370,rv380 */
1126extern void r300_set_reg_safe(struct radeon_device *rdev);
1127extern void r300_mc_program(struct radeon_device *rdev);
1128extern void r300_vram_info(struct radeon_device *rdev);
ca6ffc64
JG		 1129extern void r300_clock_startup(struct radeon_device *rdev);
1130extern int r300_mc_wait_for_idle(struct radeon_device *rdev);
4aac0473
JG		 1131extern int rv370_pcie_gart_init(struct radeon_device *rdev);
1132extern void rv370_pcie_gart_fini(struct radeon_device *rdev);
1133extern int rv370_pcie_gart_enable(struct radeon_device *rdev);
9f022ddf 1134extern void rv370_pcie_gart_disable(struct radeon_device *rdev);
a18d7ea1 1135
905b6822 1136/* r420,r423,rv410 */
d39c3b89 1137extern int r420_mc_init(struct radeon_device *rdev);
21f9a437
JG		 1138extern u32 r420_mc_rreg(struct radeon_device *rdev, u32 reg);
1139extern void r420_mc_wreg(struct radeon_device *rdev, u32 reg, u32 v);
9f022ddf 1140extern int r420_debugfs_pipes_info_init(struct radeon_device *rdev);
d39c3b89 1141extern void r420_pipes_init(struct radeon_device *rdev);
905b6822 1142
21f9a437 1143/* rv515 */
d39c3b89
JG		 1144struct rv515_mc_save {
1145 u32 d1vga_control;
1146 u32 d2vga_control;
1147 u32 vga_render_control;
1148 u32 vga_hdp_control;
1149 u32 d1crtc_control;
1150 u32 d2crtc_control;
1151};
21f9a437 1152extern void rv515_bandwidth_avivo_update(struct radeon_device *rdev);
d39c3b89
JG		 1153extern void rv515_vga_render_disable(struct radeon_device *rdev);
1154extern void rv515_set_safe_registers(struct radeon_device *rdev);
f0ed1f65
JG		 1155extern void rv515_mc_stop(struct radeon_device *rdev, struct rv515_mc_save *save);
1156extern void rv515_mc_resume(struct radeon_device *rdev, struct rv515_mc_save *save);
1157extern void rv515_clock_startup(struct radeon_device *rdev);
1158extern void rv515_debugfs(struct radeon_device *rdev);
1159extern int rv515_suspend(struct radeon_device *rdev);
21f9a437 1160
3bc68535
JG		 1161/* rs400 */
1162extern int rs400_gart_init(struct radeon_device *rdev);
1163extern int rs400_gart_enable(struct radeon_device *rdev);
1164extern void rs400_gart_adjust_size(struct radeon_device *rdev);
1165extern void rs400_gart_disable(struct radeon_device *rdev);
1166extern void rs400_gart_fini(struct radeon_device *rdev);
1167
1168/* rs600 */
1169extern void rs600_set_safe_registers(struct radeon_device *rdev);
ac447df4
JG		 1170extern int rs600_irq_set(struct radeon_device *rdev);
1171extern void rs600_irq_disable(struct radeon_device *rdev);
3bc68535 1172
21f9a437
JG		 1173/* rs690, rs740 */
1174extern void rs690_line_buffer_adjust(struct radeon_device *rdev,
1175 struct drm_display_mode *mode1,
1176 struct drm_display_mode *mode2);
1177
1178/* r600, rv610, rv630, rv620, rv635, rv670, rs780, rs880 */
1179extern bool r600_card_posted(struct radeon_device *rdev);
1180extern void r600_cp_stop(struct radeon_device *rdev);
1181extern void r600_ring_init(struct radeon_device *rdev, unsigned ring_size);
1182extern int r600_cp_resume(struct radeon_device *rdev);
655efd3d 1183extern void r600_cp_fini(struct radeon_device *rdev);
21f9a437
JG		 1184extern int r600_count_pipe_bits(uint32_t val);
1185extern int r600_gart_clear_page(struct radeon_device *rdev, int i);
1186extern int r600_mc_wait_for_idle(struct radeon_device *rdev);
4aac0473 1187extern int r600_pcie_gart_init(struct radeon_device *rdev);
21f9a437
JG		 1188extern void r600_pcie_gart_tlb_flush(struct radeon_device *rdev);
1189extern int r600_ib_test(struct radeon_device *rdev);
1190extern int r600_ring_test(struct radeon_device *rdev);
21f9a437 1191extern void r600_wb_fini(struct radeon_device *rdev);
81cc35bf
JG		 1192extern int r600_wb_enable(struct radeon_device *rdev);
1193extern void r600_wb_disable(struct radeon_device *rdev);
21f9a437
JG		 1194extern void r600_scratch_init(struct radeon_device *rdev);
1195extern int r600_blit_init(struct radeon_device *rdev);
1196extern void r600_blit_fini(struct radeon_device *rdev);
d8f60cfc 1197extern int r600_init_microcode(struct radeon_device *rdev);
fe62e1a4 1198extern int r600_gpu_reset(struct radeon_device *rdev);
d8f60cfc
AD		 1199/* r600 irq */
1200extern int r600_irq_init(struct radeon_device *rdev);
1201extern void r600_irq_fini(struct radeon_device *rdev);
1202extern void r600_ih_ring_init(struct radeon_device *rdev, unsigned ring_size);
1203extern int r600_irq_set(struct radeon_device *rdev);
0c45249f
JG		 1204extern void r600_irq_suspend(struct radeon_device *rdev);
1205/* r600 audio */
dafc3bd5
CK		 1206extern int r600_audio_init(struct radeon_device *rdev);
1207extern int r600_audio_tmds_index(struct drm_encoder *encoder);
1208extern void r600_audio_set_clock(struct drm_encoder *encoder, int clock);
1209extern void r600_audio_fini(struct radeon_device *rdev);
1210extern void r600_hdmi_init(struct drm_encoder *encoder);
1211extern void r600_hdmi_enable(struct drm_encoder *encoder, int enable);
1212extern void r600_hdmi_setmode(struct drm_encoder *encoder, struct drm_display_mode *mode);
1213extern int r600_hdmi_buffer_status_changed(struct drm_encoder *encoder);
1214extern void r600_hdmi_update_audio_settings(struct drm_encoder *encoder,
1215 int channels,
1216 int rate,
1217 int bps,
1218 uint8_t status_bits,
1219 uint8_t category_code);
1220
4c788679
JG		 1221#include "radeon_object.h"
1222
771fe6b9 1223#endif
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