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Commit | Line | Data |
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771fe6b9 JG |
1 | /* |
2 | * Copyright 2007-8 Advanced Micro Devices, Inc. | |
3 | * Copyright 2008 Red Hat Inc. | |
4 | * | |
5 | * Permission is hereby granted, free of charge, to any person obtaining a | |
6 | * copy of this software and associated documentation files (the "Software"), | |
7 | * to deal in the Software without restriction, including without limitation | |
8 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
9 | * and/or sell copies of the Software, and to permit persons to whom the | |
10 | * Software is furnished to do so, subject to the following conditions: | |
11 | * | |
12 | * The above copyright notice and this permission notice shall be included in | |
13 | * all copies or substantial portions of the Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
19 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
20 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
21 | * OTHER DEALINGS IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: Dave Airlie | |
24 | * Alex Deucher | |
25 | */ | |
760285e7 DH |
26 | #include <drm/drmP.h> |
27 | #include <drm/radeon_drm.h> | |
771fe6b9 JG |
28 | #include "radeon.h" |
29 | ||
30 | #include "atom.h" | |
31 | #include <asm/div64.h> | |
32 | ||
10ebc0bc | 33 | #include <linux/pm_runtime.h> |
760285e7 DH |
34 | #include <drm/drm_crtc_helper.h> |
35 | #include <drm/drm_edid.h> | |
771fe6b9 | 36 | |
32167016 CK |
37 | #include <linux/gcd.h> |
38 | ||
771fe6b9 JG |
39 | static void avivo_crtc_load_lut(struct drm_crtc *crtc) |
40 | { | |
41 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); | |
42 | struct drm_device *dev = crtc->dev; | |
43 | struct radeon_device *rdev = dev->dev_private; | |
44 | int i; | |
45 | ||
d9fdaafb | 46 | DRM_DEBUG_KMS("%d\n", radeon_crtc->crtc_id); |
771fe6b9 JG |
47 | WREG32(AVIVO_DC_LUTA_CONTROL + radeon_crtc->crtc_offset, 0); |
48 | ||
49 | WREG32(AVIVO_DC_LUTA_BLACK_OFFSET_BLUE + radeon_crtc->crtc_offset, 0); | |
50 | WREG32(AVIVO_DC_LUTA_BLACK_OFFSET_GREEN + radeon_crtc->crtc_offset, 0); | |
51 | WREG32(AVIVO_DC_LUTA_BLACK_OFFSET_RED + radeon_crtc->crtc_offset, 0); | |
52 | ||
53 | WREG32(AVIVO_DC_LUTA_WHITE_OFFSET_BLUE + radeon_crtc->crtc_offset, 0xffff); | |
54 | WREG32(AVIVO_DC_LUTA_WHITE_OFFSET_GREEN + radeon_crtc->crtc_offset, 0xffff); | |
55 | WREG32(AVIVO_DC_LUTA_WHITE_OFFSET_RED + radeon_crtc->crtc_offset, 0xffff); | |
56 | ||
57 | WREG32(AVIVO_DC_LUT_RW_SELECT, radeon_crtc->crtc_id); | |
58 | WREG32(AVIVO_DC_LUT_RW_MODE, 0); | |
59 | WREG32(AVIVO_DC_LUT_WRITE_EN_MASK, 0x0000003f); | |
60 | ||
61 | WREG8(AVIVO_DC_LUT_RW_INDEX, 0); | |
62 | for (i = 0; i < 256; i++) { | |
63 | WREG32(AVIVO_DC_LUT_30_COLOR, | |
64 | (radeon_crtc->lut_r[i] << 20) | | |
65 | (radeon_crtc->lut_g[i] << 10) | | |
66 | (radeon_crtc->lut_b[i] << 0)); | |
67 | } | |
68 | ||
69 | WREG32(AVIVO_D1GRPH_LUT_SEL + radeon_crtc->crtc_offset, radeon_crtc->crtc_id); | |
70 | } | |
71 | ||
fee298fd | 72 | static void dce4_crtc_load_lut(struct drm_crtc *crtc) |
bcc1c2a1 AD |
73 | { |
74 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); | |
75 | struct drm_device *dev = crtc->dev; | |
76 | struct radeon_device *rdev = dev->dev_private; | |
77 | int i; | |
78 | ||
d9fdaafb | 79 | DRM_DEBUG_KMS("%d\n", radeon_crtc->crtc_id); |
bcc1c2a1 AD |
80 | WREG32(EVERGREEN_DC_LUT_CONTROL + radeon_crtc->crtc_offset, 0); |
81 | ||
82 | WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_BLUE + radeon_crtc->crtc_offset, 0); | |
83 | WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_GREEN + radeon_crtc->crtc_offset, 0); | |
84 | WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_RED + radeon_crtc->crtc_offset, 0); | |
85 | ||
86 | WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_BLUE + radeon_crtc->crtc_offset, 0xffff); | |
87 | WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_GREEN + radeon_crtc->crtc_offset, 0xffff); | |
88 | WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_RED + radeon_crtc->crtc_offset, 0xffff); | |
89 | ||
677d0768 AD |
90 | WREG32(EVERGREEN_DC_LUT_RW_MODE + radeon_crtc->crtc_offset, 0); |
91 | WREG32(EVERGREEN_DC_LUT_WRITE_EN_MASK + radeon_crtc->crtc_offset, 0x00000007); | |
bcc1c2a1 | 92 | |
677d0768 | 93 | WREG32(EVERGREEN_DC_LUT_RW_INDEX + radeon_crtc->crtc_offset, 0); |
bcc1c2a1 | 94 | for (i = 0; i < 256; i++) { |
677d0768 | 95 | WREG32(EVERGREEN_DC_LUT_30_COLOR + radeon_crtc->crtc_offset, |
bcc1c2a1 AD |
96 | (radeon_crtc->lut_r[i] << 20) | |
97 | (radeon_crtc->lut_g[i] << 10) | | |
98 | (radeon_crtc->lut_b[i] << 0)); | |
99 | } | |
100 | } | |
101 | ||
fee298fd AD |
102 | static void dce5_crtc_load_lut(struct drm_crtc *crtc) |
103 | { | |
104 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); | |
105 | struct drm_device *dev = crtc->dev; | |
106 | struct radeon_device *rdev = dev->dev_private; | |
107 | int i; | |
108 | ||
109 | DRM_DEBUG_KMS("%d\n", radeon_crtc->crtc_id); | |
110 | ||
111 | WREG32(NI_INPUT_CSC_CONTROL + radeon_crtc->crtc_offset, | |
112 | (NI_INPUT_CSC_GRPH_MODE(NI_INPUT_CSC_BYPASS) | | |
113 | NI_INPUT_CSC_OVL_MODE(NI_INPUT_CSC_BYPASS))); | |
114 | WREG32(NI_PRESCALE_GRPH_CONTROL + radeon_crtc->crtc_offset, | |
115 | NI_GRPH_PRESCALE_BYPASS); | |
116 | WREG32(NI_PRESCALE_OVL_CONTROL + radeon_crtc->crtc_offset, | |
117 | NI_OVL_PRESCALE_BYPASS); | |
118 | WREG32(NI_INPUT_GAMMA_CONTROL + radeon_crtc->crtc_offset, | |
119 | (NI_GRPH_INPUT_GAMMA_MODE(NI_INPUT_GAMMA_USE_LUT) | | |
120 | NI_OVL_INPUT_GAMMA_MODE(NI_INPUT_GAMMA_USE_LUT))); | |
121 | ||
122 | WREG32(EVERGREEN_DC_LUT_CONTROL + radeon_crtc->crtc_offset, 0); | |
123 | ||
124 | WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_BLUE + radeon_crtc->crtc_offset, 0); | |
125 | WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_GREEN + radeon_crtc->crtc_offset, 0); | |
126 | WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_RED + radeon_crtc->crtc_offset, 0); | |
127 | ||
128 | WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_BLUE + radeon_crtc->crtc_offset, 0xffff); | |
129 | WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_GREEN + radeon_crtc->crtc_offset, 0xffff); | |
130 | WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_RED + radeon_crtc->crtc_offset, 0xffff); | |
131 | ||
132 | WREG32(EVERGREEN_DC_LUT_RW_MODE + radeon_crtc->crtc_offset, 0); | |
133 | WREG32(EVERGREEN_DC_LUT_WRITE_EN_MASK + radeon_crtc->crtc_offset, 0x00000007); | |
134 | ||
135 | WREG32(EVERGREEN_DC_LUT_RW_INDEX + radeon_crtc->crtc_offset, 0); | |
136 | for (i = 0; i < 256; i++) { | |
137 | WREG32(EVERGREEN_DC_LUT_30_COLOR + radeon_crtc->crtc_offset, | |
138 | (radeon_crtc->lut_r[i] << 20) | | |
139 | (radeon_crtc->lut_g[i] << 10) | | |
140 | (radeon_crtc->lut_b[i] << 0)); | |
141 | } | |
142 | ||
143 | WREG32(NI_DEGAMMA_CONTROL + radeon_crtc->crtc_offset, | |
144 | (NI_GRPH_DEGAMMA_MODE(NI_DEGAMMA_BYPASS) | | |
145 | NI_OVL_DEGAMMA_MODE(NI_DEGAMMA_BYPASS) | | |
146 | NI_ICON_DEGAMMA_MODE(NI_DEGAMMA_BYPASS) | | |
147 | NI_CURSOR_DEGAMMA_MODE(NI_DEGAMMA_BYPASS))); | |
148 | WREG32(NI_GAMUT_REMAP_CONTROL + radeon_crtc->crtc_offset, | |
149 | (NI_GRPH_GAMUT_REMAP_MODE(NI_GAMUT_REMAP_BYPASS) | | |
150 | NI_OVL_GAMUT_REMAP_MODE(NI_GAMUT_REMAP_BYPASS))); | |
151 | WREG32(NI_REGAMMA_CONTROL + radeon_crtc->crtc_offset, | |
152 | (NI_GRPH_REGAMMA_MODE(NI_REGAMMA_BYPASS) | | |
153 | NI_OVL_REGAMMA_MODE(NI_REGAMMA_BYPASS))); | |
154 | WREG32(NI_OUTPUT_CSC_CONTROL + radeon_crtc->crtc_offset, | |
155 | (NI_OUTPUT_CSC_GRPH_MODE(NI_OUTPUT_CSC_BYPASS) | | |
156 | NI_OUTPUT_CSC_OVL_MODE(NI_OUTPUT_CSC_BYPASS))); | |
157 | /* XXX match this to the depth of the crtc fmt block, move to modeset? */ | |
158 | WREG32(0x6940 + radeon_crtc->crtc_offset, 0); | |
9e05fa1d AD |
159 | if (ASIC_IS_DCE8(rdev)) { |
160 | /* XXX this only needs to be programmed once per crtc at startup, | |
161 | * not sure where the best place for it is | |
162 | */ | |
163 | WREG32(CIK_ALPHA_CONTROL + radeon_crtc->crtc_offset, | |
164 | CIK_CURSOR_ALPHA_BLND_ENA); | |
165 | } | |
fee298fd AD |
166 | } |
167 | ||
771fe6b9 JG |
168 | static void legacy_crtc_load_lut(struct drm_crtc *crtc) |
169 | { | |
170 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); | |
171 | struct drm_device *dev = crtc->dev; | |
172 | struct radeon_device *rdev = dev->dev_private; | |
173 | int i; | |
174 | uint32_t dac2_cntl; | |
175 | ||
176 | dac2_cntl = RREG32(RADEON_DAC_CNTL2); | |
177 | if (radeon_crtc->crtc_id == 0) | |
178 | dac2_cntl &= (uint32_t)~RADEON_DAC2_PALETTE_ACC_CTL; | |
179 | else | |
180 | dac2_cntl |= RADEON_DAC2_PALETTE_ACC_CTL; | |
181 | WREG32(RADEON_DAC_CNTL2, dac2_cntl); | |
182 | ||
183 | WREG8(RADEON_PALETTE_INDEX, 0); | |
184 | for (i = 0; i < 256; i++) { | |
185 | WREG32(RADEON_PALETTE_30_DATA, | |
186 | (radeon_crtc->lut_r[i] << 20) | | |
187 | (radeon_crtc->lut_g[i] << 10) | | |
188 | (radeon_crtc->lut_b[i] << 0)); | |
189 | } | |
190 | } | |
191 | ||
192 | void radeon_crtc_load_lut(struct drm_crtc *crtc) | |
193 | { | |
194 | struct drm_device *dev = crtc->dev; | |
195 | struct radeon_device *rdev = dev->dev_private; | |
196 | ||
197 | if (!crtc->enabled) | |
198 | return; | |
199 | ||
fee298fd AD |
200 | if (ASIC_IS_DCE5(rdev)) |
201 | dce5_crtc_load_lut(crtc); | |
202 | else if (ASIC_IS_DCE4(rdev)) | |
203 | dce4_crtc_load_lut(crtc); | |
bcc1c2a1 | 204 | else if (ASIC_IS_AVIVO(rdev)) |
771fe6b9 JG |
205 | avivo_crtc_load_lut(crtc); |
206 | else | |
207 | legacy_crtc_load_lut(crtc); | |
208 | } | |
209 | ||
b8c00ac5 | 210 | /** Sets the color ramps on behalf of fbcon */ |
771fe6b9 JG |
211 | void radeon_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green, |
212 | u16 blue, int regno) | |
213 | { | |
214 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); | |
215 | ||
771fe6b9 JG |
216 | radeon_crtc->lut_r[regno] = red >> 6; |
217 | radeon_crtc->lut_g[regno] = green >> 6; | |
218 | radeon_crtc->lut_b[regno] = blue >> 6; | |
219 | } | |
220 | ||
b8c00ac5 DA |
221 | /** Gets the color ramps on behalf of fbcon */ |
222 | void radeon_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green, | |
223 | u16 *blue, int regno) | |
224 | { | |
225 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); | |
226 | ||
227 | *red = radeon_crtc->lut_r[regno] << 6; | |
228 | *green = radeon_crtc->lut_g[regno] << 6; | |
229 | *blue = radeon_crtc->lut_b[regno] << 6; | |
230 | } | |
231 | ||
771fe6b9 | 232 | static void radeon_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green, |
7203425a | 233 | u16 *blue, uint32_t start, uint32_t size) |
771fe6b9 JG |
234 | { |
235 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); | |
7203425a | 236 | int end = (start + size > 256) ? 256 : start + size, i; |
771fe6b9 | 237 | |
b8c00ac5 | 238 | /* userspace palettes are always correct as is */ |
7203425a | 239 | for (i = start; i < end; i++) { |
b8c00ac5 DA |
240 | radeon_crtc->lut_r[i] = red[i] >> 6; |
241 | radeon_crtc->lut_g[i] = green[i] >> 6; | |
242 | radeon_crtc->lut_b[i] = blue[i] >> 6; | |
771fe6b9 | 243 | } |
771fe6b9 JG |
244 | radeon_crtc_load_lut(crtc); |
245 | } | |
246 | ||
247 | static void radeon_crtc_destroy(struct drm_crtc *crtc) | |
248 | { | |
249 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); | |
250 | ||
771fe6b9 | 251 | drm_crtc_cleanup(crtc); |
1aab5514 | 252 | destroy_workqueue(radeon_crtc->flip_queue); |
771fe6b9 JG |
253 | kfree(radeon_crtc); |
254 | } | |
255 | ||
1aab5514 CK |
256 | /** |
257 | * radeon_unpin_work_func - unpin old buffer object | |
258 | * | |
259 | * @__work - kernel work item | |
260 | * | |
261 | * Unpin the old frame buffer object outside of the interrupt handler | |
6f34be50 AD |
262 | */ |
263 | static void radeon_unpin_work_func(struct work_struct *__work) | |
264 | { | |
1aab5514 CK |
265 | struct radeon_flip_work *work = |
266 | container_of(__work, struct radeon_flip_work, unpin_work); | |
6f34be50 AD |
267 | int r; |
268 | ||
269 | /* unpin of the old buffer */ | |
270 | r = radeon_bo_reserve(work->old_rbo, false); | |
271 | if (likely(r == 0)) { | |
272 | r = radeon_bo_unpin(work->old_rbo); | |
273 | if (unlikely(r != 0)) { | |
274 | DRM_ERROR("failed to unpin buffer after flip\n"); | |
275 | } | |
276 | radeon_bo_unreserve(work->old_rbo); | |
277 | } else | |
278 | DRM_ERROR("failed to reserve buffer after flip\n"); | |
498c555f DA |
279 | |
280 | drm_gem_object_unreference_unlocked(&work->old_rbo->gem_base); | |
6f34be50 AD |
281 | kfree(work); |
282 | } | |
283 | ||
1a0e7918 | 284 | void radeon_crtc_handle_vblank(struct radeon_device *rdev, int crtc_id) |
6f34be50 AD |
285 | { |
286 | struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id]; | |
1aab5514 | 287 | struct radeon_flip_work *work; |
6f34be50 AD |
288 | unsigned long flags; |
289 | u32 update_pending; | |
290 | int vpos, hpos; | |
291 | ||
292 | spin_lock_irqsave(&rdev->ddev->event_lock, flags); | |
1aab5514 CK |
293 | work = radeon_crtc->flip_work; |
294 | if (work == NULL) { | |
6f34be50 AD |
295 | spin_unlock_irqrestore(&rdev->ddev->event_lock, flags); |
296 | return; | |
297 | } | |
1aab5514 CK |
298 | |
299 | update_pending = radeon_page_flip_pending(rdev, crtc_id); | |
6f34be50 AD |
300 | |
301 | /* Has the pageflip already completed in crtc, or is it certain | |
302 | * to complete in this vblank? | |
303 | */ | |
304 | if (update_pending && | |
abca9e45 | 305 | (DRM_SCANOUTPOS_VALID & radeon_get_crtc_scanoutpos(rdev->ddev, crtc_id, 0, |
d47abc58 | 306 | &vpos, &hpos, NULL, NULL)) && |
81ffbbed FK |
307 | ((vpos >= (99 * rdev->mode_info.crtcs[crtc_id]->base.hwmode.crtc_vdisplay)/100) || |
308 | (vpos < 0 && !ASIC_IS_AVIVO(rdev)))) { | |
309 | /* crtc didn't flip in this target vblank interval, | |
310 | * but flip is pending in crtc. Based on the current | |
311 | * scanout position we know that the current frame is | |
312 | * (nearly) complete and the flip will (likely) | |
313 | * complete before the start of the next frame. | |
314 | */ | |
315 | update_pending = 0; | |
316 | } | |
1aab5514 CK |
317 | spin_unlock_irqrestore(&rdev->ddev->event_lock, flags); |
318 | if (!update_pending) | |
1a0e7918 | 319 | radeon_crtc_handle_flip(rdev, crtc_id); |
1a0e7918 CK |
320 | } |
321 | ||
322 | /** | |
323 | * radeon_crtc_handle_flip - page flip completed | |
324 | * | |
325 | * @rdev: radeon device pointer | |
326 | * @crtc_id: crtc number this event is for | |
327 | * | |
328 | * Called when we are sure that a page flip for this crtc is completed. | |
329 | */ | |
330 | void radeon_crtc_handle_flip(struct radeon_device *rdev, int crtc_id) | |
331 | { | |
332 | struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id]; | |
1aab5514 | 333 | struct radeon_flip_work *work; |
1a0e7918 CK |
334 | unsigned long flags; |
335 | ||
336 | /* this can happen at init */ | |
337 | if (radeon_crtc == NULL) | |
338 | return; | |
339 | ||
340 | spin_lock_irqsave(&rdev->ddev->event_lock, flags); | |
1aab5514 | 341 | work = radeon_crtc->flip_work; |
1a0e7918 CK |
342 | if (work == NULL) { |
343 | spin_unlock_irqrestore(&rdev->ddev->event_lock, flags); | |
344 | return; | |
6f34be50 AD |
345 | } |
346 | ||
1aab5514 CK |
347 | /* Pageflip completed. Clean up. */ |
348 | radeon_crtc->flip_work = NULL; | |
6f34be50 AD |
349 | |
350 | /* wakeup userspace */ | |
26ae4667 RC |
351 | if (work->event) |
352 | drm_send_vblank_event(rdev->ddev, crtc_id, work->event); | |
353 | ||
6f34be50 AD |
354 | spin_unlock_irqrestore(&rdev->ddev->event_lock, flags); |
355 | ||
6f34be50 | 356 | radeon_fence_unref(&work->fence); |
e928c61a | 357 | radeon_irq_kms_pflip_irq_get(rdev, work->crtc_id); |
1aab5514 | 358 | queue_work(radeon_crtc->flip_queue, &work->unpin_work); |
6f34be50 AD |
359 | } |
360 | ||
1aab5514 CK |
361 | /** |
362 | * radeon_flip_work_func - page flip framebuffer | |
363 | * | |
364 | * @work - kernel work item | |
365 | * | |
366 | * Wait for the buffer object to become idle and do the actual page flip | |
367 | */ | |
368 | static void radeon_flip_work_func(struct work_struct *__work) | |
6f34be50 | 369 | { |
1aab5514 CK |
370 | struct radeon_flip_work *work = |
371 | container_of(__work, struct radeon_flip_work, flip_work); | |
372 | struct radeon_device *rdev = work->rdev; | |
373 | struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[work->crtc_id]; | |
6f34be50 | 374 | |
1aab5514 CK |
375 | struct drm_crtc *crtc = &radeon_crtc->base; |
376 | struct drm_framebuffer *fb = work->fb; | |
6f34be50 | 377 | |
1aab5514 CK |
378 | uint32_t tiling_flags, pitch_pixels; |
379 | uint64_t base; | |
9af20792 | 380 | |
1aab5514 CK |
381 | unsigned long flags; |
382 | int r; | |
9af20792 | 383 | |
1aab5514 CK |
384 | down_read(&rdev->exclusive_lock); |
385 | while (work->fence) { | |
386 | r = radeon_fence_wait(work->fence, false); | |
387 | if (r == -EDEADLK) { | |
388 | up_read(&rdev->exclusive_lock); | |
389 | r = radeon_gpu_reset(rdev); | |
390 | down_read(&rdev->exclusive_lock); | |
391 | } | |
6f34be50 | 392 | |
1aab5514 CK |
393 | if (r) { |
394 | DRM_ERROR("failed to wait on page flip fence (%d)!\n", | |
395 | r); | |
396 | goto cleanup; | |
397 | } else | |
398 | radeon_fence_unref(&work->fence); | |
6f34be50 | 399 | } |
6f34be50 AD |
400 | |
401 | /* pin the new buffer */ | |
6f34be50 | 402 | DRM_DEBUG_DRIVER("flip-ioctl() cur_fbo = %p, cur_bbo = %p\n", |
1aab5514 | 403 | work->old_rbo, work->new_rbo); |
6f34be50 | 404 | |
1aab5514 | 405 | r = radeon_bo_reserve(work->new_rbo, false); |
6f34be50 AD |
406 | if (unlikely(r != 0)) { |
407 | DRM_ERROR("failed to reserve new rbo buffer before flip\n"); | |
1aab5514 | 408 | goto cleanup; |
6f34be50 | 409 | } |
0349af70 | 410 | /* Only 27 bit offset for legacy CRTC */ |
1aab5514 | 411 | r = radeon_bo_pin_restricted(work->new_rbo, RADEON_GEM_DOMAIN_VRAM, |
0349af70 | 412 | ASIC_IS_AVIVO(rdev) ? 0 : 1 << 27, &base); |
6f34be50 | 413 | if (unlikely(r != 0)) { |
1aab5514 | 414 | radeon_bo_unreserve(work->new_rbo); |
6f34be50 AD |
415 | r = -EINVAL; |
416 | DRM_ERROR("failed to pin new rbo buffer before flip\n"); | |
1aab5514 | 417 | goto cleanup; |
6f34be50 | 418 | } |
1aab5514 CK |
419 | radeon_bo_get_tiling_flags(work->new_rbo, &tiling_flags, NULL); |
420 | radeon_bo_unreserve(work->new_rbo); | |
6f34be50 AD |
421 | |
422 | if (!ASIC_IS_AVIVO(rdev)) { | |
423 | /* crtc offset is from display base addr not FB location */ | |
424 | base -= radeon_crtc->legacy_display_base_addr; | |
01f2c773 | 425 | pitch_pixels = fb->pitches[0] / (fb->bits_per_pixel / 8); |
6f34be50 AD |
426 | |
427 | if (tiling_flags & RADEON_TILING_MACRO) { | |
428 | if (ASIC_IS_R300(rdev)) { | |
429 | base &= ~0x7ff; | |
430 | } else { | |
431 | int byteshift = fb->bits_per_pixel >> 4; | |
432 | int tile_addr = (((crtc->y >> 3) * pitch_pixels + crtc->x) >> (8 - byteshift)) << 11; | |
433 | base += tile_addr + ((crtc->x << byteshift) % 256) + ((crtc->y % 8) << 8); | |
434 | } | |
435 | } else { | |
436 | int offset = crtc->y * pitch_pixels + crtc->x; | |
437 | switch (fb->bits_per_pixel) { | |
438 | case 8: | |
439 | default: | |
440 | offset *= 1; | |
441 | break; | |
442 | case 15: | |
443 | case 16: | |
444 | offset *= 2; | |
445 | break; | |
446 | case 24: | |
447 | offset *= 3; | |
448 | break; | |
449 | case 32: | |
450 | offset *= 4; | |
451 | break; | |
452 | } | |
453 | base += offset; | |
454 | } | |
455 | base &= ~7; | |
456 | } | |
457 | ||
1aab5514 CK |
458 | /* We borrow the event spin lock for protecting flip_work */ |
459 | spin_lock_irqsave(&crtc->dev->event_lock, flags); | |
6f34be50 | 460 | |
6f34be50 | 461 | /* set the proper interrupt */ |
e928c61a | 462 | radeon_irq_kms_pflip_irq_get(rdev, radeon_crtc->crtc_id); |
6f34be50 | 463 | |
1aab5514 CK |
464 | /* do the flip (mmio) */ |
465 | radeon_page_flip(rdev, radeon_crtc->crtc_id, base); | |
6f34be50 | 466 | |
1aab5514 CK |
467 | spin_unlock_irqrestore(&crtc->dev->event_lock, flags); |
468 | up_read(&rdev->exclusive_lock); | |
469 | ||
470 | return; | |
471 | ||
472 | cleanup: | |
473 | drm_gem_object_unreference_unlocked(&work->old_rbo->gem_base); | |
fcc485d6 | 474 | radeon_fence_unref(&work->fence); |
6f34be50 | 475 | kfree(work); |
1aab5514 CK |
476 | up_read(&rdev->exclusive_lock); |
477 | } | |
478 | ||
479 | static int radeon_crtc_page_flip(struct drm_crtc *crtc, | |
480 | struct drm_framebuffer *fb, | |
481 | struct drm_pending_vblank_event *event, | |
482 | uint32_t page_flip_flags) | |
483 | { | |
484 | struct drm_device *dev = crtc->dev; | |
485 | struct radeon_device *rdev = dev->dev_private; | |
486 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); | |
487 | struct radeon_framebuffer *old_radeon_fb; | |
488 | struct radeon_framebuffer *new_radeon_fb; | |
489 | struct drm_gem_object *obj; | |
490 | struct radeon_flip_work *work; | |
491 | unsigned long flags; | |
492 | ||
493 | work = kzalloc(sizeof *work, GFP_KERNEL); | |
494 | if (work == NULL) | |
495 | return -ENOMEM; | |
496 | ||
497 | INIT_WORK(&work->flip_work, radeon_flip_work_func); | |
498 | INIT_WORK(&work->unpin_work, radeon_unpin_work_func); | |
6f34be50 | 499 | |
1aab5514 CK |
500 | work->rdev = rdev; |
501 | work->crtc_id = radeon_crtc->crtc_id; | |
502 | work->fb = fb; | |
503 | work->event = event; | |
504 | ||
505 | /* schedule unpin of the old buffer */ | |
506 | old_radeon_fb = to_radeon_framebuffer(crtc->primary->fb); | |
507 | obj = old_radeon_fb->obj; | |
508 | ||
509 | /* take a reference to the old object */ | |
510 | drm_gem_object_reference(obj); | |
511 | work->old_rbo = gem_to_radeon_bo(obj); | |
512 | ||
513 | new_radeon_fb = to_radeon_framebuffer(fb); | |
514 | obj = new_radeon_fb->obj; | |
515 | work->new_rbo = gem_to_radeon_bo(obj); | |
516 | ||
517 | spin_lock(&work->new_rbo->tbo.bdev->fence_lock); | |
518 | if (work->new_rbo->tbo.sync_obj) | |
519 | work->fence = radeon_fence_ref(work->new_rbo->tbo.sync_obj); | |
520 | spin_unlock(&work->new_rbo->tbo.bdev->fence_lock); | |
521 | ||
522 | /* update crtc fb */ | |
523 | crtc->primary->fb = fb; | |
524 | ||
525 | /* We borrow the event spin lock for protecting flip_work */ | |
526 | spin_lock_irqsave(&crtc->dev->event_lock, flags); | |
527 | ||
528 | if (radeon_crtc->flip_work) { | |
529 | DRM_DEBUG_DRIVER("flip queue: crtc already busy\n"); | |
530 | spin_unlock_irqrestore(&crtc->dev->event_lock, flags); | |
531 | drm_gem_object_unreference_unlocked(&work->old_rbo->gem_base); | |
532 | radeon_fence_unref(&work->fence); | |
533 | kfree(work); | |
534 | return -EBUSY; | |
535 | } | |
536 | radeon_crtc->flip_work = work; | |
537 | ||
538 | spin_unlock_irqrestore(&crtc->dev->event_lock, flags); | |
539 | ||
540 | queue_work(radeon_crtc->flip_queue, &work->flip_work); | |
541 | ||
542 | return 0; | |
6f34be50 AD |
543 | } |
544 | ||
10ebc0bc DA |
545 | static int |
546 | radeon_crtc_set_config(struct drm_mode_set *set) | |
547 | { | |
548 | struct drm_device *dev; | |
549 | struct radeon_device *rdev; | |
550 | struct drm_crtc *crtc; | |
551 | bool active = false; | |
552 | int ret; | |
553 | ||
554 | if (!set || !set->crtc) | |
555 | return -EINVAL; | |
556 | ||
557 | dev = set->crtc->dev; | |
558 | ||
559 | ret = pm_runtime_get_sync(dev->dev); | |
560 | if (ret < 0) | |
561 | return ret; | |
562 | ||
563 | ret = drm_crtc_helper_set_config(set); | |
564 | ||
565 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) | |
566 | if (crtc->enabled) | |
567 | active = true; | |
568 | ||
569 | pm_runtime_mark_last_busy(dev->dev); | |
570 | ||
571 | rdev = dev->dev_private; | |
572 | /* if we have active crtcs and we don't have a power ref, | |
573 | take the current one */ | |
574 | if (active && !rdev->have_disp_power_ref) { | |
575 | rdev->have_disp_power_ref = true; | |
576 | return ret; | |
577 | } | |
578 | /* if we have no active crtcs, then drop the power ref | |
579 | we got before */ | |
580 | if (!active && rdev->have_disp_power_ref) { | |
581 | pm_runtime_put_autosuspend(dev->dev); | |
582 | rdev->have_disp_power_ref = false; | |
583 | } | |
584 | ||
585 | /* drop the power reference we got coming in here */ | |
586 | pm_runtime_put_autosuspend(dev->dev); | |
587 | return ret; | |
588 | } | |
771fe6b9 JG |
589 | static const struct drm_crtc_funcs radeon_crtc_funcs = { |
590 | .cursor_set = radeon_crtc_cursor_set, | |
591 | .cursor_move = radeon_crtc_cursor_move, | |
592 | .gamma_set = radeon_crtc_gamma_set, | |
10ebc0bc | 593 | .set_config = radeon_crtc_set_config, |
771fe6b9 | 594 | .destroy = radeon_crtc_destroy, |
6f34be50 | 595 | .page_flip = radeon_crtc_page_flip, |
771fe6b9 JG |
596 | }; |
597 | ||
598 | static void radeon_crtc_init(struct drm_device *dev, int index) | |
599 | { | |
600 | struct radeon_device *rdev = dev->dev_private; | |
601 | struct radeon_crtc *radeon_crtc; | |
602 | int i; | |
603 | ||
604 | radeon_crtc = kzalloc(sizeof(struct radeon_crtc) + (RADEONFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL); | |
605 | if (radeon_crtc == NULL) | |
606 | return; | |
607 | ||
608 | drm_crtc_init(dev, &radeon_crtc->base, &radeon_crtc_funcs); | |
609 | ||
610 | drm_mode_crtc_set_gamma_size(&radeon_crtc->base, 256); | |
611 | radeon_crtc->crtc_id = index; | |
1aab5514 | 612 | radeon_crtc->flip_queue = create_singlethread_workqueue("radeon-crtc"); |
c93bb85b | 613 | rdev->mode_info.crtcs[index] = radeon_crtc; |
771fe6b9 | 614 | |
9e05fa1d AD |
615 | if (rdev->family >= CHIP_BONAIRE) { |
616 | radeon_crtc->max_cursor_width = CIK_CURSOR_WIDTH; | |
617 | radeon_crtc->max_cursor_height = CIK_CURSOR_HEIGHT; | |
618 | } else { | |
619 | radeon_crtc->max_cursor_width = CURSOR_WIDTH; | |
620 | radeon_crtc->max_cursor_height = CURSOR_HEIGHT; | |
621 | } | |
bea61c59 AD |
622 | dev->mode_config.cursor_width = radeon_crtc->max_cursor_width; |
623 | dev->mode_config.cursor_height = radeon_crtc->max_cursor_height; | |
9e05fa1d | 624 | |
785b93ef | 625 | #if 0 |
771fe6b9 JG |
626 | radeon_crtc->mode_set.crtc = &radeon_crtc->base; |
627 | radeon_crtc->mode_set.connectors = (struct drm_connector **)(radeon_crtc + 1); | |
628 | radeon_crtc->mode_set.num_connectors = 0; | |
785b93ef | 629 | #endif |
771fe6b9 JG |
630 | |
631 | for (i = 0; i < 256; i++) { | |
632 | radeon_crtc->lut_r[i] = i << 2; | |
633 | radeon_crtc->lut_g[i] = i << 2; | |
634 | radeon_crtc->lut_b[i] = i << 2; | |
635 | } | |
636 | ||
637 | if (rdev->is_atom_bios && (ASIC_IS_AVIVO(rdev) || radeon_r4xx_atom)) | |
638 | radeon_atombios_init_crtc(dev, radeon_crtc); | |
639 | else | |
640 | radeon_legacy_init_crtc(dev, radeon_crtc); | |
641 | } | |
642 | ||
e68adef8 | 643 | static const char *encoder_names[38] = { |
771fe6b9 JG |
644 | "NONE", |
645 | "INTERNAL_LVDS", | |
646 | "INTERNAL_TMDS1", | |
647 | "INTERNAL_TMDS2", | |
648 | "INTERNAL_DAC1", | |
649 | "INTERNAL_DAC2", | |
650 | "INTERNAL_SDVOA", | |
651 | "INTERNAL_SDVOB", | |
652 | "SI170B", | |
653 | "CH7303", | |
654 | "CH7301", | |
655 | "INTERNAL_DVO1", | |
656 | "EXTERNAL_SDVOA", | |
657 | "EXTERNAL_SDVOB", | |
658 | "TITFP513", | |
659 | "INTERNAL_LVTM1", | |
660 | "VT1623", | |
661 | "HDMI_SI1930", | |
662 | "HDMI_INTERNAL", | |
663 | "INTERNAL_KLDSCP_TMDS1", | |
664 | "INTERNAL_KLDSCP_DVO1", | |
665 | "INTERNAL_KLDSCP_DAC1", | |
666 | "INTERNAL_KLDSCP_DAC2", | |
667 | "SI178", | |
668 | "MVPU_FPGA", | |
669 | "INTERNAL_DDI", | |
670 | "VT1625", | |
671 | "HDMI_SI1932", | |
672 | "DP_AN9801", | |
673 | "DP_DP501", | |
674 | "INTERNAL_UNIPHY", | |
675 | "INTERNAL_KLDSCP_LVTMA", | |
676 | "INTERNAL_UNIPHY1", | |
677 | "INTERNAL_UNIPHY2", | |
bf982ebf AD |
678 | "NUTMEG", |
679 | "TRAVIS", | |
e68adef8 AD |
680 | "INTERNAL_VCE", |
681 | "INTERNAL_UNIPHY3", | |
771fe6b9 JG |
682 | }; |
683 | ||
cbd4623d | 684 | static const char *hpd_names[6] = { |
eed45b30 AD |
685 | "HPD1", |
686 | "HPD2", | |
687 | "HPD3", | |
688 | "HPD4", | |
689 | "HPD5", | |
690 | "HPD6", | |
691 | }; | |
692 | ||
771fe6b9 JG |
693 | static void radeon_print_display_setup(struct drm_device *dev) |
694 | { | |
695 | struct drm_connector *connector; | |
696 | struct radeon_connector *radeon_connector; | |
697 | struct drm_encoder *encoder; | |
698 | struct radeon_encoder *radeon_encoder; | |
699 | uint32_t devices; | |
700 | int i = 0; | |
701 | ||
702 | DRM_INFO("Radeon Display Connectors\n"); | |
703 | list_for_each_entry(connector, &dev->mode_config.connector_list, head) { | |
704 | radeon_connector = to_radeon_connector(connector); | |
705 | DRM_INFO("Connector %d:\n", i); | |
c1d2dbd2 | 706 | DRM_INFO(" %s\n", drm_get_connector_name(connector)); |
eed45b30 AD |
707 | if (radeon_connector->hpd.hpd != RADEON_HPD_NONE) |
708 | DRM_INFO(" %s\n", hpd_names[radeon_connector->hpd.hpd]); | |
4b9d2a21 | 709 | if (radeon_connector->ddc_bus) { |
771fe6b9 JG |
710 | DRM_INFO(" DDC: 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x\n", |
711 | radeon_connector->ddc_bus->rec.mask_clk_reg, | |
712 | radeon_connector->ddc_bus->rec.mask_data_reg, | |
713 | radeon_connector->ddc_bus->rec.a_clk_reg, | |
714 | radeon_connector->ddc_bus->rec.a_data_reg, | |
9b9fe724 AD |
715 | radeon_connector->ddc_bus->rec.en_clk_reg, |
716 | radeon_connector->ddc_bus->rec.en_data_reg, | |
717 | radeon_connector->ddc_bus->rec.y_clk_reg, | |
718 | radeon_connector->ddc_bus->rec.y_data_reg); | |
fb939dfc | 719 | if (radeon_connector->router.ddc_valid) |
26b5bc98 | 720 | DRM_INFO(" DDC Router 0x%x/0x%x\n", |
fb939dfc AD |
721 | radeon_connector->router.ddc_mux_control_pin, |
722 | radeon_connector->router.ddc_mux_state); | |
723 | if (radeon_connector->router.cd_valid) | |
724 | DRM_INFO(" Clock/Data Router 0x%x/0x%x\n", | |
725 | radeon_connector->router.cd_mux_control_pin, | |
726 | radeon_connector->router.cd_mux_state); | |
4b9d2a21 DA |
727 | } else { |
728 | if (connector->connector_type == DRM_MODE_CONNECTOR_VGA || | |
729 | connector->connector_type == DRM_MODE_CONNECTOR_DVII || | |
730 | connector->connector_type == DRM_MODE_CONNECTOR_DVID || | |
731 | connector->connector_type == DRM_MODE_CONNECTOR_DVIA || | |
732 | connector->connector_type == DRM_MODE_CONNECTOR_HDMIA || | |
733 | connector->connector_type == DRM_MODE_CONNECTOR_HDMIB) | |
734 | DRM_INFO(" DDC: no ddc bus - possible BIOS bug - please report to xorg-driver-ati@lists.x.org\n"); | |
735 | } | |
771fe6b9 JG |
736 | DRM_INFO(" Encoders:\n"); |
737 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { | |
738 | radeon_encoder = to_radeon_encoder(encoder); | |
739 | devices = radeon_encoder->devices & radeon_connector->devices; | |
740 | if (devices) { | |
741 | if (devices & ATOM_DEVICE_CRT1_SUPPORT) | |
742 | DRM_INFO(" CRT1: %s\n", encoder_names[radeon_encoder->encoder_id]); | |
743 | if (devices & ATOM_DEVICE_CRT2_SUPPORT) | |
744 | DRM_INFO(" CRT2: %s\n", encoder_names[radeon_encoder->encoder_id]); | |
745 | if (devices & ATOM_DEVICE_LCD1_SUPPORT) | |
746 | DRM_INFO(" LCD1: %s\n", encoder_names[radeon_encoder->encoder_id]); | |
747 | if (devices & ATOM_DEVICE_DFP1_SUPPORT) | |
748 | DRM_INFO(" DFP1: %s\n", encoder_names[radeon_encoder->encoder_id]); | |
749 | if (devices & ATOM_DEVICE_DFP2_SUPPORT) | |
750 | DRM_INFO(" DFP2: %s\n", encoder_names[radeon_encoder->encoder_id]); | |
751 | if (devices & ATOM_DEVICE_DFP3_SUPPORT) | |
752 | DRM_INFO(" DFP3: %s\n", encoder_names[radeon_encoder->encoder_id]); | |
753 | if (devices & ATOM_DEVICE_DFP4_SUPPORT) | |
754 | DRM_INFO(" DFP4: %s\n", encoder_names[radeon_encoder->encoder_id]); | |
755 | if (devices & ATOM_DEVICE_DFP5_SUPPORT) | |
756 | DRM_INFO(" DFP5: %s\n", encoder_names[radeon_encoder->encoder_id]); | |
73758a5d AD |
757 | if (devices & ATOM_DEVICE_DFP6_SUPPORT) |
758 | DRM_INFO(" DFP6: %s\n", encoder_names[radeon_encoder->encoder_id]); | |
771fe6b9 JG |
759 | if (devices & ATOM_DEVICE_TV1_SUPPORT) |
760 | DRM_INFO(" TV1: %s\n", encoder_names[radeon_encoder->encoder_id]); | |
761 | if (devices & ATOM_DEVICE_CV_SUPPORT) | |
762 | DRM_INFO(" CV: %s\n", encoder_names[radeon_encoder->encoder_id]); | |
763 | } | |
764 | } | |
765 | i++; | |
766 | } | |
767 | } | |
768 | ||
4ce001ab | 769 | static bool radeon_setup_enc_conn(struct drm_device *dev) |
771fe6b9 JG |
770 | { |
771 | struct radeon_device *rdev = dev->dev_private; | |
771fe6b9 JG |
772 | bool ret = false; |
773 | ||
774 | if (rdev->bios) { | |
775 | if (rdev->is_atom_bios) { | |
a084e6ee AD |
776 | ret = radeon_get_atom_connector_info_from_supported_devices_table(dev); |
777 | if (ret == false) | |
771fe6b9 | 778 | ret = radeon_get_atom_connector_info_from_object_table(dev); |
b9597a1c | 779 | } else { |
771fe6b9 | 780 | ret = radeon_get_legacy_connector_info_from_bios(dev); |
b9597a1c AD |
781 | if (ret == false) |
782 | ret = radeon_get_legacy_connector_info_from_table(dev); | |
783 | } | |
771fe6b9 JG |
784 | } else { |
785 | if (!ASIC_IS_AVIVO(rdev)) | |
786 | ret = radeon_get_legacy_connector_info_from_table(dev); | |
787 | } | |
788 | if (ret) { | |
1f3b6a45 | 789 | radeon_setup_encoder_clones(dev); |
771fe6b9 | 790 | radeon_print_display_setup(dev); |
771fe6b9 JG |
791 | } |
792 | ||
793 | return ret; | |
794 | } | |
795 | ||
796 | int radeon_ddc_get_modes(struct radeon_connector *radeon_connector) | |
797 | { | |
3c537889 AD |
798 | struct drm_device *dev = radeon_connector->base.dev; |
799 | struct radeon_device *rdev = dev->dev_private; | |
771fe6b9 JG |
800 | int ret = 0; |
801 | ||
26b5bc98 | 802 | /* on hw with routers, select right port */ |
fb939dfc AD |
803 | if (radeon_connector->router.ddc_valid) |
804 | radeon_router_select_ddc_port(radeon_connector); | |
26b5bc98 | 805 | |
0a9069d3 NOS |
806 | if (radeon_connector_encoder_get_dp_bridge_encoder_id(&radeon_connector->base) != |
807 | ENCODER_OBJECT_ID_NONE) { | |
379dfc25 | 808 | if (radeon_connector->ddc_bus->has_aux) |
0a9069d3 | 809 | radeon_connector->edid = drm_get_edid(&radeon_connector->base, |
379dfc25 | 810 | &radeon_connector->ddc_bus->aux.ddc); |
0a9069d3 NOS |
811 | } else if ((radeon_connector->base.connector_type == DRM_MODE_CONNECTOR_DisplayPort) || |
812 | (radeon_connector->base.connector_type == DRM_MODE_CONNECTOR_eDP)) { | |
746c1aa4 | 813 | struct radeon_connector_atom_dig *dig = radeon_connector->con_priv; |
b06947b5 | 814 | |
7a15cbd4 | 815 | if ((dig->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT || |
379dfc25 AD |
816 | dig->dp_sink_type == CONNECTOR_OBJECT_ID_eDP) && |
817 | radeon_connector->ddc_bus->has_aux) | |
b06947b5 | 818 | radeon_connector->edid = drm_get_edid(&radeon_connector->base, |
379dfc25 | 819 | &radeon_connector->ddc_bus->aux.ddc); |
b06947b5 AD |
820 | else if (radeon_connector->ddc_bus && !radeon_connector->edid) |
821 | radeon_connector->edid = drm_get_edid(&radeon_connector->base, | |
822 | &radeon_connector->ddc_bus->adapter); | |
823 | } else { | |
824 | if (radeon_connector->ddc_bus && !radeon_connector->edid) | |
825 | radeon_connector->edid = drm_get_edid(&radeon_connector->base, | |
826 | &radeon_connector->ddc_bus->adapter); | |
0294cf4f | 827 | } |
c324acd5 AD |
828 | |
829 | if (!radeon_connector->edid) { | |
830 | if (rdev->is_atom_bios) { | |
831 | /* some laptops provide a hardcoded edid in rom for LCDs */ | |
832 | if (((radeon_connector->base.connector_type == DRM_MODE_CONNECTOR_LVDS) || | |
833 | (radeon_connector->base.connector_type == DRM_MODE_CONNECTOR_eDP))) | |
834 | radeon_connector->edid = radeon_bios_get_hardcoded_edid(rdev); | |
835 | } else | |
836 | /* some servers provide a hardcoded edid in rom for KVMs */ | |
837 | radeon_connector->edid = radeon_bios_get_hardcoded_edid(rdev); | |
838 | } | |
0294cf4f AD |
839 | if (radeon_connector->edid) { |
840 | drm_mode_connector_update_edid_property(&radeon_connector->base, radeon_connector->edid); | |
841 | ret = drm_add_edid_modes(&radeon_connector->base, radeon_connector->edid); | |
16086279 | 842 | drm_edid_to_eld(&radeon_connector->base, radeon_connector->edid); |
771fe6b9 JG |
843 | return ret; |
844 | } | |
845 | drm_mode_connector_update_edid_property(&radeon_connector->base, NULL); | |
42dea5dd | 846 | return 0; |
771fe6b9 JG |
847 | } |
848 | ||
f523f74e | 849 | /* avivo */ |
f523f74e | 850 | |
32167016 CK |
851 | /** |
852 | * avivo_reduce_ratio - fractional number reduction | |
853 | * | |
854 | * @nom: nominator | |
855 | * @den: denominator | |
856 | * @nom_min: minimum value for nominator | |
857 | * @den_min: minimum value for denominator | |
858 | * | |
859 | * Find the greatest common divisor and apply it on both nominator and | |
860 | * denominator, but make nominator and denominator are at least as large | |
861 | * as their minimum values. | |
862 | */ | |
863 | static void avivo_reduce_ratio(unsigned *nom, unsigned *den, | |
864 | unsigned nom_min, unsigned den_min) | |
f523f74e | 865 | { |
32167016 CK |
866 | unsigned tmp; |
867 | ||
868 | /* reduce the numbers to a simpler ratio */ | |
869 | tmp = gcd(*nom, *den); | |
870 | *nom /= tmp; | |
871 | *den /= tmp; | |
872 | ||
873 | /* make sure nominator is large enough */ | |
874 | if (*nom < nom_min) { | |
875 | tmp = (nom_min + *nom - 1) / *nom; | |
876 | *nom *= tmp; | |
877 | *den *= tmp; | |
f523f74e AD |
878 | } |
879 | ||
32167016 CK |
880 | /* make sure the denominator is large enough */ |
881 | if (*den < den_min) { | |
882 | tmp = (den_min + *den - 1) / *den; | |
883 | *nom *= tmp; | |
884 | *den *= tmp; | |
f523f74e | 885 | } |
f523f74e AD |
886 | } |
887 | ||
c2fb3094 CK |
888 | /** |
889 | * avivo_get_fb_ref_div - feedback and ref divider calculation | |
890 | * | |
891 | * @nom: nominator | |
892 | * @den: denominator | |
893 | * @post_div: post divider | |
894 | * @fb_div_max: feedback divider maximum | |
895 | * @ref_div_max: reference divider maximum | |
896 | * @fb_div: resulting feedback divider | |
897 | * @ref_div: resulting reference divider | |
898 | * | |
899 | * Calculate feedback and reference divider for a given post divider. Makes | |
900 | * sure we stay within the limits. | |
901 | */ | |
902 | static void avivo_get_fb_ref_div(unsigned nom, unsigned den, unsigned post_div, | |
903 | unsigned fb_div_max, unsigned ref_div_max, | |
904 | unsigned *fb_div, unsigned *ref_div) | |
905 | { | |
906 | /* limit reference * post divider to a maximum */ | |
907 | ref_div_max = min(210 / post_div, ref_div_max); | |
908 | ||
909 | /* get matching reference and feedback divider */ | |
910 | *ref_div = min(max(DIV_ROUND_CLOSEST(den, post_div), 1u), ref_div_max); | |
911 | *fb_div = DIV_ROUND_CLOSEST(nom * *ref_div * post_div, den); | |
912 | ||
913 | /* limit fb divider to its maximum */ | |
914 | if (*fb_div > fb_div_max) { | |
915 | *ref_div = DIV_ROUND_CLOSEST(*ref_div * fb_div_max, *fb_div); | |
916 | *fb_div = fb_div_max; | |
917 | } | |
918 | } | |
919 | ||
32167016 CK |
920 | /** |
921 | * radeon_compute_pll_avivo - compute PLL paramaters | |
922 | * | |
923 | * @pll: information about the PLL | |
924 | * @dot_clock_p: resulting pixel clock | |
925 | * fb_div_p: resulting feedback divider | |
926 | * frac_fb_div_p: fractional part of the feedback divider | |
927 | * ref_div_p: resulting reference divider | |
928 | * post_div_p: resulting reference divider | |
929 | * | |
930 | * Try to calculate the PLL parameters to generate the given frequency: | |
931 | * dot_clock = (ref_freq * feedback_div) / (ref_div * post_div) | |
932 | */ | |
f523f74e AD |
933 | void radeon_compute_pll_avivo(struct radeon_pll *pll, |
934 | u32 freq, | |
935 | u32 *dot_clock_p, | |
936 | u32 *fb_div_p, | |
937 | u32 *frac_fb_div_p, | |
938 | u32 *ref_div_p, | |
939 | u32 *post_div_p) | |
940 | { | |
c2fb3094 CK |
941 | unsigned target_clock = pll->flags & RADEON_PLL_USE_FRAC_FB_DIV ? |
942 | freq : freq / 10; | |
943 | ||
32167016 CK |
944 | unsigned fb_div_min, fb_div_max, fb_div; |
945 | unsigned post_div_min, post_div_max, post_div; | |
946 | unsigned ref_div_min, ref_div_max, ref_div; | |
947 | unsigned post_div_best, diff_best; | |
f8a2645e | 948 | unsigned nom, den; |
f523f74e | 949 | |
32167016 CK |
950 | /* determine allowed feedback divider range */ |
951 | fb_div_min = pll->min_feedback_div; | |
952 | fb_div_max = pll->max_feedback_div; | |
f523f74e AD |
953 | |
954 | if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV) { | |
32167016 CK |
955 | fb_div_min *= 10; |
956 | fb_div_max *= 10; | |
957 | } | |
958 | ||
959 | /* determine allowed ref divider range */ | |
960 | if (pll->flags & RADEON_PLL_USE_REF_DIV) | |
961 | ref_div_min = pll->reference_div; | |
962 | else | |
963 | ref_div_min = pll->min_ref_div; | |
24315814 CK |
964 | |
965 | if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV && | |
966 | pll->flags & RADEON_PLL_USE_REF_DIV) | |
967 | ref_div_max = pll->reference_div; | |
968 | else | |
969 | ref_div_max = pll->max_ref_div; | |
32167016 CK |
970 | |
971 | /* determine allowed post divider range */ | |
972 | if (pll->flags & RADEON_PLL_USE_POST_DIV) { | |
973 | post_div_min = pll->post_div; | |
974 | post_div_max = pll->post_div; | |
975 | } else { | |
32167016 CK |
976 | unsigned vco_min, vco_max; |
977 | ||
978 | if (pll->flags & RADEON_PLL_IS_LCD) { | |
979 | vco_min = pll->lcd_pll_out_min; | |
980 | vco_max = pll->lcd_pll_out_max; | |
981 | } else { | |
982 | vco_min = pll->pll_out_min; | |
983 | vco_max = pll->pll_out_max; | |
f523f74e | 984 | } |
32167016 | 985 | |
c2fb3094 CK |
986 | if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV) { |
987 | vco_min *= 10; | |
988 | vco_max *= 10; | |
989 | } | |
990 | ||
32167016 CK |
991 | post_div_min = vco_min / target_clock; |
992 | if ((target_clock * post_div_min) < vco_min) | |
993 | ++post_div_min; | |
994 | if (post_div_min < pll->min_post_div) | |
995 | post_div_min = pll->min_post_div; | |
996 | ||
997 | post_div_max = vco_max / target_clock; | |
998 | if ((target_clock * post_div_max) > vco_max) | |
999 | --post_div_max; | |
1000 | if (post_div_max > pll->max_post_div) | |
1001 | post_div_max = pll->max_post_div; | |
1002 | } | |
1003 | ||
1004 | /* represent the searched ratio as fractional number */ | |
c2fb3094 | 1005 | nom = target_clock; |
32167016 CK |
1006 | den = pll->reference_freq; |
1007 | ||
1008 | /* reduce the numbers to a simpler ratio */ | |
1009 | avivo_reduce_ratio(&nom, &den, fb_div_min, post_div_min); | |
1010 | ||
1011 | /* now search for a post divider */ | |
1012 | if (pll->flags & RADEON_PLL_PREFER_MINM_OVER_MAXP) | |
1013 | post_div_best = post_div_min; | |
1014 | else | |
1015 | post_div_best = post_div_max; | |
1016 | diff_best = ~0; | |
1017 | ||
1018 | for (post_div = post_div_min; post_div <= post_div_max; ++post_div) { | |
c2fb3094 CK |
1019 | unsigned diff; |
1020 | avivo_get_fb_ref_div(nom, den, post_div, fb_div_max, | |
1021 | ref_div_max, &fb_div, &ref_div); | |
1022 | diff = abs(target_clock - (pll->reference_freq * fb_div) / | |
1023 | (ref_div * post_div)); | |
1024 | ||
32167016 CK |
1025 | if (diff < diff_best || (diff == diff_best && |
1026 | !(pll->flags & RADEON_PLL_PREFER_MINM_OVER_MAXP))) { | |
1027 | ||
1028 | post_div_best = post_div; | |
1029 | diff_best = diff; | |
f523f74e | 1030 | } |
32167016 CK |
1031 | } |
1032 | post_div = post_div_best; | |
1033 | ||
c2fb3094 CK |
1034 | /* get the feedback and reference divider for the optimal value */ |
1035 | avivo_get_fb_ref_div(nom, den, post_div, fb_div_max, ref_div_max, | |
1036 | &fb_div, &ref_div); | |
32167016 CK |
1037 | |
1038 | /* reduce the numbers to a simpler ratio once more */ | |
1039 | /* this also makes sure that the reference divider is large enough */ | |
1040 | avivo_reduce_ratio(&fb_div, &ref_div, fb_div_min, ref_div_min); | |
1041 | ||
1042 | /* and finally save the result */ | |
1043 | if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV) { | |
1044 | *fb_div_p = fb_div / 10; | |
1045 | *frac_fb_div_p = fb_div % 10; | |
f523f74e | 1046 | } else { |
32167016 CK |
1047 | *fb_div_p = fb_div; |
1048 | *frac_fb_div_p = 0; | |
f523f74e AD |
1049 | } |
1050 | ||
32167016 CK |
1051 | *dot_clock_p = ((pll->reference_freq * *fb_div_p * 10) + |
1052 | (pll->reference_freq * *frac_fb_div_p)) / | |
1053 | (ref_div * post_div * 10); | |
f523f74e AD |
1054 | *ref_div_p = ref_div; |
1055 | *post_div_p = post_div; | |
32167016 CK |
1056 | |
1057 | DRM_DEBUG_KMS("%d - %d, pll dividers - fb: %d.%d ref: %d, post %d\n", | |
c2fb3094 | 1058 | freq, *dot_clock_p * 10, *fb_div_p, *frac_fb_div_p, |
32167016 | 1059 | ref_div, post_div); |
f523f74e AD |
1060 | } |
1061 | ||
1062 | /* pre-avivo */ | |
771fe6b9 JG |
1063 | static inline uint32_t radeon_div(uint64_t n, uint32_t d) |
1064 | { | |
1065 | uint64_t mod; | |
1066 | ||
1067 | n += d / 2; | |
1068 | ||
1069 | mod = do_div(n, d); | |
1070 | return n; | |
1071 | } | |
1072 | ||
f523f74e AD |
1073 | void radeon_compute_pll_legacy(struct radeon_pll *pll, |
1074 | uint64_t freq, | |
1075 | uint32_t *dot_clock_p, | |
1076 | uint32_t *fb_div_p, | |
1077 | uint32_t *frac_fb_div_p, | |
1078 | uint32_t *ref_div_p, | |
1079 | uint32_t *post_div_p) | |
771fe6b9 JG |
1080 | { |
1081 | uint32_t min_ref_div = pll->min_ref_div; | |
1082 | uint32_t max_ref_div = pll->max_ref_div; | |
fc10332b AD |
1083 | uint32_t min_post_div = pll->min_post_div; |
1084 | uint32_t max_post_div = pll->max_post_div; | |
771fe6b9 JG |
1085 | uint32_t min_fractional_feed_div = 0; |
1086 | uint32_t max_fractional_feed_div = 0; | |
1087 | uint32_t best_vco = pll->best_vco; | |
1088 | uint32_t best_post_div = 1; | |
1089 | uint32_t best_ref_div = 1; | |
1090 | uint32_t best_feedback_div = 1; | |
1091 | uint32_t best_frac_feedback_div = 0; | |
1092 | uint32_t best_freq = -1; | |
1093 | uint32_t best_error = 0xffffffff; | |
1094 | uint32_t best_vco_diff = 1; | |
1095 | uint32_t post_div; | |
86cb2bbf | 1096 | u32 pll_out_min, pll_out_max; |
771fe6b9 | 1097 | |
d9fdaafb | 1098 | DRM_DEBUG_KMS("PLL freq %llu %u %u\n", freq, pll->min_ref_div, pll->max_ref_div); |
771fe6b9 JG |
1099 | freq = freq * 1000; |
1100 | ||
86cb2bbf AD |
1101 | if (pll->flags & RADEON_PLL_IS_LCD) { |
1102 | pll_out_min = pll->lcd_pll_out_min; | |
1103 | pll_out_max = pll->lcd_pll_out_max; | |
1104 | } else { | |
1105 | pll_out_min = pll->pll_out_min; | |
1106 | pll_out_max = pll->pll_out_max; | |
1107 | } | |
1108 | ||
619efb10 AD |
1109 | if (pll_out_min > 64800) |
1110 | pll_out_min = 64800; | |
1111 | ||
fc10332b | 1112 | if (pll->flags & RADEON_PLL_USE_REF_DIV) |
771fe6b9 JG |
1113 | min_ref_div = max_ref_div = pll->reference_div; |
1114 | else { | |
1115 | while (min_ref_div < max_ref_div-1) { | |
1116 | uint32_t mid = (min_ref_div + max_ref_div) / 2; | |
1117 | uint32_t pll_in = pll->reference_freq / mid; | |
1118 | if (pll_in < pll->pll_in_min) | |
1119 | max_ref_div = mid; | |
1120 | else if (pll_in > pll->pll_in_max) | |
1121 | min_ref_div = mid; | |
1122 | else | |
1123 | break; | |
1124 | } | |
1125 | } | |
1126 | ||
fc10332b AD |
1127 | if (pll->flags & RADEON_PLL_USE_POST_DIV) |
1128 | min_post_div = max_post_div = pll->post_div; | |
1129 | ||
1130 | if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV) { | |
771fe6b9 JG |
1131 | min_fractional_feed_div = pll->min_frac_feedback_div; |
1132 | max_fractional_feed_div = pll->max_frac_feedback_div; | |
1133 | } | |
1134 | ||
bd6a60af | 1135 | for (post_div = max_post_div; post_div >= min_post_div; --post_div) { |
771fe6b9 JG |
1136 | uint32_t ref_div; |
1137 | ||
fc10332b | 1138 | if ((pll->flags & RADEON_PLL_NO_ODD_POST_DIV) && (post_div & 1)) |
771fe6b9 JG |
1139 | continue; |
1140 | ||
1141 | /* legacy radeons only have a few post_divs */ | |
fc10332b | 1142 | if (pll->flags & RADEON_PLL_LEGACY) { |
771fe6b9 JG |
1143 | if ((post_div == 5) || |
1144 | (post_div == 7) || | |
1145 | (post_div == 9) || | |
1146 | (post_div == 10) || | |
1147 | (post_div == 11) || | |
1148 | (post_div == 13) || | |
1149 | (post_div == 14) || | |
1150 | (post_div == 15)) | |
1151 | continue; | |
1152 | } | |
1153 | ||
1154 | for (ref_div = min_ref_div; ref_div <= max_ref_div; ++ref_div) { | |
1155 | uint32_t feedback_div, current_freq = 0, error, vco_diff; | |
1156 | uint32_t pll_in = pll->reference_freq / ref_div; | |
1157 | uint32_t min_feed_div = pll->min_feedback_div; | |
1158 | uint32_t max_feed_div = pll->max_feedback_div + 1; | |
1159 | ||
1160 | if (pll_in < pll->pll_in_min || pll_in > pll->pll_in_max) | |
1161 | continue; | |
1162 | ||
1163 | while (min_feed_div < max_feed_div) { | |
1164 | uint32_t vco; | |
1165 | uint32_t min_frac_feed_div = min_fractional_feed_div; | |
1166 | uint32_t max_frac_feed_div = max_fractional_feed_div + 1; | |
1167 | uint32_t frac_feedback_div; | |
1168 | uint64_t tmp; | |
1169 | ||
1170 | feedback_div = (min_feed_div + max_feed_div) / 2; | |
1171 | ||
1172 | tmp = (uint64_t)pll->reference_freq * feedback_div; | |
1173 | vco = radeon_div(tmp, ref_div); | |
1174 | ||
86cb2bbf | 1175 | if (vco < pll_out_min) { |
771fe6b9 JG |
1176 | min_feed_div = feedback_div + 1; |
1177 | continue; | |
86cb2bbf | 1178 | } else if (vco > pll_out_max) { |
771fe6b9 JG |
1179 | max_feed_div = feedback_div; |
1180 | continue; | |
1181 | } | |
1182 | ||
1183 | while (min_frac_feed_div < max_frac_feed_div) { | |
1184 | frac_feedback_div = (min_frac_feed_div + max_frac_feed_div) / 2; | |
1185 | tmp = (uint64_t)pll->reference_freq * 10000 * feedback_div; | |
1186 | tmp += (uint64_t)pll->reference_freq * 1000 * frac_feedback_div; | |
1187 | current_freq = radeon_div(tmp, ref_div * post_div); | |
1188 | ||
fc10332b | 1189 | if (pll->flags & RADEON_PLL_PREFER_CLOSEST_LOWER) { |
167ffc44 DC |
1190 | if (freq < current_freq) |
1191 | error = 0xffffffff; | |
1192 | else | |
1193 | error = freq - current_freq; | |
d0e275a9 AD |
1194 | } else |
1195 | error = abs(current_freq - freq); | |
771fe6b9 JG |
1196 | vco_diff = abs(vco - best_vco); |
1197 | ||
1198 | if ((best_vco == 0 && error < best_error) || | |
1199 | (best_vco != 0 && | |
167ffc44 | 1200 | ((best_error > 100 && error < best_error - 100) || |
5480f727 | 1201 | (abs(error - best_error) < 100 && vco_diff < best_vco_diff)))) { |
771fe6b9 JG |
1202 | best_post_div = post_div; |
1203 | best_ref_div = ref_div; | |
1204 | best_feedback_div = feedback_div; | |
1205 | best_frac_feedback_div = frac_feedback_div; | |
1206 | best_freq = current_freq; | |
1207 | best_error = error; | |
1208 | best_vco_diff = vco_diff; | |
5480f727 DA |
1209 | } else if (current_freq == freq) { |
1210 | if (best_freq == -1) { | |
1211 | best_post_div = post_div; | |
1212 | best_ref_div = ref_div; | |
1213 | best_feedback_div = feedback_div; | |
1214 | best_frac_feedback_div = frac_feedback_div; | |
1215 | best_freq = current_freq; | |
1216 | best_error = error; | |
1217 | best_vco_diff = vco_diff; | |
1218 | } else if (((pll->flags & RADEON_PLL_PREFER_LOW_REF_DIV) && (ref_div < best_ref_div)) || | |
1219 | ((pll->flags & RADEON_PLL_PREFER_HIGH_REF_DIV) && (ref_div > best_ref_div)) || | |
1220 | ((pll->flags & RADEON_PLL_PREFER_LOW_FB_DIV) && (feedback_div < best_feedback_div)) || | |
1221 | ((pll->flags & RADEON_PLL_PREFER_HIGH_FB_DIV) && (feedback_div > best_feedback_div)) || | |
1222 | ((pll->flags & RADEON_PLL_PREFER_LOW_POST_DIV) && (post_div < best_post_div)) || | |
1223 | ((pll->flags & RADEON_PLL_PREFER_HIGH_POST_DIV) && (post_div > best_post_div))) { | |
1224 | best_post_div = post_div; | |
1225 | best_ref_div = ref_div; | |
1226 | best_feedback_div = feedback_div; | |
1227 | best_frac_feedback_div = frac_feedback_div; | |
1228 | best_freq = current_freq; | |
1229 | best_error = error; | |
1230 | best_vco_diff = vco_diff; | |
1231 | } | |
771fe6b9 JG |
1232 | } |
1233 | if (current_freq < freq) | |
1234 | min_frac_feed_div = frac_feedback_div + 1; | |
1235 | else | |
1236 | max_frac_feed_div = frac_feedback_div; | |
1237 | } | |
1238 | if (current_freq < freq) | |
1239 | min_feed_div = feedback_div + 1; | |
1240 | else | |
1241 | max_feed_div = feedback_div; | |
1242 | } | |
1243 | } | |
1244 | } | |
1245 | ||
1246 | *dot_clock_p = best_freq / 10000; | |
1247 | *fb_div_p = best_feedback_div; | |
1248 | *frac_fb_div_p = best_frac_feedback_div; | |
1249 | *ref_div_p = best_ref_div; | |
1250 | *post_div_p = best_post_div; | |
bbb0aef5 JP |
1251 | DRM_DEBUG_KMS("%lld %d, pll dividers - fb: %d.%d ref: %d, post %d\n", |
1252 | (long long)freq, | |
1253 | best_freq / 1000, best_feedback_div, best_frac_feedback_div, | |
51d4bf84 AD |
1254 | best_ref_div, best_post_div); |
1255 | ||
771fe6b9 JG |
1256 | } |
1257 | ||
1258 | static void radeon_user_framebuffer_destroy(struct drm_framebuffer *fb) | |
1259 | { | |
1260 | struct radeon_framebuffer *radeon_fb = to_radeon_framebuffer(fb); | |
771fe6b9 | 1261 | |
29d08b3e | 1262 | if (radeon_fb->obj) { |
bc9025bd | 1263 | drm_gem_object_unreference_unlocked(radeon_fb->obj); |
29d08b3e | 1264 | } |
771fe6b9 JG |
1265 | drm_framebuffer_cleanup(fb); |
1266 | kfree(radeon_fb); | |
1267 | } | |
1268 | ||
1269 | static int radeon_user_framebuffer_create_handle(struct drm_framebuffer *fb, | |
1270 | struct drm_file *file_priv, | |
1271 | unsigned int *handle) | |
1272 | { | |
1273 | struct radeon_framebuffer *radeon_fb = to_radeon_framebuffer(fb); | |
1274 | ||
1275 | return drm_gem_handle_create(file_priv, radeon_fb->obj, handle); | |
1276 | } | |
1277 | ||
1278 | static const struct drm_framebuffer_funcs radeon_fb_funcs = { | |
1279 | .destroy = radeon_user_framebuffer_destroy, | |
1280 | .create_handle = radeon_user_framebuffer_create_handle, | |
1281 | }; | |
1282 | ||
aaefcd42 | 1283 | int |
38651674 DA |
1284 | radeon_framebuffer_init(struct drm_device *dev, |
1285 | struct radeon_framebuffer *rfb, | |
308e5bcb | 1286 | struct drm_mode_fb_cmd2 *mode_cmd, |
38651674 | 1287 | struct drm_gem_object *obj) |
771fe6b9 | 1288 | { |
aaefcd42 | 1289 | int ret; |
38651674 | 1290 | rfb->obj = obj; |
c7d73f6a | 1291 | drm_helper_mode_fill_fb_struct(&rfb->base, mode_cmd); |
aaefcd42 DA |
1292 | ret = drm_framebuffer_init(dev, &rfb->base, &radeon_fb_funcs); |
1293 | if (ret) { | |
1294 | rfb->obj = NULL; | |
1295 | return ret; | |
1296 | } | |
aaefcd42 | 1297 | return 0; |
771fe6b9 JG |
1298 | } |
1299 | ||
1300 | static struct drm_framebuffer * | |
1301 | radeon_user_framebuffer_create(struct drm_device *dev, | |
1302 | struct drm_file *file_priv, | |
308e5bcb | 1303 | struct drm_mode_fb_cmd2 *mode_cmd) |
771fe6b9 JG |
1304 | { |
1305 | struct drm_gem_object *obj; | |
38651674 | 1306 | struct radeon_framebuffer *radeon_fb; |
aaefcd42 | 1307 | int ret; |
771fe6b9 | 1308 | |
308e5bcb | 1309 | obj = drm_gem_object_lookup(dev, file_priv, mode_cmd->handles[0]); |
7e71c9e2 JG |
1310 | if (obj == NULL) { |
1311 | dev_err(&dev->pdev->dev, "No GEM object associated to handle 0x%08X, " | |
308e5bcb | 1312 | "can't create framebuffer\n", mode_cmd->handles[0]); |
cce13ff7 | 1313 | return ERR_PTR(-ENOENT); |
7e71c9e2 | 1314 | } |
38651674 DA |
1315 | |
1316 | radeon_fb = kzalloc(sizeof(*radeon_fb), GFP_KERNEL); | |
f2d68cf4 | 1317 | if (radeon_fb == NULL) { |
1318 | drm_gem_object_unreference_unlocked(obj); | |
cce13ff7 | 1319 | return ERR_PTR(-ENOMEM); |
f2d68cf4 | 1320 | } |
38651674 | 1321 | |
aaefcd42 DA |
1322 | ret = radeon_framebuffer_init(dev, radeon_fb, mode_cmd, obj); |
1323 | if (ret) { | |
1324 | kfree(radeon_fb); | |
1325 | drm_gem_object_unreference_unlocked(obj); | |
b2f4b03f | 1326 | return ERR_PTR(ret); |
aaefcd42 | 1327 | } |
38651674 DA |
1328 | |
1329 | return &radeon_fb->base; | |
771fe6b9 JG |
1330 | } |
1331 | ||
eb1f8e4f DA |
1332 | static void radeon_output_poll_changed(struct drm_device *dev) |
1333 | { | |
1334 | struct radeon_device *rdev = dev->dev_private; | |
1335 | radeon_fb_output_poll_changed(rdev); | |
1336 | } | |
1337 | ||
771fe6b9 JG |
1338 | static const struct drm_mode_config_funcs radeon_mode_funcs = { |
1339 | .fb_create = radeon_user_framebuffer_create, | |
eb1f8e4f | 1340 | .output_poll_changed = radeon_output_poll_changed |
771fe6b9 JG |
1341 | }; |
1342 | ||
445282db DA |
1343 | static struct drm_prop_enum_list radeon_tmds_pll_enum_list[] = |
1344 | { { 0, "driver" }, | |
1345 | { 1, "bios" }, | |
1346 | }; | |
1347 | ||
1348 | static struct drm_prop_enum_list radeon_tv_std_enum_list[] = | |
1349 | { { TV_STD_NTSC, "ntsc" }, | |
1350 | { TV_STD_PAL, "pal" }, | |
1351 | { TV_STD_PAL_M, "pal-m" }, | |
1352 | { TV_STD_PAL_60, "pal-60" }, | |
1353 | { TV_STD_NTSC_J, "ntsc-j" }, | |
1354 | { TV_STD_SCART_PAL, "scart-pal" }, | |
1355 | { TV_STD_PAL_CN, "pal-cn" }, | |
1356 | { TV_STD_SECAM, "secam" }, | |
1357 | }; | |
1358 | ||
5b1714d3 AD |
1359 | static struct drm_prop_enum_list radeon_underscan_enum_list[] = |
1360 | { { UNDERSCAN_OFF, "off" }, | |
1361 | { UNDERSCAN_ON, "on" }, | |
1362 | { UNDERSCAN_AUTO, "auto" }, | |
1363 | }; | |
1364 | ||
8666c076 AD |
1365 | static struct drm_prop_enum_list radeon_audio_enum_list[] = |
1366 | { { RADEON_AUDIO_DISABLE, "off" }, | |
1367 | { RADEON_AUDIO_ENABLE, "on" }, | |
1368 | { RADEON_AUDIO_AUTO, "auto" }, | |
1369 | }; | |
1370 | ||
6214bb74 AD |
1371 | /* XXX support different dither options? spatial, temporal, both, etc. */ |
1372 | static struct drm_prop_enum_list radeon_dither_enum_list[] = | |
1373 | { { RADEON_FMT_DITHER_DISABLE, "off" }, | |
1374 | { RADEON_FMT_DITHER_ENABLE, "on" }, | |
1375 | }; | |
1376 | ||
d79766fa | 1377 | static int radeon_modeset_create_props(struct radeon_device *rdev) |
445282db | 1378 | { |
4a67d391 | 1379 | int sz; |
445282db DA |
1380 | |
1381 | if (rdev->is_atom_bios) { | |
1382 | rdev->mode_info.coherent_mode_property = | |
d9bc3c02 | 1383 | drm_property_create_range(rdev->ddev, 0 , "coherent", 0, 1); |
445282db DA |
1384 | if (!rdev->mode_info.coherent_mode_property) |
1385 | return -ENOMEM; | |
445282db DA |
1386 | } |
1387 | ||
1388 | if (!ASIC_IS_AVIVO(rdev)) { | |
1389 | sz = ARRAY_SIZE(radeon_tmds_pll_enum_list); | |
1390 | rdev->mode_info.tmds_pll_property = | |
4a67d391 SH |
1391 | drm_property_create_enum(rdev->ddev, 0, |
1392 | "tmds_pll", | |
1393 | radeon_tmds_pll_enum_list, sz); | |
445282db DA |
1394 | } |
1395 | ||
1396 | rdev->mode_info.load_detect_property = | |
d9bc3c02 | 1397 | drm_property_create_range(rdev->ddev, 0, "load detection", 0, 1); |
445282db DA |
1398 | if (!rdev->mode_info.load_detect_property) |
1399 | return -ENOMEM; | |
445282db DA |
1400 | |
1401 | drm_mode_create_scaling_mode_property(rdev->ddev); | |
1402 | ||
1403 | sz = ARRAY_SIZE(radeon_tv_std_enum_list); | |
1404 | rdev->mode_info.tv_std_property = | |
4a67d391 SH |
1405 | drm_property_create_enum(rdev->ddev, 0, |
1406 | "tv standard", | |
1407 | radeon_tv_std_enum_list, sz); | |
445282db | 1408 | |
5b1714d3 AD |
1409 | sz = ARRAY_SIZE(radeon_underscan_enum_list); |
1410 | rdev->mode_info.underscan_property = | |
4a67d391 SH |
1411 | drm_property_create_enum(rdev->ddev, 0, |
1412 | "underscan", | |
1413 | radeon_underscan_enum_list, sz); | |
5b1714d3 | 1414 | |
5bccf5e3 | 1415 | rdev->mode_info.underscan_hborder_property = |
d9bc3c02 SH |
1416 | drm_property_create_range(rdev->ddev, 0, |
1417 | "underscan hborder", 0, 128); | |
5bccf5e3 MG |
1418 | if (!rdev->mode_info.underscan_hborder_property) |
1419 | return -ENOMEM; | |
5bccf5e3 MG |
1420 | |
1421 | rdev->mode_info.underscan_vborder_property = | |
d9bc3c02 SH |
1422 | drm_property_create_range(rdev->ddev, 0, |
1423 | "underscan vborder", 0, 128); | |
5bccf5e3 MG |
1424 | if (!rdev->mode_info.underscan_vborder_property) |
1425 | return -ENOMEM; | |
5bccf5e3 | 1426 | |
8666c076 AD |
1427 | sz = ARRAY_SIZE(radeon_audio_enum_list); |
1428 | rdev->mode_info.audio_property = | |
1429 | drm_property_create_enum(rdev->ddev, 0, | |
1430 | "audio", | |
1431 | radeon_audio_enum_list, sz); | |
1432 | ||
6214bb74 AD |
1433 | sz = ARRAY_SIZE(radeon_dither_enum_list); |
1434 | rdev->mode_info.dither_property = | |
1435 | drm_property_create_enum(rdev->ddev, 0, | |
1436 | "dither", | |
1437 | radeon_dither_enum_list, sz); | |
1438 | ||
445282db DA |
1439 | return 0; |
1440 | } | |
1441 | ||
f46c0120 AD |
1442 | void radeon_update_display_priority(struct radeon_device *rdev) |
1443 | { | |
1444 | /* adjustment options for the display watermarks */ | |
1445 | if ((radeon_disp_priority == 0) || (radeon_disp_priority > 2)) { | |
1446 | /* set display priority to high for r3xx, rv515 chips | |
1447 | * this avoids flickering due to underflow to the | |
1448 | * display controllers during heavy acceleration. | |
45737447 AD |
1449 | * Don't force high on rs4xx igp chips as it seems to |
1450 | * affect the sound card. See kernel bug 15982. | |
f46c0120 | 1451 | */ |
45737447 AD |
1452 | if ((ASIC_IS_R300(rdev) || (rdev->family == CHIP_RV515)) && |
1453 | !(rdev->flags & RADEON_IS_IGP)) | |
f46c0120 AD |
1454 | rdev->disp_priority = 2; |
1455 | else | |
1456 | rdev->disp_priority = 0; | |
1457 | } else | |
1458 | rdev->disp_priority = radeon_disp_priority; | |
1459 | ||
1460 | } | |
1461 | ||
0783986a AD |
1462 | /* |
1463 | * Allocate hdmi structs and determine register offsets | |
1464 | */ | |
1465 | static void radeon_afmt_init(struct radeon_device *rdev) | |
1466 | { | |
1467 | int i; | |
1468 | ||
1469 | for (i = 0; i < RADEON_MAX_AFMT_BLOCKS; i++) | |
1470 | rdev->mode_info.afmt[i] = NULL; | |
1471 | ||
b530602f AD |
1472 | if (ASIC_IS_NODCE(rdev)) { |
1473 | /* nothing to do */ | |
0783986a | 1474 | } else if (ASIC_IS_DCE4(rdev)) { |
a4d39e68 RM |
1475 | static uint32_t eg_offsets[] = { |
1476 | EVERGREEN_CRTC0_REGISTER_OFFSET, | |
1477 | EVERGREEN_CRTC1_REGISTER_OFFSET, | |
1478 | EVERGREEN_CRTC2_REGISTER_OFFSET, | |
1479 | EVERGREEN_CRTC3_REGISTER_OFFSET, | |
1480 | EVERGREEN_CRTC4_REGISTER_OFFSET, | |
1481 | EVERGREEN_CRTC5_REGISTER_OFFSET, | |
b530602f | 1482 | 0x13830 - 0x7030, |
a4d39e68 RM |
1483 | }; |
1484 | int num_afmt; | |
1485 | ||
b530602f AD |
1486 | /* DCE8 has 7 audio blocks tied to DIG encoders */ |
1487 | /* DCE6 has 6 audio blocks tied to DIG encoders */ | |
0783986a AD |
1488 | /* DCE4/5 has 6 audio blocks tied to DIG encoders */ |
1489 | /* DCE4.1 has 2 audio blocks tied to DIG encoders */ | |
b530602f AD |
1490 | if (ASIC_IS_DCE8(rdev)) |
1491 | num_afmt = 7; | |
1492 | else if (ASIC_IS_DCE6(rdev)) | |
1493 | num_afmt = 6; | |
1494 | else if (ASIC_IS_DCE5(rdev)) | |
a4d39e68 RM |
1495 | num_afmt = 6; |
1496 | else if (ASIC_IS_DCE41(rdev)) | |
1497 | num_afmt = 2; | |
1498 | else /* DCE4 */ | |
1499 | num_afmt = 6; | |
1500 | ||
1501 | BUG_ON(num_afmt > ARRAY_SIZE(eg_offsets)); | |
1502 | for (i = 0; i < num_afmt; i++) { | |
1503 | rdev->mode_info.afmt[i] = kzalloc(sizeof(struct radeon_afmt), GFP_KERNEL); | |
1504 | if (rdev->mode_info.afmt[i]) { | |
1505 | rdev->mode_info.afmt[i]->offset = eg_offsets[i]; | |
1506 | rdev->mode_info.afmt[i]->id = i; | |
0783986a AD |
1507 | } |
1508 | } | |
1509 | } else if (ASIC_IS_DCE3(rdev)) { | |
1510 | /* DCE3.x has 2 audio blocks tied to DIG encoders */ | |
1511 | rdev->mode_info.afmt[0] = kzalloc(sizeof(struct radeon_afmt), GFP_KERNEL); | |
1512 | if (rdev->mode_info.afmt[0]) { | |
1513 | rdev->mode_info.afmt[0]->offset = DCE3_HDMI_OFFSET0; | |
1514 | rdev->mode_info.afmt[0]->id = 0; | |
1515 | } | |
1516 | rdev->mode_info.afmt[1] = kzalloc(sizeof(struct radeon_afmt), GFP_KERNEL); | |
1517 | if (rdev->mode_info.afmt[1]) { | |
1518 | rdev->mode_info.afmt[1]->offset = DCE3_HDMI_OFFSET1; | |
1519 | rdev->mode_info.afmt[1]->id = 1; | |
1520 | } | |
1521 | } else if (ASIC_IS_DCE2(rdev)) { | |
1522 | /* DCE2 has at least 1 routable audio block */ | |
1523 | rdev->mode_info.afmt[0] = kzalloc(sizeof(struct radeon_afmt), GFP_KERNEL); | |
1524 | if (rdev->mode_info.afmt[0]) { | |
1525 | rdev->mode_info.afmt[0]->offset = DCE2_HDMI_OFFSET0; | |
1526 | rdev->mode_info.afmt[0]->id = 0; | |
1527 | } | |
1528 | /* r6xx has 2 routable audio blocks */ | |
1529 | if (rdev->family >= CHIP_R600) { | |
1530 | rdev->mode_info.afmt[1] = kzalloc(sizeof(struct radeon_afmt), GFP_KERNEL); | |
1531 | if (rdev->mode_info.afmt[1]) { | |
1532 | rdev->mode_info.afmt[1]->offset = DCE2_HDMI_OFFSET1; | |
1533 | rdev->mode_info.afmt[1]->id = 1; | |
1534 | } | |
1535 | } | |
1536 | } | |
1537 | } | |
1538 | ||
1539 | static void radeon_afmt_fini(struct radeon_device *rdev) | |
1540 | { | |
1541 | int i; | |
1542 | ||
1543 | for (i = 0; i < RADEON_MAX_AFMT_BLOCKS; i++) { | |
1544 | kfree(rdev->mode_info.afmt[i]); | |
1545 | rdev->mode_info.afmt[i] = NULL; | |
1546 | } | |
1547 | } | |
1548 | ||
771fe6b9 JG |
1549 | int radeon_modeset_init(struct radeon_device *rdev) |
1550 | { | |
18917b60 | 1551 | int i; |
771fe6b9 JG |
1552 | int ret; |
1553 | ||
1554 | drm_mode_config_init(rdev->ddev); | |
1555 | rdev->mode_info.mode_config_initialized = true; | |
1556 | ||
e6ecefaa | 1557 | rdev->ddev->mode_config.funcs = &radeon_mode_funcs; |
771fe6b9 | 1558 | |
881dd74e AD |
1559 | if (ASIC_IS_DCE5(rdev)) { |
1560 | rdev->ddev->mode_config.max_width = 16384; | |
1561 | rdev->ddev->mode_config.max_height = 16384; | |
1562 | } else if (ASIC_IS_AVIVO(rdev)) { | |
771fe6b9 JG |
1563 | rdev->ddev->mode_config.max_width = 8192; |
1564 | rdev->ddev->mode_config.max_height = 8192; | |
1565 | } else { | |
1566 | rdev->ddev->mode_config.max_width = 4096; | |
1567 | rdev->ddev->mode_config.max_height = 4096; | |
1568 | } | |
1569 | ||
019d96cb DA |
1570 | rdev->ddev->mode_config.preferred_depth = 24; |
1571 | rdev->ddev->mode_config.prefer_shadow = 1; | |
1572 | ||
771fe6b9 JG |
1573 | rdev->ddev->mode_config.fb_base = rdev->mc.aper_base; |
1574 | ||
445282db DA |
1575 | ret = radeon_modeset_create_props(rdev); |
1576 | if (ret) { | |
1577 | return ret; | |
1578 | } | |
dfee5614 | 1579 | |
f376b94f AD |
1580 | /* init i2c buses */ |
1581 | radeon_i2c_init(rdev); | |
1582 | ||
3c537889 AD |
1583 | /* check combios for a valid hardcoded EDID - Sun servers */ |
1584 | if (!rdev->is_atom_bios) { | |
1585 | /* check for hardcoded EDID in BIOS */ | |
1586 | radeon_combios_check_hardcoded_edid(rdev); | |
1587 | } | |
1588 | ||
dfee5614 | 1589 | /* allocate crtcs */ |
18917b60 | 1590 | for (i = 0; i < rdev->num_crtc; i++) { |
771fe6b9 JG |
1591 | radeon_crtc_init(rdev->ddev, i); |
1592 | } | |
1593 | ||
1594 | /* okay we should have all the bios connectors */ | |
1595 | ret = radeon_setup_enc_conn(rdev->ddev); | |
1596 | if (!ret) { | |
1597 | return ret; | |
1598 | } | |
ac89af1e | 1599 | |
3fa47d9e AD |
1600 | /* init dig PHYs, disp eng pll */ |
1601 | if (rdev->is_atom_bios) { | |
ac89af1e | 1602 | radeon_atom_encoder_init(rdev); |
f3f1f03e | 1603 | radeon_atom_disp_eng_pll_init(rdev); |
3fa47d9e | 1604 | } |
ac89af1e | 1605 | |
d4877cf2 AD |
1606 | /* initialize hpd */ |
1607 | radeon_hpd_init(rdev); | |
38651674 | 1608 | |
0783986a AD |
1609 | /* setup afmt */ |
1610 | radeon_afmt_init(rdev); | |
1611 | ||
38651674 | 1612 | radeon_fbdev_init(rdev); |
eb1f8e4f DA |
1613 | drm_kms_helper_poll_init(rdev->ddev); |
1614 | ||
6c7bccea AD |
1615 | if (rdev->pm.dpm_enabled) { |
1616 | /* do dpm late init */ | |
1617 | ret = radeon_pm_late_init(rdev); | |
1618 | if (ret) { | |
1619 | rdev->pm.dpm_enabled = false; | |
1620 | DRM_ERROR("radeon_pm_late_init failed, disabling dpm\n"); | |
1621 | } | |
1622 | /* set the dpm state for PX since there won't be | |
1623 | * a modeset to call this. | |
1624 | */ | |
1625 | radeon_pm_compute_clocks(rdev); | |
1626 | } | |
1627 | ||
771fe6b9 JG |
1628 | return 0; |
1629 | } | |
1630 | ||
1631 | void radeon_modeset_fini(struct radeon_device *rdev) | |
1632 | { | |
38651674 | 1633 | radeon_fbdev_fini(rdev); |
3c537889 AD |
1634 | kfree(rdev->mode_info.bios_hardcoded_edid); |
1635 | ||
771fe6b9 | 1636 | if (rdev->mode_info.mode_config_initialized) { |
0783986a | 1637 | radeon_afmt_fini(rdev); |
eb1f8e4f | 1638 | drm_kms_helper_poll_fini(rdev->ddev); |
d4877cf2 | 1639 | radeon_hpd_fini(rdev); |
771fe6b9 JG |
1640 | drm_mode_config_cleanup(rdev->ddev); |
1641 | rdev->mode_info.mode_config_initialized = false; | |
1642 | } | |
f376b94f AD |
1643 | /* free i2c buses */ |
1644 | radeon_i2c_fini(rdev); | |
771fe6b9 JG |
1645 | } |
1646 | ||
e811f5ae | 1647 | static bool is_hdtv_mode(const struct drm_display_mode *mode) |
039ed2d9 AD |
1648 | { |
1649 | /* try and guess if this is a tv or a monitor */ | |
1650 | if ((mode->vdisplay == 480 && mode->hdisplay == 720) || /* 480p */ | |
1651 | (mode->vdisplay == 576) || /* 576p */ | |
1652 | (mode->vdisplay == 720) || /* 720p */ | |
1653 | (mode->vdisplay == 1080)) /* 1080p */ | |
1654 | return true; | |
1655 | else | |
1656 | return false; | |
1657 | } | |
1658 | ||
c93bb85b | 1659 | bool radeon_crtc_scaling_mode_fixup(struct drm_crtc *crtc, |
e811f5ae | 1660 | const struct drm_display_mode *mode, |
c93bb85b | 1661 | struct drm_display_mode *adjusted_mode) |
771fe6b9 | 1662 | { |
c93bb85b | 1663 | struct drm_device *dev = crtc->dev; |
5b1714d3 | 1664 | struct radeon_device *rdev = dev->dev_private; |
c93bb85b JG |
1665 | struct drm_encoder *encoder; |
1666 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); | |
1667 | struct radeon_encoder *radeon_encoder; | |
5b1714d3 AD |
1668 | struct drm_connector *connector; |
1669 | struct radeon_connector *radeon_connector; | |
c93bb85b | 1670 | bool first = true; |
d65d65b1 AD |
1671 | u32 src_v = 1, dst_v = 1; |
1672 | u32 src_h = 1, dst_h = 1; | |
771fe6b9 | 1673 | |
5b1714d3 AD |
1674 | radeon_crtc->h_border = 0; |
1675 | radeon_crtc->v_border = 0; | |
1676 | ||
c93bb85b | 1677 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { |
c93bb85b JG |
1678 | if (encoder->crtc != crtc) |
1679 | continue; | |
d65d65b1 | 1680 | radeon_encoder = to_radeon_encoder(encoder); |
5b1714d3 AD |
1681 | connector = radeon_get_connector_for_encoder(encoder); |
1682 | radeon_connector = to_radeon_connector(connector); | |
1683 | ||
c93bb85b | 1684 | if (first) { |
80297e87 AD |
1685 | /* set scaling */ |
1686 | if (radeon_encoder->rmx_type == RMX_OFF) | |
1687 | radeon_crtc->rmx_type = RMX_OFF; | |
1688 | else if (mode->hdisplay < radeon_encoder->native_mode.hdisplay || | |
1689 | mode->vdisplay < radeon_encoder->native_mode.vdisplay) | |
1690 | radeon_crtc->rmx_type = radeon_encoder->rmx_type; | |
1691 | else | |
1692 | radeon_crtc->rmx_type = RMX_OFF; | |
1693 | /* copy native mode */ | |
c93bb85b | 1694 | memcpy(&radeon_crtc->native_mode, |
80297e87 | 1695 | &radeon_encoder->native_mode, |
de2103e4 | 1696 | sizeof(struct drm_display_mode)); |
ff32a59d AD |
1697 | src_v = crtc->mode.vdisplay; |
1698 | dst_v = radeon_crtc->native_mode.vdisplay; | |
1699 | src_h = crtc->mode.hdisplay; | |
1700 | dst_h = radeon_crtc->native_mode.hdisplay; | |
5b1714d3 AD |
1701 | |
1702 | /* fix up for overscan on hdmi */ | |
1703 | if (ASIC_IS_AVIVO(rdev) && | |
e6db0da0 | 1704 | (!(mode->flags & DRM_MODE_FLAG_INTERLACE)) && |
5b1714d3 AD |
1705 | ((radeon_encoder->underscan_type == UNDERSCAN_ON) || |
1706 | ((radeon_encoder->underscan_type == UNDERSCAN_AUTO) && | |
039ed2d9 AD |
1707 | drm_detect_hdmi_monitor(radeon_connector->edid) && |
1708 | is_hdtv_mode(mode)))) { | |
5bccf5e3 MG |
1709 | if (radeon_encoder->underscan_hborder != 0) |
1710 | radeon_crtc->h_border = radeon_encoder->underscan_hborder; | |
1711 | else | |
1712 | radeon_crtc->h_border = (mode->hdisplay >> 5) + 16; | |
1713 | if (radeon_encoder->underscan_vborder != 0) | |
1714 | radeon_crtc->v_border = radeon_encoder->underscan_vborder; | |
1715 | else | |
1716 | radeon_crtc->v_border = (mode->vdisplay >> 5) + 16; | |
5b1714d3 AD |
1717 | radeon_crtc->rmx_type = RMX_FULL; |
1718 | src_v = crtc->mode.vdisplay; | |
1719 | dst_v = crtc->mode.vdisplay - (radeon_crtc->v_border * 2); | |
1720 | src_h = crtc->mode.hdisplay; | |
1721 | dst_h = crtc->mode.hdisplay - (radeon_crtc->h_border * 2); | |
1722 | } | |
c93bb85b JG |
1723 | first = false; |
1724 | } else { | |
1725 | if (radeon_crtc->rmx_type != radeon_encoder->rmx_type) { | |
1726 | /* WARNING: Right now this can't happen but | |
1727 | * in the future we need to check that scaling | |
d65d65b1 | 1728 | * are consistent across different encoder |
c93bb85b JG |
1729 | * (ie all encoder can work with the same |
1730 | * scaling). | |
1731 | */ | |
d65d65b1 | 1732 | DRM_ERROR("Scaling not consistent across encoder.\n"); |
c93bb85b JG |
1733 | return false; |
1734 | } | |
771fe6b9 JG |
1735 | } |
1736 | } | |
c93bb85b JG |
1737 | if (radeon_crtc->rmx_type != RMX_OFF) { |
1738 | fixed20_12 a, b; | |
d65d65b1 AD |
1739 | a.full = dfixed_const(src_v); |
1740 | b.full = dfixed_const(dst_v); | |
68adac5e | 1741 | radeon_crtc->vsc.full = dfixed_div(a, b); |
d65d65b1 AD |
1742 | a.full = dfixed_const(src_h); |
1743 | b.full = dfixed_const(dst_h); | |
68adac5e | 1744 | radeon_crtc->hsc.full = dfixed_div(a, b); |
771fe6b9 | 1745 | } else { |
68adac5e BS |
1746 | radeon_crtc->vsc.full = dfixed_const(1); |
1747 | radeon_crtc->hsc.full = dfixed_const(1); | |
771fe6b9 | 1748 | } |
c93bb85b | 1749 | return true; |
771fe6b9 | 1750 | } |
6383cf7d MK |
1751 | |
1752 | /* | |
d47abc58 MK |
1753 | * Retrieve current video scanout position of crtc on a given gpu, and |
1754 | * an optional accurate timestamp of when query happened. | |
6383cf7d | 1755 | * |
f5a80209 | 1756 | * \param dev Device to query. |
6383cf7d | 1757 | * \param crtc Crtc to query. |
abca9e45 | 1758 | * \param flags Flags from caller (DRM_CALLED_FROM_VBLIRQ or 0). |
6383cf7d MK |
1759 | * \param *vpos Location where vertical scanout position should be stored. |
1760 | * \param *hpos Location where horizontal scanout position should go. | |
d47abc58 MK |
1761 | * \param *stime Target location for timestamp taken immediately before |
1762 | * scanout position query. Can be NULL to skip timestamp. | |
1763 | * \param *etime Target location for timestamp taken immediately after | |
1764 | * scanout position query. Can be NULL to skip timestamp. | |
6383cf7d MK |
1765 | * |
1766 | * Returns vpos as a positive number while in active scanout area. | |
1767 | * Returns vpos as a negative number inside vblank, counting the number | |
1768 | * of scanlines to go until end of vblank, e.g., -1 means "one scanline | |
1769 | * until start of active scanout / end of vblank." | |
1770 | * | |
1771 | * \return Flags, or'ed together as follows: | |
1772 | * | |
25985edc | 1773 | * DRM_SCANOUTPOS_VALID = Query successful. |
f5a80209 MK |
1774 | * DRM_SCANOUTPOS_INVBL = Inside vblank. |
1775 | * DRM_SCANOUTPOS_ACCURATE = Returned position is accurate. A lack of | |
6383cf7d MK |
1776 | * this flag means that returned position may be offset by a constant but |
1777 | * unknown small number of scanlines wrt. real scanout position. | |
1778 | * | |
1779 | */ | |
abca9e45 VS |
1780 | int radeon_get_crtc_scanoutpos(struct drm_device *dev, int crtc, unsigned int flags, |
1781 | int *vpos, int *hpos, ktime_t *stime, ktime_t *etime) | |
6383cf7d MK |
1782 | { |
1783 | u32 stat_crtc = 0, vbl = 0, position = 0; | |
1784 | int vbl_start, vbl_end, vtotal, ret = 0; | |
1785 | bool in_vbl = true; | |
1786 | ||
f5a80209 MK |
1787 | struct radeon_device *rdev = dev->dev_private; |
1788 | ||
d47abc58 MK |
1789 | /* preempt_disable_rt() should go right here in PREEMPT_RT patchset. */ |
1790 | ||
1791 | /* Get optional system timestamp before query. */ | |
1792 | if (stime) | |
1793 | *stime = ktime_get(); | |
1794 | ||
6383cf7d MK |
1795 | if (ASIC_IS_DCE4(rdev)) { |
1796 | if (crtc == 0) { | |
1797 | vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END + | |
1798 | EVERGREEN_CRTC0_REGISTER_OFFSET); | |
1799 | position = RREG32(EVERGREEN_CRTC_STATUS_POSITION + | |
1800 | EVERGREEN_CRTC0_REGISTER_OFFSET); | |
f5a80209 | 1801 | ret |= DRM_SCANOUTPOS_VALID; |
6383cf7d MK |
1802 | } |
1803 | if (crtc == 1) { | |
1804 | vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END + | |
1805 | EVERGREEN_CRTC1_REGISTER_OFFSET); | |
1806 | position = RREG32(EVERGREEN_CRTC_STATUS_POSITION + | |
1807 | EVERGREEN_CRTC1_REGISTER_OFFSET); | |
f5a80209 | 1808 | ret |= DRM_SCANOUTPOS_VALID; |
6383cf7d MK |
1809 | } |
1810 | if (crtc == 2) { | |
1811 | vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END + | |
1812 | EVERGREEN_CRTC2_REGISTER_OFFSET); | |
1813 | position = RREG32(EVERGREEN_CRTC_STATUS_POSITION + | |
1814 | EVERGREEN_CRTC2_REGISTER_OFFSET); | |
f5a80209 | 1815 | ret |= DRM_SCANOUTPOS_VALID; |
6383cf7d MK |
1816 | } |
1817 | if (crtc == 3) { | |
1818 | vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END + | |
1819 | EVERGREEN_CRTC3_REGISTER_OFFSET); | |
1820 | position = RREG32(EVERGREEN_CRTC_STATUS_POSITION + | |
1821 | EVERGREEN_CRTC3_REGISTER_OFFSET); | |
f5a80209 | 1822 | ret |= DRM_SCANOUTPOS_VALID; |
6383cf7d MK |
1823 | } |
1824 | if (crtc == 4) { | |
1825 | vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END + | |
1826 | EVERGREEN_CRTC4_REGISTER_OFFSET); | |
1827 | position = RREG32(EVERGREEN_CRTC_STATUS_POSITION + | |
1828 | EVERGREEN_CRTC4_REGISTER_OFFSET); | |
f5a80209 | 1829 | ret |= DRM_SCANOUTPOS_VALID; |
6383cf7d MK |
1830 | } |
1831 | if (crtc == 5) { | |
1832 | vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END + | |
1833 | EVERGREEN_CRTC5_REGISTER_OFFSET); | |
1834 | position = RREG32(EVERGREEN_CRTC_STATUS_POSITION + | |
1835 | EVERGREEN_CRTC5_REGISTER_OFFSET); | |
f5a80209 | 1836 | ret |= DRM_SCANOUTPOS_VALID; |
6383cf7d MK |
1837 | } |
1838 | } else if (ASIC_IS_AVIVO(rdev)) { | |
1839 | if (crtc == 0) { | |
1840 | vbl = RREG32(AVIVO_D1CRTC_V_BLANK_START_END); | |
1841 | position = RREG32(AVIVO_D1CRTC_STATUS_POSITION); | |
f5a80209 | 1842 | ret |= DRM_SCANOUTPOS_VALID; |
6383cf7d MK |
1843 | } |
1844 | if (crtc == 1) { | |
1845 | vbl = RREG32(AVIVO_D2CRTC_V_BLANK_START_END); | |
1846 | position = RREG32(AVIVO_D2CRTC_STATUS_POSITION); | |
f5a80209 | 1847 | ret |= DRM_SCANOUTPOS_VALID; |
6383cf7d MK |
1848 | } |
1849 | } else { | |
1850 | /* Pre-AVIVO: Different encoding of scanout pos and vblank interval. */ | |
1851 | if (crtc == 0) { | |
1852 | /* Assume vbl_end == 0, get vbl_start from | |
1853 | * upper 16 bits. | |
1854 | */ | |
1855 | vbl = (RREG32(RADEON_CRTC_V_TOTAL_DISP) & | |
1856 | RADEON_CRTC_V_DISP) >> RADEON_CRTC_V_DISP_SHIFT; | |
1857 | /* Only retrieve vpos from upper 16 bits, set hpos == 0. */ | |
1858 | position = (RREG32(RADEON_CRTC_VLINE_CRNT_VLINE) >> 16) & RADEON_CRTC_V_TOTAL; | |
1859 | stat_crtc = RREG32(RADEON_CRTC_STATUS); | |
1860 | if (!(stat_crtc & 1)) | |
1861 | in_vbl = false; | |
1862 | ||
f5a80209 | 1863 | ret |= DRM_SCANOUTPOS_VALID; |
6383cf7d MK |
1864 | } |
1865 | if (crtc == 1) { | |
1866 | vbl = (RREG32(RADEON_CRTC2_V_TOTAL_DISP) & | |
1867 | RADEON_CRTC_V_DISP) >> RADEON_CRTC_V_DISP_SHIFT; | |
1868 | position = (RREG32(RADEON_CRTC2_VLINE_CRNT_VLINE) >> 16) & RADEON_CRTC_V_TOTAL; | |
1869 | stat_crtc = RREG32(RADEON_CRTC2_STATUS); | |
1870 | if (!(stat_crtc & 1)) | |
1871 | in_vbl = false; | |
1872 | ||
f5a80209 | 1873 | ret |= DRM_SCANOUTPOS_VALID; |
6383cf7d MK |
1874 | } |
1875 | } | |
1876 | ||
d47abc58 MK |
1877 | /* Get optional system timestamp after query. */ |
1878 | if (etime) | |
1879 | *etime = ktime_get(); | |
1880 | ||
1881 | /* preempt_enable_rt() should go right here in PREEMPT_RT patchset. */ | |
1882 | ||
6383cf7d MK |
1883 | /* Decode into vertical and horizontal scanout position. */ |
1884 | *vpos = position & 0x1fff; | |
1885 | *hpos = (position >> 16) & 0x1fff; | |
1886 | ||
1887 | /* Valid vblank area boundaries from gpu retrieved? */ | |
1888 | if (vbl > 0) { | |
1889 | /* Yes: Decode. */ | |
f5a80209 | 1890 | ret |= DRM_SCANOUTPOS_ACCURATE; |
6383cf7d MK |
1891 | vbl_start = vbl & 0x1fff; |
1892 | vbl_end = (vbl >> 16) & 0x1fff; | |
1893 | } | |
1894 | else { | |
1895 | /* No: Fake something reasonable which gives at least ok results. */ | |
f5a80209 | 1896 | vbl_start = rdev->mode_info.crtcs[crtc]->base.hwmode.crtc_vdisplay; |
6383cf7d MK |
1897 | vbl_end = 0; |
1898 | } | |
1899 | ||
1900 | /* Test scanout position against vblank region. */ | |
1901 | if ((*vpos < vbl_start) && (*vpos >= vbl_end)) | |
1902 | in_vbl = false; | |
1903 | ||
1904 | /* Check if inside vblank area and apply corrective offsets: | |
1905 | * vpos will then be >=0 in video scanout area, but negative | |
1906 | * within vblank area, counting down the number of lines until | |
1907 | * start of scanout. | |
1908 | */ | |
1909 | ||
1910 | /* Inside "upper part" of vblank area? Apply corrective offset if so: */ | |
1911 | if (in_vbl && (*vpos >= vbl_start)) { | |
f5a80209 | 1912 | vtotal = rdev->mode_info.crtcs[crtc]->base.hwmode.crtc_vtotal; |
6383cf7d MK |
1913 | *vpos = *vpos - vtotal; |
1914 | } | |
1915 | ||
1916 | /* Correct for shifted end of vbl at vbl_end. */ | |
1917 | *vpos = *vpos - vbl_end; | |
1918 | ||
1919 | /* In vblank? */ | |
1920 | if (in_vbl) | |
f5a80209 | 1921 | ret |= DRM_SCANOUTPOS_INVBL; |
6383cf7d | 1922 | |
8072bfa6 VS |
1923 | /* Is vpos outside nominal vblank area, but less than |
1924 | * 1/100 of a frame height away from start of vblank? | |
1925 | * If so, assume this isn't a massively delayed vblank | |
1926 | * interrupt, but a vblank interrupt that fired a few | |
1927 | * microseconds before true start of vblank. Compensate | |
1928 | * by adding a full frame duration to the final timestamp. | |
1929 | * Happens, e.g., on ATI R500, R600. | |
1930 | * | |
1931 | * We only do this if DRM_CALLED_FROM_VBLIRQ. | |
1932 | */ | |
1933 | if ((flags & DRM_CALLED_FROM_VBLIRQ) && !in_vbl) { | |
1934 | vbl_start = rdev->mode_info.crtcs[crtc]->base.hwmode.crtc_vdisplay; | |
1935 | vtotal = rdev->mode_info.crtcs[crtc]->base.hwmode.crtc_vtotal; | |
1936 | ||
1937 | if (vbl_start - *vpos < vtotal / 100) { | |
1938 | *vpos -= vtotal; | |
1939 | ||
1940 | /* Signal this correction as "applied". */ | |
1941 | ret |= 0x8; | |
1942 | } | |
1943 | } | |
1944 | ||
6383cf7d MK |
1945 | return ret; |
1946 | } |