[mirror_ubuntu-focal-kernel.git] / drivers / gpu / drm / radeon / radeon_fb.c

/*
 * Copyright © 2007 David Airlie
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice (including the next
 * paragraph) shall be included in all copies or substantial portions of the
 * Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
 * DEALINGS IN THE SOFTWARE.
 *
 * Authors:
 *     David Airlie
 */
    /*
     *  Modularization
     */

#include <linux/module.h>
#include <linux/slab.h>
#include <linux/fb.h>

#include "drmP.h"
#include "drm.h"
#include "drm_crtc.h"
#include "drm_crtc_helper.h"
#include "radeon_drm.h"
#include "radeon.h"

#include "drm_fb_helper.h"

#include <linux/vga_switcheroo.h>

struct radeon_fb_device {
	struct drm_fb_helper helper;
	struct radeon_framebuffer	*rfb;
	struct radeon_device		*rdev;
};

static struct fb_ops radeonfb_ops = {
	.owner = THIS_MODULE,
	.fb_check_var = drm_fb_helper_check_var,
	.fb_set_par = drm_fb_helper_set_par,
	.fb_setcolreg = drm_fb_helper_setcolreg,
	.fb_fillrect = cfb_fillrect,
	.fb_copyarea = cfb_copyarea,
	.fb_imageblit = cfb_imageblit,
	.fb_pan_display = drm_fb_helper_pan_display,
	.fb_blank = drm_fb_helper_blank,
	.fb_setcmap = drm_fb_helper_setcmap,
};

/**
 * Currently it is assumed that the old framebuffer is reused.
 *
 * LOCKING
 * caller should hold the mode config lock.
 *
 */
int radeonfb_resize(struct drm_device *dev, struct drm_crtc *crtc)
{
	struct fb_info *info;
	struct drm_framebuffer *fb;
	struct drm_display_mode *mode = crtc->desired_mode;

	fb = crtc->fb;
	if (fb == NULL) {
		return 1;
	}
	info = fb->fbdev;
	if (info == NULL) {
		return 1;
	}
	if (mode == NULL) {
		return 1;
	}
	info->var.xres = mode->hdisplay;
	info->var.right_margin = mode->hsync_start - mode->hdisplay;
	info->var.hsync_len = mode->hsync_end - mode->hsync_start;
	info->var.left_margin = mode->htotal - mode->hsync_end;
	info->var.yres = mode->vdisplay;
	info->var.lower_margin = mode->vsync_start - mode->vdisplay;
	info->var.vsync_len = mode->vsync_end - mode->vsync_start;
	info->var.upper_margin = mode->vtotal - mode->vsync_end;
	info->var.pixclock = 10000000 / mode->htotal * 1000 / mode->vtotal * 100;
	/* avoid overflow */
	info->var.pixclock = info->var.pixclock * 1000 / mode->vrefresh;

	return 0;
}
EXPORT_SYMBOL(radeonfb_resize);

static int radeon_align_pitch(struct radeon_device *rdev, int width, int bpp, bool tiled)
{
	int aligned = width;
	int align_large = (ASIC_IS_AVIVO(rdev)) || tiled;
	int pitch_mask = 0;

	switch (bpp / 8) {
	case 1:
		pitch_mask = align_large ? 255 : 127;
		break;
	case 2:
		pitch_mask = align_large ? 127 : 31;
		break;
	case 3:
	case 4:
		pitch_mask = align_large ? 63 : 15;
		break;
	}

	aligned += pitch_mask;
	aligned &= ~pitch_mask;
	return aligned;
}

static struct drm_fb_helper_funcs radeon_fb_helper_funcs = {
	.gamma_set = radeon_crtc_fb_gamma_set,
	.gamma_get = radeon_crtc_fb_gamma_get,
};

int radeonfb_create(struct drm_device *dev,
		    uint32_t fb_width, uint32_t fb_height,
		    uint32_t surface_width, uint32_t surface_height,
		    uint32_t surface_depth, uint32_t surface_bpp,
		    struct drm_framebuffer **fb_p)
{
	struct radeon_device *rdev = dev->dev_private;
	struct fb_info *info;
	struct radeon_fb_device *rfbdev;
	struct drm_framebuffer *fb = NULL;
	struct radeon_framebuffer *rfb;
	struct drm_mode_fb_cmd mode_cmd;
	struct drm_gem_object *gobj = NULL;
	struct radeon_bo *rbo = NULL;
	struct device *device = &rdev->pdev->dev;
	int size, aligned_size, ret;
	u64 fb_gpuaddr;
	void *fbptr = NULL;
	unsigned long tmp;
	bool fb_tiled = false; /* useful for testing */
	u32 tiling_flags = 0;

	mode_cmd.width = surface_width;
	mode_cmd.height = surface_height;

	/* avivo can't scanout real 24bpp */
	if ((surface_bpp == 24) && ASIC_IS_AVIVO(rdev))
		surface_bpp = 32;

	mode_cmd.bpp = surface_bpp;
	/* need to align pitch with crtc limits */
	mode_cmd.pitch = radeon_align_pitch(rdev, mode_cmd.width, mode_cmd.bpp, fb_tiled) * ((mode_cmd.bpp + 1) / 8);
	mode_cmd.depth = surface_depth;

	size = mode_cmd.pitch * mode_cmd.height;
	aligned_size = ALIGN(size, PAGE_SIZE);

	ret = radeon_gem_object_create(rdev, aligned_size, 0,
			RADEON_GEM_DOMAIN_VRAM,
			false, ttm_bo_type_kernel,
			&gobj);
	if (ret) {
		printk(KERN_ERR "failed to allocate framebuffer (%d %d)\n",
		       surface_width, surface_height);
		ret = -ENOMEM;
		goto out;
	}
	rbo = gobj->driver_private;

	if (fb_tiled)
		tiling_flags = RADEON_TILING_MACRO;

#ifdef __BIG_ENDIAN
	switch (mode_cmd.bpp) {
	case 32:
		tiling_flags |= RADEON_TILING_SWAP_32BIT;
		break;
	case 16:
		tiling_flags |= RADEON_TILING_SWAP_16BIT;
	default:
		break;
	}
#endif

	if (tiling_flags) {
		ret = radeon_bo_set_tiling_flags(rbo,
					tiling_flags | RADEON_TILING_SURFACE,
					mode_cmd.pitch);
		if (ret)
			dev_err(rdev->dev, "FB failed to set tiling flags\n");
	}
	mutex_lock(&rdev->ddev->struct_mutex);
	fb = radeon_framebuffer_create(rdev->ddev, &mode_cmd, gobj);
	if (fb == NULL) {
		DRM_ERROR("failed to allocate fb.\n");
		ret = -ENOMEM;
		goto out_unref;
	}
	ret = radeon_bo_reserve(rbo, false);
	if (unlikely(ret != 0))
		goto out_unref;
	ret = radeon_bo_pin(rbo, RADEON_GEM_DOMAIN_VRAM, &fb_gpuaddr);
	if (ret) {
		radeon_bo_unreserve(rbo);
		goto out_unref;
	}
	if (fb_tiled)
		radeon_bo_check_tiling(rbo, 0, 0);
	ret = radeon_bo_kmap(rbo, &fbptr);
	radeon_bo_unreserve(rbo);
	if (ret) {
		goto out_unref;
	}

	list_add(&fb->filp_head, &rdev->ddev->mode_config.fb_kernel_list);

	*fb_p = fb;
	rfb = to_radeon_framebuffer(fb);
	rdev->fbdev_rfb = rfb;
	rdev->fbdev_rbo = rbo;

	info = framebuffer_alloc(sizeof(struct radeon_fb_device), device);
	if (info == NULL) {
		ret = -ENOMEM;
		goto out_unref;
	}

	rdev->fbdev_info = info;
	rfbdev = info->par;
	rfbdev->helper.funcs = &radeon_fb_helper_funcs;
	rfbdev->helper.dev = dev;
	ret = drm_fb_helper_init_crtc_count(&rfbdev->helper, rdev->num_crtc,
					    RADEONFB_CONN_LIMIT);
	if (ret)
		goto out_unref;

	memset_io(fbptr, 0x0, aligned_size);

	strcpy(info->fix.id, "radeondrmfb");

	drm_fb_helper_fill_fix(info, fb->pitch, fb->depth);

	info->flags = FBINFO_DEFAULT;
	info->fbops = &radeonfb_ops;

	tmp = fb_gpuaddr - rdev->mc.vram_start;
	info->fix.smem_start = rdev->mc.aper_base + tmp;
	info->fix.smem_len = size;
	info->screen_base = fbptr;
	info->screen_size = size;

	drm_fb_helper_fill_var(info, fb, fb_width, fb_height);

	/* setup aperture base/size for vesafb takeover */
	info->aperture_base = rdev->ddev->mode_config.fb_base;
	info->aperture_size = rdev->mc.real_vram_size;

	info->fix.mmio_start = 0;
	info->fix.mmio_len = 0;
	info->pixmap.size = 64*1024;
	info->pixmap.buf_align = 8;
	info->pixmap.access_align = 32;
	info->pixmap.flags = FB_PIXMAP_SYSTEM;
	info->pixmap.scan_align = 1;
	if (info->screen_base == NULL) {
		ret = -ENOSPC;
		goto out_unref;
	}
	DRM_INFO("fb mappable at 0x%lX\n",  info->fix.smem_start);
	DRM_INFO("vram apper at 0x%lX\n",  (unsigned long)rdev->mc.aper_base);
	DRM_INFO("size %lu\n", (unsigned long)size);
	DRM_INFO("fb depth is %d\n", fb->depth);
	DRM_INFO("   pitch is %d\n", fb->pitch);

	fb->fbdev = info;
	rfbdev->rfb = rfb;
	rfbdev->rdev = rdev;

	mutex_unlock(&rdev->ddev->struct_mutex);
	vga_switcheroo_client_fb_set(rdev->ddev->pdev, info);
	return 0;

out_unref:
	if (rbo) {
		ret = radeon_bo_reserve(rbo, false);
		if (likely(ret == 0)) {
			radeon_bo_kunmap(rbo);
			radeon_bo_unreserve(rbo);
		}
	}
	if (fb && ret) {
		list_del(&fb->filp_head);
		drm_gem_object_unreference(gobj);
		drm_framebuffer_cleanup(fb);
		kfree(fb);
	}
	drm_gem_object_unreference(gobj);
	mutex_unlock(&rdev->ddev->struct_mutex);
out:
	return ret;
}

static char *mode_option;
int radeon_parse_options(char *options)
{
	char *this_opt;

	if (!options || !*options)
		return 0;

	while ((this_opt = strsep(&options, ",")) != NULL) {
		if (!*this_opt)
			continue;
		mode_option = this_opt;
	}
	return 0;
}

int radeonfb_probe(struct drm_device *dev)
{
	struct radeon_device *rdev = dev->dev_private;
	int bpp_sel = 32;

	/* select 8 bpp console on RN50 or 16MB cards */
	if (ASIC_IS_RN50(rdev) || rdev->mc.real_vram_size <= (32*1024*1024))
		bpp_sel = 8;

	return drm_fb_helper_single_fb_probe(dev, bpp_sel, &radeonfb_create);
}

int radeonfb_remove(struct drm_device *dev, struct drm_framebuffer *fb)
{
	struct fb_info *info;
	struct radeon_framebuffer *rfb = to_radeon_framebuffer(fb);
	struct radeon_bo *rbo;
	int r;

	if (!fb) {
		return -EINVAL;
	}
	info = fb->fbdev;
	if (info) {
		struct radeon_fb_device *rfbdev = info->par;
		rbo = rfb->obj->driver_private;
		unregister_framebuffer(info);
		r = radeon_bo_reserve(rbo, false);
		if (likely(r == 0)) {
			radeon_bo_kunmap(rbo);
			radeon_bo_unpin(rbo);
			radeon_bo_unreserve(rbo);
		}
		drm_fb_helper_free(&rfbdev->helper);
		framebuffer_release(info);
	}

	printk(KERN_INFO "unregistered panic notifier\n");

	return 0;
}
EXPORT_SYMBOL(radeonfb_remove);
MODULE_LICENSE("GPL");
Commit	Line	Data
771fe6b9 JG	1	/*
	2	* Copyright © 2007 David Airlie
	3	*
	4	* Permission is hereby granted, free of charge, to any person obtaining a
	5	* copy of this software and associated documentation files (the "Software"),
	6	* to deal in the Software without restriction, including without limitation
	7	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
	8	* and/or sell copies of the Software, and to permit persons to whom the
	9	* Software is furnished to do so, subject to the following conditions:
	10	*
	11	* The above copyright notice and this permission notice (including the next
	12	* paragraph) shall be included in all copies or substantial portions of the
	13	* Software.
	14	*
	15	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	16	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	17	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	18	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
	19	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
	20	* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
	21	* DEALINGS IN THE SOFTWARE.
	22	*
	23	* Authors:
	24	* David Airlie
	25	*/
	26	/*
	27	* Modularization
	28	*/
	29
	30	#include <linux/module.h>
5a0e3ad6	31	#include <linux/slab.h>
771fe6b9	32	#include <linux/fb.h>
771fe6b9 JG	33
	34	#include "drmP.h"
	35	#include "drm.h"
	36	#include "drm_crtc.h"
	37	#include "drm_crtc_helper.h"
	38	#include "radeon_drm.h"
	39	#include "radeon.h"
	40
785b93ef DA	41	#include "drm_fb_helper.h"
785b93ef DA	42
6a9ee8af DA	43	#include <linux/vga_switcheroo.h>
6a9ee8af DA	44
771fe6b9	45	struct radeon_fb_device {
785b93ef	46	struct drm_fb_helper helper;
771fe6b9	47	struct radeon_framebuffer *rfb;
785b93ef	48	struct radeon_device *rdev;
771fe6b9 JG	49	};
771fe6b9 JG	50
771fe6b9 JG	51	static struct fb_ops radeonfb_ops = {
771fe6b9 JG	52	.owner = THIS_MODULE,
c88f9f0c	53	.fb_check_var = drm_fb_helper_check_var,
785b93ef DA	54	.fb_set_par = drm_fb_helper_set_par,
785b93ef DA	55	.fb_setcolreg = drm_fb_helper_setcolreg,
771fe6b9 JG	56	.fb_fillrect = cfb_fillrect,
	57	.fb_copyarea = cfb_copyarea,
	58	.fb_imageblit = cfb_imageblit,
785b93ef DA	59	.fb_pan_display = drm_fb_helper_pan_display,
785b93ef DA	60	.fb_blank = drm_fb_helper_blank,
068143d3	61	.fb_setcmap = drm_fb_helper_setcmap,
771fe6b9 JG	62	};
	63
	64	/**
af901ca1	65	* Currently it is assumed that the old framebuffer is reused.
771fe6b9 JG	66	*
	67	* LOCKING
	68	* caller should hold the mode config lock.
	69	*
	70	*/
	71	int radeonfb_resize(struct drm_device dev, struct drm_crtc crtc)
	72	{
	73	struct fb_info *info;
	74	struct drm_framebuffer *fb;
	75	struct drm_display_mode *mode = crtc->desired_mode;
	76
	77	fb = crtc->fb;
	78	if (fb == NULL) {
	79	return 1;
	80	}
	81	info = fb->fbdev;
	82	if (info == NULL) {
	83	return 1;
	84	}
	85	if (mode == NULL) {
	86	return 1;
	87	}
	88	info->var.xres = mode->hdisplay;
	89	info->var.right_margin = mode->hsync_start - mode->hdisplay;
	90	info->var.hsync_len = mode->hsync_end - mode->hsync_start;
	91	info->var.left_margin = mode->htotal - mode->hsync_end;
	92	info->var.yres = mode->vdisplay;
	93	info->var.lower_margin = mode->vsync_start - mode->vdisplay;
	94	info->var.vsync_len = mode->vsync_end - mode->vsync_start;
	95	info->var.upper_margin = mode->vtotal - mode->vsync_end;
	96	info->var.pixclock = 10000000 / mode->htotal * 1000 / mode->vtotal * 100;
	97	/* avoid overflow */
	98	info->var.pixclock = info->var.pixclock * 1000 / mode->vrefresh;
	99
	100	return 0;
	101	}
	102	EXPORT_SYMBOL(radeonfb_resize);
	103
e024e110	104	static int radeon_align_pitch(struct radeon_device *rdev, int width, int bpp, bool tiled)
771fe6b9 JG	105	{
771fe6b9 JG	106	int aligned = width;
e024e110	107	int align_large = (ASIC_IS_AVIVO(rdev)) \|\| tiled;
771fe6b9 JG	108	int pitch_mask = 0;
	109
	110	switch (bpp / 8) {
	111	case 1:
	112	pitch_mask = align_large ? 255 : 127;
	113	break;
	114	case 2:
	115	pitch_mask = align_large ? 127 : 31;
	116	break;
	117	case 3:
	118	case 4:
	119	pitch_mask = align_large ? 63 : 15;
	120	break;
	121	}
	122
	123	aligned += pitch_mask;
	124	aligned &= ~pitch_mask;
	125	return aligned;
	126	}
	127
785b93ef DA	128	static struct drm_fb_helper_funcs radeon_fb_helper_funcs = {
785b93ef DA	129	.gamma_set = radeon_crtc_fb_gamma_set,
b8c00ac5	130	.gamma_get = radeon_crtc_fb_gamma_get,
785b93ef DA	131	};
	132
	133	int radeonfb_create(struct drm_device *dev,
771fe6b9 JG	134	uint32_t fb_width, uint32_t fb_height,
771fe6b9 JG	135	uint32_t surface_width, uint32_t surface_height,
d50ba256	136	uint32_t surface_depth, uint32_t surface_bpp,
785b93ef	137	struct drm_framebuffer **fb_p)
771fe6b9	138	{
785b93ef	139	struct radeon_device *rdev = dev->dev_private;
771fe6b9 JG	140	struct fb_info *info;
771fe6b9 JG	141	struct radeon_fb_device *rfbdev;
f92e93eb	142	struct drm_framebuffer *fb = NULL;
771fe6b9 JG	143	struct radeon_framebuffer *rfb;
	144	struct drm_mode_fb_cmd mode_cmd;
	145	struct drm_gem_object *gobj = NULL;
4c788679	146	struct radeon_bo *rbo = NULL;
771fe6b9 JG	147	struct device *device = &rdev->pdev->dev;
771fe6b9 JG	148	int size, aligned_size, ret;
f92e93eb	149	u64 fb_gpuaddr;
771fe6b9	150	void *fbptr = NULL;
f92e93eb	151	unsigned long tmp;
e024e110	152	bool fb_tiled = false; /* useful for testing */
c88f9f0c	153	u32 tiling_flags = 0;
771fe6b9 JG	154
	155	mode_cmd.width = surface_width;
	156	mode_cmd.height = surface_height;
b8c00ac5 DA	157
	158	/* avivo can't scanout real 24bpp */
	159	if ((surface_bpp == 24) && ASIC_IS_AVIVO(rdev))
	160	surface_bpp = 32;
	161
d50ba256	162	mode_cmd.bpp = surface_bpp;
771fe6b9	163	/* need to align pitch with crtc limits */
e024e110	164	mode_cmd.pitch = radeon_align_pitch(rdev, mode_cmd.width, mode_cmd.bpp, fb_tiled) * ((mode_cmd.bpp + 1) / 8);
d50ba256	165	mode_cmd.depth = surface_depth;
771fe6b9 JG	166
	167	size = mode_cmd.pitch * mode_cmd.height;
	168	aligned_size = ALIGN(size, PAGE_SIZE);
	169
	170	ret = radeon_gem_object_create(rdev, aligned_size, 0,
f92e93eb JG	171	RADEON_GEM_DOMAIN_VRAM,
f92e93eb JG	172	false, ttm_bo_type_kernel,
4c788679	173	&gobj);
771fe6b9	174	if (ret) {
f92e93eb JG	175	printk(KERN_ERR "failed to allocate framebuffer (%d %d)\n",
f92e93eb JG	176	surface_width, surface_height);
771fe6b9 JG	177	ret = -ENOMEM;
	178	goto out;
	179	}
4c788679	180	rbo = gobj->driver_private;
771fe6b9	181
e024e110	182	if (fb_tiled)
c88f9f0c MD	183	tiling_flags = RADEON_TILING_MACRO;
	184
	185	#ifdef __BIG_ENDIAN
	186	switch (mode_cmd.bpp) {
	187	case 32:
	188	tiling_flags \|= RADEON_TILING_SWAP_32BIT;
	189	break;
	190	case 16:
	191	tiling_flags \|= RADEON_TILING_SWAP_16BIT;
	192	default:
	193	break;
	194	}
	195	#endif
	196
4c788679 JG	197	if (tiling_flags) {
	198	ret = radeon_bo_set_tiling_flags(rbo,
	199	tiling_flags \| RADEON_TILING_SURFACE,
	200	mode_cmd.pitch);
	201	if (ret)
	202	dev_err(rdev->dev, "FB failed to set tiling flags\n");
	203	}
771fe6b9 JG	204	mutex_lock(&rdev->ddev->struct_mutex);
	205	fb = radeon_framebuffer_create(rdev->ddev, &mode_cmd, gobj);
	206	if (fb == NULL) {
	207	DRM_ERROR("failed to allocate fb.\n");
	208	ret = -ENOMEM;
	209	goto out_unref;
	210	}
4c788679 JG	211	ret = radeon_bo_reserve(rbo, false);
	212	if (unlikely(ret != 0))
	213	goto out_unref;
	214	ret = radeon_bo_pin(rbo, RADEON_GEM_DOMAIN_VRAM, &fb_gpuaddr);
	215	if (ret) {
	216	radeon_bo_unreserve(rbo);
	217	goto out_unref;
	218	}
	219	if (fb_tiled)
	220	radeon_bo_check_tiling(rbo, 0, 0);
	221	ret = radeon_bo_kmap(rbo, &fbptr);
	222	radeon_bo_unreserve(rbo);
f92e93eb	223	if (ret) {
f92e93eb JG	224	goto out_unref;
f92e93eb JG	225	}
771fe6b9 JG	226
	227	list_add(&fb->filp_head, &rdev->ddev->mode_config.fb_kernel_list);
	228
785b93ef	229	*fb_p = fb;
771fe6b9	230	rfb = to_radeon_framebuffer(fb);
771fe6b9	231	rdev->fbdev_rfb = rfb;
4c788679	232	rdev->fbdev_rbo = rbo;
771fe6b9 JG	233
	234	info = framebuffer_alloc(sizeof(struct radeon_fb_device), device);
	235	if (info == NULL) {
	236	ret = -ENOMEM;
	237	goto out_unref;
	238	}
785b93ef	239
2f9a60d7	240	rdev->fbdev_info = info;
771fe6b9	241	rfbdev = info->par;
785b93ef DA	242	rfbdev->helper.funcs = &radeon_fb_helper_funcs;
785b93ef DA	243	rfbdev->helper.dev = dev;
18917b60	244	ret = drm_fb_helper_init_crtc_count(&rfbdev->helper, rdev->num_crtc,
785b93ef DA	245	RADEONFB_CONN_LIMIT);
	246	if (ret)
	247	goto out_unref;
771fe6b9	248
6719fc66	249	memset_io(fbptr, 0x0, aligned_size);
bf8e828b	250
771fe6b9	251	strcpy(info->fix.id, "radeondrmfb");
785b93ef	252
068143d3	253	drm_fb_helper_fill_fix(info, fb->pitch, fb->depth);
785b93ef	254
771fe6b9 JG	255	info->flags = FBINFO_DEFAULT;
771fe6b9 JG	256	info->fbops = &radeonfb_ops;
785b93ef	257
d594e46a	258	tmp = fb_gpuaddr - rdev->mc.vram_start;
f92e93eb	259	info->fix.smem_start = rdev->mc.aper_base + tmp;
771fe6b9 JG	260	info->fix.smem_len = size;
	261	info->screen_base = fbptr;
	262	info->screen_size = size;
785b93ef DA	263
785b93ef DA	264	drm_fb_helper_fill_var(info, fb, fb_width, fb_height);
ed8f0d9e DA	265
	266	/* setup aperture base/size for vesafb takeover */
	267	info->aperture_base = rdev->ddev->mode_config.fb_base;
	268	info->aperture_size = rdev->mc.real_vram_size;
	269
696d4df1 MD	270	info->fix.mmio_start = 0;
696d4df1 MD	271	info->fix.mmio_len = 0;
771fe6b9 JG	272	info->pixmap.size = 64*1024;
	273	info->pixmap.buf_align = 8;
	274	info->pixmap.access_align = 32;
	275	info->pixmap.flags = FB_PIXMAP_SYSTEM;
	276	info->pixmap.scan_align = 1;
	277	if (info->screen_base == NULL) {
	278	ret = -ENOSPC;
	279	goto out_unref;
	280	}
	281	DRM_INFO("fb mappable at 0x%lX\n", info->fix.smem_start);
	282	DRM_INFO("vram apper at 0x%lX\n", (unsigned long)rdev->mc.aper_base);
	283	DRM_INFO("size %lu\n", (unsigned long)size);
	284	DRM_INFO("fb depth is %d\n", fb->depth);
	285	DRM_INFO(" pitch is %d\n", fb->pitch);
	286
771fe6b9 JG	287	fb->fbdev = info;
	288	rfbdev->rfb = rfb;
	289	rfbdev->rdev = rdev;
	290
	291	mutex_unlock(&rdev->ddev->struct_mutex);
6a9ee8af	292	vga_switcheroo_client_fb_set(rdev->ddev->pdev, info);
771fe6b9 JG	293	return 0;
	294
	295	out_unref:
4c788679 JG	296	if (rbo) {
	297	ret = radeon_bo_reserve(rbo, false);
	298	if (likely(ret == 0)) {
	299	radeon_bo_kunmap(rbo);
	300	radeon_bo_unreserve(rbo);
	301	}
771fe6b9	302	}
f92e93eb	303	if (fb && ret) {
771fe6b9 JG	304	list_del(&fb->filp_head);
	305	drm_gem_object_unreference(gobj);
	306	drm_framebuffer_cleanup(fb);
	307	kfree(fb);
	308	}
	309	drm_gem_object_unreference(gobj);
	310	mutex_unlock(&rdev->ddev->struct_mutex);
	311	out:
	312	return ret;
	313	}
	314
d50ba256 DA	315	static char *mode_option;
	316	int radeon_parse_options(char *options)
	317	{
	318	char *this_opt;
	319
	320	if (!options \|\| !*options)
	321	return 0;
	322
	323	while ((this_opt = strsep(&options, ",")) != NULL) {
	324	if (!*this_opt)
	325	continue;
	326	mode_option = this_opt;
	327	}
	328	return 0;
	329	}
	330
771fe6b9 JG	331	int radeonfb_probe(struct drm_device *dev)
771fe6b9 JG	332	{
47381156 DA	333	struct radeon_device *rdev = dev->dev_private;
	334	int bpp_sel = 32;
	335
	336	/* select 8 bpp console on RN50 or 16MB cards */
	337	if (ASIC_IS_RN50(rdev) \|\| rdev->mc.real_vram_size <= (3210241024))
	338	bpp_sel = 8;
	339
	340	return drm_fb_helper_single_fb_probe(dev, bpp_sel, &radeonfb_create);
771fe6b9	341	}
771fe6b9 JG	342
	343	int radeonfb_remove(struct drm_device dev, struct drm_framebuffer fb)
	344	{
	345	struct fb_info *info;
	346	struct radeon_framebuffer *rfb = to_radeon_framebuffer(fb);
4c788679 JG	347	struct radeon_bo *rbo;
4c788679 JG	348	int r;
771fe6b9 JG	349
	350	if (!fb) {
	351	return -EINVAL;
	352	}
	353	info = fb->fbdev;
	354	if (info) {
785b93ef	355	struct radeon_fb_device *rfbdev = info->par;
4c788679	356	rbo = rfb->obj->driver_private;
771fe6b9	357	unregister_framebuffer(info);
4c788679 JG	358	r = radeon_bo_reserve(rbo, false);
	359	if (likely(r == 0)) {
	360	radeon_bo_kunmap(rbo);
	361	radeon_bo_unpin(rbo);
	362	radeon_bo_unreserve(rbo);
	363	}
785b93ef	364	drm_fb_helper_free(&rfbdev->helper);
771fe6b9 JG	365	framebuffer_release(info);
	366	}
	367
	368	printk(KERN_INFO "unregistered panic notifier\n");
785b93ef	369
771fe6b9 JG	370	return 0;
	371	}
	372	EXPORT_SYMBOL(radeonfb_remove);
	373	MODULE_LICENSE("GPL");