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Commit | Line | Data |
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2048e328 MY |
1 | /* |
2 | * Copyright (C) Fuzhou Rockchip Electronics Co.Ltd | |
3 | * Author:Mark Yao <mark.yao@rock-chips.com> | |
4 | * | |
5 | * This software is licensed under the terms of the GNU General Public | |
6 | * License version 2, as published by the Free Software Foundation, and | |
7 | * may be copied, distributed, and modified under those terms. | |
8 | * | |
9 | * This program is distributed in the hope that it will be useful, | |
10 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
11 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
12 | * GNU General Public License for more details. | |
13 | */ | |
14 | ||
15 | #include <drm/drm.h> | |
16 | #include <drm/drmP.h> | |
63ebb9fa | 17 | #include <drm/drm_atomic.h> |
2048e328 MY |
18 | #include <drm/drm_crtc.h> |
19 | #include <drm/drm_crtc_helper.h> | |
20 | #include <drm/drm_plane_helper.h> | |
21 | ||
22 | #include <linux/kernel.h> | |
00fe6148 | 23 | #include <linux/module.h> |
2048e328 MY |
24 | #include <linux/platform_device.h> |
25 | #include <linux/clk.h> | |
26 | #include <linux/of.h> | |
27 | #include <linux/of_device.h> | |
28 | #include <linux/pm_runtime.h> | |
29 | #include <linux/component.h> | |
30 | ||
31 | #include <linux/reset.h> | |
32 | #include <linux/delay.h> | |
33 | ||
34 | #include "rockchip_drm_drv.h" | |
35 | #include "rockchip_drm_gem.h" | |
36 | #include "rockchip_drm_fb.h" | |
37 | #include "rockchip_drm_vop.h" | |
38 | ||
2048e328 MY |
39 | #define __REG_SET_RELAXED(x, off, mask, shift, v) \ |
40 | vop_mask_write_relaxed(x, off, (mask) << shift, (v) << shift) | |
41 | #define __REG_SET_NORMAL(x, off, mask, shift, v) \ | |
42 | vop_mask_write(x, off, (mask) << shift, (v) << shift) | |
43 | ||
44 | #define REG_SET(x, base, reg, v, mode) \ | |
45 | __REG_SET_##mode(x, base + reg.offset, reg.mask, reg.shift, v) | |
c7647f86 JK |
46 | #define REG_SET_MASK(x, base, reg, mask, v, mode) \ |
47 | __REG_SET_##mode(x, base + reg.offset, mask, reg.shift, v) | |
2048e328 MY |
48 | |
49 | #define VOP_WIN_SET(x, win, name, v) \ | |
50 | REG_SET(x, win->base, win->phy->name, v, RELAXED) | |
4c156c21 MY |
51 | #define VOP_SCL_SET(x, win, name, v) \ |
52 | REG_SET(x, win->base, win->phy->scl->name, v, RELAXED) | |
1194fffb MY |
53 | #define VOP_SCL_SET_EXT(x, win, name, v) \ |
54 | REG_SET(x, win->base, win->phy->scl->ext->name, v, RELAXED) | |
2048e328 MY |
55 | #define VOP_CTRL_SET(x, name, v) \ |
56 | REG_SET(x, 0, (x)->data->ctrl->name, v, NORMAL) | |
57 | ||
dbb3d944 MY |
58 | #define VOP_INTR_GET(vop, name) \ |
59 | vop_read_reg(vop, 0, &vop->data->ctrl->name) | |
60 | ||
c7647f86 JK |
61 | #define VOP_INTR_SET(vop, name, mask, v) \ |
62 | REG_SET_MASK(vop, 0, vop->data->intr->name, mask, v, NORMAL) | |
dbb3d944 MY |
63 | #define VOP_INTR_SET_TYPE(vop, name, type, v) \ |
64 | do { \ | |
c7647f86 | 65 | int i, reg = 0, mask = 0; \ |
dbb3d944 | 66 | for (i = 0; i < vop->data->intr->nintrs; i++) { \ |
c7647f86 | 67 | if (vop->data->intr->intrs[i] & type) { \ |
dbb3d944 | 68 | reg |= (v) << i; \ |
c7647f86 JK |
69 | mask |= 1 << i; \ |
70 | } \ | |
dbb3d944 | 71 | } \ |
c7647f86 | 72 | VOP_INTR_SET(vop, name, mask, reg); \ |
dbb3d944 MY |
73 | } while (0) |
74 | #define VOP_INTR_GET_TYPE(vop, name, type) \ | |
75 | vop_get_intr_type(vop, &vop->data->intr->name, type) | |
76 | ||
2048e328 MY |
77 | #define VOP_WIN_GET(x, win, name) \ |
78 | vop_read_reg(x, win->base, &win->phy->name) | |
79 | ||
80 | #define VOP_WIN_GET_YRGBADDR(vop, win) \ | |
81 | vop_readl(vop, win->base + win->phy->yrgb_mst.offset) | |
82 | ||
83 | #define to_vop(x) container_of(x, struct vop, crtc) | |
84 | #define to_vop_win(x) container_of(x, struct vop_win, base) | |
63ebb9fa | 85 | #define to_vop_plane_state(x) container_of(x, struct vop_plane_state, base) |
2048e328 | 86 | |
63ebb9fa MY |
87 | struct vop_plane_state { |
88 | struct drm_plane_state base; | |
89 | int format; | |
90 | struct drm_rect src; | |
91 | struct drm_rect dest; | |
2048e328 | 92 | dma_addr_t yrgb_mst; |
63ebb9fa | 93 | bool enable; |
2048e328 MY |
94 | }; |
95 | ||
96 | struct vop_win { | |
97 | struct drm_plane base; | |
98 | const struct vop_win_data *data; | |
99 | struct vop *vop; | |
100 | ||
63ebb9fa | 101 | struct vop_plane_state state; |
2048e328 MY |
102 | }; |
103 | ||
104 | struct vop { | |
105 | struct drm_crtc crtc; | |
106 | struct device *dev; | |
107 | struct drm_device *drm_dev; | |
31e980c5 | 108 | bool is_enabled; |
2048e328 | 109 | |
2048e328 MY |
110 | /* mutex vsync_ work */ |
111 | struct mutex vsync_mutex; | |
112 | bool vsync_work_pending; | |
1067219b | 113 | struct completion dsp_hold_completion; |
63ebb9fa MY |
114 | struct completion wait_update_complete; |
115 | struct drm_pending_vblank_event *event; | |
2048e328 MY |
116 | |
117 | const struct vop_data *data; | |
118 | ||
119 | uint32_t *regsbak; | |
120 | void __iomem *regs; | |
121 | ||
122 | /* physical map length of vop register */ | |
123 | uint32_t len; | |
124 | ||
125 | /* one time only one process allowed to config the register */ | |
126 | spinlock_t reg_lock; | |
127 | /* lock vop irq reg */ | |
128 | spinlock_t irq_lock; | |
129 | ||
130 | unsigned int irq; | |
131 | ||
132 | /* vop AHP clk */ | |
133 | struct clk *hclk; | |
134 | /* vop dclk */ | |
135 | struct clk *dclk; | |
136 | /* vop share memory frequency */ | |
137 | struct clk *aclk; | |
138 | ||
139 | /* vop dclk reset */ | |
140 | struct reset_control *dclk_rst; | |
141 | ||
2048e328 MY |
142 | struct vop_win win[]; |
143 | }; | |
144 | ||
2048e328 MY |
145 | static inline void vop_writel(struct vop *vop, uint32_t offset, uint32_t v) |
146 | { | |
147 | writel(v, vop->regs + offset); | |
148 | vop->regsbak[offset >> 2] = v; | |
149 | } | |
150 | ||
151 | static inline uint32_t vop_readl(struct vop *vop, uint32_t offset) | |
152 | { | |
153 | return readl(vop->regs + offset); | |
154 | } | |
155 | ||
156 | static inline uint32_t vop_read_reg(struct vop *vop, uint32_t base, | |
157 | const struct vop_reg *reg) | |
158 | { | |
159 | return (vop_readl(vop, base + reg->offset) >> reg->shift) & reg->mask; | |
160 | } | |
161 | ||
2048e328 MY |
162 | static inline void vop_mask_write(struct vop *vop, uint32_t offset, |
163 | uint32_t mask, uint32_t v) | |
164 | { | |
165 | if (mask) { | |
166 | uint32_t cached_val = vop->regsbak[offset >> 2]; | |
167 | ||
168 | cached_val = (cached_val & ~mask) | v; | |
169 | writel(cached_val, vop->regs + offset); | |
170 | vop->regsbak[offset >> 2] = cached_val; | |
171 | } | |
172 | } | |
173 | ||
174 | static inline void vop_mask_write_relaxed(struct vop *vop, uint32_t offset, | |
175 | uint32_t mask, uint32_t v) | |
176 | { | |
177 | if (mask) { | |
178 | uint32_t cached_val = vop->regsbak[offset >> 2]; | |
179 | ||
180 | cached_val = (cached_val & ~mask) | v; | |
181 | writel_relaxed(cached_val, vop->regs + offset); | |
182 | vop->regsbak[offset >> 2] = cached_val; | |
183 | } | |
184 | } | |
185 | ||
dbb3d944 MY |
186 | static inline uint32_t vop_get_intr_type(struct vop *vop, |
187 | const struct vop_reg *reg, int type) | |
188 | { | |
189 | uint32_t i, ret = 0; | |
190 | uint32_t regs = vop_read_reg(vop, 0, reg); | |
191 | ||
192 | for (i = 0; i < vop->data->intr->nintrs; i++) { | |
193 | if ((type & vop->data->intr->intrs[i]) && (regs & 1 << i)) | |
194 | ret |= vop->data->intr->intrs[i]; | |
195 | } | |
196 | ||
197 | return ret; | |
198 | } | |
199 | ||
0cf33fe3 MY |
200 | static inline void vop_cfg_done(struct vop *vop) |
201 | { | |
202 | VOP_CTRL_SET(vop, cfg_done, 1); | |
203 | } | |
204 | ||
85a359f2 TF |
205 | static bool has_rb_swapped(uint32_t format) |
206 | { | |
207 | switch (format) { | |
208 | case DRM_FORMAT_XBGR8888: | |
209 | case DRM_FORMAT_ABGR8888: | |
210 | case DRM_FORMAT_BGR888: | |
211 | case DRM_FORMAT_BGR565: | |
212 | return true; | |
213 | default: | |
214 | return false; | |
215 | } | |
216 | } | |
217 | ||
2048e328 MY |
218 | static enum vop_data_format vop_convert_format(uint32_t format) |
219 | { | |
220 | switch (format) { | |
221 | case DRM_FORMAT_XRGB8888: | |
222 | case DRM_FORMAT_ARGB8888: | |
85a359f2 TF |
223 | case DRM_FORMAT_XBGR8888: |
224 | case DRM_FORMAT_ABGR8888: | |
2048e328 MY |
225 | return VOP_FMT_ARGB8888; |
226 | case DRM_FORMAT_RGB888: | |
85a359f2 | 227 | case DRM_FORMAT_BGR888: |
2048e328 MY |
228 | return VOP_FMT_RGB888; |
229 | case DRM_FORMAT_RGB565: | |
85a359f2 | 230 | case DRM_FORMAT_BGR565: |
2048e328 MY |
231 | return VOP_FMT_RGB565; |
232 | case DRM_FORMAT_NV12: | |
233 | return VOP_FMT_YUV420SP; | |
234 | case DRM_FORMAT_NV16: | |
235 | return VOP_FMT_YUV422SP; | |
236 | case DRM_FORMAT_NV24: | |
237 | return VOP_FMT_YUV444SP; | |
238 | default: | |
239 | DRM_ERROR("unsupport format[%08x]\n", format); | |
240 | return -EINVAL; | |
241 | } | |
242 | } | |
243 | ||
84c7f8ca MY |
244 | static bool is_yuv_support(uint32_t format) |
245 | { | |
246 | switch (format) { | |
247 | case DRM_FORMAT_NV12: | |
248 | case DRM_FORMAT_NV16: | |
249 | case DRM_FORMAT_NV24: | |
250 | return true; | |
251 | default: | |
252 | return false; | |
253 | } | |
254 | } | |
255 | ||
2048e328 MY |
256 | static bool is_alpha_support(uint32_t format) |
257 | { | |
258 | switch (format) { | |
259 | case DRM_FORMAT_ARGB8888: | |
85a359f2 | 260 | case DRM_FORMAT_ABGR8888: |
2048e328 MY |
261 | return true; |
262 | default: | |
263 | return false; | |
264 | } | |
265 | } | |
266 | ||
4c156c21 MY |
267 | static uint16_t scl_vop_cal_scale(enum scale_mode mode, uint32_t src, |
268 | uint32_t dst, bool is_horizontal, | |
269 | int vsu_mode, int *vskiplines) | |
270 | { | |
271 | uint16_t val = 1 << SCL_FT_DEFAULT_FIXPOINT_SHIFT; | |
272 | ||
273 | if (is_horizontal) { | |
274 | if (mode == SCALE_UP) | |
275 | val = GET_SCL_FT_BIC(src, dst); | |
276 | else if (mode == SCALE_DOWN) | |
277 | val = GET_SCL_FT_BILI_DN(src, dst); | |
278 | } else { | |
279 | if (mode == SCALE_UP) { | |
280 | if (vsu_mode == SCALE_UP_BIL) | |
281 | val = GET_SCL_FT_BILI_UP(src, dst); | |
282 | else | |
283 | val = GET_SCL_FT_BIC(src, dst); | |
284 | } else if (mode == SCALE_DOWN) { | |
285 | if (vskiplines) { | |
286 | *vskiplines = scl_get_vskiplines(src, dst); | |
287 | val = scl_get_bili_dn_vskip(src, dst, | |
288 | *vskiplines); | |
289 | } else { | |
290 | val = GET_SCL_FT_BILI_DN(src, dst); | |
291 | } | |
292 | } | |
293 | } | |
294 | ||
295 | return val; | |
296 | } | |
297 | ||
298 | static void scl_vop_cal_scl_fac(struct vop *vop, const struct vop_win_data *win, | |
299 | uint32_t src_w, uint32_t src_h, uint32_t dst_w, | |
300 | uint32_t dst_h, uint32_t pixel_format) | |
301 | { | |
302 | uint16_t yrgb_hor_scl_mode, yrgb_ver_scl_mode; | |
303 | uint16_t cbcr_hor_scl_mode = SCALE_NONE; | |
304 | uint16_t cbcr_ver_scl_mode = SCALE_NONE; | |
305 | int hsub = drm_format_horz_chroma_subsampling(pixel_format); | |
306 | int vsub = drm_format_vert_chroma_subsampling(pixel_format); | |
307 | bool is_yuv = is_yuv_support(pixel_format); | |
308 | uint16_t cbcr_src_w = src_w / hsub; | |
309 | uint16_t cbcr_src_h = src_h / vsub; | |
310 | uint16_t vsu_mode; | |
311 | uint16_t lb_mode; | |
312 | uint32_t val; | |
313 | int vskiplines; | |
314 | ||
315 | if (dst_w > 3840) { | |
316 | DRM_ERROR("Maximum destination width (3840) exceeded\n"); | |
317 | return; | |
318 | } | |
319 | ||
1194fffb MY |
320 | if (!win->phy->scl->ext) { |
321 | VOP_SCL_SET(vop, win, scale_yrgb_x, | |
322 | scl_cal_scale2(src_w, dst_w)); | |
323 | VOP_SCL_SET(vop, win, scale_yrgb_y, | |
324 | scl_cal_scale2(src_h, dst_h)); | |
325 | if (is_yuv) { | |
326 | VOP_SCL_SET(vop, win, scale_cbcr_x, | |
327 | scl_cal_scale2(src_w, dst_w)); | |
328 | VOP_SCL_SET(vop, win, scale_cbcr_y, | |
329 | scl_cal_scale2(src_h, dst_h)); | |
330 | } | |
331 | return; | |
332 | } | |
333 | ||
4c156c21 MY |
334 | yrgb_hor_scl_mode = scl_get_scl_mode(src_w, dst_w); |
335 | yrgb_ver_scl_mode = scl_get_scl_mode(src_h, dst_h); | |
336 | ||
337 | if (is_yuv) { | |
338 | cbcr_hor_scl_mode = scl_get_scl_mode(cbcr_src_w, dst_w); | |
339 | cbcr_ver_scl_mode = scl_get_scl_mode(cbcr_src_h, dst_h); | |
340 | if (cbcr_hor_scl_mode == SCALE_DOWN) | |
341 | lb_mode = scl_vop_cal_lb_mode(dst_w, true); | |
342 | else | |
343 | lb_mode = scl_vop_cal_lb_mode(cbcr_src_w, true); | |
344 | } else { | |
345 | if (yrgb_hor_scl_mode == SCALE_DOWN) | |
346 | lb_mode = scl_vop_cal_lb_mode(dst_w, false); | |
347 | else | |
348 | lb_mode = scl_vop_cal_lb_mode(src_w, false); | |
349 | } | |
350 | ||
1194fffb | 351 | VOP_SCL_SET_EXT(vop, win, lb_mode, lb_mode); |
4c156c21 MY |
352 | if (lb_mode == LB_RGB_3840X2) { |
353 | if (yrgb_ver_scl_mode != SCALE_NONE) { | |
354 | DRM_ERROR("ERROR : not allow yrgb ver scale\n"); | |
355 | return; | |
356 | } | |
357 | if (cbcr_ver_scl_mode != SCALE_NONE) { | |
358 | DRM_ERROR("ERROR : not allow cbcr ver scale\n"); | |
359 | return; | |
360 | } | |
361 | vsu_mode = SCALE_UP_BIL; | |
362 | } else if (lb_mode == LB_RGB_2560X4) { | |
363 | vsu_mode = SCALE_UP_BIL; | |
364 | } else { | |
365 | vsu_mode = SCALE_UP_BIC; | |
366 | } | |
367 | ||
368 | val = scl_vop_cal_scale(yrgb_hor_scl_mode, src_w, dst_w, | |
369 | true, 0, NULL); | |
370 | VOP_SCL_SET(vop, win, scale_yrgb_x, val); | |
371 | val = scl_vop_cal_scale(yrgb_ver_scl_mode, src_h, dst_h, | |
372 | false, vsu_mode, &vskiplines); | |
373 | VOP_SCL_SET(vop, win, scale_yrgb_y, val); | |
374 | ||
1194fffb MY |
375 | VOP_SCL_SET_EXT(vop, win, vsd_yrgb_gt4, vskiplines == 4); |
376 | VOP_SCL_SET_EXT(vop, win, vsd_yrgb_gt2, vskiplines == 2); | |
4c156c21 | 377 | |
1194fffb MY |
378 | VOP_SCL_SET_EXT(vop, win, yrgb_hor_scl_mode, yrgb_hor_scl_mode); |
379 | VOP_SCL_SET_EXT(vop, win, yrgb_ver_scl_mode, yrgb_ver_scl_mode); | |
380 | VOP_SCL_SET_EXT(vop, win, yrgb_hsd_mode, SCALE_DOWN_BIL); | |
381 | VOP_SCL_SET_EXT(vop, win, yrgb_vsd_mode, SCALE_DOWN_BIL); | |
382 | VOP_SCL_SET_EXT(vop, win, yrgb_vsu_mode, vsu_mode); | |
4c156c21 MY |
383 | if (is_yuv) { |
384 | val = scl_vop_cal_scale(cbcr_hor_scl_mode, cbcr_src_w, | |
385 | dst_w, true, 0, NULL); | |
386 | VOP_SCL_SET(vop, win, scale_cbcr_x, val); | |
387 | val = scl_vop_cal_scale(cbcr_ver_scl_mode, cbcr_src_h, | |
388 | dst_h, false, vsu_mode, &vskiplines); | |
389 | VOP_SCL_SET(vop, win, scale_cbcr_y, val); | |
390 | ||
1194fffb MY |
391 | VOP_SCL_SET_EXT(vop, win, vsd_cbcr_gt4, vskiplines == 4); |
392 | VOP_SCL_SET_EXT(vop, win, vsd_cbcr_gt2, vskiplines == 2); | |
393 | VOP_SCL_SET_EXT(vop, win, cbcr_hor_scl_mode, cbcr_hor_scl_mode); | |
394 | VOP_SCL_SET_EXT(vop, win, cbcr_ver_scl_mode, cbcr_ver_scl_mode); | |
395 | VOP_SCL_SET_EXT(vop, win, cbcr_hsd_mode, SCALE_DOWN_BIL); | |
396 | VOP_SCL_SET_EXT(vop, win, cbcr_vsd_mode, SCALE_DOWN_BIL); | |
397 | VOP_SCL_SET_EXT(vop, win, cbcr_vsu_mode, vsu_mode); | |
4c156c21 MY |
398 | } |
399 | } | |
400 | ||
1067219b MY |
401 | static void vop_dsp_hold_valid_irq_enable(struct vop *vop) |
402 | { | |
403 | unsigned long flags; | |
404 | ||
405 | if (WARN_ON(!vop->is_enabled)) | |
406 | return; | |
407 | ||
408 | spin_lock_irqsave(&vop->irq_lock, flags); | |
409 | ||
dbb3d944 | 410 | VOP_INTR_SET_TYPE(vop, enable, DSP_HOLD_VALID_INTR, 1); |
1067219b MY |
411 | |
412 | spin_unlock_irqrestore(&vop->irq_lock, flags); | |
413 | } | |
414 | ||
415 | static void vop_dsp_hold_valid_irq_disable(struct vop *vop) | |
416 | { | |
417 | unsigned long flags; | |
418 | ||
419 | if (WARN_ON(!vop->is_enabled)) | |
420 | return; | |
421 | ||
422 | spin_lock_irqsave(&vop->irq_lock, flags); | |
423 | ||
dbb3d944 | 424 | VOP_INTR_SET_TYPE(vop, enable, DSP_HOLD_VALID_INTR, 0); |
1067219b MY |
425 | |
426 | spin_unlock_irqrestore(&vop->irq_lock, flags); | |
427 | } | |
428 | ||
63ebb9fa | 429 | static void vop_enable(struct drm_crtc *crtc) |
2048e328 MY |
430 | { |
431 | struct vop *vop = to_vop(crtc); | |
432 | int ret; | |
433 | ||
31e980c5 MY |
434 | if (vop->is_enabled) |
435 | return; | |
436 | ||
5d82d1a7 MY |
437 | ret = pm_runtime_get_sync(vop->dev); |
438 | if (ret < 0) { | |
439 | dev_err(vop->dev, "failed to get pm runtime: %d\n", ret); | |
440 | return; | |
441 | } | |
442 | ||
2048e328 MY |
443 | ret = clk_enable(vop->hclk); |
444 | if (ret < 0) { | |
445 | dev_err(vop->dev, "failed to enable hclk - %d\n", ret); | |
446 | return; | |
447 | } | |
448 | ||
449 | ret = clk_enable(vop->dclk); | |
450 | if (ret < 0) { | |
451 | dev_err(vop->dev, "failed to enable dclk - %d\n", ret); | |
452 | goto err_disable_hclk; | |
453 | } | |
454 | ||
455 | ret = clk_enable(vop->aclk); | |
456 | if (ret < 0) { | |
457 | dev_err(vop->dev, "failed to enable aclk - %d\n", ret); | |
458 | goto err_disable_dclk; | |
459 | } | |
460 | ||
461 | /* | |
462 | * Slave iommu shares power, irq and clock with vop. It was associated | |
463 | * automatically with this master device via common driver code. | |
464 | * Now that we have enabled the clock we attach it to the shared drm | |
465 | * mapping. | |
466 | */ | |
467 | ret = rockchip_drm_dma_attach_device(vop->drm_dev, vop->dev); | |
468 | if (ret) { | |
469 | dev_err(vop->dev, "failed to attach dma mapping, %d\n", ret); | |
470 | goto err_disable_aclk; | |
471 | } | |
472 | ||
77faa161 | 473 | memcpy(vop->regs, vop->regsbak, vop->len); |
52ab7891 MY |
474 | /* |
475 | * At here, vop clock & iommu is enable, R/W vop regs would be safe. | |
476 | */ | |
477 | vop->is_enabled = true; | |
478 | ||
2048e328 MY |
479 | spin_lock(&vop->reg_lock); |
480 | ||
481 | VOP_CTRL_SET(vop, standby, 0); | |
482 | ||
483 | spin_unlock(&vop->reg_lock); | |
484 | ||
485 | enable_irq(vop->irq); | |
486 | ||
b5f7b755 | 487 | drm_crtc_vblank_on(crtc); |
2048e328 MY |
488 | |
489 | return; | |
490 | ||
491 | err_disable_aclk: | |
492 | clk_disable(vop->aclk); | |
493 | err_disable_dclk: | |
494 | clk_disable(vop->dclk); | |
495 | err_disable_hclk: | |
496 | clk_disable(vop->hclk); | |
497 | } | |
498 | ||
0ad3675d | 499 | static void vop_crtc_disable(struct drm_crtc *crtc) |
2048e328 MY |
500 | { |
501 | struct vop *vop = to_vop(crtc); | |
502 | ||
31e980c5 MY |
503 | if (!vop->is_enabled) |
504 | return; | |
505 | ||
b5f7b755 | 506 | drm_crtc_vblank_off(crtc); |
2048e328 | 507 | |
2048e328 | 508 | /* |
1067219b MY |
509 | * Vop standby will take effect at end of current frame, |
510 | * if dsp hold valid irq happen, it means standby complete. | |
511 | * | |
512 | * we must wait standby complete when we want to disable aclk, | |
513 | * if not, memory bus maybe dead. | |
2048e328 | 514 | */ |
1067219b MY |
515 | reinit_completion(&vop->dsp_hold_completion); |
516 | vop_dsp_hold_valid_irq_enable(vop); | |
517 | ||
2048e328 MY |
518 | spin_lock(&vop->reg_lock); |
519 | ||
520 | VOP_CTRL_SET(vop, standby, 1); | |
521 | ||
522 | spin_unlock(&vop->reg_lock); | |
52ab7891 | 523 | |
1067219b MY |
524 | wait_for_completion(&vop->dsp_hold_completion); |
525 | ||
526 | vop_dsp_hold_valid_irq_disable(vop); | |
527 | ||
528 | disable_irq(vop->irq); | |
529 | ||
52ab7891 | 530 | vop->is_enabled = false; |
1067219b | 531 | |
2048e328 | 532 | /* |
1067219b | 533 | * vop standby complete, so iommu detach is safe. |
2048e328 | 534 | */ |
2048e328 MY |
535 | rockchip_drm_dma_detach_device(vop->drm_dev, vop->dev); |
536 | ||
1067219b | 537 | clk_disable(vop->dclk); |
2048e328 MY |
538 | clk_disable(vop->aclk); |
539 | clk_disable(vop->hclk); | |
5d82d1a7 | 540 | pm_runtime_put(vop->dev); |
2048e328 MY |
541 | } |
542 | ||
63ebb9fa | 543 | static void vop_plane_destroy(struct drm_plane *plane) |
2048e328 | 544 | { |
63ebb9fa | 545 | drm_plane_cleanup(plane); |
2048e328 MY |
546 | } |
547 | ||
63ebb9fa MY |
548 | static int vop_plane_atomic_check(struct drm_plane *plane, |
549 | struct drm_plane_state *state) | |
2048e328 | 550 | { |
63ebb9fa MY |
551 | struct drm_crtc *crtc = state->crtc; |
552 | struct drm_framebuffer *fb = state->fb; | |
2048e328 | 553 | struct vop_win *vop_win = to_vop_win(plane); |
63ebb9fa | 554 | struct vop_plane_state *vop_plane_state = to_vop_plane_state(state); |
2048e328 | 555 | const struct vop_win_data *win = vop_win->data; |
2048e328 MY |
556 | bool visible; |
557 | int ret; | |
63ebb9fa MY |
558 | struct drm_rect *dest = &vop_plane_state->dest; |
559 | struct drm_rect *src = &vop_plane_state->src; | |
560 | struct drm_rect clip; | |
4c156c21 MY |
561 | int min_scale = win->phy->scl ? FRAC_16_16(1, 8) : |
562 | DRM_PLANE_HELPER_NO_SCALING; | |
563 | int max_scale = win->phy->scl ? FRAC_16_16(8, 1) : | |
564 | DRM_PLANE_HELPER_NO_SCALING; | |
2048e328 | 565 | |
63ebb9fa MY |
566 | crtc = crtc ? crtc : plane->state->crtc; |
567 | /* | |
568 | * Both crtc or plane->state->crtc can be null. | |
569 | */ | |
570 | if (!crtc || !fb) | |
571 | goto out_disable; | |
572 | src->x1 = state->src_x; | |
573 | src->y1 = state->src_y; | |
574 | src->x2 = state->src_x + state->src_w; | |
575 | src->y2 = state->src_y + state->src_h; | |
576 | dest->x1 = state->crtc_x; | |
577 | dest->y1 = state->crtc_y; | |
578 | dest->x2 = state->crtc_x + state->crtc_w; | |
579 | dest->y2 = state->crtc_y + state->crtc_h; | |
580 | ||
581 | clip.x1 = 0; | |
582 | clip.y1 = 0; | |
583 | clip.x2 = crtc->mode.hdisplay; | |
584 | clip.y2 = crtc->mode.vdisplay; | |
585 | ||
586 | ret = drm_plane_helper_check_update(plane, crtc, state->fb, | |
587 | src, dest, &clip, | |
4c156c21 MY |
588 | min_scale, |
589 | max_scale, | |
63ebb9fa | 590 | true, true, &visible); |
2048e328 MY |
591 | if (ret) |
592 | return ret; | |
593 | ||
594 | if (!visible) | |
63ebb9fa | 595 | goto out_disable; |
2048e328 | 596 | |
63ebb9fa MY |
597 | vop_plane_state->format = vop_convert_format(fb->pixel_format); |
598 | if (vop_plane_state->format < 0) | |
599 | return vop_plane_state->format; | |
84c7f8ca | 600 | |
63ebb9fa MY |
601 | /* |
602 | * Src.x1 can be odd when do clip, but yuv plane start point | |
603 | * need align with 2 pixel. | |
604 | */ | |
605 | if (is_yuv_support(fb->pixel_format) && ((src->x1 >> 16) % 2)) | |
2048e328 | 606 | return -EINVAL; |
2048e328 | 607 | |
63ebb9fa | 608 | vop_plane_state->enable = true; |
2048e328 | 609 | |
63ebb9fa | 610 | return 0; |
84c7f8ca | 611 | |
63ebb9fa MY |
612 | out_disable: |
613 | vop_plane_state->enable = false; | |
614 | return 0; | |
615 | } | |
2048e328 | 616 | |
63ebb9fa MY |
617 | static void vop_plane_atomic_disable(struct drm_plane *plane, |
618 | struct drm_plane_state *old_state) | |
619 | { | |
620 | struct vop_plane_state *vop_plane_state = to_vop_plane_state(old_state); | |
621 | struct vop_win *vop_win = to_vop_win(plane); | |
622 | const struct vop_win_data *win = vop_win->data; | |
623 | struct vop *vop = to_vop(old_state->crtc); | |
2048e328 | 624 | |
63ebb9fa MY |
625 | if (!old_state->crtc) |
626 | return; | |
2048e328 | 627 | |
63ebb9fa | 628 | spin_lock(&vop->reg_lock); |
2048e328 | 629 | |
63ebb9fa | 630 | VOP_WIN_SET(vop, win, enable, 0); |
84c7f8ca | 631 | |
63ebb9fa | 632 | spin_unlock(&vop->reg_lock); |
84c7f8ca | 633 | |
63ebb9fa MY |
634 | vop_plane_state->enable = false; |
635 | } | |
84c7f8ca | 636 | |
63ebb9fa MY |
637 | static void vop_plane_atomic_update(struct drm_plane *plane, |
638 | struct drm_plane_state *old_state) | |
639 | { | |
640 | struct drm_plane_state *state = plane->state; | |
641 | struct drm_crtc *crtc = state->crtc; | |
642 | struct vop_win *vop_win = to_vop_win(plane); | |
643 | struct vop_plane_state *vop_plane_state = to_vop_plane_state(state); | |
644 | const struct vop_win_data *win = vop_win->data; | |
645 | struct vop *vop = to_vop(state->crtc); | |
646 | struct drm_framebuffer *fb = state->fb; | |
647 | unsigned int actual_w, actual_h; | |
648 | unsigned int dsp_stx, dsp_sty; | |
649 | uint32_t act_info, dsp_info, dsp_st; | |
650 | struct drm_rect *src = &vop_plane_state->src; | |
651 | struct drm_rect *dest = &vop_plane_state->dest; | |
652 | struct drm_gem_object *obj, *uv_obj; | |
653 | struct rockchip_gem_object *rk_obj, *rk_uv_obj; | |
654 | unsigned long offset; | |
655 | dma_addr_t dma_addr; | |
656 | uint32_t val; | |
657 | bool rb_swap; | |
84c7f8ca | 658 | |
2048e328 | 659 | /* |
63ebb9fa | 660 | * can't update plane when vop is disabled. |
2048e328 | 661 | */ |
63ebb9fa MY |
662 | if (!crtc) |
663 | return; | |
2048e328 | 664 | |
63ebb9fa MY |
665 | if (WARN_ON(!vop->is_enabled)) |
666 | return; | |
2048e328 | 667 | |
63ebb9fa MY |
668 | if (!vop_plane_state->enable) { |
669 | vop_plane_atomic_disable(plane, old_state); | |
670 | return; | |
2048e328 | 671 | } |
63ebb9fa MY |
672 | |
673 | obj = rockchip_fb_get_gem_obj(fb, 0); | |
674 | rk_obj = to_rockchip_obj(obj); | |
675 | ||
676 | actual_w = drm_rect_width(src) >> 16; | |
677 | actual_h = drm_rect_height(src) >> 16; | |
678 | act_info = (actual_h - 1) << 16 | ((actual_w - 1) & 0xffff); | |
679 | ||
680 | dsp_info = (drm_rect_height(dest) - 1) << 16; | |
681 | dsp_info |= (drm_rect_width(dest) - 1) & 0xffff; | |
682 | ||
683 | dsp_stx = dest->x1 + crtc->mode.htotal - crtc->mode.hsync_start; | |
684 | dsp_sty = dest->y1 + crtc->mode.vtotal - crtc->mode.vsync_start; | |
685 | dsp_st = dsp_sty << 16 | (dsp_stx & 0xffff); | |
686 | ||
687 | offset = (src->x1 >> 16) * drm_format_plane_cpp(fb->pixel_format, 0); | |
688 | offset += (src->y1 >> 16) * fb->pitches[0]; | |
689 | vop_plane_state->yrgb_mst = rk_obj->dma_addr + offset + fb->offsets[0]; | |
2048e328 MY |
690 | |
691 | spin_lock(&vop->reg_lock); | |
692 | ||
63ebb9fa MY |
693 | VOP_WIN_SET(vop, win, format, vop_plane_state->format); |
694 | VOP_WIN_SET(vop, win, yrgb_vir, fb->pitches[0] >> 2); | |
695 | VOP_WIN_SET(vop, win, yrgb_mst, vop_plane_state->yrgb_mst); | |
696 | if (is_yuv_support(fb->pixel_format)) { | |
697 | int hsub = drm_format_horz_chroma_subsampling(fb->pixel_format); | |
698 | int vsub = drm_format_vert_chroma_subsampling(fb->pixel_format); | |
699 | int bpp = drm_format_plane_cpp(fb->pixel_format, 1); | |
700 | ||
701 | uv_obj = rockchip_fb_get_gem_obj(fb, 1); | |
702 | rk_uv_obj = to_rockchip_obj(uv_obj); | |
703 | ||
704 | offset = (src->x1 >> 16) * bpp / hsub; | |
705 | offset += (src->y1 >> 16) * fb->pitches[1] / vsub; | |
706 | ||
707 | dma_addr = rk_uv_obj->dma_addr + offset + fb->offsets[1]; | |
708 | VOP_WIN_SET(vop, win, uv_vir, fb->pitches[1] >> 2); | |
709 | VOP_WIN_SET(vop, win, uv_mst, dma_addr); | |
84c7f8ca | 710 | } |
4c156c21 MY |
711 | |
712 | if (win->phy->scl) | |
713 | scl_vop_cal_scl_fac(vop, win, actual_w, actual_h, | |
63ebb9fa | 714 | drm_rect_width(dest), drm_rect_height(dest), |
4c156c21 MY |
715 | fb->pixel_format); |
716 | ||
63ebb9fa MY |
717 | VOP_WIN_SET(vop, win, act_info, act_info); |
718 | VOP_WIN_SET(vop, win, dsp_info, dsp_info); | |
719 | VOP_WIN_SET(vop, win, dsp_st, dsp_st); | |
4c156c21 | 720 | |
63ebb9fa | 721 | rb_swap = has_rb_swapped(fb->pixel_format); |
85a359f2 | 722 | VOP_WIN_SET(vop, win, rb_swap, rb_swap); |
2048e328 | 723 | |
63ebb9fa | 724 | if (is_alpha_support(fb->pixel_format)) { |
2048e328 MY |
725 | VOP_WIN_SET(vop, win, dst_alpha_ctl, |
726 | DST_FACTOR_M0(ALPHA_SRC_INVERSE)); | |
727 | val = SRC_ALPHA_EN(1) | SRC_COLOR_M0(ALPHA_SRC_PRE_MUL) | | |
728 | SRC_ALPHA_M0(ALPHA_STRAIGHT) | | |
729 | SRC_BLEND_M0(ALPHA_PER_PIX) | | |
730 | SRC_ALPHA_CAL_M0(ALPHA_NO_SATURATION) | | |
731 | SRC_FACTOR_M0(ALPHA_ONE); | |
732 | VOP_WIN_SET(vop, win, src_alpha_ctl, val); | |
733 | } else { | |
734 | VOP_WIN_SET(vop, win, src_alpha_ctl, SRC_ALPHA_EN(0)); | |
735 | } | |
736 | ||
737 | VOP_WIN_SET(vop, win, enable, 1); | |
2048e328 | 738 | spin_unlock(&vop->reg_lock); |
2048e328 MY |
739 | } |
740 | ||
63ebb9fa MY |
741 | static const struct drm_plane_helper_funcs plane_helper_funcs = { |
742 | .atomic_check = vop_plane_atomic_check, | |
743 | .atomic_update = vop_plane_atomic_update, | |
744 | .atomic_disable = vop_plane_atomic_disable, | |
745 | }; | |
2048e328 | 746 | |
63ebb9fa | 747 | void vop_atomic_plane_reset(struct drm_plane *plane) |
2048e328 | 748 | { |
63ebb9fa MY |
749 | struct vop_plane_state *vop_plane_state = |
750 | to_vop_plane_state(plane->state); | |
2048e328 | 751 | |
63ebb9fa MY |
752 | if (plane->state && plane->state->fb) |
753 | drm_framebuffer_unreference(plane->state->fb); | |
754 | ||
755 | kfree(vop_plane_state); | |
756 | vop_plane_state = kzalloc(sizeof(*vop_plane_state), GFP_KERNEL); | |
757 | if (!vop_plane_state) | |
758 | return; | |
2048e328 | 759 | |
63ebb9fa MY |
760 | plane->state = &vop_plane_state->base; |
761 | plane->state->plane = plane; | |
2048e328 MY |
762 | } |
763 | ||
63ebb9fa MY |
764 | struct drm_plane_state * |
765 | vop_atomic_plane_duplicate_state(struct drm_plane *plane) | |
2048e328 | 766 | { |
63ebb9fa MY |
767 | struct vop_plane_state *old_vop_plane_state; |
768 | struct vop_plane_state *vop_plane_state; | |
2048e328 | 769 | |
63ebb9fa MY |
770 | if (WARN_ON(!plane->state)) |
771 | return NULL; | |
2048e328 | 772 | |
63ebb9fa MY |
773 | old_vop_plane_state = to_vop_plane_state(plane->state); |
774 | vop_plane_state = kmemdup(old_vop_plane_state, | |
775 | sizeof(*vop_plane_state), GFP_KERNEL); | |
776 | if (!vop_plane_state) | |
777 | return NULL; | |
2048e328 | 778 | |
63ebb9fa MY |
779 | __drm_atomic_helper_plane_duplicate_state(plane, |
780 | &vop_plane_state->base); | |
2048e328 | 781 | |
63ebb9fa | 782 | return &vop_plane_state->base; |
2048e328 MY |
783 | } |
784 | ||
63ebb9fa MY |
785 | static void vop_atomic_plane_destroy_state(struct drm_plane *plane, |
786 | struct drm_plane_state *state) | |
2048e328 | 787 | { |
63ebb9fa MY |
788 | struct vop_plane_state *vop_state = to_vop_plane_state(state); |
789 | ||
790 | __drm_atomic_helper_plane_destroy_state(plane, state); | |
791 | ||
792 | kfree(vop_state); | |
2048e328 MY |
793 | } |
794 | ||
795 | static const struct drm_plane_funcs vop_plane_funcs = { | |
63ebb9fa MY |
796 | .update_plane = drm_atomic_helper_update_plane, |
797 | .disable_plane = drm_atomic_helper_disable_plane, | |
2048e328 | 798 | .destroy = vop_plane_destroy, |
63ebb9fa MY |
799 | .reset = vop_atomic_plane_reset, |
800 | .atomic_duplicate_state = vop_atomic_plane_duplicate_state, | |
801 | .atomic_destroy_state = vop_atomic_plane_destroy_state, | |
2048e328 MY |
802 | }; |
803 | ||
804 | int rockchip_drm_crtc_mode_config(struct drm_crtc *crtc, | |
805 | int connector_type, | |
806 | int out_mode) | |
807 | { | |
808 | struct vop *vop = to_vop(crtc); | |
809 | ||
d0e20d0e MY |
810 | if (WARN_ON(!vop->is_enabled)) |
811 | return -EINVAL; | |
812 | ||
813 | switch (connector_type) { | |
814 | case DRM_MODE_CONNECTOR_LVDS: | |
815 | VOP_CTRL_SET(vop, rgb_en, 1); | |
816 | break; | |
817 | case DRM_MODE_CONNECTOR_eDP: | |
818 | VOP_CTRL_SET(vop, edp_en, 1); | |
819 | break; | |
820 | case DRM_MODE_CONNECTOR_HDMIA: | |
821 | VOP_CTRL_SET(vop, hdmi_en, 1); | |
822 | break; | |
84e05408 CZ |
823 | case DRM_MODE_CONNECTOR_DSI: |
824 | VOP_CTRL_SET(vop, mipi_en, 1); | |
825 | break; | |
d0e20d0e MY |
826 | default: |
827 | DRM_ERROR("unsupport connector_type[%d]\n", connector_type); | |
828 | return -EINVAL; | |
829 | }; | |
830 | VOP_CTRL_SET(vop, out_mode, out_mode); | |
2048e328 MY |
831 | |
832 | return 0; | |
833 | } | |
f66a1627 | 834 | EXPORT_SYMBOL_GPL(rockchip_drm_crtc_mode_config); |
2048e328 MY |
835 | |
836 | static int vop_crtc_enable_vblank(struct drm_crtc *crtc) | |
837 | { | |
838 | struct vop *vop = to_vop(crtc); | |
839 | unsigned long flags; | |
840 | ||
63ebb9fa | 841 | if (WARN_ON(!vop->is_enabled)) |
2048e328 MY |
842 | return -EPERM; |
843 | ||
844 | spin_lock_irqsave(&vop->irq_lock, flags); | |
845 | ||
dbb3d944 | 846 | VOP_INTR_SET_TYPE(vop, enable, FS_INTR, 1); |
2048e328 MY |
847 | |
848 | spin_unlock_irqrestore(&vop->irq_lock, flags); | |
849 | ||
850 | return 0; | |
851 | } | |
852 | ||
853 | static void vop_crtc_disable_vblank(struct drm_crtc *crtc) | |
854 | { | |
855 | struct vop *vop = to_vop(crtc); | |
856 | unsigned long flags; | |
857 | ||
63ebb9fa | 858 | if (WARN_ON(!vop->is_enabled)) |
2048e328 | 859 | return; |
31e980c5 | 860 | |
2048e328 | 861 | spin_lock_irqsave(&vop->irq_lock, flags); |
dbb3d944 MY |
862 | |
863 | VOP_INTR_SET_TYPE(vop, enable, FS_INTR, 0); | |
864 | ||
2048e328 MY |
865 | spin_unlock_irqrestore(&vop->irq_lock, flags); |
866 | } | |
867 | ||
63ebb9fa MY |
868 | static void vop_crtc_wait_for_update(struct drm_crtc *crtc) |
869 | { | |
870 | struct vop *vop = to_vop(crtc); | |
871 | ||
872 | reinit_completion(&vop->wait_update_complete); | |
873 | WARN_ON(!wait_for_completion_timeout(&vop->wait_update_complete, 100)); | |
874 | } | |
875 | ||
2048e328 MY |
876 | static const struct rockchip_crtc_funcs private_crtc_funcs = { |
877 | .enable_vblank = vop_crtc_enable_vblank, | |
878 | .disable_vblank = vop_crtc_disable_vblank, | |
63ebb9fa | 879 | .wait_for_update = vop_crtc_wait_for_update, |
2048e328 MY |
880 | }; |
881 | ||
2048e328 MY |
882 | static bool vop_crtc_mode_fixup(struct drm_crtc *crtc, |
883 | const struct drm_display_mode *mode, | |
884 | struct drm_display_mode *adjusted_mode) | |
885 | { | |
b59b8de3 CZ |
886 | struct vop *vop = to_vop(crtc); |
887 | ||
2048e328 MY |
888 | if (adjusted_mode->htotal == 0 || adjusted_mode->vtotal == 0) |
889 | return false; | |
890 | ||
b59b8de3 CZ |
891 | adjusted_mode->clock = |
892 | clk_round_rate(vop->dclk, mode->clock * 1000) / 1000; | |
893 | ||
2048e328 MY |
894 | return true; |
895 | } | |
896 | ||
63ebb9fa | 897 | static void vop_crtc_enable(struct drm_crtc *crtc) |
2048e328 MY |
898 | { |
899 | struct vop *vop = to_vop(crtc); | |
63ebb9fa | 900 | struct drm_display_mode *adjusted_mode = &crtc->state->adjusted_mode; |
2048e328 MY |
901 | u16 hsync_len = adjusted_mode->hsync_end - adjusted_mode->hsync_start; |
902 | u16 hdisplay = adjusted_mode->hdisplay; | |
903 | u16 htotal = adjusted_mode->htotal; | |
904 | u16 hact_st = adjusted_mode->htotal - adjusted_mode->hsync_start; | |
905 | u16 hact_end = hact_st + hdisplay; | |
906 | u16 vdisplay = adjusted_mode->vdisplay; | |
907 | u16 vtotal = adjusted_mode->vtotal; | |
908 | u16 vsync_len = adjusted_mode->vsync_end - adjusted_mode->vsync_start; | |
909 | u16 vact_st = adjusted_mode->vtotal - adjusted_mode->vsync_start; | |
910 | u16 vact_end = vact_st + vdisplay; | |
2048e328 MY |
911 | uint32_t val; |
912 | ||
63ebb9fa | 913 | vop_enable(crtc); |
2048e328 | 914 | /* |
ce3887ed MY |
915 | * If dclk rate is zero, mean that scanout is stop, |
916 | * we don't need wait any more. | |
2048e328 | 917 | */ |
ce3887ed MY |
918 | if (clk_get_rate(vop->dclk)) { |
919 | /* | |
920 | * Rk3288 vop timing register is immediately, when configure | |
921 | * display timing on display time, may cause tearing. | |
922 | * | |
923 | * Vop standby will take effect at end of current frame, | |
924 | * if dsp hold valid irq happen, it means standby complete. | |
925 | * | |
926 | * mode set: | |
927 | * standby and wait complete --> |---- | |
928 | * | display time | |
929 | * |---- | |
930 | * |---> dsp hold irq | |
931 | * configure display timing --> | | |
932 | * standby exit | | |
933 | * | new frame start. | |
934 | */ | |
935 | ||
936 | reinit_completion(&vop->dsp_hold_completion); | |
937 | vop_dsp_hold_valid_irq_enable(vop); | |
938 | ||
939 | spin_lock(&vop->reg_lock); | |
940 | ||
941 | VOP_CTRL_SET(vop, standby, 1); | |
942 | ||
943 | spin_unlock(&vop->reg_lock); | |
944 | ||
945 | wait_for_completion(&vop->dsp_hold_completion); | |
946 | ||
947 | vop_dsp_hold_valid_irq_disable(vop); | |
948 | } | |
2048e328 | 949 | |
2048e328 | 950 | val = 0x8; |
44ddb7ef MY |
951 | val |= (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC) ? 0 : 1; |
952 | val |= (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC) ? 0 : (1 << 1); | |
2048e328 MY |
953 | VOP_CTRL_SET(vop, pin_pol, val); |
954 | ||
955 | VOP_CTRL_SET(vop, htotal_pw, (htotal << 16) | hsync_len); | |
956 | val = hact_st << 16; | |
957 | val |= hact_end; | |
958 | VOP_CTRL_SET(vop, hact_st_end, val); | |
959 | VOP_CTRL_SET(vop, hpost_st_end, val); | |
960 | ||
961 | VOP_CTRL_SET(vop, vtotal_pw, (vtotal << 16) | vsync_len); | |
962 | val = vact_st << 16; | |
963 | val |= vact_end; | |
964 | VOP_CTRL_SET(vop, vact_st_end, val); | |
965 | VOP_CTRL_SET(vop, vpost_st_end, val); | |
966 | ||
2048e328 | 967 | clk_set_rate(vop->dclk, adjusted_mode->clock * 1000); |
ce3887ed MY |
968 | |
969 | VOP_CTRL_SET(vop, standby, 0); | |
2048e328 MY |
970 | } |
971 | ||
63ebb9fa MY |
972 | static void vop_crtc_atomic_flush(struct drm_crtc *crtc, |
973 | struct drm_crtc_state *old_crtc_state) | |
2048e328 MY |
974 | { |
975 | struct vop *vop = to_vop(crtc); | |
2048e328 | 976 | |
63ebb9fa MY |
977 | if (WARN_ON(!vop->is_enabled)) |
978 | return; | |
2048e328 | 979 | |
63ebb9fa | 980 | spin_lock(&vop->reg_lock); |
2048e328 | 981 | |
63ebb9fa | 982 | vop_cfg_done(vop); |
2048e328 | 983 | |
63ebb9fa | 984 | spin_unlock(&vop->reg_lock); |
2048e328 MY |
985 | } |
986 | ||
63ebb9fa MY |
987 | static void vop_crtc_atomic_begin(struct drm_crtc *crtc, |
988 | struct drm_crtc_state *old_crtc_state) | |
2048e328 | 989 | { |
63ebb9fa | 990 | struct vop *vop = to_vop(crtc); |
2048e328 | 991 | |
63ebb9fa MY |
992 | if (crtc->state->event) { |
993 | WARN_ON(drm_crtc_vblank_get(crtc) != 0); | |
2048e328 | 994 | |
63ebb9fa MY |
995 | vop->event = crtc->state->event; |
996 | crtc->state->event = NULL; | |
997 | } | |
2048e328 MY |
998 | } |
999 | ||
63ebb9fa MY |
1000 | static const struct drm_crtc_helper_funcs vop_crtc_helper_funcs = { |
1001 | .enable = vop_crtc_enable, | |
1002 | .disable = vop_crtc_disable, | |
1003 | .mode_fixup = vop_crtc_mode_fixup, | |
1004 | .atomic_flush = vop_crtc_atomic_flush, | |
1005 | .atomic_begin = vop_crtc_atomic_begin, | |
1006 | }; | |
1007 | ||
2048e328 MY |
1008 | static void vop_crtc_destroy(struct drm_crtc *crtc) |
1009 | { | |
1010 | drm_crtc_cleanup(crtc); | |
1011 | } | |
1012 | ||
1013 | static const struct drm_crtc_funcs vop_crtc_funcs = { | |
63ebb9fa MY |
1014 | .set_config = drm_atomic_helper_set_config, |
1015 | .page_flip = drm_atomic_helper_page_flip, | |
2048e328 | 1016 | .destroy = vop_crtc_destroy, |
63ebb9fa MY |
1017 | .reset = drm_atomic_helper_crtc_reset, |
1018 | .atomic_duplicate_state = drm_atomic_helper_crtc_duplicate_state, | |
1019 | .atomic_destroy_state = drm_atomic_helper_crtc_destroy_state, | |
2048e328 MY |
1020 | }; |
1021 | ||
63ebb9fa | 1022 | static bool vop_win_pending_is_complete(struct vop_win *vop_win) |
2048e328 | 1023 | { |
63ebb9fa MY |
1024 | struct drm_plane *plane = &vop_win->base; |
1025 | struct vop_plane_state *state = to_vop_plane_state(plane->state); | |
1026 | dma_addr_t yrgb_mst; | |
2048e328 | 1027 | |
63ebb9fa MY |
1028 | if (!state->enable) |
1029 | return VOP_WIN_GET(vop_win->vop, vop_win->data, enable) == 0; | |
2048e328 | 1030 | |
63ebb9fa | 1031 | yrgb_mst = VOP_WIN_GET_YRGBADDR(vop_win->vop, vop_win->data); |
2048e328 | 1032 | |
63ebb9fa | 1033 | return yrgb_mst == state->yrgb_mst; |
2048e328 MY |
1034 | } |
1035 | ||
63ebb9fa | 1036 | static void vop_handle_vblank(struct vop *vop) |
2048e328 | 1037 | { |
63ebb9fa MY |
1038 | struct drm_device *drm = vop->drm_dev; |
1039 | struct drm_crtc *crtc = &vop->crtc; | |
1040 | unsigned long flags; | |
1041 | int i; | |
2048e328 | 1042 | |
63ebb9fa MY |
1043 | for (i = 0; i < vop->data->win_size; i++) { |
1044 | if (!vop_win_pending_is_complete(&vop->win[i])) | |
1045 | return; | |
2048e328 MY |
1046 | } |
1047 | ||
63ebb9fa MY |
1048 | if (vop->event) { |
1049 | spin_lock_irqsave(&drm->event_lock, flags); | |
2048e328 | 1050 | |
63ebb9fa MY |
1051 | drm_crtc_send_vblank_event(crtc, vop->event); |
1052 | drm_crtc_vblank_put(crtc); | |
1053 | vop->event = NULL; | |
2048e328 | 1054 | |
63ebb9fa | 1055 | spin_unlock_irqrestore(&drm->event_lock, flags); |
2048e328 | 1056 | } |
63ebb9fa MY |
1057 | if (!completion_done(&vop->wait_update_complete)) |
1058 | complete(&vop->wait_update_complete); | |
2048e328 MY |
1059 | } |
1060 | ||
1061 | static irqreturn_t vop_isr(int irq, void *data) | |
1062 | { | |
1063 | struct vop *vop = data; | |
b5f7b755 | 1064 | struct drm_crtc *crtc = &vop->crtc; |
dbb3d944 | 1065 | uint32_t active_irqs; |
2048e328 | 1066 | unsigned long flags; |
1067219b | 1067 | int ret = IRQ_NONE; |
2048e328 MY |
1068 | |
1069 | /* | |
dbb3d944 | 1070 | * interrupt register has interrupt status, enable and clear bits, we |
2048e328 MY |
1071 | * must hold irq_lock to avoid a race with enable/disable_vblank(). |
1072 | */ | |
1073 | spin_lock_irqsave(&vop->irq_lock, flags); | |
dbb3d944 MY |
1074 | |
1075 | active_irqs = VOP_INTR_GET_TYPE(vop, status, INTR_MASK); | |
2048e328 MY |
1076 | /* Clear all active interrupt sources */ |
1077 | if (active_irqs) | |
dbb3d944 MY |
1078 | VOP_INTR_SET_TYPE(vop, clear, active_irqs, 1); |
1079 | ||
2048e328 MY |
1080 | spin_unlock_irqrestore(&vop->irq_lock, flags); |
1081 | ||
1082 | /* This is expected for vop iommu irqs, since the irq is shared */ | |
1083 | if (!active_irqs) | |
1084 | return IRQ_NONE; | |
1085 | ||
1067219b MY |
1086 | if (active_irqs & DSP_HOLD_VALID_INTR) { |
1087 | complete(&vop->dsp_hold_completion); | |
1088 | active_irqs &= ~DSP_HOLD_VALID_INTR; | |
1089 | ret = IRQ_HANDLED; | |
2048e328 MY |
1090 | } |
1091 | ||
1067219b | 1092 | if (active_irqs & FS_INTR) { |
b5f7b755 | 1093 | drm_crtc_handle_vblank(crtc); |
63ebb9fa | 1094 | vop_handle_vblank(vop); |
1067219b | 1095 | active_irqs &= ~FS_INTR; |
63ebb9fa | 1096 | ret = IRQ_HANDLED; |
1067219b | 1097 | } |
2048e328 | 1098 | |
1067219b MY |
1099 | /* Unhandled irqs are spurious. */ |
1100 | if (active_irqs) | |
1101 | DRM_ERROR("Unknown VOP IRQs: %#02x\n", active_irqs); | |
1102 | ||
1103 | return ret; | |
2048e328 MY |
1104 | } |
1105 | ||
1106 | static int vop_create_crtc(struct vop *vop) | |
1107 | { | |
1108 | const struct vop_data *vop_data = vop->data; | |
1109 | struct device *dev = vop->dev; | |
1110 | struct drm_device *drm_dev = vop->drm_dev; | |
1111 | struct drm_plane *primary = NULL, *cursor = NULL, *plane; | |
1112 | struct drm_crtc *crtc = &vop->crtc; | |
1113 | struct device_node *port; | |
1114 | int ret; | |
1115 | int i; | |
1116 | ||
1117 | /* | |
1118 | * Create drm_plane for primary and cursor planes first, since we need | |
1119 | * to pass them to drm_crtc_init_with_planes, which sets the | |
1120 | * "possible_crtcs" to the newly initialized crtc. | |
1121 | */ | |
1122 | for (i = 0; i < vop_data->win_size; i++) { | |
1123 | struct vop_win *vop_win = &vop->win[i]; | |
1124 | const struct vop_win_data *win_data = vop_win->data; | |
1125 | ||
1126 | if (win_data->type != DRM_PLANE_TYPE_PRIMARY && | |
1127 | win_data->type != DRM_PLANE_TYPE_CURSOR) | |
1128 | continue; | |
1129 | ||
1130 | ret = drm_universal_plane_init(vop->drm_dev, &vop_win->base, | |
1131 | 0, &vop_plane_funcs, | |
1132 | win_data->phy->data_formats, | |
1133 | win_data->phy->nformats, | |
b0b3b795 | 1134 | win_data->type, NULL); |
2048e328 MY |
1135 | if (ret) { |
1136 | DRM_ERROR("failed to initialize plane\n"); | |
1137 | goto err_cleanup_planes; | |
1138 | } | |
1139 | ||
1140 | plane = &vop_win->base; | |
63ebb9fa | 1141 | drm_plane_helper_add(plane, &plane_helper_funcs); |
2048e328 MY |
1142 | if (plane->type == DRM_PLANE_TYPE_PRIMARY) |
1143 | primary = plane; | |
1144 | else if (plane->type == DRM_PLANE_TYPE_CURSOR) | |
1145 | cursor = plane; | |
1146 | } | |
1147 | ||
1148 | ret = drm_crtc_init_with_planes(drm_dev, crtc, primary, cursor, | |
f9882876 | 1149 | &vop_crtc_funcs, NULL); |
2048e328 MY |
1150 | if (ret) |
1151 | return ret; | |
1152 | ||
1153 | drm_crtc_helper_add(crtc, &vop_crtc_helper_funcs); | |
1154 | ||
1155 | /* | |
1156 | * Create drm_planes for overlay windows with possible_crtcs restricted | |
1157 | * to the newly created crtc. | |
1158 | */ | |
1159 | for (i = 0; i < vop_data->win_size; i++) { | |
1160 | struct vop_win *vop_win = &vop->win[i]; | |
1161 | const struct vop_win_data *win_data = vop_win->data; | |
1162 | unsigned long possible_crtcs = 1 << drm_crtc_index(crtc); | |
1163 | ||
1164 | if (win_data->type != DRM_PLANE_TYPE_OVERLAY) | |
1165 | continue; | |
1166 | ||
1167 | ret = drm_universal_plane_init(vop->drm_dev, &vop_win->base, | |
1168 | possible_crtcs, | |
1169 | &vop_plane_funcs, | |
1170 | win_data->phy->data_formats, | |
1171 | win_data->phy->nformats, | |
b0b3b795 | 1172 | win_data->type, NULL); |
2048e328 MY |
1173 | if (ret) { |
1174 | DRM_ERROR("failed to initialize overlay plane\n"); | |
1175 | goto err_cleanup_crtc; | |
1176 | } | |
63ebb9fa | 1177 | drm_plane_helper_add(&vop_win->base, &plane_helper_funcs); |
2048e328 MY |
1178 | } |
1179 | ||
1180 | port = of_get_child_by_name(dev->of_node, "port"); | |
1181 | if (!port) { | |
1182 | DRM_ERROR("no port node found in %s\n", | |
1183 | dev->of_node->full_name); | |
1184 | goto err_cleanup_crtc; | |
1185 | } | |
1186 | ||
1067219b | 1187 | init_completion(&vop->dsp_hold_completion); |
63ebb9fa | 1188 | init_completion(&vop->wait_update_complete); |
2048e328 | 1189 | crtc->port = port; |
b5f7b755 | 1190 | rockchip_register_crtc_funcs(crtc, &private_crtc_funcs); |
2048e328 MY |
1191 | |
1192 | return 0; | |
1193 | ||
1194 | err_cleanup_crtc: | |
1195 | drm_crtc_cleanup(crtc); | |
1196 | err_cleanup_planes: | |
1197 | list_for_each_entry(plane, &drm_dev->mode_config.plane_list, head) | |
1198 | drm_plane_cleanup(plane); | |
1199 | return ret; | |
1200 | } | |
1201 | ||
1202 | static void vop_destroy_crtc(struct vop *vop) | |
1203 | { | |
1204 | struct drm_crtc *crtc = &vop->crtc; | |
1205 | ||
b5f7b755 | 1206 | rockchip_unregister_crtc_funcs(crtc); |
2048e328 MY |
1207 | of_node_put(crtc->port); |
1208 | drm_crtc_cleanup(crtc); | |
1209 | } | |
1210 | ||
1211 | static int vop_initial(struct vop *vop) | |
1212 | { | |
1213 | const struct vop_data *vop_data = vop->data; | |
1214 | const struct vop_reg_data *init_table = vop_data->init_table; | |
1215 | struct reset_control *ahb_rst; | |
1216 | int i, ret; | |
1217 | ||
1218 | vop->hclk = devm_clk_get(vop->dev, "hclk_vop"); | |
1219 | if (IS_ERR(vop->hclk)) { | |
1220 | dev_err(vop->dev, "failed to get hclk source\n"); | |
1221 | return PTR_ERR(vop->hclk); | |
1222 | } | |
1223 | vop->aclk = devm_clk_get(vop->dev, "aclk_vop"); | |
1224 | if (IS_ERR(vop->aclk)) { | |
1225 | dev_err(vop->dev, "failed to get aclk source\n"); | |
1226 | return PTR_ERR(vop->aclk); | |
1227 | } | |
1228 | vop->dclk = devm_clk_get(vop->dev, "dclk_vop"); | |
1229 | if (IS_ERR(vop->dclk)) { | |
1230 | dev_err(vop->dev, "failed to get dclk source\n"); | |
1231 | return PTR_ERR(vop->dclk); | |
1232 | } | |
1233 | ||
2048e328 MY |
1234 | ret = clk_prepare(vop->dclk); |
1235 | if (ret < 0) { | |
1236 | dev_err(vop->dev, "failed to prepare dclk\n"); | |
d7b53fd9 | 1237 | return ret; |
2048e328 MY |
1238 | } |
1239 | ||
d7b53fd9 SS |
1240 | /* Enable both the hclk and aclk to setup the vop */ |
1241 | ret = clk_prepare_enable(vop->hclk); | |
2048e328 | 1242 | if (ret < 0) { |
d7b53fd9 | 1243 | dev_err(vop->dev, "failed to prepare/enable hclk\n"); |
2048e328 MY |
1244 | goto err_unprepare_dclk; |
1245 | } | |
1246 | ||
d7b53fd9 | 1247 | ret = clk_prepare_enable(vop->aclk); |
2048e328 | 1248 | if (ret < 0) { |
d7b53fd9 SS |
1249 | dev_err(vop->dev, "failed to prepare/enable aclk\n"); |
1250 | goto err_disable_hclk; | |
2048e328 | 1251 | } |
d7b53fd9 | 1252 | |
2048e328 MY |
1253 | /* |
1254 | * do hclk_reset, reset all vop registers. | |
1255 | */ | |
1256 | ahb_rst = devm_reset_control_get(vop->dev, "ahb"); | |
1257 | if (IS_ERR(ahb_rst)) { | |
1258 | dev_err(vop->dev, "failed to get ahb reset\n"); | |
1259 | ret = PTR_ERR(ahb_rst); | |
d7b53fd9 | 1260 | goto err_disable_aclk; |
2048e328 MY |
1261 | } |
1262 | reset_control_assert(ahb_rst); | |
1263 | usleep_range(10, 20); | |
1264 | reset_control_deassert(ahb_rst); | |
1265 | ||
1266 | memcpy(vop->regsbak, vop->regs, vop->len); | |
1267 | ||
1268 | for (i = 0; i < vop_data->table_size; i++) | |
1269 | vop_writel(vop, init_table[i].offset, init_table[i].value); | |
1270 | ||
1271 | for (i = 0; i < vop_data->win_size; i++) { | |
1272 | const struct vop_win_data *win = &vop_data->win[i]; | |
1273 | ||
1274 | VOP_WIN_SET(vop, win, enable, 0); | |
1275 | } | |
1276 | ||
1277 | vop_cfg_done(vop); | |
1278 | ||
1279 | /* | |
1280 | * do dclk_reset, let all config take affect. | |
1281 | */ | |
1282 | vop->dclk_rst = devm_reset_control_get(vop->dev, "dclk"); | |
1283 | if (IS_ERR(vop->dclk_rst)) { | |
1284 | dev_err(vop->dev, "failed to get dclk reset\n"); | |
1285 | ret = PTR_ERR(vop->dclk_rst); | |
d7b53fd9 | 1286 | goto err_disable_aclk; |
2048e328 MY |
1287 | } |
1288 | reset_control_assert(vop->dclk_rst); | |
1289 | usleep_range(10, 20); | |
1290 | reset_control_deassert(vop->dclk_rst); | |
1291 | ||
1292 | clk_disable(vop->hclk); | |
d7b53fd9 | 1293 | clk_disable(vop->aclk); |
2048e328 | 1294 | |
31e980c5 | 1295 | vop->is_enabled = false; |
2048e328 MY |
1296 | |
1297 | return 0; | |
1298 | ||
d7b53fd9 SS |
1299 | err_disable_aclk: |
1300 | clk_disable_unprepare(vop->aclk); | |
2048e328 | 1301 | err_disable_hclk: |
d7b53fd9 | 1302 | clk_disable_unprepare(vop->hclk); |
2048e328 MY |
1303 | err_unprepare_dclk: |
1304 | clk_unprepare(vop->dclk); | |
2048e328 MY |
1305 | return ret; |
1306 | } | |
1307 | ||
1308 | /* | |
1309 | * Initialize the vop->win array elements. | |
1310 | */ | |
1311 | static void vop_win_init(struct vop *vop) | |
1312 | { | |
1313 | const struct vop_data *vop_data = vop->data; | |
1314 | unsigned int i; | |
1315 | ||
1316 | for (i = 0; i < vop_data->win_size; i++) { | |
1317 | struct vop_win *vop_win = &vop->win[i]; | |
1318 | const struct vop_win_data *win_data = &vop_data->win[i]; | |
1319 | ||
1320 | vop_win->data = win_data; | |
1321 | vop_win->vop = vop; | |
2048e328 MY |
1322 | } |
1323 | } | |
1324 | ||
1325 | static int vop_bind(struct device *dev, struct device *master, void *data) | |
1326 | { | |
1327 | struct platform_device *pdev = to_platform_device(dev); | |
2048e328 MY |
1328 | const struct vop_data *vop_data; |
1329 | struct drm_device *drm_dev = data; | |
1330 | struct vop *vop; | |
1331 | struct resource *res; | |
1332 | size_t alloc_size; | |
3ea68922 | 1333 | int ret, irq; |
2048e328 | 1334 | |
a67719d1 | 1335 | vop_data = of_device_get_match_data(dev); |
2048e328 MY |
1336 | if (!vop_data) |
1337 | return -ENODEV; | |
1338 | ||
1339 | /* Allocate vop struct and its vop_win array */ | |
1340 | alloc_size = sizeof(*vop) + sizeof(*vop->win) * vop_data->win_size; | |
1341 | vop = devm_kzalloc(dev, alloc_size, GFP_KERNEL); | |
1342 | if (!vop) | |
1343 | return -ENOMEM; | |
1344 | ||
1345 | vop->dev = dev; | |
1346 | vop->data = vop_data; | |
1347 | vop->drm_dev = drm_dev; | |
1348 | dev_set_drvdata(dev, vop); | |
1349 | ||
1350 | vop_win_init(vop); | |
1351 | ||
1352 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
1353 | vop->len = resource_size(res); | |
1354 | vop->regs = devm_ioremap_resource(dev, res); | |
1355 | if (IS_ERR(vop->regs)) | |
1356 | return PTR_ERR(vop->regs); | |
1357 | ||
1358 | vop->regsbak = devm_kzalloc(dev, vop->len, GFP_KERNEL); | |
1359 | if (!vop->regsbak) | |
1360 | return -ENOMEM; | |
1361 | ||
1362 | ret = vop_initial(vop); | |
1363 | if (ret < 0) { | |
1364 | dev_err(&pdev->dev, "cannot initial vop dev - err %d\n", ret); | |
1365 | return ret; | |
1366 | } | |
1367 | ||
3ea68922 HS |
1368 | irq = platform_get_irq(pdev, 0); |
1369 | if (irq < 0) { | |
2048e328 | 1370 | dev_err(dev, "cannot find irq for vop\n"); |
3ea68922 | 1371 | return irq; |
2048e328 | 1372 | } |
3ea68922 | 1373 | vop->irq = (unsigned int)irq; |
2048e328 MY |
1374 | |
1375 | spin_lock_init(&vop->reg_lock); | |
1376 | spin_lock_init(&vop->irq_lock); | |
1377 | ||
1378 | mutex_init(&vop->vsync_mutex); | |
1379 | ||
63ebb9fa MY |
1380 | ret = devm_request_irq(dev, vop->irq, vop_isr, |
1381 | IRQF_SHARED, dev_name(dev), vop); | |
2048e328 MY |
1382 | if (ret) |
1383 | return ret; | |
1384 | ||
1385 | /* IRQ is initially disabled; it gets enabled in power_on */ | |
1386 | disable_irq(vop->irq); | |
1387 | ||
1388 | ret = vop_create_crtc(vop); | |
1389 | if (ret) | |
1390 | return ret; | |
1391 | ||
1392 | pm_runtime_enable(&pdev->dev); | |
1393 | return 0; | |
1394 | } | |
1395 | ||
1396 | static void vop_unbind(struct device *dev, struct device *master, void *data) | |
1397 | { | |
1398 | struct vop *vop = dev_get_drvdata(dev); | |
1399 | ||
1400 | pm_runtime_disable(dev); | |
1401 | vop_destroy_crtc(vop); | |
1402 | } | |
1403 | ||
a67719d1 | 1404 | const struct component_ops vop_component_ops = { |
2048e328 MY |
1405 | .bind = vop_bind, |
1406 | .unbind = vop_unbind, | |
1407 | }; | |
54255e81 | 1408 | EXPORT_SYMBOL_GPL(vop_component_ops); |