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Commit | Line | Data |
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d8f4a9ed TR |
1 | /* |
2 | * Copyright (C) 2012 Avionic Design GmbH | |
d43f81cb | 3 | * Copyright (C) 2012-2013 NVIDIA CORPORATION. All rights reserved. |
d8f4a9ed TR |
4 | * |
5 | * This program is free software; you can redistribute it and/or modify | |
6 | * it under the terms of the GNU General Public License version 2 as | |
7 | * published by the Free Software Foundation. | |
8 | */ | |
9 | ||
4231c6b0 TB |
10 | #ifndef HOST1X_DRM_H |
11 | #define HOST1X_DRM_H 1 | |
d8f4a9ed | 12 | |
e1e90644 TR |
13 | #include <uapi/drm/tegra_drm.h> |
14 | #include <linux/host1x.h> | |
15 | ||
d8f4a9ed TR |
16 | #include <drm/drmP.h> |
17 | #include <drm/drm_crtc_helper.h> | |
18 | #include <drm/drm_edid.h> | |
19 | #include <drm/drm_fb_helper.h> | |
d8f4a9ed TR |
20 | #include <drm/drm_fixed.h> |
21 | ||
ca48080a SW |
22 | struct reset_control; |
23 | ||
de2ba664 AM |
24 | struct tegra_fb { |
25 | struct drm_framebuffer base; | |
26 | struct tegra_bo **planes; | |
27 | unsigned int num_planes; | |
28 | }; | |
29 | ||
30 | struct tegra_fbdev { | |
31 | struct drm_fb_helper base; | |
32 | struct tegra_fb *fb; | |
33 | }; | |
34 | ||
386a2a71 | 35 | struct tegra_drm { |
d8f4a9ed | 36 | struct drm_device *drm; |
d8f4a9ed TR |
37 | |
38 | struct mutex clients_lock; | |
39 | struct list_head clients; | |
40 | ||
de2ba664 | 41 | struct tegra_fbdev *fbdev; |
d8f4a9ed TR |
42 | }; |
43 | ||
53fa7f72 | 44 | struct tegra_drm_client; |
d8f4a9ed | 45 | |
c88c3630 | 46 | struct tegra_drm_context { |
53fa7f72 | 47 | struct tegra_drm_client *client; |
d43f81cb TB |
48 | struct host1x_channel *channel; |
49 | struct list_head list; | |
50 | }; | |
51 | ||
53fa7f72 TR |
52 | struct tegra_drm_client_ops { |
53 | int (*open_channel)(struct tegra_drm_client *client, | |
c88c3630 TR |
54 | struct tegra_drm_context *context); |
55 | void (*close_channel)(struct tegra_drm_context *context); | |
c40f0f1a | 56 | int (*is_addr_reg)(struct device *dev, u32 class, u32 offset); |
c88c3630 | 57 | int (*submit)(struct tegra_drm_context *context, |
d43f81cb TB |
58 | struct drm_tegra_submit *args, struct drm_device *drm, |
59 | struct drm_file *file); | |
60 | }; | |
61 | ||
c40f0f1a TR |
62 | int tegra_drm_submit(struct tegra_drm_context *context, |
63 | struct drm_tegra_submit *args, struct drm_device *drm, | |
64 | struct drm_file *file); | |
65 | ||
53fa7f72 TR |
66 | struct tegra_drm_client { |
67 | struct host1x_client base; | |
776dc384 | 68 | struct list_head list; |
d43f81cb | 69 | |
53fa7f72 | 70 | const struct tegra_drm_client_ops *ops; |
d8f4a9ed TR |
71 | }; |
72 | ||
53fa7f72 | 73 | static inline struct tegra_drm_client * |
776dc384 | 74 | host1x_to_drm_client(struct host1x_client *client) |
53fa7f72 TR |
75 | { |
76 | return container_of(client, struct tegra_drm_client, base); | |
77 | } | |
78 | ||
776dc384 TR |
79 | extern int tegra_drm_register_client(struct tegra_drm *tegra, |
80 | struct tegra_drm_client *client); | |
81 | extern int tegra_drm_unregister_client(struct tegra_drm *tegra, | |
82 | struct tegra_drm_client *client); | |
83 | ||
386a2a71 TR |
84 | extern int tegra_drm_init(struct tegra_drm *tegra, struct drm_device *drm); |
85 | extern int tegra_drm_exit(struct tegra_drm *tegra); | |
d8f4a9ed | 86 | |
d8f4a9ed TR |
87 | struct tegra_output; |
88 | ||
89 | struct tegra_dc { | |
776dc384 | 90 | struct host1x_client client; |
d8f4a9ed | 91 | struct device *dev; |
d18d3033 | 92 | spinlock_t lock; |
d8f4a9ed TR |
93 | |
94 | struct drm_crtc base; | |
95 | int pipe; | |
96 | ||
97 | struct clk *clk; | |
ca48080a | 98 | struct reset_control *rst; |
d8f4a9ed TR |
99 | void __iomem *regs; |
100 | int irq; | |
101 | ||
102 | struct tegra_output *rgb; | |
103 | ||
104 | struct list_head list; | |
105 | ||
106 | struct drm_info_list *debugfs_files; | |
107 | struct drm_minor *minor; | |
108 | struct dentry *debugfs; | |
3c03c46a TR |
109 | |
110 | /* page-flip handling */ | |
111 | struct drm_pending_vblank_event *event; | |
d8f4a9ed TR |
112 | }; |
113 | ||
53fa7f72 | 114 | static inline struct tegra_dc * |
776dc384 | 115 | host1x_client_to_dc(struct host1x_client *client) |
d8f4a9ed TR |
116 | { |
117 | return container_of(client, struct tegra_dc, client); | |
118 | } | |
119 | ||
120 | static inline struct tegra_dc *to_tegra_dc(struct drm_crtc *crtc) | |
121 | { | |
37826519 | 122 | return crtc ? container_of(crtc, struct tegra_dc, base) : NULL; |
d8f4a9ed TR |
123 | } |
124 | ||
125 | static inline void tegra_dc_writel(struct tegra_dc *dc, unsigned long value, | |
126 | unsigned long reg) | |
127 | { | |
128 | writel(value, dc->regs + (reg << 2)); | |
129 | } | |
130 | ||
131 | static inline unsigned long tegra_dc_readl(struct tegra_dc *dc, | |
132 | unsigned long reg) | |
133 | { | |
134 | return readl(dc->regs + (reg << 2)); | |
135 | } | |
136 | ||
f34bc787 TR |
137 | struct tegra_dc_window { |
138 | struct { | |
139 | unsigned int x; | |
140 | unsigned int y; | |
141 | unsigned int w; | |
142 | unsigned int h; | |
143 | } src; | |
144 | struct { | |
145 | unsigned int x; | |
146 | unsigned int y; | |
147 | unsigned int w; | |
148 | unsigned int h; | |
149 | } dst; | |
150 | unsigned int bits_per_pixel; | |
151 | unsigned int format; | |
152 | unsigned int stride[2]; | |
153 | unsigned long base[3]; | |
db7fbdfd | 154 | bool bottom_up; |
773af77f | 155 | bool tiled; |
f34bc787 TR |
156 | }; |
157 | ||
158 | /* from dc.c */ | |
159 | extern unsigned int tegra_dc_format(uint32_t format); | |
160 | extern int tegra_dc_setup_window(struct tegra_dc *dc, unsigned int index, | |
161 | const struct tegra_dc_window *window); | |
6e5ff998 TR |
162 | extern void tegra_dc_enable_vblank(struct tegra_dc *dc); |
163 | extern void tegra_dc_disable_vblank(struct tegra_dc *dc); | |
3c03c46a TR |
164 | extern void tegra_dc_cancel_page_flip(struct drm_crtc *crtc, |
165 | struct drm_file *file); | |
f34bc787 | 166 | |
d8f4a9ed TR |
167 | struct tegra_output_ops { |
168 | int (*enable)(struct tegra_output *output); | |
169 | int (*disable)(struct tegra_output *output); | |
170 | int (*setup_clock)(struct tegra_output *output, struct clk *clk, | |
171 | unsigned long pclk); | |
172 | int (*check_mode)(struct tegra_output *output, | |
173 | struct drm_display_mode *mode, | |
174 | enum drm_mode_status *status); | |
175 | }; | |
176 | ||
177 | enum tegra_output_type { | |
178 | TEGRA_OUTPUT_RGB, | |
edec4af4 | 179 | TEGRA_OUTPUT_HDMI, |
d8f4a9ed TR |
180 | }; |
181 | ||
182 | struct tegra_output { | |
183 | struct device_node *of_node; | |
184 | struct device *dev; | |
185 | ||
186 | const struct tegra_output_ops *ops; | |
187 | enum tegra_output_type type; | |
188 | ||
189 | struct i2c_adapter *ddc; | |
190 | const struct edid *edid; | |
191 | unsigned int hpd_irq; | |
192 | int hpd_gpio; | |
193 | ||
194 | struct drm_encoder encoder; | |
195 | struct drm_connector connector; | |
196 | }; | |
197 | ||
198 | static inline struct tegra_output *encoder_to_output(struct drm_encoder *e) | |
199 | { | |
200 | return container_of(e, struct tegra_output, encoder); | |
201 | } | |
202 | ||
203 | static inline struct tegra_output *connector_to_output(struct drm_connector *c) | |
204 | { | |
205 | return container_of(c, struct tegra_output, connector); | |
206 | } | |
207 | ||
208 | static inline int tegra_output_enable(struct tegra_output *output) | |
209 | { | |
210 | if (output && output->ops && output->ops->enable) | |
211 | return output->ops->enable(output); | |
212 | ||
213 | return output ? -ENOSYS : -EINVAL; | |
214 | } | |
215 | ||
216 | static inline int tegra_output_disable(struct tegra_output *output) | |
217 | { | |
218 | if (output && output->ops && output->ops->disable) | |
219 | return output->ops->disable(output); | |
220 | ||
221 | return output ? -ENOSYS : -EINVAL; | |
222 | } | |
223 | ||
224 | static inline int tegra_output_setup_clock(struct tegra_output *output, | |
225 | struct clk *clk, unsigned long pclk) | |
226 | { | |
227 | if (output && output->ops && output->ops->setup_clock) | |
228 | return output->ops->setup_clock(output, clk, pclk); | |
229 | ||
230 | return output ? -ENOSYS : -EINVAL; | |
231 | } | |
232 | ||
233 | static inline int tegra_output_check_mode(struct tegra_output *output, | |
234 | struct drm_display_mode *mode, | |
235 | enum drm_mode_status *status) | |
236 | { | |
237 | if (output && output->ops && output->ops->check_mode) | |
238 | return output->ops->check_mode(output, mode, status); | |
239 | ||
240 | return output ? -ENOSYS : -EINVAL; | |
241 | } | |
242 | ||
776dc384 TR |
243 | /* from bus.c */ |
244 | int drm_host1x_init(struct drm_driver *driver, struct host1x_device *device); | |
245 | void drm_host1x_exit(struct drm_driver *driver, struct host1x_device *device); | |
246 | ||
d8f4a9ed TR |
247 | /* from rgb.c */ |
248 | extern int tegra_dc_rgb_probe(struct tegra_dc *dc); | |
59d29c0e | 249 | extern int tegra_dc_rgb_remove(struct tegra_dc *dc); |
d8f4a9ed TR |
250 | extern int tegra_dc_rgb_init(struct drm_device *drm, struct tegra_dc *dc); |
251 | extern int tegra_dc_rgb_exit(struct tegra_dc *dc); | |
252 | ||
253 | /* from output.c */ | |
59d29c0e TR |
254 | extern int tegra_output_probe(struct tegra_output *output); |
255 | extern int tegra_output_remove(struct tegra_output *output); | |
d8f4a9ed TR |
256 | extern int tegra_output_init(struct drm_device *drm, struct tegra_output *output); |
257 | extern int tegra_output_exit(struct tegra_output *output); | |
258 | ||
d8f4a9ed | 259 | /* from fb.c */ |
de2ba664 AM |
260 | struct tegra_bo *tegra_fb_get_plane(struct drm_framebuffer *framebuffer, |
261 | unsigned int index); | |
db7fbdfd | 262 | bool tegra_fb_is_bottom_up(struct drm_framebuffer *framebuffer); |
773af77f | 263 | bool tegra_fb_is_tiled(struct drm_framebuffer *framebuffer); |
d8f4a9ed TR |
264 | extern int tegra_drm_fb_init(struct drm_device *drm); |
265 | extern void tegra_drm_fb_exit(struct drm_device *drm); | |
de2ba664 | 266 | extern void tegra_fbdev_restore_mode(struct tegra_fbdev *fbdev); |
d8f4a9ed | 267 | |
776dc384 TR |
268 | extern struct platform_driver tegra_dc_driver; |
269 | extern struct platform_driver tegra_hdmi_driver; | |
270 | extern struct platform_driver tegra_gr2d_driver; | |
5f60ed0d | 271 | extern struct platform_driver tegra_gr3d_driver; |
d8f4a9ed | 272 | |
4231c6b0 | 273 | #endif /* HOST1X_DRM_H */ |