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caab277b | 1 | // SPDX-License-Identifier: GPL-2.0-only |
4078f575 EA |
2 | /* |
3 | * Copyright (C) 2016 Broadcom | |
4078f575 EA |
4 | */ |
5 | ||
6 | /** | |
7 | * DOC: VC4 DSI0/DSI1 module | |
8 | * | |
9 | * BCM2835 contains two DSI modules, DSI0 and DSI1. DSI0 is a | |
10 | * single-lane DSI controller, while DSI1 is a more modern 4-lane DSI | |
11 | * controller. | |
12 | * | |
13 | * Most Raspberry Pi boards expose DSI1 as their "DISPLAY" connector, | |
14 | * while the compute module brings both DSI0 and DSI1 out. | |
15 | * | |
16 | * This driver has been tested for DSI1 video-mode display only | |
17 | * currently, with most of the information necessary for DSI0 | |
18 | * hopefully present. | |
19 | */ | |
20 | ||
b7e8e25b | 21 | #include <drm/drm_atomic_helper.h> |
b7e8e25b MY |
22 | #include <drm/drm_edid.h> |
23 | #include <drm/drm_mipi_dsi.h> | |
32ad958d | 24 | #include <drm/drm_of.h> |
b7e8e25b | 25 | #include <drm/drm_panel.h> |
fcd70cd3 | 26 | #include <drm/drm_probe_helper.h> |
b7e8e25b MY |
27 | #include <linux/clk.h> |
28 | #include <linux/clk-provider.h> | |
29 | #include <linux/completion.h> | |
30 | #include <linux/component.h> | |
31 | #include <linux/dmaengine.h> | |
32 | #include <linux/i2c.h> | |
62e59c4e | 33 | #include <linux/io.h> |
b7e8e25b MY |
34 | #include <linux/of_address.h> |
35 | #include <linux/of_platform.h> | |
36 | #include <linux/pm_runtime.h> | |
4078f575 EA |
37 | #include "vc4_drv.h" |
38 | #include "vc4_regs.h" | |
39 | ||
40 | #define DSI_CMD_FIFO_DEPTH 16 | |
41 | #define DSI_PIX_FIFO_DEPTH 256 | |
42 | #define DSI_PIX_FIFO_WIDTH 4 | |
43 | ||
44 | #define DSI0_CTRL 0x00 | |
45 | ||
46 | /* Command packet control. */ | |
47 | #define DSI0_TXPKT1C 0x04 /* AKA PKTC */ | |
48 | #define DSI1_TXPKT1C 0x04 | |
49 | # define DSI_TXPKT1C_TRIG_CMD_MASK VC4_MASK(31, 24) | |
50 | # define DSI_TXPKT1C_TRIG_CMD_SHIFT 24 | |
51 | # define DSI_TXPKT1C_CMD_REPEAT_MASK VC4_MASK(23, 10) | |
52 | # define DSI_TXPKT1C_CMD_REPEAT_SHIFT 10 | |
53 | ||
54 | # define DSI_TXPKT1C_DISPLAY_NO_MASK VC4_MASK(9, 8) | |
55 | # define DSI_TXPKT1C_DISPLAY_NO_SHIFT 8 | |
56 | /* Short, trigger, BTA, or a long packet that fits all in CMDFIFO. */ | |
57 | # define DSI_TXPKT1C_DISPLAY_NO_SHORT 0 | |
58 | /* Primary display where cmdfifo provides part of the payload and | |
59 | * pixelvalve the rest. | |
60 | */ | |
61 | # define DSI_TXPKT1C_DISPLAY_NO_PRIMARY 1 | |
62 | /* Secondary display where cmdfifo provides part of the payload and | |
63 | * pixfifo the rest. | |
64 | */ | |
65 | # define DSI_TXPKT1C_DISPLAY_NO_SECONDARY 2 | |
66 | ||
67 | # define DSI_TXPKT1C_CMD_TX_TIME_MASK VC4_MASK(7, 6) | |
68 | # define DSI_TXPKT1C_CMD_TX_TIME_SHIFT 6 | |
69 | ||
70 | # define DSI_TXPKT1C_CMD_CTRL_MASK VC4_MASK(5, 4) | |
71 | # define DSI_TXPKT1C_CMD_CTRL_SHIFT 4 | |
72 | /* Command only. Uses TXPKT1H and DISPLAY_NO */ | |
73 | # define DSI_TXPKT1C_CMD_CTRL_TX 0 | |
74 | /* Command with BTA for either ack or read data. */ | |
75 | # define DSI_TXPKT1C_CMD_CTRL_RX 1 | |
76 | /* Trigger according to TRIG_CMD */ | |
77 | # define DSI_TXPKT1C_CMD_CTRL_TRIG 2 | |
78 | /* BTA alone for getting error status after a command, or a TE trigger | |
79 | * without a previous command. | |
80 | */ | |
81 | # define DSI_TXPKT1C_CMD_CTRL_BTA 3 | |
82 | ||
83 | # define DSI_TXPKT1C_CMD_MODE_LP BIT(3) | |
84 | # define DSI_TXPKT1C_CMD_TYPE_LONG BIT(2) | |
85 | # define DSI_TXPKT1C_CMD_TE_EN BIT(1) | |
86 | # define DSI_TXPKT1C_CMD_EN BIT(0) | |
87 | ||
88 | /* Command packet header. */ | |
89 | #define DSI0_TXPKT1H 0x08 /* AKA PKTH */ | |
90 | #define DSI1_TXPKT1H 0x08 | |
91 | # define DSI_TXPKT1H_BC_CMDFIFO_MASK VC4_MASK(31, 24) | |
92 | # define DSI_TXPKT1H_BC_CMDFIFO_SHIFT 24 | |
93 | # define DSI_TXPKT1H_BC_PARAM_MASK VC4_MASK(23, 8) | |
94 | # define DSI_TXPKT1H_BC_PARAM_SHIFT 8 | |
95 | # define DSI_TXPKT1H_BC_DT_MASK VC4_MASK(7, 0) | |
96 | # define DSI_TXPKT1H_BC_DT_SHIFT 0 | |
97 | ||
98 | #define DSI0_RXPKT1H 0x0c /* AKA RX1_PKTH */ | |
99 | #define DSI1_RXPKT1H 0x14 | |
100 | # define DSI_RXPKT1H_CRC_ERR BIT(31) | |
101 | # define DSI_RXPKT1H_DET_ERR BIT(30) | |
102 | # define DSI_RXPKT1H_ECC_ERR BIT(29) | |
103 | # define DSI_RXPKT1H_COR_ERR BIT(28) | |
104 | # define DSI_RXPKT1H_INCOMP_PKT BIT(25) | |
105 | # define DSI_RXPKT1H_PKT_TYPE_LONG BIT(24) | |
106 | /* Byte count if DSI_RXPKT1H_PKT_TYPE_LONG */ | |
107 | # define DSI_RXPKT1H_BC_PARAM_MASK VC4_MASK(23, 8) | |
108 | # define DSI_RXPKT1H_BC_PARAM_SHIFT 8 | |
109 | /* Short return bytes if !DSI_RXPKT1H_PKT_TYPE_LONG */ | |
110 | # define DSI_RXPKT1H_SHORT_1_MASK VC4_MASK(23, 16) | |
111 | # define DSI_RXPKT1H_SHORT_1_SHIFT 16 | |
112 | # define DSI_RXPKT1H_SHORT_0_MASK VC4_MASK(15, 8) | |
113 | # define DSI_RXPKT1H_SHORT_0_SHIFT 8 | |
114 | # define DSI_RXPKT1H_DT_LP_CMD_MASK VC4_MASK(7, 0) | |
115 | # define DSI_RXPKT1H_DT_LP_CMD_SHIFT 0 | |
116 | ||
117 | #define DSI0_RXPKT2H 0x10 /* AKA RX2_PKTH */ | |
118 | #define DSI1_RXPKT2H 0x18 | |
119 | # define DSI_RXPKT1H_DET_ERR BIT(30) | |
120 | # define DSI_RXPKT1H_ECC_ERR BIT(29) | |
121 | # define DSI_RXPKT1H_COR_ERR BIT(28) | |
122 | # define DSI_RXPKT1H_INCOMP_PKT BIT(25) | |
123 | # define DSI_RXPKT1H_BC_PARAM_MASK VC4_MASK(23, 8) | |
124 | # define DSI_RXPKT1H_BC_PARAM_SHIFT 8 | |
125 | # define DSI_RXPKT1H_DT_MASK VC4_MASK(7, 0) | |
126 | # define DSI_RXPKT1H_DT_SHIFT 0 | |
127 | ||
128 | #define DSI0_TXPKT_CMD_FIFO 0x14 /* AKA CMD_DATAF */ | |
129 | #define DSI1_TXPKT_CMD_FIFO 0x1c | |
130 | ||
131 | #define DSI0_DISP0_CTRL 0x18 | |
132 | # define DSI_DISP0_PIX_CLK_DIV_MASK VC4_MASK(21, 13) | |
133 | # define DSI_DISP0_PIX_CLK_DIV_SHIFT 13 | |
134 | # define DSI_DISP0_LP_STOP_CTRL_MASK VC4_MASK(12, 11) | |
135 | # define DSI_DISP0_LP_STOP_CTRL_SHIFT 11 | |
136 | # define DSI_DISP0_LP_STOP_DISABLE 0 | |
137 | # define DSI_DISP0_LP_STOP_PERLINE 1 | |
138 | # define DSI_DISP0_LP_STOP_PERFRAME 2 | |
139 | ||
140 | /* Transmit RGB pixels and null packets only during HACTIVE, instead | |
141 | * of going to LP-STOP. | |
142 | */ | |
143 | # define DSI_DISP_HACTIVE_NULL BIT(10) | |
144 | /* Transmit blanking packet only during vblank, instead of allowing LP-STOP. */ | |
145 | # define DSI_DISP_VBLP_CTRL BIT(9) | |
146 | /* Transmit blanking packet only during HFP, instead of allowing LP-STOP. */ | |
147 | # define DSI_DISP_HFP_CTRL BIT(8) | |
148 | /* Transmit blanking packet only during HBP, instead of allowing LP-STOP. */ | |
149 | # define DSI_DISP_HBP_CTRL BIT(7) | |
150 | # define DSI_DISP0_CHANNEL_MASK VC4_MASK(6, 5) | |
151 | # define DSI_DISP0_CHANNEL_SHIFT 5 | |
152 | /* Enables end events for HSYNC/VSYNC, not just start events. */ | |
153 | # define DSI_DISP0_ST_END BIT(4) | |
154 | # define DSI_DISP0_PFORMAT_MASK VC4_MASK(3, 2) | |
155 | # define DSI_DISP0_PFORMAT_SHIFT 2 | |
156 | # define DSI_PFORMAT_RGB565 0 | |
157 | # define DSI_PFORMAT_RGB666_PACKED 1 | |
158 | # define DSI_PFORMAT_RGB666 2 | |
159 | # define DSI_PFORMAT_RGB888 3 | |
160 | /* Default is VIDEO mode. */ | |
161 | # define DSI_DISP0_COMMAND_MODE BIT(1) | |
162 | # define DSI_DISP0_ENABLE BIT(0) | |
163 | ||
164 | #define DSI0_DISP1_CTRL 0x1c | |
165 | #define DSI1_DISP1_CTRL 0x2c | |
166 | /* Format of the data written to TXPKT_PIX_FIFO. */ | |
167 | # define DSI_DISP1_PFORMAT_MASK VC4_MASK(2, 1) | |
168 | # define DSI_DISP1_PFORMAT_SHIFT 1 | |
169 | # define DSI_DISP1_PFORMAT_16BIT 0 | |
170 | # define DSI_DISP1_PFORMAT_24BIT 1 | |
171 | # define DSI_DISP1_PFORMAT_32BIT_LE 2 | |
172 | # define DSI_DISP1_PFORMAT_32BIT_BE 3 | |
173 | ||
174 | /* DISP1 is always command mode. */ | |
175 | # define DSI_DISP1_ENABLE BIT(0) | |
176 | ||
177 | #define DSI0_TXPKT_PIX_FIFO 0x20 /* AKA PIX_FIFO */ | |
178 | ||
179 | #define DSI0_INT_STAT 0x24 | |
180 | #define DSI0_INT_EN 0x28 | |
181 | # define DSI1_INT_PHY_D3_ULPS BIT(30) | |
182 | # define DSI1_INT_PHY_D3_STOP BIT(29) | |
183 | # define DSI1_INT_PHY_D2_ULPS BIT(28) | |
184 | # define DSI1_INT_PHY_D2_STOP BIT(27) | |
185 | # define DSI1_INT_PHY_D1_ULPS BIT(26) | |
186 | # define DSI1_INT_PHY_D1_STOP BIT(25) | |
187 | # define DSI1_INT_PHY_D0_ULPS BIT(24) | |
188 | # define DSI1_INT_PHY_D0_STOP BIT(23) | |
189 | # define DSI1_INT_FIFO_ERR BIT(22) | |
190 | # define DSI1_INT_PHY_DIR_RTF BIT(21) | |
191 | # define DSI1_INT_PHY_RXLPDT BIT(20) | |
192 | # define DSI1_INT_PHY_RXTRIG BIT(19) | |
193 | # define DSI1_INT_PHY_D0_LPDT BIT(18) | |
194 | # define DSI1_INT_PHY_DIR_FTR BIT(17) | |
195 | ||
196 | /* Signaled when the clock lane enters the given state. */ | |
197 | # define DSI1_INT_PHY_CLOCK_ULPS BIT(16) | |
198 | # define DSI1_INT_PHY_CLOCK_HS BIT(15) | |
199 | # define DSI1_INT_PHY_CLOCK_STOP BIT(14) | |
200 | ||
201 | /* Signaled on timeouts */ | |
202 | # define DSI1_INT_PR_TO BIT(13) | |
203 | # define DSI1_INT_TA_TO BIT(12) | |
204 | # define DSI1_INT_LPRX_TO BIT(11) | |
205 | # define DSI1_INT_HSTX_TO BIT(10) | |
206 | ||
207 | /* Contention on a line when trying to drive the line low */ | |
208 | # define DSI1_INT_ERR_CONT_LP1 BIT(9) | |
209 | # define DSI1_INT_ERR_CONT_LP0 BIT(8) | |
210 | ||
211 | /* Control error: incorrect line state sequence on data lane 0. */ | |
212 | # define DSI1_INT_ERR_CONTROL BIT(7) | |
213 | /* LPDT synchronization error (bits received not a multiple of 8. */ | |
214 | ||
215 | # define DSI1_INT_ERR_SYNC_ESC BIT(6) | |
216 | /* Signaled after receiving an error packet from the display in | |
217 | * response to a read. | |
218 | */ | |
219 | # define DSI1_INT_RXPKT2 BIT(5) | |
220 | /* Signaled after receiving a packet. The header and optional short | |
221 | * response will be in RXPKT1H, and a long response will be in the | |
222 | * RXPKT_FIFO. | |
223 | */ | |
224 | # define DSI1_INT_RXPKT1 BIT(4) | |
225 | # define DSI1_INT_TXPKT2_DONE BIT(3) | |
226 | # define DSI1_INT_TXPKT2_END BIT(2) | |
227 | /* Signaled after all repeats of TXPKT1 are transferred. */ | |
228 | # define DSI1_INT_TXPKT1_DONE BIT(1) | |
229 | /* Signaled after each TXPKT1 repeat is scheduled. */ | |
230 | # define DSI1_INT_TXPKT1_END BIT(0) | |
231 | ||
232 | #define DSI1_INTERRUPTS_ALWAYS_ENABLED (DSI1_INT_ERR_SYNC_ESC | \ | |
233 | DSI1_INT_ERR_CONTROL | \ | |
234 | DSI1_INT_ERR_CONT_LP0 | \ | |
235 | DSI1_INT_ERR_CONT_LP1 | \ | |
236 | DSI1_INT_HSTX_TO | \ | |
237 | DSI1_INT_LPRX_TO | \ | |
238 | DSI1_INT_TA_TO | \ | |
239 | DSI1_INT_PR_TO) | |
240 | ||
241 | #define DSI0_STAT 0x2c | |
242 | #define DSI0_HSTX_TO_CNT 0x30 | |
243 | #define DSI0_LPRX_TO_CNT 0x34 | |
244 | #define DSI0_TA_TO_CNT 0x38 | |
245 | #define DSI0_PR_TO_CNT 0x3c | |
246 | #define DSI0_PHYC 0x40 | |
247 | # define DSI1_PHYC_ESC_CLK_LPDT_MASK VC4_MASK(25, 20) | |
248 | # define DSI1_PHYC_ESC_CLK_LPDT_SHIFT 20 | |
249 | # define DSI1_PHYC_HS_CLK_CONTINUOUS BIT(18) | |
250 | # define DSI0_PHYC_ESC_CLK_LPDT_MASK VC4_MASK(17, 12) | |
251 | # define DSI0_PHYC_ESC_CLK_LPDT_SHIFT 12 | |
252 | # define DSI1_PHYC_CLANE_ULPS BIT(17) | |
253 | # define DSI1_PHYC_CLANE_ENABLE BIT(16) | |
254 | # define DSI_PHYC_DLANE3_ULPS BIT(13) | |
255 | # define DSI_PHYC_DLANE3_ENABLE BIT(12) | |
256 | # define DSI0_PHYC_HS_CLK_CONTINUOUS BIT(10) | |
257 | # define DSI0_PHYC_CLANE_ULPS BIT(9) | |
258 | # define DSI_PHYC_DLANE2_ULPS BIT(9) | |
259 | # define DSI0_PHYC_CLANE_ENABLE BIT(8) | |
260 | # define DSI_PHYC_DLANE2_ENABLE BIT(8) | |
261 | # define DSI_PHYC_DLANE1_ULPS BIT(5) | |
262 | # define DSI_PHYC_DLANE1_ENABLE BIT(4) | |
263 | # define DSI_PHYC_DLANE0_FORCE_STOP BIT(2) | |
264 | # define DSI_PHYC_DLANE0_ULPS BIT(1) | |
265 | # define DSI_PHYC_DLANE0_ENABLE BIT(0) | |
266 | ||
267 | #define DSI0_HS_CLT0 0x44 | |
268 | #define DSI0_HS_CLT1 0x48 | |
269 | #define DSI0_HS_CLT2 0x4c | |
270 | #define DSI0_HS_DLT3 0x50 | |
271 | #define DSI0_HS_DLT4 0x54 | |
272 | #define DSI0_HS_DLT5 0x58 | |
273 | #define DSI0_HS_DLT6 0x5c | |
274 | #define DSI0_HS_DLT7 0x60 | |
275 | ||
276 | #define DSI0_PHY_AFEC0 0x64 | |
277 | # define DSI0_PHY_AFEC0_DDR2CLK_EN BIT(26) | |
278 | # define DSI0_PHY_AFEC0_DDRCLK_EN BIT(25) | |
279 | # define DSI0_PHY_AFEC0_LATCH_ULPS BIT(24) | |
280 | # define DSI1_PHY_AFEC0_IDR_DLANE3_MASK VC4_MASK(31, 29) | |
281 | # define DSI1_PHY_AFEC0_IDR_DLANE3_SHIFT 29 | |
282 | # define DSI1_PHY_AFEC0_IDR_DLANE2_MASK VC4_MASK(28, 26) | |
283 | # define DSI1_PHY_AFEC0_IDR_DLANE2_SHIFT 26 | |
284 | # define DSI1_PHY_AFEC0_IDR_DLANE1_MASK VC4_MASK(27, 23) | |
285 | # define DSI1_PHY_AFEC0_IDR_DLANE1_SHIFT 23 | |
286 | # define DSI1_PHY_AFEC0_IDR_DLANE0_MASK VC4_MASK(22, 20) | |
287 | # define DSI1_PHY_AFEC0_IDR_DLANE0_SHIFT 20 | |
288 | # define DSI1_PHY_AFEC0_IDR_CLANE_MASK VC4_MASK(19, 17) | |
289 | # define DSI1_PHY_AFEC0_IDR_CLANE_SHIFT 17 | |
290 | # define DSI0_PHY_AFEC0_ACTRL_DLANE1_MASK VC4_MASK(23, 20) | |
291 | # define DSI0_PHY_AFEC0_ACTRL_DLANE1_SHIFT 20 | |
292 | # define DSI0_PHY_AFEC0_ACTRL_DLANE0_MASK VC4_MASK(19, 16) | |
293 | # define DSI0_PHY_AFEC0_ACTRL_DLANE0_SHIFT 16 | |
294 | # define DSI0_PHY_AFEC0_ACTRL_CLANE_MASK VC4_MASK(15, 12) | |
295 | # define DSI0_PHY_AFEC0_ACTRL_CLANE_SHIFT 12 | |
296 | # define DSI1_PHY_AFEC0_DDR2CLK_EN BIT(16) | |
297 | # define DSI1_PHY_AFEC0_DDRCLK_EN BIT(15) | |
298 | # define DSI1_PHY_AFEC0_LATCH_ULPS BIT(14) | |
299 | # define DSI1_PHY_AFEC0_RESET BIT(13) | |
300 | # define DSI1_PHY_AFEC0_PD BIT(12) | |
301 | # define DSI0_PHY_AFEC0_RESET BIT(11) | |
302 | # define DSI1_PHY_AFEC0_PD_BG BIT(11) | |
303 | # define DSI0_PHY_AFEC0_PD BIT(10) | |
304 | # define DSI1_PHY_AFEC0_PD_DLANE3 BIT(10) | |
305 | # define DSI0_PHY_AFEC0_PD_BG BIT(9) | |
306 | # define DSI1_PHY_AFEC0_PD_DLANE2 BIT(9) | |
307 | # define DSI0_PHY_AFEC0_PD_DLANE1 BIT(8) | |
308 | # define DSI1_PHY_AFEC0_PD_DLANE1 BIT(8) | |
309 | # define DSI_PHY_AFEC0_PTATADJ_MASK VC4_MASK(7, 4) | |
310 | # define DSI_PHY_AFEC0_PTATADJ_SHIFT 4 | |
311 | # define DSI_PHY_AFEC0_CTATADJ_MASK VC4_MASK(3, 0) | |
312 | # define DSI_PHY_AFEC0_CTATADJ_SHIFT 0 | |
313 | ||
314 | #define DSI0_PHY_AFEC1 0x68 | |
315 | # define DSI0_PHY_AFEC1_IDR_DLANE1_MASK VC4_MASK(10, 8) | |
316 | # define DSI0_PHY_AFEC1_IDR_DLANE1_SHIFT 8 | |
317 | # define DSI0_PHY_AFEC1_IDR_DLANE0_MASK VC4_MASK(6, 4) | |
318 | # define DSI0_PHY_AFEC1_IDR_DLANE0_SHIFT 4 | |
319 | # define DSI0_PHY_AFEC1_IDR_CLANE_MASK VC4_MASK(2, 0) | |
320 | # define DSI0_PHY_AFEC1_IDR_CLANE_SHIFT 0 | |
321 | ||
322 | #define DSI0_TST_SEL 0x6c | |
323 | #define DSI0_TST_MON 0x70 | |
324 | #define DSI0_ID 0x74 | |
325 | # define DSI_ID_VALUE 0x00647369 | |
326 | ||
327 | #define DSI1_CTRL 0x00 | |
328 | # define DSI_CTRL_HS_CLKC_MASK VC4_MASK(15, 14) | |
329 | # define DSI_CTRL_HS_CLKC_SHIFT 14 | |
330 | # define DSI_CTRL_HS_CLKC_BYTE 0 | |
331 | # define DSI_CTRL_HS_CLKC_DDR2 1 | |
332 | # define DSI_CTRL_HS_CLKC_DDR 2 | |
333 | ||
334 | # define DSI_CTRL_RX_LPDT_EOT_DISABLE BIT(13) | |
335 | # define DSI_CTRL_LPDT_EOT_DISABLE BIT(12) | |
336 | # define DSI_CTRL_HSDT_EOT_DISABLE BIT(11) | |
337 | # define DSI_CTRL_SOFT_RESET_CFG BIT(10) | |
338 | # define DSI_CTRL_CAL_BYTE BIT(9) | |
339 | # define DSI_CTRL_INV_BYTE BIT(8) | |
340 | # define DSI_CTRL_CLR_LDF BIT(7) | |
341 | # define DSI0_CTRL_CLR_PBCF BIT(6) | |
342 | # define DSI1_CTRL_CLR_RXF BIT(6) | |
343 | # define DSI0_CTRL_CLR_CPBCF BIT(5) | |
344 | # define DSI1_CTRL_CLR_PDF BIT(5) | |
345 | # define DSI0_CTRL_CLR_PDF BIT(4) | |
346 | # define DSI1_CTRL_CLR_CDF BIT(4) | |
347 | # define DSI0_CTRL_CLR_CDF BIT(3) | |
348 | # define DSI0_CTRL_CTRL2 BIT(2) | |
349 | # define DSI1_CTRL_DISABLE_DISP_CRCC BIT(2) | |
350 | # define DSI0_CTRL_CTRL1 BIT(1) | |
351 | # define DSI1_CTRL_DISABLE_DISP_ECCC BIT(1) | |
352 | # define DSI0_CTRL_CTRL0 BIT(0) | |
353 | # define DSI1_CTRL_EN BIT(0) | |
354 | # define DSI0_CTRL_RESET_FIFOS (DSI_CTRL_CLR_LDF | \ | |
355 | DSI0_CTRL_CLR_PBCF | \ | |
356 | DSI0_CTRL_CLR_CPBCF | \ | |
357 | DSI0_CTRL_CLR_PDF | \ | |
358 | DSI0_CTRL_CLR_CDF) | |
359 | # define DSI1_CTRL_RESET_FIFOS (DSI_CTRL_CLR_LDF | \ | |
360 | DSI1_CTRL_CLR_RXF | \ | |
361 | DSI1_CTRL_CLR_PDF | \ | |
362 | DSI1_CTRL_CLR_CDF) | |
363 | ||
364 | #define DSI1_TXPKT2C 0x0c | |
365 | #define DSI1_TXPKT2H 0x10 | |
366 | #define DSI1_TXPKT_PIX_FIFO 0x20 | |
367 | #define DSI1_RXPKT_FIFO 0x24 | |
368 | #define DSI1_DISP0_CTRL 0x28 | |
369 | #define DSI1_INT_STAT 0x30 | |
370 | #define DSI1_INT_EN 0x34 | |
371 | /* State reporting bits. These mostly behave like INT_STAT, where | |
372 | * writing a 1 clears the bit. | |
373 | */ | |
374 | #define DSI1_STAT 0x38 | |
375 | # define DSI1_STAT_PHY_D3_ULPS BIT(31) | |
376 | # define DSI1_STAT_PHY_D3_STOP BIT(30) | |
377 | # define DSI1_STAT_PHY_D2_ULPS BIT(29) | |
378 | # define DSI1_STAT_PHY_D2_STOP BIT(28) | |
379 | # define DSI1_STAT_PHY_D1_ULPS BIT(27) | |
380 | # define DSI1_STAT_PHY_D1_STOP BIT(26) | |
381 | # define DSI1_STAT_PHY_D0_ULPS BIT(25) | |
382 | # define DSI1_STAT_PHY_D0_STOP BIT(24) | |
383 | # define DSI1_STAT_FIFO_ERR BIT(23) | |
384 | # define DSI1_STAT_PHY_RXLPDT BIT(22) | |
385 | # define DSI1_STAT_PHY_RXTRIG BIT(21) | |
386 | # define DSI1_STAT_PHY_D0_LPDT BIT(20) | |
387 | /* Set when in forward direction */ | |
388 | # define DSI1_STAT_PHY_DIR BIT(19) | |
389 | # define DSI1_STAT_PHY_CLOCK_ULPS BIT(18) | |
390 | # define DSI1_STAT_PHY_CLOCK_HS BIT(17) | |
391 | # define DSI1_STAT_PHY_CLOCK_STOP BIT(16) | |
392 | # define DSI1_STAT_PR_TO BIT(15) | |
393 | # define DSI1_STAT_TA_TO BIT(14) | |
394 | # define DSI1_STAT_LPRX_TO BIT(13) | |
395 | # define DSI1_STAT_HSTX_TO BIT(12) | |
396 | # define DSI1_STAT_ERR_CONT_LP1 BIT(11) | |
397 | # define DSI1_STAT_ERR_CONT_LP0 BIT(10) | |
398 | # define DSI1_STAT_ERR_CONTROL BIT(9) | |
399 | # define DSI1_STAT_ERR_SYNC_ESC BIT(8) | |
400 | # define DSI1_STAT_RXPKT2 BIT(7) | |
401 | # define DSI1_STAT_RXPKT1 BIT(6) | |
402 | # define DSI1_STAT_TXPKT2_BUSY BIT(5) | |
403 | # define DSI1_STAT_TXPKT2_DONE BIT(4) | |
404 | # define DSI1_STAT_TXPKT2_END BIT(3) | |
405 | # define DSI1_STAT_TXPKT1_BUSY BIT(2) | |
406 | # define DSI1_STAT_TXPKT1_DONE BIT(1) | |
407 | # define DSI1_STAT_TXPKT1_END BIT(0) | |
408 | ||
409 | #define DSI1_HSTX_TO_CNT 0x3c | |
410 | #define DSI1_LPRX_TO_CNT 0x40 | |
411 | #define DSI1_TA_TO_CNT 0x44 | |
412 | #define DSI1_PR_TO_CNT 0x48 | |
413 | #define DSI1_PHYC 0x4c | |
414 | ||
415 | #define DSI1_HS_CLT0 0x50 | |
416 | # define DSI_HS_CLT0_CZERO_MASK VC4_MASK(26, 18) | |
417 | # define DSI_HS_CLT0_CZERO_SHIFT 18 | |
418 | # define DSI_HS_CLT0_CPRE_MASK VC4_MASK(17, 9) | |
419 | # define DSI_HS_CLT0_CPRE_SHIFT 9 | |
420 | # define DSI_HS_CLT0_CPREP_MASK VC4_MASK(8, 0) | |
421 | # define DSI_HS_CLT0_CPREP_SHIFT 0 | |
422 | ||
423 | #define DSI1_HS_CLT1 0x54 | |
424 | # define DSI_HS_CLT1_CTRAIL_MASK VC4_MASK(17, 9) | |
425 | # define DSI_HS_CLT1_CTRAIL_SHIFT 9 | |
426 | # define DSI_HS_CLT1_CPOST_MASK VC4_MASK(8, 0) | |
427 | # define DSI_HS_CLT1_CPOST_SHIFT 0 | |
428 | ||
429 | #define DSI1_HS_CLT2 0x58 | |
430 | # define DSI_HS_CLT2_WUP_MASK VC4_MASK(23, 0) | |
431 | # define DSI_HS_CLT2_WUP_SHIFT 0 | |
432 | ||
433 | #define DSI1_HS_DLT3 0x5c | |
434 | # define DSI_HS_DLT3_EXIT_MASK VC4_MASK(26, 18) | |
435 | # define DSI_HS_DLT3_EXIT_SHIFT 18 | |
436 | # define DSI_HS_DLT3_ZERO_MASK VC4_MASK(17, 9) | |
437 | # define DSI_HS_DLT3_ZERO_SHIFT 9 | |
438 | # define DSI_HS_DLT3_PRE_MASK VC4_MASK(8, 0) | |
439 | # define DSI_HS_DLT3_PRE_SHIFT 0 | |
440 | ||
441 | #define DSI1_HS_DLT4 0x60 | |
442 | # define DSI_HS_DLT4_ANLAT_MASK VC4_MASK(22, 18) | |
443 | # define DSI_HS_DLT4_ANLAT_SHIFT 18 | |
444 | # define DSI_HS_DLT4_TRAIL_MASK VC4_MASK(17, 9) | |
445 | # define DSI_HS_DLT4_TRAIL_SHIFT 9 | |
446 | # define DSI_HS_DLT4_LPX_MASK VC4_MASK(8, 0) | |
447 | # define DSI_HS_DLT4_LPX_SHIFT 0 | |
448 | ||
449 | #define DSI1_HS_DLT5 0x64 | |
450 | # define DSI_HS_DLT5_INIT_MASK VC4_MASK(23, 0) | |
451 | # define DSI_HS_DLT5_INIT_SHIFT 0 | |
452 | ||
453 | #define DSI1_HS_DLT6 0x68 | |
454 | # define DSI_HS_DLT6_TA_GET_MASK VC4_MASK(31, 24) | |
455 | # define DSI_HS_DLT6_TA_GET_SHIFT 24 | |
456 | # define DSI_HS_DLT6_TA_SURE_MASK VC4_MASK(23, 16) | |
457 | # define DSI_HS_DLT6_TA_SURE_SHIFT 16 | |
458 | # define DSI_HS_DLT6_TA_GO_MASK VC4_MASK(15, 8) | |
459 | # define DSI_HS_DLT6_TA_GO_SHIFT 8 | |
460 | # define DSI_HS_DLT6_LP_LPX_MASK VC4_MASK(7, 0) | |
461 | # define DSI_HS_DLT6_LP_LPX_SHIFT 0 | |
462 | ||
463 | #define DSI1_HS_DLT7 0x6c | |
464 | # define DSI_HS_DLT7_LP_WUP_MASK VC4_MASK(23, 0) | |
465 | # define DSI_HS_DLT7_LP_WUP_SHIFT 0 | |
466 | ||
467 | #define DSI1_PHY_AFEC0 0x70 | |
468 | ||
469 | #define DSI1_PHY_AFEC1 0x74 | |
470 | # define DSI1_PHY_AFEC1_ACTRL_DLANE3_MASK VC4_MASK(19, 16) | |
471 | # define DSI1_PHY_AFEC1_ACTRL_DLANE3_SHIFT 16 | |
472 | # define DSI1_PHY_AFEC1_ACTRL_DLANE2_MASK VC4_MASK(15, 12) | |
473 | # define DSI1_PHY_AFEC1_ACTRL_DLANE2_SHIFT 12 | |
474 | # define DSI1_PHY_AFEC1_ACTRL_DLANE1_MASK VC4_MASK(11, 8) | |
475 | # define DSI1_PHY_AFEC1_ACTRL_DLANE1_SHIFT 8 | |
476 | # define DSI1_PHY_AFEC1_ACTRL_DLANE0_MASK VC4_MASK(7, 4) | |
477 | # define DSI1_PHY_AFEC1_ACTRL_DLANE0_SHIFT 4 | |
478 | # define DSI1_PHY_AFEC1_ACTRL_CLANE_MASK VC4_MASK(3, 0) | |
479 | # define DSI1_PHY_AFEC1_ACTRL_CLANE_SHIFT 0 | |
480 | ||
481 | #define DSI1_TST_SEL 0x78 | |
482 | #define DSI1_TST_MON 0x7c | |
483 | #define DSI1_PHY_TST1 0x80 | |
484 | #define DSI1_PHY_TST2 0x84 | |
485 | #define DSI1_PHY_FIFO_STAT 0x88 | |
486 | /* Actually, all registers in the range that aren't otherwise claimed | |
487 | * will return the ID. | |
488 | */ | |
489 | #define DSI1_ID 0x8c | |
490 | ||
491 | /* General DSI hardware state. */ | |
492 | struct vc4_dsi { | |
493 | struct platform_device *pdev; | |
494 | ||
495 | struct mipi_dsi_host dsi_host; | |
496 | struct drm_encoder *encoder; | |
656fa22f | 497 | struct drm_bridge *bridge; |
4078f575 EA |
498 | |
499 | void __iomem *regs; | |
500 | ||
501 | struct dma_chan *reg_dma_chan; | |
502 | dma_addr_t reg_dma_paddr; | |
503 | u32 *reg_dma_mem; | |
504 | dma_addr_t reg_paddr; | |
505 | ||
506 | /* Whether we're on bcm2835's DSI0 or DSI1. */ | |
507 | int port; | |
508 | ||
509 | /* DSI channel for the panel we're connected to. */ | |
510 | u32 channel; | |
511 | u32 lanes; | |
86c1b9ef EA |
512 | u32 format; |
513 | u32 divider; | |
4078f575 EA |
514 | u32 mode_flags; |
515 | ||
516 | /* Input clock from CPRMAN to the digital PHY, for the DSI | |
517 | * escape clock. | |
518 | */ | |
519 | struct clk *escape_clock; | |
520 | ||
521 | /* Input clock to the analog PHY, used to generate the DSI bit | |
522 | * clock. | |
523 | */ | |
524 | struct clk *pll_phy_clock; | |
525 | ||
526 | /* HS Clocks generated within the DSI analog PHY. */ | |
527 | struct clk_fixed_factor phy_clocks[3]; | |
528 | ||
529 | struct clk_hw_onecell_data *clk_onecell; | |
530 | ||
531 | /* Pixel clock output to the pixelvalve, generated from the HS | |
532 | * clock. | |
533 | */ | |
534 | struct clk *pixel_clock; | |
535 | ||
536 | struct completion xfer_completion; | |
537 | int xfer_result; | |
3051719a EA |
538 | |
539 | struct debugfs_regset32 regset; | |
4078f575 EA |
540 | }; |
541 | ||
542 | #define host_to_dsi(host) container_of(host, struct vc4_dsi, dsi_host) | |
543 | ||
544 | static inline void | |
545 | dsi_dma_workaround_write(struct vc4_dsi *dsi, u32 offset, u32 val) | |
546 | { | |
547 | struct dma_chan *chan = dsi->reg_dma_chan; | |
548 | struct dma_async_tx_descriptor *tx; | |
549 | dma_cookie_t cookie; | |
550 | int ret; | |
551 | ||
552 | /* DSI0 should be able to write normally. */ | |
553 | if (!chan) { | |
554 | writel(val, dsi->regs + offset); | |
555 | return; | |
556 | } | |
557 | ||
558 | *dsi->reg_dma_mem = val; | |
559 | ||
560 | tx = chan->device->device_prep_dma_memcpy(chan, | |
561 | dsi->reg_paddr + offset, | |
562 | dsi->reg_dma_paddr, | |
563 | 4, 0); | |
564 | if (!tx) { | |
565 | DRM_ERROR("Failed to set up DMA register write\n"); | |
566 | return; | |
567 | } | |
568 | ||
569 | cookie = tx->tx_submit(tx); | |
570 | ret = dma_submit_error(cookie); | |
571 | if (ret) { | |
572 | DRM_ERROR("Failed to submit DMA: %d\n", ret); | |
573 | return; | |
574 | } | |
575 | ret = dma_sync_wait(chan, cookie); | |
576 | if (ret) | |
577 | DRM_ERROR("Failed to wait for DMA: %d\n", ret); | |
578 | } | |
579 | ||
580 | #define DSI_READ(offset) readl(dsi->regs + (offset)) | |
581 | #define DSI_WRITE(offset, val) dsi_dma_workaround_write(dsi, offset, val) | |
582 | #define DSI_PORT_READ(offset) \ | |
583 | DSI_READ(dsi->port ? DSI1_##offset : DSI0_##offset) | |
584 | #define DSI_PORT_WRITE(offset, val) \ | |
585 | DSI_WRITE(dsi->port ? DSI1_##offset : DSI0_##offset, val) | |
586 | #define DSI_PORT_BIT(bit) (dsi->port ? DSI1_##bit : DSI0_##bit) | |
587 | ||
588 | /* VC4 DSI encoder KMS struct */ | |
589 | struct vc4_dsi_encoder { | |
590 | struct vc4_encoder base; | |
591 | struct vc4_dsi *dsi; | |
592 | }; | |
593 | ||
594 | static inline struct vc4_dsi_encoder * | |
595 | to_vc4_dsi_encoder(struct drm_encoder *encoder) | |
596 | { | |
597 | return container_of(encoder, struct vc4_dsi_encoder, base.base); | |
598 | } | |
599 | ||
3051719a EA |
600 | static const struct debugfs_reg32 dsi0_regs[] = { |
601 | VC4_REG32(DSI0_CTRL), | |
602 | VC4_REG32(DSI0_STAT), | |
603 | VC4_REG32(DSI0_HSTX_TO_CNT), | |
604 | VC4_REG32(DSI0_LPRX_TO_CNT), | |
605 | VC4_REG32(DSI0_TA_TO_CNT), | |
606 | VC4_REG32(DSI0_PR_TO_CNT), | |
607 | VC4_REG32(DSI0_DISP0_CTRL), | |
608 | VC4_REG32(DSI0_DISP1_CTRL), | |
609 | VC4_REG32(DSI0_INT_STAT), | |
610 | VC4_REG32(DSI0_INT_EN), | |
611 | VC4_REG32(DSI0_PHYC), | |
612 | VC4_REG32(DSI0_HS_CLT0), | |
613 | VC4_REG32(DSI0_HS_CLT1), | |
614 | VC4_REG32(DSI0_HS_CLT2), | |
615 | VC4_REG32(DSI0_HS_DLT3), | |
616 | VC4_REG32(DSI0_HS_DLT4), | |
617 | VC4_REG32(DSI0_HS_DLT5), | |
618 | VC4_REG32(DSI0_HS_DLT6), | |
619 | VC4_REG32(DSI0_HS_DLT7), | |
620 | VC4_REG32(DSI0_PHY_AFEC0), | |
621 | VC4_REG32(DSI0_PHY_AFEC1), | |
622 | VC4_REG32(DSI0_ID), | |
4078f575 EA |
623 | }; |
624 | ||
3051719a EA |
625 | static const struct debugfs_reg32 dsi1_regs[] = { |
626 | VC4_REG32(DSI1_CTRL), | |
627 | VC4_REG32(DSI1_STAT), | |
628 | VC4_REG32(DSI1_HSTX_TO_CNT), | |
629 | VC4_REG32(DSI1_LPRX_TO_CNT), | |
630 | VC4_REG32(DSI1_TA_TO_CNT), | |
631 | VC4_REG32(DSI1_PR_TO_CNT), | |
632 | VC4_REG32(DSI1_DISP0_CTRL), | |
633 | VC4_REG32(DSI1_DISP1_CTRL), | |
634 | VC4_REG32(DSI1_INT_STAT), | |
635 | VC4_REG32(DSI1_INT_EN), | |
636 | VC4_REG32(DSI1_PHYC), | |
637 | VC4_REG32(DSI1_HS_CLT0), | |
638 | VC4_REG32(DSI1_HS_CLT1), | |
639 | VC4_REG32(DSI1_HS_CLT2), | |
640 | VC4_REG32(DSI1_HS_DLT3), | |
641 | VC4_REG32(DSI1_HS_DLT4), | |
642 | VC4_REG32(DSI1_HS_DLT5), | |
643 | VC4_REG32(DSI1_HS_DLT6), | |
644 | VC4_REG32(DSI1_HS_DLT7), | |
645 | VC4_REG32(DSI1_PHY_AFEC0), | |
646 | VC4_REG32(DSI1_PHY_AFEC1), | |
647 | VC4_REG32(DSI1_ID), | |
4078f575 EA |
648 | }; |
649 | ||
4078f575 EA |
650 | static void vc4_dsi_encoder_destroy(struct drm_encoder *encoder) |
651 | { | |
652 | drm_encoder_cleanup(encoder); | |
653 | } | |
654 | ||
655 | static const struct drm_encoder_funcs vc4_dsi_encoder_funcs = { | |
656 | .destroy = vc4_dsi_encoder_destroy, | |
657 | }; | |
658 | ||
659 | static void vc4_dsi_latch_ulps(struct vc4_dsi *dsi, bool latch) | |
660 | { | |
661 | u32 afec0 = DSI_PORT_READ(PHY_AFEC0); | |
662 | ||
663 | if (latch) | |
664 | afec0 |= DSI_PORT_BIT(PHY_AFEC0_LATCH_ULPS); | |
665 | else | |
666 | afec0 &= ~DSI_PORT_BIT(PHY_AFEC0_LATCH_ULPS); | |
667 | ||
668 | DSI_PORT_WRITE(PHY_AFEC0, afec0); | |
669 | } | |
670 | ||
671 | /* Enters or exits Ultra Low Power State. */ | |
672 | static void vc4_dsi_ulps(struct vc4_dsi *dsi, bool ulps) | |
673 | { | |
ec878c07 EA |
674 | bool non_continuous = dsi->mode_flags & MIPI_DSI_CLOCK_NON_CONTINUOUS; |
675 | u32 phyc_ulps = ((non_continuous ? DSI_PORT_BIT(PHYC_CLANE_ULPS) : 0) | | |
4078f575 EA |
676 | DSI_PHYC_DLANE0_ULPS | |
677 | (dsi->lanes > 1 ? DSI_PHYC_DLANE1_ULPS : 0) | | |
678 | (dsi->lanes > 2 ? DSI_PHYC_DLANE2_ULPS : 0) | | |
679 | (dsi->lanes > 3 ? DSI_PHYC_DLANE3_ULPS : 0)); | |
ec878c07 | 680 | u32 stat_ulps = ((non_continuous ? DSI1_STAT_PHY_CLOCK_ULPS : 0) | |
4078f575 EA |
681 | DSI1_STAT_PHY_D0_ULPS | |
682 | (dsi->lanes > 1 ? DSI1_STAT_PHY_D1_ULPS : 0) | | |
683 | (dsi->lanes > 2 ? DSI1_STAT_PHY_D2_ULPS : 0) | | |
684 | (dsi->lanes > 3 ? DSI1_STAT_PHY_D3_ULPS : 0)); | |
ec878c07 | 685 | u32 stat_stop = ((non_continuous ? DSI1_STAT_PHY_CLOCK_STOP : 0) | |
4078f575 EA |
686 | DSI1_STAT_PHY_D0_STOP | |
687 | (dsi->lanes > 1 ? DSI1_STAT_PHY_D1_STOP : 0) | | |
688 | (dsi->lanes > 2 ? DSI1_STAT_PHY_D2_STOP : 0) | | |
689 | (dsi->lanes > 3 ? DSI1_STAT_PHY_D3_STOP : 0)); | |
690 | int ret; | |
1825067e EA |
691 | bool ulps_currently_enabled = (DSI_PORT_READ(PHY_AFEC0) & |
692 | DSI_PORT_BIT(PHY_AFEC0_LATCH_ULPS)); | |
693 | ||
694 | if (ulps == ulps_currently_enabled) | |
695 | return; | |
4078f575 EA |
696 | |
697 | DSI_PORT_WRITE(STAT, stat_ulps); | |
698 | DSI_PORT_WRITE(PHYC, DSI_PORT_READ(PHYC) | phyc_ulps); | |
699 | ret = wait_for((DSI_PORT_READ(STAT) & stat_ulps) == stat_ulps, 200); | |
700 | if (ret) { | |
701 | dev_warn(&dsi->pdev->dev, | |
702 | "Timeout waiting for DSI ULPS entry: STAT 0x%08x", | |
703 | DSI_PORT_READ(STAT)); | |
704 | DSI_PORT_WRITE(PHYC, DSI_PORT_READ(PHYC) & ~phyc_ulps); | |
705 | vc4_dsi_latch_ulps(dsi, false); | |
706 | return; | |
707 | } | |
708 | ||
709 | /* The DSI module can't be disabled while the module is | |
710 | * generating ULPS state. So, to be able to disable the | |
711 | * module, we have the AFE latch the ULPS state and continue | |
712 | * on to having the module enter STOP. | |
713 | */ | |
714 | vc4_dsi_latch_ulps(dsi, ulps); | |
715 | ||
716 | DSI_PORT_WRITE(STAT, stat_stop); | |
717 | DSI_PORT_WRITE(PHYC, DSI_PORT_READ(PHYC) & ~phyc_ulps); | |
718 | ret = wait_for((DSI_PORT_READ(STAT) & stat_stop) == stat_stop, 200); | |
719 | if (ret) { | |
720 | dev_warn(&dsi->pdev->dev, | |
721 | "Timeout waiting for DSI STOP entry: STAT 0x%08x", | |
722 | DSI_PORT_READ(STAT)); | |
723 | DSI_PORT_WRITE(PHYC, DSI_PORT_READ(PHYC) & ~phyc_ulps); | |
724 | return; | |
725 | } | |
726 | } | |
727 | ||
728 | static u32 | |
729 | dsi_hs_timing(u32 ui_ns, u32 ns, u32 ui) | |
730 | { | |
731 | /* The HS timings have to be rounded up to a multiple of 8 | |
732 | * because we're using the byte clock. | |
733 | */ | |
734 | return roundup(ui + DIV_ROUND_UP(ns, ui_ns), 8); | |
735 | } | |
736 | ||
737 | /* ESC always runs at 100Mhz. */ | |
738 | #define ESC_TIME_NS 10 | |
739 | ||
740 | static u32 | |
741 | dsi_esc_timing(u32 ns) | |
742 | { | |
743 | return DIV_ROUND_UP(ns, ESC_TIME_NS); | |
744 | } | |
745 | ||
746 | static void vc4_dsi_encoder_disable(struct drm_encoder *encoder) | |
747 | { | |
748 | struct vc4_dsi_encoder *vc4_encoder = to_vc4_dsi_encoder(encoder); | |
749 | struct vc4_dsi *dsi = vc4_encoder->dsi; | |
750 | struct device *dev = &dsi->pdev->dev; | |
751 | ||
491657a9 | 752 | drm_bridge_disable(dsi->bridge); |
4078f575 | 753 | vc4_dsi_ulps(dsi, true); |
491657a9 | 754 | drm_bridge_post_disable(dsi->bridge); |
4078f575 | 755 | |
4078f575 EA |
756 | clk_disable_unprepare(dsi->pll_phy_clock); |
757 | clk_disable_unprepare(dsi->escape_clock); | |
758 | clk_disable_unprepare(dsi->pixel_clock); | |
759 | ||
760 | pm_runtime_put(dev); | |
761 | } | |
762 | ||
86c1b9ef EA |
763 | /* Extends the mode's blank intervals to handle BCM2835's integer-only |
764 | * DSI PLL divider. | |
765 | * | |
766 | * On 2835, PLLD is set to 2Ghz, and may not be changed by the display | |
767 | * driver since most peripherals are hanging off of the PLLD_PER | |
768 | * divider. PLLD_DSI1, which drives our DSI bit clock (and therefore | |
769 | * the pixel clock), only has an integer divider off of DSI. | |
770 | * | |
771 | * To get our panel mode to refresh at the expected 60Hz, we need to | |
772 | * extend the horizontal blank time. This means we drive a | |
773 | * higher-than-expected clock rate to the panel, but that's what the | |
774 | * firmware does too. | |
775 | */ | |
776 | static bool vc4_dsi_encoder_mode_fixup(struct drm_encoder *encoder, | |
777 | const struct drm_display_mode *mode, | |
778 | struct drm_display_mode *adjusted_mode) | |
779 | { | |
780 | struct vc4_dsi_encoder *vc4_encoder = to_vc4_dsi_encoder(encoder); | |
781 | struct vc4_dsi *dsi = vc4_encoder->dsi; | |
782 | struct clk *phy_parent = clk_get_parent(dsi->pll_phy_clock); | |
783 | unsigned long parent_rate = clk_get_rate(phy_parent); | |
784 | unsigned long pixel_clock_hz = mode->clock * 1000; | |
785 | unsigned long pll_clock = pixel_clock_hz * dsi->divider; | |
786 | int divider; | |
787 | ||
788 | /* Find what divider gets us a faster clock than the requested | |
789 | * pixel clock. | |
790 | */ | |
791 | for (divider = 1; divider < 8; divider++) { | |
792 | if (parent_rate / divider < pll_clock) { | |
793 | divider--; | |
794 | break; | |
795 | } | |
796 | } | |
797 | ||
798 | /* Now that we've picked a PLL divider, calculate back to its | |
799 | * pixel clock. | |
800 | */ | |
801 | pll_clock = parent_rate / divider; | |
802 | pixel_clock_hz = pll_clock / dsi->divider; | |
803 | ||
d409eeaf | 804 | adjusted_mode->clock = pixel_clock_hz / 1000; |
86c1b9ef EA |
805 | |
806 | /* Given the new pixel clock, adjust HFP to keep vrefresh the same. */ | |
af2eca53 EA |
807 | adjusted_mode->htotal = adjusted_mode->clock * mode->htotal / |
808 | mode->clock; | |
86c1b9ef EA |
809 | adjusted_mode->hsync_end += adjusted_mode->htotal - mode->htotal; |
810 | adjusted_mode->hsync_start += adjusted_mode->htotal - mode->htotal; | |
811 | ||
812 | return true; | |
813 | } | |
814 | ||
4078f575 EA |
815 | static void vc4_dsi_encoder_enable(struct drm_encoder *encoder) |
816 | { | |
86c1b9ef | 817 | struct drm_display_mode *mode = &encoder->crtc->state->adjusted_mode; |
4078f575 EA |
818 | struct vc4_dsi_encoder *vc4_encoder = to_vc4_dsi_encoder(encoder); |
819 | struct vc4_dsi *dsi = vc4_encoder->dsi; | |
820 | struct device *dev = &dsi->pdev->dev; | |
4078f575 EA |
821 | bool debug_dump_regs = false; |
822 | unsigned long hs_clock; | |
823 | u32 ui_ns; | |
824 | /* Minimum LP state duration in escape clock cycles. */ | |
825 | u32 lpx = dsi_esc_timing(60); | |
826 | unsigned long pixel_clock_hz = mode->clock * 1000; | |
827 | unsigned long dsip_clock; | |
828 | unsigned long phy_clock; | |
829 | int ret; | |
830 | ||
831 | ret = pm_runtime_get_sync(dev); | |
832 | if (ret) { | |
833 | DRM_ERROR("Failed to runtime PM enable on DSI%d\n", dsi->port); | |
834 | return; | |
835 | } | |
836 | ||
4078f575 | 837 | if (debug_dump_regs) { |
3051719a EA |
838 | struct drm_printer p = drm_info_printer(&dsi->pdev->dev); |
839 | dev_info(&dsi->pdev->dev, "DSI regs before:\n"); | |
840 | drm_print_regset32(&p, &dsi->regset); | |
4078f575 EA |
841 | } |
842 | ||
d409eeaf EA |
843 | /* Round up the clk_set_rate() request slightly, since |
844 | * PLLD_DSI1 is an integer divider and its rate selection will | |
845 | * never round up. | |
846 | */ | |
847 | phy_clock = (pixel_clock_hz + 1000) * dsi->divider; | |
4078f575 EA |
848 | ret = clk_set_rate(dsi->pll_phy_clock, phy_clock); |
849 | if (ret) { | |
850 | dev_err(&dsi->pdev->dev, | |
851 | "Failed to set phy clock to %ld: %d\n", phy_clock, ret); | |
852 | } | |
853 | ||
854 | /* Reset the DSI and all its fifos. */ | |
855 | DSI_PORT_WRITE(CTRL, | |
856 | DSI_CTRL_SOFT_RESET_CFG | | |
857 | DSI_PORT_BIT(CTRL_RESET_FIFOS)); | |
858 | ||
859 | DSI_PORT_WRITE(CTRL, | |
860 | DSI_CTRL_HSDT_EOT_DISABLE | | |
861 | DSI_CTRL_RX_LPDT_EOT_DISABLE); | |
862 | ||
863 | /* Clear all stat bits so we see what has happened during enable. */ | |
864 | DSI_PORT_WRITE(STAT, DSI_PORT_READ(STAT)); | |
865 | ||
866 | /* Set AFE CTR00/CTR1 to release powerdown of analog. */ | |
867 | if (dsi->port == 0) { | |
868 | u32 afec0 = (VC4_SET_FIELD(7, DSI_PHY_AFEC0_PTATADJ) | | |
869 | VC4_SET_FIELD(7, DSI_PHY_AFEC0_CTATADJ)); | |
870 | ||
871 | if (dsi->lanes < 2) | |
872 | afec0 |= DSI0_PHY_AFEC0_PD_DLANE1; | |
873 | ||
874 | if (!(dsi->mode_flags & MIPI_DSI_MODE_VIDEO)) | |
875 | afec0 |= DSI0_PHY_AFEC0_RESET; | |
876 | ||
877 | DSI_PORT_WRITE(PHY_AFEC0, afec0); | |
878 | ||
879 | DSI_PORT_WRITE(PHY_AFEC1, | |
880 | VC4_SET_FIELD(6, DSI0_PHY_AFEC1_IDR_DLANE1) | | |
881 | VC4_SET_FIELD(6, DSI0_PHY_AFEC1_IDR_DLANE0) | | |
882 | VC4_SET_FIELD(6, DSI0_PHY_AFEC1_IDR_CLANE)); | |
883 | } else { | |
884 | u32 afec0 = (VC4_SET_FIELD(7, DSI_PHY_AFEC0_PTATADJ) | | |
885 | VC4_SET_FIELD(7, DSI_PHY_AFEC0_CTATADJ) | | |
886 | VC4_SET_FIELD(6, DSI1_PHY_AFEC0_IDR_CLANE) | | |
887 | VC4_SET_FIELD(6, DSI1_PHY_AFEC0_IDR_DLANE0) | | |
888 | VC4_SET_FIELD(6, DSI1_PHY_AFEC0_IDR_DLANE1) | | |
889 | VC4_SET_FIELD(6, DSI1_PHY_AFEC0_IDR_DLANE2) | | |
890 | VC4_SET_FIELD(6, DSI1_PHY_AFEC0_IDR_DLANE3)); | |
891 | ||
892 | if (dsi->lanes < 4) | |
893 | afec0 |= DSI1_PHY_AFEC0_PD_DLANE3; | |
894 | if (dsi->lanes < 3) | |
895 | afec0 |= DSI1_PHY_AFEC0_PD_DLANE2; | |
896 | if (dsi->lanes < 2) | |
897 | afec0 |= DSI1_PHY_AFEC0_PD_DLANE1; | |
898 | ||
899 | afec0 |= DSI1_PHY_AFEC0_RESET; | |
900 | ||
901 | DSI_PORT_WRITE(PHY_AFEC0, afec0); | |
902 | ||
903 | DSI_PORT_WRITE(PHY_AFEC1, 0); | |
904 | ||
905 | /* AFEC reset hold time */ | |
906 | mdelay(1); | |
907 | } | |
908 | ||
909 | ret = clk_prepare_enable(dsi->escape_clock); | |
910 | if (ret) { | |
911 | DRM_ERROR("Failed to turn on DSI escape clock: %d\n", ret); | |
912 | return; | |
913 | } | |
914 | ||
915 | ret = clk_prepare_enable(dsi->pll_phy_clock); | |
916 | if (ret) { | |
917 | DRM_ERROR("Failed to turn on DSI PLL: %d\n", ret); | |
918 | return; | |
919 | } | |
920 | ||
921 | hs_clock = clk_get_rate(dsi->pll_phy_clock); | |
922 | ||
923 | /* Yes, we set the DSI0P/DSI1P pixel clock to the byte rate, | |
924 | * not the pixel clock rate. DSIxP take from the APHY's byte, | |
925 | * DDR2, or DDR4 clock (we use byte) and feed into the PV at | |
926 | * that rate. Separately, a value derived from PIX_CLK_DIV | |
927 | * and HS_CLKC is fed into the PV to divide down to the actual | |
928 | * pixel clock for pushing pixels into DSI. | |
929 | */ | |
930 | dsip_clock = phy_clock / 8; | |
931 | ret = clk_set_rate(dsi->pixel_clock, dsip_clock); | |
932 | if (ret) { | |
933 | dev_err(dev, "Failed to set pixel clock to %ldHz: %d\n", | |
934 | dsip_clock, ret); | |
935 | } | |
936 | ||
937 | ret = clk_prepare_enable(dsi->pixel_clock); | |
938 | if (ret) { | |
939 | DRM_ERROR("Failed to turn on DSI pixel clock: %d\n", ret); | |
940 | return; | |
941 | } | |
942 | ||
943 | /* How many ns one DSI unit interval is. Note that the clock | |
944 | * is DDR, so there's an extra divide by 2. | |
945 | */ | |
946 | ui_ns = DIV_ROUND_UP(500000000, hs_clock); | |
947 | ||
948 | DSI_PORT_WRITE(HS_CLT0, | |
949 | VC4_SET_FIELD(dsi_hs_timing(ui_ns, 262, 0), | |
950 | DSI_HS_CLT0_CZERO) | | |
951 | VC4_SET_FIELD(dsi_hs_timing(ui_ns, 0, 8), | |
952 | DSI_HS_CLT0_CPRE) | | |
953 | VC4_SET_FIELD(dsi_hs_timing(ui_ns, 38, 0), | |
954 | DSI_HS_CLT0_CPREP)); | |
955 | ||
956 | DSI_PORT_WRITE(HS_CLT1, | |
957 | VC4_SET_FIELD(dsi_hs_timing(ui_ns, 60, 0), | |
958 | DSI_HS_CLT1_CTRAIL) | | |
959 | VC4_SET_FIELD(dsi_hs_timing(ui_ns, 60, 52), | |
960 | DSI_HS_CLT1_CPOST)); | |
961 | ||
962 | DSI_PORT_WRITE(HS_CLT2, | |
963 | VC4_SET_FIELD(dsi_hs_timing(ui_ns, 1000000, 0), | |
964 | DSI_HS_CLT2_WUP)); | |
965 | ||
966 | DSI_PORT_WRITE(HS_DLT3, | |
967 | VC4_SET_FIELD(dsi_hs_timing(ui_ns, 100, 0), | |
968 | DSI_HS_DLT3_EXIT) | | |
969 | VC4_SET_FIELD(dsi_hs_timing(ui_ns, 105, 6), | |
970 | DSI_HS_DLT3_ZERO) | | |
971 | VC4_SET_FIELD(dsi_hs_timing(ui_ns, 40, 4), | |
972 | DSI_HS_DLT3_PRE)); | |
973 | ||
974 | DSI_PORT_WRITE(HS_DLT4, | |
975 | VC4_SET_FIELD(dsi_hs_timing(ui_ns, lpx * ESC_TIME_NS, 0), | |
976 | DSI_HS_DLT4_LPX) | | |
977 | VC4_SET_FIELD(max(dsi_hs_timing(ui_ns, 0, 8), | |
978 | dsi_hs_timing(ui_ns, 60, 4)), | |
979 | DSI_HS_DLT4_TRAIL) | | |
980 | VC4_SET_FIELD(0, DSI_HS_DLT4_ANLAT)); | |
981 | ||
e65d5112 EA |
982 | /* T_INIT is how long STOP is driven after power-up to |
983 | * indicate to the slave (also coming out of power-up) that | |
984 | * master init is complete, and should be greater than the | |
985 | * maximum of two value: T_INIT,MASTER and T_INIT,SLAVE. The | |
986 | * D-PHY spec gives a minimum 100us for T_INIT,MASTER and | |
987 | * T_INIT,SLAVE, while allowing protocols on top of it to give | |
988 | * greater minimums. The vc4 firmware uses an extremely | |
989 | * conservative 5ms, and we maintain that here. | |
990 | */ | |
991 | DSI_PORT_WRITE(HS_DLT5, VC4_SET_FIELD(dsi_hs_timing(ui_ns, | |
992 | 5 * 1000 * 1000, 0), | |
4078f575 EA |
993 | DSI_HS_DLT5_INIT)); |
994 | ||
995 | DSI_PORT_WRITE(HS_DLT6, | |
996 | VC4_SET_FIELD(lpx * 5, DSI_HS_DLT6_TA_GET) | | |
997 | VC4_SET_FIELD(lpx, DSI_HS_DLT6_TA_SURE) | | |
998 | VC4_SET_FIELD(lpx * 4, DSI_HS_DLT6_TA_GO) | | |
999 | VC4_SET_FIELD(lpx, DSI_HS_DLT6_LP_LPX)); | |
1000 | ||
1001 | DSI_PORT_WRITE(HS_DLT7, | |
1002 | VC4_SET_FIELD(dsi_esc_timing(1000000), | |
1003 | DSI_HS_DLT7_LP_WUP)); | |
1004 | ||
1005 | DSI_PORT_WRITE(PHYC, | |
1006 | DSI_PHYC_DLANE0_ENABLE | | |
1007 | (dsi->lanes >= 2 ? DSI_PHYC_DLANE1_ENABLE : 0) | | |
1008 | (dsi->lanes >= 3 ? DSI_PHYC_DLANE2_ENABLE : 0) | | |
1009 | (dsi->lanes >= 4 ? DSI_PHYC_DLANE3_ENABLE : 0) | | |
1010 | DSI_PORT_BIT(PHYC_CLANE_ENABLE) | | |
1011 | ((dsi->mode_flags & MIPI_DSI_CLOCK_NON_CONTINUOUS) ? | |
1012 | 0 : DSI_PORT_BIT(PHYC_HS_CLK_CONTINUOUS)) | | |
1013 | (dsi->port == 0 ? | |
1014 | VC4_SET_FIELD(lpx - 1, DSI0_PHYC_ESC_CLK_LPDT) : | |
1015 | VC4_SET_FIELD(lpx - 1, DSI1_PHYC_ESC_CLK_LPDT))); | |
1016 | ||
1017 | DSI_PORT_WRITE(CTRL, | |
1018 | DSI_PORT_READ(CTRL) | | |
1019 | DSI_CTRL_CAL_BYTE); | |
1020 | ||
1021 | /* HS timeout in HS clock cycles: disabled. */ | |
1022 | DSI_PORT_WRITE(HSTX_TO_CNT, 0); | |
1023 | /* LP receive timeout in HS clocks. */ | |
1024 | DSI_PORT_WRITE(LPRX_TO_CNT, 0xffffff); | |
1025 | /* Bus turnaround timeout */ | |
1026 | DSI_PORT_WRITE(TA_TO_CNT, 100000); | |
1027 | /* Display reset sequence timeout */ | |
1028 | DSI_PORT_WRITE(PR_TO_CNT, 100000); | |
1029 | ||
4078f575 EA |
1030 | /* Set up DISP1 for transferring long command payloads through |
1031 | * the pixfifo. | |
1032 | */ | |
1033 | DSI_PORT_WRITE(DISP1_CTRL, | |
1034 | VC4_SET_FIELD(DSI_DISP1_PFORMAT_32BIT_LE, | |
1035 | DSI_DISP1_PFORMAT) | | |
1036 | DSI_DISP1_ENABLE); | |
1037 | ||
1038 | /* Ungate the block. */ | |
1039 | if (dsi->port == 0) | |
1040 | DSI_PORT_WRITE(CTRL, DSI_PORT_READ(CTRL) | DSI0_CTRL_CTRL0); | |
1041 | else | |
1042 | DSI_PORT_WRITE(CTRL, DSI_PORT_READ(CTRL) | DSI1_CTRL_EN); | |
1043 | ||
1044 | /* Bring AFE out of reset. */ | |
1045 | if (dsi->port == 0) { | |
1046 | } else { | |
1047 | DSI_PORT_WRITE(PHY_AFEC0, | |
1048 | DSI_PORT_READ(PHY_AFEC0) & | |
1049 | ~DSI1_PHY_AFEC0_RESET); | |
1050 | } | |
1051 | ||
1052 | vc4_dsi_ulps(dsi, false); | |
1053 | ||
491657a9 EA |
1054 | drm_bridge_pre_enable(dsi->bridge); |
1055 | ||
1056 | if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO) { | |
1057 | DSI_PORT_WRITE(DISP0_CTRL, | |
1058 | VC4_SET_FIELD(dsi->divider, | |
1059 | DSI_DISP0_PIX_CLK_DIV) | | |
1060 | VC4_SET_FIELD(dsi->format, DSI_DISP0_PFORMAT) | | |
1061 | VC4_SET_FIELD(DSI_DISP0_LP_STOP_PERFRAME, | |
1062 | DSI_DISP0_LP_STOP_CTRL) | | |
1063 | DSI_DISP0_ST_END | | |
1064 | DSI_DISP0_ENABLE); | |
1065 | } else { | |
1066 | DSI_PORT_WRITE(DISP0_CTRL, | |
1067 | DSI_DISP0_COMMAND_MODE | | |
1068 | DSI_DISP0_ENABLE); | |
1069 | } | |
1070 | ||
1071 | drm_bridge_enable(dsi->bridge); | |
1072 | ||
4078f575 | 1073 | if (debug_dump_regs) { |
3051719a EA |
1074 | struct drm_printer p = drm_info_printer(&dsi->pdev->dev); |
1075 | dev_info(&dsi->pdev->dev, "DSI regs after:\n"); | |
1076 | drm_print_regset32(&p, &dsi->regset); | |
4078f575 | 1077 | } |
4078f575 EA |
1078 | } |
1079 | ||
1080 | static ssize_t vc4_dsi_host_transfer(struct mipi_dsi_host *host, | |
1081 | const struct mipi_dsi_msg *msg) | |
1082 | { | |
1083 | struct vc4_dsi *dsi = host_to_dsi(host); | |
1084 | struct mipi_dsi_packet packet; | |
1085 | u32 pkth = 0, pktc = 0; | |
1086 | int i, ret; | |
1087 | bool is_long = mipi_dsi_packet_format_is_long(msg->type); | |
1088 | u32 cmd_fifo_len = 0, pix_fifo_len = 0; | |
1089 | ||
1090 | mipi_dsi_create_packet(&packet, msg); | |
1091 | ||
1092 | pkth |= VC4_SET_FIELD(packet.header[0], DSI_TXPKT1H_BC_DT); | |
1093 | pkth |= VC4_SET_FIELD(packet.header[1] | | |
1094 | (packet.header[2] << 8), | |
1095 | DSI_TXPKT1H_BC_PARAM); | |
1096 | if (is_long) { | |
1097 | /* Divide data across the various FIFOs we have available. | |
1098 | * The command FIFO takes byte-oriented data, but is of | |
1099 | * limited size. The pixel FIFO (never actually used for | |
1100 | * pixel data in reality) is word oriented, and substantially | |
1101 | * larger. So, we use the pixel FIFO for most of the data, | |
1102 | * sending the residual bytes in the command FIFO at the start. | |
1103 | * | |
1104 | * With this arrangement, the command FIFO will never get full. | |
1105 | */ | |
1106 | if (packet.payload_length <= 16) { | |
1107 | cmd_fifo_len = packet.payload_length; | |
1108 | pix_fifo_len = 0; | |
1109 | } else { | |
1110 | cmd_fifo_len = (packet.payload_length % | |
1111 | DSI_PIX_FIFO_WIDTH); | |
1112 | pix_fifo_len = ((packet.payload_length - cmd_fifo_len) / | |
1113 | DSI_PIX_FIFO_WIDTH); | |
1114 | } | |
1115 | ||
1116 | WARN_ON_ONCE(pix_fifo_len >= DSI_PIX_FIFO_DEPTH); | |
1117 | ||
1118 | pkth |= VC4_SET_FIELD(cmd_fifo_len, DSI_TXPKT1H_BC_CMDFIFO); | |
1119 | } | |
1120 | ||
1121 | if (msg->rx_len) { | |
1122 | pktc |= VC4_SET_FIELD(DSI_TXPKT1C_CMD_CTRL_RX, | |
1123 | DSI_TXPKT1C_CMD_CTRL); | |
1124 | } else { | |
1125 | pktc |= VC4_SET_FIELD(DSI_TXPKT1C_CMD_CTRL_TX, | |
1126 | DSI_TXPKT1C_CMD_CTRL); | |
1127 | } | |
1128 | ||
1129 | for (i = 0; i < cmd_fifo_len; i++) | |
1130 | DSI_PORT_WRITE(TXPKT_CMD_FIFO, packet.payload[i]); | |
1131 | for (i = 0; i < pix_fifo_len; i++) { | |
1132 | const u8 *pix = packet.payload + cmd_fifo_len + i * 4; | |
1133 | ||
1134 | DSI_PORT_WRITE(TXPKT_PIX_FIFO, | |
1135 | pix[0] | | |
1136 | pix[1] << 8 | | |
1137 | pix[2] << 16 | | |
1138 | pix[3] << 24); | |
1139 | } | |
1140 | ||
1141 | if (msg->flags & MIPI_DSI_MSG_USE_LPM) | |
1142 | pktc |= DSI_TXPKT1C_CMD_MODE_LP; | |
1143 | if (is_long) | |
1144 | pktc |= DSI_TXPKT1C_CMD_TYPE_LONG; | |
1145 | ||
1146 | /* Send one copy of the packet. Larger repeats are used for pixel | |
1147 | * data in command mode. | |
1148 | */ | |
1149 | pktc |= VC4_SET_FIELD(1, DSI_TXPKT1C_CMD_REPEAT); | |
1150 | ||
1151 | pktc |= DSI_TXPKT1C_CMD_EN; | |
1152 | if (pix_fifo_len) { | |
1153 | pktc |= VC4_SET_FIELD(DSI_TXPKT1C_DISPLAY_NO_SECONDARY, | |
1154 | DSI_TXPKT1C_DISPLAY_NO); | |
1155 | } else { | |
1156 | pktc |= VC4_SET_FIELD(DSI_TXPKT1C_DISPLAY_NO_SHORT, | |
1157 | DSI_TXPKT1C_DISPLAY_NO); | |
1158 | } | |
1159 | ||
1160 | /* Enable the appropriate interrupt for the transfer completion. */ | |
1161 | dsi->xfer_result = 0; | |
1162 | reinit_completion(&dsi->xfer_completion); | |
1163 | DSI_PORT_WRITE(INT_STAT, DSI1_INT_TXPKT1_DONE | DSI1_INT_PHY_DIR_RTF); | |
1164 | if (msg->rx_len) { | |
1165 | DSI_PORT_WRITE(INT_EN, (DSI1_INTERRUPTS_ALWAYS_ENABLED | | |
1166 | DSI1_INT_PHY_DIR_RTF)); | |
1167 | } else { | |
1168 | DSI_PORT_WRITE(INT_EN, (DSI1_INTERRUPTS_ALWAYS_ENABLED | | |
1169 | DSI1_INT_TXPKT1_DONE)); | |
1170 | } | |
1171 | ||
1172 | /* Send the packet. */ | |
1173 | DSI_PORT_WRITE(TXPKT1H, pkth); | |
1174 | DSI_PORT_WRITE(TXPKT1C, pktc); | |
1175 | ||
1176 | if (!wait_for_completion_timeout(&dsi->xfer_completion, | |
1177 | msecs_to_jiffies(1000))) { | |
1178 | dev_err(&dsi->pdev->dev, "transfer interrupt wait timeout"); | |
1179 | dev_err(&dsi->pdev->dev, "instat: 0x%08x\n", | |
1180 | DSI_PORT_READ(INT_STAT)); | |
1181 | ret = -ETIMEDOUT; | |
1182 | } else { | |
1183 | ret = dsi->xfer_result; | |
1184 | } | |
1185 | ||
1186 | DSI_PORT_WRITE(INT_EN, DSI1_INTERRUPTS_ALWAYS_ENABLED); | |
1187 | ||
1188 | if (ret) | |
1189 | goto reset_fifo_and_return; | |
1190 | ||
1191 | if (ret == 0 && msg->rx_len) { | |
1192 | u32 rxpkt1h = DSI_PORT_READ(RXPKT1H); | |
1193 | u8 *msg_rx = msg->rx_buf; | |
1194 | ||
1195 | if (rxpkt1h & DSI_RXPKT1H_PKT_TYPE_LONG) { | |
1196 | u32 rxlen = VC4_GET_FIELD(rxpkt1h, | |
1197 | DSI_RXPKT1H_BC_PARAM); | |
1198 | ||
1199 | if (rxlen != msg->rx_len) { | |
1200 | DRM_ERROR("DSI returned %db, expecting %db\n", | |
1201 | rxlen, (int)msg->rx_len); | |
1202 | ret = -ENXIO; | |
1203 | goto reset_fifo_and_return; | |
1204 | } | |
1205 | ||
1206 | for (i = 0; i < msg->rx_len; i++) | |
1207 | msg_rx[i] = DSI_READ(DSI1_RXPKT_FIFO); | |
1208 | } else { | |
1209 | /* FINISHME: Handle AWER */ | |
1210 | ||
1211 | msg_rx[0] = VC4_GET_FIELD(rxpkt1h, | |
1212 | DSI_RXPKT1H_SHORT_0); | |
1213 | if (msg->rx_len > 1) { | |
1214 | msg_rx[1] = VC4_GET_FIELD(rxpkt1h, | |
1215 | DSI_RXPKT1H_SHORT_1); | |
1216 | } | |
1217 | } | |
1218 | } | |
1219 | ||
1220 | return ret; | |
1221 | ||
1222 | reset_fifo_and_return: | |
1223 | DRM_ERROR("DSI transfer failed, resetting: %d\n", ret); | |
1224 | ||
1225 | DSI_PORT_WRITE(TXPKT1C, DSI_PORT_READ(TXPKT1C) & ~DSI_TXPKT1C_CMD_EN); | |
1226 | udelay(1); | |
1227 | DSI_PORT_WRITE(CTRL, | |
1228 | DSI_PORT_READ(CTRL) | | |
1229 | DSI_PORT_BIT(CTRL_RESET_FIFOS)); | |
1230 | ||
1231 | DSI_PORT_WRITE(TXPKT1C, 0); | |
1232 | DSI_PORT_WRITE(INT_EN, DSI1_INTERRUPTS_ALWAYS_ENABLED); | |
1233 | return ret; | |
1234 | } | |
1235 | ||
1236 | static int vc4_dsi_host_attach(struct mipi_dsi_host *host, | |
1237 | struct mipi_dsi_device *device) | |
1238 | { | |
1239 | struct vc4_dsi *dsi = host_to_dsi(host); | |
4078f575 EA |
1240 | |
1241 | dsi->lanes = device->lanes; | |
1242 | dsi->channel = device->channel; | |
4078f575 EA |
1243 | dsi->mode_flags = device->mode_flags; |
1244 | ||
86c1b9ef EA |
1245 | switch (device->format) { |
1246 | case MIPI_DSI_FMT_RGB888: | |
1247 | dsi->format = DSI_PFORMAT_RGB888; | |
1248 | dsi->divider = 24 / dsi->lanes; | |
1249 | break; | |
1250 | case MIPI_DSI_FMT_RGB666: | |
1251 | dsi->format = DSI_PFORMAT_RGB666; | |
1252 | dsi->divider = 24 / dsi->lanes; | |
1253 | break; | |
1254 | case MIPI_DSI_FMT_RGB666_PACKED: | |
1255 | dsi->format = DSI_PFORMAT_RGB666_PACKED; | |
1256 | dsi->divider = 18 / dsi->lanes; | |
1257 | break; | |
1258 | case MIPI_DSI_FMT_RGB565: | |
1259 | dsi->format = DSI_PFORMAT_RGB565; | |
1260 | dsi->divider = 16 / dsi->lanes; | |
1261 | break; | |
1262 | default: | |
1263 | dev_err(&dsi->pdev->dev, "Unknown DSI format: %d.\n", | |
1264 | dsi->format); | |
1265 | return 0; | |
1266 | } | |
1267 | ||
4078f575 EA |
1268 | if (!(dsi->mode_flags & MIPI_DSI_MODE_VIDEO)) { |
1269 | dev_err(&dsi->pdev->dev, | |
1270 | "Only VIDEO mode panels supported currently.\n"); | |
1271 | return 0; | |
1272 | } | |
1273 | ||
32ad958d | 1274 | return 0; |
4078f575 EA |
1275 | } |
1276 | ||
1277 | static int vc4_dsi_host_detach(struct mipi_dsi_host *host, | |
1278 | struct mipi_dsi_device *device) | |
1279 | { | |
4078f575 EA |
1280 | return 0; |
1281 | } | |
1282 | ||
1283 | static const struct mipi_dsi_host_ops vc4_dsi_host_ops = { | |
1284 | .attach = vc4_dsi_host_attach, | |
1285 | .detach = vc4_dsi_host_detach, | |
1286 | .transfer = vc4_dsi_host_transfer, | |
1287 | }; | |
1288 | ||
1289 | static const struct drm_encoder_helper_funcs vc4_dsi_encoder_helper_funcs = { | |
1290 | .disable = vc4_dsi_encoder_disable, | |
1291 | .enable = vc4_dsi_encoder_enable, | |
86c1b9ef | 1292 | .mode_fixup = vc4_dsi_encoder_mode_fixup, |
4078f575 EA |
1293 | }; |
1294 | ||
1295 | static const struct of_device_id vc4_dsi_dt_match[] = { | |
1296 | { .compatible = "brcm,bcm2835-dsi1", (void *)(uintptr_t)1 }, | |
1297 | {} | |
1298 | }; | |
1299 | ||
1300 | static void dsi_handle_error(struct vc4_dsi *dsi, | |
1301 | irqreturn_t *ret, u32 stat, u32 bit, | |
1302 | const char *type) | |
1303 | { | |
1304 | if (!(stat & bit)) | |
1305 | return; | |
1306 | ||
1307 | DRM_ERROR("DSI%d: %s error\n", dsi->port, type); | |
1308 | *ret = IRQ_HANDLED; | |
1309 | } | |
1310 | ||
af0c8c10 EA |
1311 | /* |
1312 | * Initial handler for port 1 where we need the reg_dma workaround. | |
1313 | * The register DMA writes sleep, so we can't do it in the top half. | |
1314 | * Instead we use IRQF_ONESHOT so that the IRQ gets disabled in the | |
1315 | * parent interrupt contrller until our interrupt thread is done. | |
1316 | */ | |
1317 | static irqreturn_t vc4_dsi_irq_defer_to_thread_handler(int irq, void *data) | |
1318 | { | |
1319 | struct vc4_dsi *dsi = data; | |
1320 | u32 stat = DSI_PORT_READ(INT_STAT); | |
1321 | ||
1322 | if (!stat) | |
1323 | return IRQ_NONE; | |
1324 | ||
1325 | return IRQ_WAKE_THREAD; | |
1326 | } | |
1327 | ||
1328 | /* | |
1329 | * Normal IRQ handler for port 0, or the threaded IRQ handler for port | |
1330 | * 1 where we need the reg_dma workaround. | |
1331 | */ | |
4078f575 EA |
1332 | static irqreturn_t vc4_dsi_irq_handler(int irq, void *data) |
1333 | { | |
1334 | struct vc4_dsi *dsi = data; | |
1335 | u32 stat = DSI_PORT_READ(INT_STAT); | |
1336 | irqreturn_t ret = IRQ_NONE; | |
1337 | ||
1338 | DSI_PORT_WRITE(INT_STAT, stat); | |
1339 | ||
1340 | dsi_handle_error(dsi, &ret, stat, | |
1341 | DSI1_INT_ERR_SYNC_ESC, "LPDT sync"); | |
1342 | dsi_handle_error(dsi, &ret, stat, | |
1343 | DSI1_INT_ERR_CONTROL, "data lane 0 sequence"); | |
1344 | dsi_handle_error(dsi, &ret, stat, | |
1345 | DSI1_INT_ERR_CONT_LP0, "LP0 contention"); | |
1346 | dsi_handle_error(dsi, &ret, stat, | |
1347 | DSI1_INT_ERR_CONT_LP1, "LP1 contention"); | |
1348 | dsi_handle_error(dsi, &ret, stat, | |
1349 | DSI1_INT_HSTX_TO, "HSTX timeout"); | |
1350 | dsi_handle_error(dsi, &ret, stat, | |
1351 | DSI1_INT_LPRX_TO, "LPRX timeout"); | |
1352 | dsi_handle_error(dsi, &ret, stat, | |
1353 | DSI1_INT_TA_TO, "turnaround timeout"); | |
1354 | dsi_handle_error(dsi, &ret, stat, | |
1355 | DSI1_INT_PR_TO, "peripheral reset timeout"); | |
1356 | ||
1357 | if (stat & (DSI1_INT_TXPKT1_DONE | DSI1_INT_PHY_DIR_RTF)) { | |
1358 | complete(&dsi->xfer_completion); | |
1359 | ret = IRQ_HANDLED; | |
1360 | } else if (stat & DSI1_INT_HSTX_TO) { | |
1361 | complete(&dsi->xfer_completion); | |
1362 | dsi->xfer_result = -ETIMEDOUT; | |
1363 | ret = IRQ_HANDLED; | |
1364 | } | |
1365 | ||
1366 | return ret; | |
1367 | } | |
1368 | ||
1369 | /** | |
72f793f1 EA |
1370 | * vc4_dsi_init_phy_clocks - Exposes clocks generated by the analog |
1371 | * PHY that are consumed by CPRMAN (clk-bcm2835.c). | |
1372 | * @dsi: DSI encoder | |
4078f575 EA |
1373 | */ |
1374 | static int | |
1375 | vc4_dsi_init_phy_clocks(struct vc4_dsi *dsi) | |
1376 | { | |
1377 | struct device *dev = &dsi->pdev->dev; | |
1378 | const char *parent_name = __clk_get_name(dsi->pll_phy_clock); | |
1379 | static const struct { | |
1380 | const char *dsi0_name, *dsi1_name; | |
1381 | int div; | |
1382 | } phy_clocks[] = { | |
1383 | { "dsi0_byte", "dsi1_byte", 8 }, | |
1384 | { "dsi0_ddr2", "dsi1_ddr2", 4 }, | |
1385 | { "dsi0_ddr", "dsi1_ddr", 2 }, | |
1386 | }; | |
1387 | int i; | |
1388 | ||
1389 | dsi->clk_onecell = devm_kzalloc(dev, | |
1390 | sizeof(*dsi->clk_onecell) + | |
1391 | ARRAY_SIZE(phy_clocks) * | |
1392 | sizeof(struct clk_hw *), | |
1393 | GFP_KERNEL); | |
1394 | if (!dsi->clk_onecell) | |
1395 | return -ENOMEM; | |
1396 | dsi->clk_onecell->num = ARRAY_SIZE(phy_clocks); | |
1397 | ||
1398 | for (i = 0; i < ARRAY_SIZE(phy_clocks); i++) { | |
1399 | struct clk_fixed_factor *fix = &dsi->phy_clocks[i]; | |
1400 | struct clk_init_data init; | |
1401 | int ret; | |
1402 | ||
1403 | /* We just use core fixed factor clock ops for the PHY | |
1404 | * clocks. The clocks are actually gated by the | |
1405 | * PHY_AFEC0_DDRCLK_EN bits, which we should be | |
1406 | * setting if we use the DDR/DDR2 clocks. However, | |
1407 | * vc4_dsi_encoder_enable() is setting up both AFEC0, | |
1408 | * setting both our parent DSI PLL's rate and this | |
1409 | * clock's rate, so it knows if DDR/DDR2 are going to | |
1410 | * be used and could enable the gates itself. | |
1411 | */ | |
1412 | fix->mult = 1; | |
1413 | fix->div = phy_clocks[i].div; | |
1414 | fix->hw.init = &init; | |
1415 | ||
1416 | memset(&init, 0, sizeof(init)); | |
1417 | init.parent_names = &parent_name; | |
1418 | init.num_parents = 1; | |
1419 | if (dsi->port == 1) | |
1420 | init.name = phy_clocks[i].dsi1_name; | |
1421 | else | |
1422 | init.name = phy_clocks[i].dsi0_name; | |
1423 | init.ops = &clk_fixed_factor_ops; | |
1424 | ||
1425 | ret = devm_clk_hw_register(dev, &fix->hw); | |
1426 | if (ret) | |
1427 | return ret; | |
1428 | ||
1429 | dsi->clk_onecell->hws[i] = &fix->hw; | |
1430 | } | |
1431 | ||
1432 | return of_clk_add_hw_provider(dev->of_node, | |
1433 | of_clk_hw_onecell_get, | |
1434 | dsi->clk_onecell); | |
1435 | } | |
1436 | ||
1437 | static int vc4_dsi_bind(struct device *dev, struct device *master, void *data) | |
1438 | { | |
1439 | struct platform_device *pdev = to_platform_device(dev); | |
1440 | struct drm_device *drm = dev_get_drvdata(master); | |
1441 | struct vc4_dev *vc4 = to_vc4_dev(drm); | |
32ad958d | 1442 | struct vc4_dsi *dsi = dev_get_drvdata(dev); |
4078f575 | 1443 | struct vc4_dsi_encoder *vc4_dsi_encoder; |
32ad958d | 1444 | struct drm_panel *panel; |
4078f575 EA |
1445 | const struct of_device_id *match; |
1446 | dma_cap_mask_t dma_mask; | |
1447 | int ret; | |
1448 | ||
4078f575 EA |
1449 | match = of_match_device(vc4_dsi_dt_match, dev); |
1450 | if (!match) | |
1451 | return -ENODEV; | |
1452 | ||
1453 | dsi->port = (uintptr_t)match->data; | |
1454 | ||
1455 | vc4_dsi_encoder = devm_kzalloc(dev, sizeof(*vc4_dsi_encoder), | |
1456 | GFP_KERNEL); | |
1457 | if (!vc4_dsi_encoder) | |
1458 | return -ENOMEM; | |
1459 | vc4_dsi_encoder->base.type = VC4_ENCODER_TYPE_DSI1; | |
1460 | vc4_dsi_encoder->dsi = dsi; | |
1461 | dsi->encoder = &vc4_dsi_encoder->base.base; | |
1462 | ||
4078f575 EA |
1463 | dsi->regs = vc4_ioremap_regs(pdev, 0); |
1464 | if (IS_ERR(dsi->regs)) | |
1465 | return PTR_ERR(dsi->regs); | |
1466 | ||
3051719a EA |
1467 | dsi->regset.base = dsi->regs; |
1468 | if (dsi->port == 0) { | |
1469 | dsi->regset.regs = dsi0_regs; | |
1470 | dsi->regset.nregs = ARRAY_SIZE(dsi0_regs); | |
1471 | } else { | |
1472 | dsi->regset.regs = dsi1_regs; | |
1473 | dsi->regset.nregs = ARRAY_SIZE(dsi1_regs); | |
1474 | } | |
1475 | ||
4078f575 EA |
1476 | if (DSI_PORT_READ(ID) != DSI_ID_VALUE) { |
1477 | dev_err(dev, "Port returned 0x%08x for ID instead of 0x%08x\n", | |
1478 | DSI_PORT_READ(ID), DSI_ID_VALUE); | |
1479 | return -ENODEV; | |
1480 | } | |
1481 | ||
1482 | /* DSI1 has a broken AXI slave that doesn't respond to writes | |
1483 | * from the ARM. It does handle writes from the DMA engine, | |
1484 | * so set up a channel for talking to it. | |
1485 | */ | |
1486 | if (dsi->port == 1) { | |
1487 | dsi->reg_dma_mem = dma_alloc_coherent(dev, 4, | |
1488 | &dsi->reg_dma_paddr, | |
1489 | GFP_KERNEL); | |
1490 | if (!dsi->reg_dma_mem) { | |
1491 | DRM_ERROR("Failed to get DMA memory\n"); | |
1492 | return -ENOMEM; | |
1493 | } | |
1494 | ||
1495 | dma_cap_zero(dma_mask); | |
1496 | dma_cap_set(DMA_MEMCPY, dma_mask); | |
1497 | dsi->reg_dma_chan = dma_request_chan_by_mask(&dma_mask); | |
1498 | if (IS_ERR(dsi->reg_dma_chan)) { | |
1499 | ret = PTR_ERR(dsi->reg_dma_chan); | |
1500 | if (ret != -EPROBE_DEFER) | |
1501 | DRM_ERROR("Failed to get DMA channel: %d\n", | |
1502 | ret); | |
1503 | return ret; | |
1504 | } | |
1505 | ||
1506 | /* Get the physical address of the device's registers. The | |
1507 | * struct resource for the regs gives us the bus address | |
1508 | * instead. | |
1509 | */ | |
1510 | dsi->reg_paddr = be32_to_cpup(of_get_address(dev->of_node, | |
1511 | 0, NULL, NULL)); | |
1512 | } | |
1513 | ||
1514 | init_completion(&dsi->xfer_completion); | |
1515 | /* At startup enable error-reporting interrupts and nothing else. */ | |
1516 | DSI_PORT_WRITE(INT_EN, DSI1_INTERRUPTS_ALWAYS_ENABLED); | |
1517 | /* Clear any existing interrupt state. */ | |
1518 | DSI_PORT_WRITE(INT_STAT, DSI_PORT_READ(INT_STAT)); | |
1519 | ||
af0c8c10 EA |
1520 | if (dsi->reg_dma_mem) |
1521 | ret = devm_request_threaded_irq(dev, platform_get_irq(pdev, 0), | |
1522 | vc4_dsi_irq_defer_to_thread_handler, | |
1523 | vc4_dsi_irq_handler, | |
1524 | IRQF_ONESHOT, | |
1525 | "vc4 dsi", dsi); | |
1526 | else | |
1527 | ret = devm_request_irq(dev, platform_get_irq(pdev, 0), | |
1528 | vc4_dsi_irq_handler, 0, "vc4 dsi", dsi); | |
4078f575 EA |
1529 | if (ret) { |
1530 | if (ret != -EPROBE_DEFER) | |
1531 | dev_err(dev, "Failed to get interrupt: %d\n", ret); | |
1532 | return ret; | |
1533 | } | |
1534 | ||
1535 | dsi->escape_clock = devm_clk_get(dev, "escape"); | |
1536 | if (IS_ERR(dsi->escape_clock)) { | |
1537 | ret = PTR_ERR(dsi->escape_clock); | |
1538 | if (ret != -EPROBE_DEFER) | |
1539 | dev_err(dev, "Failed to get escape clock: %d\n", ret); | |
1540 | return ret; | |
1541 | } | |
1542 | ||
1543 | dsi->pll_phy_clock = devm_clk_get(dev, "phy"); | |
1544 | if (IS_ERR(dsi->pll_phy_clock)) { | |
1545 | ret = PTR_ERR(dsi->pll_phy_clock); | |
1546 | if (ret != -EPROBE_DEFER) | |
1547 | dev_err(dev, "Failed to get phy clock: %d\n", ret); | |
1548 | return ret; | |
1549 | } | |
1550 | ||
1551 | dsi->pixel_clock = devm_clk_get(dev, "pixel"); | |
1552 | if (IS_ERR(dsi->pixel_clock)) { | |
1553 | ret = PTR_ERR(dsi->pixel_clock); | |
1554 | if (ret != -EPROBE_DEFER) | |
1555 | dev_err(dev, "Failed to get pixel clock: %d\n", ret); | |
1556 | return ret; | |
1557 | } | |
1558 | ||
32ad958d EA |
1559 | ret = drm_of_find_panel_or_bridge(dev->of_node, 0, 0, |
1560 | &panel, &dsi->bridge); | |
1b9883ea BB |
1561 | if (ret) { |
1562 | /* If the bridge or panel pointed by dev->of_node is not | |
1563 | * enabled, just return 0 here so that we don't prevent the DRM | |
1564 | * dev from being registered. Of course that means the DSI | |
1565 | * encoder won't be exposed, but that's not a problem since | |
1566 | * nothing is connected to it. | |
1567 | */ | |
1568 | if (ret == -ENODEV) | |
1569 | return 0; | |
1570 | ||
32ad958d | 1571 | return ret; |
1b9883ea | 1572 | } |
32ad958d EA |
1573 | |
1574 | if (panel) { | |
1575 | dsi->bridge = devm_drm_panel_bridge_add(dev, panel, | |
1576 | DRM_MODE_CONNECTOR_DSI); | |
1577 | if (IS_ERR(dsi->bridge)) | |
1578 | return PTR_ERR(dsi->bridge); | |
1579 | } | |
1580 | ||
4078f575 EA |
1581 | /* The esc clock rate is supposed to always be 100Mhz. */ |
1582 | ret = clk_set_rate(dsi->escape_clock, 100 * 1000000); | |
1583 | if (ret) { | |
1584 | dev_err(dev, "Failed to set esc clock: %d\n", ret); | |
1585 | return ret; | |
1586 | } | |
1587 | ||
1588 | ret = vc4_dsi_init_phy_clocks(dsi); | |
1589 | if (ret) | |
1590 | return ret; | |
1591 | ||
1592 | if (dsi->port == 1) | |
1593 | vc4->dsi1 = dsi; | |
1594 | ||
1595 | drm_encoder_init(drm, dsi->encoder, &vc4_dsi_encoder_funcs, | |
1596 | DRM_MODE_ENCODER_DSI, NULL); | |
1597 | drm_encoder_helper_add(dsi->encoder, &vc4_dsi_encoder_helper_funcs); | |
1598 | ||
32ad958d EA |
1599 | ret = drm_bridge_attach(dsi->encoder, dsi->bridge, NULL); |
1600 | if (ret) { | |
1601 | dev_err(dev, "bridge attach failed: %d\n", ret); | |
1602 | return ret; | |
1603 | } | |
491657a9 EA |
1604 | /* Disable the atomic helper calls into the bridge. We |
1605 | * manually call the bridge pre_enable / enable / etc. calls | |
1606 | * from our driver, since we need to sequence them within the | |
1607 | * encoder's enable/disable paths. | |
1608 | */ | |
1609 | dsi->encoder->bridge = NULL; | |
4078f575 | 1610 | |
c9be804c EA |
1611 | if (dsi->port == 0) |
1612 | vc4_debugfs_add_regset32(drm, "dsi0_regs", &dsi->regset); | |
1613 | else | |
1614 | vc4_debugfs_add_regset32(drm, "dsi1_regs", &dsi->regset); | |
1615 | ||
4078f575 EA |
1616 | pm_runtime_enable(dev); |
1617 | ||
1618 | return 0; | |
4078f575 EA |
1619 | } |
1620 | ||
1621 | static void vc4_dsi_unbind(struct device *dev, struct device *master, | |
1622 | void *data) | |
1623 | { | |
1624 | struct drm_device *drm = dev_get_drvdata(master); | |
1625 | struct vc4_dev *vc4 = to_vc4_dev(drm); | |
1626 | struct vc4_dsi *dsi = dev_get_drvdata(dev); | |
1627 | ||
1b9883ea BB |
1628 | if (dsi->bridge) |
1629 | pm_runtime_disable(dev); | |
4078f575 | 1630 | |
4078f575 EA |
1631 | vc4_dsi_encoder_destroy(dsi->encoder); |
1632 | ||
4078f575 EA |
1633 | if (dsi->port == 1) |
1634 | vc4->dsi1 = NULL; | |
1635 | } | |
1636 | ||
1637 | static const struct component_ops vc4_dsi_ops = { | |
1638 | .bind = vc4_dsi_bind, | |
1639 | .unbind = vc4_dsi_unbind, | |
1640 | }; | |
1641 | ||
1642 | static int vc4_dsi_dev_probe(struct platform_device *pdev) | |
1643 | { | |
32ad958d EA |
1644 | struct device *dev = &pdev->dev; |
1645 | struct vc4_dsi *dsi; | |
1646 | int ret; | |
1647 | ||
1648 | dsi = devm_kzalloc(dev, sizeof(*dsi), GFP_KERNEL); | |
1649 | if (!dsi) | |
1650 | return -ENOMEM; | |
1651 | dev_set_drvdata(dev, dsi); | |
1652 | ||
1653 | dsi->pdev = pdev; | |
1654 | ||
1655 | /* Note, the initialization sequence for DSI and panels is | |
1656 | * tricky. The component bind above won't get past its | |
1657 | * -EPROBE_DEFER until the panel/bridge probes. The | |
1658 | * panel/bridge will return -EPROBE_DEFER until it has a | |
1659 | * mipi_dsi_host to register its device to. So, we register | |
1660 | * the host during pdev probe time, so vc4 as a whole can then | |
1661 | * -EPROBE_DEFER its component bind process until the panel | |
1662 | * successfully attaches. | |
1663 | */ | |
1664 | dsi->dsi_host.ops = &vc4_dsi_host_ops; | |
1665 | dsi->dsi_host.dev = dev; | |
1666 | mipi_dsi_host_register(&dsi->dsi_host); | |
1667 | ||
1668 | ret = component_add(&pdev->dev, &vc4_dsi_ops); | |
1669 | if (ret) { | |
1670 | mipi_dsi_host_unregister(&dsi->dsi_host); | |
1671 | return ret; | |
1672 | } | |
1673 | ||
1674 | return 0; | |
4078f575 EA |
1675 | } |
1676 | ||
1677 | static int vc4_dsi_dev_remove(struct platform_device *pdev) | |
1678 | { | |
32ad958d EA |
1679 | struct device *dev = &pdev->dev; |
1680 | struct vc4_dsi *dsi = dev_get_drvdata(dev); | |
1681 | ||
4078f575 | 1682 | component_del(&pdev->dev, &vc4_dsi_ops); |
32ad958d EA |
1683 | mipi_dsi_host_unregister(&dsi->dsi_host); |
1684 | ||
4078f575 EA |
1685 | return 0; |
1686 | } | |
1687 | ||
1688 | struct platform_driver vc4_dsi_driver = { | |
1689 | .probe = vc4_dsi_dev_probe, | |
1690 | .remove = vc4_dsi_dev_remove, | |
1691 | .driver = { | |
1692 | .name = "vc4_dsi", | |
1693 | .of_match_table = vc4_dsi_dt_match, | |
1694 | }, | |
1695 | }; |