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hwmon: (w83627ehf) The W83627DHG has 8 VID pins
[mirror_ubuntu-bionic-kernel.git] / drivers / hwmon / w83627hf.c
CommitLineData
1da177e4
LT
1/*
2 w83627hf.c - Part of lm_sensors, Linux kernel modules for hardware
3 monitoring
4 Copyright (c) 1998 - 2003 Frodo Looijaard <frodol@dds.nl>,
5 Philip Edelbrock <phil@netroedge.com>,
6 and Mark Studebaker <mdsxyz123@yahoo.com>
7 Ported to 2.6 by Bernhard C. Schrenk <clemy@clemy.org>
787c72b1 8 Copyright (c) 2007 Jean Delvare <khali@linux-fr.org>
1da177e4
LT
9
10 This program is free software; you can redistribute it and/or modify
11 it under the terms of the GNU General Public License as published by
12 the Free Software Foundation; either version 2 of the License, or
13 (at your option) any later version.
14
15 This program is distributed in the hope that it will be useful,
16 but WITHOUT ANY WARRANTY; without even the implied warranty of
17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 GNU General Public License for more details.
19
20 You should have received a copy of the GNU General Public License
21 along with this program; if not, write to the Free Software
22 Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
23*/
24
25/*
26 Supports following chips:
27
28 Chip #vin #fanin #pwm #temp wchipid vendid i2c ISA
29 w83627hf 9 3 2 3 0x20 0x5ca3 no yes(LPC)
30 w83627thf 7 3 3 3 0x90 0x5ca3 no yes(LPC)
31 w83637hf 7 3 3 3 0x80 0x5ca3 no yes(LPC)
c2db6ce1 32 w83687thf 7 3 3 3 0x90 0x5ca3 no yes(LPC)
1da177e4
LT
33 w83697hf 8 2 2 2 0x60 0x5ca3 no yes(LPC)
34
35 For other winbond chips, and for i2c support in the above chips,
36 use w83781d.c.
37
38 Note: automatic ("cruise") fan control for 697, 637 & 627thf not
39 supported yet.
40*/
41
42#include <linux/module.h>
43#include <linux/init.h>
44#include <linux/slab.h>
45#include <linux/jiffies.h>
787c72b1 46#include <linux/platform_device.h>
943b0830 47#include <linux/hwmon.h>
07584c76 48#include <linux/hwmon-sysfs.h>
303760b4 49#include <linux/hwmon-vid.h>
943b0830 50#include <linux/err.h>
9a61bf63 51#include <linux/mutex.h>
d27c37c0 52#include <linux/ioport.h>
1da177e4
LT
53#include <asm/io.h>
54#include "lm75.h"
55
787c72b1 56static struct platform_device *pdev;
d27c37c0
JD
57
58#define DRVNAME "w83627hf"
59enum chips { w83627hf, w83627thf, w83697hf, w83637hf, w83687thf };
60
1da177e4
LT
61static u16 force_addr;
62module_param(force_addr, ushort, 0);
63MODULE_PARM_DESC(force_addr,
64 "Initialize the base address of the sensors");
65static u8 force_i2c = 0x1f;
66module_param(force_i2c, byte, 0);
67MODULE_PARM_DESC(force_i2c,
68 "Initialize the i2c address of the sensors");
69
2251cf1a
JD
70static int reset;
71module_param(reset, bool, 0);
72MODULE_PARM_DESC(reset, "Set to one to reset chip on load");
73
1da177e4
LT
74static int init = 1;
75module_param(init, bool, 0);
76MODULE_PARM_DESC(init, "Set to zero to bypass chip initialization");
77
67b671bc
JD
78static unsigned short force_id;
79module_param(force_id, ushort, 0);
80MODULE_PARM_DESC(force_id, "Override the detected device ID");
81
1da177e4
LT
82/* modified from kernel/include/traps.c */
83static int REG; /* The register to read/write */
84#define DEV 0x07 /* Register: Logical device select */
85static int VAL; /* The value to read/write */
86
87/* logical device numbers for superio_select (below) */
88#define W83627HF_LD_FDC 0x00
89#define W83627HF_LD_PRT 0x01
90#define W83627HF_LD_UART1 0x02
91#define W83627HF_LD_UART2 0x03
92#define W83627HF_LD_KBC 0x05
93#define W83627HF_LD_CIR 0x06 /* w83627hf only */
94#define W83627HF_LD_GAME 0x07
95#define W83627HF_LD_MIDI 0x07
96#define W83627HF_LD_GPIO1 0x07
97#define W83627HF_LD_GPIO5 0x07 /* w83627thf only */
98#define W83627HF_LD_GPIO2 0x08
99#define W83627HF_LD_GPIO3 0x09
100#define W83627HF_LD_GPIO4 0x09 /* w83627thf only */
101#define W83627HF_LD_ACPI 0x0a
102#define W83627HF_LD_HWM 0x0b
103
104#define DEVID 0x20 /* Register: Device ID */
105
106#define W83627THF_GPIO5_EN 0x30 /* w83627thf only */
107#define W83627THF_GPIO5_IOSR 0xf3 /* w83627thf only */
108#define W83627THF_GPIO5_DR 0xf4 /* w83627thf only */
109
c2db6ce1
JD
110#define W83687THF_VID_EN 0x29 /* w83687thf only */
111#define W83687THF_VID_CFG 0xF0 /* w83687thf only */
112#define W83687THF_VID_DATA 0xF1 /* w83687thf only */
113
1da177e4
LT
114static inline void
115superio_outb(int reg, int val)
116{
117 outb(reg, REG);
118 outb(val, VAL);
119}
120
121static inline int
122superio_inb(int reg)
123{
124 outb(reg, REG);
125 return inb(VAL);
126}
127
128static inline void
129superio_select(int ld)
130{
131 outb(DEV, REG);
132 outb(ld, VAL);
133}
134
135static inline void
136superio_enter(void)
137{
138 outb(0x87, REG);
139 outb(0x87, REG);
140}
141
142static inline void
143superio_exit(void)
144{
145 outb(0xAA, REG);
146}
147
148#define W627_DEVID 0x52
149#define W627THF_DEVID 0x82
150#define W697_DEVID 0x60
151#define W637_DEVID 0x70
c2db6ce1 152#define W687THF_DEVID 0x85
1da177e4
LT
153#define WINB_ACT_REG 0x30
154#define WINB_BASE_REG 0x60
155/* Constants specified below */
156
ada0c2f8
PV
157/* Alignment of the base address */
158#define WINB_ALIGNMENT ~7
1da177e4 159
ada0c2f8
PV
160/* Offset & size of I/O region we are interested in */
161#define WINB_REGION_OFFSET 5
162#define WINB_REGION_SIZE 2
163
787c72b1
JD
164/* Where are the sensors address/data registers relative to the region offset */
165#define W83781D_ADDR_REG_OFFSET 0
166#define W83781D_DATA_REG_OFFSET 1
1da177e4
LT
167
168/* The W83781D registers */
169/* The W83782D registers for nr=7,8 are in bank 5 */
170#define W83781D_REG_IN_MAX(nr) ((nr < 7) ? (0x2b + (nr) * 2) : \
171 (0x554 + (((nr) - 7) * 2)))
172#define W83781D_REG_IN_MIN(nr) ((nr < 7) ? (0x2c + (nr) * 2) : \
173 (0x555 + (((nr) - 7) * 2)))
174#define W83781D_REG_IN(nr) ((nr < 7) ? (0x20 + (nr)) : \
175 (0x550 + (nr) - 7))
176
2ca2fcd1
JC
177/* nr:0-2 for fans:1-3 */
178#define W83627HF_REG_FAN_MIN(nr) (0x3b + (nr))
179#define W83627HF_REG_FAN(nr) (0x28 + (nr))
1da177e4 180
df48ed80
JC
181#define W83627HF_REG_TEMP2_CONFIG 0x152
182#define W83627HF_REG_TEMP3_CONFIG 0x252
183/* these are zero-based, unlike config constants above */
184static const u16 w83627hf_reg_temp[] = { 0x27, 0x150, 0x250 };
185static const u16 w83627hf_reg_temp_hyst[] = { 0x3A, 0x153, 0x253 };
186static const u16 w83627hf_reg_temp_over[] = { 0x39, 0x155, 0x255 };
1da177e4
LT
187
188#define W83781D_REG_BANK 0x4E
189
190#define W83781D_REG_CONFIG 0x40
4a1c4447
YM
191#define W83781D_REG_ALARM1 0x459
192#define W83781D_REG_ALARM2 0x45A
193#define W83781D_REG_ALARM3 0x45B
1da177e4 194
1da177e4
LT
195#define W83781D_REG_BEEP_CONFIG 0x4D
196#define W83781D_REG_BEEP_INTS1 0x56
197#define W83781D_REG_BEEP_INTS2 0x57
198#define W83781D_REG_BEEP_INTS3 0x453
199
200#define W83781D_REG_VID_FANDIV 0x47
201
202#define W83781D_REG_CHIPID 0x49
203#define W83781D_REG_WCHIPID 0x58
204#define W83781D_REG_CHIPMAN 0x4F
205#define W83781D_REG_PIN 0x4B
206
207#define W83781D_REG_VBAT 0x5D
208
209#define W83627HF_REG_PWM1 0x5A
210#define W83627HF_REG_PWM2 0x5B
1da177e4 211
c2db6ce1
JD
212#define W83627THF_REG_PWM1 0x01 /* 697HF/637HF/687THF too */
213#define W83627THF_REG_PWM2 0x03 /* 697HF/637HF/687THF too */
214#define W83627THF_REG_PWM3 0x11 /* 637HF/687THF too */
1da177e4 215
c2db6ce1 216#define W83627THF_REG_VRM_OVT_CFG 0x18 /* 637HF/687THF too */
1da177e4
LT
217
218static const u8 regpwm_627hf[] = { W83627HF_REG_PWM1, W83627HF_REG_PWM2 };
219static const u8 regpwm[] = { W83627THF_REG_PWM1, W83627THF_REG_PWM2,
220 W83627THF_REG_PWM3 };
221#define W836X7HF_REG_PWM(type, nr) (((type) == w83627hf) ? \
07584c76 222 regpwm_627hf[nr] : regpwm[nr])
1da177e4 223
1550cb6d
COM
224#define W83627HF_REG_PWM_FREQ 0x5C /* Only for the 627HF */
225
226#define W83637HF_REG_PWM_FREQ1 0x00 /* 697HF/687THF too */
227#define W83637HF_REG_PWM_FREQ2 0x02 /* 697HF/687THF too */
228#define W83637HF_REG_PWM_FREQ3 0x10 /* 687THF too */
229
230static const u8 W83637HF_REG_PWM_FREQ[] = { W83637HF_REG_PWM_FREQ1,
231 W83637HF_REG_PWM_FREQ2,
232 W83637HF_REG_PWM_FREQ3 };
233
234#define W83627HF_BASE_PWM_FREQ 46870
235
1da177e4
LT
236#define W83781D_REG_I2C_ADDR 0x48
237#define W83781D_REG_I2C_SUBADDR 0x4A
238
239/* Sensor selection */
240#define W83781D_REG_SCFG1 0x5D
241static const u8 BIT_SCFG1[] = { 0x02, 0x04, 0x08 };
242#define W83781D_REG_SCFG2 0x59
243static const u8 BIT_SCFG2[] = { 0x10, 0x20, 0x40 };
244#define W83781D_DEFAULT_BETA 3435
245
246/* Conversions. Limit checking is only done on the TO_REG
247 variants. Note that you should be a bit careful with which arguments
248 these macros are called: arguments may be evaluated more than once.
249 Fixing this is just not worth it. */
250#define IN_TO_REG(val) (SENSORS_LIMIT((((val) + 8)/16),0,255))
251#define IN_FROM_REG(val) ((val) * 16)
252
253static inline u8 FAN_TO_REG(long rpm, int div)
254{
255 if (rpm == 0)
256 return 255;
257 rpm = SENSORS_LIMIT(rpm, 1, 1000000);
258 return SENSORS_LIMIT((1350000 + rpm * div / 2) / (rpm * div), 1,
259 254);
260}
261
262#define TEMP_MIN (-128000)
263#define TEMP_MAX ( 127000)
264
265/* TEMP: 0.001C/bit (-128C to +127C)
266 REG: 1C/bit, two's complement */
5bfedac0 267static u8 TEMP_TO_REG(long temp)
1da177e4
LT
268{
269 int ntemp = SENSORS_LIMIT(temp, TEMP_MIN, TEMP_MAX);
270 ntemp += (ntemp<0 ? -500 : 500);
271 return (u8)(ntemp / 1000);
272}
273
274static int TEMP_FROM_REG(u8 reg)
275{
276 return (s8)reg * 1000;
277}
278
279#define FAN_FROM_REG(val,div) ((val)==0?-1:(val)==255?0:1350000/((val)*(div)))
280
281#define PWM_TO_REG(val) (SENSORS_LIMIT((val),0,255))
282
1550cb6d
COM
283static inline unsigned long pwm_freq_from_reg_627hf(u8 reg)
284{
285 unsigned long freq;
286 freq = W83627HF_BASE_PWM_FREQ >> reg;
287 return freq;
288}
289static inline u8 pwm_freq_to_reg_627hf(unsigned long val)
290{
291 u8 i;
292 /* Only 5 dividers (1 2 4 8 16)
293 Search for the nearest available frequency */
294 for (i = 0; i < 4; i++) {
295 if (val > (((W83627HF_BASE_PWM_FREQ >> i) +
296 (W83627HF_BASE_PWM_FREQ >> (i+1))) / 2))
297 break;
298 }
299 return i;
300}
301
302static inline unsigned long pwm_freq_from_reg(u8 reg)
303{
304 /* Clock bit 8 -> 180 kHz or 24 MHz */
305 unsigned long clock = (reg & 0x80) ? 180000UL : 24000000UL;
306
307 reg &= 0x7f;
308 /* This should not happen but anyway... */
309 if (reg == 0)
310 reg++;
311 return (clock / (reg << 8));
312}
313static inline u8 pwm_freq_to_reg(unsigned long val)
314{
315 /* Minimum divider value is 0x01 and maximum is 0x7F */
316 if (val >= 93750) /* The highest we can do */
317 return 0x01;
318 if (val >= 720) /* Use 24 MHz clock */
319 return (24000000UL / (val << 8));
320 if (val < 6) /* The lowest we can do */
321 return 0xFF;
322 else /* Use 180 kHz clock */
323 return (0x80 | (180000UL / (val << 8)));
324}
325
1da177e4
LT
326#define BEEP_MASK_FROM_REG(val) (val)
327#define BEEP_MASK_TO_REG(val) ((val) & 0xffffff)
328#define BEEP_ENABLE_TO_REG(val) ((val)?1:0)
329#define BEEP_ENABLE_FROM_REG(val) ((val)?1:0)
330
331#define DIV_FROM_REG(val) (1 << (val))
332
333static inline u8 DIV_TO_REG(long val)
334{
335 int i;
336 val = SENSORS_LIMIT(val, 1, 128) >> 1;
abc01922 337 for (i = 0; i < 7; i++) {
1da177e4
LT
338 if (val == 0)
339 break;
340 val >>= 1;
341 }
342 return ((u8) i);
343}
344
ed6bafbf
JD
345/* For each registered chip, we need to keep some data in memory.
346 The structure is dynamically allocated. */
1da177e4 347struct w83627hf_data {
787c72b1
JD
348 unsigned short addr;
349 const char *name;
1beeffe4 350 struct device *hwmon_dev;
9a61bf63 351 struct mutex lock;
1da177e4
LT
352 enum chips type;
353
9a61bf63 354 struct mutex update_lock;
1da177e4
LT
355 char valid; /* !=0 if following fields are valid */
356 unsigned long last_updated; /* In jiffies */
357
1da177e4
LT
358 u8 in[9]; /* Register value */
359 u8 in_max[9]; /* Register value */
360 u8 in_min[9]; /* Register value */
361 u8 fan[3]; /* Register value */
362 u8 fan_min[3]; /* Register value */
df48ed80
JC
363 u16 temp[3]; /* Register value */
364 u16 temp_max[3]; /* Register value */
365 u16 temp_max_hyst[3]; /* Register value */
1da177e4
LT
366 u8 fan_div[3]; /* Register encoding, shifted right */
367 u8 vid; /* Register encoding, combined */
368 u32 alarms; /* Register encoding, combined */
369 u32 beep_mask; /* Register encoding, combined */
370 u8 beep_enable; /* Boolean */
371 u8 pwm[3]; /* Register value */
1550cb6d 372 u8 pwm_freq[3]; /* Register value */
b26f9330
JD
373 u16 sens[3]; /* 1 = pentium diode; 2 = 3904 diode;
374 4 = thermistor */
1da177e4 375 u8 vrm;
c2db6ce1 376 u8 vrm_ovt; /* Register value, 627THF/637HF/687THF only */
1da177e4
LT
377};
378
787c72b1
JD
379struct w83627hf_sio_data {
380 enum chips type;
381};
1da177e4 382
1da177e4 383
787c72b1 384static int w83627hf_probe(struct platform_device *pdev);
d0546128 385static int __devexit w83627hf_remove(struct platform_device *pdev);
787c72b1
JD
386
387static int w83627hf_read_value(struct w83627hf_data *data, u16 reg);
388static int w83627hf_write_value(struct w83627hf_data *data, u16 reg, u16 value);
c09c5184 389static void w83627hf_update_fan_div(struct w83627hf_data *data);
1da177e4 390static struct w83627hf_data *w83627hf_update_device(struct device *dev);
787c72b1 391static void w83627hf_init_device(struct platform_device *pdev);
1da177e4 392
787c72b1 393static struct platform_driver w83627hf_driver = {
cdaf7934 394 .driver = {
87218842 395 .owner = THIS_MODULE,
d27c37c0 396 .name = DRVNAME,
cdaf7934 397 },
787c72b1
JD
398 .probe = w83627hf_probe,
399 .remove = __devexit_p(w83627hf_remove),
1da177e4
LT
400};
401
07584c76
JC
402static ssize_t
403show_in_input(struct device *dev, struct device_attribute *devattr, char *buf)
404{
405 int nr = to_sensor_dev_attr(devattr)->index;
406 struct w83627hf_data *data = w83627hf_update_device(dev);
407 return sprintf(buf, "%ld\n", (long)IN_FROM_REG(data->in[nr]));
1da177e4 408}
07584c76
JC
409static ssize_t
410show_in_min(struct device *dev, struct device_attribute *devattr, char *buf)
411{
412 int nr = to_sensor_dev_attr(devattr)->index;
413 struct w83627hf_data *data = w83627hf_update_device(dev);
414 return sprintf(buf, "%ld\n", (long)IN_FROM_REG(data->in_min[nr]));
415}
416static ssize_t
417show_in_max(struct device *dev, struct device_attribute *devattr, char *buf)
418{
419 int nr = to_sensor_dev_attr(devattr)->index;
420 struct w83627hf_data *data = w83627hf_update_device(dev);
421 return sprintf(buf, "%ld\n", (long)IN_FROM_REG(data->in_max[nr]));
1da177e4 422}
07584c76
JC
423static ssize_t
424store_in_min(struct device *dev, struct device_attribute *devattr,
425 const char *buf, size_t count)
426{
427 int nr = to_sensor_dev_attr(devattr)->index;
428 struct w83627hf_data *data = dev_get_drvdata(dev);
429 long val = simple_strtol(buf, NULL, 10);
1da177e4 430
07584c76
JC
431 mutex_lock(&data->update_lock);
432 data->in_min[nr] = IN_TO_REG(val);
433 w83627hf_write_value(data, W83781D_REG_IN_MIN(nr), data->in_min[nr]);
434 mutex_unlock(&data->update_lock);
435 return count;
436}
437static ssize_t
438store_in_max(struct device *dev, struct device_attribute *devattr,
439 const char *buf, size_t count)
440{
441 int nr = to_sensor_dev_attr(devattr)->index;
442 struct w83627hf_data *data = dev_get_drvdata(dev);
443 long val = simple_strtol(buf, NULL, 10);
1da177e4 444
07584c76
JC
445 mutex_lock(&data->update_lock);
446 data->in_max[nr] = IN_TO_REG(val);
447 w83627hf_write_value(data, W83781D_REG_IN_MAX(nr), data->in_max[nr]);
448 mutex_unlock(&data->update_lock);
449 return count;
450}
451#define sysfs_vin_decl(offset) \
452static SENSOR_DEVICE_ATTR(in##offset##_input, S_IRUGO, \
453 show_in_input, NULL, offset); \
454static SENSOR_DEVICE_ATTR(in##offset##_min, S_IRUGO|S_IWUSR, \
455 show_in_min, store_in_min, offset); \
456static SENSOR_DEVICE_ATTR(in##offset##_max, S_IRUGO|S_IWUSR, \
457 show_in_max, store_in_max, offset);
458
459sysfs_vin_decl(1);
460sysfs_vin_decl(2);
461sysfs_vin_decl(3);
462sysfs_vin_decl(4);
463sysfs_vin_decl(5);
464sysfs_vin_decl(6);
465sysfs_vin_decl(7);
466sysfs_vin_decl(8);
1da177e4
LT
467
468/* use a different set of functions for in0 */
469static ssize_t show_in_0(struct w83627hf_data *data, char *buf, u8 reg)
470{
471 long in0;
472
473 if ((data->vrm_ovt & 0x01) &&
c2db6ce1
JD
474 (w83627thf == data->type || w83637hf == data->type
475 || w83687thf == data->type))
1da177e4
LT
476
477 /* use VRM9 calculation */
478 in0 = (long)((reg * 488 + 70000 + 50) / 100);
479 else
480 /* use VRM8 (standard) calculation */
481 in0 = (long)IN_FROM_REG(reg);
482
483 return sprintf(buf,"%ld\n", in0);
484}
485
a5099cfc 486static ssize_t show_regs_in_0(struct device *dev, struct device_attribute *attr, char *buf)
1da177e4
LT
487{
488 struct w83627hf_data *data = w83627hf_update_device(dev);
489 return show_in_0(data, buf, data->in[0]);
490}
491
a5099cfc 492static ssize_t show_regs_in_min0(struct device *dev, struct device_attribute *attr, char *buf)
1da177e4
LT
493{
494 struct w83627hf_data *data = w83627hf_update_device(dev);
495 return show_in_0(data, buf, data->in_min[0]);
496}
497
a5099cfc 498static ssize_t show_regs_in_max0(struct device *dev, struct device_attribute *attr, char *buf)
1da177e4
LT
499{
500 struct w83627hf_data *data = w83627hf_update_device(dev);
501 return show_in_0(data, buf, data->in_max[0]);
502}
503
a5099cfc 504static ssize_t store_regs_in_min0(struct device *dev, struct device_attribute *attr,
1da177e4
LT
505 const char *buf, size_t count)
506{
787c72b1 507 struct w83627hf_data *data = dev_get_drvdata(dev);
1da177e4
LT
508 u32 val;
509
510 val = simple_strtoul(buf, NULL, 10);
511
9a61bf63 512 mutex_lock(&data->update_lock);
1da177e4
LT
513
514 if ((data->vrm_ovt & 0x01) &&
c2db6ce1
JD
515 (w83627thf == data->type || w83637hf == data->type
516 || w83687thf == data->type))
1da177e4
LT
517
518 /* use VRM9 calculation */
2723ab91
YM
519 data->in_min[0] =
520 SENSORS_LIMIT(((val * 100) - 70000 + 244) / 488, 0,
521 255);
1da177e4
LT
522 else
523 /* use VRM8 (standard) calculation */
524 data->in_min[0] = IN_TO_REG(val);
525
787c72b1 526 w83627hf_write_value(data, W83781D_REG_IN_MIN(0), data->in_min[0]);
9a61bf63 527 mutex_unlock(&data->update_lock);
1da177e4
LT
528 return count;
529}
530
a5099cfc 531static ssize_t store_regs_in_max0(struct device *dev, struct device_attribute *attr,
1da177e4
LT
532 const char *buf, size_t count)
533{
787c72b1 534 struct w83627hf_data *data = dev_get_drvdata(dev);
1da177e4
LT
535 u32 val;
536
537 val = simple_strtoul(buf, NULL, 10);
538
9a61bf63 539 mutex_lock(&data->update_lock);
1da177e4
LT
540
541 if ((data->vrm_ovt & 0x01) &&
c2db6ce1
JD
542 (w83627thf == data->type || w83637hf == data->type
543 || w83687thf == data->type))
1da177e4
LT
544
545 /* use VRM9 calculation */
2723ab91
YM
546 data->in_max[0] =
547 SENSORS_LIMIT(((val * 100) - 70000 + 244) / 488, 0,
548 255);
1da177e4
LT
549 else
550 /* use VRM8 (standard) calculation */
551 data->in_max[0] = IN_TO_REG(val);
552
787c72b1 553 w83627hf_write_value(data, W83781D_REG_IN_MAX(0), data->in_max[0]);
9a61bf63 554 mutex_unlock(&data->update_lock);
1da177e4
LT
555 return count;
556}
557
558static DEVICE_ATTR(in0_input, S_IRUGO, show_regs_in_0, NULL);
559static DEVICE_ATTR(in0_min, S_IRUGO | S_IWUSR,
560 show_regs_in_min0, store_regs_in_min0);
561static DEVICE_ATTR(in0_max, S_IRUGO | S_IWUSR,
562 show_regs_in_max0, store_regs_in_max0);
563
07584c76
JC
564static ssize_t
565show_fan_input(struct device *dev, struct device_attribute *devattr, char *buf)
566{
567 int nr = to_sensor_dev_attr(devattr)->index;
568 struct w83627hf_data *data = w83627hf_update_device(dev);
569 return sprintf(buf, "%ld\n", FAN_FROM_REG(data->fan[nr],
570 (long)DIV_FROM_REG(data->fan_div[nr])));
571}
572static ssize_t
573show_fan_min(struct device *dev, struct device_attribute *devattr, char *buf)
574{
575 int nr = to_sensor_dev_attr(devattr)->index;
576 struct w83627hf_data *data = w83627hf_update_device(dev);
577 return sprintf(buf, "%ld\n", FAN_FROM_REG(data->fan_min[nr],
578 (long)DIV_FROM_REG(data->fan_div[nr])));
1da177e4 579}
1da177e4 580static ssize_t
07584c76
JC
581store_fan_min(struct device *dev, struct device_attribute *devattr,
582 const char *buf, size_t count)
1da177e4 583{
07584c76 584 int nr = to_sensor_dev_attr(devattr)->index;
787c72b1 585 struct w83627hf_data *data = dev_get_drvdata(dev);
07584c76 586 u32 val = simple_strtoul(buf, NULL, 10);
1da177e4 587
9a61bf63 588 mutex_lock(&data->update_lock);
07584c76 589 data->fan_min[nr] = FAN_TO_REG(val, DIV_FROM_REG(data->fan_div[nr]));
2ca2fcd1 590 w83627hf_write_value(data, W83627HF_REG_FAN_MIN(nr),
07584c76 591 data->fan_min[nr]);
1da177e4 592
9a61bf63 593 mutex_unlock(&data->update_lock);
1da177e4
LT
594 return count;
595}
07584c76
JC
596#define sysfs_fan_decl(offset) \
597static SENSOR_DEVICE_ATTR(fan##offset##_input, S_IRUGO, \
598 show_fan_input, NULL, offset - 1); \
599static SENSOR_DEVICE_ATTR(fan##offset##_min, S_IRUGO | S_IWUSR, \
600 show_fan_min, store_fan_min, offset - 1);
1da177e4 601
07584c76
JC
602sysfs_fan_decl(1);
603sysfs_fan_decl(2);
604sysfs_fan_decl(3);
1da177e4 605
07584c76
JC
606static ssize_t
607show_temp(struct device *dev, struct device_attribute *devattr, char *buf)
608{
609 int nr = to_sensor_dev_attr(devattr)->index;
610 struct w83627hf_data *data = w83627hf_update_device(dev);
df48ed80
JC
611
612 u16 tmp = data->temp[nr];
613 return sprintf(buf, "%ld\n", (nr) ? (long) LM75_TEMP_FROM_REG(tmp)
614 : (long) TEMP_FROM_REG(tmp));
1da177e4 615}
1da177e4 616
07584c76
JC
617static ssize_t
618show_temp_max(struct device *dev, struct device_attribute *devattr,
619 char *buf)
620{
621 int nr = to_sensor_dev_attr(devattr)->index;
622 struct w83627hf_data *data = w83627hf_update_device(dev);
df48ed80
JC
623
624 u16 tmp = data->temp_max[nr];
625 return sprintf(buf, "%ld\n", (nr) ? (long) LM75_TEMP_FROM_REG(tmp)
626 : (long) TEMP_FROM_REG(tmp));
1da177e4 627}
1da177e4 628
07584c76
JC
629static ssize_t
630show_temp_max_hyst(struct device *dev, struct device_attribute *devattr,
631 char *buf)
632{
633 int nr = to_sensor_dev_attr(devattr)->index;
634 struct w83627hf_data *data = w83627hf_update_device(dev);
df48ed80
JC
635
636 u16 tmp = data->temp_max_hyst[nr];
637 return sprintf(buf, "%ld\n", (nr) ? (long) LM75_TEMP_FROM_REG(tmp)
638 : (long) TEMP_FROM_REG(tmp));
07584c76 639}
1da177e4 640
07584c76
JC
641static ssize_t
642store_temp_max(struct device *dev, struct device_attribute *devattr,
643 const char *buf, size_t count)
644{
645 int nr = to_sensor_dev_attr(devattr)->index;
646 struct w83627hf_data *data = dev_get_drvdata(dev);
647 long val = simple_strtol(buf, NULL, 10);
df48ed80 648 u16 tmp = (nr) ? LM75_TEMP_TO_REG(val) : TEMP_TO_REG(val);
1da177e4 649
07584c76 650 mutex_lock(&data->update_lock);
df48ed80
JC
651 data->temp_max[nr] = tmp;
652 w83627hf_write_value(data, w83627hf_reg_temp_over[nr], tmp);
07584c76
JC
653 mutex_unlock(&data->update_lock);
654 return count;
655}
656
657static ssize_t
658store_temp_max_hyst(struct device *dev, struct device_attribute *devattr,
659 const char *buf, size_t count)
660{
661 int nr = to_sensor_dev_attr(devattr)->index;
662 struct w83627hf_data *data = dev_get_drvdata(dev);
663 long val = simple_strtol(buf, NULL, 10);
df48ed80 664 u16 tmp = (nr) ? LM75_TEMP_TO_REG(val) : TEMP_TO_REG(val);
07584c76
JC
665
666 mutex_lock(&data->update_lock);
df48ed80
JC
667 data->temp_max_hyst[nr] = tmp;
668 w83627hf_write_value(data, w83627hf_reg_temp_hyst[nr], tmp);
07584c76
JC
669 mutex_unlock(&data->update_lock);
670 return count;
671}
672
673#define sysfs_temp_decl(offset) \
674static SENSOR_DEVICE_ATTR(temp##offset##_input, S_IRUGO, \
df48ed80 675 show_temp, NULL, offset - 1); \
07584c76 676static SENSOR_DEVICE_ATTR(temp##offset##_max, S_IRUGO|S_IWUSR, \
df48ed80 677 show_temp_max, store_temp_max, offset - 1); \
07584c76 678static SENSOR_DEVICE_ATTR(temp##offset##_max_hyst, S_IRUGO|S_IWUSR, \
df48ed80 679 show_temp_max_hyst, store_temp_max_hyst, offset - 1);
07584c76
JC
680
681sysfs_temp_decl(1);
682sysfs_temp_decl(2);
683sysfs_temp_decl(3);
1da177e4 684
1da177e4 685static ssize_t
a5099cfc 686show_vid_reg(struct device *dev, struct device_attribute *attr, char *buf)
1da177e4
LT
687{
688 struct w83627hf_data *data = w83627hf_update_device(dev);
689 return sprintf(buf, "%ld\n", (long) vid_from_reg(data->vid, data->vrm));
690}
691static DEVICE_ATTR(cpu0_vid, S_IRUGO, show_vid_reg, NULL);
1da177e4
LT
692
693static ssize_t
a5099cfc 694show_vrm_reg(struct device *dev, struct device_attribute *attr, char *buf)
1da177e4 695{
90d6619a 696 struct w83627hf_data *data = dev_get_drvdata(dev);
1da177e4
LT
697 return sprintf(buf, "%ld\n", (long) data->vrm);
698}
699static ssize_t
a5099cfc 700store_vrm_reg(struct device *dev, struct device_attribute *attr, const char *buf, size_t count)
1da177e4 701{
787c72b1 702 struct w83627hf_data *data = dev_get_drvdata(dev);
1da177e4
LT
703 u32 val;
704
705 val = simple_strtoul(buf, NULL, 10);
706 data->vrm = val;
707
708 return count;
709}
710static DEVICE_ATTR(vrm, S_IRUGO | S_IWUSR, show_vrm_reg, store_vrm_reg);
1da177e4
LT
711
712static ssize_t
a5099cfc 713show_alarms_reg(struct device *dev, struct device_attribute *attr, char *buf)
1da177e4
LT
714{
715 struct w83627hf_data *data = w83627hf_update_device(dev);
716 return sprintf(buf, "%ld\n", (long) data->alarms);
717}
718static DEVICE_ATTR(alarms, S_IRUGO, show_alarms_reg, NULL);
1da177e4
LT
719
720#define show_beep_reg(REG, reg) \
a5099cfc 721static ssize_t show_beep_##reg (struct device *dev, struct device_attribute *attr, char *buf) \
1da177e4
LT
722{ \
723 struct w83627hf_data *data = w83627hf_update_device(dev); \
724 return sprintf(buf,"%ld\n", \
725 (long)BEEP_##REG##_FROM_REG(data->beep_##reg)); \
726}
727show_beep_reg(ENABLE, enable)
728show_beep_reg(MASK, mask)
729
730#define BEEP_ENABLE 0 /* Store beep_enable */
731#define BEEP_MASK 1 /* Store beep_mask */
732
733static ssize_t
734store_beep_reg(struct device *dev, const char *buf, size_t count,
735 int update_mask)
736{
787c72b1 737 struct w83627hf_data *data = dev_get_drvdata(dev);
1da177e4
LT
738 u32 val, val2;
739
740 val = simple_strtoul(buf, NULL, 10);
741
9a61bf63 742 mutex_lock(&data->update_lock);
1da177e4
LT
743
744 if (update_mask == BEEP_MASK) { /* We are storing beep_mask */
745 data->beep_mask = BEEP_MASK_TO_REG(val);
787c72b1 746 w83627hf_write_value(data, W83781D_REG_BEEP_INTS1,
1da177e4 747 data->beep_mask & 0xff);
787c72b1 748 w83627hf_write_value(data, W83781D_REG_BEEP_INTS3,
1da177e4
LT
749 ((data->beep_mask) >> 16) & 0xff);
750 val2 = (data->beep_mask >> 8) & 0x7f;
751 } else { /* We are storing beep_enable */
752 val2 =
787c72b1 753 w83627hf_read_value(data, W83781D_REG_BEEP_INTS2) & 0x7f;
1da177e4
LT
754 data->beep_enable = BEEP_ENABLE_TO_REG(val);
755 }
756
787c72b1 757 w83627hf_write_value(data, W83781D_REG_BEEP_INTS2,
1da177e4
LT
758 val2 | data->beep_enable << 7);
759
9a61bf63 760 mutex_unlock(&data->update_lock);
1da177e4
LT
761 return count;
762}
763
764#define sysfs_beep(REG, reg) \
a5099cfc 765static ssize_t show_regs_beep_##reg (struct device *dev, struct device_attribute *attr, char *buf) \
1da177e4 766{ \
a5099cfc 767 return show_beep_##reg(dev, attr, buf); \
1da177e4
LT
768} \
769static ssize_t \
a5099cfc 770store_regs_beep_##reg (struct device *dev, struct device_attribute *attr, const char *buf, size_t count) \
1da177e4
LT
771{ \
772 return store_beep_reg(dev, buf, count, BEEP_##REG); \
773} \
774static DEVICE_ATTR(beep_##reg, S_IRUGO | S_IWUSR, \
775 show_regs_beep_##reg, store_regs_beep_##reg);
776
777sysfs_beep(ENABLE, enable);
778sysfs_beep(MASK, mask);
779
1da177e4 780static ssize_t
07584c76 781show_fan_div(struct device *dev, struct device_attribute *devattr, char *buf)
1da177e4 782{
07584c76 783 int nr = to_sensor_dev_attr(devattr)->index;
1da177e4
LT
784 struct w83627hf_data *data = w83627hf_update_device(dev);
785 return sprintf(buf, "%ld\n",
07584c76 786 (long) DIV_FROM_REG(data->fan_div[nr]));
1da177e4 787}
1da177e4
LT
788/* Note: we save and restore the fan minimum here, because its value is
789 determined in part by the fan divisor. This follows the principle of
d6e05edc 790 least surprise; the user doesn't expect the fan minimum to change just
1da177e4
LT
791 because the divisor changed. */
792static ssize_t
07584c76
JC
793store_fan_div(struct device *dev, struct device_attribute *devattr,
794 const char *buf, size_t count)
1da177e4 795{
07584c76 796 int nr = to_sensor_dev_attr(devattr)->index;
787c72b1 797 struct w83627hf_data *data = dev_get_drvdata(dev);
1da177e4
LT
798 unsigned long min;
799 u8 reg;
800 unsigned long val = simple_strtoul(buf, NULL, 10);
801
9a61bf63 802 mutex_lock(&data->update_lock);
1da177e4
LT
803
804 /* Save fan_min */
805 min = FAN_FROM_REG(data->fan_min[nr],
806 DIV_FROM_REG(data->fan_div[nr]));
807
808 data->fan_div[nr] = DIV_TO_REG(val);
809
787c72b1 810 reg = (w83627hf_read_value(data, nr==2 ? W83781D_REG_PIN : W83781D_REG_VID_FANDIV)
1da177e4
LT
811 & (nr==0 ? 0xcf : 0x3f))
812 | ((data->fan_div[nr] & 0x03) << (nr==0 ? 4 : 6));
787c72b1 813 w83627hf_write_value(data, nr==2 ? W83781D_REG_PIN : W83781D_REG_VID_FANDIV, reg);
1da177e4 814
787c72b1 815 reg = (w83627hf_read_value(data, W83781D_REG_VBAT)
1da177e4
LT
816 & ~(1 << (5 + nr)))
817 | ((data->fan_div[nr] & 0x04) << (3 + nr));
787c72b1 818 w83627hf_write_value(data, W83781D_REG_VBAT, reg);
1da177e4
LT
819
820 /* Restore fan_min */
821 data->fan_min[nr] = FAN_TO_REG(min, DIV_FROM_REG(data->fan_div[nr]));
2ca2fcd1 822 w83627hf_write_value(data, W83627HF_REG_FAN_MIN(nr), data->fan_min[nr]);
1da177e4 823
9a61bf63 824 mutex_unlock(&data->update_lock);
1da177e4
LT
825 return count;
826}
827
07584c76
JC
828static SENSOR_DEVICE_ATTR(fan1_div, S_IRUGO|S_IWUSR,
829 show_fan_div, store_fan_div, 0);
830static SENSOR_DEVICE_ATTR(fan2_div, S_IRUGO|S_IWUSR,
831 show_fan_div, store_fan_div, 1);
832static SENSOR_DEVICE_ATTR(fan3_div, S_IRUGO|S_IWUSR,
833 show_fan_div, store_fan_div, 2);
1da177e4 834
1da177e4 835static ssize_t
07584c76 836show_pwm(struct device *dev, struct device_attribute *devattr, char *buf)
1da177e4 837{
07584c76 838 int nr = to_sensor_dev_attr(devattr)->index;
1da177e4 839 struct w83627hf_data *data = w83627hf_update_device(dev);
07584c76 840 return sprintf(buf, "%ld\n", (long) data->pwm[nr]);
1da177e4
LT
841}
842
843static ssize_t
07584c76
JC
844store_pwm(struct device *dev, struct device_attribute *devattr,
845 const char *buf, size_t count)
1da177e4 846{
07584c76 847 int nr = to_sensor_dev_attr(devattr)->index;
787c72b1 848 struct w83627hf_data *data = dev_get_drvdata(dev);
07584c76 849 u32 val = simple_strtoul(buf, NULL, 10);
1da177e4 850
9a61bf63 851 mutex_lock(&data->update_lock);
1da177e4
LT
852
853 if (data->type == w83627thf) {
854 /* bits 0-3 are reserved in 627THF */
07584c76 855 data->pwm[nr] = PWM_TO_REG(val) & 0xf0;
787c72b1 856 w83627hf_write_value(data,
1da177e4 857 W836X7HF_REG_PWM(data->type, nr),
07584c76 858 data->pwm[nr] |
787c72b1 859 (w83627hf_read_value(data,
1da177e4
LT
860 W836X7HF_REG_PWM(data->type, nr)) & 0x0f));
861 } else {
07584c76 862 data->pwm[nr] = PWM_TO_REG(val);
787c72b1 863 w83627hf_write_value(data,
1da177e4 864 W836X7HF_REG_PWM(data->type, nr),
07584c76 865 data->pwm[nr]);
1da177e4
LT
866 }
867
9a61bf63 868 mutex_unlock(&data->update_lock);
1da177e4
LT
869 return count;
870}
871
07584c76
JC
872static SENSOR_DEVICE_ATTR(pwm1, S_IRUGO|S_IWUSR, show_pwm, store_pwm, 0);
873static SENSOR_DEVICE_ATTR(pwm2, S_IRUGO|S_IWUSR, show_pwm, store_pwm, 1);
874static SENSOR_DEVICE_ATTR(pwm3, S_IRUGO|S_IWUSR, show_pwm, store_pwm, 2);
1da177e4 875
1550cb6d 876static ssize_t
07584c76 877show_pwm_freq(struct device *dev, struct device_attribute *devattr, char *buf)
1550cb6d 878{
07584c76 879 int nr = to_sensor_dev_attr(devattr)->index;
1550cb6d
COM
880 struct w83627hf_data *data = w83627hf_update_device(dev);
881 if (data->type == w83627hf)
882 return sprintf(buf, "%ld\n",
07584c76 883 pwm_freq_from_reg_627hf(data->pwm_freq[nr]));
1550cb6d
COM
884 else
885 return sprintf(buf, "%ld\n",
07584c76 886 pwm_freq_from_reg(data->pwm_freq[nr]));
1550cb6d
COM
887}
888
889static ssize_t
07584c76
JC
890store_pwm_freq(struct device *dev, struct device_attribute *devattr,
891 const char *buf, size_t count)
1550cb6d 892{
07584c76 893 int nr = to_sensor_dev_attr(devattr)->index;
1550cb6d
COM
894 struct w83627hf_data *data = dev_get_drvdata(dev);
895 static const u8 mask[]={0xF8, 0x8F};
896 u32 val;
897
898 val = simple_strtoul(buf, NULL, 10);
899
900 mutex_lock(&data->update_lock);
901
902 if (data->type == w83627hf) {
07584c76 903 data->pwm_freq[nr] = pwm_freq_to_reg_627hf(val);
1550cb6d 904 w83627hf_write_value(data, W83627HF_REG_PWM_FREQ,
07584c76 905 (data->pwm_freq[nr] << (nr*4)) |
1550cb6d 906 (w83627hf_read_value(data,
07584c76 907 W83627HF_REG_PWM_FREQ) & mask[nr]));
1550cb6d 908 } else {
07584c76
JC
909 data->pwm_freq[nr] = pwm_freq_to_reg(val);
910 w83627hf_write_value(data, W83637HF_REG_PWM_FREQ[nr],
911 data->pwm_freq[nr]);
1550cb6d
COM
912 }
913
914 mutex_unlock(&data->update_lock);
915 return count;
916}
917
07584c76
JC
918static SENSOR_DEVICE_ATTR(pwm1_freq, S_IRUGO|S_IWUSR,
919 show_pwm_freq, store_pwm_freq, 0);
920static SENSOR_DEVICE_ATTR(pwm2_freq, S_IRUGO|S_IWUSR,
921 show_pwm_freq, store_pwm_freq, 1);
922static SENSOR_DEVICE_ATTR(pwm3_freq, S_IRUGO|S_IWUSR,
923 show_pwm_freq, store_pwm_freq, 2);
1550cb6d 924
1da177e4 925static ssize_t
07584c76
JC
926show_temp_type(struct device *dev, struct device_attribute *devattr,
927 char *buf)
1da177e4 928{
07584c76 929 int nr = to_sensor_dev_attr(devattr)->index;
1da177e4 930 struct w83627hf_data *data = w83627hf_update_device(dev);
07584c76 931 return sprintf(buf, "%ld\n", (long) data->sens[nr]);
1da177e4
LT
932}
933
934static ssize_t
07584c76
JC
935store_temp_type(struct device *dev, struct device_attribute *devattr,
936 const char *buf, size_t count)
1da177e4 937{
07584c76 938 int nr = to_sensor_dev_attr(devattr)->index;
787c72b1 939 struct w83627hf_data *data = dev_get_drvdata(dev);
1da177e4
LT
940 u32 val, tmp;
941
942 val = simple_strtoul(buf, NULL, 10);
943
9a61bf63 944 mutex_lock(&data->update_lock);
1da177e4
LT
945
946 switch (val) {
947 case 1: /* PII/Celeron diode */
787c72b1
JD
948 tmp = w83627hf_read_value(data, W83781D_REG_SCFG1);
949 w83627hf_write_value(data, W83781D_REG_SCFG1,
07584c76 950 tmp | BIT_SCFG1[nr]);
787c72b1
JD
951 tmp = w83627hf_read_value(data, W83781D_REG_SCFG2);
952 w83627hf_write_value(data, W83781D_REG_SCFG2,
07584c76
JC
953 tmp | BIT_SCFG2[nr]);
954 data->sens[nr] = val;
1da177e4
LT
955 break;
956 case 2: /* 3904 */
787c72b1
JD
957 tmp = w83627hf_read_value(data, W83781D_REG_SCFG1);
958 w83627hf_write_value(data, W83781D_REG_SCFG1,
07584c76 959 tmp | BIT_SCFG1[nr]);
787c72b1
JD
960 tmp = w83627hf_read_value(data, W83781D_REG_SCFG2);
961 w83627hf_write_value(data, W83781D_REG_SCFG2,
07584c76
JC
962 tmp & ~BIT_SCFG2[nr]);
963 data->sens[nr] = val;
1da177e4 964 break;
b26f9330
JD
965 case W83781D_DEFAULT_BETA:
966 dev_warn(dev, "Sensor type %d is deprecated, please use 4 "
967 "instead\n", W83781D_DEFAULT_BETA);
968 /* fall through */
969 case 4: /* thermistor */
787c72b1
JD
970 tmp = w83627hf_read_value(data, W83781D_REG_SCFG1);
971 w83627hf_write_value(data, W83781D_REG_SCFG1,
07584c76
JC
972 tmp & ~BIT_SCFG1[nr]);
973 data->sens[nr] = val;
1da177e4
LT
974 break;
975 default:
787c72b1 976 dev_err(dev,
b26f9330
JD
977 "Invalid sensor type %ld; must be 1, 2, or 4\n",
978 (long) val);
1da177e4
LT
979 break;
980 }
981
9a61bf63 982 mutex_unlock(&data->update_lock);
1da177e4
LT
983 return count;
984}
985
07584c76
JC
986#define sysfs_temp_type(offset) \
987static SENSOR_DEVICE_ATTR(temp##offset##_type, S_IRUGO | S_IWUSR, \
988 show_temp_type, store_temp_type, offset - 1);
1da177e4 989
07584c76
JC
990sysfs_temp_type(1);
991sysfs_temp_type(2);
992sysfs_temp_type(3);
1da177e4 993
07584c76
JC
994static ssize_t
995show_name(struct device *dev, struct device_attribute *devattr, char *buf)
787c72b1
JD
996{
997 struct w83627hf_data *data = dev_get_drvdata(dev);
998
999 return sprintf(buf, "%s\n", data->name);
1000}
1001static DEVICE_ATTR(name, S_IRUGO, show_name, NULL);
1002
1003static int __init w83627hf_find(int sioaddr, unsigned short *addr,
1004 struct w83627hf_sio_data *sio_data)
1da177e4 1005{
d27c37c0 1006 int err = -ENODEV;
1da177e4
LT
1007 u16 val;
1008
787c72b1
JD
1009 static const __initdata char *names[] = {
1010 "W83627HF",
1011 "W83627THF",
1012 "W83697HF",
1013 "W83637HF",
1014 "W83687THF",
1015 };
1016
1da177e4
LT
1017 REG = sioaddr;
1018 VAL = sioaddr + 1;
1019
1020 superio_enter();
67b671bc 1021 val = force_id ? force_id : superio_inb(DEVID);
787c72b1
JD
1022 switch (val) {
1023 case W627_DEVID:
1024 sio_data->type = w83627hf;
1025 break;
1026 case W627THF_DEVID:
1027 sio_data->type = w83627thf;
1028 break;
1029 case W697_DEVID:
1030 sio_data->type = w83697hf;
1031 break;
1032 case W637_DEVID:
1033 sio_data->type = w83637hf;
1034 break;
1035 case W687THF_DEVID:
1036 sio_data->type = w83687thf;
1037 break;
e142e2a3
JD
1038 case 0xff: /* No device at all */
1039 goto exit;
787c72b1 1040 default:
e142e2a3 1041 pr_debug(DRVNAME ": Unsupported chip (DEVID=0x%02x)\n", val);
d27c37c0 1042 goto exit;
1da177e4
LT
1043 }
1044
1045 superio_select(W83627HF_LD_HWM);
d27c37c0
JD
1046 force_addr &= WINB_ALIGNMENT;
1047 if (force_addr) {
1048 printk(KERN_WARNING DRVNAME ": Forcing address 0x%x\n",
1049 force_addr);
1050 superio_outb(WINB_BASE_REG, force_addr >> 8);
1051 superio_outb(WINB_BASE_REG + 1, force_addr & 0xff);
1052 }
1da177e4
LT
1053 val = (superio_inb(WINB_BASE_REG) << 8) |
1054 superio_inb(WINB_BASE_REG + 1);
ada0c2f8 1055 *addr = val & WINB_ALIGNMENT;
d27c37c0
JD
1056 if (*addr == 0) {
1057 printk(KERN_WARNING DRVNAME ": Base address not set, "
1058 "skipping\n");
1059 goto exit;
1da177e4 1060 }
1da177e4 1061
d27c37c0
JD
1062 val = superio_inb(WINB_ACT_REG);
1063 if (!(val & 0x01)) {
1064 printk(KERN_WARNING DRVNAME ": Enabling HWM logical device\n");
1065 superio_outb(WINB_ACT_REG, val | 0x01);
1066 }
1067
1068 err = 0;
787c72b1
JD
1069 pr_info(DRVNAME ": Found %s chip at %#x\n",
1070 names[sio_data->type], *addr);
d27c37c0
JD
1071
1072 exit:
1da177e4 1073 superio_exit();
d27c37c0 1074 return err;
1da177e4
LT
1075}
1076
07584c76
JC
1077#define VIN_UNIT_ATTRS(_X_) \
1078 &sensor_dev_attr_in##_X_##_input.dev_attr.attr, \
1079 &sensor_dev_attr_in##_X_##_min.dev_attr.attr, \
1080 &sensor_dev_attr_in##_X_##_max.dev_attr.attr
1081
1082#define FAN_UNIT_ATTRS(_X_) \
1083 &sensor_dev_attr_fan##_X_##_input.dev_attr.attr, \
1084 &sensor_dev_attr_fan##_X_##_min.dev_attr.attr, \
1085 &sensor_dev_attr_fan##_X_##_div.dev_attr.attr
1086
1087#define TEMP_UNIT_ATTRS(_X_) \
1088 &sensor_dev_attr_temp##_X_##_input.dev_attr.attr, \
1089 &sensor_dev_attr_temp##_X_##_max.dev_attr.attr, \
1090 &sensor_dev_attr_temp##_X_##_max_hyst.dev_attr.attr, \
1091 &sensor_dev_attr_temp##_X_##_type.dev_attr.attr
1092
c1685f61
MH
1093static struct attribute *w83627hf_attributes[] = {
1094 &dev_attr_in0_input.attr,
1095 &dev_attr_in0_min.attr,
1096 &dev_attr_in0_max.attr,
07584c76
JC
1097 VIN_UNIT_ATTRS(2),
1098 VIN_UNIT_ATTRS(3),
1099 VIN_UNIT_ATTRS(4),
1100 VIN_UNIT_ATTRS(7),
1101 VIN_UNIT_ATTRS(8),
1102
1103 FAN_UNIT_ATTRS(1),
1104 FAN_UNIT_ATTRS(2),
1105
1106 TEMP_UNIT_ATTRS(1),
1107 TEMP_UNIT_ATTRS(2),
c1685f61
MH
1108
1109 &dev_attr_alarms.attr,
1110 &dev_attr_beep_enable.attr,
1111 &dev_attr_beep_mask.attr,
1112
07584c76
JC
1113 &sensor_dev_attr_pwm1.dev_attr.attr,
1114 &sensor_dev_attr_pwm2.dev_attr.attr,
787c72b1 1115 &dev_attr_name.attr,
c1685f61
MH
1116 NULL
1117};
1118
1119static const struct attribute_group w83627hf_group = {
1120 .attrs = w83627hf_attributes,
1121};
1122
1123static struct attribute *w83627hf_attributes_opt[] = {
07584c76
JC
1124 VIN_UNIT_ATTRS(1),
1125 VIN_UNIT_ATTRS(5),
1126 VIN_UNIT_ATTRS(6),
1127
1128 FAN_UNIT_ATTRS(3),
1129 TEMP_UNIT_ATTRS(3),
1130 &sensor_dev_attr_pwm3.dev_attr.attr,
1131
1132 &sensor_dev_attr_pwm1_freq.dev_attr.attr,
1133 &sensor_dev_attr_pwm2_freq.dev_attr.attr,
1134 &sensor_dev_attr_pwm3_freq.dev_attr.attr,
c1685f61
MH
1135 NULL
1136};
1137
1138static const struct attribute_group w83627hf_group_opt = {
1139 .attrs = w83627hf_attributes_opt,
1140};
1141
787c72b1 1142static int __devinit w83627hf_probe(struct platform_device *pdev)
1da177e4 1143{
787c72b1
JD
1144 struct device *dev = &pdev->dev;
1145 struct w83627hf_sio_data *sio_data = dev->platform_data;
1da177e4 1146 struct w83627hf_data *data;
787c72b1 1147 struct resource *res;
2ca2fcd1 1148 int err, i;
1da177e4 1149
787c72b1
JD
1150 static const char *names[] = {
1151 "w83627hf",
1152 "w83627thf",
1153 "w83697hf",
1154 "w83637hf",
1155 "w83687thf",
1156 };
1157
1158 res = platform_get_resource(pdev, IORESOURCE_IO, 0);
1159 if (!request_region(res->start, WINB_REGION_SIZE, DRVNAME)) {
1160 dev_err(dev, "Failed to request region 0x%lx-0x%lx\n",
1161 (unsigned long)res->start,
1162 (unsigned long)(res->start + WINB_REGION_SIZE - 1));
1da177e4
LT
1163 err = -EBUSY;
1164 goto ERROR0;
1165 }
1166
ba9c2e8d 1167 if (!(data = kzalloc(sizeof(struct w83627hf_data), GFP_KERNEL))) {
1da177e4
LT
1168 err = -ENOMEM;
1169 goto ERROR1;
1170 }
787c72b1
JD
1171 data->addr = res->start;
1172 data->type = sio_data->type;
1173 data->name = names[sio_data->type];
9a61bf63 1174 mutex_init(&data->lock);
9a61bf63 1175 mutex_init(&data->update_lock);
787c72b1 1176 platform_set_drvdata(pdev, data);
1da177e4 1177
1da177e4 1178 /* Initialize the chip */
787c72b1 1179 w83627hf_init_device(pdev);
1da177e4
LT
1180
1181 /* A few vars need to be filled upon startup */
2ca2fcd1
JC
1182 for (i = 0; i <= 2; i++)
1183 data->fan_min[i] = w83627hf_read_value(
1184 data, W83627HF_REG_FAN_MIN(i));
c09c5184 1185 w83627hf_update_fan_div(data);
1da177e4 1186
c1685f61 1187 /* Register common device attributes */
787c72b1 1188 if ((err = sysfs_create_group(&dev->kobj, &w83627hf_group)))
943b0830 1189 goto ERROR3;
1da177e4 1190
c1685f61 1191 /* Register chip-specific device attributes */
787c72b1 1192 if (data->type == w83627hf || data->type == w83697hf)
07584c76
JC
1193 if ((err = device_create_file(dev,
1194 &sensor_dev_attr_in5_input.dev_attr))
1195 || (err = device_create_file(dev,
1196 &sensor_dev_attr_in5_min.dev_attr))
1197 || (err = device_create_file(dev,
1198 &sensor_dev_attr_in5_max.dev_attr))
1199 || (err = device_create_file(dev,
1200 &sensor_dev_attr_in6_input.dev_attr))
1201 || (err = device_create_file(dev,
1202 &sensor_dev_attr_in6_min.dev_attr))
1203 || (err = device_create_file(dev,
1204 &sensor_dev_attr_in6_max.dev_attr))
1205 || (err = device_create_file(dev,
1206 &sensor_dev_attr_pwm1_freq.dev_attr))
1207 || (err = device_create_file(dev,
1208 &sensor_dev_attr_pwm2_freq.dev_attr)))
c1685f61 1209 goto ERROR4;
1da177e4 1210
787c72b1 1211 if (data->type != w83697hf)
07584c76
JC
1212 if ((err = device_create_file(dev,
1213 &sensor_dev_attr_in1_input.dev_attr))
1214 || (err = device_create_file(dev,
1215 &sensor_dev_attr_in1_min.dev_attr))
1216 || (err = device_create_file(dev,
1217 &sensor_dev_attr_in1_max.dev_attr))
1218 || (err = device_create_file(dev,
1219 &sensor_dev_attr_fan3_input.dev_attr))
1220 || (err = device_create_file(dev,
1221 &sensor_dev_attr_fan3_min.dev_attr))
1222 || (err = device_create_file(dev,
1223 &sensor_dev_attr_fan3_div.dev_attr))
1224 || (err = device_create_file(dev,
1225 &sensor_dev_attr_temp3_input.dev_attr))
1226 || (err = device_create_file(dev,
1227 &sensor_dev_attr_temp3_max.dev_attr))
1228 || (err = device_create_file(dev,
1229 &sensor_dev_attr_temp3_max_hyst.dev_attr))
1230 || (err = device_create_file(dev,
1231 &sensor_dev_attr_temp3_type.dev_attr)))
c1685f61
MH
1232 goto ERROR4;
1233
787c72b1 1234 if (data->type != w83697hf && data->vid != 0xff) {
8a665a05
JD
1235 /* Convert VID to voltage based on VRM */
1236 data->vrm = vid_which_vrm();
1237
787c72b1
JD
1238 if ((err = device_create_file(dev, &dev_attr_cpu0_vid))
1239 || (err = device_create_file(dev, &dev_attr_vrm)))
c1685f61 1240 goto ERROR4;
8a665a05 1241 }
1da177e4 1242
787c72b1
JD
1243 if (data->type == w83627thf || data->type == w83637hf
1244 || data->type == w83687thf)
07584c76
JC
1245 if ((err = device_create_file(dev,
1246 &sensor_dev_attr_pwm3.dev_attr)))
c1685f61 1247 goto ERROR4;
1da177e4 1248
1550cb6d 1249 if (data->type == w83637hf || data->type == w83687thf)
07584c76
JC
1250 if ((err = device_create_file(dev,
1251 &sensor_dev_attr_pwm1_freq.dev_attr))
1252 || (err = device_create_file(dev,
1253 &sensor_dev_attr_pwm2_freq.dev_attr))
1254 || (err = device_create_file(dev,
1255 &sensor_dev_attr_pwm3_freq.dev_attr)))
1550cb6d
COM
1256 goto ERROR4;
1257
1beeffe4
TJ
1258 data->hwmon_dev = hwmon_device_register(dev);
1259 if (IS_ERR(data->hwmon_dev)) {
1260 err = PTR_ERR(data->hwmon_dev);
c1685f61
MH
1261 goto ERROR4;
1262 }
1da177e4
LT
1263
1264 return 0;
1265
c1685f61 1266 ERROR4:
787c72b1
JD
1267 sysfs_remove_group(&dev->kobj, &w83627hf_group);
1268 sysfs_remove_group(&dev->kobj, &w83627hf_group_opt);
943b0830 1269 ERROR3:
04a6217d 1270 platform_set_drvdata(pdev, NULL);
1da177e4
LT
1271 kfree(data);
1272 ERROR1:
787c72b1 1273 release_region(res->start, WINB_REGION_SIZE);
1da177e4
LT
1274 ERROR0:
1275 return err;
1276}
1277
787c72b1 1278static int __devexit w83627hf_remove(struct platform_device *pdev)
1da177e4 1279{
787c72b1
JD
1280 struct w83627hf_data *data = platform_get_drvdata(pdev);
1281 struct resource *res;
1da177e4 1282
1beeffe4 1283 hwmon_device_unregister(data->hwmon_dev);
943b0830 1284
787c72b1
JD
1285 sysfs_remove_group(&pdev->dev.kobj, &w83627hf_group);
1286 sysfs_remove_group(&pdev->dev.kobj, &w83627hf_group_opt);
04a6217d 1287 platform_set_drvdata(pdev, NULL);
943b0830 1288 kfree(data);
1da177e4 1289
787c72b1
JD
1290 res = platform_get_resource(pdev, IORESOURCE_IO, 0);
1291 release_region(res->start, WINB_REGION_SIZE);
1292
1da177e4
LT
1293 return 0;
1294}
1295
1296
d58df9cd
JD
1297/* Registers 0x50-0x5f are banked */
1298static inline void w83627hf_set_bank(struct w83627hf_data *data, u16 reg)
1299{
1300 if ((reg & 0x00f0) == 0x50) {
1301 outb_p(W83781D_REG_BANK, data->addr + W83781D_ADDR_REG_OFFSET);
1302 outb_p(reg >> 8, data->addr + W83781D_DATA_REG_OFFSET);
1303 }
1304}
1305
1306/* Not strictly necessary, but play it safe for now */
1307static inline void w83627hf_reset_bank(struct w83627hf_data *data, u16 reg)
1308{
1309 if (reg & 0xff00) {
1310 outb_p(W83781D_REG_BANK, data->addr + W83781D_ADDR_REG_OFFSET);
1311 outb_p(0, data->addr + W83781D_DATA_REG_OFFSET);
1312 }
1313}
1314
787c72b1 1315static int w83627hf_read_value(struct w83627hf_data *data, u16 reg)
1da177e4 1316{
1da177e4
LT
1317 int res, word_sized;
1318
9a61bf63 1319 mutex_lock(&data->lock);
1da177e4
LT
1320 word_sized = (((reg & 0xff00) == 0x100)
1321 || ((reg & 0xff00) == 0x200))
1322 && (((reg & 0x00ff) == 0x50)
1323 || ((reg & 0x00ff) == 0x53)
1324 || ((reg & 0x00ff) == 0x55));
d58df9cd 1325 w83627hf_set_bank(data, reg);
787c72b1
JD
1326 outb_p(reg & 0xff, data->addr + W83781D_ADDR_REG_OFFSET);
1327 res = inb_p(data->addr + W83781D_DATA_REG_OFFSET);
1da177e4
LT
1328 if (word_sized) {
1329 outb_p((reg & 0xff) + 1,
787c72b1 1330 data->addr + W83781D_ADDR_REG_OFFSET);
1da177e4 1331 res =
787c72b1 1332 (res << 8) + inb_p(data->addr +
1da177e4
LT
1333 W83781D_DATA_REG_OFFSET);
1334 }
d58df9cd 1335 w83627hf_reset_bank(data, reg);
9a61bf63 1336 mutex_unlock(&data->lock);
1da177e4
LT
1337 return res;
1338}
1339
787c72b1 1340static int __devinit w83627thf_read_gpio5(struct platform_device *pdev)
1da177e4
LT
1341{
1342 int res = 0xff, sel;
1343
1344 superio_enter();
1345 superio_select(W83627HF_LD_GPIO5);
1346
1347 /* Make sure these GPIO pins are enabled */
1348 if (!(superio_inb(W83627THF_GPIO5_EN) & (1<<3))) {
787c72b1 1349 dev_dbg(&pdev->dev, "GPIO5 disabled, no VID function\n");
1da177e4
LT
1350 goto exit;
1351 }
1352
1353 /* Make sure the pins are configured for input
1354 There must be at least five (VRM 9), and possibly 6 (VRM 10) */
dd149c52 1355 sel = superio_inb(W83627THF_GPIO5_IOSR) & 0x3f;
1da177e4 1356 if ((sel & 0x1f) != 0x1f) {
787c72b1 1357 dev_dbg(&pdev->dev, "GPIO5 not configured for VID "
1da177e4
LT
1358 "function\n");
1359 goto exit;
1360 }
1361
787c72b1 1362 dev_info(&pdev->dev, "Reading VID from GPIO5\n");
1da177e4
LT
1363 res = superio_inb(W83627THF_GPIO5_DR) & sel;
1364
1365exit:
1366 superio_exit();
1367 return res;
1368}
1369
787c72b1 1370static int __devinit w83687thf_read_vid(struct platform_device *pdev)
c2db6ce1
JD
1371{
1372 int res = 0xff;
1373
1374 superio_enter();
1375 superio_select(W83627HF_LD_HWM);
1376
1377 /* Make sure these GPIO pins are enabled */
1378 if (!(superio_inb(W83687THF_VID_EN) & (1 << 2))) {
787c72b1 1379 dev_dbg(&pdev->dev, "VID disabled, no VID function\n");
c2db6ce1
JD
1380 goto exit;
1381 }
1382
1383 /* Make sure the pins are configured for input */
1384 if (!(superio_inb(W83687THF_VID_CFG) & (1 << 4))) {
787c72b1 1385 dev_dbg(&pdev->dev, "VID configured as output, "
c2db6ce1
JD
1386 "no VID function\n");
1387 goto exit;
1388 }
1389
1390 res = superio_inb(W83687THF_VID_DATA) & 0x3f;
1391
1392exit:
1393 superio_exit();
1394 return res;
1395}
1396
787c72b1 1397static int w83627hf_write_value(struct w83627hf_data *data, u16 reg, u16 value)
1da177e4 1398{
1da177e4
LT
1399 int word_sized;
1400
9a61bf63 1401 mutex_lock(&data->lock);
1da177e4
LT
1402 word_sized = (((reg & 0xff00) == 0x100)
1403 || ((reg & 0xff00) == 0x200))
1404 && (((reg & 0x00ff) == 0x53)
1405 || ((reg & 0x00ff) == 0x55));
d58df9cd 1406 w83627hf_set_bank(data, reg);
787c72b1 1407 outb_p(reg & 0xff, data->addr + W83781D_ADDR_REG_OFFSET);
1da177e4
LT
1408 if (word_sized) {
1409 outb_p(value >> 8,
787c72b1 1410 data->addr + W83781D_DATA_REG_OFFSET);
1da177e4 1411 outb_p((reg & 0xff) + 1,
787c72b1 1412 data->addr + W83781D_ADDR_REG_OFFSET);
1da177e4
LT
1413 }
1414 outb_p(value & 0xff,
787c72b1 1415 data->addr + W83781D_DATA_REG_OFFSET);
d58df9cd 1416 w83627hf_reset_bank(data, reg);
9a61bf63 1417 mutex_unlock(&data->lock);
1da177e4
LT
1418 return 0;
1419}
1420
787c72b1 1421static void __devinit w83627hf_init_device(struct platform_device *pdev)
1da177e4 1422{
787c72b1 1423 struct w83627hf_data *data = platform_get_drvdata(pdev);
1da177e4 1424 int i;
d27c37c0 1425 enum chips type = data->type;
1da177e4
LT
1426 u8 tmp;
1427
2251cf1a
JD
1428 if (reset) {
1429 /* Resetting the chip has been the default for a long time,
1430 but repeatedly caused problems (fans going to full
1431 speed...) so it is now optional. It might even go away if
1432 nobody reports it as being useful, as I see very little
1433 reason why this would be needed at all. */
787c72b1 1434 dev_info(&pdev->dev, "If reset=1 solved a problem you were "
2251cf1a
JD
1435 "having, please report!\n");
1436
1da177e4 1437 /* save this register */
787c72b1 1438 i = w83627hf_read_value(data, W83781D_REG_BEEP_CONFIG);
1da177e4
LT
1439 /* Reset all except Watchdog values and last conversion values
1440 This sets fan-divs to 2, among others */
787c72b1 1441 w83627hf_write_value(data, W83781D_REG_CONFIG, 0x80);
1da177e4
LT
1442 /* Restore the register and disable power-on abnormal beep.
1443 This saves FAN 1/2/3 input/output values set by BIOS. */
787c72b1 1444 w83627hf_write_value(data, W83781D_REG_BEEP_CONFIG, i | 0x80);
1da177e4
LT
1445 /* Disable master beep-enable (reset turns it on).
1446 Individual beeps should be reset to off but for some reason
1447 disabling this bit helps some people not get beeped */
787c72b1 1448 w83627hf_write_value(data, W83781D_REG_BEEP_INTS2, 0);
1da177e4
LT
1449 }
1450
1451 /* Minimize conflicts with other winbond i2c-only clients... */
1452 /* disable i2c subclients... how to disable main i2c client?? */
1453 /* force i2c address to relatively uncommon address */
787c72b1
JD
1454 w83627hf_write_value(data, W83781D_REG_I2C_SUBADDR, 0x89);
1455 w83627hf_write_value(data, W83781D_REG_I2C_ADDR, force_i2c);
1da177e4
LT
1456
1457 /* Read VID only once */
d27c37c0 1458 if (type == w83627hf || type == w83637hf) {
787c72b1
JD
1459 int lo = w83627hf_read_value(data, W83781D_REG_VID_FANDIV);
1460 int hi = w83627hf_read_value(data, W83781D_REG_CHIPID);
1da177e4 1461 data->vid = (lo & 0x0f) | ((hi & 0x01) << 4);
d27c37c0 1462 } else if (type == w83627thf) {
787c72b1 1463 data->vid = w83627thf_read_gpio5(pdev);
d27c37c0 1464 } else if (type == w83687thf) {
787c72b1 1465 data->vid = w83687thf_read_vid(pdev);
1da177e4
LT
1466 }
1467
1468 /* Read VRM & OVT Config only once */
d27c37c0 1469 if (type == w83627thf || type == w83637hf || type == w83687thf) {
1da177e4 1470 data->vrm_ovt =
787c72b1 1471 w83627hf_read_value(data, W83627THF_REG_VRM_OVT_CFG);
1da177e4
LT
1472 }
1473
787c72b1 1474 tmp = w83627hf_read_value(data, W83781D_REG_SCFG1);
1da177e4
LT
1475 for (i = 1; i <= 3; i++) {
1476 if (!(tmp & BIT_SCFG1[i - 1])) {
b26f9330 1477 data->sens[i - 1] = 4;
1da177e4
LT
1478 } else {
1479 if (w83627hf_read_value
787c72b1 1480 (data,
1da177e4
LT
1481 W83781D_REG_SCFG2) & BIT_SCFG2[i - 1])
1482 data->sens[i - 1] = 1;
1483 else
1484 data->sens[i - 1] = 2;
1485 }
1486 if ((type == w83697hf) && (i == 2))
1487 break;
1488 }
1489
1490 if(init) {
1491 /* Enable temp2 */
df48ed80 1492 tmp = w83627hf_read_value(data, W83627HF_REG_TEMP2_CONFIG);
1da177e4 1493 if (tmp & 0x01) {
787c72b1 1494 dev_warn(&pdev->dev, "Enabling temp2, readings "
1da177e4 1495 "might not make sense\n");
df48ed80 1496 w83627hf_write_value(data, W83627HF_REG_TEMP2_CONFIG,
1da177e4
LT
1497 tmp & 0xfe);
1498 }
1499
1500 /* Enable temp3 */
1501 if (type != w83697hf) {
787c72b1 1502 tmp = w83627hf_read_value(data,
df48ed80 1503 W83627HF_REG_TEMP3_CONFIG);
1da177e4 1504 if (tmp & 0x01) {
787c72b1 1505 dev_warn(&pdev->dev, "Enabling temp3, "
1da177e4 1506 "readings might not make sense\n");
787c72b1 1507 w83627hf_write_value(data,
df48ed80 1508 W83627HF_REG_TEMP3_CONFIG, tmp & 0xfe);
1da177e4
LT
1509 }
1510 }
1da177e4
LT
1511 }
1512
1513 /* Start monitoring */
787c72b1
JD
1514 w83627hf_write_value(data, W83781D_REG_CONFIG,
1515 (w83627hf_read_value(data,
1da177e4
LT
1516 W83781D_REG_CONFIG) & 0xf7)
1517 | 0x01);
1518}
1519
c09c5184
JD
1520static void w83627hf_update_fan_div(struct w83627hf_data *data)
1521{
1522 int reg;
1523
1524 reg = w83627hf_read_value(data, W83781D_REG_VID_FANDIV);
1525 data->fan_div[0] = (reg >> 4) & 0x03;
1526 data->fan_div[1] = (reg >> 6) & 0x03;
1527 if (data->type != w83697hf) {
1528 data->fan_div[2] = (w83627hf_read_value(data,
1529 W83781D_REG_PIN) >> 6) & 0x03;
1530 }
1531 reg = w83627hf_read_value(data, W83781D_REG_VBAT);
1532 data->fan_div[0] |= (reg >> 3) & 0x04;
1533 data->fan_div[1] |= (reg >> 4) & 0x04;
1534 if (data->type != w83697hf)
1535 data->fan_div[2] |= (reg >> 5) & 0x04;
1536}
1537
1da177e4
LT
1538static struct w83627hf_data *w83627hf_update_device(struct device *dev)
1539{
787c72b1 1540 struct w83627hf_data *data = dev_get_drvdata(dev);
df48ed80 1541 int i, num_temps = (data->type == w83697hf) ? 2 : 3;
1da177e4 1542
9a61bf63 1543 mutex_lock(&data->update_lock);
1da177e4
LT
1544
1545 if (time_after(jiffies, data->last_updated + HZ + HZ / 2)
1546 || !data->valid) {
1547 for (i = 0; i <= 8; i++) {
1548 /* skip missing sensors */
1549 if (((data->type == w83697hf) && (i == 1)) ||
c2db6ce1 1550 ((data->type != w83627hf && data->type != w83697hf)
4a1c4447 1551 && (i == 5 || i == 6)))
1da177e4
LT
1552 continue;
1553 data->in[i] =
787c72b1 1554 w83627hf_read_value(data, W83781D_REG_IN(i));
1da177e4 1555 data->in_min[i] =
787c72b1 1556 w83627hf_read_value(data,
1da177e4
LT
1557 W83781D_REG_IN_MIN(i));
1558 data->in_max[i] =
787c72b1 1559 w83627hf_read_value(data,
1da177e4
LT
1560 W83781D_REG_IN_MAX(i));
1561 }
2ca2fcd1
JC
1562 for (i = 0; i <= 2; i++) {
1563 data->fan[i] =
1564 w83627hf_read_value(data, W83627HF_REG_FAN(i));
1565 data->fan_min[i] =
787c72b1 1566 w83627hf_read_value(data,
2ca2fcd1 1567 W83627HF_REG_FAN_MIN(i));
1da177e4 1568 }
07584c76 1569 for (i = 0; i <= 2; i++) {
787c72b1 1570 u8 tmp = w83627hf_read_value(data,
1da177e4
LT
1571 W836X7HF_REG_PWM(data->type, i));
1572 /* bits 0-3 are reserved in 627THF */
1573 if (data->type == w83627thf)
1574 tmp &= 0xf0;
07584c76
JC
1575 data->pwm[i] = tmp;
1576 if (i == 1 &&
1577 (data->type == w83627hf || data->type == w83697hf))
1da177e4
LT
1578 break;
1579 }
1550cb6d
COM
1580 if (data->type == w83627hf) {
1581 u8 tmp = w83627hf_read_value(data,
1582 W83627HF_REG_PWM_FREQ);
1583 data->pwm_freq[0] = tmp & 0x07;
1584 data->pwm_freq[1] = (tmp >> 4) & 0x07;
1585 } else if (data->type != w83627thf) {
1586 for (i = 1; i <= 3; i++) {
1587 data->pwm_freq[i - 1] =
1588 w83627hf_read_value(data,
1589 W83637HF_REG_PWM_FREQ[i - 1]);
1590 if (i == 2 && (data->type == w83697hf))
1591 break;
1592 }
1593 }
df48ed80
JC
1594 for (i = 0; i < num_temps; i++) {
1595 data->temp[i] = w83627hf_read_value(
1596 data, w83627hf_reg_temp[i]);
1597 data->temp_max[i] = w83627hf_read_value(
1598 data, w83627hf_reg_temp_over[i]);
1599 data->temp_max_hyst[i] = w83627hf_read_value(
1600 data, w83627hf_reg_temp_hyst[i]);
1da177e4
LT
1601 }
1602
c09c5184
JD
1603 w83627hf_update_fan_div(data);
1604
1da177e4 1605 data->alarms =
787c72b1
JD
1606 w83627hf_read_value(data, W83781D_REG_ALARM1) |
1607 (w83627hf_read_value(data, W83781D_REG_ALARM2) << 8) |
1608 (w83627hf_read_value(data, W83781D_REG_ALARM3) << 16);
1609 i = w83627hf_read_value(data, W83781D_REG_BEEP_INTS2);
1da177e4
LT
1610 data->beep_enable = i >> 7;
1611 data->beep_mask = ((i & 0x7f) << 8) |
787c72b1
JD
1612 w83627hf_read_value(data, W83781D_REG_BEEP_INTS1) |
1613 w83627hf_read_value(data, W83781D_REG_BEEP_INTS3) << 16;
1da177e4
LT
1614 data->last_updated = jiffies;
1615 data->valid = 1;
1616 }
1617
9a61bf63 1618 mutex_unlock(&data->update_lock);
1da177e4
LT
1619
1620 return data;
1621}
1622
787c72b1
JD
1623static int __init w83627hf_device_add(unsigned short address,
1624 const struct w83627hf_sio_data *sio_data)
1625{
1626 struct resource res = {
1627 .start = address + WINB_REGION_OFFSET,
1628 .end = address + WINB_REGION_OFFSET + WINB_REGION_SIZE - 1,
1629 .name = DRVNAME,
1630 .flags = IORESOURCE_IO,
1631 };
1632 int err;
1633
1634 pdev = platform_device_alloc(DRVNAME, address);
1635 if (!pdev) {
1636 err = -ENOMEM;
1637 printk(KERN_ERR DRVNAME ": Device allocation failed\n");
1638 goto exit;
1639 }
1640
1641 err = platform_device_add_resources(pdev, &res, 1);
1642 if (err) {
1643 printk(KERN_ERR DRVNAME ": Device resource addition failed "
1644 "(%d)\n", err);
1645 goto exit_device_put;
1646 }
1647
2df6d811
JD
1648 err = platform_device_add_data(pdev, sio_data,
1649 sizeof(struct w83627hf_sio_data));
1650 if (err) {
787c72b1
JD
1651 printk(KERN_ERR DRVNAME ": Platform data allocation failed\n");
1652 goto exit_device_put;
1653 }
787c72b1
JD
1654
1655 err = platform_device_add(pdev);
1656 if (err) {
1657 printk(KERN_ERR DRVNAME ": Device addition failed (%d)\n",
1658 err);
1659 goto exit_device_put;
1660 }
1661
1662 return 0;
1663
1664exit_device_put:
1665 platform_device_put(pdev);
1666exit:
1667 return err;
1668}
1669
1da177e4
LT
1670static int __init sensors_w83627hf_init(void)
1671{
787c72b1
JD
1672 int err;
1673 unsigned short address;
1674 struct w83627hf_sio_data sio_data;
1675
1676 if (w83627hf_find(0x2e, &address, &sio_data)
1677 && w83627hf_find(0x4e, &address, &sio_data))
1da177e4 1678 return -ENODEV;
1da177e4 1679
787c72b1
JD
1680 err = platform_driver_register(&w83627hf_driver);
1681 if (err)
1682 goto exit;
1683
1684 /* Sets global pdev as a side effect */
1685 err = w83627hf_device_add(address, &sio_data);
1686 if (err)
1687 goto exit_driver;
1688
1689 return 0;
1690
1691exit_driver:
1692 platform_driver_unregister(&w83627hf_driver);
1693exit:
1694 return err;
1da177e4
LT
1695}
1696
1697static void __exit sensors_w83627hf_exit(void)
1698{
787c72b1
JD
1699 platform_device_unregister(pdev);
1700 platform_driver_unregister(&w83627hf_driver);
1da177e4
LT
1701}
1702
1703MODULE_AUTHOR("Frodo Looijaard <frodol@dds.nl>, "
1704 "Philip Edelbrock <phil@netroedge.com>, "
1705 "and Mark Studebaker <mdsxyz123@yahoo.com>");
1706MODULE_DESCRIPTION("W83627HF driver");
1707MODULE_LICENSE("GPL");
1708
1709module_init(sensors_w83627hf_init);
1710module_exit(sensors_w83627hf_exit);