[mirror_ubuntu-focal-kernel.git] / drivers / i2c / busses / i2c-nforce2.c

// SPDX-License-Identifier: GPL-2.0-or-later
/*
    SMBus driver for nVidia nForce2 MCP

    Added nForce3 Pro 150  Thomas Leibold <thomas@plx.com>,
	Ported to 2.5 Patrick Dreker <patrick@dreker.de>,
    Copyright (c) 2003  Hans-Frieder Vogt <hfvogt@arcor.de>,
    Based on
    SMBus 2.0 driver for AMD-8111 IO-Hub
    Copyright (c) 2002 Vojtech Pavlik

*/

/*
    SUPPORTED DEVICES		PCI ID
    nForce2 MCP			0064
    nForce2 Ultra 400 MCP	0084
    nForce3 Pro150 MCP		00D4
    nForce3 250Gb MCP		00E4
    nForce4 MCP			0052
    nForce4 MCP-04		0034
    nForce MCP51		0264
    nForce MCP55		0368
    nForce MCP61		03EB
    nForce MCP65		0446
    nForce MCP67		0542
    nForce MCP73		07D8
    nForce MCP78S		0752
    nForce MCP79		0AA2

    This driver supports the 2 SMBuses that are included in the MCP of the
    nForce2/3/4/5xx chipsets.
*/

/* Note: we assume there can only be one nForce2, with two SMBus interfaces */

#include <linux/module.h>
#include <linux/pci.h>
#include <linux/kernel.h>
#include <linux/stddef.h>
#include <linux/ioport.h>
#include <linux/i2c.h>
#include <linux/delay.h>
#include <linux/dmi.h>
#include <linux/acpi.h>
#include <linux/slab.h>
#include <linux/io.h>

MODULE_LICENSE("GPL");
MODULE_AUTHOR("Hans-Frieder Vogt <hfvogt@gmx.net>");
MODULE_DESCRIPTION("nForce2/3/4/5xx SMBus driver");


struct nforce2_smbus {
	struct i2c_adapter adapter;
	int base;
	int size;
	int blockops;
	int can_abort;
};


/*
 * nVidia nForce2 SMBus control register definitions
 * (Newer incarnations use standard BARs 4 and 5 instead)
 */
#define NFORCE_PCI_SMB1	0x50
#define NFORCE_PCI_SMB2	0x54


/*
 * ACPI 2.0 chapter 13 SMBus 2.0 EC register model
 */
#define NVIDIA_SMB_PRTCL	(smbus->base + 0x00)	/* protocol, PEC */
#define NVIDIA_SMB_STS		(smbus->base + 0x01)	/* status */
#define NVIDIA_SMB_ADDR		(smbus->base + 0x02)	/* address */
#define NVIDIA_SMB_CMD		(smbus->base + 0x03)	/* command */
#define NVIDIA_SMB_DATA		(smbus->base + 0x04)	/* 32 data registers */
#define NVIDIA_SMB_BCNT		(smbus->base + 0x24)	/* number of data
							   bytes */
#define NVIDIA_SMB_STATUS_ABRT	(smbus->base + 0x3c)	/* register used to
							   check the status of
							   the abort command */
#define NVIDIA_SMB_CTRL		(smbus->base + 0x3e)	/* control register */

#define NVIDIA_SMB_STATUS_ABRT_STS	0x01		/* Bit to notify that
							   abort succeeded */
#define NVIDIA_SMB_CTRL_ABORT	0x20
#define NVIDIA_SMB_STS_DONE	0x80
#define NVIDIA_SMB_STS_ALRM	0x40
#define NVIDIA_SMB_STS_RES	0x20
#define NVIDIA_SMB_STS_STATUS	0x1f

#define NVIDIA_SMB_PRTCL_WRITE			0x00
#define NVIDIA_SMB_PRTCL_READ			0x01
#define NVIDIA_SMB_PRTCL_QUICK			0x02
#define NVIDIA_SMB_PRTCL_BYTE			0x04
#define NVIDIA_SMB_PRTCL_BYTE_DATA		0x06
#define NVIDIA_SMB_PRTCL_WORD_DATA		0x08
#define NVIDIA_SMB_PRTCL_BLOCK_DATA		0x0a
#define NVIDIA_SMB_PRTCL_PEC			0x80

/* Misc definitions */
#define MAX_TIMEOUT	100

/* We disable the second SMBus channel on these boards */
static const struct dmi_system_id nforce2_dmi_blacklist2[] = {
	{
		.ident = "DFI Lanparty NF4 Expert",
		.matches = {
			DMI_MATCH(DMI_BOARD_VENDOR, "DFI Corp,LTD"),
			DMI_MATCH(DMI_BOARD_NAME, "LP UT NF4 Expert"),
		},
	},
	{ }
};

static struct pci_driver nforce2_driver;

/* For multiplexing support, we need a global reference to the 1st
   SMBus channel */
#if IS_ENABLED(CONFIG_I2C_NFORCE2_S4985)
struct i2c_adapter *nforce2_smbus;
EXPORT_SYMBOL_GPL(nforce2_smbus);

static void nforce2_set_reference(struct i2c_adapter *adap)
{
	nforce2_smbus = adap;
}
#else
static inline void nforce2_set_reference(struct i2c_adapter *adap) { }
#endif

static void nforce2_abort(struct i2c_adapter *adap)
{
	struct nforce2_smbus *smbus = adap->algo_data;
	int timeout = 0;
	unsigned char temp;

	dev_dbg(&adap->dev, "Aborting current transaction\n");

	outb_p(NVIDIA_SMB_CTRL_ABORT, NVIDIA_SMB_CTRL);
	do {
		msleep(1);
		temp = inb_p(NVIDIA_SMB_STATUS_ABRT);
	} while (!(temp & NVIDIA_SMB_STATUS_ABRT_STS) &&
			(timeout++ < MAX_TIMEOUT));
	if (!(temp & NVIDIA_SMB_STATUS_ABRT_STS))
		dev_err(&adap->dev, "Can't reset the smbus\n");
	outb_p(NVIDIA_SMB_STATUS_ABRT_STS, NVIDIA_SMB_STATUS_ABRT);
}

static int nforce2_check_status(struct i2c_adapter *adap)
{
	struct nforce2_smbus *smbus = adap->algo_data;
	int timeout = 0;
	unsigned char temp;

	do {
		msleep(1);
		temp = inb_p(NVIDIA_SMB_STS);
	} while ((!temp) && (timeout++ < MAX_TIMEOUT));

	if (timeout > MAX_TIMEOUT) {
		dev_dbg(&adap->dev, "SMBus Timeout!\n");
		if (smbus->can_abort)
			nforce2_abort(adap);
		return -ETIMEDOUT;
	}
	if (!(temp & NVIDIA_SMB_STS_DONE) || (temp & NVIDIA_SMB_STS_STATUS)) {
		dev_dbg(&adap->dev, "Transaction failed (0x%02x)!\n", temp);
		return -EIO;
	}
	return 0;
}

/* Return negative errno on error */
static s32 nforce2_access(struct i2c_adapter *adap, u16 addr,
		unsigned short flags, char read_write,
		u8 command, int size, union i2c_smbus_data *data)
{
	struct nforce2_smbus *smbus = adap->algo_data;
	unsigned char protocol, pec;
	u8 len;
	int i, status;

	protocol = (read_write == I2C_SMBUS_READ) ? NVIDIA_SMB_PRTCL_READ :
		NVIDIA_SMB_PRTCL_WRITE;
	pec = (flags & I2C_CLIENT_PEC) ? NVIDIA_SMB_PRTCL_PEC : 0;

	switch (size) {
	case I2C_SMBUS_QUICK:
		protocol |= NVIDIA_SMB_PRTCL_QUICK;
		read_write = I2C_SMBUS_WRITE;
		break;

	case I2C_SMBUS_BYTE:
		if (read_write == I2C_SMBUS_WRITE)
			outb_p(command, NVIDIA_SMB_CMD);
		protocol |= NVIDIA_SMB_PRTCL_BYTE;
		break;

	case I2C_SMBUS_BYTE_DATA:
		outb_p(command, NVIDIA_SMB_CMD);
		if (read_write == I2C_SMBUS_WRITE)
			outb_p(data->byte, NVIDIA_SMB_DATA);
		protocol |= NVIDIA_SMB_PRTCL_BYTE_DATA;
		break;

	case I2C_SMBUS_WORD_DATA:
		outb_p(command, NVIDIA_SMB_CMD);
		if (read_write == I2C_SMBUS_WRITE) {
			outb_p(data->word, NVIDIA_SMB_DATA);
			outb_p(data->word >> 8, NVIDIA_SMB_DATA + 1);
		}
		protocol |= NVIDIA_SMB_PRTCL_WORD_DATA | pec;
		break;

	case I2C_SMBUS_BLOCK_DATA:
		outb_p(command, NVIDIA_SMB_CMD);
		if (read_write == I2C_SMBUS_WRITE) {
			len = data->block[0];
			if ((len == 0) || (len > I2C_SMBUS_BLOCK_MAX)) {
				dev_err(&adap->dev,
					"Transaction failed (requested block size: %d)\n",
					len);
				return -EINVAL;
			}
			outb_p(len, NVIDIA_SMB_BCNT);
			for (i = 0; i < I2C_SMBUS_BLOCK_MAX; i++)
				outb_p(data->block[i + 1],
				       NVIDIA_SMB_DATA + i);
		}
		protocol |= NVIDIA_SMB_PRTCL_BLOCK_DATA | pec;
		break;

	default:
		dev_err(&adap->dev, "Unsupported transaction %d\n", size);
		return -EOPNOTSUPP;
	}

	outb_p((addr & 0x7f) << 1, NVIDIA_SMB_ADDR);
	outb_p(protocol, NVIDIA_SMB_PRTCL);

	status = nforce2_check_status(adap);
	if (status)
		return status;

	if (read_write == I2C_SMBUS_WRITE)
		return 0;

	switch (size) {
	case I2C_SMBUS_BYTE:
	case I2C_SMBUS_BYTE_DATA:
		data->byte = inb_p(NVIDIA_SMB_DATA);
		break;

	case I2C_SMBUS_WORD_DATA:
		data->word = inb_p(NVIDIA_SMB_DATA) |
			     (inb_p(NVIDIA_SMB_DATA + 1) << 8);
		break;

	case I2C_SMBUS_BLOCK_DATA:
		len = inb_p(NVIDIA_SMB_BCNT);
		if ((len <= 0) || (len > I2C_SMBUS_BLOCK_MAX)) {
			dev_err(&adap->dev,
				"Transaction failed (received block size: 0x%02x)\n",
				len);
			return -EPROTO;
		}
		for (i = 0; i < len; i++)
			data->block[i + 1] = inb_p(NVIDIA_SMB_DATA + i);
		data->block[0] = len;
		break;
	}

	return 0;
}


static u32 nforce2_func(struct i2c_adapter *adapter)
{
	/* other functionality might be possible, but is not tested */
	return I2C_FUNC_SMBUS_QUICK | I2C_FUNC_SMBUS_BYTE |
	       I2C_FUNC_SMBUS_BYTE_DATA | I2C_FUNC_SMBUS_WORD_DATA |
	       I2C_FUNC_SMBUS_PEC |
	       (((struct nforce2_smbus *)adapter->algo_data)->blockops ?
		I2C_FUNC_SMBUS_BLOCK_DATA : 0);
}

static const struct i2c_algorithm smbus_algorithm = {
	.smbus_xfer	= nforce2_access,
	.functionality	= nforce2_func,
};


static const struct pci_device_id nforce2_ids[] = {
	{ PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE2_SMBUS) },
	{ PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE2S_SMBUS) },
	{ PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE3_SMBUS) },
	{ PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE3S_SMBUS) },
	{ PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE4_SMBUS) },
	{ PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP04_SMBUS) },
	{ PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP51_SMBUS) },
	{ PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP55_SMBUS) },
	{ PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP61_SMBUS) },
	{ PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP65_SMBUS) },
	{ PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP67_SMBUS) },
	{ PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP73_SMBUS) },
	{ PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP78S_SMBUS) },
	{ PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP79_SMBUS) },
	{ 0 }
};

MODULE_DEVICE_TABLE(pci, nforce2_ids);


static int nforce2_probe_smb(struct pci_dev *dev, int bar, int alt_reg,
			     struct nforce2_smbus *smbus, const char *name)
{
	int error;

	smbus->base = pci_resource_start(dev, bar);
	if (smbus->base) {
		smbus->size = pci_resource_len(dev, bar);
	} else {
		/* Older incarnations of the device used non-standard BARs */
		u16 iobase;

		if (pci_read_config_word(dev, alt_reg, &iobase)
		    != PCIBIOS_SUCCESSFUL) {
			dev_err(&dev->dev, "Error reading PCI config for %s\n",
				name);
			return -EIO;
		}

		smbus->base = iobase & PCI_BASE_ADDRESS_IO_MASK;
		smbus->size = 64;
	}

	error = acpi_check_region(smbus->base, smbus->size,
				  nforce2_driver.name);
	if (error)
		return error;

	if (!request_region(smbus->base, smbus->size, nforce2_driver.name)) {
		dev_err(&smbus->adapter.dev, "Error requesting region %02x .. %02X for %s\n",
			smbus->base, smbus->base+smbus->size-1, name);
		return -EBUSY;
	}
	smbus->adapter.owner = THIS_MODULE;
	smbus->adapter.class = I2C_CLASS_HWMON | I2C_CLASS_SPD;
	smbus->adapter.algo = &smbus_algorithm;
	smbus->adapter.algo_data = smbus;
	smbus->adapter.dev.parent = &dev->dev;
	snprintf(smbus->adapter.name, sizeof(smbus->adapter.name),
		"SMBus nForce2 adapter at %04x", smbus->base);

	error = i2c_add_adapter(&smbus->adapter);
	if (error) {
		release_region(smbus->base, smbus->size);
		return error;
	}
	dev_info(&smbus->adapter.dev, "nForce2 SMBus adapter at %#x\n",
		smbus->base);
	return 0;
}


static int nforce2_probe(struct pci_dev *dev, const struct pci_device_id *id)
{
	struct nforce2_smbus *smbuses;
	int res1, res2;

	/* we support 2 SMBus adapters */
	smbuses = kcalloc(2, sizeof(struct nforce2_smbus), GFP_KERNEL);
	if (!smbuses)
		return -ENOMEM;
	pci_set_drvdata(dev, smbuses);

	switch (dev->device) {
	case PCI_DEVICE_ID_NVIDIA_NFORCE2_SMBUS:
	case PCI_DEVICE_ID_NVIDIA_NFORCE_MCP51_SMBUS:
	case PCI_DEVICE_ID_NVIDIA_NFORCE_MCP55_SMBUS:
		smbuses[0].blockops = 1;
		smbuses[1].blockops = 1;
		smbuses[0].can_abort = 1;
		smbuses[1].can_abort = 1;
	}

	/* SMBus adapter 1 */
	res1 = nforce2_probe_smb(dev, 4, NFORCE_PCI_SMB1, &smbuses[0], "SMB1");
	if (res1 < 0)
		smbuses[0].base = 0;	/* to have a check value */

	/* SMBus adapter 2 */
	if (dmi_check_system(nforce2_dmi_blacklist2)) {
		dev_err(&dev->dev, "Disabling SMB2 for safety reasons.\n");
		res2 = -EPERM;
		smbuses[1].base = 0;
	} else {
		res2 = nforce2_probe_smb(dev, 5, NFORCE_PCI_SMB2, &smbuses[1],
					 "SMB2");
		if (res2 < 0)
			smbuses[1].base = 0;	/* to have a check value */
	}

	if ((res1 < 0) && (res2 < 0)) {
		/* we did not find even one of the SMBuses, so we give up */
		kfree(smbuses);
		return -ENODEV;
	}

	nforce2_set_reference(&smbuses[0].adapter);
	return 0;
}


static void nforce2_remove(struct pci_dev *dev)
{
	struct nforce2_smbus *smbuses = pci_get_drvdata(dev);

	nforce2_set_reference(NULL);
	if (smbuses[0].base) {
		i2c_del_adapter(&smbuses[0].adapter);
		release_region(smbuses[0].base, smbuses[0].size);
	}
	if (smbuses[1].base) {
		i2c_del_adapter(&smbuses[1].adapter);
		release_region(smbuses[1].base, smbuses[1].size);
	}
	kfree(smbuses);
}

static struct pci_driver nforce2_driver = {
	.name		= "nForce2_smbus",
	.id_table	= nforce2_ids,
	.probe		= nforce2_probe,
	.remove		= nforce2_remove,
};

module_pci_driver(nforce2_driver);
Commit	Line	Data
c942fddf	1	// SPDX-License-Identifier: GPL-2.0-or-later
1da177e4 LT	2	/*
	3	SMBus driver for nVidia nForce2 MCP
	4
	5	Added nForce3 Pro 150 Thomas Leibold <thomas@plx.com>,
	6	Ported to 2.5 Patrick Dreker <patrick@dreker.de>,
	7	Copyright (c) 2003 Hans-Frieder Vogt <hfvogt@arcor.de>,
	8	Based on
	9	SMBus 2.0 driver for AMD-8111 IO-Hub
	10	Copyright (c) 2002 Vojtech Pavlik
	11
1da177e4 LT	12	*/
	13
	14	/*
	15	SUPPORTED DEVICES PCI ID
	16	nForce2 MCP 0064
	17	nForce2 Ultra 400 MCP 0084
	18	nForce3 Pro150 MCP 00D4
	19	nForce3 250Gb MCP 00E4
	20	nForce4 MCP 0052
7c72ccf0	21	nForce4 MCP-04 0034
d2dd14ac JD	22	nForce MCP51 0264
d2dd14ac JD	23	nForce MCP55 0368
f75803de JD	24	nForce MCP61 03EB
f75803de JD	25	nForce MCP65 0446
d2dd14ac JD	26	nForce MCP67 0542
	27	nForce MCP73 07D8
	28	nForce MCP78S 0752
	29	nForce MCP79 0AA2
1da177e4 LT	30
1da177e4 LT	31	This driver supports the 2 SMBuses that are included in the MCP of the
ad04d5c3	32	nForce2/3/4/5xx chipsets.
1da177e4 LT	33	*/
	34
	35	/* Note: we assume there can only be one nForce2, with two SMBus interfaces */
	36
1da177e4 LT	37	#include <linux/module.h>
	38	#include <linux/pci.h>
	39	#include <linux/kernel.h>
	40	#include <linux/stddef.h>
1da177e4	41	#include <linux/ioport.h>
1da177e4 LT	42	#include <linux/i2c.h>
1da177e4 LT	43	#include <linux/delay.h>
08851d6e	44	#include <linux/dmi.h>
54fb4a05	45	#include <linux/acpi.h>
5a0e3ad6	46	#include <linux/slab.h>
21782180	47	#include <linux/io.h>
1da177e4 LT	48
1da177e4 LT	49	MODULE_LICENSE("GPL");
5c38dc89	50	MODULE_AUTHOR("Hans-Frieder Vogt <hfvogt@gmx.net>");
ad04d5c3	51	MODULE_DESCRIPTION("nForce2/3/4/5xx SMBus driver");
1da177e4 LT	52
	53
	54	struct nforce2_smbus {
1da177e4 LT	55	struct i2c_adapter adapter;
	56	int base;
	57	int size;
b53c8221	58	int blockops;
d49584c4	59	int can_abort;
1da177e4 LT	60	};
	61
	62
	63	/*
	64	* nVidia nForce2 SMBus control register definitions
5c7ae658	65	* (Newer incarnations use standard BARs 4 and 5 instead)
1da177e4 LT	66	*/
	67	#define NFORCE_PCI_SMB1 0x50
	68	#define NFORCE_PCI_SMB2 0x54
	69
	70
	71	/*
	72	* ACPI 2.0 chapter 13 SMBus 2.0 EC register model
	73	*/
	74	#define NVIDIA_SMB_PRTCL (smbus->base + 0x00) /* protocol, PEC */
	75	#define NVIDIA_SMB_STS (smbus->base + 0x01) /* status */
	76	#define NVIDIA_SMB_ADDR (smbus->base + 0x02) /* address */
	77	#define NVIDIA_SMB_CMD (smbus->base + 0x03) /* command */
	78	#define NVIDIA_SMB_DATA (smbus->base + 0x04) /* 32 data registers */
b53c8221 OR	79	#define NVIDIA_SMB_BCNT (smbus->base + 0x24) /* number of data
b53c8221 OR	80	bytes */
d49584c4 OR	81	#define NVIDIA_SMB_STATUS_ABRT (smbus->base + 0x3c) /* register used to
	82	check the status of
	83	the abort command */
	84	#define NVIDIA_SMB_CTRL (smbus->base + 0x3e) /* control register */
	85
	86	#define NVIDIA_SMB_STATUS_ABRT_STS 0x01 /* Bit to notify that
	87	abort succeeded */
	88	#define NVIDIA_SMB_CTRL_ABORT 0x20
1da177e4 LT	89	#define NVIDIA_SMB_STS_DONE 0x80
	90	#define NVIDIA_SMB_STS_ALRM 0x40
	91	#define NVIDIA_SMB_STS_RES 0x20
	92	#define NVIDIA_SMB_STS_STATUS 0x1f
	93
	94	#define NVIDIA_SMB_PRTCL_WRITE 0x00
	95	#define NVIDIA_SMB_PRTCL_READ 0x01
	96	#define NVIDIA_SMB_PRTCL_QUICK 0x02
	97	#define NVIDIA_SMB_PRTCL_BYTE 0x04
	98	#define NVIDIA_SMB_PRTCL_BYTE_DATA 0x06
	99	#define NVIDIA_SMB_PRTCL_WORD_DATA 0x08
b53c8221	100	#define NVIDIA_SMB_PRTCL_BLOCK_DATA 0x0a
1da177e4 LT	101	#define NVIDIA_SMB_PRTCL_PEC 0x80
1da177e4 LT	102
41535497 OR	103	/* Misc definitions */
	104	#define MAX_TIMEOUT 100
	105
08851d6e	106	/* We disable the second SMBus channel on these boards */
0b255e92	107	static const struct dmi_system_id nforce2_dmi_blacklist2[] = {
08851d6e JD	108	{
	109	.ident = "DFI Lanparty NF4 Expert",
	110	.matches = {
	111	DMI_MATCH(DMI_BOARD_VENDOR, "DFI Corp,LTD"),
	112	DMI_MATCH(DMI_BOARD_NAME, "LP UT NF4 Expert"),
	113	},
	114	},
	115	{ }
	116	};
	117
d6072f84	118	static struct pci_driver nforce2_driver;
1da177e4	119
279e9024 JD	120	/* For multiplexing support, we need a global reference to the 1st
279e9024 JD	121	SMBus channel */
dd485951	122	#if IS_ENABLED(CONFIG_I2C_NFORCE2_S4985)
279e9024 JD	123	struct i2c_adapter *nforce2_smbus;
	124	EXPORT_SYMBOL_GPL(nforce2_smbus);
	125
	126	static void nforce2_set_reference(struct i2c_adapter *adap)
	127	{
	128	nforce2_smbus = adap;
	129	}
	130	#else
	131	static inline void nforce2_set_reference(struct i2c_adapter *adap) { }
	132	#endif
	133
d49584c4 OR	134	static void nforce2_abort(struct i2c_adapter *adap)
	135	{
	136	struct nforce2_smbus *smbus = adap->algo_data;
	137	int timeout = 0;
	138	unsigned char temp;
	139
	140	dev_dbg(&adap->dev, "Aborting current transaction\n");
	141
	142	outb_p(NVIDIA_SMB_CTRL_ABORT, NVIDIA_SMB_CTRL);
	143	do {
	144	msleep(1);
	145	temp = inb_p(NVIDIA_SMB_STATUS_ABRT);
	146	} while (!(temp & NVIDIA_SMB_STATUS_ABRT_STS) &&
	147	(timeout++ < MAX_TIMEOUT));
	148	if (!(temp & NVIDIA_SMB_STATUS_ABRT_STS))
	149	dev_err(&adap->dev, "Can't reset the smbus\n");
	150	outb_p(NVIDIA_SMB_STATUS_ABRT_STS, NVIDIA_SMB_STATUS_ABRT);
	151	}
	152
41535497 OR	153	static int nforce2_check_status(struct i2c_adapter *adap)
	154	{
	155	struct nforce2_smbus *smbus = adap->algo_data;
	156	int timeout = 0;
	157	unsigned char temp;
	158
	159	do {
	160	msleep(1);
	161	temp = inb_p(NVIDIA_SMB_STS);
	162	} while ((!temp) && (timeout++ < MAX_TIMEOUT));
	163
4ccc28f7	164	if (timeout > MAX_TIMEOUT) {
41535497	165	dev_dbg(&adap->dev, "SMBus Timeout!\n");
d49584c4 OR	166	if (smbus->can_abort)
d49584c4 OR	167	nforce2_abort(adap);
97140342	168	return -ETIMEDOUT;
41535497 OR	169	}
	170	if (!(temp & NVIDIA_SMB_STS_DONE) \|\| (temp & NVIDIA_SMB_STS_STATUS)) {
	171	dev_dbg(&adap->dev, "Transaction failed (0x%02x)!\n", temp);
97140342	172	return -EIO;
41535497 OR	173	}
	174	return 0;
	175	}
	176
97140342	177	/* Return negative errno on error */
5c38dc89	178	static s32 nforce2_access(struct i2c_adapter *adap, u16 addr,
1da177e4	179	unsigned short flags, char read_write,
5c38dc89	180	u8 command, int size, union i2c_smbus_data *data)
1da177e4 LT	181	{
1da177e4 LT	182	struct nforce2_smbus *smbus = adap->algo_data;
41535497	183	unsigned char protocol, pec;
b53c8221	184	u8 len;
97140342	185	int i, status;
1da177e4 LT	186
	187	protocol = (read_write == I2C_SMBUS_READ) ? NVIDIA_SMB_PRTCL_READ :
	188	NVIDIA_SMB_PRTCL_WRITE;
	189	pec = (flags & I2C_CLIENT_PEC) ? NVIDIA_SMB_PRTCL_PEC : 0;
	190
	191	switch (size) {
5c38dc89 LN	192	case I2C_SMBUS_QUICK:
	193	protocol \|= NVIDIA_SMB_PRTCL_QUICK;
	194	read_write = I2C_SMBUS_WRITE;
	195	break;
1da177e4	196
5c38dc89 LN	197	case I2C_SMBUS_BYTE:
5c38dc89 LN	198	if (read_write == I2C_SMBUS_WRITE)
1da177e4	199	outb_p(command, NVIDIA_SMB_CMD);
5c38dc89 LN	200	protocol \|= NVIDIA_SMB_PRTCL_BYTE;
	201	break;
	202
	203	case I2C_SMBUS_BYTE_DATA:
	204	outb_p(command, NVIDIA_SMB_CMD);
	205	if (read_write == I2C_SMBUS_WRITE)
	206	outb_p(data->byte, NVIDIA_SMB_DATA);
	207	protocol \|= NVIDIA_SMB_PRTCL_BYTE_DATA;
	208	break;
	209
	210	case I2C_SMBUS_WORD_DATA:
	211	outb_p(command, NVIDIA_SMB_CMD);
	212	if (read_write == I2C_SMBUS_WRITE) {
	213	outb_p(data->word, NVIDIA_SMB_DATA);
	214	outb_p(data->word >> 8, NVIDIA_SMB_DATA + 1);
	215	}
	216	protocol \|= NVIDIA_SMB_PRTCL_WORD_DATA \| pec;
	217	break;
	218
	219	case I2C_SMBUS_BLOCK_DATA:
	220	outb_p(command, NVIDIA_SMB_CMD);
	221	if (read_write == I2C_SMBUS_WRITE) {
	222	len = data->block[0];
	223	if ((len == 0) \|\| (len > I2C_SMBUS_BLOCK_MAX)) {
	224	dev_err(&adap->dev,
	225	"Transaction failed (requested block size: %d)\n",
	226	len);
	227	return -EINVAL;
b53c8221	228	}
5c38dc89 LN	229	outb_p(len, NVIDIA_SMB_BCNT);
	230	for (i = 0; i < I2C_SMBUS_BLOCK_MAX; i++)
	231	outb_p(data->block[i + 1],
	232	NVIDIA_SMB_DATA + i);
	233	}
	234	protocol \|= NVIDIA_SMB_PRTCL_BLOCK_DATA \| pec;
	235	break;
b53c8221	236
5c38dc89 LN	237	default:
	238	dev_err(&adap->dev, "Unsupported transaction %d\n", size);
	239	return -EOPNOTSUPP;
1da177e4 LT	240	}
	241
	242	outb_p((addr & 0x7f) << 1, NVIDIA_SMB_ADDR);
	243	outb_p(protocol, NVIDIA_SMB_PRTCL);
	244
97140342 DB	245	status = nforce2_check_status(adap);
	246	if (status)
	247	return status;
1da177e4 LT	248
	249	if (read_write == I2C_SMBUS_WRITE)
	250	return 0;
	251
	252	switch (size) {
5c38dc89 LN	253	case I2C_SMBUS_BYTE:
	254	case I2C_SMBUS_BYTE_DATA:
	255	data->byte = inb_p(NVIDIA_SMB_DATA);
	256	break;
	257
	258	case I2C_SMBUS_WORD_DATA:
	259	data->word = inb_p(NVIDIA_SMB_DATA) \|
	260	(inb_p(NVIDIA_SMB_DATA + 1) << 8);
	261	break;
	262
	263	case I2C_SMBUS_BLOCK_DATA:
	264	len = inb_p(NVIDIA_SMB_BCNT);
	265	if ((len <= 0) \|\| (len > I2C_SMBUS_BLOCK_MAX)) {
	266	dev_err(&adap->dev,
	267	"Transaction failed (received block size: 0x%02x)\n",
	268	len);
	269	return -EPROTO;
	270	}
	271	for (i = 0; i < len; i++)
	272	data->block[i + 1] = inb_p(NVIDIA_SMB_DATA + i);
	273	data->block[0] = len;
	274	break;
1da177e4 LT	275	}
	276
	277	return 0;
	278	}
	279
	280
	281	static u32 nforce2_func(struct i2c_adapter *adapter)
	282	{
	283	/* other functionality might be possible, but is not tested */
	284	return I2C_FUNC_SMBUS_QUICK \| I2C_FUNC_SMBUS_BYTE \|
b53c8221	285	I2C_FUNC_SMBUS_BYTE_DATA \| I2C_FUNC_SMBUS_WORD_DATA \|
ac3f5753	286	I2C_FUNC_SMBUS_PEC \|
5c38dc89	287	(((struct nforce2_smbus *)adapter->algo_data)->blockops ?
b53c8221	288	I2C_FUNC_SMBUS_BLOCK_DATA : 0);
1da177e4 LT	289	}
1da177e4 LT	290
92d9d0df	291	static const struct i2c_algorithm smbus_algorithm = {
ad04d5c3 HFV	292	.smbus_xfer = nforce2_access,
	293	.functionality = nforce2_func,
	294	};
	295
1da177e4	296
392debf1	297	static const struct pci_device_id nforce2_ids[] = {
1da177e4 LT	298	{ PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE2_SMBUS) },
	299	{ PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE2S_SMBUS) },
	300	{ PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE3_SMBUS) },
	301	{ PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE3S_SMBUS) },
	302	{ PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE4_SMBUS) },
7c72ccf0	303	{ PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP04_SMBUS) },
5c7ae658 JD	304	{ PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP51_SMBUS) },
5c7ae658 JD	305	{ PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP55_SMBUS) },
f75803de JD	306	{ PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP61_SMBUS) },
f75803de JD	307	{ PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP65_SMBUS) },
d2dd14ac JD	308	{ PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP67_SMBUS) },
	309	{ PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP73_SMBUS) },
	310	{ PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP78S_SMBUS) },
	311	{ PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP79_SMBUS) },
1da177e4 LT	312	{ 0 }
	313	};
	314
5c38dc89	315	MODULE_DEVICE_TABLE(pci, nforce2_ids);
1da177e4 LT	316
1da177e4 LT	317
0b255e92 BP	318	static int nforce2_probe_smb(struct pci_dev *dev, int bar, int alt_reg,
0b255e92 BP	319	struct nforce2_smbus smbus, const char name)
1da177e4	320	{
1da177e4 LT	321	int error;
1da177e4 LT	322
5c7ae658 JD	323	smbus->base = pci_resource_start(dev, bar);
	324	if (smbus->base) {
	325	smbus->size = pci_resource_len(dev, bar);
	326	} else {
	327	/* Older incarnations of the device used non-standard BARs */
	328	u16 iobase;
	329
	330	if (pci_read_config_word(dev, alt_reg, &iobase)
	331	!= PCIBIOS_SUCCESSFUL) {
	332	dev_err(&dev->dev, "Error reading PCI config for %s\n",
	333	name);
97140342	334	return -EIO;
5c7ae658 JD	335	}
	336
	337	smbus->base = iobase & PCI_BASE_ADDRESS_IO_MASK;
ad04d5c3	338	smbus->size = 64;
1da177e4	339	}
1da177e4	340
54fb4a05 JD	341	error = acpi_check_region(smbus->base, smbus->size,
	342	nforce2_driver.name);
	343	if (error)
7c1f59c9	344	return error;
54fb4a05	345
d6072f84	346	if (!request_region(smbus->base, smbus->size, nforce2_driver.name)) {
1da177e4 LT	347	dev_err(&smbus->adapter.dev, "Error requesting region %02x .. %02X for %s\n",
1da177e4 LT	348	smbus->base, smbus->base+smbus->size-1, name);
97140342	349	return -EBUSY;
1da177e4	350	}
ad04d5c3	351	smbus->adapter.owner = THIS_MODULE;
3401b2ff	352	smbus->adapter.class = I2C_CLASS_HWMON \| I2C_CLASS_SPD;
ad04d5c3	353	smbus->adapter.algo = &smbus_algorithm;
1da177e4 LT	354	smbus->adapter.algo_data = smbus;
1da177e4 LT	355	smbus->adapter.dev.parent = &dev->dev;
2096b956	356	snprintf(smbus->adapter.name, sizeof(smbus->adapter.name),
1da177e4 LT	357	"SMBus nForce2 adapter at %04x", smbus->base);
	358
	359	error = i2c_add_adapter(&smbus->adapter);
	360	if (error) {
1da177e4	361	release_region(smbus->base, smbus->size);
97140342	362	return error;
1da177e4	363	}
5c38dc89 LN	364	dev_info(&smbus->adapter.dev, "nForce2 SMBus adapter at %#x\n",
5c38dc89 LN	365	smbus->base);
1da177e4 LT	366	return 0;
	367	}
	368
	369
0b255e92	370	static int nforce2_probe(struct pci_dev dev, const struct pci_device_id id)
1da177e4 LT	371	{
	372	struct nforce2_smbus *smbuses;
	373	int res1, res2;
	374
	375	/* we support 2 SMBus adapters */
6396bb22	376	smbuses = kcalloc(2, sizeof(struct nforce2_smbus), GFP_KERNEL);
5c38dc89	377	if (!smbuses)
1da177e4	378	return -ENOMEM;
1da177e4 LT	379	pci_set_drvdata(dev, smbuses);
1da177e4 LT	380
5c38dc89	381	switch (dev->device) {
541b6a7a	382	case PCI_DEVICE_ID_NVIDIA_NFORCE2_SMBUS:
b53c8221 OR	383	case PCI_DEVICE_ID_NVIDIA_NFORCE_MCP51_SMBUS:
	384	case PCI_DEVICE_ID_NVIDIA_NFORCE_MCP55_SMBUS:
	385	smbuses[0].blockops = 1;
	386	smbuses[1].blockops = 1;
d49584c4 OR	387	smbuses[0].can_abort = 1;
d49584c4 OR	388	smbuses[1].can_abort = 1;
b53c8221 OR	389	}
b53c8221 OR	390
1da177e4	391	/* SMBus adapter 1 */
5c7ae658	392	res1 = nforce2_probe_smb(dev, 4, NFORCE_PCI_SMB1, &smbuses[0], "SMB1");
7c4fda1a	393	if (res1 < 0)
1da177e4	394	smbuses[0].base = 0; /* to have a check value */
7c4fda1a	395
5c7ae658	396	/* SMBus adapter 2 */
08851d6e JD	397	if (dmi_check_system(nforce2_dmi_blacklist2)) {
	398	dev_err(&dev->dev, "Disabling SMB2 for safety reasons.\n");
	399	res2 = -EPERM;
	400	smbuses[1].base = 0;
	401	} else {
	402	res2 = nforce2_probe_smb(dev, 5, NFORCE_PCI_SMB2, &smbuses[1],
	403	"SMB2");
7c4fda1a	404	if (res2 < 0)
08851d6e	405	smbuses[1].base = 0; /* to have a check value */
1da177e4	406	}
7c4fda1a	407
1da177e4 LT	408	if ((res1 < 0) && (res2 < 0)) {
	409	/* we did not find even one of the SMBuses, so we give up */
	410	kfree(smbuses);
	411	return -ENODEV;
	412	}
	413
279e9024	414	nforce2_set_reference(&smbuses[0].adapter);
1da177e4 LT	415	return 0;
	416	}
	417
	418
0b255e92	419	static void nforce2_remove(struct pci_dev *dev)
1da177e4	420	{
b18a5c80	421	struct nforce2_smbus *smbuses = pci_get_drvdata(dev);
1da177e4	422
279e9024	423	nforce2_set_reference(NULL);
1da177e4 LT	424	if (smbuses[0].base) {
	425	i2c_del_adapter(&smbuses[0].adapter);
	426	release_region(smbuses[0].base, smbuses[0].size);
	427	}
	428	if (smbuses[1].base) {
	429	i2c_del_adapter(&smbuses[1].adapter);
	430	release_region(smbuses[1].base, smbuses[1].size);
	431	}
	432	kfree(smbuses);
	433	}
	434
	435	static struct pci_driver nforce2_driver = {
	436	.name = "nForce2_smbus",
	437	.id_table = nforce2_ids,
	438	.probe = nforce2_probe,
0b255e92	439	.remove = nforce2_remove,
1da177e4 LT	440	};
1da177e4 LT	441
56f21788	442	module_pci_driver(nforce2_driver);