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Commit | Line | Data |
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1da177e4 | 1 | /* |
1da177e4 LT |
2 | Copyright (c) 1998 - 2002 Frodo Looijaard <frodol@dds.nl> and |
3 | Philip Edelbrock <phil@netroedge.com> | |
4 | ||
5 | This program is free software; you can redistribute it and/or modify | |
6 | it under the terms of the GNU General Public License as published by | |
7 | the Free Software Foundation; either version 2 of the License, or | |
8 | (at your option) any later version. | |
9 | ||
10 | This program is distributed in the hope that it will be useful, | |
11 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
13 | GNU General Public License for more details. | |
1da177e4 LT |
14 | */ |
15 | ||
16 | /* | |
17 | Supports: | |
18 | Intel PIIX4, 440MX | |
506a8b6c | 19 | Serverworks OSB4, CSB5, CSB6, HT-1000, HT-1100 |
2a2f7404 | 20 | ATI IXP200, IXP300, IXP400, SB600, SB700/SP5100, SB800 |
032f708b | 21 | AMD Hudson-2, ML, CZ |
1da177e4 LT |
22 | SMSC Victory66 |
23 | ||
2a2f7404 AA |
24 | Note: we assume there can only be one device, with one or more |
25 | SMBus interfaces. | |
2fee61d2 CF |
26 | The device can register multiple i2c_adapters (up to PIIX4_MAX_ADAPTERS). |
27 | For devices supporting multiple ports the i2c_adapter should provide | |
28 | an i2c_algorithm to access them. | |
1da177e4 LT |
29 | */ |
30 | ||
1da177e4 LT |
31 | #include <linux/module.h> |
32 | #include <linux/moduleparam.h> | |
33 | #include <linux/pci.h> | |
34 | #include <linux/kernel.h> | |
35 | #include <linux/delay.h> | |
36 | #include <linux/stddef.h> | |
1da177e4 LT |
37 | #include <linux/ioport.h> |
38 | #include <linux/i2c.h> | |
c415b303 | 39 | #include <linux/slab.h> |
1da177e4 | 40 | #include <linux/dmi.h> |
54fb4a05 | 41 | #include <linux/acpi.h> |
21782180 | 42 | #include <linux/io.h> |
2fee61d2 | 43 | #include <linux/mutex.h> |
1da177e4 LT |
44 | |
45 | ||
1da177e4 LT |
46 | /* PIIX4 SMBus address offsets */ |
47 | #define SMBHSTSTS (0 + piix4_smba) | |
48 | #define SMBHSLVSTS (1 + piix4_smba) | |
49 | #define SMBHSTCNT (2 + piix4_smba) | |
50 | #define SMBHSTCMD (3 + piix4_smba) | |
51 | #define SMBHSTADD (4 + piix4_smba) | |
52 | #define SMBHSTDAT0 (5 + piix4_smba) | |
53 | #define SMBHSTDAT1 (6 + piix4_smba) | |
54 | #define SMBBLKDAT (7 + piix4_smba) | |
55 | #define SMBSLVCNT (8 + piix4_smba) | |
56 | #define SMBSHDWCMD (9 + piix4_smba) | |
57 | #define SMBSLVEVT (0xA + piix4_smba) | |
58 | #define SMBSLVDAT (0xC + piix4_smba) | |
59 | ||
60 | /* count for request_region */ | |
f43128c7 | 61 | #define SMBIOSIZE 9 |
1da177e4 LT |
62 | |
63 | /* PCI Address Constants */ | |
64 | #define SMBBA 0x090 | |
65 | #define SMBHSTCFG 0x0D2 | |
66 | #define SMBSLVC 0x0D3 | |
67 | #define SMBSHDW1 0x0D4 | |
68 | #define SMBSHDW2 0x0D5 | |
69 | #define SMBREV 0x0D6 | |
70 | ||
71 | /* Other settings */ | |
72 | #define MAX_TIMEOUT 500 | |
73 | #define ENABLE_INT9 0 | |
74 | ||
75 | /* PIIX4 constants */ | |
76 | #define PIIX4_QUICK 0x00 | |
77 | #define PIIX4_BYTE 0x04 | |
78 | #define PIIX4_BYTE_DATA 0x08 | |
79 | #define PIIX4_WORD_DATA 0x0C | |
80 | #define PIIX4_BLOCK_DATA 0x14 | |
81 | ||
ca2061e1 CF |
82 | /* Multi-port constants */ |
83 | #define PIIX4_MAX_ADAPTERS 4 | |
84 | ||
2fee61d2 CF |
85 | /* SB800 constants */ |
86 | #define SB800_PIIX4_SMB_IDX 0xcd6 | |
87 | ||
88fa2dfb RRD |
88 | #define KERNCZ_IMC_IDX 0x3e |
89 | #define KERNCZ_IMC_DATA 0x3f | |
90 | ||
6befa3fd JD |
91 | /* |
92 | * SB800 port is selected by bits 2:1 of the smb_en register (0x2c) | |
93 | * or the smb_sel register (0x2e), depending on bit 0 of register 0x2f. | |
94 | * Hudson-2/Bolton port is always selected by bits 2:1 of register 0x2f. | |
95 | */ | |
2fee61d2 | 96 | #define SB800_PIIX4_PORT_IDX 0x2c |
6befa3fd JD |
97 | #define SB800_PIIX4_PORT_IDX_ALT 0x2e |
98 | #define SB800_PIIX4_PORT_IDX_SEL 0x2f | |
2fee61d2 | 99 | #define SB800_PIIX4_PORT_IDX_MASK 0x06 |
0fe16195 GR |
100 | #define SB800_PIIX4_PORT_IDX_SHIFT 1 |
101 | ||
102 | /* On kerncz, SmBus0Sel is at bit 20:19 of PMx00 DecodeEn */ | |
103 | #define SB800_PIIX4_PORT_IDX_KERNCZ 0x02 | |
104 | #define SB800_PIIX4_PORT_IDX_MASK_KERNCZ 0x18 | |
105 | #define SB800_PIIX4_PORT_IDX_SHIFT_KERNCZ 3 | |
2fee61d2 | 106 | |
1da177e4 LT |
107 | /* insmod parameters */ |
108 | ||
109 | /* If force is set to anything different from 0, we forcibly enable the | |
110 | PIIX4. DANGEROUS! */ | |
60507095 | 111 | static int force; |
1da177e4 LT |
112 | module_param (force, int, 0); |
113 | MODULE_PARM_DESC(force, "Forcibly enable the PIIX4. DANGEROUS!"); | |
114 | ||
115 | /* If force_addr is set to anything different from 0, we forcibly enable | |
116 | the PIIX4 at the given address. VERY DANGEROUS! */ | |
60507095 | 117 | static int force_addr; |
c78babcc | 118 | module_param_hw(force_addr, int, ioport, 0); |
1da177e4 LT |
119 | MODULE_PARM_DESC(force_addr, |
120 | "Forcibly enable the PIIX4 at the given address. " | |
121 | "EXTREMELY DANGEROUS!"); | |
122 | ||
b1c1759c | 123 | static int srvrworks_csb5_delay; |
d6072f84 | 124 | static struct pci_driver piix4_driver; |
1da177e4 | 125 | |
0b255e92 | 126 | static const struct dmi_system_id piix4_dmi_blacklist[] = { |
c2fc54fc JD |
127 | { |
128 | .ident = "Sapphire AM2RD790", | |
129 | .matches = { | |
130 | DMI_MATCH(DMI_BOARD_VENDOR, "SAPPHIRE Inc."), | |
131 | DMI_MATCH(DMI_BOARD_NAME, "PC-AM2RD790"), | |
132 | }, | |
133 | }, | |
134 | { | |
135 | .ident = "DFI Lanparty UT 790FX", | |
136 | .matches = { | |
137 | DMI_MATCH(DMI_BOARD_VENDOR, "DFI Inc."), | |
138 | DMI_MATCH(DMI_BOARD_NAME, "LP UT 790FX"), | |
139 | }, | |
140 | }, | |
141 | { } | |
142 | }; | |
143 | ||
144 | /* The IBM entry is in a separate table because we only check it | |
145 | on Intel-based systems */ | |
0b255e92 | 146 | static const struct dmi_system_id piix4_dmi_ibm[] = { |
1da177e4 LT |
147 | { |
148 | .ident = "IBM", | |
149 | .matches = { DMI_MATCH(DMI_SYS_VENDOR, "IBM"), }, | |
150 | }, | |
151 | { }, | |
152 | }; | |
153 | ||
6befa3fd JD |
154 | /* |
155 | * SB800 globals | |
156 | * piix4_mutex_sb800 protects piix4_port_sel_sb800 and the pair | |
157 | * of I/O ports at SB800_PIIX4_SMB_IDX. | |
158 | */ | |
a28e3517 | 159 | static DEFINE_MUTEX(piix4_mutex_sb800); |
6befa3fd | 160 | static u8 piix4_port_sel_sb800; |
0fe16195 GR |
161 | static u8 piix4_port_mask_sb800; |
162 | static u8 piix4_port_shift_sb800; | |
725d2e3f | 163 | static const char *piix4_main_port_names_sb800[PIIX4_MAX_ADAPTERS] = { |
52795f6f | 164 | " port 0", " port 2", " port 3", " port 4" |
725d2e3f | 165 | }; |
52795f6f | 166 | static const char *piix4_aux_port_name_sb800 = " port 1"; |
725d2e3f | 167 | |
14a8086d AA |
168 | struct i2c_piix4_adapdata { |
169 | unsigned short smba; | |
2fee61d2 CF |
170 | |
171 | /* SB800 */ | |
172 | bool sb800_main; | |
88fa2dfb | 173 | bool notify_imc; |
33f5ccc3 | 174 | u8 port; /* Port number, shifted */ |
14a8086d AA |
175 | }; |
176 | ||
0b255e92 BP |
177 | static int piix4_setup(struct pci_dev *PIIX4_dev, |
178 | const struct pci_device_id *id) | |
1da177e4 LT |
179 | { |
180 | unsigned char temp; | |
14a8086d | 181 | unsigned short piix4_smba; |
1da177e4 | 182 | |
b1c1759c DM |
183 | if ((PIIX4_dev->vendor == PCI_VENDOR_ID_SERVERWORKS) && |
184 | (PIIX4_dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB5)) | |
185 | srvrworks_csb5_delay = 1; | |
186 | ||
c2fc54fc JD |
187 | /* On some motherboards, it was reported that accessing the SMBus |
188 | caused severe hardware problems */ | |
189 | if (dmi_check_system(piix4_dmi_blacklist)) { | |
190 | dev_err(&PIIX4_dev->dev, | |
191 | "Accessing the SMBus on this system is unsafe!\n"); | |
192 | return -EPERM; | |
193 | } | |
194 | ||
1da177e4 | 195 | /* Don't access SMBus on IBM systems which get corrupted eeproms */ |
c2fc54fc | 196 | if (dmi_check_system(piix4_dmi_ibm) && |
1da177e4 | 197 | PIIX4_dev->vendor == PCI_VENDOR_ID_INTEL) { |
f9ba6c04 | 198 | dev_err(&PIIX4_dev->dev, "IBM system detected; this module " |
1da177e4 LT |
199 | "may corrupt your serial eeprom! Refusing to load " |
200 | "module!\n"); | |
201 | return -EPERM; | |
202 | } | |
203 | ||
204 | /* Determine the address of the SMBus areas */ | |
205 | if (force_addr) { | |
206 | piix4_smba = force_addr & 0xfff0; | |
207 | force = 0; | |
208 | } else { | |
209 | pci_read_config_word(PIIX4_dev, SMBBA, &piix4_smba); | |
210 | piix4_smba &= 0xfff0; | |
211 | if(piix4_smba == 0) { | |
fa63cd56 | 212 | dev_err(&PIIX4_dev->dev, "SMBus base address " |
1da177e4 LT |
213 | "uninitialized - upgrade BIOS or use " |
214 | "force_addr=0xaddr\n"); | |
215 | return -ENODEV; | |
216 | } | |
217 | } | |
218 | ||
54fb4a05 | 219 | if (acpi_check_region(piix4_smba, SMBIOSIZE, piix4_driver.name)) |
18669eab | 220 | return -ENODEV; |
54fb4a05 | 221 | |
d6072f84 | 222 | if (!request_region(piix4_smba, SMBIOSIZE, piix4_driver.name)) { |
fa63cd56 | 223 | dev_err(&PIIX4_dev->dev, "SMBus region 0x%x already in use!\n", |
1da177e4 | 224 | piix4_smba); |
fa63cd56 | 225 | return -EBUSY; |
1da177e4 LT |
226 | } |
227 | ||
228 | pci_read_config_byte(PIIX4_dev, SMBHSTCFG, &temp); | |
229 | ||
1da177e4 LT |
230 | /* If force_addr is set, we program the new address here. Just to make |
231 | sure, we disable the PIIX4 first. */ | |
232 | if (force_addr) { | |
233 | pci_write_config_byte(PIIX4_dev, SMBHSTCFG, temp & 0xfe); | |
234 | pci_write_config_word(PIIX4_dev, SMBBA, piix4_smba); | |
235 | pci_write_config_byte(PIIX4_dev, SMBHSTCFG, temp | 0x01); | |
236 | dev_info(&PIIX4_dev->dev, "WARNING: SMBus interface set to " | |
237 | "new address %04x!\n", piix4_smba); | |
238 | } else if ((temp & 1) == 0) { | |
239 | if (force) { | |
240 | /* This should never need to be done, but has been | |
241 | * noted that many Dell machines have the SMBus | |
242 | * interface on the PIIX4 disabled!? NOTE: This assumes | |
243 | * I/O space and other allocations WERE done by the | |
244 | * Bios! Don't complain if your hardware does weird | |
245 | * things after enabling this. :') Check for Bios | |
246 | * updates before resorting to this. | |
247 | */ | |
248 | pci_write_config_byte(PIIX4_dev, SMBHSTCFG, | |
249 | temp | 1); | |
8117e41e JP |
250 | dev_notice(&PIIX4_dev->dev, |
251 | "WARNING: SMBus interface has been FORCEFULLY ENABLED!\n"); | |
1da177e4 LT |
252 | } else { |
253 | dev_err(&PIIX4_dev->dev, | |
66f8a8ff | 254 | "SMBus Host Controller not enabled!\n"); |
1da177e4 | 255 | release_region(piix4_smba, SMBIOSIZE); |
1da177e4 LT |
256 | return -ENODEV; |
257 | } | |
258 | } | |
259 | ||
54aaa1ca | 260 | if (((temp & 0x0E) == 8) || ((temp & 0x0E) == 2)) |
66f8a8ff | 261 | dev_dbg(&PIIX4_dev->dev, "Using IRQ for SMBus\n"); |
1da177e4 | 262 | else if ((temp & 0x0E) == 0) |
66f8a8ff | 263 | dev_dbg(&PIIX4_dev->dev, "Using SMI# for SMBus\n"); |
1da177e4 LT |
264 | else |
265 | dev_err(&PIIX4_dev->dev, "Illegal Interrupt configuration " | |
266 | "(or code out of date)!\n"); | |
267 | ||
268 | pci_read_config_byte(PIIX4_dev, SMBREV, &temp); | |
fa63cd56 JD |
269 | dev_info(&PIIX4_dev->dev, |
270 | "SMBus Host Controller at 0x%x, revision %d\n", | |
271 | piix4_smba, temp); | |
1da177e4 | 272 | |
14a8086d | 273 | return piix4_smba; |
1da177e4 LT |
274 | } |
275 | ||
0b255e92 | 276 | static int piix4_setup_sb800(struct pci_dev *PIIX4_dev, |
a94dd00f | 277 | const struct pci_device_id *id, u8 aux) |
87e1960e | 278 | { |
14a8086d | 279 | unsigned short piix4_smba; |
6befa3fd | 280 | u8 smba_en_lo, smba_en_hi, smb_en, smb_en_status, port_sel; |
032f708b | 281 | u8 i2ccfg, i2ccfg_offset = 0x10; |
87e1960e | 282 | |
3806e94b | 283 | /* SB800 and later SMBus does not support forcing address */ |
87e1960e | 284 | if (force || force_addr) { |
3806e94b | 285 | dev_err(&PIIX4_dev->dev, "SMBus does not support " |
87e1960e SH |
286 | "forcing address!\n"); |
287 | return -EINVAL; | |
288 | } | |
289 | ||
290 | /* Determine the address of the SMBus areas */ | |
032f708b SH |
291 | if ((PIIX4_dev->vendor == PCI_VENDOR_ID_AMD && |
292 | PIIX4_dev->device == PCI_DEVICE_ID_AMD_HUDSON2_SMBUS && | |
293 | PIIX4_dev->revision >= 0x41) || | |
294 | (PIIX4_dev->vendor == PCI_VENDOR_ID_AMD && | |
bcb29994 | 295 | PIIX4_dev->device == PCI_DEVICE_ID_AMD_KERNCZ_SMBUS && |
032f708b SH |
296 | PIIX4_dev->revision >= 0x49)) |
297 | smb_en = 0x00; | |
298 | else | |
299 | smb_en = (aux) ? 0x28 : 0x2c; | |
a94dd00f | 300 | |
a28e3517 | 301 | mutex_lock(&piix4_mutex_sb800); |
2fee61d2 CF |
302 | outb_p(smb_en, SB800_PIIX4_SMB_IDX); |
303 | smba_en_lo = inb_p(SB800_PIIX4_SMB_IDX + 1); | |
304 | outb_p(smb_en + 1, SB800_PIIX4_SMB_IDX); | |
305 | smba_en_hi = inb_p(SB800_PIIX4_SMB_IDX + 1); | |
a28e3517 | 306 | mutex_unlock(&piix4_mutex_sb800); |
87e1960e | 307 | |
032f708b SH |
308 | if (!smb_en) { |
309 | smb_en_status = smba_en_lo & 0x10; | |
310 | piix4_smba = smba_en_hi << 8; | |
311 | if (aux) | |
312 | piix4_smba |= 0x20; | |
313 | } else { | |
314 | smb_en_status = smba_en_lo & 0x01; | |
315 | piix4_smba = ((smba_en_hi << 8) | smba_en_lo) & 0xffe0; | |
316 | } | |
317 | ||
318 | if (!smb_en_status) { | |
87e1960e | 319 | dev_err(&PIIX4_dev->dev, |
66f8a8ff | 320 | "SMBus Host Controller not enabled!\n"); |
87e1960e SH |
321 | return -ENODEV; |
322 | } | |
323 | ||
87e1960e | 324 | if (acpi_check_region(piix4_smba, SMBIOSIZE, piix4_driver.name)) |
18669eab | 325 | return -ENODEV; |
87e1960e SH |
326 | |
327 | if (!request_region(piix4_smba, SMBIOSIZE, piix4_driver.name)) { | |
328 | dev_err(&PIIX4_dev->dev, "SMBus region 0x%x already in use!\n", | |
329 | piix4_smba); | |
330 | return -EBUSY; | |
331 | } | |
332 | ||
a94dd00f RM |
333 | /* Aux SMBus does not support IRQ information */ |
334 | if (aux) { | |
335 | dev_info(&PIIX4_dev->dev, | |
85fd0fe6 SH |
336 | "Auxiliary SMBus Host Controller at 0x%x\n", |
337 | piix4_smba); | |
a94dd00f RM |
338 | return piix4_smba; |
339 | } | |
340 | ||
87e1960e SH |
341 | /* Request the SMBus I2C bus config region */ |
342 | if (!request_region(piix4_smba + i2ccfg_offset, 1, "i2ccfg")) { | |
343 | dev_err(&PIIX4_dev->dev, "SMBus I2C bus config region " | |
344 | "0x%x already in use!\n", piix4_smba + i2ccfg_offset); | |
345 | release_region(piix4_smba, SMBIOSIZE); | |
87e1960e SH |
346 | return -EBUSY; |
347 | } | |
348 | i2ccfg = inb_p(piix4_smba + i2ccfg_offset); | |
349 | release_region(piix4_smba + i2ccfg_offset, 1); | |
350 | ||
351 | if (i2ccfg & 1) | |
66f8a8ff | 352 | dev_dbg(&PIIX4_dev->dev, "Using IRQ for SMBus\n"); |
87e1960e | 353 | else |
66f8a8ff | 354 | dev_dbg(&PIIX4_dev->dev, "Using SMI# for SMBus\n"); |
87e1960e SH |
355 | |
356 | dev_info(&PIIX4_dev->dev, | |
357 | "SMBus Host Controller at 0x%x, revision %d\n", | |
358 | piix4_smba, i2ccfg >> 4); | |
359 | ||
6befa3fd JD |
360 | /* Find which register is used for port selection */ |
361 | if (PIIX4_dev->vendor == PCI_VENDOR_ID_AMD) { | |
0fe16195 GR |
362 | switch (PIIX4_dev->device) { |
363 | case PCI_DEVICE_ID_AMD_KERNCZ_SMBUS: | |
364 | piix4_port_sel_sb800 = SB800_PIIX4_PORT_IDX_KERNCZ; | |
365 | piix4_port_mask_sb800 = SB800_PIIX4_PORT_IDX_MASK_KERNCZ; | |
366 | piix4_port_shift_sb800 = SB800_PIIX4_PORT_IDX_SHIFT_KERNCZ; | |
367 | break; | |
368 | case PCI_DEVICE_ID_AMD_HUDSON2_SMBUS: | |
369 | default: | |
370 | piix4_port_sel_sb800 = SB800_PIIX4_PORT_IDX_ALT; | |
371 | piix4_port_mask_sb800 = SB800_PIIX4_PORT_IDX_MASK; | |
372 | piix4_port_shift_sb800 = SB800_PIIX4_PORT_IDX_SHIFT; | |
373 | break; | |
374 | } | |
6befa3fd JD |
375 | } else { |
376 | mutex_lock(&piix4_mutex_sb800); | |
377 | outb_p(SB800_PIIX4_PORT_IDX_SEL, SB800_PIIX4_SMB_IDX); | |
378 | port_sel = inb_p(SB800_PIIX4_SMB_IDX + 1); | |
379 | piix4_port_sel_sb800 = (port_sel & 0x01) ? | |
380 | SB800_PIIX4_PORT_IDX_ALT : | |
381 | SB800_PIIX4_PORT_IDX; | |
0fe16195 GR |
382 | piix4_port_mask_sb800 = SB800_PIIX4_PORT_IDX_MASK; |
383 | piix4_port_shift_sb800 = SB800_PIIX4_PORT_IDX_SHIFT; | |
6befa3fd JD |
384 | mutex_unlock(&piix4_mutex_sb800); |
385 | } | |
386 | ||
387 | dev_info(&PIIX4_dev->dev, | |
388 | "Using register 0x%02x for SMBus port selection\n", | |
389 | (unsigned int)piix4_port_sel_sb800); | |
390 | ||
14a8086d | 391 | return piix4_smba; |
87e1960e SH |
392 | } |
393 | ||
0b255e92 BP |
394 | static int piix4_setup_aux(struct pci_dev *PIIX4_dev, |
395 | const struct pci_device_id *id, | |
396 | unsigned short base_reg_addr) | |
2a2f7404 AA |
397 | { |
398 | /* Set up auxiliary SMBus controllers found on some | |
399 | * AMD chipsets e.g. SP5100 (SB700 derivative) */ | |
400 | ||
401 | unsigned short piix4_smba; | |
402 | ||
403 | /* Read address of auxiliary SMBus controller */ | |
404 | pci_read_config_word(PIIX4_dev, base_reg_addr, &piix4_smba); | |
405 | if ((piix4_smba & 1) == 0) { | |
406 | dev_dbg(&PIIX4_dev->dev, | |
407 | "Auxiliary SMBus controller not enabled\n"); | |
408 | return -ENODEV; | |
409 | } | |
410 | ||
411 | piix4_smba &= 0xfff0; | |
412 | if (piix4_smba == 0) { | |
413 | dev_dbg(&PIIX4_dev->dev, | |
414 | "Auxiliary SMBus base address uninitialized\n"); | |
415 | return -ENODEV; | |
416 | } | |
417 | ||
418 | if (acpi_check_region(piix4_smba, SMBIOSIZE, piix4_driver.name)) | |
419 | return -ENODEV; | |
420 | ||
421 | if (!request_region(piix4_smba, SMBIOSIZE, piix4_driver.name)) { | |
422 | dev_err(&PIIX4_dev->dev, "Auxiliary SMBus region 0x%x " | |
423 | "already in use!\n", piix4_smba); | |
424 | return -EBUSY; | |
425 | } | |
426 | ||
427 | dev_info(&PIIX4_dev->dev, | |
428 | "Auxiliary SMBus Host Controller at 0x%x\n", | |
429 | piix4_smba); | |
430 | ||
431 | return piix4_smba; | |
432 | } | |
433 | ||
e154bf6f | 434 | static int piix4_transaction(struct i2c_adapter *piix4_adapter) |
1da177e4 | 435 | { |
e154bf6f AA |
436 | struct i2c_piix4_adapdata *adapdata = i2c_get_adapdata(piix4_adapter); |
437 | unsigned short piix4_smba = adapdata->smba; | |
1da177e4 LT |
438 | int temp; |
439 | int result = 0; | |
440 | int timeout = 0; | |
441 | ||
e154bf6f | 442 | dev_dbg(&piix4_adapter->dev, "Transaction (pre): CNT=%02x, CMD=%02x, " |
1da177e4 LT |
443 | "ADD=%02x, DAT0=%02x, DAT1=%02x\n", inb_p(SMBHSTCNT), |
444 | inb_p(SMBHSTCMD), inb_p(SMBHSTADD), inb_p(SMBHSTDAT0), | |
445 | inb_p(SMBHSTDAT1)); | |
446 | ||
447 | /* Make sure the SMBus host is ready to start transmitting */ | |
448 | if ((temp = inb_p(SMBHSTSTS)) != 0x00) { | |
e154bf6f | 449 | dev_dbg(&piix4_adapter->dev, "SMBus busy (%02x). " |
541e6a02 | 450 | "Resetting...\n", temp); |
1da177e4 LT |
451 | outb_p(temp, SMBHSTSTS); |
452 | if ((temp = inb_p(SMBHSTSTS)) != 0x00) { | |
e154bf6f | 453 | dev_err(&piix4_adapter->dev, "Failed! (%02x)\n", temp); |
97140342 | 454 | return -EBUSY; |
1da177e4 | 455 | } else { |
e154bf6f | 456 | dev_dbg(&piix4_adapter->dev, "Successful!\n"); |
1da177e4 LT |
457 | } |
458 | } | |
459 | ||
460 | /* start the transaction by setting bit 6 */ | |
461 | outb_p(inb(SMBHSTCNT) | 0x040, SMBHSTCNT); | |
462 | ||
463 | /* We will always wait for a fraction of a second! (See PIIX4 docs errata) */ | |
b1c1759c DM |
464 | if (srvrworks_csb5_delay) /* Extra delay for SERVERWORKS_CSB5 */ |
465 | msleep(2); | |
466 | else | |
467 | msleep(1); | |
468 | ||
b6a31950 | 469 | while ((++timeout < MAX_TIMEOUT) && |
b1c1759c | 470 | ((temp = inb_p(SMBHSTSTS)) & 0x01)) |
1da177e4 | 471 | msleep(1); |
1da177e4 LT |
472 | |
473 | /* If the SMBus is still busy, we give up */ | |
b6a31950 | 474 | if (timeout == MAX_TIMEOUT) { |
e154bf6f | 475 | dev_err(&piix4_adapter->dev, "SMBus Timeout!\n"); |
97140342 | 476 | result = -ETIMEDOUT; |
1da177e4 LT |
477 | } |
478 | ||
479 | if (temp & 0x10) { | |
97140342 | 480 | result = -EIO; |
e154bf6f | 481 | dev_err(&piix4_adapter->dev, "Error: Failed bus transaction\n"); |
1da177e4 LT |
482 | } |
483 | ||
484 | if (temp & 0x08) { | |
97140342 | 485 | result = -EIO; |
e154bf6f | 486 | dev_dbg(&piix4_adapter->dev, "Bus collision! SMBus may be " |
1da177e4 LT |
487 | "locked until next hard reset. (sorry!)\n"); |
488 | /* Clock stops and slave is stuck in mid-transmission */ | |
489 | } | |
490 | ||
491 | if (temp & 0x04) { | |
97140342 | 492 | result = -ENXIO; |
e154bf6f | 493 | dev_dbg(&piix4_adapter->dev, "Error: no response!\n"); |
1da177e4 LT |
494 | } |
495 | ||
496 | if (inb_p(SMBHSTSTS) != 0x00) | |
497 | outb_p(inb(SMBHSTSTS), SMBHSTSTS); | |
498 | ||
499 | if ((temp = inb_p(SMBHSTSTS)) != 0x00) { | |
e154bf6f | 500 | dev_err(&piix4_adapter->dev, "Failed reset at end of " |
1da177e4 LT |
501 | "transaction (%02x)\n", temp); |
502 | } | |
e154bf6f | 503 | dev_dbg(&piix4_adapter->dev, "Transaction (post): CNT=%02x, CMD=%02x, " |
1da177e4 LT |
504 | "ADD=%02x, DAT0=%02x, DAT1=%02x\n", inb_p(SMBHSTCNT), |
505 | inb_p(SMBHSTCMD), inb_p(SMBHSTADD), inb_p(SMBHSTDAT0), | |
506 | inb_p(SMBHSTDAT1)); | |
507 | return result; | |
508 | } | |
509 | ||
97140342 | 510 | /* Return negative errno on error. */ |
1da177e4 LT |
511 | static s32 piix4_access(struct i2c_adapter * adap, u16 addr, |
512 | unsigned short flags, char read_write, | |
513 | u8 command, int size, union i2c_smbus_data * data) | |
514 | { | |
14a8086d AA |
515 | struct i2c_piix4_adapdata *adapdata = i2c_get_adapdata(adap); |
516 | unsigned short piix4_smba = adapdata->smba; | |
1da177e4 | 517 | int i, len; |
97140342 | 518 | int status; |
1da177e4 LT |
519 | |
520 | switch (size) { | |
1da177e4 | 521 | case I2C_SMBUS_QUICK: |
fa63cd56 | 522 | outb_p((addr << 1) | read_write, |
1da177e4 LT |
523 | SMBHSTADD); |
524 | size = PIIX4_QUICK; | |
525 | break; | |
526 | case I2C_SMBUS_BYTE: | |
fa63cd56 | 527 | outb_p((addr << 1) | read_write, |
1da177e4 LT |
528 | SMBHSTADD); |
529 | if (read_write == I2C_SMBUS_WRITE) | |
530 | outb_p(command, SMBHSTCMD); | |
531 | size = PIIX4_BYTE; | |
532 | break; | |
533 | case I2C_SMBUS_BYTE_DATA: | |
fa63cd56 | 534 | outb_p((addr << 1) | read_write, |
1da177e4 LT |
535 | SMBHSTADD); |
536 | outb_p(command, SMBHSTCMD); | |
537 | if (read_write == I2C_SMBUS_WRITE) | |
538 | outb_p(data->byte, SMBHSTDAT0); | |
539 | size = PIIX4_BYTE_DATA; | |
540 | break; | |
541 | case I2C_SMBUS_WORD_DATA: | |
fa63cd56 | 542 | outb_p((addr << 1) | read_write, |
1da177e4 LT |
543 | SMBHSTADD); |
544 | outb_p(command, SMBHSTCMD); | |
545 | if (read_write == I2C_SMBUS_WRITE) { | |
546 | outb_p(data->word & 0xff, SMBHSTDAT0); | |
547 | outb_p((data->word & 0xff00) >> 8, SMBHSTDAT1); | |
548 | } | |
549 | size = PIIX4_WORD_DATA; | |
550 | break; | |
551 | case I2C_SMBUS_BLOCK_DATA: | |
fa63cd56 | 552 | outb_p((addr << 1) | read_write, |
1da177e4 LT |
553 | SMBHSTADD); |
554 | outb_p(command, SMBHSTCMD); | |
555 | if (read_write == I2C_SMBUS_WRITE) { | |
556 | len = data->block[0]; | |
fa63cd56 JD |
557 | if (len == 0 || len > I2C_SMBUS_BLOCK_MAX) |
558 | return -EINVAL; | |
1da177e4 | 559 | outb_p(len, SMBHSTDAT0); |
d7a4c763 | 560 | inb_p(SMBHSTCNT); /* Reset SMBBLKDAT */ |
1da177e4 LT |
561 | for (i = 1; i <= len; i++) |
562 | outb_p(data->block[i], SMBBLKDAT); | |
563 | } | |
564 | size = PIIX4_BLOCK_DATA; | |
565 | break; | |
ac7fc4fb JD |
566 | default: |
567 | dev_warn(&adap->dev, "Unsupported transaction %d\n", size); | |
568 | return -EOPNOTSUPP; | |
1da177e4 LT |
569 | } |
570 | ||
571 | outb_p((size & 0x1C) + (ENABLE_INT9 & 1), SMBHSTCNT); | |
572 | ||
e154bf6f | 573 | status = piix4_transaction(adap); |
97140342 DB |
574 | if (status) |
575 | return status; | |
1da177e4 LT |
576 | |
577 | if ((read_write == I2C_SMBUS_WRITE) || (size == PIIX4_QUICK)) | |
578 | return 0; | |
579 | ||
580 | ||
581 | switch (size) { | |
3578a075 | 582 | case PIIX4_BYTE: |
1da177e4 LT |
583 | case PIIX4_BYTE_DATA: |
584 | data->byte = inb_p(SMBHSTDAT0); | |
585 | break; | |
586 | case PIIX4_WORD_DATA: | |
587 | data->word = inb_p(SMBHSTDAT0) + (inb_p(SMBHSTDAT1) << 8); | |
588 | break; | |
589 | case PIIX4_BLOCK_DATA: | |
590 | data->block[0] = inb_p(SMBHSTDAT0); | |
fa63cd56 JD |
591 | if (data->block[0] == 0 || data->block[0] > I2C_SMBUS_BLOCK_MAX) |
592 | return -EPROTO; | |
d7a4c763 | 593 | inb_p(SMBHSTCNT); /* Reset SMBBLKDAT */ |
1da177e4 LT |
594 | for (i = 1; i <= data->block[0]; i++) |
595 | data->block[i] = inb_p(SMBBLKDAT); | |
596 | break; | |
597 | } | |
598 | return 0; | |
599 | } | |
600 | ||
88fa2dfb RRD |
601 | static uint8_t piix4_imc_read(uint8_t idx) |
602 | { | |
603 | outb_p(idx, KERNCZ_IMC_IDX); | |
604 | return inb_p(KERNCZ_IMC_DATA); | |
605 | } | |
606 | ||
607 | static void piix4_imc_write(uint8_t idx, uint8_t value) | |
608 | { | |
609 | outb_p(idx, KERNCZ_IMC_IDX); | |
610 | outb_p(value, KERNCZ_IMC_DATA); | |
611 | } | |
612 | ||
613 | static int piix4_imc_sleep(void) | |
614 | { | |
615 | int timeout = MAX_TIMEOUT; | |
616 | ||
617 | if (!request_muxed_region(KERNCZ_IMC_IDX, 2, "smbus_kerncz_imc")) | |
618 | return -EBUSY; | |
619 | ||
620 | /* clear response register */ | |
621 | piix4_imc_write(0x82, 0x00); | |
622 | /* request ownership flag */ | |
623 | piix4_imc_write(0x83, 0xB4); | |
624 | /* kick off IMC Mailbox command 96 */ | |
625 | piix4_imc_write(0x80, 0x96); | |
626 | ||
627 | while (timeout--) { | |
628 | if (piix4_imc_read(0x82) == 0xfa) { | |
629 | release_region(KERNCZ_IMC_IDX, 2); | |
630 | return 0; | |
631 | } | |
632 | usleep_range(1000, 2000); | |
633 | } | |
634 | ||
635 | release_region(KERNCZ_IMC_IDX, 2); | |
636 | return -ETIMEDOUT; | |
637 | } | |
638 | ||
639 | static void piix4_imc_wakeup(void) | |
640 | { | |
641 | int timeout = MAX_TIMEOUT; | |
642 | ||
643 | if (!request_muxed_region(KERNCZ_IMC_IDX, 2, "smbus_kerncz_imc")) | |
644 | return; | |
645 | ||
646 | /* clear response register */ | |
647 | piix4_imc_write(0x82, 0x00); | |
648 | /* release ownership flag */ | |
649 | piix4_imc_write(0x83, 0xB5); | |
650 | /* kick off IMC Mailbox command 96 */ | |
651 | piix4_imc_write(0x80, 0x96); | |
652 | ||
653 | while (timeout--) { | |
654 | if (piix4_imc_read(0x82) == 0xfa) | |
655 | break; | |
656 | usleep_range(1000, 2000); | |
657 | } | |
658 | ||
659 | release_region(KERNCZ_IMC_IDX, 2); | |
660 | } | |
661 | ||
2fee61d2 CF |
662 | /* |
663 | * Handles access to multiple SMBus ports on the SB800. | |
664 | * The port is selected by bits 2:1 of the smb_en register (0x2c). | |
665 | * Returns negative errno on error. | |
666 | * | |
667 | * Note: The selected port must be returned to the initial selection to avoid | |
668 | * problems on certain systems. | |
669 | */ | |
670 | static s32 piix4_access_sb800(struct i2c_adapter *adap, u16 addr, | |
671 | unsigned short flags, char read_write, | |
672 | u8 command, int size, union i2c_smbus_data *data) | |
673 | { | |
674 | struct i2c_piix4_adapdata *adapdata = i2c_get_adapdata(adap); | |
701dc207 RRD |
675 | unsigned short piix4_smba = adapdata->smba; |
676 | int retries = MAX_TIMEOUT; | |
677 | int smbslvcnt; | |
2fee61d2 CF |
678 | u8 smba_en_lo; |
679 | u8 port; | |
680 | int retval; | |
681 | ||
bbb27fc3 RRD |
682 | mutex_lock(&piix4_mutex_sb800); |
683 | ||
701dc207 RRD |
684 | /* Request the SMBUS semaphore, avoid conflicts with the IMC */ |
685 | smbslvcnt = inb_p(SMBSLVCNT); | |
686 | do { | |
687 | outb_p(smbslvcnt | 0x10, SMBSLVCNT); | |
688 | ||
689 | /* Check the semaphore status */ | |
690 | smbslvcnt = inb_p(SMBSLVCNT); | |
691 | if (smbslvcnt & 0x10) | |
692 | break; | |
693 | ||
694 | usleep_range(1000, 2000); | |
695 | } while (--retries); | |
696 | /* SMBus is still owned by the IMC, we give up */ | |
bbb27fc3 RRD |
697 | if (!retries) { |
698 | mutex_unlock(&piix4_mutex_sb800); | |
701dc207 | 699 | return -EBUSY; |
bbb27fc3 | 700 | } |
2fee61d2 | 701 | |
88fa2dfb RRD |
702 | /* |
703 | * Notify the IMC (Integrated Micro Controller) if required. | |
704 | * Among other responsibilities, the IMC is in charge of monitoring | |
705 | * the System fans and temperature sensors, and act accordingly. | |
706 | * All this is done through SMBus and can/will collide | |
707 | * with our transactions if they are long (BLOCK_DATA). | |
708 | * Therefore we need to request the ownership flag during those | |
709 | * transactions. | |
710 | */ | |
711 | if ((size == I2C_SMBUS_BLOCK_DATA) && adapdata->notify_imc) { | |
712 | int ret; | |
713 | ||
714 | ret = piix4_imc_sleep(); | |
715 | switch (ret) { | |
716 | case -EBUSY: | |
717 | dev_warn(&adap->dev, | |
718 | "IMC base address index region 0x%x already in use.\n", | |
719 | KERNCZ_IMC_IDX); | |
720 | break; | |
721 | case -ETIMEDOUT: | |
722 | dev_warn(&adap->dev, | |
723 | "Failed to communicate with the IMC.\n"); | |
724 | break; | |
725 | default: | |
726 | break; | |
727 | } | |
728 | ||
729 | /* If IMC communication fails do not retry */ | |
730 | if (ret) { | |
731 | dev_warn(&adap->dev, | |
732 | "Continuing without IMC notification.\n"); | |
733 | adapdata->notify_imc = false; | |
734 | } | |
735 | } | |
736 | ||
6befa3fd | 737 | outb_p(piix4_port_sel_sb800, SB800_PIIX4_SMB_IDX); |
2fee61d2 CF |
738 | smba_en_lo = inb_p(SB800_PIIX4_SMB_IDX + 1); |
739 | ||
740 | port = adapdata->port; | |
0fe16195 GR |
741 | if ((smba_en_lo & piix4_port_mask_sb800) != port) |
742 | outb_p((smba_en_lo & ~piix4_port_mask_sb800) | port, | |
2fee61d2 CF |
743 | SB800_PIIX4_SMB_IDX + 1); |
744 | ||
745 | retval = piix4_access(adap, addr, flags, read_write, | |
746 | command, size, data); | |
747 | ||
748 | outb_p(smba_en_lo, SB800_PIIX4_SMB_IDX + 1); | |
749 | ||
701dc207 RRD |
750 | /* Release the semaphore */ |
751 | outb_p(smbslvcnt | 0x20, SMBSLVCNT); | |
752 | ||
88fa2dfb RRD |
753 | if ((size == I2C_SMBUS_BLOCK_DATA) && adapdata->notify_imc) |
754 | piix4_imc_wakeup(); | |
755 | ||
bbb27fc3 RRD |
756 | mutex_unlock(&piix4_mutex_sb800); |
757 | ||
2fee61d2 CF |
758 | return retval; |
759 | } | |
760 | ||
1da177e4 LT |
761 | static u32 piix4_func(struct i2c_adapter *adapter) |
762 | { | |
763 | return I2C_FUNC_SMBUS_QUICK | I2C_FUNC_SMBUS_BYTE | | |
764 | I2C_FUNC_SMBUS_BYTE_DATA | I2C_FUNC_SMBUS_WORD_DATA | | |
765 | I2C_FUNC_SMBUS_BLOCK_DATA; | |
766 | } | |
767 | ||
8f9082c5 | 768 | static const struct i2c_algorithm smbus_algorithm = { |
1da177e4 LT |
769 | .smbus_xfer = piix4_access, |
770 | .functionality = piix4_func, | |
771 | }; | |
772 | ||
2fee61d2 CF |
773 | static const struct i2c_algorithm piix4_smbus_algorithm_sb800 = { |
774 | .smbus_xfer = piix4_access_sb800, | |
775 | .functionality = piix4_func, | |
776 | }; | |
777 | ||
392debf1 | 778 | static const struct pci_device_id piix4_ids[] = { |
9b7389c0 JD |
779 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371AB_3) }, |
780 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443MX_3) }, | |
781 | { PCI_DEVICE(PCI_VENDOR_ID_EFAR, PCI_DEVICE_ID_EFAR_SLC90E66_3) }, | |
782 | { PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP200_SMBUS) }, | |
783 | { PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP300_SMBUS) }, | |
784 | { PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP400_SMBUS) }, | |
785 | { PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_SBX00_SMBUS) }, | |
3806e94b | 786 | { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_HUDSON2_SMBUS) }, |
bcb29994 | 787 | { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_KERNCZ_SMBUS) }, |
9b7389c0 JD |
788 | { PCI_DEVICE(PCI_VENDOR_ID_SERVERWORKS, |
789 | PCI_DEVICE_ID_SERVERWORKS_OSB4) }, | |
790 | { PCI_DEVICE(PCI_VENDOR_ID_SERVERWORKS, | |
791 | PCI_DEVICE_ID_SERVERWORKS_CSB5) }, | |
792 | { PCI_DEVICE(PCI_VENDOR_ID_SERVERWORKS, | |
793 | PCI_DEVICE_ID_SERVERWORKS_CSB6) }, | |
794 | { PCI_DEVICE(PCI_VENDOR_ID_SERVERWORKS, | |
795 | PCI_DEVICE_ID_SERVERWORKS_HT1000SB) }, | |
506a8b6c FL |
796 | { PCI_DEVICE(PCI_VENDOR_ID_SERVERWORKS, |
797 | PCI_DEVICE_ID_SERVERWORKS_HT1100LD) }, | |
1da177e4 LT |
798 | { 0, } |
799 | }; | |
800 | ||
801 | MODULE_DEVICE_TABLE (pci, piix4_ids); | |
802 | ||
ca2061e1 | 803 | static struct i2c_adapter *piix4_main_adapters[PIIX4_MAX_ADAPTERS]; |
2a2f7404 | 804 | static struct i2c_adapter *piix4_aux_adapter; |
e154bf6f | 805 | |
0b255e92 | 806 | static int piix4_add_adapter(struct pci_dev *dev, unsigned short smba, |
88fa2dfb | 807 | bool sb800_main, u8 port, bool notify_imc, |
725d2e3f | 808 | const char *name, struct i2c_adapter **padap) |
e154bf6f AA |
809 | { |
810 | struct i2c_adapter *adap; | |
811 | struct i2c_piix4_adapdata *adapdata; | |
812 | int retval; | |
813 | ||
814 | adap = kzalloc(sizeof(*adap), GFP_KERNEL); | |
815 | if (adap == NULL) { | |
816 | release_region(smba, SMBIOSIZE); | |
817 | return -ENOMEM; | |
818 | } | |
819 | ||
820 | adap->owner = THIS_MODULE; | |
821 | adap->class = I2C_CLASS_HWMON | I2C_CLASS_SPD; | |
83c60158 JD |
822 | adap->algo = sb800_main ? &piix4_smbus_algorithm_sb800 |
823 | : &smbus_algorithm; | |
e154bf6f AA |
824 | |
825 | adapdata = kzalloc(sizeof(*adapdata), GFP_KERNEL); | |
826 | if (adapdata == NULL) { | |
827 | kfree(adap); | |
828 | release_region(smba, SMBIOSIZE); | |
829 | return -ENOMEM; | |
830 | } | |
831 | ||
832 | adapdata->smba = smba; | |
83c60158 | 833 | adapdata->sb800_main = sb800_main; |
0fe16195 | 834 | adapdata->port = port << piix4_port_shift_sb800; |
88fa2dfb | 835 | adapdata->notify_imc = notify_imc; |
e154bf6f AA |
836 | |
837 | /* set up the sysfs linkage to our parent device */ | |
838 | adap->dev.parent = &dev->dev; | |
839 | ||
840 | snprintf(adap->name, sizeof(adap->name), | |
52795f6f | 841 | "SMBus PIIX4 adapter%s at %04x", name, smba); |
e154bf6f AA |
842 | |
843 | i2c_set_adapdata(adap, adapdata); | |
844 | ||
845 | retval = i2c_add_adapter(adap); | |
846 | if (retval) { | |
e154bf6f AA |
847 | kfree(adapdata); |
848 | kfree(adap); | |
849 | release_region(smba, SMBIOSIZE); | |
850 | return retval; | |
851 | } | |
852 | ||
853 | *padap = adap; | |
854 | return 0; | |
855 | } | |
856 | ||
88fa2dfb RRD |
857 | static int piix4_add_adapters_sb800(struct pci_dev *dev, unsigned short smba, |
858 | bool notify_imc) | |
2fee61d2 | 859 | { |
2fee61d2 CF |
860 | struct i2c_piix4_adapdata *adapdata; |
861 | int port; | |
862 | int retval; | |
863 | ||
2fee61d2 | 864 | for (port = 0; port < PIIX4_MAX_ADAPTERS; port++) { |
88fa2dfb | 865 | retval = piix4_add_adapter(dev, smba, true, port, notify_imc, |
725d2e3f | 866 | piix4_main_port_names_sb800[port], |
2fee61d2 CF |
867 | &piix4_main_adapters[port]); |
868 | if (retval < 0) | |
869 | goto error; | |
2fee61d2 CF |
870 | } |
871 | ||
872 | return retval; | |
873 | ||
874 | error: | |
875 | dev_err(&dev->dev, | |
876 | "Error setting up SB800 adapters. Unregistering!\n"); | |
877 | while (--port >= 0) { | |
878 | adapdata = i2c_get_adapdata(piix4_main_adapters[port]); | |
879 | if (adapdata->smba) { | |
880 | i2c_del_adapter(piix4_main_adapters[port]); | |
881 | kfree(adapdata); | |
882 | kfree(piix4_main_adapters[port]); | |
883 | piix4_main_adapters[port] = NULL; | |
884 | } | |
885 | } | |
886 | ||
2fee61d2 CF |
887 | return retval; |
888 | } | |
889 | ||
0b255e92 | 890 | static int piix4_probe(struct pci_dev *dev, const struct pci_device_id *id) |
1da177e4 LT |
891 | { |
892 | int retval; | |
52795f6f | 893 | bool is_sb800 = false; |
1da177e4 | 894 | |
76b3e28f CC |
895 | if ((dev->vendor == PCI_VENDOR_ID_ATI && |
896 | dev->device == PCI_DEVICE_ID_ATI_SBX00_SMBUS && | |
897 | dev->revision >= 0x40) || | |
2fee61d2 | 898 | dev->vendor == PCI_VENDOR_ID_AMD) { |
88fa2dfb | 899 | bool notify_imc = false; |
52795f6f JD |
900 | is_sb800 = true; |
901 | ||
2fee61d2 CF |
902 | if (!request_region(SB800_PIIX4_SMB_IDX, 2, "smba_idx")) { |
903 | dev_err(&dev->dev, | |
904 | "SMBus base address index region 0x%x already in use!\n", | |
905 | SB800_PIIX4_SMB_IDX); | |
906 | return -EBUSY; | |
907 | } | |
908 | ||
88fa2dfb RRD |
909 | if (dev->vendor == PCI_VENDOR_ID_AMD && |
910 | dev->device == PCI_DEVICE_ID_AMD_KERNCZ_SMBUS) { | |
911 | u8 imc; | |
912 | ||
913 | /* | |
914 | * Detect if IMC is active or not, this method is | |
915 | * described on coreboot's AMD IMC notes | |
916 | */ | |
917 | pci_bus_read_config_byte(dev->bus, PCI_DEVFN(0x14, 3), | |
918 | 0x40, &imc); | |
919 | if (imc & 0x80) | |
920 | notify_imc = true; | |
921 | } | |
922 | ||
87e1960e | 923 | /* base address location etc changed in SB800 */ |
a94dd00f | 924 | retval = piix4_setup_sb800(dev, id, 0); |
2fee61d2 CF |
925 | if (retval < 0) { |
926 | release_region(SB800_PIIX4_SMB_IDX, 2); | |
927 | return retval; | |
928 | } | |
87e1960e | 929 | |
2fee61d2 CF |
930 | /* |
931 | * Try to register multiplexed main SMBus adapter, | |
932 | * give up if we can't | |
933 | */ | |
88fa2dfb | 934 | retval = piix4_add_adapters_sb800(dev, retval, notify_imc); |
2fee61d2 CF |
935 | if (retval < 0) { |
936 | release_region(SB800_PIIX4_SMB_IDX, 2); | |
937 | return retval; | |
938 | } | |
939 | } else { | |
940 | retval = piix4_setup(dev, id); | |
941 | if (retval < 0) | |
942 | return retval; | |
1da177e4 | 943 | |
2fee61d2 | 944 | /* Try to register main SMBus adapter, give up if we can't */ |
88fa2dfb | 945 | retval = piix4_add_adapter(dev, retval, false, 0, false, "", |
2fee61d2 CF |
946 | &piix4_main_adapters[0]); |
947 | if (retval < 0) | |
948 | return retval; | |
949 | } | |
2a2f7404 AA |
950 | |
951 | /* Check for auxiliary SMBus on some AMD chipsets */ | |
a94dd00f RM |
952 | retval = -ENODEV; |
953 | ||
2a2f7404 | 954 | if (dev->vendor == PCI_VENDOR_ID_ATI && |
a94dd00f RM |
955 | dev->device == PCI_DEVICE_ID_ATI_SBX00_SMBUS) { |
956 | if (dev->revision < 0x40) { | |
957 | retval = piix4_setup_aux(dev, id, 0x58); | |
958 | } else { | |
959 | /* SB800 added aux bus too */ | |
960 | retval = piix4_setup_sb800(dev, id, 1); | |
2a2f7404 AA |
961 | } |
962 | } | |
963 | ||
a94dd00f RM |
964 | if (dev->vendor == PCI_VENDOR_ID_AMD && |
965 | dev->device == PCI_DEVICE_ID_AMD_HUDSON2_SMBUS) { | |
966 | retval = piix4_setup_sb800(dev, id, 1); | |
967 | } | |
968 | ||
969 | if (retval > 0) { | |
970 | /* Try to add the aux adapter if it exists, | |
971 | * piix4_add_adapter will clean up if this fails */ | |
88fa2dfb | 972 | piix4_add_adapter(dev, retval, false, 0, false, |
52795f6f | 973 | is_sb800 ? piix4_aux_port_name_sb800 : "", |
725d2e3f | 974 | &piix4_aux_adapter); |
a94dd00f RM |
975 | } |
976 | ||
2a2f7404 | 977 | return 0; |
1da177e4 LT |
978 | } |
979 | ||
0b255e92 | 980 | static void piix4_adap_remove(struct i2c_adapter *adap) |
1da177e4 | 981 | { |
14a8086d AA |
982 | struct i2c_piix4_adapdata *adapdata = i2c_get_adapdata(adap); |
983 | ||
984 | if (adapdata->smba) { | |
985 | i2c_del_adapter(adap); | |
45fd4470 | 986 | if (adapdata->port == (0 << piix4_port_shift_sb800)) { |
2fee61d2 | 987 | release_region(adapdata->smba, SMBIOSIZE); |
a28e3517 | 988 | if (adapdata->sb800_main) |
2fee61d2 | 989 | release_region(SB800_PIIX4_SMB_IDX, 2); |
2fee61d2 | 990 | } |
e154bf6f AA |
991 | kfree(adapdata); |
992 | kfree(adap); | |
1da177e4 LT |
993 | } |
994 | } | |
995 | ||
0b255e92 | 996 | static void piix4_remove(struct pci_dev *dev) |
14a8086d | 997 | { |
ca2061e1 CF |
998 | int port = PIIX4_MAX_ADAPTERS; |
999 | ||
1000 | while (--port >= 0) { | |
1001 | if (piix4_main_adapters[port]) { | |
1002 | piix4_adap_remove(piix4_main_adapters[port]); | |
1003 | piix4_main_adapters[port] = NULL; | |
1004 | } | |
e154bf6f | 1005 | } |
2a2f7404 AA |
1006 | |
1007 | if (piix4_aux_adapter) { | |
1008 | piix4_adap_remove(piix4_aux_adapter); | |
1009 | piix4_aux_adapter = NULL; | |
1010 | } | |
14a8086d AA |
1011 | } |
1012 | ||
1da177e4 LT |
1013 | static struct pci_driver piix4_driver = { |
1014 | .name = "piix4_smbus", | |
1015 | .id_table = piix4_ids, | |
1016 | .probe = piix4_probe, | |
0b255e92 | 1017 | .remove = piix4_remove, |
1da177e4 LT |
1018 | }; |
1019 | ||
56f21788 | 1020 | module_pci_driver(piix4_driver); |
1da177e4 LT |
1021 | |
1022 | MODULE_AUTHOR("Frodo Looijaard <frodol@dds.nl> and " | |
1023 | "Philip Edelbrock <phil@netroedge.com>"); | |
1024 | MODULE_DESCRIPTION("PIIX4 SMBus driver"); | |
1025 | MODULE_LICENSE("GPL"); |