[mirror_ubuntu-artful-kernel.git] / drivers / ide / pci / atiixp.c

/*
 *  Copyright (C) 2003 ATI Inc. <hyu@ati.com>
 *  Copyright (C) 2004,2007 Bartlomiej Zolnierkiewicz
 */

#include <linux/types.h>
#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/ioport.h>
#include <linux/pci.h>
#include <linux/hdreg.h>
#include <linux/ide.h>
#include <linux/delay.h>
#include <linux/init.h>

#include <asm/io.h>

#define ATIIXP_IDE_PIO_TIMING		0x40
#define ATIIXP_IDE_MDMA_TIMING		0x44
#define ATIIXP_IDE_PIO_CONTROL		0x48
#define ATIIXP_IDE_PIO_MODE		0x4a
#define ATIIXP_IDE_UDMA_CONTROL		0x54
#define ATIIXP_IDE_UDMA_MODE		0x56

typedef struct {
	u8 command_width;
	u8 recover_width;
} atiixp_ide_timing;

static atiixp_ide_timing pio_timing[] = {
	{ 0x05, 0x0d },
	{ 0x04, 0x07 },
	{ 0x03, 0x04 },
	{ 0x02, 0x02 },
	{ 0x02, 0x00 },
};

static atiixp_ide_timing mdma_timing[] = {
	{ 0x07, 0x07 },
	{ 0x02, 0x01 },
	{ 0x02, 0x00 },
};

static DEFINE_SPINLOCK(atiixp_lock);

/**
 *	atiixp_set_pio_mode	-	set host controller for PIO mode
 *	@drive: drive
 *	@pio: PIO mode number
 *
 *	Set the interface PIO mode.
 */

static void atiixp_set_pio_mode(ide_drive_t *drive, const u8 pio)
{
	struct pci_dev *dev = to_pci_dev(drive->hwif->dev);
	unsigned long flags;
	int timing_shift = (drive->dn & 2) ? 16 : 0 + (drive->dn & 1) ? 0 : 8;
	u32 pio_timing_data;
	u16 pio_mode_data;

	spin_lock_irqsave(&atiixp_lock, flags);

	pci_read_config_word(dev, ATIIXP_IDE_PIO_MODE, &pio_mode_data);
	pio_mode_data &= ~(0x07 << (drive->dn * 4));
	pio_mode_data |= (pio << (drive->dn * 4));
	pci_write_config_word(dev, ATIIXP_IDE_PIO_MODE, pio_mode_data);

	pci_read_config_dword(dev, ATIIXP_IDE_PIO_TIMING, &pio_timing_data);
	pio_timing_data &= ~(0xff << timing_shift);
	pio_timing_data |= (pio_timing[pio].recover_width << timing_shift) |
		 (pio_timing[pio].command_width << (timing_shift + 4));
	pci_write_config_dword(dev, ATIIXP_IDE_PIO_TIMING, pio_timing_data);

	spin_unlock_irqrestore(&atiixp_lock, flags);
}

/**
 *	atiixp_set_dma_mode	-	set host controller for DMA mode
 *	@drive: drive
 *	@speed: DMA mode
 *
 *	Set a ATIIXP host controller to the desired DMA mode.  This involves
 *	programming the right timing data into the PCI configuration space.
 */

static void atiixp_set_dma_mode(ide_drive_t *drive, const u8 speed)
{
	struct pci_dev *dev = to_pci_dev(drive->hwif->dev);
	unsigned long flags;
	int timing_shift = (drive->dn & 2) ? 16 : 0 + (drive->dn & 1) ? 0 : 8;
	u32 tmp32;
	u16 tmp16;
	u16 udma_ctl = 0;

	spin_lock_irqsave(&atiixp_lock, flags);

	pci_read_config_word(dev, ATIIXP_IDE_UDMA_CONTROL, &udma_ctl);

	if (speed >= XFER_UDMA_0) {
		pci_read_config_word(dev, ATIIXP_IDE_UDMA_MODE, &tmp16);
		tmp16 &= ~(0x07 << (drive->dn * 4));
		tmp16 |= ((speed & 0x07) << (drive->dn * 4));
		pci_write_config_word(dev, ATIIXP_IDE_UDMA_MODE, tmp16);

		udma_ctl |= (1 << drive->dn);
	} else if (speed >= XFER_MW_DMA_0) {
		u8 i = speed & 0x03;

		pci_read_config_dword(dev, ATIIXP_IDE_MDMA_TIMING, &tmp32);
		tmp32 &= ~(0xff << timing_shift);
		tmp32 |= (mdma_timing[i].recover_width << timing_shift) |
			 (mdma_timing[i].command_width << (timing_shift + 4));
		pci_write_config_dword(dev, ATIIXP_IDE_MDMA_TIMING, tmp32);

		udma_ctl &= ~(1 << drive->dn);
	}

	pci_write_config_word(dev, ATIIXP_IDE_UDMA_CONTROL, udma_ctl);

	spin_unlock_irqrestore(&atiixp_lock, flags);
}

/**
 *	init_hwif_atiixp		-	fill in the hwif for the ATIIXP
 *	@hwif: IDE interface
 *
 *	Set up the ide_hwif_t for the ATIIXP interface according to the
 *	capabilities of the hardware.
 */

static void __devinit init_hwif_atiixp(ide_hwif_t *hwif)
{
	struct pci_dev *pdev = to_pci_dev(hwif->dev);
	u8 udma_mode = 0, ch = hwif->channel;

	hwif->set_pio_mode = &atiixp_set_pio_mode;
	hwif->set_dma_mode = &atiixp_set_dma_mode;

	if (!hwif->dma_base)
		return;

	pci_read_config_byte(pdev, ATIIXP_IDE_UDMA_MODE + ch, &udma_mode);

	if ((udma_mode & 0x07) >= 0x04 || (udma_mode & 0x70) >= 0x40)
		hwif->cbl = ATA_CBL_PATA80;
	else
		hwif->cbl = ATA_CBL_PATA40;
}

static const struct ide_port_info atiixp_pci_info[] __devinitdata = {
	{	/* 0 */
		.name		= "ATIIXP",
		.init_hwif	= init_hwif_atiixp,
		.enablebits	= {{0x48,0x01,0x00}, {0x48,0x08,0x00}},
		.host_flags	= IDE_HFLAG_LEGACY_IRQS | IDE_HFLAG_BOOTABLE,
		.pio_mask	= ATA_PIO4,
		.mwdma_mask	= ATA_MWDMA2,
		.udma_mask	= ATA_UDMA5,
	},{	/* 1 */
		.name		= "SB600_PATA",
		.init_hwif	= init_hwif_atiixp,
		.enablebits	= {{0x48,0x01,0x00}, {0x00,0x00,0x00}},
 		.host_flags	= IDE_HFLAG_SINGLE | IDE_HFLAG_LEGACY_IRQS |
				  IDE_HFLAG_BOOTABLE,
		.pio_mask	= ATA_PIO4,
		.mwdma_mask	= ATA_MWDMA2,
		.udma_mask	= ATA_UDMA5,
 	},
};

/**
 *	atiixp_init_one	-	called when a ATIIXP is found
 *	@dev: the atiixp device
 *	@id: the matching pci id
 *
 *	Called when the PCI registration layer (or the IDE initialization)
 *	finds a device matching our IDE device tables.
 */

static int __devinit atiixp_init_one(struct pci_dev *dev, const struct pci_device_id *id)
{
	return ide_setup_pci_device(dev, &atiixp_pci_info[id->driver_data]);
}

static const struct pci_device_id atiixp_pci_tbl[] = {
	{ PCI_VDEVICE(ATI, PCI_DEVICE_ID_ATI_IXP200_IDE), 0 },
	{ PCI_VDEVICE(ATI, PCI_DEVICE_ID_ATI_IXP300_IDE), 0 },
	{ PCI_VDEVICE(ATI, PCI_DEVICE_ID_ATI_IXP400_IDE), 0 },
	{ PCI_VDEVICE(ATI, PCI_DEVICE_ID_ATI_IXP600_IDE), 1 },
	{ PCI_VDEVICE(ATI, PCI_DEVICE_ID_ATI_IXP700_IDE), 0 },
	{ 0, },
};
MODULE_DEVICE_TABLE(pci, atiixp_pci_tbl);

static struct pci_driver driver = {
	.name		= "ATIIXP_IDE",
	.id_table	= atiixp_pci_tbl,
	.probe		= atiixp_init_one,
};

static int __init atiixp_ide_init(void)
{
	return ide_pci_register_driver(&driver);
}

module_init(atiixp_ide_init);

MODULE_AUTHOR("HUI YU");
MODULE_DESCRIPTION("PCI driver module for ATI IXP IDE");
MODULE_LICENSE("GPL");
Commit	Line	Data
1da177e4	1	/*
1da177e4	2	* Copyright (C) 2003 ATI Inc. <hyu@ati.com>
485efc6c	3	* Copyright (C) 2004,2007 Bartlomiej Zolnierkiewicz
1da177e4 LT	4	*/
1da177e4 LT	5
1da177e4 LT	6	#include <linux/types.h>
	7	#include <linux/module.h>
	8	#include <linux/kernel.h>
	9	#include <linux/ioport.h>
	10	#include <linux/pci.h>
	11	#include <linux/hdreg.h>
	12	#include <linux/ide.h>
	13	#include <linux/delay.h>
	14	#include <linux/init.h>
	15
	16	#include <asm/io.h>
	17
	18	#define ATIIXP_IDE_PIO_TIMING 0x40
	19	#define ATIIXP_IDE_MDMA_TIMING 0x44
	20	#define ATIIXP_IDE_PIO_CONTROL 0x48
	21	#define ATIIXP_IDE_PIO_MODE 0x4a
	22	#define ATIIXP_IDE_UDMA_CONTROL 0x54
	23	#define ATIIXP_IDE_UDMA_MODE 0x56
	24
	25	typedef struct {
	26	u8 command_width;
	27	u8 recover_width;
	28	} atiixp_ide_timing;
	29
	30	static atiixp_ide_timing pio_timing[] = {
	31	{ 0x05, 0x0d },
	32	{ 0x04, 0x07 },
	33	{ 0x03, 0x04 },
	34	{ 0x02, 0x02 },
	35	{ 0x02, 0x00 },
	36	};
	37
	38	static atiixp_ide_timing mdma_timing[] = {
	39	{ 0x07, 0x07 },
	40	{ 0x02, 0x01 },
	41	{ 0x02, 0x00 },
	42	};
	43
6c5f8cc3 AC	44	static DEFINE_SPINLOCK(atiixp_lock);
6c5f8cc3 AC	45
1da177e4	46	/**
88b2b32b BZ	47	* atiixp_set_pio_mode - set host controller for PIO mode
	48	* @drive: drive
	49	* @pio: PIO mode number
1da177e4 LT	50	*
	51	* Set the interface PIO mode.
	52	*/
	53
88b2b32b	54	static void atiixp_set_pio_mode(ide_drive_t *drive, const u8 pio)
1da177e4	55	{
36501650	56	struct pci_dev *dev = to_pci_dev(drive->hwif->dev);
1da177e4 LT	57	unsigned long flags;
	58	int timing_shift = (drive->dn & 2) ? 16 : 0 + (drive->dn & 1) ? 0 : 8;
	59	u32 pio_timing_data;
	60	u16 pio_mode_data;
	61
6c5f8cc3	62	spin_lock_irqsave(&atiixp_lock, flags);
1da177e4 LT	63
	64	pci_read_config_word(dev, ATIIXP_IDE_PIO_MODE, &pio_mode_data);
	65	pio_mode_data &= ~(0x07 << (drive->dn * 4));
	66	pio_mode_data \|= (pio << (drive->dn * 4));
	67	pci_write_config_word(dev, ATIIXP_IDE_PIO_MODE, pio_mode_data);
	68
	69	pci_read_config_dword(dev, ATIIXP_IDE_PIO_TIMING, &pio_timing_data);
	70	pio_timing_data &= ~(0xff << timing_shift);
	71	pio_timing_data \|= (pio_timing[pio].recover_width << timing_shift) \|
	72	(pio_timing[pio].command_width << (timing_shift + 4));
	73	pci_write_config_dword(dev, ATIIXP_IDE_PIO_TIMING, pio_timing_data);
	74
6c5f8cc3	75	spin_unlock_irqrestore(&atiixp_lock, flags);
1da177e4 LT	76	}
	77
	78	/**
88b2b32b BZ	79	* atiixp_set_dma_mode - set host controller for DMA mode
	80	* @drive: drive
	81	* @speed: DMA mode
1da177e4	82	*
88b2b32b BZ	83	* Set a ATIIXP host controller to the desired DMA mode. This involves
88b2b32b BZ	84	* programming the right timing data into the PCI configuration space.
1da177e4 LT	85	*/
1da177e4 LT	86
88b2b32b	87	static void atiixp_set_dma_mode(ide_drive_t *drive, const u8 speed)
1da177e4	88	{
36501650	89	struct pci_dev *dev = to_pci_dev(drive->hwif->dev);
1da177e4 LT	90	unsigned long flags;
	91	int timing_shift = (drive->dn & 2) ? 16 : 0 + (drive->dn & 1) ? 0 : 8;
	92	u32 tmp32;
	93	u16 tmp16;
8ae60e34	94	u16 udma_ctl = 0;
94c7fa0f	95
6c5f8cc3	96	spin_lock_irqsave(&atiixp_lock, flags);
1da177e4	97
8ae60e34 BZ	98	pci_read_config_word(dev, ATIIXP_IDE_UDMA_CONTROL, &udma_ctl);
8ae60e34 BZ	99
1da177e4 LT	100	if (speed >= XFER_UDMA_0) {
	101	pci_read_config_word(dev, ATIIXP_IDE_UDMA_MODE, &tmp16);
	102	tmp16 &= ~(0x07 << (drive->dn * 4));
	103	tmp16 \|= ((speed & 0x07) << (drive->dn * 4));
	104	pci_write_config_word(dev, ATIIXP_IDE_UDMA_MODE, tmp16);
8ae60e34 BZ	105
	106	udma_ctl \|= (1 << drive->dn);
	107	} else if (speed >= XFER_MW_DMA_0) {
	108	u8 i = speed & 0x03;
	109
	110	pci_read_config_dword(dev, ATIIXP_IDE_MDMA_TIMING, &tmp32);
	111	tmp32 &= ~(0xff << timing_shift);
	112	tmp32 \|= (mdma_timing[i].recover_width << timing_shift) \|
	113	(mdma_timing[i].command_width << (timing_shift + 4));
	114	pci_write_config_dword(dev, ATIIXP_IDE_MDMA_TIMING, tmp32);
	115
	116	udma_ctl &= ~(1 << drive->dn);
1da177e4 LT	117	}
1da177e4 LT	118
8ae60e34 BZ	119	pci_write_config_word(dev, ATIIXP_IDE_UDMA_CONTROL, udma_ctl);
8ae60e34 BZ	120
6c5f8cc3	121	spin_unlock_irqrestore(&atiixp_lock, flags);
1da177e4 LT	122	}
1da177e4 LT	123
1da177e4 LT	124	/**
	125	* init_hwif_atiixp - fill in the hwif for the ATIIXP
	126	* @hwif: IDE interface
	127	*
	128	* Set up the ide_hwif_t for the ATIIXP interface according to the
	129	* capabilities of the hardware.
	130	*/
	131
	132	static void __devinit init_hwif_atiixp(ide_hwif_t *hwif)
	133	{
36501650 BZ	134	struct pci_dev *pdev = to_pci_dev(hwif->dev);
36501650 BZ	135	u8 udma_mode = 0, ch = hwif->channel;
e5c073ff	136
26bcb879	137	hwif->set_pio_mode = &atiixp_set_pio_mode;
88b2b32b	138	hwif->set_dma_mode = &atiixp_set_dma_mode;
1da177e4 LT	139
	140	if (!hwif->dma_base)
	141	return;
	142
e5c073ff	143	pci_read_config_byte(pdev, ATIIXP_IDE_UDMA_MODE + ch, &udma_mode);
49521f97	144
e5c073ff	145	if ((udma_mode & 0x07) >= 0x04 \|\| (udma_mode & 0x70) >= 0x40)
49521f97	146	hwif->cbl = ATA_CBL_PATA80;
e5c073ff	147	else
49521f97	148	hwif->cbl = ATA_CBL_PATA40;
1da177e4 LT	149	}
1da177e4 LT	150
85620436	151	static const struct ide_port_info atiixp_pci_info[] __devinitdata = {
1da177e4 LT	152	{ /* 0 */
	153	.name = "ATIIXP",
	154	.init_hwif = init_hwif_atiixp,
1da177e4	155	.enablebits = {{0x48,0x01,0x00}, {0x48,0x08,0x00}},
3985ee3b	156	.host_flags = IDE_HFLAG_LEGACY_IRQS \| IDE_HFLAG_BOOTABLE,
4099d143	157	.pio_mask = ATA_PIO4,
5f8b6c34 BZ	158	.mwdma_mask = ATA_MWDMA2,
5f8b6c34 BZ	159	.udma_mask = ATA_UDMA5,
b25168df CH	160	},{ /* 1 */
	161	.name = "SB600_PATA",
	162	.init_hwif = init_hwif_atiixp,
b25168df	163	.enablebits = {{0x48,0x01,0x00}, {0x00,0x00,0x00}},
3985ee3b BZ	164	.host_flags = IDE_HFLAG_SINGLE \| IDE_HFLAG_LEGACY_IRQS \|
3985ee3b BZ	165	IDE_HFLAG_BOOTABLE,
4099d143	166	.pio_mask = ATA_PIO4,
5f8b6c34 BZ	167	.mwdma_mask = ATA_MWDMA2,
5f8b6c34 BZ	168	.udma_mask = ATA_UDMA5,
b25168df	169	},
1da177e4 LT	170	};
	171
	172	/**
	173	* atiixp_init_one - called when a ATIIXP is found
	174	* @dev: the atiixp device
	175	* @id: the matching pci id
	176	*
	177	* Called when the PCI registration layer (or the IDE initialization)
	178	* finds a device matching our IDE device tables.
	179	*/
	180
	181	static int __devinit atiixp_init_one(struct pci_dev dev, const struct pci_device_id id)
	182	{
	183	return ide_setup_pci_device(dev, &atiixp_pci_info[id->driver_data]);
	184	}
	185
9cbcc5e3 BZ	186	static const struct pci_device_id atiixp_pci_tbl[] = {
	187	{ PCI_VDEVICE(ATI, PCI_DEVICE_ID_ATI_IXP200_IDE), 0 },
	188	{ PCI_VDEVICE(ATI, PCI_DEVICE_ID_ATI_IXP300_IDE), 0 },
	189	{ PCI_VDEVICE(ATI, PCI_DEVICE_ID_ATI_IXP400_IDE), 0 },
	190	{ PCI_VDEVICE(ATI, PCI_DEVICE_ID_ATI_IXP600_IDE), 1 },
	191	{ PCI_VDEVICE(ATI, PCI_DEVICE_ID_ATI_IXP700_IDE), 0 },
1da177e4 LT	192	{ 0, },
	193	};
	194	MODULE_DEVICE_TABLE(pci, atiixp_pci_tbl);
	195
	196	static struct pci_driver driver = {
	197	.name = "ATIIXP_IDE",
	198	.id_table = atiixp_pci_tbl,
	199	.probe = atiixp_init_one,
	200	};
	201
82ab1eec	202	static int __init atiixp_ide_init(void)
1da177e4 LT	203	{
	204	return ide_pci_register_driver(&driver);
	205	}
	206
	207	module_init(atiixp_ide_init);
	208
	209	MODULE_AUTHOR("HUI YU");
	210	MODULE_DESCRIPTION("PCI driver module for ATI IXP IDE");
	211	MODULE_LICENSE("GPL");