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1da177e4 | 1 | /* |
1da177e4 LT |
2 | * Copyright (C) 1995-1996 Linus Torvalds & authors (see below) |
3 | */ | |
4 | ||
5 | /* | |
6 | * Original authors: abramov@cecmow.enet.dec.com (Igor Abramov) | |
4752b5e7 | 7 | * mlord@pobox.com (Mark Lord) |
1da177e4 LT |
8 | * |
9 | * See linux/MAINTAINERS for address of current maintainer. | |
10 | * | |
11 | * This file provides support for the advanced features and bugs | |
12 | * of IDE interfaces using the CMD Technologies 0640 IDE interface chip. | |
13 | * | |
14 | * These chips are basically fucked by design, and getting this driver | |
15 | * to work on every motherboard design that uses this screwed chip seems | |
16 | * bloody well impossible. However, we're still trying. | |
17 | * | |
18 | * Version 0.97 worked for everybody. | |
19 | * | |
20 | * User feedback is essential. Many thanks to the beta test team: | |
21 | * | |
22 | * A.Hartgers@stud.tue.nl, JZDQC@CUNYVM.CUNY.edu, abramov@cecmow.enet.dec.com, | |
23 | * bardj@utopia.ppp.sn.no, bart@gaga.tue.nl, bbol001@cs.auckland.ac.nz, | |
24 | * chrisc@dbass.demon.co.uk, dalecki@namu26.Num.Math.Uni-Goettingen.de, | |
25 | * derekn@vw.ece.cmu.edu, florian@btp2x3.phy.uni-bayreuth.de, | |
26 | * flynn@dei.unipd.it, gadio@netvision.net.il, godzilla@futuris.net, | |
27 | * j@pobox.com, jkemp1@mises.uni-paderborn.de, jtoppe@hiwaay.net, | |
28 | * kerouac@ssnet.com, meskes@informatik.rwth-aachen.de, hzoli@cs.elte.hu, | |
29 | * peter@udgaard.isgtec.com, phil@tazenda.demon.co.uk, roadcapw@cfw.com, | |
30 | * s0033las@sun10.vsz.bme.hu, schaffer@tam.cornell.edu, sjd@slip.net, | |
31 | * steve@ei.org, ulrpeg@bigcomm.gun.de, ism@tardis.ed.ac.uk, mack@cray.com | |
32 | * liug@mama.indstate.edu, and others. | |
33 | * | |
34 | * Version 0.01 Initial version, hacked out of ide.c, | |
35 | * and #include'd rather than compiled separately. | |
36 | * This will get cleaned up in a subsequent release. | |
37 | * | |
38 | * Version 0.02 Fixes for vlb initialization code, enable prefetch | |
39 | * for versions 'B' and 'C' of chip by default, | |
40 | * some code cleanup. | |
41 | * | |
42 | * Version 0.03 Added reset of secondary interface, | |
43 | * and black list for devices which are not compatible | |
44 | * with prefetch mode. Separate function for setting | |
45 | * prefetch is added, possibly it will be called some | |
46 | * day from ioctl processing code. | |
47 | * | |
48 | * Version 0.04 Now configs/compiles separate from ide.c | |
49 | * | |
50 | * Version 0.05 Major rewrite of interface timing code. | |
51 | * Added new function cmd640_set_mode to set PIO mode | |
52 | * from ioctl call. New drives added to black list. | |
53 | * | |
54 | * Version 0.06 More code cleanup. Prefetch is enabled only for | |
55 | * detected hard drives, not included in prefetch | |
56 | * black list. | |
57 | * | |
58 | * Version 0.07 Changed to more conservative drive tuning policy. | |
59 | * Unknown drives, which report PIO < 4 are set to | |
60 | * (reported_PIO - 1) if it is supported, or to PIO0. | |
61 | * List of known drives extended by info provided by | |
62 | * CMD at their ftp site. | |
63 | * | |
64 | * Version 0.08 Added autotune/noautotune support. | |
65 | * | |
66 | * Version 0.09 Try to be smarter about 2nd port enabling. | |
67 | * Version 0.10 Be nice and don't reset 2nd port. | |
68 | * Version 0.11 Try to handle more weird situations. | |
69 | * | |
70 | * Version 0.12 Lots of bug fixes from Laszlo Peter | |
71 | * irq unmasking disabled for reliability. | |
72 | * try to be even smarter about the second port. | |
73 | * tidy up source code formatting. | |
74 | * Version 0.13 permit irq unmasking again. | |
75 | * Version 0.90 massive code cleanup, some bugs fixed. | |
76 | * defaults all drives to PIO mode0, prefetch off. | |
77 | * autotune is OFF by default, with compile time flag. | |
78 | * prefetch can be turned OFF/ON using "hdparm -p8/-p9" | |
79 | * (requires hdparm-3.1 or newer) | |
80 | * Version 0.91 first release to linux-kernel list. | |
81 | * Version 0.92 move initial reg dump to separate callable function | |
82 | * change "readahead" to "prefetch" to avoid confusion | |
83 | * Version 0.95 respect original BIOS timings unless autotuning. | |
84 | * tons of code cleanup and rearrangement. | |
85 | * added CONFIG_BLK_DEV_CMD640_ENHANCED option | |
86 | * prevent use of unmask when prefetch is on | |
87 | * Version 0.96 prevent use of io_32bit when prefetch is off | |
88 | * Version 0.97 fix VLB secondary interface for sjd@slip.net | |
89 | * other minor tune-ups: 0.96 was very good. | |
90 | * Version 0.98 ignore PCI version when disabled by BIOS | |
91 | * Version 0.99 display setup/active/recovery clocks with PIO mode | |
92 | * Version 1.00 Mmm.. cannot depend on PCMD_ENA in all systems | |
93 | * Version 1.01 slow/fast devsel can be selected with "hdparm -p6/-p7" | |
94 | * ("fast" is necessary for 32bit I/O in some systems) | |
95 | * Version 1.02 fix bug that resulted in slow "setup times" | |
96 | * (patch courtesy of Zoltan Hidvegi) | |
97 | */ | |
98 | ||
1da177e4 LT |
99 | #define CMD640_PREFETCH_MASKS 1 |
100 | ||
4752b5e7 | 101 | /*#define CMD640_DUMP_REGS */ |
1da177e4 | 102 | |
1da177e4 LT |
103 | #include <linux/types.h> |
104 | #include <linux/kernel.h> | |
105 | #include <linux/delay.h> | |
1da177e4 LT |
106 | #include <linux/hdreg.h> |
107 | #include <linux/ide.h> | |
108 | #include <linux/init.h> | |
109 | ||
110 | #include <asm/io.h> | |
111 | ||
7ebe5936 BZ |
112 | #define DRV_NAME "cmd640" |
113 | ||
ef87f8d0 | 114 | static int cmd640_vlb; |
1da177e4 LT |
115 | |
116 | /* | |
117 | * CMD640 specific registers definition. | |
118 | */ | |
119 | ||
120 | #define VID 0x00 | |
121 | #define DID 0x02 | |
122 | #define PCMD 0x04 | |
123 | #define PCMD_ENA 0x01 | |
124 | #define PSTTS 0x06 | |
125 | #define REVID 0x08 | |
126 | #define PROGIF 0x09 | |
127 | #define SUBCL 0x0a | |
128 | #define BASCL 0x0b | |
129 | #define BaseA0 0x10 | |
130 | #define BaseA1 0x14 | |
131 | #define BaseA2 0x18 | |
132 | #define BaseA3 0x1c | |
133 | #define INTLINE 0x3c | |
134 | #define INPINE 0x3d | |
135 | ||
136 | #define CFR 0x50 | |
137 | #define CFR_DEVREV 0x03 | |
138 | #define CFR_IDE01INTR 0x04 | |
139 | #define CFR_DEVID 0x18 | |
140 | #define CFR_AT_VESA_078h 0x20 | |
141 | #define CFR_DSA1 0x40 | |
142 | #define CFR_DSA0 0x80 | |
143 | ||
144 | #define CNTRL 0x51 | |
145 | #define CNTRL_DIS_RA0 0x40 | |
146 | #define CNTRL_DIS_RA1 0x80 | |
147 | #define CNTRL_ENA_2ND 0x08 | |
148 | ||
149 | #define CMDTIM 0x52 | |
150 | #define ARTTIM0 0x53 | |
151 | #define DRWTIM0 0x54 | |
152 | #define ARTTIM1 0x55 | |
153 | #define DRWTIM1 0x56 | |
154 | #define ARTTIM23 0x57 | |
155 | #define ARTTIM23_DIS_RA2 0x04 | |
156 | #define ARTTIM23_DIS_RA3 0x08 | |
157 | #define DRWTIM23 0x58 | |
158 | #define BRST 0x59 | |
159 | ||
160 | /* | |
161 | * Registers and masks for easy access by drive index: | |
162 | */ | |
163 | static u8 prefetch_regs[4] = {CNTRL, CNTRL, ARTTIM23, ARTTIM23}; | |
164 | static u8 prefetch_masks[4] = {CNTRL_DIS_RA0, CNTRL_DIS_RA1, ARTTIM23_DIS_RA2, ARTTIM23_DIS_RA3}; | |
165 | ||
166 | #ifdef CONFIG_BLK_DEV_CMD640_ENHANCED | |
167 | ||
168 | static u8 arttim_regs[4] = {ARTTIM0, ARTTIM1, ARTTIM23, ARTTIM23}; | |
169 | static u8 drwtim_regs[4] = {DRWTIM0, DRWTIM1, DRWTIM23, DRWTIM23}; | |
170 | ||
171 | /* | |
172 | * Current cmd640 timing values for each drive. | |
173 | * The defaults for each are the slowest possible timings. | |
174 | */ | |
175 | static u8 setup_counts[4] = {4, 4, 4, 4}; /* Address setup count (in clocks) */ | |
176 | static u8 active_counts[4] = {16, 16, 16, 16}; /* Active count (encoded) */ | |
177 | static u8 recovery_counts[4] = {16, 16, 16, 16}; /* Recovery count (encoded) */ | |
178 | ||
179 | #endif /* CONFIG_BLK_DEV_CMD640_ENHANCED */ | |
180 | ||
5bbcf924 BZ |
181 | static DEFINE_SPINLOCK(cmd640_lock); |
182 | ||
1da177e4 LT |
183 | /* |
184 | * These are initialized to point at the devices we control | |
185 | */ | |
186 | static ide_hwif_t *cmd_hwif0, *cmd_hwif1; | |
1da177e4 LT |
187 | |
188 | /* | |
189 | * Interface to access cmd640x registers | |
190 | */ | |
191 | static unsigned int cmd640_key; | |
192 | static void (*__put_cmd640_reg)(u16 reg, u8 val); | |
193 | static u8 (*__get_cmd640_reg)(u16 reg); | |
194 | ||
195 | /* | |
196 | * This is read from the CFR reg, and is used in several places. | |
197 | */ | |
198 | static unsigned int cmd640_chip_version; | |
199 | ||
200 | /* | |
201 | * The CMD640x chip does not support DWORD config write cycles, but some | |
202 | * of the BIOSes use them to implement the config services. | |
203 | * Therefore, we must use direct IO instead. | |
204 | */ | |
205 | ||
206 | /* PCI method 1 access */ | |
207 | ||
4752b5e7 | 208 | static void put_cmd640_reg_pci1(u16 reg, u8 val) |
1da177e4 LT |
209 | { |
210 | outl_p((reg & 0xfc) | cmd640_key, 0xcf8); | |
211 | outb_p(val, (reg & 3) | 0xcfc); | |
212 | } | |
213 | ||
4752b5e7 | 214 | static u8 get_cmd640_reg_pci1(u16 reg) |
1da177e4 LT |
215 | { |
216 | outl_p((reg & 0xfc) | cmd640_key, 0xcf8); | |
217 | return inb_p((reg & 3) | 0xcfc); | |
218 | } | |
219 | ||
220 | /* PCI method 2 access (from CMD datasheet) */ | |
221 | ||
4752b5e7 | 222 | static void put_cmd640_reg_pci2(u16 reg, u8 val) |
1da177e4 LT |
223 | { |
224 | outb_p(0x10, 0xcf8); | |
225 | outb_p(val, cmd640_key + reg); | |
226 | outb_p(0, 0xcf8); | |
227 | } | |
228 | ||
4752b5e7 | 229 | static u8 get_cmd640_reg_pci2(u16 reg) |
1da177e4 LT |
230 | { |
231 | u8 b; | |
232 | ||
233 | outb_p(0x10, 0xcf8); | |
234 | b = inb_p(cmd640_key + reg); | |
235 | outb_p(0, 0xcf8); | |
236 | return b; | |
237 | } | |
238 | ||
239 | /* VLB access */ | |
240 | ||
4752b5e7 | 241 | static void put_cmd640_reg_vlb(u16 reg, u8 val) |
1da177e4 LT |
242 | { |
243 | outb_p(reg, cmd640_key); | |
244 | outb_p(val, cmd640_key + 4); | |
245 | } | |
246 | ||
4752b5e7 | 247 | static u8 get_cmd640_reg_vlb(u16 reg) |
1da177e4 LT |
248 | { |
249 | outb_p(reg, cmd640_key); | |
250 | return inb_p(cmd640_key + 4); | |
251 | } | |
252 | ||
253 | static u8 get_cmd640_reg(u16 reg) | |
254 | { | |
1da177e4 | 255 | unsigned long flags; |
5bbcf924 | 256 | u8 b; |
1da177e4 | 257 | |
5bbcf924 | 258 | spin_lock_irqsave(&cmd640_lock, flags); |
1da177e4 | 259 | b = __get_cmd640_reg(reg); |
5bbcf924 | 260 | spin_unlock_irqrestore(&cmd640_lock, flags); |
1da177e4 LT |
261 | return b; |
262 | } | |
263 | ||
264 | static void put_cmd640_reg(u16 reg, u8 val) | |
265 | { | |
266 | unsigned long flags; | |
267 | ||
5bbcf924 | 268 | spin_lock_irqsave(&cmd640_lock, flags); |
4752b5e7 | 269 | __put_cmd640_reg(reg, val); |
5bbcf924 | 270 | spin_unlock_irqrestore(&cmd640_lock, flags); |
1da177e4 LT |
271 | } |
272 | ||
4752b5e7 | 273 | static int __init match_pci_cmd640_device(void) |
1da177e4 LT |
274 | { |
275 | const u8 ven_dev[4] = {0x95, 0x10, 0x40, 0x06}; | |
276 | unsigned int i; | |
277 | for (i = 0; i < 4; i++) { | |
278 | if (get_cmd640_reg(i) != ven_dev[i]) | |
279 | return 0; | |
280 | } | |
281 | #ifdef STUPIDLY_TRUST_BROKEN_PCMD_ENA_BIT | |
282 | if ((get_cmd640_reg(PCMD) & PCMD_ENA) == 0) { | |
283 | printk("ide: cmd640 on PCI disabled by BIOS\n"); | |
284 | return 0; | |
285 | } | |
286 | #endif /* STUPIDLY_TRUST_BROKEN_PCMD_ENA_BIT */ | |
287 | return 1; /* success */ | |
288 | } | |
289 | ||
290 | /* | |
291 | * Probe for CMD640x -- pci method 1 | |
292 | */ | |
4752b5e7 | 293 | static int __init probe_for_cmd640_pci1(void) |
1da177e4 LT |
294 | { |
295 | __get_cmd640_reg = get_cmd640_reg_pci1; | |
296 | __put_cmd640_reg = put_cmd640_reg_pci1; | |
297 | for (cmd640_key = 0x80000000; | |
298 | cmd640_key <= 0x8000f800; | |
299 | cmd640_key += 0x800) { | |
300 | if (match_pci_cmd640_device()) | |
301 | return 1; /* success */ | |
302 | } | |
303 | return 0; | |
304 | } | |
305 | ||
306 | /* | |
307 | * Probe for CMD640x -- pci method 2 | |
308 | */ | |
4752b5e7 | 309 | static int __init probe_for_cmd640_pci2(void) |
1da177e4 LT |
310 | { |
311 | __get_cmd640_reg = get_cmd640_reg_pci2; | |
312 | __put_cmd640_reg = put_cmd640_reg_pci2; | |
313 | for (cmd640_key = 0xc000; cmd640_key <= 0xcf00; cmd640_key += 0x100) { | |
314 | if (match_pci_cmd640_device()) | |
315 | return 1; /* success */ | |
316 | } | |
317 | return 0; | |
318 | } | |
319 | ||
320 | /* | |
321 | * Probe for CMD640x -- vlb | |
322 | */ | |
4752b5e7 | 323 | static int __init probe_for_cmd640_vlb(void) |
1da177e4 LT |
324 | { |
325 | u8 b; | |
326 | ||
327 | __get_cmd640_reg = get_cmd640_reg_vlb; | |
328 | __put_cmd640_reg = put_cmd640_reg_vlb; | |
329 | cmd640_key = 0x178; | |
330 | b = get_cmd640_reg(CFR); | |
331 | if (b == 0xff || b == 0x00 || (b & CFR_AT_VESA_078h)) { | |
332 | cmd640_key = 0x78; | |
333 | b = get_cmd640_reg(CFR); | |
334 | if (b == 0xff || b == 0x00 || !(b & CFR_AT_VESA_078h)) | |
335 | return 0; | |
336 | } | |
337 | return 1; /* success */ | |
338 | } | |
339 | ||
340 | /* | |
341 | * Returns 1 if an IDE interface/drive exists at 0x170, | |
342 | * Returns 0 otherwise. | |
343 | */ | |
4752b5e7 | 344 | static int __init secondary_port_responding(void) |
1da177e4 LT |
345 | { |
346 | unsigned long flags; | |
347 | ||
5bbcf924 | 348 | spin_lock_irqsave(&cmd640_lock, flags); |
1da177e4 LT |
349 | |
350 | outb_p(0x0a, 0x170 + IDE_SELECT_OFFSET); /* select drive0 */ | |
351 | udelay(100); | |
352 | if ((inb_p(0x170 + IDE_SELECT_OFFSET) & 0x1f) != 0x0a) { | |
353 | outb_p(0x1a, 0x170 + IDE_SELECT_OFFSET); /* select drive1 */ | |
354 | udelay(100); | |
355 | if ((inb_p(0x170 + IDE_SELECT_OFFSET) & 0x1f) != 0x1a) { | |
5bbcf924 | 356 | spin_unlock_irqrestore(&cmd640_lock, flags); |
1da177e4 LT |
357 | return 0; /* nothing responded */ |
358 | } | |
359 | } | |
5bbcf924 | 360 | spin_unlock_irqrestore(&cmd640_lock, flags); |
1da177e4 LT |
361 | return 1; /* success */ |
362 | } | |
363 | ||
364 | #ifdef CMD640_DUMP_REGS | |
365 | /* | |
366 | * Dump out all cmd640 registers. May be called from ide.c | |
367 | */ | |
4752b5e7 | 368 | static void cmd640_dump_regs(void) |
1da177e4 LT |
369 | { |
370 | unsigned int reg = cmd640_vlb ? 0x50 : 0x00; | |
371 | ||
372 | /* Dump current state of chip registers */ | |
373 | printk("ide: cmd640 internal register dump:"); | |
374 | for (; reg <= 0x59; reg++) { | |
375 | if (!(reg & 0x0f)) | |
376 | printk("\n%04x:", reg); | |
377 | printk(" %02x", get_cmd640_reg(reg)); | |
378 | } | |
379 | printk("\n"); | |
380 | } | |
381 | #endif | |
382 | ||
383 | /* | |
384 | * Check whether prefetch is on for a drive, | |
385 | * and initialize the unmask flags for safe operation. | |
386 | */ | |
9523076a | 387 | static void __init check_prefetch(ide_drive_t *drive, unsigned int index) |
1da177e4 | 388 | { |
1da177e4 LT |
389 | u8 b = get_cmd640_reg(prefetch_regs[index]); |
390 | ||
391 | if (b & prefetch_masks[index]) { /* is prefetch off? */ | |
392 | drive->no_unmask = 0; | |
393 | drive->no_io_32bit = 1; | |
394 | drive->io_32bit = 0; | |
395 | } else { | |
396 | #if CMD640_PREFETCH_MASKS | |
397 | drive->no_unmask = 1; | |
398 | drive->unmask = 0; | |
399 | #endif | |
400 | drive->no_io_32bit = 0; | |
401 | } | |
402 | } | |
403 | ||
1da177e4 LT |
404 | #ifdef CONFIG_BLK_DEV_CMD640_ENHANCED |
405 | ||
406 | /* | |
407 | * Sets prefetch mode for a drive. | |
408 | */ | |
9523076a | 409 | static void set_prefetch_mode(ide_drive_t *drive, unsigned int index, int mode) |
1da177e4 | 410 | { |
5bbcf924 | 411 | unsigned long flags; |
1da177e4 LT |
412 | int reg = prefetch_regs[index]; |
413 | u8 b; | |
1da177e4 | 414 | |
5bbcf924 | 415 | spin_lock_irqsave(&cmd640_lock, flags); |
1da177e4 LT |
416 | b = __get_cmd640_reg(reg); |
417 | if (mode) { /* want prefetch on? */ | |
418 | #if CMD640_PREFETCH_MASKS | |
419 | drive->no_unmask = 1; | |
420 | drive->unmask = 0; | |
421 | #endif | |
422 | drive->no_io_32bit = 0; | |
423 | b &= ~prefetch_masks[index]; /* enable prefetch */ | |
424 | } else { | |
425 | drive->no_unmask = 0; | |
426 | drive->no_io_32bit = 1; | |
427 | drive->io_32bit = 0; | |
428 | b |= prefetch_masks[index]; /* disable prefetch */ | |
429 | } | |
430 | __put_cmd640_reg(reg, b); | |
5bbcf924 | 431 | spin_unlock_irqrestore(&cmd640_lock, flags); |
1da177e4 LT |
432 | } |
433 | ||
434 | /* | |
435 | * Dump out current drive clocks settings | |
436 | */ | |
4752b5e7 | 437 | static void display_clocks(unsigned int index) |
1da177e4 LT |
438 | { |
439 | u8 active_count, recovery_count; | |
440 | ||
441 | active_count = active_counts[index]; | |
442 | if (active_count == 1) | |
443 | ++active_count; | |
444 | recovery_count = recovery_counts[index]; | |
445 | if (active_count > 3 && recovery_count == 1) | |
446 | ++recovery_count; | |
447 | if (cmd640_chip_version > 1) | |
448 | recovery_count += 1; /* cmd640b uses (count + 1)*/ | |
449 | printk(", clocks=%d/%d/%d\n", setup_counts[index], active_count, recovery_count); | |
450 | } | |
451 | ||
452 | /* | |
453 | * Pack active and recovery counts into single byte representation | |
454 | * used by controller | |
455 | */ | |
4752b5e7 | 456 | static inline u8 pack_nibbles(u8 upper, u8 lower) |
1da177e4 LT |
457 | { |
458 | return ((upper & 0x0f) << 4) | (lower & 0x0f); | |
459 | } | |
460 | ||
461 | /* | |
462 | * This routine retrieves the initial drive timings from the chipset. | |
463 | */ | |
4752b5e7 | 464 | static void __init retrieve_drive_counts(unsigned int index) |
1da177e4 LT |
465 | { |
466 | u8 b; | |
467 | ||
468 | /* | |
469 | * Get the internal setup timing, and convert to clock count | |
470 | */ | |
471 | b = get_cmd640_reg(arttim_regs[index]) & ~0x3f; | |
472 | switch (b) { | |
4752b5e7 PC |
473 | case 0x00: b = 4; break; |
474 | case 0x80: b = 3; break; | |
475 | case 0x40: b = 2; break; | |
476 | default: b = 5; break; | |
1da177e4 LT |
477 | } |
478 | setup_counts[index] = b; | |
479 | ||
480 | /* | |
481 | * Get the active/recovery counts | |
482 | */ | |
483 | b = get_cmd640_reg(drwtim_regs[index]); | |
484 | active_counts[index] = (b >> 4) ? (b >> 4) : 0x10; | |
485 | recovery_counts[index] = (b & 0x0f) ? (b & 0x0f) : 0x10; | |
486 | } | |
487 | ||
488 | ||
489 | /* | |
490 | * This routine writes the prepared setup/active/recovery counts | |
491 | * for a drive into the cmd640 chipset registers to active them. | |
492 | */ | |
9523076a | 493 | static void program_drive_counts(ide_drive_t *drive, unsigned int index) |
1da177e4 LT |
494 | { |
495 | unsigned long flags; | |
496 | u8 setup_count = setup_counts[index]; | |
497 | u8 active_count = active_counts[index]; | |
498 | u8 recovery_count = recovery_counts[index]; | |
499 | ||
500 | /* | |
501 | * Set up address setup count and drive read/write timing registers. | |
502 | * Primary interface has individual count/timing registers for | |
503 | * each drive. Secondary interface has one common set of registers, | |
504 | * so we merge the timings, using the slowest value for each timing. | |
505 | */ | |
506 | if (index > 1) { | |
9523076a BZ |
507 | ide_hwif_t *hwif = drive->hwif; |
508 | ide_drive_t *peer = &hwif->drives[!drive->select.b.unit]; | |
509 | unsigned int mate = index ^ 1; | |
510 | ||
511 | if (peer->present) { | |
1da177e4 LT |
512 | if (setup_count < setup_counts[mate]) |
513 | setup_count = setup_counts[mate]; | |
514 | if (active_count < active_counts[mate]) | |
515 | active_count = active_counts[mate]; | |
516 | if (recovery_count < recovery_counts[mate]) | |
517 | recovery_count = recovery_counts[mate]; | |
518 | } | |
519 | } | |
520 | ||
521 | /* | |
522 | * Convert setup_count to internal chipset representation | |
523 | */ | |
524 | switch (setup_count) { | |
4752b5e7 PC |
525 | case 4: setup_count = 0x00; break; |
526 | case 3: setup_count = 0x80; break; | |
527 | case 1: | |
528 | case 2: setup_count = 0x40; break; | |
529 | default: setup_count = 0xc0; /* case 5 */ | |
1da177e4 LT |
530 | } |
531 | ||
532 | /* | |
533 | * Now that everything is ready, program the new timings | |
534 | */ | |
5bbcf924 | 535 | spin_lock_irqsave(&cmd640_lock, flags); |
1da177e4 LT |
536 | /* |
537 | * Program the address_setup clocks into ARTTIM reg, | |
538 | * and then the active/recovery counts into the DRWTIM reg | |
539 | * (this converts counts of 16 into counts of zero -- okay). | |
540 | */ | |
541 | setup_count |= __get_cmd640_reg(arttim_regs[index]) & 0x3f; | |
542 | __put_cmd640_reg(arttim_regs[index], setup_count); | |
543 | __put_cmd640_reg(drwtim_regs[index], pack_nibbles(active_count, recovery_count)); | |
5bbcf924 | 544 | spin_unlock_irqrestore(&cmd640_lock, flags); |
1da177e4 LT |
545 | } |
546 | ||
547 | /* | |
548 | * Set a specific pio_mode for a drive | |
549 | */ | |
9523076a BZ |
550 | static void cmd640_set_mode(ide_drive_t *drive, unsigned int index, |
551 | u8 pio_mode, unsigned int cycle_time) | |
1da177e4 LT |
552 | { |
553 | int setup_time, active_time, recovery_time, clock_time; | |
554 | u8 setup_count, active_count, recovery_count, recovery_count2, cycle_count; | |
ebae41a5 BZ |
555 | int bus_speed; |
556 | ||
557 | if (cmd640_vlb && ide_vlb_clk) | |
558 | bus_speed = ide_vlb_clk; | |
559 | else if (!cmd640_vlb && ide_pci_clk) | |
560 | bus_speed = ide_pci_clk; | |
561 | else | |
562 | bus_speed = system_bus_clock(); | |
1da177e4 LT |
563 | |
564 | if (pio_mode > 5) | |
565 | pio_mode = 5; | |
566 | setup_time = ide_pio_timings[pio_mode].setup_time; | |
567 | active_time = ide_pio_timings[pio_mode].active_time; | |
568 | recovery_time = cycle_time - (setup_time + active_time); | |
569 | clock_time = 1000 / bus_speed; | |
00fe8b7a | 570 | cycle_count = DIV_ROUND_UP(cycle_time, clock_time); |
1da177e4 | 571 | |
00fe8b7a | 572 | setup_count = DIV_ROUND_UP(setup_time, clock_time); |
1da177e4 | 573 | |
00fe8b7a | 574 | active_count = DIV_ROUND_UP(active_time, clock_time); |
1da177e4 LT |
575 | if (active_count < 2) |
576 | active_count = 2; /* minimum allowed by cmd640 */ | |
577 | ||
00fe8b7a | 578 | recovery_count = DIV_ROUND_UP(recovery_time, clock_time); |
1da177e4 LT |
579 | recovery_count2 = cycle_count - (setup_count + active_count); |
580 | if (recovery_count2 > recovery_count) | |
581 | recovery_count = recovery_count2; | |
582 | if (recovery_count < 2) | |
583 | recovery_count = 2; /* minimum allowed by cmd640 */ | |
584 | if (recovery_count > 17) { | |
585 | active_count += recovery_count - 17; | |
586 | recovery_count = 17; | |
587 | } | |
588 | if (active_count > 16) | |
589 | active_count = 16; /* maximum allowed by cmd640 */ | |
590 | if (cmd640_chip_version > 1) | |
591 | recovery_count -= 1; /* cmd640b uses (count + 1)*/ | |
592 | if (recovery_count > 16) | |
593 | recovery_count = 16; /* maximum allowed by cmd640 */ | |
594 | ||
595 | setup_counts[index] = setup_count; | |
596 | active_counts[index] = active_count; | |
597 | recovery_counts[index] = recovery_count; | |
598 | ||
599 | /* | |
600 | * In a perfect world, we might set the drive pio mode here | |
601 | * (using WIN_SETFEATURE) before continuing. | |
602 | * | |
603 | * But we do not, because: | |
604 | * 1) this is the wrong place to do it (proper is do_special() in ide.c) | |
605 | * 2) in practice this is rarely, if ever, necessary | |
606 | */ | |
9523076a | 607 | program_drive_counts(drive, index); |
1da177e4 LT |
608 | } |
609 | ||
26bcb879 | 610 | static void cmd640_set_pio_mode(ide_drive_t *drive, const u8 pio) |
1da177e4 | 611 | { |
7dd00083 | 612 | unsigned int index = 0, cycle_time; |
1da177e4 | 613 | u8 b; |
1da177e4 | 614 | |
26bcb879 | 615 | switch (pio) { |
4752b5e7 PC |
616 | case 6: /* set fast-devsel off */ |
617 | case 7: /* set fast-devsel on */ | |
618 | b = get_cmd640_reg(CNTRL) & ~0x27; | |
619 | if (pio & 1) | |
620 | b |= 0x27; | |
621 | put_cmd640_reg(CNTRL, b); | |
622 | printk("%s: %sabled cmd640 fast host timing (devsel)\n", | |
623 | drive->name, (pio & 1) ? "en" : "dis"); | |
624 | return; | |
625 | case 8: /* set prefetch off */ | |
626 | case 9: /* set prefetch on */ | |
627 | set_prefetch_mode(drive, index, pio & 1); | |
628 | printk("%s: %sabled cmd640 prefetch\n", | |
629 | drive->name, (pio & 1) ? "en" : "dis"); | |
630 | return; | |
1da177e4 LT |
631 | } |
632 | ||
26bcb879 | 633 | cycle_time = ide_pio_cycle_time(drive, pio); |
9523076a | 634 | cmd640_set_mode(drive, index, pio, cycle_time); |
1da177e4 | 635 | |
342cdb6d | 636 | printk("%s: selected cmd640 PIO mode%d (%dns)", |
26bcb879 | 637 | drive->name, pio, cycle_time); |
342cdb6d | 638 | |
1da177e4 | 639 | display_clocks(index); |
1da177e4 LT |
640 | } |
641 | ||
ac95beed BZ |
642 | static const struct ide_port_ops cmd640_port_ops = { |
643 | .set_pio_mode = cmd640_set_pio_mode, | |
644 | }; | |
1da177e4 LT |
645 | #endif /* CONFIG_BLK_DEV_CMD640_ENHANCED */ |
646 | ||
647 | static int pci_conf1(void) | |
648 | { | |
1da177e4 | 649 | unsigned long flags; |
5bbcf924 | 650 | u32 tmp; |
1da177e4 | 651 | |
5bbcf924 | 652 | spin_lock_irqsave(&cmd640_lock, flags); |
1da177e4 LT |
653 | outb(0x01, 0xCFB); |
654 | tmp = inl(0xCF8); | |
655 | outl(0x80000000, 0xCF8); | |
656 | if (inl(0xCF8) == 0x80000000) { | |
657 | outl(tmp, 0xCF8); | |
5bbcf924 | 658 | spin_unlock_irqrestore(&cmd640_lock, flags); |
1da177e4 LT |
659 | return 1; |
660 | } | |
661 | outl(tmp, 0xCF8); | |
5bbcf924 | 662 | spin_unlock_irqrestore(&cmd640_lock, flags); |
1da177e4 LT |
663 | return 0; |
664 | } | |
665 | ||
666 | static int pci_conf2(void) | |
667 | { | |
668 | unsigned long flags; | |
669 | ||
5bbcf924 | 670 | spin_lock_irqsave(&cmd640_lock, flags); |
1da177e4 LT |
671 | outb(0x00, 0xCFB); |
672 | outb(0x00, 0xCF8); | |
673 | outb(0x00, 0xCFA); | |
674 | if (inb(0xCF8) == 0x00 && inb(0xCF8) == 0x00) { | |
5bbcf924 | 675 | spin_unlock_irqrestore(&cmd640_lock, flags); |
1da177e4 LT |
676 | return 1; |
677 | } | |
5bbcf924 | 678 | spin_unlock_irqrestore(&cmd640_lock, flags); |
1da177e4 LT |
679 | return 0; |
680 | } | |
681 | ||
c413b9b9 BZ |
682 | static const struct ide_port_info cmd640_port_info __initdata = { |
683 | .chipset = ide_cmd640, | |
684 | .host_flags = IDE_HFLAG_SERIALIZE | | |
685 | IDE_HFLAG_NO_DMA | | |
686 | IDE_HFLAG_NO_AUTOTUNE | | |
687 | IDE_HFLAG_ABUSE_PREFETCH | | |
688 | IDE_HFLAG_ABUSE_FAST_DEVSEL, | |
689 | #ifdef CONFIG_BLK_DEV_CMD640_ENHANCED | |
ac95beed | 690 | .port_ops = &cmd640_port_ops, |
c413b9b9 BZ |
691 | .pio_mask = ATA_PIO5, |
692 | #endif | |
693 | }; | |
694 | ||
7ebe5936 BZ |
695 | static int cmd640x_init_one(unsigned long base, unsigned long ctl) |
696 | { | |
697 | if (!request_region(base, 8, DRV_NAME)) { | |
698 | printk(KERN_ERR "%s: I/O resource 0x%lX-0x%lX not free.\n", | |
699 | DRV_NAME, base, base + 7); | |
700 | return -EBUSY; | |
701 | } | |
702 | ||
703 | if (!request_region(ctl, 1, DRV_NAME)) { | |
704 | printk(KERN_ERR "%s: I/O resource 0x%lX not free.\n", | |
705 | DRV_NAME, ctl); | |
706 | release_region(base, 8); | |
707 | return -EBUSY; | |
708 | } | |
709 | ||
710 | return 0; | |
711 | } | |
712 | ||
1da177e4 | 713 | /* |
ade2daf9 | 714 | * Probe for a cmd640 chipset, and initialize it if found. |
1da177e4 | 715 | */ |
ade2daf9 | 716 | static int __init cmd640x_init(void) |
1da177e4 LT |
717 | { |
718 | #ifdef CONFIG_BLK_DEV_CMD640_ENHANCED | |
719 | int second_port_toggled = 0; | |
720 | #endif /* CONFIG_BLK_DEV_CMD640_ENHANCED */ | |
7ebe5936 | 721 | int second_port_cmd640 = 0, rc; |
1da177e4 LT |
722 | const char *bus_type, *port2; |
723 | unsigned int index; | |
724 | u8 b, cfr; | |
8ac4ce74 | 725 | u8 idx[4] = { 0xff, 0xff, 0xff, 0xff }; |
6d3803b6 | 726 | hw_regs_t hw[2]; |
1da177e4 LT |
727 | |
728 | if (cmd640_vlb && probe_for_cmd640_vlb()) { | |
729 | bus_type = "VLB"; | |
730 | } else { | |
731 | cmd640_vlb = 0; | |
732 | /* Find out what kind of PCI probing is supported otherwise | |
733 | Justin Gibbs will sulk.. */ | |
734 | if (pci_conf1() && probe_for_cmd640_pci1()) | |
735 | bus_type = "PCI (type1)"; | |
736 | else if (pci_conf2() && probe_for_cmd640_pci2()) | |
737 | bus_type = "PCI (type2)"; | |
738 | else | |
739 | return 0; | |
740 | } | |
741 | /* | |
742 | * Undocumented magic (there is no 0x5b reg in specs) | |
743 | */ | |
744 | put_cmd640_reg(0x5b, 0xbd); | |
745 | if (get_cmd640_reg(0x5b) != 0xbd) { | |
746 | printk(KERN_ERR "ide: cmd640 init failed: wrong value in reg 0x5b\n"); | |
747 | return 0; | |
748 | } | |
749 | put_cmd640_reg(0x5b, 0); | |
750 | ||
751 | #ifdef CMD640_DUMP_REGS | |
752 | cmd640_dump_regs(); | |
753 | #endif | |
754 | ||
755 | /* | |
756 | * Documented magic begins here | |
757 | */ | |
758 | cfr = get_cmd640_reg(CFR); | |
759 | cmd640_chip_version = cfr & CFR_DEVREV; | |
760 | if (cmd640_chip_version == 0) { | |
4752b5e7 | 761 | printk("ide: bad cmd640 revision: %d\n", cmd640_chip_version); |
1da177e4 LT |
762 | return 0; |
763 | } | |
764 | ||
7ebe5936 BZ |
765 | rc = cmd640x_init_one(0x1f0, 0x3f6); |
766 | if (rc) | |
767 | return rc; | |
768 | ||
769 | rc = cmd640x_init_one(0x170, 0x376); | |
770 | if (rc) { | |
771 | release_region(0x3f6, 1); | |
772 | release_region(0x1f0, 8); | |
773 | return rc; | |
774 | } | |
775 | ||
6d3803b6 BZ |
776 | memset(&hw, 0, sizeof(hw)); |
777 | ||
778 | ide_std_init_ports(&hw[0], 0x1f0, 0x3f6); | |
779 | hw[0].irq = 14; | |
780 | ||
781 | ide_std_init_ports(&hw[1], 0x170, 0x376); | |
782 | hw[1].irq = 15; | |
783 | ||
784 | printk(KERN_INFO "cmd640: buggy cmd640%c interface on %s, config=0x%02x" | |
785 | "\n", 'a' + cmd640_chip_version - 1, bus_type, cfr); | |
786 | ||
84f05df4 | 787 | cmd_hwif0 = ide_find_port(); |
9523076a | 788 | |
1da177e4 LT |
789 | /* |
790 | * Initialize data for primary port | |
791 | */ | |
84f05df4 BZ |
792 | if (cmd_hwif0) { |
793 | ide_init_port_hw(cmd_hwif0, &hw[0]); | |
84f05df4 BZ |
794 | idx[0] = cmd_hwif0->index; |
795 | } | |
8ac4ce74 | 796 | |
1da177e4 LT |
797 | /* |
798 | * Ensure compatibility by always using the slowest timings | |
799 | * for access to the drive's command register block, | |
800 | * and reset the prefetch burstsize to default (512 bytes). | |
801 | * | |
802 | * Maybe we need a way to NOT do these on *some* systems? | |
803 | */ | |
804 | put_cmd640_reg(CMDTIM, 0); | |
805 | put_cmd640_reg(BRST, 0x40); | |
806 | ||
84f05df4 BZ |
807 | cmd_hwif1 = ide_find_port(); |
808 | ||
1da177e4 LT |
809 | /* |
810 | * Try to enable the secondary interface, if not already enabled | |
811 | */ | |
84f05df4 BZ |
812 | if (cmd_hwif1 && |
813 | cmd_hwif1->drives[0].noprobe && cmd_hwif1->drives[1].noprobe) { | |
1da177e4 LT |
814 | port2 = "not probed"; |
815 | } else { | |
816 | b = get_cmd640_reg(CNTRL); | |
817 | if (secondary_port_responding()) { | |
818 | if ((b & CNTRL_ENA_2ND)) { | |
819 | second_port_cmd640 = 1; | |
820 | port2 = "okay"; | |
821 | } else if (cmd640_vlb) { | |
822 | second_port_cmd640 = 1; | |
823 | port2 = "alive"; | |
824 | } else | |
825 | port2 = "not cmd640"; | |
826 | } else { | |
827 | put_cmd640_reg(CNTRL, b ^ CNTRL_ENA_2ND); /* toggle the bit */ | |
828 | if (secondary_port_responding()) { | |
829 | second_port_cmd640 = 1; | |
830 | #ifdef CONFIG_BLK_DEV_CMD640_ENHANCED | |
831 | second_port_toggled = 1; | |
832 | #endif /* CONFIG_BLK_DEV_CMD640_ENHANCED */ | |
833 | port2 = "enabled"; | |
834 | } else { | |
835 | put_cmd640_reg(CNTRL, b); /* restore original setting */ | |
836 | port2 = "not responding"; | |
837 | } | |
838 | } | |
839 | } | |
840 | ||
841 | /* | |
842 | * Initialize data for secondary cmd640 port, if enabled | |
843 | */ | |
84f05df4 | 844 | if (second_port_cmd640 && cmd_hwif1) { |
6d3803b6 | 845 | ide_init_port_hw(cmd_hwif1, &hw[1]); |
8ac4ce74 | 846 | idx[1] = cmd_hwif1->index; |
1da177e4 | 847 | } |
84f05df4 | 848 | printk(KERN_INFO "cmd640: %sserialized, secondary interface %s\n", |
c413b9b9 | 849 | second_port_cmd640 ? "" : "not ", port2); |
1da177e4 LT |
850 | |
851 | /* | |
852 | * Establish initial timings/prefetch for all drives. | |
853 | * Do not unnecessarily disturb any prior BIOS setup of these. | |
854 | */ | |
855 | for (index = 0; index < (2 + (second_port_cmd640 << 1)); index++) { | |
9523076a BZ |
856 | ide_drive_t *drive; |
857 | ||
84f05df4 BZ |
858 | if (index > 1) { |
859 | if (cmd_hwif1 == NULL) | |
860 | continue; | |
9523076a | 861 | drive = &cmd_hwif1->drives[index & 1]; |
84f05df4 BZ |
862 | } else { |
863 | if (cmd_hwif0 == NULL) | |
864 | continue; | |
9523076a | 865 | drive = &cmd_hwif0->drives[index & 1]; |
84f05df4 | 866 | } |
9523076a | 867 | |
1da177e4 LT |
868 | #ifdef CONFIG_BLK_DEV_CMD640_ENHANCED |
869 | if (drive->autotune || ((index > 1) && second_port_toggled)) { | |
4752b5e7 PC |
870 | /* |
871 | * Reset timing to the slowest speed and turn off | |
872 | * prefetch. This way, the drive identify code has | |
873 | * a better chance. | |
1da177e4 LT |
874 | */ |
875 | setup_counts [index] = 4; /* max possible */ | |
876 | active_counts [index] = 16; /* max possible */ | |
877 | recovery_counts [index] = 16; /* max possible */ | |
9523076a BZ |
878 | program_drive_counts(drive, index); |
879 | set_prefetch_mode(drive, index, 0); | |
1da177e4 LT |
880 | printk("cmd640: drive%d timings/prefetch cleared\n", index); |
881 | } else { | |
882 | /* | |
883 | * Record timings/prefetch without changing them. | |
884 | * This preserves any prior BIOS setup. | |
885 | */ | |
886 | retrieve_drive_counts (index); | |
9523076a | 887 | check_prefetch(drive, index); |
1da177e4 LT |
888 | printk("cmd640: drive%d timings/prefetch(%s) preserved", |
889 | index, drive->no_io_32bit ? "off" : "on"); | |
890 | display_clocks(index); | |
891 | } | |
892 | #else | |
893 | /* | |
894 | * Set the drive unmask flags to match the prefetch setting | |
895 | */ | |
9523076a | 896 | check_prefetch(drive, index); |
1da177e4 LT |
897 | printk("cmd640: drive%d timings/prefetch(%s) preserved\n", |
898 | index, drive->no_io_32bit ? "off" : "on"); | |
899 | #endif /* CONFIG_BLK_DEV_CMD640_ENHANCED */ | |
900 | } | |
901 | ||
902 | #ifdef CMD640_DUMP_REGS | |
903 | cmd640_dump_regs(); | |
904 | #endif | |
8ac4ce74 | 905 | |
c413b9b9 | 906 | ide_device_add(idx, &cmd640_port_info); |
8ac4ce74 | 907 | |
1da177e4 LT |
908 | return 1; |
909 | } | |
910 | ||
ade2daf9 BZ |
911 | module_param_named(probe_vlb, cmd640_vlb, bool, 0); |
912 | MODULE_PARM_DESC(probe_vlb, "probe for VLB version of CMD640 chipset"); | |
913 | ||
914 | module_init(cmd640x_init); | |
776c0bce AB |
915 | |
916 | MODULE_LICENSE("GPL"); |