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26717172 LB |
1 | /* |
2 | * intel_idle.c - native hardware idle loop for modern Intel processors | |
3 | * | |
fab04b22 | 4 | * Copyright (c) 2013, Intel Corporation. |
26717172 LB |
5 | * Len Brown <len.brown@intel.com> |
6 | * | |
7 | * This program is free software; you can redistribute it and/or modify it | |
8 | * under the terms and conditions of the GNU General Public License, | |
9 | * version 2, as published by the Free Software Foundation. | |
10 | * | |
11 | * This program is distributed in the hope it will be useful, but WITHOUT | |
12 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
13 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
14 | * more details. | |
15 | * | |
16 | * You should have received a copy of the GNU General Public License along with | |
17 | * this program; if not, write to the Free Software Foundation, Inc., | |
18 | * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. | |
19 | */ | |
20 | ||
21 | /* | |
22 | * intel_idle is a cpuidle driver that loads on specific Intel processors | |
23 | * in lieu of the legacy ACPI processor_idle driver. The intent is to | |
24 | * make Linux more efficient on these processors, as intel_idle knows | |
25 | * more than ACPI, as well as make Linux more immune to ACPI BIOS bugs. | |
26 | */ | |
27 | ||
28 | /* | |
29 | * Design Assumptions | |
30 | * | |
31 | * All CPUs have same idle states as boot CPU | |
32 | * | |
33 | * Chipset BM_STS (bus master status) bit is a NOP | |
34 | * for preventing entry into deep C-stats | |
35 | */ | |
36 | ||
37 | /* | |
38 | * Known limitations | |
39 | * | |
40 | * The driver currently initializes for_each_online_cpu() upon modprobe. | |
41 | * It it unaware of subsequent processors hot-added to the system. | |
42 | * This means that if you boot with maxcpus=n and later online | |
43 | * processors above n, those processors will use C1 only. | |
44 | * | |
45 | * ACPI has a .suspend hack to turn off deep c-statees during suspend | |
46 | * to avoid complications with the lapic timer workaround. | |
47 | * Have not seen issues with suspend, but may need same workaround here. | |
48 | * | |
26717172 LB |
49 | */ |
50 | ||
51 | /* un-comment DEBUG to enable pr_debug() statements */ | |
52 | #define DEBUG | |
53 | ||
54 | #include <linux/kernel.h> | |
55 | #include <linux/cpuidle.h> | |
76962caa | 56 | #include <linux/tick.h> |
26717172 LB |
57 | #include <trace/events/power.h> |
58 | #include <linux/sched.h> | |
2a2d31c8 SL |
59 | #include <linux/notifier.h> |
60 | #include <linux/cpu.h> | |
02c4fae9 | 61 | #include <linux/moduleparam.h> |
b66b8b9a | 62 | #include <asm/cpu_device_id.h> |
db73c5a8 | 63 | #include <asm/intel-family.h> |
bc83cccc | 64 | #include <asm/mwait.h> |
14796fca | 65 | #include <asm/msr.h> |
26717172 | 66 | |
d70e28f5 | 67 | #define INTEL_IDLE_VERSION "0.4.1" |
26717172 LB |
68 | #define PREFIX "intel_idle: " |
69 | ||
26717172 LB |
70 | static struct cpuidle_driver intel_idle_driver = { |
71 | .name = "intel_idle", | |
72 | .owner = THIS_MODULE, | |
73 | }; | |
74 | /* intel_idle.max_cstate=0 disables driver */ | |
137ecc77 | 75 | static int max_cstate = CPUIDLE_STATE_MAX - 1; |
26717172 | 76 | |
c4236282 | 77 | static unsigned int mwait_substates; |
26717172 | 78 | |
2a2d31c8 | 79 | #define LAPIC_TIMER_ALWAYS_RELIABLE 0xFFFFFFFF |
26717172 | 80 | /* Reliable LAPIC Timer States, bit 1 for C1 etc. */ |
d13780d4 | 81 | static unsigned int lapic_timer_reliable_states = (1 << 1); /* Default to only C1 */ |
26717172 | 82 | |
b66b8b9a AK |
83 | struct idle_cpu { |
84 | struct cpuidle_state *state_table; | |
85 | ||
86 | /* | |
87 | * Hardware C-state auto-demotion may not always be optimal. | |
88 | * Indicate which enable bits to clear here. | |
89 | */ | |
90 | unsigned long auto_demotion_disable_flags; | |
8c058d53 | 91 | bool byt_auto_demotion_disable_flag; |
32e95180 | 92 | bool disable_promotion_to_c1e; |
b66b8b9a AK |
93 | }; |
94 | ||
95 | static const struct idle_cpu *icpu; | |
3265eba0 | 96 | static struct cpuidle_device __percpu *intel_idle_cpuidle_devices; |
46bcfad7 DD |
97 | static int intel_idle(struct cpuidle_device *dev, |
98 | struct cpuidle_driver *drv, int index); | |
5fe2e527 RW |
99 | static void intel_idle_freeze(struct cpuidle_device *dev, |
100 | struct cpuidle_driver *drv, int index); | |
26717172 LB |
101 | static struct cpuidle_state *cpuidle_state_table; |
102 | ||
956d033f LB |
103 | /* |
104 | * Set this flag for states where the HW flushes the TLB for us | |
105 | * and so we don't need cross-calls to keep it consistent. | |
106 | * If this flag is set, SW flushes the TLB, so even if the | |
107 | * HW doesn't do the flushing, this flag is safe to use. | |
108 | */ | |
109 | #define CPUIDLE_FLAG_TLB_FLUSHED 0x10000 | |
110 | ||
b1beab48 LB |
111 | /* |
112 | * MWAIT takes an 8-bit "hint" in EAX "suggesting" | |
113 | * the C-state (top nibble) and sub-state (bottom nibble) | |
114 | * 0x00 means "MWAIT(C1)", 0x10 means "MWAIT(C2)" etc. | |
115 | * | |
116 | * We store the hint at the top of our "flags" for each state. | |
117 | */ | |
118 | #define flg2MWAIT(flags) (((flags) >> 24) & 0xFF) | |
119 | #define MWAIT2flg(eax) ((eax & 0xFF) << 24) | |
120 | ||
26717172 LB |
121 | /* |
122 | * States are indexed by the cstate number, | |
123 | * which is also the index into the MWAIT hint array. | |
124 | * Thus C0 is a dummy. | |
125 | */ | |
ba0dc81e | 126 | static struct cpuidle_state nehalem_cstates[] = { |
e022e7eb | 127 | { |
de09cdd0 | 128 | .name = "C1", |
26717172 | 129 | .desc = "MWAIT 0x00", |
b82b6cca | 130 | .flags = MWAIT2flg(0x00), |
26717172 | 131 | .exit_latency = 3, |
26717172 | 132 | .target_residency = 6, |
5fe2e527 RW |
133 | .enter = &intel_idle, |
134 | .enter_freeze = intel_idle_freeze, }, | |
32e95180 | 135 | { |
de09cdd0 | 136 | .name = "C1E", |
32e95180 | 137 | .desc = "MWAIT 0x01", |
b82b6cca | 138 | .flags = MWAIT2flg(0x01), |
32e95180 LB |
139 | .exit_latency = 10, |
140 | .target_residency = 20, | |
5fe2e527 RW |
141 | .enter = &intel_idle, |
142 | .enter_freeze = intel_idle_freeze, }, | |
e022e7eb | 143 | { |
de09cdd0 | 144 | .name = "C3", |
26717172 | 145 | .desc = "MWAIT 0x10", |
b82b6cca | 146 | .flags = MWAIT2flg(0x10) | CPUIDLE_FLAG_TLB_FLUSHED, |
26717172 | 147 | .exit_latency = 20, |
26717172 | 148 | .target_residency = 80, |
5fe2e527 RW |
149 | .enter = &intel_idle, |
150 | .enter_freeze = intel_idle_freeze, }, | |
e022e7eb | 151 | { |
de09cdd0 | 152 | .name = "C6", |
26717172 | 153 | .desc = "MWAIT 0x20", |
b82b6cca | 154 | .flags = MWAIT2flg(0x20) | CPUIDLE_FLAG_TLB_FLUSHED, |
26717172 | 155 | .exit_latency = 200, |
26717172 | 156 | .target_residency = 800, |
5fe2e527 RW |
157 | .enter = &intel_idle, |
158 | .enter_freeze = intel_idle_freeze, }, | |
e022e7eb LB |
159 | { |
160 | .enter = NULL } | |
26717172 LB |
161 | }; |
162 | ||
ba0dc81e | 163 | static struct cpuidle_state snb_cstates[] = { |
e022e7eb | 164 | { |
de09cdd0 | 165 | .name = "C1", |
d13780d4 | 166 | .desc = "MWAIT 0x00", |
b82b6cca | 167 | .flags = MWAIT2flg(0x00), |
32e95180 LB |
168 | .exit_latency = 2, |
169 | .target_residency = 2, | |
5fe2e527 RW |
170 | .enter = &intel_idle, |
171 | .enter_freeze = intel_idle_freeze, }, | |
32e95180 | 172 | { |
de09cdd0 | 173 | .name = "C1E", |
32e95180 | 174 | .desc = "MWAIT 0x01", |
b82b6cca | 175 | .flags = MWAIT2flg(0x01), |
32e95180 LB |
176 | .exit_latency = 10, |
177 | .target_residency = 20, | |
5fe2e527 RW |
178 | .enter = &intel_idle, |
179 | .enter_freeze = intel_idle_freeze, }, | |
e022e7eb | 180 | { |
de09cdd0 | 181 | .name = "C3", |
d13780d4 | 182 | .desc = "MWAIT 0x10", |
b82b6cca | 183 | .flags = MWAIT2flg(0x10) | CPUIDLE_FLAG_TLB_FLUSHED, |
d13780d4 | 184 | .exit_latency = 80, |
ddbd550d | 185 | .target_residency = 211, |
5fe2e527 RW |
186 | .enter = &intel_idle, |
187 | .enter_freeze = intel_idle_freeze, }, | |
e022e7eb | 188 | { |
de09cdd0 | 189 | .name = "C6", |
d13780d4 | 190 | .desc = "MWAIT 0x20", |
b82b6cca | 191 | .flags = MWAIT2flg(0x20) | CPUIDLE_FLAG_TLB_FLUSHED, |
d13780d4 | 192 | .exit_latency = 104, |
ddbd550d | 193 | .target_residency = 345, |
5fe2e527 RW |
194 | .enter = &intel_idle, |
195 | .enter_freeze = intel_idle_freeze, }, | |
e022e7eb | 196 | { |
de09cdd0 | 197 | .name = "C7", |
d13780d4 | 198 | .desc = "MWAIT 0x30", |
b82b6cca | 199 | .flags = MWAIT2flg(0x30) | CPUIDLE_FLAG_TLB_FLUSHED, |
d13780d4 | 200 | .exit_latency = 109, |
ddbd550d | 201 | .target_residency = 345, |
5fe2e527 RW |
202 | .enter = &intel_idle, |
203 | .enter_freeze = intel_idle_freeze, }, | |
e022e7eb LB |
204 | { |
205 | .enter = NULL } | |
d13780d4 LB |
206 | }; |
207 | ||
718987d6 LB |
208 | static struct cpuidle_state byt_cstates[] = { |
209 | { | |
de09cdd0 | 210 | .name = "C1", |
718987d6 | 211 | .desc = "MWAIT 0x00", |
b82b6cca | 212 | .flags = MWAIT2flg(0x00), |
718987d6 LB |
213 | .exit_latency = 1, |
214 | .target_residency = 1, | |
5fe2e527 RW |
215 | .enter = &intel_idle, |
216 | .enter_freeze = intel_idle_freeze, }, | |
718987d6 | 217 | { |
de09cdd0 | 218 | .name = "C6N", |
718987d6 | 219 | .desc = "MWAIT 0x58", |
b82b6cca | 220 | .flags = MWAIT2flg(0x58) | CPUIDLE_FLAG_TLB_FLUSHED, |
d7ef7671 | 221 | .exit_latency = 300, |
718987d6 | 222 | .target_residency = 275, |
5fe2e527 RW |
223 | .enter = &intel_idle, |
224 | .enter_freeze = intel_idle_freeze, }, | |
718987d6 | 225 | { |
de09cdd0 | 226 | .name = "C6S", |
718987d6 | 227 | .desc = "MWAIT 0x52", |
b82b6cca | 228 | .flags = MWAIT2flg(0x52) | CPUIDLE_FLAG_TLB_FLUSHED, |
d7ef7671 | 229 | .exit_latency = 500, |
718987d6 | 230 | .target_residency = 560, |
5fe2e527 RW |
231 | .enter = &intel_idle, |
232 | .enter_freeze = intel_idle_freeze, }, | |
718987d6 | 233 | { |
de09cdd0 | 234 | .name = "C7", |
718987d6 | 235 | .desc = "MWAIT 0x60", |
b82b6cca | 236 | .flags = MWAIT2flg(0x60) | CPUIDLE_FLAG_TLB_FLUSHED, |
718987d6 | 237 | .exit_latency = 1200, |
d7ef7671 | 238 | .target_residency = 4000, |
5fe2e527 RW |
239 | .enter = &intel_idle, |
240 | .enter_freeze = intel_idle_freeze, }, | |
718987d6 | 241 | { |
de09cdd0 | 242 | .name = "C7S", |
718987d6 | 243 | .desc = "MWAIT 0x64", |
b82b6cca | 244 | .flags = MWAIT2flg(0x64) | CPUIDLE_FLAG_TLB_FLUSHED, |
718987d6 LB |
245 | .exit_latency = 10000, |
246 | .target_residency = 20000, | |
5fe2e527 RW |
247 | .enter = &intel_idle, |
248 | .enter_freeze = intel_idle_freeze, }, | |
718987d6 LB |
249 | { |
250 | .enter = NULL } | |
251 | }; | |
252 | ||
cab07a56 LB |
253 | static struct cpuidle_state cht_cstates[] = { |
254 | { | |
de09cdd0 | 255 | .name = "C1", |
cab07a56 LB |
256 | .desc = "MWAIT 0x00", |
257 | .flags = MWAIT2flg(0x00), | |
258 | .exit_latency = 1, | |
259 | .target_residency = 1, | |
260 | .enter = &intel_idle, | |
261 | .enter_freeze = intel_idle_freeze, }, | |
262 | { | |
de09cdd0 | 263 | .name = "C6N", |
cab07a56 LB |
264 | .desc = "MWAIT 0x58", |
265 | .flags = MWAIT2flg(0x58) | CPUIDLE_FLAG_TLB_FLUSHED, | |
266 | .exit_latency = 80, | |
267 | .target_residency = 275, | |
268 | .enter = &intel_idle, | |
269 | .enter_freeze = intel_idle_freeze, }, | |
270 | { | |
de09cdd0 | 271 | .name = "C6S", |
cab07a56 LB |
272 | .desc = "MWAIT 0x52", |
273 | .flags = MWAIT2flg(0x52) | CPUIDLE_FLAG_TLB_FLUSHED, | |
274 | .exit_latency = 200, | |
275 | .target_residency = 560, | |
276 | .enter = &intel_idle, | |
277 | .enter_freeze = intel_idle_freeze, }, | |
278 | { | |
de09cdd0 | 279 | .name = "C7", |
cab07a56 LB |
280 | .desc = "MWAIT 0x60", |
281 | .flags = MWAIT2flg(0x60) | CPUIDLE_FLAG_TLB_FLUSHED, | |
282 | .exit_latency = 1200, | |
283 | .target_residency = 4000, | |
284 | .enter = &intel_idle, | |
285 | .enter_freeze = intel_idle_freeze, }, | |
286 | { | |
de09cdd0 | 287 | .name = "C7S", |
cab07a56 LB |
288 | .desc = "MWAIT 0x64", |
289 | .flags = MWAIT2flg(0x64) | CPUIDLE_FLAG_TLB_FLUSHED, | |
290 | .exit_latency = 10000, | |
291 | .target_residency = 20000, | |
292 | .enter = &intel_idle, | |
293 | .enter_freeze = intel_idle_freeze, }, | |
294 | { | |
295 | .enter = NULL } | |
296 | }; | |
297 | ||
ba0dc81e | 298 | static struct cpuidle_state ivb_cstates[] = { |
e022e7eb | 299 | { |
de09cdd0 | 300 | .name = "C1", |
6edab08c | 301 | .desc = "MWAIT 0x00", |
b82b6cca | 302 | .flags = MWAIT2flg(0x00), |
6edab08c LB |
303 | .exit_latency = 1, |
304 | .target_residency = 1, | |
5fe2e527 RW |
305 | .enter = &intel_idle, |
306 | .enter_freeze = intel_idle_freeze, }, | |
32e95180 | 307 | { |
de09cdd0 | 308 | .name = "C1E", |
32e95180 | 309 | .desc = "MWAIT 0x01", |
b82b6cca | 310 | .flags = MWAIT2flg(0x01), |
32e95180 LB |
311 | .exit_latency = 10, |
312 | .target_residency = 20, | |
5fe2e527 RW |
313 | .enter = &intel_idle, |
314 | .enter_freeze = intel_idle_freeze, }, | |
e022e7eb | 315 | { |
de09cdd0 | 316 | .name = "C3", |
6edab08c | 317 | .desc = "MWAIT 0x10", |
b82b6cca | 318 | .flags = MWAIT2flg(0x10) | CPUIDLE_FLAG_TLB_FLUSHED, |
6edab08c LB |
319 | .exit_latency = 59, |
320 | .target_residency = 156, | |
5fe2e527 RW |
321 | .enter = &intel_idle, |
322 | .enter_freeze = intel_idle_freeze, }, | |
e022e7eb | 323 | { |
de09cdd0 | 324 | .name = "C6", |
6edab08c | 325 | .desc = "MWAIT 0x20", |
b82b6cca | 326 | .flags = MWAIT2flg(0x20) | CPUIDLE_FLAG_TLB_FLUSHED, |
6edab08c LB |
327 | .exit_latency = 80, |
328 | .target_residency = 300, | |
5fe2e527 RW |
329 | .enter = &intel_idle, |
330 | .enter_freeze = intel_idle_freeze, }, | |
e022e7eb | 331 | { |
de09cdd0 | 332 | .name = "C7", |
6edab08c | 333 | .desc = "MWAIT 0x30", |
b82b6cca | 334 | .flags = MWAIT2flg(0x30) | CPUIDLE_FLAG_TLB_FLUSHED, |
6edab08c LB |
335 | .exit_latency = 87, |
336 | .target_residency = 300, | |
5fe2e527 RW |
337 | .enter = &intel_idle, |
338 | .enter_freeze = intel_idle_freeze, }, | |
e022e7eb LB |
339 | { |
340 | .enter = NULL } | |
6edab08c LB |
341 | }; |
342 | ||
0138d8f0 LB |
343 | static struct cpuidle_state ivt_cstates[] = { |
344 | { | |
de09cdd0 | 345 | .name = "C1", |
0138d8f0 | 346 | .desc = "MWAIT 0x00", |
b82b6cca | 347 | .flags = MWAIT2flg(0x00), |
0138d8f0 LB |
348 | .exit_latency = 1, |
349 | .target_residency = 1, | |
5fe2e527 RW |
350 | .enter = &intel_idle, |
351 | .enter_freeze = intel_idle_freeze, }, | |
0138d8f0 | 352 | { |
de09cdd0 | 353 | .name = "C1E", |
0138d8f0 | 354 | .desc = "MWAIT 0x01", |
b82b6cca | 355 | .flags = MWAIT2flg(0x01), |
0138d8f0 LB |
356 | .exit_latency = 10, |
357 | .target_residency = 80, | |
5fe2e527 RW |
358 | .enter = &intel_idle, |
359 | .enter_freeze = intel_idle_freeze, }, | |
0138d8f0 | 360 | { |
de09cdd0 | 361 | .name = "C3", |
0138d8f0 | 362 | .desc = "MWAIT 0x10", |
b82b6cca | 363 | .flags = MWAIT2flg(0x10) | CPUIDLE_FLAG_TLB_FLUSHED, |
0138d8f0 LB |
364 | .exit_latency = 59, |
365 | .target_residency = 156, | |
5fe2e527 RW |
366 | .enter = &intel_idle, |
367 | .enter_freeze = intel_idle_freeze, }, | |
0138d8f0 | 368 | { |
de09cdd0 | 369 | .name = "C6", |
0138d8f0 | 370 | .desc = "MWAIT 0x20", |
b82b6cca | 371 | .flags = MWAIT2flg(0x20) | CPUIDLE_FLAG_TLB_FLUSHED, |
0138d8f0 LB |
372 | .exit_latency = 82, |
373 | .target_residency = 300, | |
5fe2e527 RW |
374 | .enter = &intel_idle, |
375 | .enter_freeze = intel_idle_freeze, }, | |
0138d8f0 LB |
376 | { |
377 | .enter = NULL } | |
378 | }; | |
379 | ||
380 | static struct cpuidle_state ivt_cstates_4s[] = { | |
381 | { | |
de09cdd0 | 382 | .name = "C1", |
0138d8f0 | 383 | .desc = "MWAIT 0x00", |
b82b6cca | 384 | .flags = MWAIT2flg(0x00), |
0138d8f0 LB |
385 | .exit_latency = 1, |
386 | .target_residency = 1, | |
5fe2e527 RW |
387 | .enter = &intel_idle, |
388 | .enter_freeze = intel_idle_freeze, }, | |
0138d8f0 | 389 | { |
de09cdd0 | 390 | .name = "C1E", |
0138d8f0 | 391 | .desc = "MWAIT 0x01", |
b82b6cca | 392 | .flags = MWAIT2flg(0x01), |
0138d8f0 LB |
393 | .exit_latency = 10, |
394 | .target_residency = 250, | |
5fe2e527 RW |
395 | .enter = &intel_idle, |
396 | .enter_freeze = intel_idle_freeze, }, | |
0138d8f0 | 397 | { |
de09cdd0 | 398 | .name = "C3", |
0138d8f0 | 399 | .desc = "MWAIT 0x10", |
b82b6cca | 400 | .flags = MWAIT2flg(0x10) | CPUIDLE_FLAG_TLB_FLUSHED, |
0138d8f0 LB |
401 | .exit_latency = 59, |
402 | .target_residency = 300, | |
5fe2e527 RW |
403 | .enter = &intel_idle, |
404 | .enter_freeze = intel_idle_freeze, }, | |
0138d8f0 | 405 | { |
de09cdd0 | 406 | .name = "C6", |
0138d8f0 | 407 | .desc = "MWAIT 0x20", |
b82b6cca | 408 | .flags = MWAIT2flg(0x20) | CPUIDLE_FLAG_TLB_FLUSHED, |
0138d8f0 LB |
409 | .exit_latency = 84, |
410 | .target_residency = 400, | |
5fe2e527 RW |
411 | .enter = &intel_idle, |
412 | .enter_freeze = intel_idle_freeze, }, | |
0138d8f0 LB |
413 | { |
414 | .enter = NULL } | |
415 | }; | |
416 | ||
417 | static struct cpuidle_state ivt_cstates_8s[] = { | |
418 | { | |
de09cdd0 | 419 | .name = "C1", |
0138d8f0 | 420 | .desc = "MWAIT 0x00", |
b82b6cca | 421 | .flags = MWAIT2flg(0x00), |
0138d8f0 LB |
422 | .exit_latency = 1, |
423 | .target_residency = 1, | |
5fe2e527 RW |
424 | .enter = &intel_idle, |
425 | .enter_freeze = intel_idle_freeze, }, | |
0138d8f0 | 426 | { |
de09cdd0 | 427 | .name = "C1E", |
0138d8f0 | 428 | .desc = "MWAIT 0x01", |
b82b6cca | 429 | .flags = MWAIT2flg(0x01), |
0138d8f0 LB |
430 | .exit_latency = 10, |
431 | .target_residency = 500, | |
5fe2e527 RW |
432 | .enter = &intel_idle, |
433 | .enter_freeze = intel_idle_freeze, }, | |
0138d8f0 | 434 | { |
de09cdd0 | 435 | .name = "C3", |
0138d8f0 | 436 | .desc = "MWAIT 0x10", |
b82b6cca | 437 | .flags = MWAIT2flg(0x10) | CPUIDLE_FLAG_TLB_FLUSHED, |
0138d8f0 LB |
438 | .exit_latency = 59, |
439 | .target_residency = 600, | |
5fe2e527 RW |
440 | .enter = &intel_idle, |
441 | .enter_freeze = intel_idle_freeze, }, | |
0138d8f0 | 442 | { |
de09cdd0 | 443 | .name = "C6", |
0138d8f0 | 444 | .desc = "MWAIT 0x20", |
b82b6cca | 445 | .flags = MWAIT2flg(0x20) | CPUIDLE_FLAG_TLB_FLUSHED, |
0138d8f0 LB |
446 | .exit_latency = 88, |
447 | .target_residency = 700, | |
5fe2e527 RW |
448 | .enter = &intel_idle, |
449 | .enter_freeze = intel_idle_freeze, }, | |
0138d8f0 LB |
450 | { |
451 | .enter = NULL } | |
452 | }; | |
453 | ||
ba0dc81e | 454 | static struct cpuidle_state hsw_cstates[] = { |
e022e7eb | 455 | { |
de09cdd0 | 456 | .name = "C1", |
85a4d2d4 | 457 | .desc = "MWAIT 0x00", |
b82b6cca | 458 | .flags = MWAIT2flg(0x00), |
85a4d2d4 LB |
459 | .exit_latency = 2, |
460 | .target_residency = 2, | |
5fe2e527 RW |
461 | .enter = &intel_idle, |
462 | .enter_freeze = intel_idle_freeze, }, | |
32e95180 | 463 | { |
de09cdd0 | 464 | .name = "C1E", |
32e95180 | 465 | .desc = "MWAIT 0x01", |
b82b6cca | 466 | .flags = MWAIT2flg(0x01), |
32e95180 LB |
467 | .exit_latency = 10, |
468 | .target_residency = 20, | |
5fe2e527 RW |
469 | .enter = &intel_idle, |
470 | .enter_freeze = intel_idle_freeze, }, | |
e022e7eb | 471 | { |
de09cdd0 | 472 | .name = "C3", |
85a4d2d4 | 473 | .desc = "MWAIT 0x10", |
b82b6cca | 474 | .flags = MWAIT2flg(0x10) | CPUIDLE_FLAG_TLB_FLUSHED, |
85a4d2d4 LB |
475 | .exit_latency = 33, |
476 | .target_residency = 100, | |
5fe2e527 RW |
477 | .enter = &intel_idle, |
478 | .enter_freeze = intel_idle_freeze, }, | |
e022e7eb | 479 | { |
de09cdd0 | 480 | .name = "C6", |
85a4d2d4 | 481 | .desc = "MWAIT 0x20", |
b82b6cca | 482 | .flags = MWAIT2flg(0x20) | CPUIDLE_FLAG_TLB_FLUSHED, |
85a4d2d4 LB |
483 | .exit_latency = 133, |
484 | .target_residency = 400, | |
5fe2e527 RW |
485 | .enter = &intel_idle, |
486 | .enter_freeze = intel_idle_freeze, }, | |
e022e7eb | 487 | { |
de09cdd0 | 488 | .name = "C7s", |
85a4d2d4 | 489 | .desc = "MWAIT 0x32", |
b82b6cca | 490 | .flags = MWAIT2flg(0x32) | CPUIDLE_FLAG_TLB_FLUSHED, |
85a4d2d4 LB |
491 | .exit_latency = 166, |
492 | .target_residency = 500, | |
5fe2e527 RW |
493 | .enter = &intel_idle, |
494 | .enter_freeze = intel_idle_freeze, }, | |
86239ceb | 495 | { |
de09cdd0 | 496 | .name = "C8", |
86239ceb | 497 | .desc = "MWAIT 0x40", |
b82b6cca | 498 | .flags = MWAIT2flg(0x40) | CPUIDLE_FLAG_TLB_FLUSHED, |
86239ceb LB |
499 | .exit_latency = 300, |
500 | .target_residency = 900, | |
5fe2e527 RW |
501 | .enter = &intel_idle, |
502 | .enter_freeze = intel_idle_freeze, }, | |
86239ceb | 503 | { |
de09cdd0 | 504 | .name = "C9", |
86239ceb | 505 | .desc = "MWAIT 0x50", |
b82b6cca | 506 | .flags = MWAIT2flg(0x50) | CPUIDLE_FLAG_TLB_FLUSHED, |
86239ceb LB |
507 | .exit_latency = 600, |
508 | .target_residency = 1800, | |
5fe2e527 RW |
509 | .enter = &intel_idle, |
510 | .enter_freeze = intel_idle_freeze, }, | |
86239ceb | 511 | { |
de09cdd0 | 512 | .name = "C10", |
86239ceb | 513 | .desc = "MWAIT 0x60", |
b82b6cca | 514 | .flags = MWAIT2flg(0x60) | CPUIDLE_FLAG_TLB_FLUSHED, |
86239ceb LB |
515 | .exit_latency = 2600, |
516 | .target_residency = 7700, | |
5fe2e527 RW |
517 | .enter = &intel_idle, |
518 | .enter_freeze = intel_idle_freeze, }, | |
e022e7eb LB |
519 | { |
520 | .enter = NULL } | |
85a4d2d4 | 521 | }; |
a138b568 LB |
522 | static struct cpuidle_state bdw_cstates[] = { |
523 | { | |
de09cdd0 | 524 | .name = "C1", |
a138b568 | 525 | .desc = "MWAIT 0x00", |
b82b6cca | 526 | .flags = MWAIT2flg(0x00), |
a138b568 LB |
527 | .exit_latency = 2, |
528 | .target_residency = 2, | |
5fe2e527 RW |
529 | .enter = &intel_idle, |
530 | .enter_freeze = intel_idle_freeze, }, | |
a138b568 | 531 | { |
de09cdd0 | 532 | .name = "C1E", |
a138b568 | 533 | .desc = "MWAIT 0x01", |
b82b6cca | 534 | .flags = MWAIT2flg(0x01), |
a138b568 LB |
535 | .exit_latency = 10, |
536 | .target_residency = 20, | |
5fe2e527 RW |
537 | .enter = &intel_idle, |
538 | .enter_freeze = intel_idle_freeze, }, | |
a138b568 | 539 | { |
de09cdd0 | 540 | .name = "C3", |
a138b568 | 541 | .desc = "MWAIT 0x10", |
b82b6cca | 542 | .flags = MWAIT2flg(0x10) | CPUIDLE_FLAG_TLB_FLUSHED, |
a138b568 LB |
543 | .exit_latency = 40, |
544 | .target_residency = 100, | |
5fe2e527 RW |
545 | .enter = &intel_idle, |
546 | .enter_freeze = intel_idle_freeze, }, | |
a138b568 | 547 | { |
de09cdd0 | 548 | .name = "C6", |
a138b568 | 549 | .desc = "MWAIT 0x20", |
b82b6cca | 550 | .flags = MWAIT2flg(0x20) | CPUIDLE_FLAG_TLB_FLUSHED, |
a138b568 LB |
551 | .exit_latency = 133, |
552 | .target_residency = 400, | |
5fe2e527 RW |
553 | .enter = &intel_idle, |
554 | .enter_freeze = intel_idle_freeze, }, | |
a138b568 | 555 | { |
de09cdd0 | 556 | .name = "C7s", |
a138b568 | 557 | .desc = "MWAIT 0x32", |
b82b6cca | 558 | .flags = MWAIT2flg(0x32) | CPUIDLE_FLAG_TLB_FLUSHED, |
a138b568 LB |
559 | .exit_latency = 166, |
560 | .target_residency = 500, | |
5fe2e527 RW |
561 | .enter = &intel_idle, |
562 | .enter_freeze = intel_idle_freeze, }, | |
a138b568 | 563 | { |
de09cdd0 | 564 | .name = "C8", |
a138b568 | 565 | .desc = "MWAIT 0x40", |
b82b6cca | 566 | .flags = MWAIT2flg(0x40) | CPUIDLE_FLAG_TLB_FLUSHED, |
a138b568 LB |
567 | .exit_latency = 300, |
568 | .target_residency = 900, | |
5fe2e527 RW |
569 | .enter = &intel_idle, |
570 | .enter_freeze = intel_idle_freeze, }, | |
a138b568 | 571 | { |
de09cdd0 | 572 | .name = "C9", |
a138b568 | 573 | .desc = "MWAIT 0x50", |
b82b6cca | 574 | .flags = MWAIT2flg(0x50) | CPUIDLE_FLAG_TLB_FLUSHED, |
a138b568 LB |
575 | .exit_latency = 600, |
576 | .target_residency = 1800, | |
5fe2e527 RW |
577 | .enter = &intel_idle, |
578 | .enter_freeze = intel_idle_freeze, }, | |
a138b568 | 579 | { |
de09cdd0 | 580 | .name = "C10", |
a138b568 | 581 | .desc = "MWAIT 0x60", |
b82b6cca | 582 | .flags = MWAIT2flg(0x60) | CPUIDLE_FLAG_TLB_FLUSHED, |
a138b568 LB |
583 | .exit_latency = 2600, |
584 | .target_residency = 7700, | |
5fe2e527 RW |
585 | .enter = &intel_idle, |
586 | .enter_freeze = intel_idle_freeze, }, | |
a138b568 LB |
587 | { |
588 | .enter = NULL } | |
589 | }; | |
85a4d2d4 | 590 | |
493f133f LB |
591 | static struct cpuidle_state skl_cstates[] = { |
592 | { | |
de09cdd0 | 593 | .name = "C1", |
493f133f LB |
594 | .desc = "MWAIT 0x00", |
595 | .flags = MWAIT2flg(0x00), | |
596 | .exit_latency = 2, | |
597 | .target_residency = 2, | |
598 | .enter = &intel_idle, | |
599 | .enter_freeze = intel_idle_freeze, }, | |
600 | { | |
de09cdd0 | 601 | .name = "C1E", |
493f133f LB |
602 | .desc = "MWAIT 0x01", |
603 | .flags = MWAIT2flg(0x01), | |
604 | .exit_latency = 10, | |
605 | .target_residency = 20, | |
606 | .enter = &intel_idle, | |
607 | .enter_freeze = intel_idle_freeze, }, | |
608 | { | |
de09cdd0 | 609 | .name = "C3", |
493f133f LB |
610 | .desc = "MWAIT 0x10", |
611 | .flags = MWAIT2flg(0x10) | CPUIDLE_FLAG_TLB_FLUSHED, | |
612 | .exit_latency = 70, | |
613 | .target_residency = 100, | |
614 | .enter = &intel_idle, | |
615 | .enter_freeze = intel_idle_freeze, }, | |
616 | { | |
de09cdd0 | 617 | .name = "C6", |
493f133f LB |
618 | .desc = "MWAIT 0x20", |
619 | .flags = MWAIT2flg(0x20) | CPUIDLE_FLAG_TLB_FLUSHED, | |
135919a3 | 620 | .exit_latency = 85, |
493f133f LB |
621 | .target_residency = 200, |
622 | .enter = &intel_idle, | |
623 | .enter_freeze = intel_idle_freeze, }, | |
624 | { | |
de09cdd0 | 625 | .name = "C7s", |
493f133f LB |
626 | .desc = "MWAIT 0x33", |
627 | .flags = MWAIT2flg(0x33) | CPUIDLE_FLAG_TLB_FLUSHED, | |
628 | .exit_latency = 124, | |
629 | .target_residency = 800, | |
630 | .enter = &intel_idle, | |
631 | .enter_freeze = intel_idle_freeze, }, | |
632 | { | |
de09cdd0 | 633 | .name = "C8", |
493f133f LB |
634 | .desc = "MWAIT 0x40", |
635 | .flags = MWAIT2flg(0x40) | CPUIDLE_FLAG_TLB_FLUSHED, | |
135919a3 | 636 | .exit_latency = 200, |
493f133f LB |
637 | .target_residency = 800, |
638 | .enter = &intel_idle, | |
639 | .enter_freeze = intel_idle_freeze, }, | |
135919a3 | 640 | { |
de09cdd0 | 641 | .name = "C9", |
135919a3 LB |
642 | .desc = "MWAIT 0x50", |
643 | .flags = MWAIT2flg(0x50) | CPUIDLE_FLAG_TLB_FLUSHED, | |
644 | .exit_latency = 480, | |
645 | .target_residency = 5000, | |
646 | .enter = &intel_idle, | |
647 | .enter_freeze = intel_idle_freeze, }, | |
493f133f | 648 | { |
de09cdd0 | 649 | .name = "C10", |
493f133f LB |
650 | .desc = "MWAIT 0x60", |
651 | .flags = MWAIT2flg(0x60) | CPUIDLE_FLAG_TLB_FLUSHED, | |
652 | .exit_latency = 890, | |
653 | .target_residency = 5000, | |
654 | .enter = &intel_idle, | |
655 | .enter_freeze = intel_idle_freeze, }, | |
656 | { | |
657 | .enter = NULL } | |
658 | }; | |
659 | ||
f9e71657 LB |
660 | static struct cpuidle_state skx_cstates[] = { |
661 | { | |
de09cdd0 | 662 | .name = "C1", |
f9e71657 LB |
663 | .desc = "MWAIT 0x00", |
664 | .flags = MWAIT2flg(0x00), | |
665 | .exit_latency = 2, | |
666 | .target_residency = 2, | |
667 | .enter = &intel_idle, | |
668 | .enter_freeze = intel_idle_freeze, }, | |
669 | { | |
de09cdd0 | 670 | .name = "C1E", |
f9e71657 LB |
671 | .desc = "MWAIT 0x01", |
672 | .flags = MWAIT2flg(0x01), | |
673 | .exit_latency = 10, | |
674 | .target_residency = 20, | |
675 | .enter = &intel_idle, | |
676 | .enter_freeze = intel_idle_freeze, }, | |
677 | { | |
de09cdd0 | 678 | .name = "C6", |
f9e71657 LB |
679 | .desc = "MWAIT 0x20", |
680 | .flags = MWAIT2flg(0x20) | CPUIDLE_FLAG_TLB_FLUSHED, | |
681 | .exit_latency = 133, | |
682 | .target_residency = 600, | |
683 | .enter = &intel_idle, | |
684 | .enter_freeze = intel_idle_freeze, }, | |
685 | { | |
686 | .enter = NULL } | |
687 | }; | |
688 | ||
ba0dc81e | 689 | static struct cpuidle_state atom_cstates[] = { |
e022e7eb | 690 | { |
de09cdd0 | 691 | .name = "C1E", |
26717172 | 692 | .desc = "MWAIT 0x00", |
b82b6cca | 693 | .flags = MWAIT2flg(0x00), |
32e95180 LB |
694 | .exit_latency = 10, |
695 | .target_residency = 20, | |
5fe2e527 RW |
696 | .enter = &intel_idle, |
697 | .enter_freeze = intel_idle_freeze, }, | |
e022e7eb | 698 | { |
de09cdd0 | 699 | .name = "C2", |
26717172 | 700 | .desc = "MWAIT 0x10", |
b82b6cca | 701 | .flags = MWAIT2flg(0x10), |
26717172 | 702 | .exit_latency = 20, |
26717172 | 703 | .target_residency = 80, |
5fe2e527 RW |
704 | .enter = &intel_idle, |
705 | .enter_freeze = intel_idle_freeze, }, | |
e022e7eb | 706 | { |
de09cdd0 | 707 | .name = "C4", |
26717172 | 708 | .desc = "MWAIT 0x30", |
b82b6cca | 709 | .flags = MWAIT2flg(0x30) | CPUIDLE_FLAG_TLB_FLUSHED, |
26717172 | 710 | .exit_latency = 100, |
26717172 | 711 | .target_residency = 400, |
5fe2e527 RW |
712 | .enter = &intel_idle, |
713 | .enter_freeze = intel_idle_freeze, }, | |
e022e7eb | 714 | { |
de09cdd0 | 715 | .name = "C6", |
7fcca7d9 | 716 | .desc = "MWAIT 0x52", |
b82b6cca | 717 | .flags = MWAIT2flg(0x52) | CPUIDLE_FLAG_TLB_FLUSHED, |
7fcca7d9 | 718 | .exit_latency = 140, |
7fcca7d9 | 719 | .target_residency = 560, |
5fe2e527 RW |
720 | .enter = &intel_idle, |
721 | .enter_freeze = intel_idle_freeze, }, | |
e022e7eb LB |
722 | { |
723 | .enter = NULL } | |
26717172 | 724 | }; |
5e7ec268 AS |
725 | static struct cpuidle_state tangier_cstates[] = { |
726 | { | |
de09cdd0 | 727 | .name = "C1", |
5e7ec268 AS |
728 | .desc = "MWAIT 0x00", |
729 | .flags = MWAIT2flg(0x00), | |
730 | .exit_latency = 1, | |
731 | .target_residency = 4, | |
732 | .enter = &intel_idle, | |
733 | .enter_freeze = intel_idle_freeze, }, | |
734 | { | |
de09cdd0 | 735 | .name = "C4", |
5e7ec268 AS |
736 | .desc = "MWAIT 0x30", |
737 | .flags = MWAIT2flg(0x30) | CPUIDLE_FLAG_TLB_FLUSHED, | |
738 | .exit_latency = 100, | |
739 | .target_residency = 400, | |
740 | .enter = &intel_idle, | |
741 | .enter_freeze = intel_idle_freeze, }, | |
742 | { | |
de09cdd0 | 743 | .name = "C6", |
5e7ec268 AS |
744 | .desc = "MWAIT 0x52", |
745 | .flags = MWAIT2flg(0x52) | CPUIDLE_FLAG_TLB_FLUSHED, | |
746 | .exit_latency = 140, | |
747 | .target_residency = 560, | |
748 | .enter = &intel_idle, | |
749 | .enter_freeze = intel_idle_freeze, }, | |
750 | { | |
de09cdd0 | 751 | .name = "C7", |
5e7ec268 AS |
752 | .desc = "MWAIT 0x60", |
753 | .flags = MWAIT2flg(0x60) | CPUIDLE_FLAG_TLB_FLUSHED, | |
754 | .exit_latency = 1200, | |
755 | .target_residency = 4000, | |
756 | .enter = &intel_idle, | |
757 | .enter_freeze = intel_idle_freeze, }, | |
758 | { | |
de09cdd0 | 759 | .name = "C9", |
5e7ec268 AS |
760 | .desc = "MWAIT 0x64", |
761 | .flags = MWAIT2flg(0x64) | CPUIDLE_FLAG_TLB_FLUSHED, | |
762 | .exit_latency = 10000, | |
763 | .target_residency = 20000, | |
764 | .enter = &intel_idle, | |
765 | .enter_freeze = intel_idle_freeze, }, | |
766 | { | |
767 | .enter = NULL } | |
768 | }; | |
88390996 | 769 | static struct cpuidle_state avn_cstates[] = { |
fab04b22 | 770 | { |
de09cdd0 | 771 | .name = "C1", |
fab04b22 | 772 | .desc = "MWAIT 0x00", |
b82b6cca | 773 | .flags = MWAIT2flg(0x00), |
fab04b22 LB |
774 | .exit_latency = 2, |
775 | .target_residency = 2, | |
5fe2e527 RW |
776 | .enter = &intel_idle, |
777 | .enter_freeze = intel_idle_freeze, }, | |
fab04b22 | 778 | { |
de09cdd0 | 779 | .name = "C6", |
fab04b22 | 780 | .desc = "MWAIT 0x51", |
b82b6cca | 781 | .flags = MWAIT2flg(0x51) | CPUIDLE_FLAG_TLB_FLUSHED, |
fab04b22 LB |
782 | .exit_latency = 15, |
783 | .target_residency = 45, | |
5fe2e527 RW |
784 | .enter = &intel_idle, |
785 | .enter_freeze = intel_idle_freeze, }, | |
88390996 JL |
786 | { |
787 | .enter = NULL } | |
fab04b22 | 788 | }; |
281baf7a DC |
789 | static struct cpuidle_state knl_cstates[] = { |
790 | { | |
de09cdd0 | 791 | .name = "C1", |
281baf7a DC |
792 | .desc = "MWAIT 0x00", |
793 | .flags = MWAIT2flg(0x00), | |
794 | .exit_latency = 1, | |
795 | .target_residency = 2, | |
796 | .enter = &intel_idle, | |
797 | .enter_freeze = intel_idle_freeze }, | |
798 | { | |
de09cdd0 | 799 | .name = "C6", |
281baf7a DC |
800 | .desc = "MWAIT 0x10", |
801 | .flags = MWAIT2flg(0x10) | CPUIDLE_FLAG_TLB_FLUSHED, | |
802 | .exit_latency = 120, | |
803 | .target_residency = 500, | |
804 | .enter = &intel_idle, | |
805 | .enter_freeze = intel_idle_freeze }, | |
806 | { | |
807 | .enter = NULL } | |
808 | }; | |
26717172 | 809 | |
5dcef694 LB |
810 | static struct cpuidle_state bxt_cstates[] = { |
811 | { | |
de09cdd0 | 812 | .name = "C1", |
5dcef694 LB |
813 | .desc = "MWAIT 0x00", |
814 | .flags = MWAIT2flg(0x00), | |
815 | .exit_latency = 2, | |
816 | .target_residency = 2, | |
817 | .enter = &intel_idle, | |
818 | .enter_freeze = intel_idle_freeze, }, | |
819 | { | |
de09cdd0 | 820 | .name = "C1E", |
5dcef694 LB |
821 | .desc = "MWAIT 0x01", |
822 | .flags = MWAIT2flg(0x01), | |
823 | .exit_latency = 10, | |
824 | .target_residency = 20, | |
825 | .enter = &intel_idle, | |
826 | .enter_freeze = intel_idle_freeze, }, | |
827 | { | |
de09cdd0 | 828 | .name = "C6", |
5dcef694 LB |
829 | .desc = "MWAIT 0x20", |
830 | .flags = MWAIT2flg(0x20) | CPUIDLE_FLAG_TLB_FLUSHED, | |
831 | .exit_latency = 133, | |
832 | .target_residency = 133, | |
833 | .enter = &intel_idle, | |
834 | .enter_freeze = intel_idle_freeze, }, | |
835 | { | |
de09cdd0 | 836 | .name = "C7s", |
5dcef694 LB |
837 | .desc = "MWAIT 0x31", |
838 | .flags = MWAIT2flg(0x31) | CPUIDLE_FLAG_TLB_FLUSHED, | |
839 | .exit_latency = 155, | |
840 | .target_residency = 155, | |
841 | .enter = &intel_idle, | |
842 | .enter_freeze = intel_idle_freeze, }, | |
843 | { | |
de09cdd0 | 844 | .name = "C8", |
5dcef694 LB |
845 | .desc = "MWAIT 0x40", |
846 | .flags = MWAIT2flg(0x40) | CPUIDLE_FLAG_TLB_FLUSHED, | |
847 | .exit_latency = 1000, | |
848 | .target_residency = 1000, | |
849 | .enter = &intel_idle, | |
850 | .enter_freeze = intel_idle_freeze, }, | |
851 | { | |
de09cdd0 | 852 | .name = "C9", |
5dcef694 LB |
853 | .desc = "MWAIT 0x50", |
854 | .flags = MWAIT2flg(0x50) | CPUIDLE_FLAG_TLB_FLUSHED, | |
855 | .exit_latency = 2000, | |
856 | .target_residency = 2000, | |
857 | .enter = &intel_idle, | |
858 | .enter_freeze = intel_idle_freeze, }, | |
859 | { | |
de09cdd0 | 860 | .name = "C10", |
5dcef694 LB |
861 | .desc = "MWAIT 0x60", |
862 | .flags = MWAIT2flg(0x60) | CPUIDLE_FLAG_TLB_FLUSHED, | |
863 | .exit_latency = 10000, | |
864 | .target_residency = 10000, | |
865 | .enter = &intel_idle, | |
866 | .enter_freeze = intel_idle_freeze, }, | |
867 | { | |
868 | .enter = NULL } | |
869 | }; | |
870 | ||
0080d65b JP |
871 | static struct cpuidle_state dnv_cstates[] = { |
872 | { | |
de09cdd0 | 873 | .name = "C1", |
0080d65b JP |
874 | .desc = "MWAIT 0x00", |
875 | .flags = MWAIT2flg(0x00), | |
876 | .exit_latency = 2, | |
877 | .target_residency = 2, | |
878 | .enter = &intel_idle, | |
879 | .enter_freeze = intel_idle_freeze, }, | |
880 | { | |
de09cdd0 | 881 | .name = "C1E", |
0080d65b JP |
882 | .desc = "MWAIT 0x01", |
883 | .flags = MWAIT2flg(0x01), | |
884 | .exit_latency = 10, | |
885 | .target_residency = 20, | |
886 | .enter = &intel_idle, | |
887 | .enter_freeze = intel_idle_freeze, }, | |
888 | { | |
de09cdd0 | 889 | .name = "C6", |
0080d65b JP |
890 | .desc = "MWAIT 0x20", |
891 | .flags = MWAIT2flg(0x20) | CPUIDLE_FLAG_TLB_FLUSHED, | |
892 | .exit_latency = 50, | |
893 | .target_residency = 500, | |
894 | .enter = &intel_idle, | |
895 | .enter_freeze = intel_idle_freeze, }, | |
896 | { | |
897 | .enter = NULL } | |
898 | }; | |
899 | ||
26717172 LB |
900 | /** |
901 | * intel_idle | |
902 | * @dev: cpuidle_device | |
46bcfad7 | 903 | * @drv: cpuidle driver |
e978aa7d | 904 | * @index: index of cpuidle state |
26717172 | 905 | * |
63ff07be | 906 | * Must be called under local_irq_disable(). |
26717172 | 907 | */ |
6727ad9e CM |
908 | static __cpuidle int intel_idle(struct cpuidle_device *dev, |
909 | struct cpuidle_driver *drv, int index) | |
26717172 LB |
910 | { |
911 | unsigned long ecx = 1; /* break on interrupt flag */ | |
46bcfad7 | 912 | struct cpuidle_state *state = &drv->states[index]; |
b1beab48 | 913 | unsigned long eax = flg2MWAIT(state->flags); |
26717172 | 914 | unsigned int cstate; |
26717172 LB |
915 | int cpu = smp_processor_id(); |
916 | ||
917 | cstate = (((eax) >> MWAIT_SUBSTATE_SIZE) & MWAIT_CSTATE_MASK) + 1; | |
918 | ||
6110a1f4 | 919 | /* |
c8381cc3 LB |
920 | * leave_mm() to avoid costly and often unnecessary wakeups |
921 | * for flushing the user TLB's associated with the active mm. | |
6110a1f4 | 922 | */ |
c8381cc3 | 923 | if (state->flags & CPUIDLE_FLAG_TLB_FLUSHED) |
6110a1f4 SS |
924 | leave_mm(cpu); |
925 | ||
26717172 | 926 | if (!(lapic_timer_reliable_states & (1 << (cstate)))) |
f6cee191 | 927 | tick_broadcast_enter(); |
26717172 | 928 | |
16824255 | 929 | mwait_idle_with_hints(eax, ecx); |
26717172 | 930 | |
26717172 | 931 | if (!(lapic_timer_reliable_states & (1 << (cstate)))) |
f6cee191 | 932 | tick_broadcast_exit(); |
26717172 | 933 | |
e978aa7d | 934 | return index; |
26717172 LB |
935 | } |
936 | ||
5fe2e527 RW |
937 | /** |
938 | * intel_idle_freeze - simplified "enter" callback routine for suspend-to-idle | |
939 | * @dev: cpuidle_device | |
940 | * @drv: cpuidle driver | |
941 | * @index: state index | |
942 | */ | |
943 | static void intel_idle_freeze(struct cpuidle_device *dev, | |
944 | struct cpuidle_driver *drv, int index) | |
945 | { | |
946 | unsigned long ecx = 1; /* break on interrupt flag */ | |
947 | unsigned long eax = flg2MWAIT(drv->states[index].flags); | |
948 | ||
949 | mwait_idle_with_hints(eax, ecx); | |
950 | } | |
951 | ||
fb1013a0 | 952 | static void __setup_broadcast_timer(bool on) |
2a2d31c8 | 953 | { |
76962caa TG |
954 | if (on) |
955 | tick_broadcast_enable(); | |
956 | else | |
957 | tick_broadcast_disable(); | |
2a2d31c8 SL |
958 | } |
959 | ||
fb1013a0 | 960 | static void auto_demotion_disable(void) |
14796fca LB |
961 | { |
962 | unsigned long long msr_bits; | |
963 | ||
6cfb2374 | 964 | rdmsrl(MSR_PKG_CST_CONFIG_CONTROL, msr_bits); |
b66b8b9a | 965 | msr_bits &= ~(icpu->auto_demotion_disable_flags); |
6cfb2374 | 966 | wrmsrl(MSR_PKG_CST_CONFIG_CONTROL, msr_bits); |
14796fca | 967 | } |
fb1013a0 | 968 | static void c1e_promotion_disable(void) |
32e95180 LB |
969 | { |
970 | unsigned long long msr_bits; | |
971 | ||
972 | rdmsrl(MSR_IA32_POWER_CTL, msr_bits); | |
973 | msr_bits &= ~0x2; | |
974 | wrmsrl(MSR_IA32_POWER_CTL, msr_bits); | |
975 | } | |
14796fca | 976 | |
b66b8b9a AK |
977 | static const struct idle_cpu idle_cpu_nehalem = { |
978 | .state_table = nehalem_cstates, | |
b66b8b9a | 979 | .auto_demotion_disable_flags = NHM_C1_AUTO_DEMOTE | NHM_C3_AUTO_DEMOTE, |
32e95180 | 980 | .disable_promotion_to_c1e = true, |
b66b8b9a AK |
981 | }; |
982 | ||
983 | static const struct idle_cpu idle_cpu_atom = { | |
984 | .state_table = atom_cstates, | |
985 | }; | |
986 | ||
5e7ec268 AS |
987 | static const struct idle_cpu idle_cpu_tangier = { |
988 | .state_table = tangier_cstates, | |
989 | }; | |
990 | ||
b66b8b9a AK |
991 | static const struct idle_cpu idle_cpu_lincroft = { |
992 | .state_table = atom_cstates, | |
993 | .auto_demotion_disable_flags = ATM_LNC_C6_AUTO_DEMOTE, | |
994 | }; | |
995 | ||
996 | static const struct idle_cpu idle_cpu_snb = { | |
997 | .state_table = snb_cstates, | |
32e95180 | 998 | .disable_promotion_to_c1e = true, |
b66b8b9a AK |
999 | }; |
1000 | ||
718987d6 LB |
1001 | static const struct idle_cpu idle_cpu_byt = { |
1002 | .state_table = byt_cstates, | |
1003 | .disable_promotion_to_c1e = true, | |
8c058d53 | 1004 | .byt_auto_demotion_disable_flag = true, |
718987d6 LB |
1005 | }; |
1006 | ||
cab07a56 LB |
1007 | static const struct idle_cpu idle_cpu_cht = { |
1008 | .state_table = cht_cstates, | |
1009 | .disable_promotion_to_c1e = true, | |
1010 | .byt_auto_demotion_disable_flag = true, | |
1011 | }; | |
1012 | ||
6edab08c LB |
1013 | static const struct idle_cpu idle_cpu_ivb = { |
1014 | .state_table = ivb_cstates, | |
32e95180 | 1015 | .disable_promotion_to_c1e = true, |
6edab08c LB |
1016 | }; |
1017 | ||
0138d8f0 LB |
1018 | static const struct idle_cpu idle_cpu_ivt = { |
1019 | .state_table = ivt_cstates, | |
1020 | .disable_promotion_to_c1e = true, | |
1021 | }; | |
1022 | ||
85a4d2d4 LB |
1023 | static const struct idle_cpu idle_cpu_hsw = { |
1024 | .state_table = hsw_cstates, | |
32e95180 | 1025 | .disable_promotion_to_c1e = true, |
85a4d2d4 LB |
1026 | }; |
1027 | ||
a138b568 LB |
1028 | static const struct idle_cpu idle_cpu_bdw = { |
1029 | .state_table = bdw_cstates, | |
1030 | .disable_promotion_to_c1e = true, | |
1031 | }; | |
1032 | ||
493f133f LB |
1033 | static const struct idle_cpu idle_cpu_skl = { |
1034 | .state_table = skl_cstates, | |
1035 | .disable_promotion_to_c1e = true, | |
1036 | }; | |
1037 | ||
f9e71657 LB |
1038 | static const struct idle_cpu idle_cpu_skx = { |
1039 | .state_table = skx_cstates, | |
1040 | .disable_promotion_to_c1e = true, | |
1041 | }; | |
493f133f | 1042 | |
fab04b22 LB |
1043 | static const struct idle_cpu idle_cpu_avn = { |
1044 | .state_table = avn_cstates, | |
1045 | .disable_promotion_to_c1e = true, | |
1046 | }; | |
1047 | ||
281baf7a DC |
1048 | static const struct idle_cpu idle_cpu_knl = { |
1049 | .state_table = knl_cstates, | |
1050 | }; | |
1051 | ||
5dcef694 LB |
1052 | static const struct idle_cpu idle_cpu_bxt = { |
1053 | .state_table = bxt_cstates, | |
1054 | .disable_promotion_to_c1e = true, | |
1055 | }; | |
1056 | ||
0080d65b JP |
1057 | static const struct idle_cpu idle_cpu_dnv = { |
1058 | .state_table = dnv_cstates, | |
1059 | .disable_promotion_to_c1e = true, | |
1060 | }; | |
1061 | ||
b66b8b9a AK |
1062 | #define ICPU(model, cpu) \ |
1063 | { X86_VENDOR_INTEL, 6, model, X86_FEATURE_MWAIT, (unsigned long)&cpu } | |
1064 | ||
d5cdc3c4 | 1065 | static const struct x86_cpu_id intel_idle_ids[] __initconst = { |
db73c5a8 DH |
1066 | ICPU(INTEL_FAM6_NEHALEM_EP, idle_cpu_nehalem), |
1067 | ICPU(INTEL_FAM6_NEHALEM, idle_cpu_nehalem), | |
4b3b234f | 1068 | ICPU(INTEL_FAM6_NEHALEM_G, idle_cpu_nehalem), |
db73c5a8 DH |
1069 | ICPU(INTEL_FAM6_WESTMERE, idle_cpu_nehalem), |
1070 | ICPU(INTEL_FAM6_WESTMERE_EP, idle_cpu_nehalem), | |
1071 | ICPU(INTEL_FAM6_NEHALEM_EX, idle_cpu_nehalem), | |
1072 | ICPU(INTEL_FAM6_ATOM_PINEVIEW, idle_cpu_atom), | |
1073 | ICPU(INTEL_FAM6_ATOM_LINCROFT, idle_cpu_lincroft), | |
1074 | ICPU(INTEL_FAM6_WESTMERE_EX, idle_cpu_nehalem), | |
1075 | ICPU(INTEL_FAM6_SANDYBRIDGE, idle_cpu_snb), | |
1076 | ICPU(INTEL_FAM6_SANDYBRIDGE_X, idle_cpu_snb), | |
1077 | ICPU(INTEL_FAM6_ATOM_CEDARVIEW, idle_cpu_atom), | |
1078 | ICPU(INTEL_FAM6_ATOM_SILVERMONT1, idle_cpu_byt), | |
5e7ec268 | 1079 | ICPU(INTEL_FAM6_ATOM_MERRIFIELD, idle_cpu_tangier), |
db73c5a8 DH |
1080 | ICPU(INTEL_FAM6_ATOM_AIRMONT, idle_cpu_cht), |
1081 | ICPU(INTEL_FAM6_IVYBRIDGE, idle_cpu_ivb), | |
1082 | ICPU(INTEL_FAM6_IVYBRIDGE_X, idle_cpu_ivt), | |
1083 | ICPU(INTEL_FAM6_HASWELL_CORE, idle_cpu_hsw), | |
1084 | ICPU(INTEL_FAM6_HASWELL_X, idle_cpu_hsw), | |
1085 | ICPU(INTEL_FAM6_HASWELL_ULT, idle_cpu_hsw), | |
1086 | ICPU(INTEL_FAM6_HASWELL_GT3E, idle_cpu_hsw), | |
1087 | ICPU(INTEL_FAM6_ATOM_SILVERMONT2, idle_cpu_avn), | |
1088 | ICPU(INTEL_FAM6_BROADWELL_CORE, idle_cpu_bdw), | |
1089 | ICPU(INTEL_FAM6_BROADWELL_GT3E, idle_cpu_bdw), | |
1090 | ICPU(INTEL_FAM6_BROADWELL_X, idle_cpu_bdw), | |
1091 | ICPU(INTEL_FAM6_BROADWELL_XEON_D, idle_cpu_bdw), | |
1092 | ICPU(INTEL_FAM6_SKYLAKE_MOBILE, idle_cpu_skl), | |
1093 | ICPU(INTEL_FAM6_SKYLAKE_DESKTOP, idle_cpu_skl), | |
1094 | ICPU(INTEL_FAM6_KABYLAKE_MOBILE, idle_cpu_skl), | |
1095 | ICPU(INTEL_FAM6_KABYLAKE_DESKTOP, idle_cpu_skl), | |
1096 | ICPU(INTEL_FAM6_SKYLAKE_X, idle_cpu_skx), | |
1097 | ICPU(INTEL_FAM6_XEON_PHI_KNL, idle_cpu_knl), | |
a2c1bc64 | 1098 | ICPU(INTEL_FAM6_XEON_PHI_KNM, idle_cpu_knl), |
db73c5a8 | 1099 | ICPU(INTEL_FAM6_ATOM_GOLDMONT, idle_cpu_bxt), |
0080d65b | 1100 | ICPU(INTEL_FAM6_ATOM_DENVERTON, idle_cpu_dnv), |
b66b8b9a AK |
1101 | {} |
1102 | }; | |
b66b8b9a | 1103 | |
26717172 LB |
1104 | /* |
1105 | * intel_idle_probe() | |
1106 | */ | |
00f3e755 | 1107 | static int __init intel_idle_probe(void) |
26717172 | 1108 | { |
c4236282 | 1109 | unsigned int eax, ebx, ecx; |
b66b8b9a | 1110 | const struct x86_cpu_id *id; |
26717172 LB |
1111 | |
1112 | if (max_cstate == 0) { | |
1113 | pr_debug(PREFIX "disabled\n"); | |
1114 | return -EPERM; | |
1115 | } | |
1116 | ||
b66b8b9a AK |
1117 | id = x86_match_cpu(intel_idle_ids); |
1118 | if (!id) { | |
1119 | if (boot_cpu_data.x86_vendor == X86_VENDOR_INTEL && | |
1120 | boot_cpu_data.x86 == 6) | |
1121 | pr_debug(PREFIX "does not run on family %d model %d\n", | |
1122 | boot_cpu_data.x86, boot_cpu_data.x86_model); | |
26717172 | 1123 | return -ENODEV; |
b66b8b9a | 1124 | } |
26717172 LB |
1125 | |
1126 | if (boot_cpu_data.cpuid_level < CPUID_MWAIT_LEAF) | |
1127 | return -ENODEV; | |
1128 | ||
c4236282 | 1129 | cpuid(CPUID_MWAIT_LEAF, &eax, &ebx, &ecx, &mwait_substates); |
26717172 LB |
1130 | |
1131 | if (!(ecx & CPUID5_ECX_EXTENSIONS_SUPPORTED) || | |
5c2a9f06 TR |
1132 | !(ecx & CPUID5_ECX_INTERRUPT_BREAK) || |
1133 | !mwait_substates) | |
26717172 | 1134 | return -ENODEV; |
26717172 | 1135 | |
c4236282 | 1136 | pr_debug(PREFIX "MWAIT substates: 0x%x\n", mwait_substates); |
26717172 | 1137 | |
b66b8b9a AK |
1138 | icpu = (const struct idle_cpu *)id->driver_data; |
1139 | cpuidle_state_table = icpu->state_table; | |
26717172 LB |
1140 | |
1141 | pr_debug(PREFIX "v" INTEL_IDLE_VERSION | |
1142 | " model 0x%X\n", boot_cpu_data.x86_model); | |
1143 | ||
26717172 LB |
1144 | return 0; |
1145 | } | |
1146 | ||
1147 | /* | |
1148 | * intel_idle_cpuidle_devices_uninit() | |
ca42489d | 1149 | * Unregisters the cpuidle devices. |
26717172 LB |
1150 | */ |
1151 | static void intel_idle_cpuidle_devices_uninit(void) | |
1152 | { | |
1153 | int i; | |
1154 | struct cpuidle_device *dev; | |
1155 | ||
1156 | for_each_online_cpu(i) { | |
1157 | dev = per_cpu_ptr(intel_idle_cpuidle_devices, i); | |
1158 | cpuidle_unregister_device(dev); | |
1159 | } | |
26717172 | 1160 | } |
0138d8f0 LB |
1161 | |
1162 | /* | |
d70e28f5 | 1163 | * ivt_idle_state_table_update(void) |
0138d8f0 | 1164 | * |
d70e28f5 | 1165 | * Tune IVT multi-socket targets |
0138d8f0 LB |
1166 | * Assumption: num_sockets == (max_package_num + 1) |
1167 | */ | |
d70e28f5 | 1168 | static void ivt_idle_state_table_update(void) |
0138d8f0 LB |
1169 | { |
1170 | /* IVT uses a different table for 1-2, 3-4, and > 4 sockets */ | |
d70e28f5 LB |
1171 | int cpu, package_num, num_sockets = 1; |
1172 | ||
1173 | for_each_online_cpu(cpu) { | |
1174 | package_num = topology_physical_package_id(cpu); | |
1175 | if (package_num + 1 > num_sockets) { | |
1176 | num_sockets = package_num + 1; | |
1177 | ||
1178 | if (num_sockets > 4) { | |
1179 | cpuidle_state_table = ivt_cstates_8s; | |
1180 | return; | |
0138d8f0 LB |
1181 | } |
1182 | } | |
d70e28f5 LB |
1183 | } |
1184 | ||
1185 | if (num_sockets > 2) | |
1186 | cpuidle_state_table = ivt_cstates_4s; | |
1187 | ||
1188 | /* else, 1 and 2 socket systems use default ivt_cstates */ | |
1189 | } | |
5dcef694 LB |
1190 | |
1191 | /* | |
1192 | * Translate IRTL (Interrupt Response Time Limit) MSR to usec | |
1193 | */ | |
1194 | ||
1195 | static unsigned int irtl_ns_units[] = { | |
1196 | 1, 32, 1024, 32768, 1048576, 33554432, 0, 0 }; | |
1197 | ||
1198 | static unsigned long long irtl_2_usec(unsigned long long irtl) | |
1199 | { | |
1200 | unsigned long long ns; | |
1201 | ||
3451ab3e JB |
1202 | if (!irtl) |
1203 | return 0; | |
1204 | ||
bef45096 | 1205 | ns = irtl_ns_units[(irtl >> 10) & 0x7]; |
5dcef694 LB |
1206 | |
1207 | return div64_u64((irtl & 0x3FF) * ns, 1000); | |
1208 | } | |
1209 | /* | |
1210 | * bxt_idle_state_table_update(void) | |
1211 | * | |
1212 | * On BXT, we trust the IRTL to show the definitive maximum latency | |
1213 | * We use the same value for target_residency. | |
1214 | */ | |
1215 | static void bxt_idle_state_table_update(void) | |
1216 | { | |
1217 | unsigned long long msr; | |
3451ab3e | 1218 | unsigned int usec; |
5dcef694 LB |
1219 | |
1220 | rdmsrl(MSR_PKGC6_IRTL, msr); | |
3451ab3e JB |
1221 | usec = irtl_2_usec(msr); |
1222 | if (usec) { | |
5dcef694 LB |
1223 | bxt_cstates[2].exit_latency = usec; |
1224 | bxt_cstates[2].target_residency = usec; | |
1225 | } | |
1226 | ||
1227 | rdmsrl(MSR_PKGC7_IRTL, msr); | |
3451ab3e JB |
1228 | usec = irtl_2_usec(msr); |
1229 | if (usec) { | |
5dcef694 LB |
1230 | bxt_cstates[3].exit_latency = usec; |
1231 | bxt_cstates[3].target_residency = usec; | |
1232 | } | |
1233 | ||
1234 | rdmsrl(MSR_PKGC8_IRTL, msr); | |
3451ab3e JB |
1235 | usec = irtl_2_usec(msr); |
1236 | if (usec) { | |
5dcef694 LB |
1237 | bxt_cstates[4].exit_latency = usec; |
1238 | bxt_cstates[4].target_residency = usec; | |
1239 | } | |
1240 | ||
1241 | rdmsrl(MSR_PKGC9_IRTL, msr); | |
3451ab3e JB |
1242 | usec = irtl_2_usec(msr); |
1243 | if (usec) { | |
5dcef694 LB |
1244 | bxt_cstates[5].exit_latency = usec; |
1245 | bxt_cstates[5].target_residency = usec; | |
1246 | } | |
1247 | ||
1248 | rdmsrl(MSR_PKGC10_IRTL, msr); | |
3451ab3e JB |
1249 | usec = irtl_2_usec(msr); |
1250 | if (usec) { | |
5dcef694 LB |
1251 | bxt_cstates[6].exit_latency = usec; |
1252 | bxt_cstates[6].target_residency = usec; | |
1253 | } | |
1254 | ||
1255 | } | |
d70e28f5 LB |
1256 | /* |
1257 | * sklh_idle_state_table_update(void) | |
1258 | * | |
1259 | * On SKL-H (model 0x5e) disable C8 and C9 if: | |
1260 | * C10 is enabled and SGX disabled | |
1261 | */ | |
1262 | static void sklh_idle_state_table_update(void) | |
1263 | { | |
1264 | unsigned long long msr; | |
1265 | unsigned int eax, ebx, ecx, edx; | |
1266 | ||
1267 | ||
1268 | /* if PC10 disabled via cmdline intel_idle.max_cstate=7 or shallower */ | |
1269 | if (max_cstate <= 7) | |
1270 | return; | |
1271 | ||
1272 | /* if PC10 not present in CPUID.MWAIT.EDX */ | |
1273 | if ((mwait_substates & (0xF << 28)) == 0) | |
1274 | return; | |
1275 | ||
6cfb2374 | 1276 | rdmsrl(MSR_PKG_CST_CONFIG_CONTROL, msr); |
d70e28f5 LB |
1277 | |
1278 | /* PC10 is not enabled in PKG C-state limit */ | |
1279 | if ((msr & 0xF) != 8) | |
1280 | return; | |
1281 | ||
1282 | ecx = 0; | |
1283 | cpuid(7, &eax, &ebx, &ecx, &edx); | |
1284 | ||
1285 | /* if SGX is present */ | |
1286 | if (ebx & (1 << 2)) { | |
0138d8f0 | 1287 | |
d70e28f5 LB |
1288 | rdmsrl(MSR_IA32_FEATURE_CONTROL, msr); |
1289 | ||
1290 | /* if SGX is enabled */ | |
1291 | if (msr & (1 << 18)) | |
1292 | return; | |
1293 | } | |
1294 | ||
1295 | skl_cstates[5].disabled = 1; /* C8-SKL */ | |
1296 | skl_cstates[6].disabled = 1; /* C9-SKL */ | |
1297 | } | |
1298 | /* | |
1299 | * intel_idle_state_table_update() | |
1300 | * | |
1301 | * Update the default state_table for this CPU-id | |
1302 | */ | |
1303 | ||
1304 | static void intel_idle_state_table_update(void) | |
1305 | { | |
1306 | switch (boot_cpu_data.x86_model) { | |
1307 | ||
db73c5a8 | 1308 | case INTEL_FAM6_IVYBRIDGE_X: |
d70e28f5 LB |
1309 | ivt_idle_state_table_update(); |
1310 | break; | |
db73c5a8 | 1311 | case INTEL_FAM6_ATOM_GOLDMONT: |
5dcef694 LB |
1312 | bxt_idle_state_table_update(); |
1313 | break; | |
db73c5a8 | 1314 | case INTEL_FAM6_SKYLAKE_DESKTOP: |
d70e28f5 LB |
1315 | sklh_idle_state_table_update(); |
1316 | break; | |
0138d8f0 | 1317 | } |
0138d8f0 LB |
1318 | } |
1319 | ||
46bcfad7 DD |
1320 | /* |
1321 | * intel_idle_cpuidle_driver_init() | |
1322 | * allocate, initialize cpuidle_states | |
1323 | */ | |
5469c827 | 1324 | static void __init intel_idle_cpuidle_driver_init(void) |
46bcfad7 DD |
1325 | { |
1326 | int cstate; | |
1327 | struct cpuidle_driver *drv = &intel_idle_driver; | |
1328 | ||
0138d8f0 LB |
1329 | intel_idle_state_table_update(); |
1330 | ||
46bcfad7 DD |
1331 | drv->state_count = 1; |
1332 | ||
e022e7eb | 1333 | for (cstate = 0; cstate < CPUIDLE_STATE_MAX; ++cstate) { |
24bfa950 | 1334 | int num_substates, mwait_hint, mwait_cstate; |
46bcfad7 | 1335 | |
7dd0e0af LB |
1336 | if ((cpuidle_state_table[cstate].enter == NULL) && |
1337 | (cpuidle_state_table[cstate].enter_freeze == NULL)) | |
e022e7eb LB |
1338 | break; |
1339 | ||
1340 | if (cstate + 1 > max_cstate) { | |
46bcfad7 DD |
1341 | printk(PREFIX "max_cstate %d reached\n", |
1342 | max_cstate); | |
1343 | break; | |
1344 | } | |
1345 | ||
e022e7eb LB |
1346 | mwait_hint = flg2MWAIT(cpuidle_state_table[cstate].flags); |
1347 | mwait_cstate = MWAIT_HINT2CSTATE(mwait_hint); | |
e022e7eb | 1348 | |
24bfa950 | 1349 | /* number of sub-states for this state in CPUID.MWAIT */ |
e022e7eb | 1350 | num_substates = (mwait_substates >> ((mwait_cstate + 1) * 4)) |
46bcfad7 | 1351 | & MWAIT_SUBSTATE_MASK; |
e022e7eb | 1352 | |
24bfa950 LB |
1353 | /* if NO sub-states for this state in CPUID, skip it */ |
1354 | if (num_substates == 0) | |
46bcfad7 | 1355 | continue; |
46bcfad7 | 1356 | |
d70e28f5 LB |
1357 | /* if state marked as disabled, skip it */ |
1358 | if (cpuidle_state_table[cstate].disabled != 0) { | |
1359 | pr_debug(PREFIX "state %s is disabled", | |
1360 | cpuidle_state_table[cstate].name); | |
1361 | continue; | |
1362 | } | |
1363 | ||
1364 | ||
e022e7eb | 1365 | if (((mwait_cstate + 1) > 2) && |
46bcfad7 DD |
1366 | !boot_cpu_has(X86_FEATURE_NONSTOP_TSC)) |
1367 | mark_tsc_unstable("TSC halts in idle" | |
1368 | " states deeper than C2"); | |
1369 | ||
1370 | drv->states[drv->state_count] = /* structure copy */ | |
1371 | cpuidle_state_table[cstate]; | |
1372 | ||
1373 | drv->state_count += 1; | |
1374 | } | |
1375 | ||
8c058d53 LB |
1376 | if (icpu->byt_auto_demotion_disable_flag) { |
1377 | wrmsrl(MSR_CC6_DEMOTION_POLICY_CONFIG, 0); | |
1378 | wrmsrl(MSR_MC6_DEMOTION_POLICY_CONFIG, 0); | |
1379 | } | |
46bcfad7 DD |
1380 | } |
1381 | ||
1382 | ||
26717172 | 1383 | /* |
65b7f839 | 1384 | * intel_idle_cpu_init() |
26717172 | 1385 | * allocate, initialize, register cpuidle_devices |
65b7f839 | 1386 | * @cpu: cpu/core to initialize |
26717172 | 1387 | */ |
fb1013a0 | 1388 | static int intel_idle_cpu_init(unsigned int cpu) |
26717172 | 1389 | { |
26717172 LB |
1390 | struct cpuidle_device *dev; |
1391 | ||
65b7f839 | 1392 | dev = per_cpu_ptr(intel_idle_cpuidle_devices, cpu); |
65b7f839 | 1393 | dev->cpu = cpu; |
26717172 | 1394 | |
65b7f839 TR |
1395 | if (cpuidle_register_device(dev)) { |
1396 | pr_debug(PREFIX "cpuidle_register_device %d failed!\n", cpu); | |
65b7f839 | 1397 | return -EIO; |
26717172 LB |
1398 | } |
1399 | ||
b66b8b9a | 1400 | if (icpu->auto_demotion_disable_flags) |
fb1013a0 | 1401 | auto_demotion_disable(); |
65b7f839 | 1402 | |
dbf87ab8 | 1403 | if (icpu->disable_promotion_to_c1e) |
fb1013a0 SAS |
1404 | c1e_promotion_disable(); |
1405 | ||
1406 | return 0; | |
1407 | } | |
1408 | ||
1409 | static int intel_idle_cpu_online(unsigned int cpu) | |
1410 | { | |
1411 | struct cpuidle_device *dev; | |
1412 | ||
1413 | if (lapic_timer_reliable_states != LAPIC_TIMER_ALWAYS_RELIABLE) | |
1414 | __setup_broadcast_timer(true); | |
1415 | ||
1416 | /* | |
1417 | * Some systems can hotplug a cpu at runtime after | |
1418 | * the kernel has booted, we have to initialize the | |
1419 | * driver in this case | |
1420 | */ | |
1421 | dev = per_cpu_ptr(intel_idle_cpuidle_devices, cpu); | |
1422 | if (!dev->registered) | |
1423 | return intel_idle_cpu_init(cpu); | |
dbf87ab8 | 1424 | |
26717172 LB |
1425 | return 0; |
1426 | } | |
26717172 LB |
1427 | |
1428 | static int __init intel_idle_init(void) | |
1429 | { | |
fb1013a0 | 1430 | int retval; |
26717172 | 1431 | |
d1896049 TR |
1432 | /* Do not load intel_idle at all for now if idle= is passed */ |
1433 | if (boot_option_idle_override != IDLE_NO_OVERRIDE) | |
1434 | return -ENODEV; | |
1435 | ||
26717172 LB |
1436 | retval = intel_idle_probe(); |
1437 | if (retval) | |
1438 | return retval; | |
1439 | ||
e9df69cc RC |
1440 | intel_idle_cpuidle_devices = alloc_percpu(struct cpuidle_device); |
1441 | if (intel_idle_cpuidle_devices == NULL) | |
1442 | return -ENOMEM; | |
1443 | ||
46bcfad7 | 1444 | intel_idle_cpuidle_driver_init(); |
26717172 LB |
1445 | retval = cpuidle_register_driver(&intel_idle_driver); |
1446 | if (retval) { | |
3735d524 | 1447 | struct cpuidle_driver *drv = cpuidle_get_driver(); |
26717172 | 1448 | printk(KERN_DEBUG PREFIX "intel_idle yielding to %s", |
3735d524 | 1449 | drv ? drv->name : "none"); |
fb1013a0 | 1450 | goto init_driver_fail; |
26717172 LB |
1451 | } |
1452 | ||
2259a819 RC |
1453 | if (boot_cpu_has(X86_FEATURE_ARAT)) /* Always Reliable APIC Timer */ |
1454 | lapic_timer_reliable_states = LAPIC_TIMER_ALWAYS_RELIABLE; | |
2259a819 | 1455 | |
fb1013a0 SAS |
1456 | retval = cpuhp_setup_state(CPUHP_AP_ONLINE_DYN, "idle/intel:online", |
1457 | intel_idle_cpu_online, NULL); | |
1458 | if (retval < 0) | |
1459 | goto hp_setup_fail; | |
26717172 | 1460 | |
2259a819 RC |
1461 | pr_debug(PREFIX "lapic_timer_reliable_states 0x%x\n", |
1462 | lapic_timer_reliable_states); | |
1463 | ||
26717172 | 1464 | return 0; |
fb1013a0 SAS |
1465 | |
1466 | hp_setup_fail: | |
1467 | intel_idle_cpuidle_devices_uninit(); | |
1468 | cpuidle_unregister_driver(&intel_idle_driver); | |
1469 | init_driver_fail: | |
1470 | free_percpu(intel_idle_cpuidle_devices); | |
1471 | return retval; | |
1472 | ||
26717172 | 1473 | } |
02c4fae9 | 1474 | device_initcall(intel_idle_init); |
26717172 | 1475 | |
02c4fae9 PG |
1476 | /* |
1477 | * We are not really modular, but we used to support that. Meaning we also | |
1478 | * support "intel_idle.max_cstate=..." at boot and also a read-only export of | |
1479 | * it at /sys/module/intel_idle/parameters/max_cstate -- so using module_param | |
1480 | * is the easiest way (currently) to continue doing that. | |
1481 | */ | |
26717172 | 1482 | module_param(max_cstate, int, 0444); |