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Commit | Line | Data |
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2b4756aa MH |
1 | /* |
2 | * AD7887 SPI ADC driver | |
3 | * | |
596d0609 | 4 | * Copyright 2010-2011 Analog Devices Inc. |
2b4756aa | 5 | * |
596d0609 | 6 | * Licensed under the GPL-2. |
2b4756aa MH |
7 | */ |
8 | ||
2b4756aa MH |
9 | #include <linux/device.h> |
10 | #include <linux/kernel.h> | |
11 | #include <linux/slab.h> | |
12 | #include <linux/sysfs.h> | |
2b4756aa MH |
13 | #include <linux/spi/spi.h> |
14 | #include <linux/regulator/consumer.h> | |
15 | #include <linux/err.h> | |
99c97852 | 16 | #include <linux/module.h> |
65dd3d3d | 17 | #include <linux/interrupt.h> |
09a1737e | 18 | #include <linux/bitops.h> |
2b4756aa | 19 | |
06458e27 JC |
20 | #include <linux/iio/iio.h> |
21 | #include <linux/iio/sysfs.h> | |
22 | #include <linux/iio/buffer.h> | |
cdf38709 | 23 | |
65dd3d3d LPC |
24 | #include <linux/iio/trigger_consumer.h> |
25 | #include <linux/iio/triggered_buffer.h> | |
2b4756aa | 26 | |
4eb3ccf1 | 27 | #include <linux/platform_data/ad7887.h> |
2b4756aa | 28 | |
09a1737e PM |
29 | #define AD7887_REF_DIS BIT(5) /* on-chip reference disable */ |
30 | #define AD7887_DUAL BIT(4) /* dual-channel mode */ | |
31 | #define AD7887_CH_AIN1 BIT(3) /* convert on channel 1, DUAL=1 */ | |
32 | #define AD7887_CH_AIN0 0 /* convert on channel 0, DUAL=0,1 */ | |
33 | #define AD7887_PM_MODE1 0 /* CS based shutdown */ | |
34 | #define AD7887_PM_MODE2 1 /* full on */ | |
35 | #define AD7887_PM_MODE3 2 /* auto shutdown after conversion */ | |
36 | #define AD7887_PM_MODE4 3 /* standby mode */ | |
65dd3d3d LPC |
37 | |
38 | enum ad7887_channels { | |
39 | AD7887_CH0, | |
40 | AD7887_CH0_CH1, | |
41 | AD7887_CH1, | |
42 | }; | |
43 | ||
65dd3d3d LPC |
44 | /** |
45 | * struct ad7887_chip_info - chip specifc information | |
46 | * @int_vref_mv: the internal reference voltage | |
47 | * @channel: channel specification | |
48 | */ | |
49 | struct ad7887_chip_info { | |
50 | u16 int_vref_mv; | |
51 | struct iio_chan_spec channel[3]; | |
52 | }; | |
53 | ||
54 | struct ad7887_state { | |
55 | struct spi_device *spi; | |
56 | const struct ad7887_chip_info *chip_info; | |
57 | struct regulator *reg; | |
58 | struct spi_transfer xfer[4]; | |
59 | struct spi_message msg[3]; | |
60 | struct spi_message *ring_msg; | |
fce7c3ea | 61 | unsigned char tx_cmd_buf[4]; |
65dd3d3d LPC |
62 | |
63 | /* | |
64 | * DMA (thus cache coherency maintenance) requires the | |
65 | * transfer buffers to live in their own cache lines. | |
66 | * Buffer needs to be large enough to hold two 16 bit samples and a | |
67 | * 64 bit aligned 64 bit timestamp. | |
68 | */ | |
69 | unsigned char data[ALIGN(4, sizeof(s64)) + sizeof(s64)] | |
70 | ____cacheline_aligned; | |
71 | }; | |
72 | ||
73 | enum ad7887_supported_device_ids { | |
74 | ID_AD7887 | |
75 | }; | |
76 | ||
77 | static int ad7887_ring_preenable(struct iio_dev *indio_dev) | |
78 | { | |
79 | struct ad7887_state *st = iio_priv(indio_dev); | |
65dd3d3d LPC |
80 | |
81 | /* We know this is a single long so can 'cheat' */ | |
82 | switch (*indio_dev->active_scan_mask) { | |
83 | case (1 << 0): | |
84 | st->ring_msg = &st->msg[AD7887_CH0]; | |
85 | break; | |
86 | case (1 << 1): | |
87 | st->ring_msg = &st->msg[AD7887_CH1]; | |
88 | /* Dummy read: push CH1 setting down to hardware */ | |
89 | spi_sync(st->spi, st->ring_msg); | |
90 | break; | |
91 | case ((1 << 1) | (1 << 0)): | |
92 | st->ring_msg = &st->msg[AD7887_CH0_CH1]; | |
93 | break; | |
94 | } | |
95 | ||
96 | return 0; | |
97 | } | |
98 | ||
99 | static int ad7887_ring_postdisable(struct iio_dev *indio_dev) | |
100 | { | |
101 | struct ad7887_state *st = iio_priv(indio_dev); | |
102 | ||
103 | /* dummy read: restore default CH0 settin */ | |
104 | return spi_sync(st->spi, &st->msg[AD7887_CH0]); | |
105 | } | |
106 | ||
107 | /** | |
108 | * ad7887_trigger_handler() bh of trigger launched polling to ring buffer | |
109 | * | |
110 | * Currently there is no option in this driver to disable the saving of | |
111 | * timestamps within the ring. | |
112 | **/ | |
113 | static irqreturn_t ad7887_trigger_handler(int irq, void *p) | |
114 | { | |
115 | struct iio_poll_func *pf = p; | |
116 | struct iio_dev *indio_dev = pf->indio_dev; | |
117 | struct ad7887_state *st = iio_priv(indio_dev); | |
65dd3d3d LPC |
118 | int b_sent; |
119 | ||
120 | b_sent = spi_sync(st->spi, st->ring_msg); | |
121 | if (b_sent) | |
122 | goto done; | |
123 | ||
5afd602b | 124 | iio_push_to_buffers_with_timestamp(indio_dev, st->data, |
bc2b7dab | 125 | iio_get_time_ns(indio_dev)); |
65dd3d3d LPC |
126 | done: |
127 | iio_trigger_notify_done(indio_dev->trig); | |
128 | ||
129 | return IRQ_HANDLED; | |
130 | } | |
131 | ||
132 | static const struct iio_buffer_setup_ops ad7887_ring_setup_ops = { | |
133 | .preenable = &ad7887_ring_preenable, | |
134 | .postenable = &iio_triggered_buffer_postenable, | |
135 | .predisable = &iio_triggered_buffer_predisable, | |
136 | .postdisable = &ad7887_ring_postdisable, | |
137 | }; | |
138 | ||
2b4756aa MH |
139 | static int ad7887_scan_direct(struct ad7887_state *st, unsigned ch) |
140 | { | |
141 | int ret = spi_sync(st->spi, &st->msg[ch]); | |
142 | if (ret) | |
143 | return ret; | |
144 | ||
145 | return (st->data[(ch * 2)] << 8) | st->data[(ch * 2) + 1]; | |
146 | } | |
147 | ||
84f79ecb | 148 | static int ad7887_read_raw(struct iio_dev *indio_dev, |
596d0609 MH |
149 | struct iio_chan_spec const *chan, |
150 | int *val, | |
151 | int *val2, | |
152 | long m) | |
2b4756aa | 153 | { |
2b4756aa | 154 | int ret; |
84f79ecb | 155 | struct ad7887_state *st = iio_priv(indio_dev); |
2b4756aa | 156 | |
596d0609 | 157 | switch (m) { |
b11f98ff | 158 | case IIO_CHAN_INFO_RAW: |
6fea8a42 AS |
159 | ret = iio_device_claim_direct_mode(indio_dev); |
160 | if (ret) | |
161 | return ret; | |
162 | ret = ad7887_scan_direct(st, chan->address); | |
163 | iio_device_release_direct_mode(indio_dev); | |
596d0609 MH |
164 | |
165 | if (ret < 0) | |
166 | return ret; | |
98efb70a | 167 | *val = ret >> chan->scan_type.shift; |
09a1737e | 168 | *val &= GENMASK(chan->scan_type.realbits - 1, 0); |
596d0609 | 169 | return IIO_VAL_INT; |
c8a9f805 | 170 | case IIO_CHAN_INFO_SCALE: |
bf5d2613 LPC |
171 | if (st->reg) { |
172 | *val = regulator_get_voltage(st->reg); | |
173 | if (*val < 0) | |
174 | return *val; | |
175 | *val /= 1000; | |
176 | } else { | |
177 | *val = st->chip_info->int_vref_mv; | |
178 | } | |
179 | ||
98efb70a | 180 | *val2 = chan->scan_type.realbits; |
bf5d2613 LPC |
181 | |
182 | return IIO_VAL_FRACTIONAL_LOG2; | |
596d0609 MH |
183 | } |
184 | return -EINVAL; | |
2b4756aa MH |
185 | } |
186 | ||
2b4756aa MH |
187 | |
188 | static const struct ad7887_chip_info ad7887_chip_info_tbl[] = { | |
189 | /* | |
190 | * More devices added in future | |
191 | */ | |
192 | [ID_AD7887] = { | |
31bf47d5 JC |
193 | .channel[0] = { |
194 | .type = IIO_VOLTAGE, | |
195 | .indexed = 1, | |
196 | .channel = 1, | |
16d186b1 JC |
197 | .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), |
198 | .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE), | |
31bf47d5 JC |
199 | .address = 1, |
200 | .scan_index = 1, | |
e39d9905 JC |
201 | .scan_type = { |
202 | .sign = 'u', | |
203 | .realbits = 12, | |
204 | .storagebits = 16, | |
205 | .shift = 0, | |
206 | .endianness = IIO_BE, | |
207 | }, | |
31bf47d5 JC |
208 | }, |
209 | .channel[1] = { | |
210 | .type = IIO_VOLTAGE, | |
211 | .indexed = 1, | |
212 | .channel = 0, | |
16d186b1 JC |
213 | .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), |
214 | .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE), | |
31bf47d5 JC |
215 | .address = 0, |
216 | .scan_index = 0, | |
e39d9905 JC |
217 | .scan_type = { |
218 | .sign = 'u', | |
219 | .realbits = 12, | |
220 | .storagebits = 16, | |
221 | .shift = 0, | |
222 | .endianness = IIO_BE, | |
223 | }, | |
31bf47d5 | 224 | }, |
596d0609 | 225 | .channel[2] = IIO_CHAN_SOFT_TIMESTAMP(2), |
2b4756aa MH |
226 | .int_vref_mv = 2500, |
227 | }, | |
228 | }; | |
229 | ||
6fe8135f JC |
230 | static const struct iio_info ad7887_info = { |
231 | .read_raw = &ad7887_read_raw, | |
232 | .driver_module = THIS_MODULE, | |
233 | }; | |
234 | ||
fc52692c | 235 | static int ad7887_probe(struct spi_device *spi) |
2b4756aa MH |
236 | { |
237 | struct ad7887_platform_data *pdata = spi->dev.platform_data; | |
238 | struct ad7887_state *st; | |
82429e0d | 239 | struct iio_dev *indio_dev; |
fce7c3ea | 240 | uint8_t mode; |
bf5d2613 | 241 | int ret; |
2b4756aa | 242 | |
82429e0d | 243 | indio_dev = devm_iio_device_alloc(&spi->dev, sizeof(*st)); |
f39e086a MH |
244 | if (indio_dev == NULL) |
245 | return -ENOMEM; | |
246 | ||
247 | st = iio_priv(indio_dev); | |
2b4756aa | 248 | |
bf5d2613 | 249 | if (!pdata || !pdata->use_onchip_ref) { |
82429e0d SK |
250 | st->reg = devm_regulator_get(&spi->dev, "vref"); |
251 | if (IS_ERR(st->reg)) | |
252 | return PTR_ERR(st->reg); | |
bf5d2613 | 253 | |
2b4756aa MH |
254 | ret = regulator_enable(st->reg); |
255 | if (ret) | |
82429e0d | 256 | return ret; |
2b4756aa MH |
257 | } |
258 | ||
259 | st->chip_info = | |
260 | &ad7887_chip_info_tbl[spi_get_device_id(spi)->driver_data]; | |
261 | ||
f39e086a | 262 | spi_set_drvdata(spi, indio_dev); |
2b4756aa MH |
263 | st->spi = spi; |
264 | ||
2b4756aa | 265 | /* Estabilish that the iio_dev is a child of the spi device */ |
f39e086a | 266 | indio_dev->dev.parent = &spi->dev; |
b541eaff | 267 | indio_dev->dev.of_node = spi->dev.of_node; |
f39e086a | 268 | indio_dev->name = spi_get_device_id(spi)->name; |
6fe8135f | 269 | indio_dev->info = &ad7887_info; |
f39e086a | 270 | indio_dev->modes = INDIO_DIRECT_MODE; |
2b4756aa MH |
271 | |
272 | /* Setup default message */ | |
273 | ||
fce7c3ea LPC |
274 | mode = AD7887_PM_MODE4; |
275 | if (!pdata || !pdata->use_onchip_ref) | |
276 | mode |= AD7887_REF_DIS; | |
277 | if (pdata && pdata->en_dual) | |
278 | mode |= AD7887_DUAL; | |
279 | ||
280 | st->tx_cmd_buf[0] = AD7887_CH_AIN0 | mode; | |
2b4756aa MH |
281 | |
282 | st->xfer[0].rx_buf = &st->data[0]; | |
283 | st->xfer[0].tx_buf = &st->tx_cmd_buf[0]; | |
284 | st->xfer[0].len = 2; | |
285 | ||
286 | spi_message_init(&st->msg[AD7887_CH0]); | |
287 | spi_message_add_tail(&st->xfer[0], &st->msg[AD7887_CH0]); | |
288 | ||
289 | if (pdata && pdata->en_dual) { | |
fce7c3ea | 290 | st->tx_cmd_buf[2] = AD7887_CH_AIN1 | mode; |
2b4756aa MH |
291 | |
292 | st->xfer[1].rx_buf = &st->data[0]; | |
293 | st->xfer[1].tx_buf = &st->tx_cmd_buf[2]; | |
294 | st->xfer[1].len = 2; | |
295 | ||
296 | st->xfer[2].rx_buf = &st->data[2]; | |
fce7c3ea | 297 | st->xfer[2].tx_buf = &st->tx_cmd_buf[0]; |
2b4756aa MH |
298 | st->xfer[2].len = 2; |
299 | ||
300 | spi_message_init(&st->msg[AD7887_CH0_CH1]); | |
301 | spi_message_add_tail(&st->xfer[1], &st->msg[AD7887_CH0_CH1]); | |
302 | spi_message_add_tail(&st->xfer[2], &st->msg[AD7887_CH0_CH1]); | |
303 | ||
fce7c3ea LPC |
304 | st->xfer[3].rx_buf = &st->data[2]; |
305 | st->xfer[3].tx_buf = &st->tx_cmd_buf[2]; | |
2b4756aa MH |
306 | st->xfer[3].len = 2; |
307 | ||
308 | spi_message_init(&st->msg[AD7887_CH1]); | |
309 | spi_message_add_tail(&st->xfer[3], &st->msg[AD7887_CH1]); | |
310 | ||
f39e086a MH |
311 | indio_dev->channels = st->chip_info->channel; |
312 | indio_dev->num_channels = 3; | |
2b4756aa | 313 | } else { |
f39e086a MH |
314 | indio_dev->channels = &st->chip_info->channel[1]; |
315 | indio_dev->num_channels = 2; | |
596d0609 | 316 | } |
2b4756aa | 317 | |
65dd3d3d LPC |
318 | ret = iio_triggered_buffer_setup(indio_dev, &iio_pollfunc_store_time, |
319 | &ad7887_trigger_handler, &ad7887_ring_setup_ops); | |
2b4756aa | 320 | if (ret) |
f39e086a | 321 | goto error_disable_reg; |
2b4756aa | 322 | |
26d25ae3 JC |
323 | ret = iio_device_register(indio_dev); |
324 | if (ret) | |
325 | goto error_unregister_ring; | |
326 | ||
327 | return 0; | |
328 | error_unregister_ring: | |
65dd3d3d | 329 | iio_triggered_buffer_cleanup(indio_dev); |
2b4756aa | 330 | error_disable_reg: |
bf5d2613 | 331 | if (st->reg) |
2b4756aa | 332 | regulator_disable(st->reg); |
f39e086a | 333 | |
2b4756aa MH |
334 | return ret; |
335 | } | |
336 | ||
fc52692c | 337 | static int ad7887_remove(struct spi_device *spi) |
2b4756aa | 338 | { |
f39e086a MH |
339 | struct iio_dev *indio_dev = spi_get_drvdata(spi); |
340 | struct ad7887_state *st = iio_priv(indio_dev); | |
341 | ||
d2fffd6c | 342 | iio_device_unregister(indio_dev); |
65dd3d3d | 343 | iio_triggered_buffer_cleanup(indio_dev); |
82429e0d | 344 | if (st->reg) |
2b4756aa | 345 | regulator_disable(st->reg); |
f39e086a | 346 | |
2b4756aa MH |
347 | return 0; |
348 | } | |
349 | ||
350 | static const struct spi_device_id ad7887_id[] = { | |
351 | {"ad7887", ID_AD7887}, | |
352 | {} | |
353 | }; | |
55e4390c | 354 | MODULE_DEVICE_TABLE(spi, ad7887_id); |
2b4756aa MH |
355 | |
356 | static struct spi_driver ad7887_driver = { | |
357 | .driver = { | |
358 | .name = "ad7887", | |
2b4756aa MH |
359 | }, |
360 | .probe = ad7887_probe, | |
fc52692c | 361 | .remove = ad7887_remove, |
2b4756aa MH |
362 | .id_table = ad7887_id, |
363 | }; | |
ae6ae6fe | 364 | module_spi_driver(ad7887_driver); |
2b4756aa MH |
365 | |
366 | MODULE_AUTHOR("Michael Hennerich <hennerich@blackfin.uclinux.org>"); | |
367 | MODULE_DESCRIPTION("Analog Devices AD7887 ADC"); | |
368 | MODULE_LICENSE("GPL v2"); |