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iio: adc: ti-ads1015: add adequate wait time to get correct conversion
[mirror_ubuntu-artful-kernel.git] / drivers / iio / adc / ti-ads1015.c
CommitLineData
ecc24e72
DB		 1/*
2 * ADS1015 - Texas Instruments Analog-to-Digital Converter
3 *
4 * Copyright (c) 2016, Intel Corporation.
5 *
6 * This file is subject to the terms and conditions of version 2 of
7 * the GNU General Public License. See the file COPYING in the main
8 * directory of this archive for more details.
9 *
10 * IIO driver for ADS1015 ADC 7-bit I2C slave address:
11 * * 0x48 - ADDR connected to Ground
12 * * 0x49 - ADDR connected to Vdd
13 * * 0x4A - ADDR connected to SDA
14 * * 0x4B - ADDR connected to SCL
15 */
16
17#include <linux/module.h>
c172d22d 18#include <linux/of_device.h>
ecc24e72
DB		 19#include <linux/init.h>
20#include <linux/i2c.h>
21#include <linux/regmap.h>
22#include <linux/pm_runtime.h>
23#include <linux/mutex.h>
24#include <linux/delay.h>
25
9010624c 26#include <linux/platform_data/ads1015.h>
ecc24e72
DB		 27
28#include <linux/iio/iio.h>
29#include <linux/iio/types.h>
30#include <linux/iio/sysfs.h>
31#include <linux/iio/buffer.h>
32#include <linux/iio/triggered_buffer.h>
33#include <linux/iio/trigger_consumer.h>
34
35#define ADS1015_DRV_NAME "ads1015"
36
37#define ADS1015_CONV_REG 0x00
38#define ADS1015_CFG_REG 0x01
39
40#define ADS1015_CFG_DR_SHIFT 5
41#define ADS1015_CFG_MOD_SHIFT 8
42#define ADS1015_CFG_PGA_SHIFT 9
43#define ADS1015_CFG_MUX_SHIFT 12
44
45#define ADS1015_CFG_DR_MASK GENMASK(7, 5)
46#define ADS1015_CFG_MOD_MASK BIT(8)
47#define ADS1015_CFG_PGA_MASK GENMASK(11, 9)
48#define ADS1015_CFG_MUX_MASK GENMASK(14, 12)
49
50/* device operating modes */
51#define ADS1015_CONTINUOUS 0
52#define ADS1015_SINGLESHOT 1
53
54#define ADS1015_SLEEP_DELAY_MS 2000
55#define ADS1015_DEFAULT_PGA 2
56#define ADS1015_DEFAULT_DATA_RATE 4
57#define ADS1015_DEFAULT_CHAN 0
58
c172d22d 59enum chip_ids {
ba35f111
MR		 60 ADS1015,
61 ADS1115,
62};
63
ecc24e72
DB		 64enum ads1015_channels {
65 ADS1015_AIN0_AIN1 = 0,
66 ADS1015_AIN0_AIN3,
67 ADS1015_AIN1_AIN3,
68 ADS1015_AIN2_AIN3,
69 ADS1015_AIN0,
70 ADS1015_AIN1,
71 ADS1015_AIN2,
72 ADS1015_AIN3,
73 ADS1015_TIMESTAMP,
74};
75
76static const unsigned int ads1015_data_rate[] = {
77 128, 250, 490, 920, 1600, 2400, 3300, 3300
78};
79
ba35f111
MR		 80static const unsigned int ads1115_data_rate[] = {
81 8, 16, 32, 64, 128, 250, 475, 860
82};
83
e99c6901
AM		 84/*
85 * Translation from PGA bits to full-scale positive and negative input voltage
86 * range in mV
87 */
88static int ads1015_fullscale_range[] = {
89 6144, 4096, 2048, 1024, 512, 256, 256, 256
ecc24e72
DB		 90};
91
92#define ADS1015_V_CHAN(_chan, _addr) { \
93 .type = IIO_VOLTAGE, \
94 .indexed = 1, \
95 .address = _addr, \
96 .channel = _chan, \
97 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \
98 BIT(IIO_CHAN_INFO_SCALE) | \
99 BIT(IIO_CHAN_INFO_SAMP_FREQ), \
100 .scan_index = _addr, \
101 .scan_type = { \
102 .sign = 's', \
103 .realbits = 12, \
104 .storagebits = 16, \
105 .shift = 4, \
106 .endianness = IIO_CPU, \
107 }, \
8ac8aa61 108 .datasheet_name = "AIN"#_chan, \
ecc24e72
DB		 109}
110
111#define ADS1015_V_DIFF_CHAN(_chan, _chan2, _addr) { \
112 .type = IIO_VOLTAGE, \
113 .differential = 1, \
114 .indexed = 1, \
115 .address = _addr, \
116 .channel = _chan, \
117 .channel2 = _chan2, \
118 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \
119 BIT(IIO_CHAN_INFO_SCALE) | \
120 BIT(IIO_CHAN_INFO_SAMP_FREQ), \
121 .scan_index = _addr, \
122 .scan_type = { \
123 .sign = 's', \
124 .realbits = 12, \
125 .storagebits = 16, \
126 .shift = 4, \
127 .endianness = IIO_CPU, \
128 }, \
8ac8aa61 129 .datasheet_name = "AIN"#_chan"-AIN"#_chan2, \
ecc24e72
DB		 130}
131
ba35f111
MR		 132#define ADS1115_V_CHAN(_chan, _addr) { \
133 .type = IIO_VOLTAGE, \
134 .indexed = 1, \
135 .address = _addr, \
136 .channel = _chan, \
137 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \
138 BIT(IIO_CHAN_INFO_SCALE) | \
139 BIT(IIO_CHAN_INFO_SAMP_FREQ), \
140 .scan_index = _addr, \
141 .scan_type = { \
142 .sign = 's', \
143 .realbits = 16, \
144 .storagebits = 16, \
145 .endianness = IIO_CPU, \
146 }, \
8ac8aa61 147 .datasheet_name = "AIN"#_chan, \
ba35f111
MR		 148}
149
150#define ADS1115_V_DIFF_CHAN(_chan, _chan2, _addr) { \
151 .type = IIO_VOLTAGE, \
152 .differential = 1, \
153 .indexed = 1, \
154 .address = _addr, \
155 .channel = _chan, \
156 .channel2 = _chan2, \
157 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \
158 BIT(IIO_CHAN_INFO_SCALE) | \
159 BIT(IIO_CHAN_INFO_SAMP_FREQ), \
160 .scan_index = _addr, \
161 .scan_type = { \
162 .sign = 's', \
163 .realbits = 16, \
164 .storagebits = 16, \
165 .endianness = IIO_CPU, \
166 }, \
8ac8aa61 167 .datasheet_name = "AIN"#_chan"-AIN"#_chan2, \
ba35f111
MR		 168}
169
ecc24e72
DB		 170struct ads1015_data {
171 struct regmap *regmap;
172 /*
173 * Protects ADC ops, e.g: concurrent sysfs/buffered
174 * data reads, configuration updates
175 */
176 struct mutex lock;
177 struct ads1015_channel_data channel_data[ADS1015_CHANNELS];
ba35f111
MR		 178
179 unsigned int *data_rate;
5e2b5032
AM		 180 /*
181 * Set to true when the ADC is switched to the continuous-conversion
182 * mode and exits from a power-down state. This flag is used to avoid
183 * getting the stale result from the conversion register.
184 */
185 bool conv_invalid;
ecc24e72
DB		 186};
187
188static bool ads1015_is_writeable_reg(struct device *dev, unsigned int reg)
189{
190 return (reg == ADS1015_CFG_REG);
191}
192
193static const struct regmap_config ads1015_regmap_config = {
194 .reg_bits = 8,
195 .val_bits = 16,
196 .max_register = ADS1015_CFG_REG,
197 .writeable_reg = ads1015_is_writeable_reg,
198};
199
200static const struct iio_chan_spec ads1015_channels[] = {
201 ADS1015_V_DIFF_CHAN(0, 1, ADS1015_AIN0_AIN1),
202 ADS1015_V_DIFF_CHAN(0, 3, ADS1015_AIN0_AIN3),
203 ADS1015_V_DIFF_CHAN(1, 3, ADS1015_AIN1_AIN3),
204 ADS1015_V_DIFF_CHAN(2, 3, ADS1015_AIN2_AIN3),
205 ADS1015_V_CHAN(0, ADS1015_AIN0),
206 ADS1015_V_CHAN(1, ADS1015_AIN1),
207 ADS1015_V_CHAN(2, ADS1015_AIN2),
208 ADS1015_V_CHAN(3, ADS1015_AIN3),
209 IIO_CHAN_SOFT_TIMESTAMP(ADS1015_TIMESTAMP),
210};
211
ba35f111
MR		 212static const struct iio_chan_spec ads1115_channels[] = {
213 ADS1115_V_DIFF_CHAN(0, 1, ADS1015_AIN0_AIN1),
214 ADS1115_V_DIFF_CHAN(0, 3, ADS1015_AIN0_AIN3),
215 ADS1115_V_DIFF_CHAN(1, 3, ADS1015_AIN1_AIN3),
216 ADS1115_V_DIFF_CHAN(2, 3, ADS1015_AIN2_AIN3),
217 ADS1115_V_CHAN(0, ADS1015_AIN0),
218 ADS1115_V_CHAN(1, ADS1015_AIN1),
219 ADS1115_V_CHAN(2, ADS1015_AIN2),
220 ADS1115_V_CHAN(3, ADS1015_AIN3),
221 IIO_CHAN_SOFT_TIMESTAMP(ADS1015_TIMESTAMP),
222};
223
ecc24e72
DB		 224static int ads1015_set_power_state(struct ads1015_data *data, bool on)
225{
226 int ret;
227 struct device *dev = regmap_get_device(data->regmap);
228
229 if (on) {
230 ret = pm_runtime_get_sync(dev);
231 if (ret < 0)
232 pm_runtime_put_noidle(dev);
233 } else {
234 pm_runtime_mark_last_busy(dev);
235 ret = pm_runtime_put_autosuspend(dev);
236 }
237
8c1ba7ea 238 return ret < 0 ? ret : 0;
ecc24e72
DB		 239}
240
241static
242int ads1015_get_adc_result(struct ads1015_data *data, int chan, int *val)
243{
244 int ret, pga, dr, conv_time;
c9461ba1 245 unsigned int old, mask, cfg;
ecc24e72
DB		 246
247 if (chan < 0 || chan >= ADS1015_CHANNELS)
248 return -EINVAL;
249
c9461ba1
AM		 250 ret = regmap_read(data->regmap, ADS1015_CFG_REG, &old);
251 if (ret)
252 return ret;
253
ecc24e72
DB		 254 pga = data->channel_data[chan].pga;
255 dr = data->channel_data[chan].data_rate;
c9461ba1
AM		 256 mask = ADS1015_CFG_MUX_MASK | ADS1015_CFG_PGA_MASK |
257 ADS1015_CFG_DR_MASK;
258 cfg = chan << ADS1015_CFG_MUX_SHIFT | pga << ADS1015_CFG_PGA_SHIFT |
259 dr << ADS1015_CFG_DR_SHIFT;
ecc24e72 260
c9461ba1
AM		 261 cfg = (old & ~mask) | (cfg & mask);
262
263 ret = regmap_write(data->regmap, ADS1015_CFG_REG, cfg);
264 if (ret)
ecc24e72
DB		 265 return ret;
266
c9461ba1
AM		 267 if (old != cfg || data->conv_invalid) {
268 int dr_old = (old & ADS1015_CFG_DR_MASK) >>
269 ADS1015_CFG_DR_SHIFT;
270
271 conv_time = DIV_ROUND_UP(USEC_PER_SEC, data->data_rate[dr_old]);
272 conv_time += DIV_ROUND_UP(USEC_PER_SEC, data->data_rate[dr]);
ecc24e72 273 usleep_range(conv_time, conv_time + 1);
5e2b5032 274 data->conv_invalid = false;
ecc24e72
DB		 275 }
276
277 return regmap_read(data->regmap, ADS1015_CONV_REG, val);
278}
279
280static irqreturn_t ads1015_trigger_handler(int irq, void *p)
281{
282 struct iio_poll_func *pf = p;
283 struct iio_dev *indio_dev = pf->indio_dev;
284 struct ads1015_data *data = iio_priv(indio_dev);
285 s16 buf[8]; /* 1x s16 ADC val + 3x s16 padding + 4x s16 timestamp */
286 int chan, ret, res;
287
288 memset(buf, 0, sizeof(buf));
289
290 mutex_lock(&data->lock);
291 chan = find_first_bit(indio_dev->active_scan_mask,
292 indio_dev->masklength);
293 ret = ads1015_get_adc_result(data, chan, &res);
294 if (ret < 0) {
295 mutex_unlock(&data->lock);
296 goto err;
297 }
298
299 buf[0] = res;
300 mutex_unlock(&data->lock);
301
bc2b7dab
GB		 302 iio_push_to_buffers_with_timestamp(indio_dev, buf,
303 iio_get_time_ns(indio_dev));
ecc24e72
DB		 304
305err:
306 iio_trigger_notify_done(indio_dev->trig);
307
308 return IRQ_HANDLED;
309}
310
e99c6901
AM		 311static int ads1015_set_scale(struct ads1015_data *data,
312 struct iio_chan_spec const *chan,
ecc24e72
DB		 313 int scale, int uscale)
314{
315 int i, ret, rindex = -1;
e99c6901
AM		 316 int fullscale = div_s64((scale * 1000000LL + uscale) <<
317 (chan->scan_type.realbits - 1), 1000000);
ecc24e72 318
e99c6901
AM		 319 for (i = 0; i < ARRAY_SIZE(ads1015_fullscale_range); i++) {
320 if (ads1015_fullscale_range[i] == fullscale) {
ecc24e72
DB		 321 rindex = i;
322 break;
323 }
e99c6901 324 }
ecc24e72
DB		 325 if (rindex < 0)
326 return -EINVAL;
327
328 ret = regmap_update_bits(data->regmap, ADS1015_CFG_REG,
329 ADS1015_CFG_PGA_MASK,
330 rindex << ADS1015_CFG_PGA_SHIFT);
331 if (ret < 0)
332 return ret;
333
e99c6901 334 data->channel_data[chan->address].pga = rindex;
ecc24e72
DB		 335
336 return 0;
337}
338
339static int ads1015_set_data_rate(struct ads1015_data *data, int chan, int rate)
340{
a8da3223 341 int i;
ecc24e72 342
a8da3223 343 for (i = 0; i < ARRAY_SIZE(ads1015_data_rate); i++) {
ba35f111 344 if (data->data_rate[i] == rate) {
a8da3223
AM		 345 data->channel_data[chan].data_rate = i;
346 return 0;
ecc24e72 347 }
a8da3223 348 }
ecc24e72 349
a8da3223 350 return -EINVAL;
ecc24e72
DB		 351}
352
353static int ads1015_read_raw(struct iio_dev *indio_dev,
354 struct iio_chan_spec const *chan, int *val,
355 int *val2, long mask)
356{
357 int ret, idx;
358 struct ads1015_data *data = iio_priv(indio_dev);
359
360 mutex_lock(&indio_dev->mlock);
361 mutex_lock(&data->lock);
362 switch (mask) {
ba35f111
MR		 363 case IIO_CHAN_INFO_RAW: {
364 int shift = chan->scan_type.shift;
365
ecc24e72
DB		 366 if (iio_buffer_enabled(indio_dev)) {
367 ret = -EBUSY;
368 break;
369 }
370
371 ret = ads1015_set_power_state(data, true);
372 if (ret < 0)
373 break;
374
375 ret = ads1015_get_adc_result(data, chan->address, val);
376 if (ret < 0) {
377 ads1015_set_power_state(data, false);
378 break;
379 }
380
ba35f111 381 *val = sign_extend32(*val >> shift, 15 - shift);
ecc24e72
DB		 382
383 ret = ads1015_set_power_state(data, false);
384 if (ret < 0)
385 break;
386
387 ret = IIO_VAL_INT;
388 break;
ba35f111 389 }
ecc24e72
DB		 390 case IIO_CHAN_INFO_SCALE:
391 idx = data->channel_data[chan->address].pga;
e99c6901
AM		 392 *val = ads1015_fullscale_range[idx];
393 *val2 = chan->scan_type.realbits - 1;
394 ret = IIO_VAL_FRACTIONAL_LOG2;
ecc24e72
DB		 395 break;
396 case IIO_CHAN_INFO_SAMP_FREQ:
397 idx = data->channel_data[chan->address].data_rate;
ba35f111 398 *val = data->data_rate[idx];
ecc24e72
DB		 399 ret = IIO_VAL_INT;
400 break;
401 default:
402 ret = -EINVAL;
403 break;
404 }
405 mutex_unlock(&data->lock);
406 mutex_unlock(&indio_dev->mlock);
407
408 return ret;
409}
410
411static int ads1015_write_raw(struct iio_dev *indio_dev,
412 struct iio_chan_spec const *chan, int val,
413 int val2, long mask)
414{
415 struct ads1015_data *data = iio_priv(indio_dev);
416 int ret;
417
418 mutex_lock(&data->lock);
419 switch (mask) {
420 case IIO_CHAN_INFO_SCALE:
e99c6901 421 ret = ads1015_set_scale(data, chan, val, val2);
ecc24e72
DB		 422 break;
423 case IIO_CHAN_INFO_SAMP_FREQ:
424 ret = ads1015_set_data_rate(data, chan->address, val);
425 break;
426 default:
427 ret = -EINVAL;
428 break;
429 }
430 mutex_unlock(&data->lock);
431
432 return ret;
433}
434
435static int ads1015_buffer_preenable(struct iio_dev *indio_dev)
436{
437 return ads1015_set_power_state(iio_priv(indio_dev), true);
438}
439
440static int ads1015_buffer_postdisable(struct iio_dev *indio_dev)
441{
442 return ads1015_set_power_state(iio_priv(indio_dev), false);
443}
444
445static const struct iio_buffer_setup_ops ads1015_buffer_setup_ops = {
446 .preenable = ads1015_buffer_preenable,
447 .postenable = iio_triggered_buffer_postenable,
448 .predisable = iio_triggered_buffer_predisable,
449 .postdisable = ads1015_buffer_postdisable,
450 .validate_scan_mask = &iio_validate_scan_mask_onehot,
451};
452
e99c6901
AM		 453static IIO_CONST_ATTR_NAMED(ads1015_scale_available, scale_available,
454 "3 2 1 0.5 0.25 0.125");
455static IIO_CONST_ATTR_NAMED(ads1115_scale_available, scale_available,
456 "0.1875 0.125 0.0625 0.03125 0.015625 0.007813");
ba35f111
MR		 457
458static IIO_CONST_ATTR_NAMED(ads1015_sampling_frequency_available,
459 sampling_frequency_available, "128 250 490 920 1600 2400 3300");
460static IIO_CONST_ATTR_NAMED(ads1115_sampling_frequency_available,
461 sampling_frequency_available, "8 16 32 64 128 250 475 860");
ecc24e72
DB		 462
463static struct attribute *ads1015_attributes[] = {
e99c6901 464 &iio_const_attr_ads1015_scale_available.dev_attr.attr,
ba35f111 465 &iio_const_attr_ads1015_sampling_frequency_available.dev_attr.attr,
ecc24e72
DB		 466 NULL,
467};
468
469static const struct attribute_group ads1015_attribute_group = {
470 .attrs = ads1015_attributes,
471};
472
ba35f111 473static struct attribute *ads1115_attributes[] = {
e99c6901 474 &iio_const_attr_ads1115_scale_available.dev_attr.attr,
ba35f111
MR		 475 &iio_const_attr_ads1115_sampling_frequency_available.dev_attr.attr,
476 NULL,
477};
478
479static const struct attribute_group ads1115_attribute_group = {
480 .attrs = ads1115_attributes,
481};
482
99a22f06 483static const struct iio_info ads1015_info = {
ba35f111
MR		 484 .driver_module = THIS_MODULE,
485 .read_raw = ads1015_read_raw,
486 .write_raw = ads1015_write_raw,
487 .attrs = &ads1015_attribute_group,
488};
489
99a22f06 490static const struct iio_info ads1115_info = {
ecc24e72
DB		 491 .driver_module = THIS_MODULE,
492 .read_raw = ads1015_read_raw,
493 .write_raw = ads1015_write_raw,
ba35f111 494 .attrs = &ads1115_attribute_group,
ecc24e72
DB		 495};
496
497#ifdef CONFIG_OF
498static int ads1015_get_channels_config_of(struct i2c_client *client)
499{
522caebb
GDM		 500 struct iio_dev *indio_dev = i2c_get_clientdata(client);
501 struct ads1015_data *data = iio_priv(indio_dev);
ecc24e72
DB		 502 struct device_node *node;
503
504 if (!client->dev.of_node ||
505 !of_get_next_child(client->dev.of_node, NULL))
506 return -EINVAL;
507
508 for_each_child_of_node(client->dev.of_node, node) {
509 u32 pval;
510 unsigned int channel;
511 unsigned int pga = ADS1015_DEFAULT_PGA;
512 unsigned int data_rate = ADS1015_DEFAULT_DATA_RATE;
513
514 if (of_property_read_u32(node, "reg", &pval)) {
515 dev_err(&client->dev, "invalid reg on %s\n",
516 node->full_name);
517 continue;
518 }
519
520 channel = pval;
521 if (channel >= ADS1015_CHANNELS) {
522 dev_err(&client->dev,
523 "invalid channel index %d on %s\n",
524 channel, node->full_name);
525 continue;
526 }
527
528 if (!of_property_read_u32(node, "ti,gain", &pval)) {
529 pga = pval;
530 if (pga > 6) {
531 dev_err(&client->dev, "invalid gain on %s\n",
532 node->full_name);
943bbe74 533 of_node_put(node);
ecc24e72
DB		 534 return -EINVAL;
535 }
536 }
537
538 if (!of_property_read_u32(node, "ti,datarate", &pval)) {
539 data_rate = pval;
540 if (data_rate > 7) {
541 dev_err(&client->dev,
542 "invalid data_rate on %s\n",
543 node->full_name);
943bbe74 544 of_node_put(node);
ecc24e72
DB		 545 return -EINVAL;
546 }
547 }
548
549 data->channel_data[channel].pga = pga;
550 data->channel_data[channel].data_rate = data_rate;
551 }
552
553 return 0;
554}
555#endif
556
557static void ads1015_get_channels_config(struct i2c_client *client)
558{
559 unsigned int k;
560
561 struct iio_dev *indio_dev = i2c_get_clientdata(client);
562 struct ads1015_data *data = iio_priv(indio_dev);
563 struct ads1015_platform_data *pdata = dev_get_platdata(&client->dev);
564
565 /* prefer platform data */
566 if (pdata) {
567 memcpy(data->channel_data, pdata->channel_data,
568 sizeof(data->channel_data));
569 return;
570 }
571
572#ifdef CONFIG_OF
573 if (!ads1015_get_channels_config_of(client))
574 return;
575#endif
576 /* fallback on default configuration */
577 for (k = 0; k < ADS1015_CHANNELS; ++k) {
578 data->channel_data[k].pga = ADS1015_DEFAULT_PGA;
579 data->channel_data[k].data_rate = ADS1015_DEFAULT_DATA_RATE;
580 }
581}
582
583static int ads1015_probe(struct i2c_client *client,
584 const struct i2c_device_id *id)
585{
586 struct iio_dev *indio_dev;
587 struct ads1015_data *data;
588 int ret;
c172d22d 589 enum chip_ids chip;
ecc24e72
DB		 590
591 indio_dev = devm_iio_device_alloc(&client->dev, sizeof(*data));
592 if (!indio_dev)
593 return -ENOMEM;
594
595 data = iio_priv(indio_dev);
596 i2c_set_clientdata(client, indio_dev);
597
598 mutex_init(&data->lock);
599
600 indio_dev->dev.parent = &client->dev;
f5241dbd 601 indio_dev->dev.of_node = client->dev.of_node;
ecc24e72 602 indio_dev->name = ADS1015_DRV_NAME;
ecc24e72
DB		 603 indio_dev->modes = INDIO_DIRECT_MODE;
604
c172d22d
JMC		 605 if (client->dev.of_node)
606 chip = (enum chip_ids)of_device_get_match_data(&client->dev);
607 else
608 chip = id->driver_data;
609 switch (chip) {
ba35f111
MR		 610 case ADS1015:
611 indio_dev->channels = ads1015_channels;
612 indio_dev->num_channels = ARRAY_SIZE(ads1015_channels);
613 indio_dev->info = &ads1015_info;
614 data->data_rate = (unsigned int *) &ads1015_data_rate;
615 break;
616 case ADS1115:
617 indio_dev->channels = ads1115_channels;
618 indio_dev->num_channels = ARRAY_SIZE(ads1115_channels);
619 indio_dev->info = &ads1115_info;
620 data->data_rate = (unsigned int *) &ads1115_data_rate;
621 break;
622 }
623
ecc24e72
DB		 624 /* we need to keep this ABI the same as used by hwmon ADS1015 driver */
625 ads1015_get_channels_config(client);
626
627 data->regmap = devm_regmap_init_i2c(client, &ads1015_regmap_config);
628 if (IS_ERR(data->regmap)) {
629 dev_err(&client->dev, "Failed to allocate register map\n");
630 return PTR_ERR(data->regmap);
631 }
632
633 ret = iio_triggered_buffer_setup(indio_dev, NULL,
634 ads1015_trigger_handler,
635 &ads1015_buffer_setup_ops);
636 if (ret < 0) {
637 dev_err(&client->dev, "iio triggered buffer setup failed\n");
638 return ret;
639 }
1df989b7
AM		 640
641 ret = regmap_update_bits(data->regmap, ADS1015_CFG_REG,
642 ADS1015_CFG_MOD_MASK,
643 ADS1015_CONTINUOUS << ADS1015_CFG_MOD_SHIFT);
644 if (ret)
645 return ret;
646
5e2b5032
AM		 647 data->conv_invalid = true;
648
ecc24e72
DB		 649 ret = pm_runtime_set_active(&client->dev);
650 if (ret)
651 goto err_buffer_cleanup;
652 pm_runtime_set_autosuspend_delay(&client->dev, ADS1015_SLEEP_DELAY_MS);
653 pm_runtime_use_autosuspend(&client->dev);
654 pm_runtime_enable(&client->dev);
655
656 ret = iio_device_register(indio_dev);
657 if (ret < 0) {
658 dev_err(&client->dev, "Failed to register IIO device\n");
659 goto err_buffer_cleanup;
660 }
661
662 return 0;
663
664err_buffer_cleanup:
665 iio_triggered_buffer_cleanup(indio_dev);
666
667 return ret;
668}
669
670static int ads1015_remove(struct i2c_client *client)
671{
672 struct iio_dev *indio_dev = i2c_get_clientdata(client);
673 struct ads1015_data *data = iio_priv(indio_dev);
674
675 iio_device_unregister(indio_dev);
676
677 pm_runtime_disable(&client->dev);
678 pm_runtime_set_suspended(&client->dev);
679 pm_runtime_put_noidle(&client->dev);
680
681 iio_triggered_buffer_cleanup(indio_dev);
682
683 /* power down single shot mode */
684 return regmap_update_bits(data->regmap, ADS1015_CFG_REG,
685 ADS1015_CFG_MOD_MASK,
686 ADS1015_SINGLESHOT << ADS1015_CFG_MOD_SHIFT);
687}
688
689#ifdef CONFIG_PM
690static int ads1015_runtime_suspend(struct device *dev)
691{
692 struct iio_dev *indio_dev = i2c_get_clientdata(to_i2c_client(dev));
693 struct ads1015_data *data = iio_priv(indio_dev);
694
695 return regmap_update_bits(data->regmap, ADS1015_CFG_REG,
696 ADS1015_CFG_MOD_MASK,
697 ADS1015_SINGLESHOT << ADS1015_CFG_MOD_SHIFT);
698}
699
700static int ads1015_runtime_resume(struct device *dev)
701{
702 struct iio_dev *indio_dev = i2c_get_clientdata(to_i2c_client(dev));
703 struct ads1015_data *data = iio_priv(indio_dev);
5e2b5032 704 int ret;
ecc24e72 705
5e2b5032 706 ret = regmap_update_bits(data->regmap, ADS1015_CFG_REG,
ecc24e72
DB		 707 ADS1015_CFG_MOD_MASK,
708 ADS1015_CONTINUOUS << ADS1015_CFG_MOD_SHIFT);
5e2b5032
AM		 709 if (!ret)
710 data->conv_invalid = true;
711
712 return ret;
ecc24e72
DB		 713}
714#endif
715
716static const struct dev_pm_ops ads1015_pm_ops = {
717 SET_RUNTIME_PM_OPS(ads1015_runtime_suspend,
718 ads1015_runtime_resume, NULL)
719};
720
721static const struct i2c_device_id ads1015_id[] = {
ba35f111
MR		 722 {"ads1015", ADS1015},
723 {"ads1115", ADS1115},
ecc24e72
DB		 724 {}
725};
726MODULE_DEVICE_TABLE(i2c, ads1015_id);
727
c172d22d
JMC		 728static const struct of_device_id ads1015_of_match[] = {
729 {
730 .compatible = "ti,ads1015",
731 .data = (void *)ADS1015
732 },
733 {
734 .compatible = "ti,ads1115",
735 .data = (void *)ADS1115
736 },
737 {}
738};
739MODULE_DEVICE_TABLE(of, ads1015_of_match);
740
ecc24e72
DB		 741static struct i2c_driver ads1015_driver = {
742 .driver = {
743 .name = ADS1015_DRV_NAME,
c172d22d 744 .of_match_table = ads1015_of_match,
ecc24e72
DB		 745 .pm = &ads1015_pm_ops,
746 },
747 .probe = ads1015_probe,
748 .remove = ads1015_remove,
749 .id_table = ads1015_id,
750};
751
752module_i2c_driver(ads1015_driver);
753
754MODULE_AUTHOR("Daniel Baluta <daniel.baluta@intel.com>");
755MODULE_DESCRIPTION("Texas Instruments ADS1015 ADC driver");
756MODULE_LICENSE("GPL v2");
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