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e126ba97 | 1 | /* |
6cf0a15f | 2 | * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved. |
e126ba97 EC |
3 | * |
4 | * This software is available to you under a choice of one of two | |
5 | * licenses. You may choose to be licensed under the terms of the GNU | |
6 | * General Public License (GPL) Version 2, available from the file | |
7 | * COPYING in the main directory of this source tree, or the | |
8 | * OpenIB.org BSD license below: | |
9 | * | |
10 | * Redistribution and use in source and binary forms, with or | |
11 | * without modification, are permitted provided that the following | |
12 | * conditions are met: | |
13 | * | |
14 | * - Redistributions of source code must retain the above | |
15 | * copyright notice, this list of conditions and the following | |
16 | * disclaimer. | |
17 | * | |
18 | * - Redistributions in binary form must reproduce the above | |
19 | * copyright notice, this list of conditions and the following | |
20 | * disclaimer in the documentation and/or other materials | |
21 | * provided with the distribution. | |
22 | * | |
23 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, | |
24 | * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | |
25 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND | |
26 | * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS | |
27 | * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN | |
28 | * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN | |
29 | * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE | |
30 | * SOFTWARE. | |
31 | */ | |
32 | ||
33 | #ifndef MLX5_IB_H | |
34 | #define MLX5_IB_H | |
35 | ||
36 | #include <linux/kernel.h> | |
37 | #include <linux/sched.h> | |
38 | #include <rdma/ib_verbs.h> | |
39 | #include <rdma/ib_smi.h> | |
40 | #include <linux/mlx5/driver.h> | |
41 | #include <linux/mlx5/cq.h> | |
42 | #include <linux/mlx5/qp.h> | |
43 | #include <linux/mlx5/srq.h> | |
44 | #include <linux/types.h> | |
146d2f1a | 45 | #include <linux/mlx5/transobj.h> |
e126ba97 EC |
46 | |
47 | #define mlx5_ib_dbg(dev, format, arg...) \ | |
48 | pr_debug("%s:%s:%d:(pid %d): " format, (dev)->ib_dev.name, __func__, \ | |
49 | __LINE__, current->pid, ##arg) | |
50 | ||
51 | #define mlx5_ib_err(dev, format, arg...) \ | |
52 | pr_err("%s:%s:%d:(pid %d): " format, (dev)->ib_dev.name, __func__, \ | |
53 | __LINE__, current->pid, ##arg) | |
54 | ||
55 | #define mlx5_ib_warn(dev, format, arg...) \ | |
56 | pr_warn("%s:%s:%d:(pid %d): " format, (dev)->ib_dev.name, __func__, \ | |
57 | __LINE__, current->pid, ##arg) | |
58 | ||
b368d7cb MB |
59 | #define field_avail(type, fld, sz) (offsetof(type, fld) + \ |
60 | sizeof(((type *)0)->fld) <= (sz)) | |
cfb5e088 HA |
61 | #define MLX5_IB_DEFAULT_UIDX 0xffffff |
62 | #define MLX5_USER_ASSIGNED_UIDX_MASK __mlx5_mask(qpc, user_index) | |
b368d7cb | 63 | |
e126ba97 EC |
64 | enum { |
65 | MLX5_IB_MMAP_CMD_SHIFT = 8, | |
66 | MLX5_IB_MMAP_CMD_MASK = 0xff, | |
67 | }; | |
68 | ||
69 | enum mlx5_ib_mmap_cmd { | |
70 | MLX5_IB_MMAP_REGULAR_PAGE = 0, | |
d69e3bcf MB |
71 | MLX5_IB_MMAP_GET_CONTIGUOUS_PAGES = 1, |
72 | /* 5 is chosen in order to be compatible with old versions of libmlx5 */ | |
73 | MLX5_IB_MMAP_CORE_CLOCK = 5, | |
e126ba97 EC |
74 | }; |
75 | ||
76 | enum { | |
77 | MLX5_RES_SCAT_DATA32_CQE = 0x1, | |
78 | MLX5_RES_SCAT_DATA64_CQE = 0x2, | |
79 | MLX5_REQ_SCAT_DATA32_CQE = 0x11, | |
80 | MLX5_REQ_SCAT_DATA64_CQE = 0x22, | |
81 | }; | |
82 | ||
83 | enum mlx5_ib_latency_class { | |
84 | MLX5_IB_LATENCY_CLASS_LOW, | |
85 | MLX5_IB_LATENCY_CLASS_MEDIUM, | |
86 | MLX5_IB_LATENCY_CLASS_HIGH, | |
87 | MLX5_IB_LATENCY_CLASS_FAST_PATH | |
88 | }; | |
89 | ||
90 | enum mlx5_ib_mad_ifc_flags { | |
91 | MLX5_MAD_IFC_IGNORE_MKEY = 1, | |
92 | MLX5_MAD_IFC_IGNORE_BKEY = 2, | |
93 | MLX5_MAD_IFC_NET_VIEW = 4, | |
94 | }; | |
95 | ||
051f2630 LR |
96 | enum { |
97 | MLX5_CROSS_CHANNEL_UUAR = 0, | |
98 | }; | |
99 | ||
cfb5e088 HA |
100 | enum { |
101 | MLX5_CQE_VERSION_V0, | |
102 | MLX5_CQE_VERSION_V1, | |
103 | }; | |
104 | ||
e126ba97 EC |
105 | struct mlx5_ib_ucontext { |
106 | struct ib_ucontext ibucontext; | |
107 | struct list_head db_page_list; | |
108 | ||
109 | /* protect doorbell record alloc/free | |
110 | */ | |
111 | struct mutex db_page_mutex; | |
112 | struct mlx5_uuar_info uuari; | |
cfb5e088 | 113 | u8 cqe_version; |
146d2f1a | 114 | /* Transport Domain number */ |
115 | u32 tdn; | |
e126ba97 EC |
116 | }; |
117 | ||
118 | static inline struct mlx5_ib_ucontext *to_mucontext(struct ib_ucontext *ibucontext) | |
119 | { | |
120 | return container_of(ibucontext, struct mlx5_ib_ucontext, ibucontext); | |
121 | } | |
122 | ||
123 | struct mlx5_ib_pd { | |
124 | struct ib_pd ibpd; | |
125 | u32 pdn; | |
e126ba97 EC |
126 | }; |
127 | ||
128 | /* Use macros here so that don't have to duplicate | |
129 | * enum ib_send_flags and enum ib_qp_type for low-level driver | |
130 | */ | |
131 | ||
132 | #define MLX5_IB_SEND_UMR_UNREG IB_SEND_RESERVED_START | |
968e78dd HE |
133 | #define MLX5_IB_SEND_UMR_FAIL_IF_FREE (IB_SEND_RESERVED_START << 1) |
134 | #define MLX5_IB_SEND_UMR_UPDATE_MTT (IB_SEND_RESERVED_START << 2) | |
e126ba97 EC |
135 | #define MLX5_IB_QPT_REG_UMR IB_QPT_RESERVED1 |
136 | #define MLX5_IB_WR_UMR IB_WR_RESERVED1 | |
137 | ||
138 | struct wr_list { | |
139 | u16 opcode; | |
140 | u16 next; | |
141 | }; | |
142 | ||
143 | struct mlx5_ib_wq { | |
144 | u64 *wrid; | |
145 | u32 *wr_data; | |
146 | struct wr_list *w_list; | |
147 | unsigned *wqe_head; | |
148 | u16 unsig_count; | |
149 | ||
150 | /* serialize post to the work queue | |
151 | */ | |
152 | spinlock_t lock; | |
153 | int wqe_cnt; | |
154 | int max_post; | |
155 | int max_gs; | |
156 | int offset; | |
157 | int wqe_shift; | |
158 | unsigned head; | |
159 | unsigned tail; | |
160 | u16 cur_post; | |
161 | u16 last_poll; | |
162 | void *qend; | |
163 | }; | |
164 | ||
165 | enum { | |
166 | MLX5_QP_USER, | |
167 | MLX5_QP_KERNEL, | |
168 | MLX5_QP_EMPTY | |
169 | }; | |
170 | ||
6aec21f6 HE |
171 | /* |
172 | * Connect-IB can trigger up to four concurrent pagefaults | |
173 | * per-QP. | |
174 | */ | |
175 | enum mlx5_ib_pagefault_context { | |
176 | MLX5_IB_PAGEFAULT_RESPONDER_READ, | |
177 | MLX5_IB_PAGEFAULT_REQUESTOR_READ, | |
178 | MLX5_IB_PAGEFAULT_RESPONDER_WRITE, | |
179 | MLX5_IB_PAGEFAULT_REQUESTOR_WRITE, | |
180 | MLX5_IB_PAGEFAULT_CONTEXTS | |
181 | }; | |
182 | ||
183 | static inline enum mlx5_ib_pagefault_context | |
184 | mlx5_ib_get_pagefault_context(struct mlx5_pagefault *pagefault) | |
185 | { | |
186 | return pagefault->flags & (MLX5_PFAULT_REQUESTOR | MLX5_PFAULT_WRITE); | |
187 | } | |
188 | ||
189 | struct mlx5_ib_pfault { | |
190 | struct work_struct work; | |
191 | struct mlx5_pagefault mpfault; | |
192 | }; | |
193 | ||
19098df2 | 194 | struct mlx5_ib_ubuffer { |
195 | struct ib_umem *umem; | |
196 | int buf_size; | |
197 | u64 buf_addr; | |
198 | }; | |
199 | ||
200 | struct mlx5_ib_qp_base { | |
201 | struct mlx5_ib_qp *container_mibqp; | |
202 | struct mlx5_core_qp mqp; | |
203 | struct mlx5_ib_ubuffer ubuffer; | |
204 | }; | |
205 | ||
206 | struct mlx5_ib_qp_trans { | |
207 | struct mlx5_ib_qp_base base; | |
208 | u16 xrcdn; | |
209 | u8 alt_port; | |
210 | u8 atomic_rd_en; | |
211 | u8 resp_depth; | |
212 | }; | |
213 | ||
0fb2ed66 | 214 | struct mlx5_ib_rq { |
215 | struct mlx5_ib_qp_base base; | |
216 | struct mlx5_ib_wq *rq; | |
217 | struct mlx5_ib_ubuffer ubuffer; | |
218 | struct mlx5_db *doorbell; | |
219 | u32 tirn; | |
220 | u8 state; | |
221 | }; | |
222 | ||
223 | struct mlx5_ib_sq { | |
224 | struct mlx5_ib_qp_base base; | |
225 | struct mlx5_ib_wq *sq; | |
226 | struct mlx5_ib_ubuffer ubuffer; | |
227 | struct mlx5_db *doorbell; | |
228 | u32 tisn; | |
229 | u8 state; | |
230 | }; | |
231 | ||
232 | struct mlx5_ib_raw_packet_qp { | |
233 | struct mlx5_ib_sq sq; | |
234 | struct mlx5_ib_rq rq; | |
235 | }; | |
236 | ||
e126ba97 EC |
237 | struct mlx5_ib_qp { |
238 | struct ib_qp ibqp; | |
0fb2ed66 | 239 | union { |
240 | struct mlx5_ib_qp_trans trans_qp; | |
241 | struct mlx5_ib_raw_packet_qp raw_packet_qp; | |
242 | }; | |
e126ba97 EC |
243 | struct mlx5_buf buf; |
244 | ||
245 | struct mlx5_db db; | |
246 | struct mlx5_ib_wq rq; | |
247 | ||
e126ba97 EC |
248 | u8 sq_signal_bits; |
249 | u8 fm_cache; | |
e126ba97 EC |
250 | struct mlx5_ib_wq sq; |
251 | ||
e126ba97 EC |
252 | /* serialize qp state modifications |
253 | */ | |
254 | struct mutex mutex; | |
e126ba97 EC |
255 | u32 flags; |
256 | u8 port; | |
e126ba97 | 257 | u8 state; |
e126ba97 EC |
258 | int wq_sig; |
259 | int scat_cqe; | |
260 | int max_inline_data; | |
261 | struct mlx5_bf *bf; | |
262 | int has_rq; | |
263 | ||
264 | /* only for user space QPs. For kernel | |
265 | * we have it from the bf object | |
266 | */ | |
267 | int uuarn; | |
268 | ||
269 | int create_type; | |
e1e66cc2 SG |
270 | |
271 | /* Store signature errors */ | |
272 | bool signature_en; | |
6aec21f6 HE |
273 | |
274 | #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING | |
275 | /* | |
276 | * A flag that is true for QP's that are in a state that doesn't | |
277 | * allow page faults, and shouldn't schedule any more faults. | |
278 | */ | |
279 | int disable_page_faults; | |
280 | /* | |
281 | * The disable_page_faults_lock protects a QP's disable_page_faults | |
282 | * field, allowing for a thread to atomically check whether the QP | |
283 | * allows page faults, and if so schedule a page fault. | |
284 | */ | |
285 | spinlock_t disable_page_faults_lock; | |
286 | struct mlx5_ib_pfault pagefaults[MLX5_IB_PAGEFAULT_CONTEXTS]; | |
287 | #endif | |
e126ba97 EC |
288 | }; |
289 | ||
290 | struct mlx5_ib_cq_buf { | |
291 | struct mlx5_buf buf; | |
292 | struct ib_umem *umem; | |
293 | int cqe_size; | |
bde51583 | 294 | int nent; |
e126ba97 EC |
295 | }; |
296 | ||
297 | enum mlx5_ib_qp_flags { | |
298 | MLX5_IB_QP_BLOCK_MULTICAST_LOOPBACK = 1 << 0, | |
299 | MLX5_IB_QP_SIGNATURE_HANDLING = 1 << 1, | |
051f2630 LR |
300 | MLX5_IB_QP_CROSS_CHANNEL = 1 << 2, |
301 | MLX5_IB_QP_MANAGED_SEND = 1 << 3, | |
302 | MLX5_IB_QP_MANAGED_RECV = 1 << 4, | |
e126ba97 EC |
303 | }; |
304 | ||
968e78dd | 305 | struct mlx5_umr_wr { |
e622f2f4 | 306 | struct ib_send_wr wr; |
968e78dd HE |
307 | union { |
308 | u64 virt_addr; | |
309 | u64 offset; | |
310 | } target; | |
311 | struct ib_pd *pd; | |
312 | unsigned int page_shift; | |
313 | unsigned int npages; | |
314 | u32 length; | |
315 | int access_flags; | |
316 | u32 mkey; | |
317 | }; | |
318 | ||
e622f2f4 CH |
319 | static inline struct mlx5_umr_wr *umr_wr(struct ib_send_wr *wr) |
320 | { | |
321 | return container_of(wr, struct mlx5_umr_wr, wr); | |
322 | } | |
323 | ||
e126ba97 EC |
324 | struct mlx5_shared_mr_info { |
325 | int mr_id; | |
326 | struct ib_umem *umem; | |
327 | }; | |
328 | ||
329 | struct mlx5_ib_cq { | |
330 | struct ib_cq ibcq; | |
331 | struct mlx5_core_cq mcq; | |
332 | struct mlx5_ib_cq_buf buf; | |
333 | struct mlx5_db db; | |
334 | ||
335 | /* serialize access to the CQ | |
336 | */ | |
337 | spinlock_t lock; | |
338 | ||
339 | /* protect resize cq | |
340 | */ | |
341 | struct mutex resize_mutex; | |
bde51583 | 342 | struct mlx5_ib_cq_buf *resize_buf; |
e126ba97 EC |
343 | struct ib_umem *resize_umem; |
344 | int cqe_size; | |
051f2630 | 345 | u32 create_flags; |
e126ba97 EC |
346 | }; |
347 | ||
348 | struct mlx5_ib_srq { | |
349 | struct ib_srq ibsrq; | |
350 | struct mlx5_core_srq msrq; | |
351 | struct mlx5_buf buf; | |
352 | struct mlx5_db db; | |
353 | u64 *wrid; | |
354 | /* protect SRQ hanlding | |
355 | */ | |
356 | spinlock_t lock; | |
357 | int head; | |
358 | int tail; | |
359 | u16 wqe_ctr; | |
360 | struct ib_umem *umem; | |
361 | /* serialize arming a SRQ | |
362 | */ | |
363 | struct mutex mutex; | |
364 | int wq_sig; | |
365 | }; | |
366 | ||
367 | struct mlx5_ib_xrcd { | |
368 | struct ib_xrcd ibxrcd; | |
369 | u32 xrcdn; | |
370 | }; | |
371 | ||
cc149f75 HE |
372 | enum mlx5_ib_mtt_access_flags { |
373 | MLX5_IB_MTT_READ = (1 << 0), | |
374 | MLX5_IB_MTT_WRITE = (1 << 1), | |
375 | }; | |
376 | ||
377 | #define MLX5_IB_MTT_PRESENT (MLX5_IB_MTT_READ | MLX5_IB_MTT_WRITE) | |
378 | ||
e126ba97 EC |
379 | struct mlx5_ib_mr { |
380 | struct ib_mr ibmr; | |
8a187ee5 SG |
381 | void *descs; |
382 | dma_addr_t desc_map; | |
383 | int ndescs; | |
384 | int max_descs; | |
385 | int desc_size; | |
e126ba97 EC |
386 | struct mlx5_core_mr mmr; |
387 | struct ib_umem *umem; | |
388 | struct mlx5_shared_mr_info *smr_info; | |
389 | struct list_head list; | |
390 | int order; | |
391 | int umred; | |
e126ba97 | 392 | int npages; |
746b5583 EC |
393 | struct mlx5_ib_dev *dev; |
394 | struct mlx5_create_mkey_mbox_out out; | |
3121e3c4 | 395 | struct mlx5_core_sig_ctx *sig; |
b4cfe447 | 396 | int live; |
8a187ee5 | 397 | void *descs_alloc; |
e126ba97 EC |
398 | }; |
399 | ||
a74d2416 SR |
400 | struct mlx5_ib_umr_context { |
401 | enum ib_wc_status status; | |
402 | struct completion done; | |
403 | }; | |
404 | ||
405 | static inline void mlx5_ib_init_umr_context(struct mlx5_ib_umr_context *context) | |
406 | { | |
407 | context->status = -1; | |
408 | init_completion(&context->done); | |
409 | } | |
410 | ||
e126ba97 EC |
411 | struct umr_common { |
412 | struct ib_pd *pd; | |
413 | struct ib_cq *cq; | |
414 | struct ib_qp *qp; | |
e126ba97 EC |
415 | /* control access to UMR QP |
416 | */ | |
417 | struct semaphore sem; | |
418 | }; | |
419 | ||
420 | enum { | |
421 | MLX5_FMR_INVALID, | |
422 | MLX5_FMR_VALID, | |
423 | MLX5_FMR_BUSY, | |
424 | }; | |
425 | ||
e126ba97 EC |
426 | struct mlx5_cache_ent { |
427 | struct list_head head; | |
428 | /* sync access to the cahce entry | |
429 | */ | |
430 | spinlock_t lock; | |
431 | ||
432 | ||
433 | struct dentry *dir; | |
434 | char name[4]; | |
435 | u32 order; | |
436 | u32 size; | |
437 | u32 cur; | |
438 | u32 miss; | |
439 | u32 limit; | |
440 | ||
441 | struct dentry *fsize; | |
442 | struct dentry *fcur; | |
443 | struct dentry *fmiss; | |
444 | struct dentry *flimit; | |
445 | ||
446 | struct mlx5_ib_dev *dev; | |
447 | struct work_struct work; | |
448 | struct delayed_work dwork; | |
746b5583 | 449 | int pending; |
e126ba97 EC |
450 | }; |
451 | ||
452 | struct mlx5_mr_cache { | |
453 | struct workqueue_struct *wq; | |
454 | struct mlx5_cache_ent ent[MAX_MR_CACHE_ENTRIES]; | |
455 | int stopped; | |
456 | struct dentry *root; | |
457 | unsigned long last_add; | |
458 | }; | |
459 | ||
460 | struct mlx5_ib_resources { | |
461 | struct ib_cq *c0; | |
462 | struct ib_xrcd *x0; | |
463 | struct ib_xrcd *x1; | |
464 | struct ib_pd *p0; | |
465 | struct ib_srq *s0; | |
4aa17b28 | 466 | struct ib_srq *s1; |
e126ba97 EC |
467 | }; |
468 | ||
fc24fc5e AS |
469 | struct mlx5_roce { |
470 | /* Protect mlx5_ib_get_netdev from invoking dev_hold() with a NULL | |
471 | * netdev pointer | |
472 | */ | |
473 | rwlock_t netdev_lock; | |
474 | struct net_device *netdev; | |
475 | struct notifier_block nb; | |
476 | }; | |
477 | ||
e126ba97 EC |
478 | struct mlx5_ib_dev { |
479 | struct ib_device ib_dev; | |
9603b61d | 480 | struct mlx5_core_dev *mdev; |
fc24fc5e | 481 | struct mlx5_roce roce; |
e126ba97 | 482 | MLX5_DECLARE_DOORBELL_LOCK(uar_lock); |
e126ba97 | 483 | int num_ports; |
e126ba97 EC |
484 | /* serialize update of capability mask |
485 | */ | |
486 | struct mutex cap_mask_mutex; | |
487 | bool ib_active; | |
488 | struct umr_common umrc; | |
489 | /* sync used page count stats | |
490 | */ | |
e126ba97 EC |
491 | struct mlx5_ib_resources devr; |
492 | struct mlx5_mr_cache cache; | |
746b5583 EC |
493 | struct timer_list delay_timer; |
494 | int fill_delay; | |
8cdd312c HE |
495 | #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING |
496 | struct ib_odp_caps odp_caps; | |
6aec21f6 HE |
497 | /* |
498 | * Sleepable RCU that prevents destruction of MRs while they are still | |
499 | * being used by a page fault handler. | |
500 | */ | |
501 | struct srcu_struct mr_srcu; | |
8cdd312c | 502 | #endif |
e126ba97 EC |
503 | }; |
504 | ||
505 | static inline struct mlx5_ib_cq *to_mibcq(struct mlx5_core_cq *mcq) | |
506 | { | |
507 | return container_of(mcq, struct mlx5_ib_cq, mcq); | |
508 | } | |
509 | ||
510 | static inline struct mlx5_ib_xrcd *to_mxrcd(struct ib_xrcd *ibxrcd) | |
511 | { | |
512 | return container_of(ibxrcd, struct mlx5_ib_xrcd, ibxrcd); | |
513 | } | |
514 | ||
515 | static inline struct mlx5_ib_dev *to_mdev(struct ib_device *ibdev) | |
516 | { | |
517 | return container_of(ibdev, struct mlx5_ib_dev, ib_dev); | |
518 | } | |
519 | ||
e126ba97 EC |
520 | static inline struct mlx5_ib_cq *to_mcq(struct ib_cq *ibcq) |
521 | { | |
522 | return container_of(ibcq, struct mlx5_ib_cq, ibcq); | |
523 | } | |
524 | ||
525 | static inline struct mlx5_ib_qp *to_mibqp(struct mlx5_core_qp *mqp) | |
526 | { | |
19098df2 | 527 | return container_of(mqp, struct mlx5_ib_qp_base, mqp)->container_mibqp; |
e126ba97 EC |
528 | } |
529 | ||
d5436ba0 SG |
530 | static inline struct mlx5_ib_mr *to_mibmr(struct mlx5_core_mr *mmr) |
531 | { | |
532 | return container_of(mmr, struct mlx5_ib_mr, mmr); | |
533 | } | |
534 | ||
e126ba97 EC |
535 | static inline struct mlx5_ib_pd *to_mpd(struct ib_pd *ibpd) |
536 | { | |
537 | return container_of(ibpd, struct mlx5_ib_pd, ibpd); | |
538 | } | |
539 | ||
540 | static inline struct mlx5_ib_srq *to_msrq(struct ib_srq *ibsrq) | |
541 | { | |
542 | return container_of(ibsrq, struct mlx5_ib_srq, ibsrq); | |
543 | } | |
544 | ||
545 | static inline struct mlx5_ib_qp *to_mqp(struct ib_qp *ibqp) | |
546 | { | |
547 | return container_of(ibqp, struct mlx5_ib_qp, ibqp); | |
548 | } | |
549 | ||
550 | static inline struct mlx5_ib_srq *to_mibsrq(struct mlx5_core_srq *msrq) | |
551 | { | |
552 | return container_of(msrq, struct mlx5_ib_srq, msrq); | |
553 | } | |
554 | ||
555 | static inline struct mlx5_ib_mr *to_mmr(struct ib_mr *ibmr) | |
556 | { | |
557 | return container_of(ibmr, struct mlx5_ib_mr, ibmr); | |
558 | } | |
559 | ||
e126ba97 EC |
560 | struct mlx5_ib_ah { |
561 | struct ib_ah ibah; | |
562 | struct mlx5_av av; | |
563 | }; | |
564 | ||
565 | static inline struct mlx5_ib_ah *to_mah(struct ib_ah *ibah) | |
566 | { | |
567 | return container_of(ibah, struct mlx5_ib_ah, ibah); | |
568 | } | |
569 | ||
e126ba97 EC |
570 | int mlx5_ib_db_map_user(struct mlx5_ib_ucontext *context, unsigned long virt, |
571 | struct mlx5_db *db); | |
572 | void mlx5_ib_db_unmap_user(struct mlx5_ib_ucontext *context, struct mlx5_db *db); | |
573 | void __mlx5_ib_cq_clean(struct mlx5_ib_cq *cq, u32 qpn, struct mlx5_ib_srq *srq); | |
574 | void mlx5_ib_cq_clean(struct mlx5_ib_cq *cq, u32 qpn, struct mlx5_ib_srq *srq); | |
575 | void mlx5_ib_free_srq_wqe(struct mlx5_ib_srq *srq, int wqe_index); | |
576 | int mlx5_MAD_IFC(struct mlx5_ib_dev *dev, int ignore_mkey, int ignore_bkey, | |
a97e2d86 IW |
577 | u8 port, const struct ib_wc *in_wc, const struct ib_grh *in_grh, |
578 | const void *in_mad, void *response_mad); | |
e126ba97 EC |
579 | struct ib_ah *mlx5_ib_create_ah(struct ib_pd *pd, struct ib_ah_attr *ah_attr); |
580 | int mlx5_ib_query_ah(struct ib_ah *ibah, struct ib_ah_attr *ah_attr); | |
581 | int mlx5_ib_destroy_ah(struct ib_ah *ah); | |
582 | struct ib_srq *mlx5_ib_create_srq(struct ib_pd *pd, | |
583 | struct ib_srq_init_attr *init_attr, | |
584 | struct ib_udata *udata); | |
585 | int mlx5_ib_modify_srq(struct ib_srq *ibsrq, struct ib_srq_attr *attr, | |
586 | enum ib_srq_attr_mask attr_mask, struct ib_udata *udata); | |
587 | int mlx5_ib_query_srq(struct ib_srq *ibsrq, struct ib_srq_attr *srq_attr); | |
588 | int mlx5_ib_destroy_srq(struct ib_srq *srq); | |
589 | int mlx5_ib_post_srq_recv(struct ib_srq *ibsrq, struct ib_recv_wr *wr, | |
590 | struct ib_recv_wr **bad_wr); | |
591 | struct ib_qp *mlx5_ib_create_qp(struct ib_pd *pd, | |
592 | struct ib_qp_init_attr *init_attr, | |
593 | struct ib_udata *udata); | |
594 | int mlx5_ib_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr, | |
595 | int attr_mask, struct ib_udata *udata); | |
596 | int mlx5_ib_query_qp(struct ib_qp *ibqp, struct ib_qp_attr *qp_attr, int qp_attr_mask, | |
597 | struct ib_qp_init_attr *qp_init_attr); | |
598 | int mlx5_ib_destroy_qp(struct ib_qp *qp); | |
599 | int mlx5_ib_post_send(struct ib_qp *ibqp, struct ib_send_wr *wr, | |
600 | struct ib_send_wr **bad_wr); | |
601 | int mlx5_ib_post_recv(struct ib_qp *ibqp, struct ib_recv_wr *wr, | |
602 | struct ib_recv_wr **bad_wr); | |
603 | void *mlx5_get_send_wqe(struct mlx5_ib_qp *qp, int n); | |
c1395a2a | 604 | int mlx5_ib_read_user_wqe(struct mlx5_ib_qp *qp, int send, int wqe_index, |
19098df2 | 605 | void *buffer, u32 length, |
606 | struct mlx5_ib_qp_base *base); | |
bcf4c1ea MB |
607 | struct ib_cq *mlx5_ib_create_cq(struct ib_device *ibdev, |
608 | const struct ib_cq_init_attr *attr, | |
609 | struct ib_ucontext *context, | |
e126ba97 EC |
610 | struct ib_udata *udata); |
611 | int mlx5_ib_destroy_cq(struct ib_cq *cq); | |
612 | int mlx5_ib_poll_cq(struct ib_cq *ibcq, int num_entries, struct ib_wc *wc); | |
613 | int mlx5_ib_arm_cq(struct ib_cq *ibcq, enum ib_cq_notify_flags flags); | |
614 | int mlx5_ib_modify_cq(struct ib_cq *cq, u16 cq_count, u16 cq_period); | |
615 | int mlx5_ib_resize_cq(struct ib_cq *ibcq, int entries, struct ib_udata *udata); | |
616 | struct ib_mr *mlx5_ib_get_dma_mr(struct ib_pd *pd, int acc); | |
617 | struct ib_mr *mlx5_ib_reg_user_mr(struct ib_pd *pd, u64 start, u64 length, | |
618 | u64 virt_addr, int access_flags, | |
619 | struct ib_udata *udata); | |
832a6b06 HE |
620 | int mlx5_ib_update_mtt(struct mlx5_ib_mr *mr, u64 start_page_index, |
621 | int npages, int zap); | |
e126ba97 | 622 | int mlx5_ib_dereg_mr(struct ib_mr *ibmr); |
9bee178b SG |
623 | struct ib_mr *mlx5_ib_alloc_mr(struct ib_pd *pd, |
624 | enum ib_mr_type mr_type, | |
625 | u32 max_num_sg); | |
8a187ee5 SG |
626 | int mlx5_ib_map_mr_sg(struct ib_mr *ibmr, |
627 | struct scatterlist *sg, | |
628 | int sg_nents); | |
e126ba97 | 629 | int mlx5_ib_process_mad(struct ib_device *ibdev, int mad_flags, u8 port_num, |
a97e2d86 | 630 | const struct ib_wc *in_wc, const struct ib_grh *in_grh, |
4cd7c947 IW |
631 | const struct ib_mad_hdr *in, size_t in_mad_size, |
632 | struct ib_mad_hdr *out, size_t *out_mad_size, | |
633 | u16 *out_mad_pkey_index); | |
e126ba97 EC |
634 | struct ib_xrcd *mlx5_ib_alloc_xrcd(struct ib_device *ibdev, |
635 | struct ib_ucontext *context, | |
636 | struct ib_udata *udata); | |
637 | int mlx5_ib_dealloc_xrcd(struct ib_xrcd *xrcd); | |
e126ba97 EC |
638 | int mlx5_ib_get_buf_offset(u64 addr, int page_shift, u32 *offset); |
639 | int mlx5_query_ext_port_caps(struct mlx5_ib_dev *dev, u8 port); | |
1b5daf11 MD |
640 | int mlx5_query_mad_ifc_smp_attr_node_info(struct ib_device *ibdev, |
641 | struct ib_smp *out_mad); | |
642 | int mlx5_query_mad_ifc_system_image_guid(struct ib_device *ibdev, | |
643 | __be64 *sys_image_guid); | |
644 | int mlx5_query_mad_ifc_max_pkeys(struct ib_device *ibdev, | |
645 | u16 *max_pkeys); | |
646 | int mlx5_query_mad_ifc_vendor_id(struct ib_device *ibdev, | |
647 | u32 *vendor_id); | |
648 | int mlx5_query_mad_ifc_node_desc(struct mlx5_ib_dev *dev, char *node_desc); | |
649 | int mlx5_query_mad_ifc_node_guid(struct mlx5_ib_dev *dev, __be64 *node_guid); | |
650 | int mlx5_query_mad_ifc_pkey(struct ib_device *ibdev, u8 port, u16 index, | |
651 | u16 *pkey); | |
652 | int mlx5_query_mad_ifc_gids(struct ib_device *ibdev, u8 port, int index, | |
653 | union ib_gid *gid); | |
654 | int mlx5_query_mad_ifc_port(struct ib_device *ibdev, u8 port, | |
655 | struct ib_port_attr *props); | |
e126ba97 EC |
656 | int mlx5_ib_query_port(struct ib_device *ibdev, u8 port, |
657 | struct ib_port_attr *props); | |
658 | int mlx5_ib_init_fmr(struct mlx5_ib_dev *dev); | |
659 | void mlx5_ib_cleanup_fmr(struct mlx5_ib_dev *dev); | |
660 | void mlx5_ib_cont_pages(struct ib_umem *umem, u64 addr, int *count, int *shift, | |
661 | int *ncont, int *order); | |
832a6b06 HE |
662 | void __mlx5_ib_populate_pas(struct mlx5_ib_dev *dev, struct ib_umem *umem, |
663 | int page_shift, size_t offset, size_t num_pages, | |
664 | __be64 *pas, int access_flags); | |
e126ba97 | 665 | void mlx5_ib_populate_pas(struct mlx5_ib_dev *dev, struct ib_umem *umem, |
cc149f75 | 666 | int page_shift, __be64 *pas, int access_flags); |
e126ba97 EC |
667 | void mlx5_ib_copy_pas(u64 *old, u64 *new, int step, int num); |
668 | int mlx5_ib_get_cqe_size(struct mlx5_ib_dev *dev, struct ib_cq *ibcq); | |
669 | int mlx5_mr_cache_init(struct mlx5_ib_dev *dev); | |
670 | int mlx5_mr_cache_cleanup(struct mlx5_ib_dev *dev); | |
671 | int mlx5_mr_ib_cont_pages(struct ib_umem *umem, u64 addr, int *count, int *shift); | |
672 | void mlx5_umr_cq_handler(struct ib_cq *cq, void *cq_context); | |
d5436ba0 SG |
673 | int mlx5_ib_check_mr_status(struct ib_mr *ibmr, u32 check_mask, |
674 | struct ib_mr_status *mr_status); | |
e126ba97 | 675 | |
8cdd312c | 676 | #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING |
6aec21f6 HE |
677 | extern struct workqueue_struct *mlx5_ib_page_fault_wq; |
678 | ||
938fe83c | 679 | void mlx5_ib_internal_fill_odp_caps(struct mlx5_ib_dev *dev); |
6aec21f6 HE |
680 | void mlx5_ib_mr_pfault_handler(struct mlx5_ib_qp *qp, |
681 | struct mlx5_ib_pfault *pfault); | |
682 | void mlx5_ib_odp_create_qp(struct mlx5_ib_qp *qp); | |
683 | int mlx5_ib_odp_init_one(struct mlx5_ib_dev *ibdev); | |
684 | void mlx5_ib_odp_remove_one(struct mlx5_ib_dev *ibdev); | |
685 | int __init mlx5_ib_odp_init(void); | |
686 | void mlx5_ib_odp_cleanup(void); | |
687 | void mlx5_ib_qp_disable_pagefaults(struct mlx5_ib_qp *qp); | |
688 | void mlx5_ib_qp_enable_pagefaults(struct mlx5_ib_qp *qp); | |
b4cfe447 HE |
689 | void mlx5_ib_invalidate_range(struct ib_umem *umem, unsigned long start, |
690 | unsigned long end); | |
6aec21f6 HE |
691 | |
692 | #else /* CONFIG_INFINIBAND_ON_DEMAND_PAGING */ | |
938fe83c | 693 | static inline void mlx5_ib_internal_fill_odp_caps(struct mlx5_ib_dev *dev) |
8cdd312c | 694 | { |
938fe83c | 695 | return; |
8cdd312c | 696 | } |
6aec21f6 HE |
697 | |
698 | static inline void mlx5_ib_odp_create_qp(struct mlx5_ib_qp *qp) {} | |
699 | static inline int mlx5_ib_odp_init_one(struct mlx5_ib_dev *ibdev) { return 0; } | |
700 | static inline void mlx5_ib_odp_remove_one(struct mlx5_ib_dev *ibdev) {} | |
701 | static inline int mlx5_ib_odp_init(void) { return 0; } | |
702 | static inline void mlx5_ib_odp_cleanup(void) {} | |
703 | static inline void mlx5_ib_qp_disable_pagefaults(struct mlx5_ib_qp *qp) {} | |
704 | static inline void mlx5_ib_qp_enable_pagefaults(struct mlx5_ib_qp *qp) {} | |
705 | ||
8cdd312c HE |
706 | #endif /* CONFIG_INFINIBAND_ON_DEMAND_PAGING */ |
707 | ||
2811ba51 AS |
708 | __be16 mlx5_get_roce_udp_sport(struct mlx5_ib_dev *dev, u8 port_num, |
709 | int index); | |
710 | ||
e126ba97 EC |
711 | static inline void init_query_mad(struct ib_smp *mad) |
712 | { | |
713 | mad->base_version = 1; | |
714 | mad->mgmt_class = IB_MGMT_CLASS_SUBN_LID_ROUTED; | |
715 | mad->class_version = 1; | |
716 | mad->method = IB_MGMT_METHOD_GET; | |
717 | } | |
718 | ||
719 | static inline u8 convert_access(int acc) | |
720 | { | |
721 | return (acc & IB_ACCESS_REMOTE_ATOMIC ? MLX5_PERM_ATOMIC : 0) | | |
722 | (acc & IB_ACCESS_REMOTE_WRITE ? MLX5_PERM_REMOTE_WRITE : 0) | | |
723 | (acc & IB_ACCESS_REMOTE_READ ? MLX5_PERM_REMOTE_READ : 0) | | |
724 | (acc & IB_ACCESS_LOCAL_WRITE ? MLX5_PERM_LOCAL_WRITE : 0) | | |
725 | MLX5_PERM_LOCAL_READ; | |
726 | } | |
727 | ||
b636401f SG |
728 | static inline int is_qp1(enum ib_qp_type qp_type) |
729 | { | |
730 | return qp_type == IB_QPT_GSI; | |
731 | } | |
732 | ||
cc149f75 HE |
733 | #define MLX5_MAX_UMR_SHIFT 16 |
734 | #define MLX5_MAX_UMR_PAGES (1 << MLX5_MAX_UMR_SHIFT) | |
735 | ||
051f2630 LR |
736 | static inline u32 check_cq_create_flags(u32 flags) |
737 | { | |
738 | /* | |
739 | * It returns non-zero value for unsupported CQ | |
740 | * create flags, otherwise it returns zero. | |
741 | */ | |
34356f64 LR |
742 | return (flags & ~(IB_CQ_FLAGS_IGNORE_OVERRUN | |
743 | IB_CQ_FLAGS_TIMESTAMP_COMPLETION)); | |
051f2630 | 744 | } |
cfb5e088 HA |
745 | |
746 | static inline int verify_assign_uidx(u8 cqe_version, u32 cmd_uidx, | |
747 | u32 *user_index) | |
748 | { | |
749 | if (cqe_version) { | |
750 | if ((cmd_uidx == MLX5_IB_DEFAULT_UIDX) || | |
751 | (cmd_uidx & ~MLX5_USER_ASSIGNED_UIDX_MASK)) | |
752 | return -EINVAL; | |
753 | *user_index = cmd_uidx; | |
754 | } else { | |
755 | *user_index = MLX5_IB_DEFAULT_UIDX; | |
756 | } | |
757 | ||
758 | return 0; | |
759 | } | |
e126ba97 | 760 | #endif /* MLX5_IB_H */ |