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45ae7cff WD |
1 | /* |
2 | * IOMMU API for ARM architected SMMU implementations. | |
3 | * | |
4 | * This program is free software; you can redistribute it and/or modify | |
5 | * it under the terms of the GNU General Public License version 2 as | |
6 | * published by the Free Software Foundation. | |
7 | * | |
8 | * This program is distributed in the hope that it will be useful, | |
9 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
10 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
11 | * GNU General Public License for more details. | |
12 | * | |
13 | * You should have received a copy of the GNU General Public License | |
14 | * along with this program; if not, write to the Free Software | |
15 | * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. | |
16 | * | |
17 | * Copyright (C) 2013 ARM Limited | |
18 | * | |
19 | * Author: Will Deacon <will.deacon@arm.com> | |
20 | * | |
21 | * This driver currently supports: | |
22 | * - SMMUv1 and v2 implementations | |
23 | * - Stream-matching and stream-indexing | |
24 | * - v7/v8 long-descriptor format | |
25 | * - Non-secure access to the SMMU | |
26 | * - 4k and 64k pages, with contiguous pte hints. | |
06f983dd | 27 | * - Up to 42-bit addressing (dependent on VA_BITS) |
45ae7cff WD |
28 | * - Context fault reporting |
29 | */ | |
30 | ||
31 | #define pr_fmt(fmt) "arm-smmu: " fmt | |
32 | ||
33 | #include <linux/delay.h> | |
34 | #include <linux/dma-mapping.h> | |
35 | #include <linux/err.h> | |
36 | #include <linux/interrupt.h> | |
37 | #include <linux/io.h> | |
38 | #include <linux/iommu.h> | |
39 | #include <linux/mm.h> | |
40 | #include <linux/module.h> | |
41 | #include <linux/of.h> | |
a9a1b0b5 | 42 | #include <linux/pci.h> |
45ae7cff WD |
43 | #include <linux/platform_device.h> |
44 | #include <linux/slab.h> | |
45 | #include <linux/spinlock.h> | |
46 | ||
47 | #include <linux/amba/bus.h> | |
48 | ||
49 | #include <asm/pgalloc.h> | |
50 | ||
51 | /* Maximum number of stream IDs assigned to a single device */ | |
636e97b0 | 52 | #define MAX_MASTER_STREAMIDS MAX_PHANDLE_ARGS |
45ae7cff WD |
53 | |
54 | /* Maximum number of context banks per SMMU */ | |
55 | #define ARM_SMMU_MAX_CBS 128 | |
56 | ||
57 | /* Maximum number of mapping groups per SMMU */ | |
58 | #define ARM_SMMU_MAX_SMRS 128 | |
59 | ||
45ae7cff WD |
60 | /* SMMU global address space */ |
61 | #define ARM_SMMU_GR0(smmu) ((smmu)->base) | |
62 | #define ARM_SMMU_GR1(smmu) ((smmu)->base + (smmu)->pagesize) | |
63 | ||
3a5df8ff AH |
64 | /* |
65 | * SMMU global address space with conditional offset to access secure | |
66 | * aliases of non-secure registers (e.g. nsCR0: 0x400, nsGFSR: 0x448, | |
67 | * nsGFSYNR0: 0x450) | |
68 | */ | |
69 | #define ARM_SMMU_GR0_NS(smmu) \ | |
70 | ((smmu)->base + \ | |
71 | ((smmu->options & ARM_SMMU_OPT_SECURE_CFG_ACCESS) \ | |
72 | ? 0x400 : 0)) | |
73 | ||
45ae7cff | 74 | /* Page table bits */ |
cf2d45b1 | 75 | #define ARM_SMMU_PTE_XN (((pteval_t)3) << 53) |
45ae7cff WD |
76 | #define ARM_SMMU_PTE_CONT (((pteval_t)1) << 52) |
77 | #define ARM_SMMU_PTE_AF (((pteval_t)1) << 10) | |
78 | #define ARM_SMMU_PTE_SH_NS (((pteval_t)0) << 8) | |
79 | #define ARM_SMMU_PTE_SH_OS (((pteval_t)2) << 8) | |
80 | #define ARM_SMMU_PTE_SH_IS (((pteval_t)3) << 8) | |
cf2d45b1 | 81 | #define ARM_SMMU_PTE_PAGE (((pteval_t)3) << 0) |
45ae7cff WD |
82 | |
83 | #if PAGE_SIZE == SZ_4K | |
84 | #define ARM_SMMU_PTE_CONT_ENTRIES 16 | |
85 | #elif PAGE_SIZE == SZ_64K | |
86 | #define ARM_SMMU_PTE_CONT_ENTRIES 32 | |
87 | #else | |
88 | #define ARM_SMMU_PTE_CONT_ENTRIES 1 | |
89 | #endif | |
90 | ||
91 | #define ARM_SMMU_PTE_CONT_SIZE (PAGE_SIZE * ARM_SMMU_PTE_CONT_ENTRIES) | |
92 | #define ARM_SMMU_PTE_CONT_MASK (~(ARM_SMMU_PTE_CONT_SIZE - 1)) | |
45ae7cff WD |
93 | |
94 | /* Stage-1 PTE */ | |
95 | #define ARM_SMMU_PTE_AP_UNPRIV (((pteval_t)1) << 6) | |
96 | #define ARM_SMMU_PTE_AP_RDONLY (((pteval_t)2) << 6) | |
97 | #define ARM_SMMU_PTE_ATTRINDX_SHIFT 2 | |
1463fe44 | 98 | #define ARM_SMMU_PTE_nG (((pteval_t)1) << 11) |
45ae7cff WD |
99 | |
100 | /* Stage-2 PTE */ | |
101 | #define ARM_SMMU_PTE_HAP_FAULT (((pteval_t)0) << 6) | |
102 | #define ARM_SMMU_PTE_HAP_READ (((pteval_t)1) << 6) | |
103 | #define ARM_SMMU_PTE_HAP_WRITE (((pteval_t)2) << 6) | |
104 | #define ARM_SMMU_PTE_MEMATTR_OIWB (((pteval_t)0xf) << 2) | |
105 | #define ARM_SMMU_PTE_MEMATTR_NC (((pteval_t)0x5) << 2) | |
106 | #define ARM_SMMU_PTE_MEMATTR_DEV (((pteval_t)0x1) << 2) | |
107 | ||
108 | /* Configuration registers */ | |
109 | #define ARM_SMMU_GR0_sCR0 0x0 | |
110 | #define sCR0_CLIENTPD (1 << 0) | |
111 | #define sCR0_GFRE (1 << 1) | |
112 | #define sCR0_GFIE (1 << 2) | |
113 | #define sCR0_GCFGFRE (1 << 4) | |
114 | #define sCR0_GCFGFIE (1 << 5) | |
115 | #define sCR0_USFCFG (1 << 10) | |
116 | #define sCR0_VMIDPNE (1 << 11) | |
117 | #define sCR0_PTM (1 << 12) | |
118 | #define sCR0_FB (1 << 13) | |
119 | #define sCR0_BSU_SHIFT 14 | |
120 | #define sCR0_BSU_MASK 0x3 | |
121 | ||
122 | /* Identification registers */ | |
123 | #define ARM_SMMU_GR0_ID0 0x20 | |
124 | #define ARM_SMMU_GR0_ID1 0x24 | |
125 | #define ARM_SMMU_GR0_ID2 0x28 | |
126 | #define ARM_SMMU_GR0_ID3 0x2c | |
127 | #define ARM_SMMU_GR0_ID4 0x30 | |
128 | #define ARM_SMMU_GR0_ID5 0x34 | |
129 | #define ARM_SMMU_GR0_ID6 0x38 | |
130 | #define ARM_SMMU_GR0_ID7 0x3c | |
131 | #define ARM_SMMU_GR0_sGFSR 0x48 | |
132 | #define ARM_SMMU_GR0_sGFSYNR0 0x50 | |
133 | #define ARM_SMMU_GR0_sGFSYNR1 0x54 | |
134 | #define ARM_SMMU_GR0_sGFSYNR2 0x58 | |
135 | #define ARM_SMMU_GR0_PIDR0 0xfe0 | |
136 | #define ARM_SMMU_GR0_PIDR1 0xfe4 | |
137 | #define ARM_SMMU_GR0_PIDR2 0xfe8 | |
138 | ||
139 | #define ID0_S1TS (1 << 30) | |
140 | #define ID0_S2TS (1 << 29) | |
141 | #define ID0_NTS (1 << 28) | |
142 | #define ID0_SMS (1 << 27) | |
143 | #define ID0_PTFS_SHIFT 24 | |
144 | #define ID0_PTFS_MASK 0x2 | |
145 | #define ID0_PTFS_V8_ONLY 0x2 | |
146 | #define ID0_CTTW (1 << 14) | |
147 | #define ID0_NUMIRPT_SHIFT 16 | |
148 | #define ID0_NUMIRPT_MASK 0xff | |
149 | #define ID0_NUMSMRG_SHIFT 0 | |
150 | #define ID0_NUMSMRG_MASK 0xff | |
151 | ||
152 | #define ID1_PAGESIZE (1 << 31) | |
153 | #define ID1_NUMPAGENDXB_SHIFT 28 | |
154 | #define ID1_NUMPAGENDXB_MASK 7 | |
155 | #define ID1_NUMS2CB_SHIFT 16 | |
156 | #define ID1_NUMS2CB_MASK 0xff | |
157 | #define ID1_NUMCB_SHIFT 0 | |
158 | #define ID1_NUMCB_MASK 0xff | |
159 | ||
160 | #define ID2_OAS_SHIFT 4 | |
161 | #define ID2_OAS_MASK 0xf | |
162 | #define ID2_IAS_SHIFT 0 | |
163 | #define ID2_IAS_MASK 0xf | |
164 | #define ID2_UBS_SHIFT 8 | |
165 | #define ID2_UBS_MASK 0xf | |
166 | #define ID2_PTFS_4K (1 << 12) | |
167 | #define ID2_PTFS_16K (1 << 13) | |
168 | #define ID2_PTFS_64K (1 << 14) | |
169 | ||
170 | #define PIDR2_ARCH_SHIFT 4 | |
171 | #define PIDR2_ARCH_MASK 0xf | |
172 | ||
173 | /* Global TLB invalidation */ | |
174 | #define ARM_SMMU_GR0_STLBIALL 0x60 | |
175 | #define ARM_SMMU_GR0_TLBIVMID 0x64 | |
176 | #define ARM_SMMU_GR0_TLBIALLNSNH 0x68 | |
177 | #define ARM_SMMU_GR0_TLBIALLH 0x6c | |
178 | #define ARM_SMMU_GR0_sTLBGSYNC 0x70 | |
179 | #define ARM_SMMU_GR0_sTLBGSTATUS 0x74 | |
180 | #define sTLBGSTATUS_GSACTIVE (1 << 0) | |
181 | #define TLB_LOOP_TIMEOUT 1000000 /* 1s! */ | |
182 | ||
183 | /* Stream mapping registers */ | |
184 | #define ARM_SMMU_GR0_SMR(n) (0x800 + ((n) << 2)) | |
185 | #define SMR_VALID (1 << 31) | |
186 | #define SMR_MASK_SHIFT 16 | |
187 | #define SMR_MASK_MASK 0x7fff | |
188 | #define SMR_ID_SHIFT 0 | |
189 | #define SMR_ID_MASK 0x7fff | |
190 | ||
191 | #define ARM_SMMU_GR0_S2CR(n) (0xc00 + ((n) << 2)) | |
192 | #define S2CR_CBNDX_SHIFT 0 | |
193 | #define S2CR_CBNDX_MASK 0xff | |
194 | #define S2CR_TYPE_SHIFT 16 | |
195 | #define S2CR_TYPE_MASK 0x3 | |
196 | #define S2CR_TYPE_TRANS (0 << S2CR_TYPE_SHIFT) | |
197 | #define S2CR_TYPE_BYPASS (1 << S2CR_TYPE_SHIFT) | |
198 | #define S2CR_TYPE_FAULT (2 << S2CR_TYPE_SHIFT) | |
199 | ||
200 | /* Context bank attribute registers */ | |
201 | #define ARM_SMMU_GR1_CBAR(n) (0x0 + ((n) << 2)) | |
202 | #define CBAR_VMID_SHIFT 0 | |
203 | #define CBAR_VMID_MASK 0xff | |
57ca90f6 WD |
204 | #define CBAR_S1_BPSHCFG_SHIFT 8 |
205 | #define CBAR_S1_BPSHCFG_MASK 3 | |
206 | #define CBAR_S1_BPSHCFG_NSH 3 | |
45ae7cff WD |
207 | #define CBAR_S1_MEMATTR_SHIFT 12 |
208 | #define CBAR_S1_MEMATTR_MASK 0xf | |
209 | #define CBAR_S1_MEMATTR_WB 0xf | |
210 | #define CBAR_TYPE_SHIFT 16 | |
211 | #define CBAR_TYPE_MASK 0x3 | |
212 | #define CBAR_TYPE_S2_TRANS (0 << CBAR_TYPE_SHIFT) | |
213 | #define CBAR_TYPE_S1_TRANS_S2_BYPASS (1 << CBAR_TYPE_SHIFT) | |
214 | #define CBAR_TYPE_S1_TRANS_S2_FAULT (2 << CBAR_TYPE_SHIFT) | |
215 | #define CBAR_TYPE_S1_TRANS_S2_TRANS (3 << CBAR_TYPE_SHIFT) | |
216 | #define CBAR_IRPTNDX_SHIFT 24 | |
217 | #define CBAR_IRPTNDX_MASK 0xff | |
218 | ||
219 | #define ARM_SMMU_GR1_CBA2R(n) (0x800 + ((n) << 2)) | |
220 | #define CBA2R_RW64_32BIT (0 << 0) | |
221 | #define CBA2R_RW64_64BIT (1 << 0) | |
222 | ||
223 | /* Translation context bank */ | |
224 | #define ARM_SMMU_CB_BASE(smmu) ((smmu)->base + ((smmu)->size >> 1)) | |
225 | #define ARM_SMMU_CB(smmu, n) ((n) * (smmu)->pagesize) | |
226 | ||
227 | #define ARM_SMMU_CB_SCTLR 0x0 | |
228 | #define ARM_SMMU_CB_RESUME 0x8 | |
229 | #define ARM_SMMU_CB_TTBCR2 0x10 | |
230 | #define ARM_SMMU_CB_TTBR0_LO 0x20 | |
231 | #define ARM_SMMU_CB_TTBR0_HI 0x24 | |
232 | #define ARM_SMMU_CB_TTBCR 0x30 | |
233 | #define ARM_SMMU_CB_S1_MAIR0 0x38 | |
234 | #define ARM_SMMU_CB_FSR 0x58 | |
235 | #define ARM_SMMU_CB_FAR_LO 0x60 | |
236 | #define ARM_SMMU_CB_FAR_HI 0x64 | |
237 | #define ARM_SMMU_CB_FSYNR0 0x68 | |
1463fe44 | 238 | #define ARM_SMMU_CB_S1_TLBIASID 0x610 |
45ae7cff WD |
239 | |
240 | #define SCTLR_S1_ASIDPNE (1 << 12) | |
241 | #define SCTLR_CFCFG (1 << 7) | |
242 | #define SCTLR_CFIE (1 << 6) | |
243 | #define SCTLR_CFRE (1 << 5) | |
244 | #define SCTLR_E (1 << 4) | |
245 | #define SCTLR_AFE (1 << 2) | |
246 | #define SCTLR_TRE (1 << 1) | |
247 | #define SCTLR_M (1 << 0) | |
248 | #define SCTLR_EAE_SBOP (SCTLR_AFE | SCTLR_TRE) | |
249 | ||
250 | #define RESUME_RETRY (0 << 0) | |
251 | #define RESUME_TERMINATE (1 << 0) | |
252 | ||
253 | #define TTBCR_EAE (1 << 31) | |
254 | ||
255 | #define TTBCR_PASIZE_SHIFT 16 | |
256 | #define TTBCR_PASIZE_MASK 0x7 | |
257 | ||
258 | #define TTBCR_TG0_4K (0 << 14) | |
259 | #define TTBCR_TG0_64K (1 << 14) | |
260 | ||
261 | #define TTBCR_SH0_SHIFT 12 | |
262 | #define TTBCR_SH0_MASK 0x3 | |
263 | #define TTBCR_SH_NS 0 | |
264 | #define TTBCR_SH_OS 2 | |
265 | #define TTBCR_SH_IS 3 | |
266 | ||
267 | #define TTBCR_ORGN0_SHIFT 10 | |
268 | #define TTBCR_IRGN0_SHIFT 8 | |
269 | #define TTBCR_RGN_MASK 0x3 | |
270 | #define TTBCR_RGN_NC 0 | |
271 | #define TTBCR_RGN_WBWA 1 | |
272 | #define TTBCR_RGN_WT 2 | |
273 | #define TTBCR_RGN_WB 3 | |
274 | ||
275 | #define TTBCR_SL0_SHIFT 6 | |
276 | #define TTBCR_SL0_MASK 0x3 | |
277 | #define TTBCR_SL0_LVL_2 0 | |
278 | #define TTBCR_SL0_LVL_1 1 | |
279 | ||
280 | #define TTBCR_T1SZ_SHIFT 16 | |
281 | #define TTBCR_T0SZ_SHIFT 0 | |
282 | #define TTBCR_SZ_MASK 0xf | |
283 | ||
284 | #define TTBCR2_SEP_SHIFT 15 | |
285 | #define TTBCR2_SEP_MASK 0x7 | |
286 | ||
287 | #define TTBCR2_PASIZE_SHIFT 0 | |
288 | #define TTBCR2_PASIZE_MASK 0x7 | |
289 | ||
290 | /* Common definitions for PASize and SEP fields */ | |
291 | #define TTBCR2_ADDR_32 0 | |
292 | #define TTBCR2_ADDR_36 1 | |
293 | #define TTBCR2_ADDR_40 2 | |
294 | #define TTBCR2_ADDR_42 3 | |
295 | #define TTBCR2_ADDR_44 4 | |
296 | #define TTBCR2_ADDR_48 5 | |
297 | ||
1463fe44 WD |
298 | #define TTBRn_HI_ASID_SHIFT 16 |
299 | ||
45ae7cff WD |
300 | #define MAIR_ATTR_SHIFT(n) ((n) << 3) |
301 | #define MAIR_ATTR_MASK 0xff | |
302 | #define MAIR_ATTR_DEVICE 0x04 | |
303 | #define MAIR_ATTR_NC 0x44 | |
304 | #define MAIR_ATTR_WBRWA 0xff | |
305 | #define MAIR_ATTR_IDX_NC 0 | |
306 | #define MAIR_ATTR_IDX_CACHE 1 | |
307 | #define MAIR_ATTR_IDX_DEV 2 | |
308 | ||
309 | #define FSR_MULTI (1 << 31) | |
310 | #define FSR_SS (1 << 30) | |
311 | #define FSR_UUT (1 << 8) | |
312 | #define FSR_ASF (1 << 7) | |
313 | #define FSR_TLBLKF (1 << 6) | |
314 | #define FSR_TLBMCF (1 << 5) | |
315 | #define FSR_EF (1 << 4) | |
316 | #define FSR_PF (1 << 3) | |
317 | #define FSR_AFF (1 << 2) | |
318 | #define FSR_TF (1 << 1) | |
319 | ||
2907320d MH |
320 | #define FSR_IGN (FSR_AFF | FSR_ASF | \ |
321 | FSR_TLBMCF | FSR_TLBLKF) | |
322 | #define FSR_FAULT (FSR_MULTI | FSR_SS | FSR_UUT | \ | |
adaba320 | 323 | FSR_EF | FSR_PF | FSR_TF | FSR_IGN) |
45ae7cff WD |
324 | |
325 | #define FSYNR0_WNR (1 << 4) | |
326 | ||
327 | struct arm_smmu_smr { | |
328 | u8 idx; | |
329 | u16 mask; | |
330 | u16 id; | |
331 | }; | |
332 | ||
a9a1b0b5 | 333 | struct arm_smmu_master_cfg { |
45ae7cff WD |
334 | int num_streamids; |
335 | u16 streamids[MAX_MASTER_STREAMIDS]; | |
45ae7cff WD |
336 | struct arm_smmu_smr *smrs; |
337 | }; | |
338 | ||
a9a1b0b5 WD |
339 | struct arm_smmu_master { |
340 | struct device_node *of_node; | |
a9a1b0b5 WD |
341 | struct rb_node node; |
342 | struct arm_smmu_master_cfg cfg; | |
343 | }; | |
344 | ||
45ae7cff WD |
345 | struct arm_smmu_device { |
346 | struct device *dev; | |
45ae7cff WD |
347 | |
348 | void __iomem *base; | |
349 | unsigned long size; | |
350 | unsigned long pagesize; | |
351 | ||
352 | #define ARM_SMMU_FEAT_COHERENT_WALK (1 << 0) | |
353 | #define ARM_SMMU_FEAT_STREAM_MATCH (1 << 1) | |
354 | #define ARM_SMMU_FEAT_TRANS_S1 (1 << 2) | |
355 | #define ARM_SMMU_FEAT_TRANS_S2 (1 << 3) | |
356 | #define ARM_SMMU_FEAT_TRANS_NESTED (1 << 4) | |
357 | u32 features; | |
3a5df8ff AH |
358 | |
359 | #define ARM_SMMU_OPT_SECURE_CFG_ACCESS (1 << 0) | |
360 | u32 options; | |
45ae7cff WD |
361 | int version; |
362 | ||
363 | u32 num_context_banks; | |
364 | u32 num_s2_context_banks; | |
365 | DECLARE_BITMAP(context_map, ARM_SMMU_MAX_CBS); | |
366 | atomic_t irptndx; | |
367 | ||
368 | u32 num_mapping_groups; | |
369 | DECLARE_BITMAP(smr_map, ARM_SMMU_MAX_SMRS); | |
370 | ||
371 | unsigned long input_size; | |
372 | unsigned long s1_output_size; | |
373 | unsigned long s2_output_size; | |
374 | ||
375 | u32 num_global_irqs; | |
376 | u32 num_context_irqs; | |
377 | unsigned int *irqs; | |
378 | ||
45ae7cff WD |
379 | struct list_head list; |
380 | struct rb_root masters; | |
381 | }; | |
382 | ||
383 | struct arm_smmu_cfg { | |
45ae7cff WD |
384 | u8 cbndx; |
385 | u8 irptndx; | |
386 | u32 cbar; | |
387 | pgd_t *pgd; | |
388 | }; | |
faea13b7 | 389 | #define INVALID_IRPTNDX 0xff |
45ae7cff | 390 | |
ecfadb6e WD |
391 | #define ARM_SMMU_CB_ASID(cfg) ((cfg)->cbndx) |
392 | #define ARM_SMMU_CB_VMID(cfg) ((cfg)->cbndx + 1) | |
393 | ||
45ae7cff | 394 | struct arm_smmu_domain { |
44680eed WD |
395 | struct arm_smmu_device *smmu; |
396 | struct arm_smmu_cfg cfg; | |
c9d09e27 | 397 | spinlock_t lock; |
45ae7cff WD |
398 | }; |
399 | ||
400 | static DEFINE_SPINLOCK(arm_smmu_devices_lock); | |
401 | static LIST_HEAD(arm_smmu_devices); | |
402 | ||
3a5df8ff AH |
403 | struct arm_smmu_option_prop { |
404 | u32 opt; | |
405 | const char *prop; | |
406 | }; | |
407 | ||
2907320d | 408 | static struct arm_smmu_option_prop arm_smmu_options[] = { |
3a5df8ff AH |
409 | { ARM_SMMU_OPT_SECURE_CFG_ACCESS, "calxeda,smmu-secure-config-access" }, |
410 | { 0, NULL}, | |
411 | }; | |
412 | ||
413 | static void parse_driver_options(struct arm_smmu_device *smmu) | |
414 | { | |
415 | int i = 0; | |
2907320d | 416 | |
3a5df8ff AH |
417 | do { |
418 | if (of_property_read_bool(smmu->dev->of_node, | |
419 | arm_smmu_options[i].prop)) { | |
420 | smmu->options |= arm_smmu_options[i].opt; | |
421 | dev_notice(smmu->dev, "option %s\n", | |
422 | arm_smmu_options[i].prop); | |
423 | } | |
424 | } while (arm_smmu_options[++i].opt); | |
425 | } | |
426 | ||
a9a1b0b5 WD |
427 | static struct device *dev_get_master_dev(struct device *dev) |
428 | { | |
429 | if (dev_is_pci(dev)) { | |
430 | struct pci_bus *bus = to_pci_dev(dev)->bus; | |
2907320d | 431 | |
a9a1b0b5 WD |
432 | while (!pci_is_root_bus(bus)) |
433 | bus = bus->parent; | |
434 | return bus->bridge->parent; | |
435 | } | |
436 | ||
437 | return dev; | |
438 | } | |
439 | ||
45ae7cff WD |
440 | static struct arm_smmu_master *find_smmu_master(struct arm_smmu_device *smmu, |
441 | struct device_node *dev_node) | |
442 | { | |
443 | struct rb_node *node = smmu->masters.rb_node; | |
444 | ||
445 | while (node) { | |
446 | struct arm_smmu_master *master; | |
2907320d | 447 | |
45ae7cff WD |
448 | master = container_of(node, struct arm_smmu_master, node); |
449 | ||
450 | if (dev_node < master->of_node) | |
451 | node = node->rb_left; | |
452 | else if (dev_node > master->of_node) | |
453 | node = node->rb_right; | |
454 | else | |
455 | return master; | |
456 | } | |
457 | ||
458 | return NULL; | |
459 | } | |
460 | ||
a9a1b0b5 WD |
461 | static struct arm_smmu_master_cfg * |
462 | find_smmu_master_cfg(struct arm_smmu_device *smmu, struct device *dev) | |
463 | { | |
464 | struct arm_smmu_master *master; | |
465 | ||
466 | if (dev_is_pci(dev)) | |
467 | return dev->archdata.iommu; | |
468 | ||
469 | master = find_smmu_master(smmu, dev->of_node); | |
470 | return master ? &master->cfg : NULL; | |
471 | } | |
472 | ||
45ae7cff WD |
473 | static int insert_smmu_master(struct arm_smmu_device *smmu, |
474 | struct arm_smmu_master *master) | |
475 | { | |
476 | struct rb_node **new, *parent; | |
477 | ||
478 | new = &smmu->masters.rb_node; | |
479 | parent = NULL; | |
480 | while (*new) { | |
2907320d MH |
481 | struct arm_smmu_master *this |
482 | = container_of(*new, struct arm_smmu_master, node); | |
45ae7cff WD |
483 | |
484 | parent = *new; | |
485 | if (master->of_node < this->of_node) | |
486 | new = &((*new)->rb_left); | |
487 | else if (master->of_node > this->of_node) | |
488 | new = &((*new)->rb_right); | |
489 | else | |
490 | return -EEXIST; | |
491 | } | |
492 | ||
493 | rb_link_node(&master->node, parent, new); | |
494 | rb_insert_color(&master->node, &smmu->masters); | |
495 | return 0; | |
496 | } | |
497 | ||
498 | static int register_smmu_master(struct arm_smmu_device *smmu, | |
499 | struct device *dev, | |
500 | struct of_phandle_args *masterspec) | |
501 | { | |
502 | int i; | |
503 | struct arm_smmu_master *master; | |
504 | ||
505 | master = find_smmu_master(smmu, masterspec->np); | |
506 | if (master) { | |
507 | dev_err(dev, | |
508 | "rejecting multiple registrations for master device %s\n", | |
509 | masterspec->np->name); | |
510 | return -EBUSY; | |
511 | } | |
512 | ||
513 | if (masterspec->args_count > MAX_MASTER_STREAMIDS) { | |
514 | dev_err(dev, | |
515 | "reached maximum number (%d) of stream IDs for master device %s\n", | |
516 | MAX_MASTER_STREAMIDS, masterspec->np->name); | |
517 | return -ENOSPC; | |
518 | } | |
519 | ||
520 | master = devm_kzalloc(dev, sizeof(*master), GFP_KERNEL); | |
521 | if (!master) | |
522 | return -ENOMEM; | |
523 | ||
a9a1b0b5 WD |
524 | master->of_node = masterspec->np; |
525 | master->cfg.num_streamids = masterspec->args_count; | |
45ae7cff | 526 | |
a9a1b0b5 WD |
527 | for (i = 0; i < master->cfg.num_streamids; ++i) |
528 | master->cfg.streamids[i] = masterspec->args[i]; | |
45ae7cff WD |
529 | |
530 | return insert_smmu_master(smmu, master); | |
531 | } | |
532 | ||
44680eed | 533 | static struct arm_smmu_device *find_smmu_for_device(struct device *dev) |
45ae7cff | 534 | { |
44680eed | 535 | struct arm_smmu_device *smmu; |
a9a1b0b5 WD |
536 | struct arm_smmu_master *master = NULL; |
537 | struct device_node *dev_node = dev_get_master_dev(dev)->of_node; | |
45ae7cff WD |
538 | |
539 | spin_lock(&arm_smmu_devices_lock); | |
44680eed | 540 | list_for_each_entry(smmu, &arm_smmu_devices, list) { |
a9a1b0b5 WD |
541 | master = find_smmu_master(smmu, dev_node); |
542 | if (master) | |
543 | break; | |
544 | } | |
45ae7cff | 545 | spin_unlock(&arm_smmu_devices_lock); |
44680eed | 546 | |
a9a1b0b5 | 547 | return master ? smmu : NULL; |
45ae7cff WD |
548 | } |
549 | ||
550 | static int __arm_smmu_alloc_bitmap(unsigned long *map, int start, int end) | |
551 | { | |
552 | int idx; | |
553 | ||
554 | do { | |
555 | idx = find_next_zero_bit(map, end, start); | |
556 | if (idx == end) | |
557 | return -ENOSPC; | |
558 | } while (test_and_set_bit(idx, map)); | |
559 | ||
560 | return idx; | |
561 | } | |
562 | ||
563 | static void __arm_smmu_free_bitmap(unsigned long *map, int idx) | |
564 | { | |
565 | clear_bit(idx, map); | |
566 | } | |
567 | ||
568 | /* Wait for any pending TLB invalidations to complete */ | |
569 | static void arm_smmu_tlb_sync(struct arm_smmu_device *smmu) | |
570 | { | |
571 | int count = 0; | |
572 | void __iomem *gr0_base = ARM_SMMU_GR0(smmu); | |
573 | ||
574 | writel_relaxed(0, gr0_base + ARM_SMMU_GR0_sTLBGSYNC); | |
575 | while (readl_relaxed(gr0_base + ARM_SMMU_GR0_sTLBGSTATUS) | |
576 | & sTLBGSTATUS_GSACTIVE) { | |
577 | cpu_relax(); | |
578 | if (++count == TLB_LOOP_TIMEOUT) { | |
579 | dev_err_ratelimited(smmu->dev, | |
580 | "TLB sync timed out -- SMMU may be deadlocked\n"); | |
581 | return; | |
582 | } | |
583 | udelay(1); | |
584 | } | |
585 | } | |
586 | ||
44680eed | 587 | static void arm_smmu_tlb_inv_context(struct arm_smmu_domain *smmu_domain) |
1463fe44 | 588 | { |
44680eed WD |
589 | struct arm_smmu_cfg *cfg = &smmu_domain->cfg; |
590 | struct arm_smmu_device *smmu = smmu_domain->smmu; | |
1463fe44 WD |
591 | void __iomem *base = ARM_SMMU_GR0(smmu); |
592 | bool stage1 = cfg->cbar != CBAR_TYPE_S2_TRANS; | |
593 | ||
594 | if (stage1) { | |
595 | base = ARM_SMMU_CB_BASE(smmu) + ARM_SMMU_CB(smmu, cfg->cbndx); | |
ecfadb6e WD |
596 | writel_relaxed(ARM_SMMU_CB_ASID(cfg), |
597 | base + ARM_SMMU_CB_S1_TLBIASID); | |
1463fe44 WD |
598 | } else { |
599 | base = ARM_SMMU_GR0(smmu); | |
ecfadb6e WD |
600 | writel_relaxed(ARM_SMMU_CB_VMID(cfg), |
601 | base + ARM_SMMU_GR0_TLBIVMID); | |
1463fe44 WD |
602 | } |
603 | ||
604 | arm_smmu_tlb_sync(smmu); | |
605 | } | |
606 | ||
45ae7cff WD |
607 | static irqreturn_t arm_smmu_context_fault(int irq, void *dev) |
608 | { | |
609 | int flags, ret; | |
610 | u32 fsr, far, fsynr, resume; | |
611 | unsigned long iova; | |
612 | struct iommu_domain *domain = dev; | |
613 | struct arm_smmu_domain *smmu_domain = domain->priv; | |
44680eed WD |
614 | struct arm_smmu_cfg *cfg = &smmu_domain->cfg; |
615 | struct arm_smmu_device *smmu = smmu_domain->smmu; | |
45ae7cff WD |
616 | void __iomem *cb_base; |
617 | ||
44680eed | 618 | cb_base = ARM_SMMU_CB_BASE(smmu) + ARM_SMMU_CB(smmu, cfg->cbndx); |
45ae7cff WD |
619 | fsr = readl_relaxed(cb_base + ARM_SMMU_CB_FSR); |
620 | ||
621 | if (!(fsr & FSR_FAULT)) | |
622 | return IRQ_NONE; | |
623 | ||
624 | if (fsr & FSR_IGN) | |
625 | dev_err_ratelimited(smmu->dev, | |
626 | "Unexpected context fault (fsr 0x%u)\n", | |
627 | fsr); | |
628 | ||
629 | fsynr = readl_relaxed(cb_base + ARM_SMMU_CB_FSYNR0); | |
630 | flags = fsynr & FSYNR0_WNR ? IOMMU_FAULT_WRITE : IOMMU_FAULT_READ; | |
631 | ||
632 | far = readl_relaxed(cb_base + ARM_SMMU_CB_FAR_LO); | |
633 | iova = far; | |
634 | #ifdef CONFIG_64BIT | |
635 | far = readl_relaxed(cb_base + ARM_SMMU_CB_FAR_HI); | |
636 | iova |= ((unsigned long)far << 32); | |
637 | #endif | |
638 | ||
639 | if (!report_iommu_fault(domain, smmu->dev, iova, flags)) { | |
640 | ret = IRQ_HANDLED; | |
641 | resume = RESUME_RETRY; | |
642 | } else { | |
2ef0f031 AH |
643 | dev_err_ratelimited(smmu->dev, |
644 | "Unhandled context fault: iova=0x%08lx, fsynr=0x%x, cb=%d\n", | |
44680eed | 645 | iova, fsynr, cfg->cbndx); |
45ae7cff WD |
646 | ret = IRQ_NONE; |
647 | resume = RESUME_TERMINATE; | |
648 | } | |
649 | ||
650 | /* Clear the faulting FSR */ | |
651 | writel(fsr, cb_base + ARM_SMMU_CB_FSR); | |
652 | ||
653 | /* Retry or terminate any stalled transactions */ | |
654 | if (fsr & FSR_SS) | |
655 | writel_relaxed(resume, cb_base + ARM_SMMU_CB_RESUME); | |
656 | ||
657 | return ret; | |
658 | } | |
659 | ||
660 | static irqreturn_t arm_smmu_global_fault(int irq, void *dev) | |
661 | { | |
662 | u32 gfsr, gfsynr0, gfsynr1, gfsynr2; | |
663 | struct arm_smmu_device *smmu = dev; | |
3a5df8ff | 664 | void __iomem *gr0_base = ARM_SMMU_GR0_NS(smmu); |
45ae7cff WD |
665 | |
666 | gfsr = readl_relaxed(gr0_base + ARM_SMMU_GR0_sGFSR); | |
667 | gfsynr0 = readl_relaxed(gr0_base + ARM_SMMU_GR0_sGFSYNR0); | |
668 | gfsynr1 = readl_relaxed(gr0_base + ARM_SMMU_GR0_sGFSYNR1); | |
669 | gfsynr2 = readl_relaxed(gr0_base + ARM_SMMU_GR0_sGFSYNR2); | |
670 | ||
3a5df8ff AH |
671 | if (!gfsr) |
672 | return IRQ_NONE; | |
673 | ||
45ae7cff WD |
674 | dev_err_ratelimited(smmu->dev, |
675 | "Unexpected global fault, this could be serious\n"); | |
676 | dev_err_ratelimited(smmu->dev, | |
677 | "\tGFSR 0x%08x, GFSYNR0 0x%08x, GFSYNR1 0x%08x, GFSYNR2 0x%08x\n", | |
678 | gfsr, gfsynr0, gfsynr1, gfsynr2); | |
679 | ||
680 | writel(gfsr, gr0_base + ARM_SMMU_GR0_sGFSR); | |
adaba320 | 681 | return IRQ_HANDLED; |
45ae7cff WD |
682 | } |
683 | ||
6dd35f45 WD |
684 | static void arm_smmu_flush_pgtable(struct arm_smmu_device *smmu, void *addr, |
685 | size_t size) | |
686 | { | |
687 | unsigned long offset = (unsigned long)addr & ~PAGE_MASK; | |
688 | ||
689 | ||
690 | /* Ensure new page tables are visible to the hardware walker */ | |
691 | if (smmu->features & ARM_SMMU_FEAT_COHERENT_WALK) { | |
3aa80ea4 | 692 | dsb(ishst); |
6dd35f45 WD |
693 | } else { |
694 | /* | |
695 | * If the SMMU can't walk tables in the CPU caches, treat them | |
696 | * like non-coherent DMA since we need to flush the new entries | |
697 | * all the way out to memory. There's no possibility of | |
698 | * recursion here as the SMMU table walker will not be wired | |
699 | * through another SMMU. | |
700 | */ | |
701 | dma_map_page(smmu->dev, virt_to_page(addr), offset, size, | |
702 | DMA_TO_DEVICE); | |
703 | } | |
704 | } | |
705 | ||
45ae7cff WD |
706 | static void arm_smmu_init_context_bank(struct arm_smmu_domain *smmu_domain) |
707 | { | |
708 | u32 reg; | |
709 | bool stage1; | |
44680eed WD |
710 | struct arm_smmu_cfg *cfg = &smmu_domain->cfg; |
711 | struct arm_smmu_device *smmu = smmu_domain->smmu; | |
45ae7cff WD |
712 | void __iomem *cb_base, *gr0_base, *gr1_base; |
713 | ||
714 | gr0_base = ARM_SMMU_GR0(smmu); | |
715 | gr1_base = ARM_SMMU_GR1(smmu); | |
44680eed WD |
716 | stage1 = cfg->cbar != CBAR_TYPE_S2_TRANS; |
717 | cb_base = ARM_SMMU_CB_BASE(smmu) + ARM_SMMU_CB(smmu, cfg->cbndx); | |
45ae7cff WD |
718 | |
719 | /* CBAR */ | |
44680eed | 720 | reg = cfg->cbar; |
45ae7cff | 721 | if (smmu->version == 1) |
2907320d | 722 | reg |= cfg->irptndx << CBAR_IRPTNDX_SHIFT; |
45ae7cff | 723 | |
57ca90f6 WD |
724 | /* |
725 | * Use the weakest shareability/memory types, so they are | |
726 | * overridden by the ttbcr/pte. | |
727 | */ | |
728 | if (stage1) { | |
729 | reg |= (CBAR_S1_BPSHCFG_NSH << CBAR_S1_BPSHCFG_SHIFT) | | |
730 | (CBAR_S1_MEMATTR_WB << CBAR_S1_MEMATTR_SHIFT); | |
731 | } else { | |
44680eed | 732 | reg |= ARM_SMMU_CB_VMID(cfg) << CBAR_VMID_SHIFT; |
57ca90f6 | 733 | } |
44680eed | 734 | writel_relaxed(reg, gr1_base + ARM_SMMU_GR1_CBAR(cfg->cbndx)); |
45ae7cff WD |
735 | |
736 | if (smmu->version > 1) { | |
737 | /* CBA2R */ | |
738 | #ifdef CONFIG_64BIT | |
739 | reg = CBA2R_RW64_64BIT; | |
740 | #else | |
741 | reg = CBA2R_RW64_32BIT; | |
742 | #endif | |
743 | writel_relaxed(reg, | |
44680eed | 744 | gr1_base + ARM_SMMU_GR1_CBA2R(cfg->cbndx)); |
45ae7cff WD |
745 | |
746 | /* TTBCR2 */ | |
747 | switch (smmu->input_size) { | |
748 | case 32: | |
749 | reg = (TTBCR2_ADDR_32 << TTBCR2_SEP_SHIFT); | |
750 | break; | |
751 | case 36: | |
752 | reg = (TTBCR2_ADDR_36 << TTBCR2_SEP_SHIFT); | |
753 | break; | |
754 | case 39: | |
755 | reg = (TTBCR2_ADDR_40 << TTBCR2_SEP_SHIFT); | |
756 | break; | |
757 | case 42: | |
758 | reg = (TTBCR2_ADDR_42 << TTBCR2_SEP_SHIFT); | |
759 | break; | |
760 | case 44: | |
761 | reg = (TTBCR2_ADDR_44 << TTBCR2_SEP_SHIFT); | |
762 | break; | |
763 | case 48: | |
764 | reg = (TTBCR2_ADDR_48 << TTBCR2_SEP_SHIFT); | |
765 | break; | |
766 | } | |
767 | ||
768 | switch (smmu->s1_output_size) { | |
769 | case 32: | |
770 | reg |= (TTBCR2_ADDR_32 << TTBCR2_PASIZE_SHIFT); | |
771 | break; | |
772 | case 36: | |
773 | reg |= (TTBCR2_ADDR_36 << TTBCR2_PASIZE_SHIFT); | |
774 | break; | |
775 | case 39: | |
776 | reg |= (TTBCR2_ADDR_40 << TTBCR2_PASIZE_SHIFT); | |
777 | break; | |
778 | case 42: | |
779 | reg |= (TTBCR2_ADDR_42 << TTBCR2_PASIZE_SHIFT); | |
780 | break; | |
781 | case 44: | |
782 | reg |= (TTBCR2_ADDR_44 << TTBCR2_PASIZE_SHIFT); | |
783 | break; | |
784 | case 48: | |
785 | reg |= (TTBCR2_ADDR_48 << TTBCR2_PASIZE_SHIFT); | |
786 | break; | |
787 | } | |
788 | ||
789 | if (stage1) | |
790 | writel_relaxed(reg, cb_base + ARM_SMMU_CB_TTBCR2); | |
791 | } | |
792 | ||
793 | /* TTBR0 */ | |
44680eed | 794 | arm_smmu_flush_pgtable(smmu, cfg->pgd, |
6dd35f45 | 795 | PTRS_PER_PGD * sizeof(pgd_t)); |
44680eed | 796 | reg = __pa(cfg->pgd); |
45ae7cff | 797 | writel_relaxed(reg, cb_base + ARM_SMMU_CB_TTBR0_LO); |
44680eed | 798 | reg = (phys_addr_t)__pa(cfg->pgd) >> 32; |
1463fe44 | 799 | if (stage1) |
44680eed | 800 | reg |= ARM_SMMU_CB_ASID(cfg) << TTBRn_HI_ASID_SHIFT; |
45ae7cff | 801 | writel_relaxed(reg, cb_base + ARM_SMMU_CB_TTBR0_HI); |
45ae7cff WD |
802 | |
803 | /* | |
804 | * TTBCR | |
805 | * We use long descriptor, with inner-shareable WBWA tables in TTBR0. | |
806 | */ | |
807 | if (smmu->version > 1) { | |
808 | if (PAGE_SIZE == SZ_4K) | |
809 | reg = TTBCR_TG0_4K; | |
810 | else | |
811 | reg = TTBCR_TG0_64K; | |
812 | ||
813 | if (!stage1) { | |
a65217a4 WD |
814 | reg |= (64 - smmu->s1_output_size) << TTBCR_T0SZ_SHIFT; |
815 | ||
45ae7cff WD |
816 | switch (smmu->s2_output_size) { |
817 | case 32: | |
818 | reg |= (TTBCR2_ADDR_32 << TTBCR_PASIZE_SHIFT); | |
819 | break; | |
820 | case 36: | |
821 | reg |= (TTBCR2_ADDR_36 << TTBCR_PASIZE_SHIFT); | |
822 | break; | |
823 | case 40: | |
824 | reg |= (TTBCR2_ADDR_40 << TTBCR_PASIZE_SHIFT); | |
825 | break; | |
826 | case 42: | |
827 | reg |= (TTBCR2_ADDR_42 << TTBCR_PASIZE_SHIFT); | |
828 | break; | |
829 | case 44: | |
830 | reg |= (TTBCR2_ADDR_44 << TTBCR_PASIZE_SHIFT); | |
831 | break; | |
832 | case 48: | |
833 | reg |= (TTBCR2_ADDR_48 << TTBCR_PASIZE_SHIFT); | |
834 | break; | |
835 | } | |
836 | } else { | |
a65217a4 | 837 | reg |= (64 - smmu->input_size) << TTBCR_T0SZ_SHIFT; |
45ae7cff WD |
838 | } |
839 | } else { | |
840 | reg = 0; | |
841 | } | |
842 | ||
843 | reg |= TTBCR_EAE | | |
844 | (TTBCR_SH_IS << TTBCR_SH0_SHIFT) | | |
845 | (TTBCR_RGN_WBWA << TTBCR_ORGN0_SHIFT) | | |
846 | (TTBCR_RGN_WBWA << TTBCR_IRGN0_SHIFT) | | |
847 | (TTBCR_SL0_LVL_1 << TTBCR_SL0_SHIFT); | |
848 | writel_relaxed(reg, cb_base + ARM_SMMU_CB_TTBCR); | |
849 | ||
850 | /* MAIR0 (stage-1 only) */ | |
851 | if (stage1) { | |
852 | reg = (MAIR_ATTR_NC << MAIR_ATTR_SHIFT(MAIR_ATTR_IDX_NC)) | | |
853 | (MAIR_ATTR_WBRWA << MAIR_ATTR_SHIFT(MAIR_ATTR_IDX_CACHE)) | | |
854 | (MAIR_ATTR_DEVICE << MAIR_ATTR_SHIFT(MAIR_ATTR_IDX_DEV)); | |
855 | writel_relaxed(reg, cb_base + ARM_SMMU_CB_S1_MAIR0); | |
856 | } | |
857 | ||
45ae7cff WD |
858 | /* SCTLR */ |
859 | reg = SCTLR_CFCFG | SCTLR_CFIE | SCTLR_CFRE | SCTLR_M | SCTLR_EAE_SBOP; | |
860 | if (stage1) | |
861 | reg |= SCTLR_S1_ASIDPNE; | |
862 | #ifdef __BIG_ENDIAN | |
863 | reg |= SCTLR_E; | |
864 | #endif | |
25724841 | 865 | writel_relaxed(reg, cb_base + ARM_SMMU_CB_SCTLR); |
45ae7cff WD |
866 | } |
867 | ||
868 | static int arm_smmu_init_domain_context(struct iommu_domain *domain, | |
44680eed | 869 | struct arm_smmu_device *smmu) |
45ae7cff WD |
870 | { |
871 | int irq, ret, start; | |
872 | struct arm_smmu_domain *smmu_domain = domain->priv; | |
44680eed | 873 | struct arm_smmu_cfg *cfg = &smmu_domain->cfg; |
45ae7cff | 874 | |
45ae7cff WD |
875 | if (smmu->features & ARM_SMMU_FEAT_TRANS_NESTED) { |
876 | /* | |
877 | * We will likely want to change this if/when KVM gets | |
878 | * involved. | |
879 | */ | |
44680eed | 880 | cfg->cbar = CBAR_TYPE_S1_TRANS_S2_BYPASS; |
45ae7cff | 881 | start = smmu->num_s2_context_banks; |
9c5c92e3 | 882 | } else if (smmu->features & ARM_SMMU_FEAT_TRANS_S1) { |
44680eed | 883 | cfg->cbar = CBAR_TYPE_S1_TRANS_S2_BYPASS; |
45ae7cff | 884 | start = smmu->num_s2_context_banks; |
9c5c92e3 WD |
885 | } else { |
886 | cfg->cbar = CBAR_TYPE_S2_TRANS; | |
887 | start = 0; | |
45ae7cff WD |
888 | } |
889 | ||
890 | ret = __arm_smmu_alloc_bitmap(smmu->context_map, start, | |
891 | smmu->num_context_banks); | |
892 | if (IS_ERR_VALUE(ret)) | |
ecfadb6e | 893 | return ret; |
45ae7cff | 894 | |
44680eed | 895 | cfg->cbndx = ret; |
45ae7cff | 896 | if (smmu->version == 1) { |
44680eed WD |
897 | cfg->irptndx = atomic_inc_return(&smmu->irptndx); |
898 | cfg->irptndx %= smmu->num_context_irqs; | |
45ae7cff | 899 | } else { |
44680eed | 900 | cfg->irptndx = cfg->cbndx; |
45ae7cff WD |
901 | } |
902 | ||
44680eed | 903 | irq = smmu->irqs[smmu->num_global_irqs + cfg->irptndx]; |
45ae7cff WD |
904 | ret = request_irq(irq, arm_smmu_context_fault, IRQF_SHARED, |
905 | "arm-smmu-context-fault", domain); | |
906 | if (IS_ERR_VALUE(ret)) { | |
907 | dev_err(smmu->dev, "failed to request context IRQ %d (%u)\n", | |
44680eed WD |
908 | cfg->irptndx, irq); |
909 | cfg->irptndx = INVALID_IRPTNDX; | |
45ae7cff WD |
910 | goto out_free_context; |
911 | } | |
912 | ||
44680eed | 913 | smmu_domain->smmu = smmu; |
45ae7cff | 914 | arm_smmu_init_context_bank(smmu_domain); |
a9a1b0b5 | 915 | return 0; |
45ae7cff WD |
916 | |
917 | out_free_context: | |
44680eed | 918 | __arm_smmu_free_bitmap(smmu->context_map, cfg->cbndx); |
45ae7cff WD |
919 | return ret; |
920 | } | |
921 | ||
922 | static void arm_smmu_destroy_domain_context(struct iommu_domain *domain) | |
923 | { | |
924 | struct arm_smmu_domain *smmu_domain = domain->priv; | |
44680eed WD |
925 | struct arm_smmu_device *smmu = smmu_domain->smmu; |
926 | struct arm_smmu_cfg *cfg = &smmu_domain->cfg; | |
1463fe44 | 927 | void __iomem *cb_base; |
45ae7cff WD |
928 | int irq; |
929 | ||
930 | if (!smmu) | |
931 | return; | |
932 | ||
1463fe44 | 933 | /* Disable the context bank and nuke the TLB before freeing it. */ |
44680eed | 934 | cb_base = ARM_SMMU_CB_BASE(smmu) + ARM_SMMU_CB(smmu, cfg->cbndx); |
1463fe44 | 935 | writel_relaxed(0, cb_base + ARM_SMMU_CB_SCTLR); |
44680eed | 936 | arm_smmu_tlb_inv_context(smmu_domain); |
1463fe44 | 937 | |
44680eed WD |
938 | if (cfg->irptndx != INVALID_IRPTNDX) { |
939 | irq = smmu->irqs[smmu->num_global_irqs + cfg->irptndx]; | |
45ae7cff WD |
940 | free_irq(irq, domain); |
941 | } | |
942 | ||
44680eed | 943 | __arm_smmu_free_bitmap(smmu->context_map, cfg->cbndx); |
45ae7cff WD |
944 | } |
945 | ||
946 | static int arm_smmu_domain_init(struct iommu_domain *domain) | |
947 | { | |
948 | struct arm_smmu_domain *smmu_domain; | |
949 | pgd_t *pgd; | |
950 | ||
951 | /* | |
952 | * Allocate the domain and initialise some of its data structures. | |
953 | * We can't really do anything meaningful until we've added a | |
954 | * master. | |
955 | */ | |
956 | smmu_domain = kzalloc(sizeof(*smmu_domain), GFP_KERNEL); | |
957 | if (!smmu_domain) | |
958 | return -ENOMEM; | |
959 | ||
2907320d | 960 | pgd = kcalloc(PTRS_PER_PGD, sizeof(pgd_t), GFP_KERNEL); |
45ae7cff WD |
961 | if (!pgd) |
962 | goto out_free_domain; | |
44680eed | 963 | smmu_domain->cfg.pgd = pgd; |
45ae7cff | 964 | |
c9d09e27 | 965 | spin_lock_init(&smmu_domain->lock); |
45ae7cff WD |
966 | domain->priv = smmu_domain; |
967 | return 0; | |
968 | ||
969 | out_free_domain: | |
970 | kfree(smmu_domain); | |
971 | return -ENOMEM; | |
972 | } | |
973 | ||
974 | static void arm_smmu_free_ptes(pmd_t *pmd) | |
975 | { | |
976 | pgtable_t table = pmd_pgtable(*pmd); | |
2907320d | 977 | |
45ae7cff WD |
978 | pgtable_page_dtor(table); |
979 | __free_page(table); | |
980 | } | |
981 | ||
982 | static void arm_smmu_free_pmds(pud_t *pud) | |
983 | { | |
984 | int i; | |
985 | pmd_t *pmd, *pmd_base = pmd_offset(pud, 0); | |
986 | ||
987 | pmd = pmd_base; | |
988 | for (i = 0; i < PTRS_PER_PMD; ++i) { | |
989 | if (pmd_none(*pmd)) | |
990 | continue; | |
991 | ||
992 | arm_smmu_free_ptes(pmd); | |
993 | pmd++; | |
994 | } | |
995 | ||
996 | pmd_free(NULL, pmd_base); | |
997 | } | |
998 | ||
999 | static void arm_smmu_free_puds(pgd_t *pgd) | |
1000 | { | |
1001 | int i; | |
1002 | pud_t *pud, *pud_base = pud_offset(pgd, 0); | |
1003 | ||
1004 | pud = pud_base; | |
1005 | for (i = 0; i < PTRS_PER_PUD; ++i) { | |
1006 | if (pud_none(*pud)) | |
1007 | continue; | |
1008 | ||
1009 | arm_smmu_free_pmds(pud); | |
1010 | pud++; | |
1011 | } | |
1012 | ||
1013 | pud_free(NULL, pud_base); | |
1014 | } | |
1015 | ||
1016 | static void arm_smmu_free_pgtables(struct arm_smmu_domain *smmu_domain) | |
1017 | { | |
1018 | int i; | |
44680eed WD |
1019 | struct arm_smmu_cfg *cfg = &smmu_domain->cfg; |
1020 | pgd_t *pgd, *pgd_base = cfg->pgd; | |
45ae7cff WD |
1021 | |
1022 | /* | |
1023 | * Recursively free the page tables for this domain. We don't | |
34fb4b37 WD |
1024 | * care about speculative TLB filling because the tables should |
1025 | * not be active in any context bank at this point (SCTLR.M is 0). | |
45ae7cff WD |
1026 | */ |
1027 | pgd = pgd_base; | |
1028 | for (i = 0; i < PTRS_PER_PGD; ++i) { | |
1029 | if (pgd_none(*pgd)) | |
1030 | continue; | |
1031 | arm_smmu_free_puds(pgd); | |
1032 | pgd++; | |
1033 | } | |
1034 | ||
1035 | kfree(pgd_base); | |
1036 | } | |
1037 | ||
1038 | static void arm_smmu_domain_destroy(struct iommu_domain *domain) | |
1039 | { | |
1040 | struct arm_smmu_domain *smmu_domain = domain->priv; | |
1463fe44 WD |
1041 | |
1042 | /* | |
1043 | * Free the domain resources. We assume that all devices have | |
1044 | * already been detached. | |
1045 | */ | |
45ae7cff WD |
1046 | arm_smmu_destroy_domain_context(domain); |
1047 | arm_smmu_free_pgtables(smmu_domain); | |
1048 | kfree(smmu_domain); | |
1049 | } | |
1050 | ||
1051 | static int arm_smmu_master_configure_smrs(struct arm_smmu_device *smmu, | |
a9a1b0b5 | 1052 | struct arm_smmu_master_cfg *cfg) |
45ae7cff WD |
1053 | { |
1054 | int i; | |
1055 | struct arm_smmu_smr *smrs; | |
1056 | void __iomem *gr0_base = ARM_SMMU_GR0(smmu); | |
1057 | ||
1058 | if (!(smmu->features & ARM_SMMU_FEAT_STREAM_MATCH)) | |
1059 | return 0; | |
1060 | ||
a9a1b0b5 | 1061 | if (cfg->smrs) |
45ae7cff WD |
1062 | return -EEXIST; |
1063 | ||
2907320d | 1064 | smrs = kmalloc_array(cfg->num_streamids, sizeof(*smrs), GFP_KERNEL); |
45ae7cff | 1065 | if (!smrs) { |
a9a1b0b5 WD |
1066 | dev_err(smmu->dev, "failed to allocate %d SMRs\n", |
1067 | cfg->num_streamids); | |
45ae7cff WD |
1068 | return -ENOMEM; |
1069 | } | |
1070 | ||
44680eed | 1071 | /* Allocate the SMRs on the SMMU */ |
a9a1b0b5 | 1072 | for (i = 0; i < cfg->num_streamids; ++i) { |
45ae7cff WD |
1073 | int idx = __arm_smmu_alloc_bitmap(smmu->smr_map, 0, |
1074 | smmu->num_mapping_groups); | |
1075 | if (IS_ERR_VALUE(idx)) { | |
1076 | dev_err(smmu->dev, "failed to allocate free SMR\n"); | |
1077 | goto err_free_smrs; | |
1078 | } | |
1079 | ||
1080 | smrs[i] = (struct arm_smmu_smr) { | |
1081 | .idx = idx, | |
1082 | .mask = 0, /* We don't currently share SMRs */ | |
a9a1b0b5 | 1083 | .id = cfg->streamids[i], |
45ae7cff WD |
1084 | }; |
1085 | } | |
1086 | ||
1087 | /* It worked! Now, poke the actual hardware */ | |
a9a1b0b5 | 1088 | for (i = 0; i < cfg->num_streamids; ++i) { |
45ae7cff WD |
1089 | u32 reg = SMR_VALID | smrs[i].id << SMR_ID_SHIFT | |
1090 | smrs[i].mask << SMR_MASK_SHIFT; | |
1091 | writel_relaxed(reg, gr0_base + ARM_SMMU_GR0_SMR(smrs[i].idx)); | |
1092 | } | |
1093 | ||
a9a1b0b5 | 1094 | cfg->smrs = smrs; |
45ae7cff WD |
1095 | return 0; |
1096 | ||
1097 | err_free_smrs: | |
1098 | while (--i >= 0) | |
1099 | __arm_smmu_free_bitmap(smmu->smr_map, smrs[i].idx); | |
1100 | kfree(smrs); | |
1101 | return -ENOSPC; | |
1102 | } | |
1103 | ||
1104 | static void arm_smmu_master_free_smrs(struct arm_smmu_device *smmu, | |
a9a1b0b5 | 1105 | struct arm_smmu_master_cfg *cfg) |
45ae7cff WD |
1106 | { |
1107 | int i; | |
1108 | void __iomem *gr0_base = ARM_SMMU_GR0(smmu); | |
a9a1b0b5 | 1109 | struct arm_smmu_smr *smrs = cfg->smrs; |
45ae7cff WD |
1110 | |
1111 | /* Invalidate the SMRs before freeing back to the allocator */ | |
a9a1b0b5 | 1112 | for (i = 0; i < cfg->num_streamids; ++i) { |
45ae7cff | 1113 | u8 idx = smrs[i].idx; |
2907320d | 1114 | |
45ae7cff WD |
1115 | writel_relaxed(~SMR_VALID, gr0_base + ARM_SMMU_GR0_SMR(idx)); |
1116 | __arm_smmu_free_bitmap(smmu->smr_map, idx); | |
1117 | } | |
1118 | ||
a9a1b0b5 | 1119 | cfg->smrs = NULL; |
45ae7cff WD |
1120 | kfree(smrs); |
1121 | } | |
1122 | ||
1123 | static void arm_smmu_bypass_stream_mapping(struct arm_smmu_device *smmu, | |
a9a1b0b5 | 1124 | struct arm_smmu_master_cfg *cfg) |
45ae7cff WD |
1125 | { |
1126 | int i; | |
1127 | void __iomem *gr0_base = ARM_SMMU_GR0(smmu); | |
1128 | ||
a9a1b0b5 WD |
1129 | for (i = 0; i < cfg->num_streamids; ++i) { |
1130 | u16 sid = cfg->streamids[i]; | |
2907320d | 1131 | |
45ae7cff WD |
1132 | writel_relaxed(S2CR_TYPE_BYPASS, |
1133 | gr0_base + ARM_SMMU_GR0_S2CR(sid)); | |
1134 | } | |
1135 | } | |
1136 | ||
1137 | static int arm_smmu_domain_add_master(struct arm_smmu_domain *smmu_domain, | |
a9a1b0b5 | 1138 | struct arm_smmu_master_cfg *cfg) |
45ae7cff WD |
1139 | { |
1140 | int i, ret; | |
44680eed | 1141 | struct arm_smmu_device *smmu = smmu_domain->smmu; |
45ae7cff WD |
1142 | void __iomem *gr0_base = ARM_SMMU_GR0(smmu); |
1143 | ||
a9a1b0b5 | 1144 | ret = arm_smmu_master_configure_smrs(smmu, cfg); |
45ae7cff WD |
1145 | if (ret) |
1146 | return ret; | |
1147 | ||
a9a1b0b5 | 1148 | for (i = 0; i < cfg->num_streamids; ++i) { |
45ae7cff | 1149 | u32 idx, s2cr; |
2907320d | 1150 | |
a9a1b0b5 | 1151 | idx = cfg->smrs ? cfg->smrs[i].idx : cfg->streamids[i]; |
6069d23c | 1152 | s2cr = S2CR_TYPE_TRANS | |
44680eed | 1153 | (smmu_domain->cfg.cbndx << S2CR_CBNDX_SHIFT); |
45ae7cff WD |
1154 | writel_relaxed(s2cr, gr0_base + ARM_SMMU_GR0_S2CR(idx)); |
1155 | } | |
1156 | ||
1157 | return 0; | |
1158 | } | |
1159 | ||
1160 | static void arm_smmu_domain_remove_master(struct arm_smmu_domain *smmu_domain, | |
a9a1b0b5 | 1161 | struct arm_smmu_master_cfg *cfg) |
45ae7cff | 1162 | { |
44680eed | 1163 | struct arm_smmu_device *smmu = smmu_domain->smmu; |
45ae7cff WD |
1164 | |
1165 | /* | |
1166 | * We *must* clear the S2CR first, because freeing the SMR means | |
1167 | * that it can be re-allocated immediately. | |
1168 | */ | |
a9a1b0b5 WD |
1169 | arm_smmu_bypass_stream_mapping(smmu, cfg); |
1170 | arm_smmu_master_free_smrs(smmu, cfg); | |
45ae7cff WD |
1171 | } |
1172 | ||
1173 | static int arm_smmu_attach_dev(struct iommu_domain *domain, struct device *dev) | |
1174 | { | |
1175 | int ret = -EINVAL; | |
1176 | struct arm_smmu_domain *smmu_domain = domain->priv; | |
44680eed | 1177 | struct arm_smmu_device *smmu; |
a9a1b0b5 | 1178 | struct arm_smmu_master_cfg *cfg; |
972157ca | 1179 | unsigned long flags; |
45ae7cff | 1180 | |
44680eed WD |
1181 | smmu = dev_get_master_dev(dev)->archdata.iommu; |
1182 | if (!smmu) { | |
45ae7cff WD |
1183 | dev_err(dev, "cannot attach to SMMU, is it on the same bus?\n"); |
1184 | return -ENXIO; | |
1185 | } | |
1186 | ||
1187 | /* | |
44680eed WD |
1188 | * Sanity check the domain. We don't support domains across |
1189 | * different SMMUs. | |
45ae7cff | 1190 | */ |
972157ca | 1191 | spin_lock_irqsave(&smmu_domain->lock, flags); |
44680eed | 1192 | if (!smmu_domain->smmu) { |
45ae7cff | 1193 | /* Now that we have a master, we can finalise the domain */ |
44680eed | 1194 | ret = arm_smmu_init_domain_context(domain, smmu); |
45ae7cff WD |
1195 | if (IS_ERR_VALUE(ret)) |
1196 | goto err_unlock; | |
44680eed | 1197 | } else if (smmu_domain->smmu != smmu) { |
45ae7cff WD |
1198 | dev_err(dev, |
1199 | "cannot attach to SMMU %s whilst already attached to domain on SMMU %s\n", | |
44680eed WD |
1200 | dev_name(smmu_domain->smmu->dev), |
1201 | dev_name(smmu->dev)); | |
45ae7cff WD |
1202 | goto err_unlock; |
1203 | } | |
972157ca | 1204 | spin_unlock_irqrestore(&smmu_domain->lock, flags); |
45ae7cff WD |
1205 | |
1206 | /* Looks ok, so add the device to the domain */ | |
44680eed | 1207 | cfg = find_smmu_master_cfg(smmu_domain->smmu, dev); |
a9a1b0b5 | 1208 | if (!cfg) |
45ae7cff WD |
1209 | return -ENODEV; |
1210 | ||
a9a1b0b5 | 1211 | return arm_smmu_domain_add_master(smmu_domain, cfg); |
45ae7cff WD |
1212 | |
1213 | err_unlock: | |
972157ca | 1214 | spin_unlock_irqrestore(&smmu_domain->lock, flags); |
45ae7cff WD |
1215 | return ret; |
1216 | } | |
1217 | ||
1218 | static void arm_smmu_detach_dev(struct iommu_domain *domain, struct device *dev) | |
1219 | { | |
1220 | struct arm_smmu_domain *smmu_domain = domain->priv; | |
a9a1b0b5 | 1221 | struct arm_smmu_master_cfg *cfg; |
45ae7cff | 1222 | |
44680eed | 1223 | cfg = find_smmu_master_cfg(smmu_domain->smmu, dev); |
a9a1b0b5 WD |
1224 | if (cfg) |
1225 | arm_smmu_domain_remove_master(smmu_domain, cfg); | |
45ae7cff WD |
1226 | } |
1227 | ||
45ae7cff WD |
1228 | static bool arm_smmu_pte_is_contiguous_range(unsigned long addr, |
1229 | unsigned long end) | |
1230 | { | |
1231 | return !(addr & ~ARM_SMMU_PTE_CONT_MASK) && | |
1232 | (addr + ARM_SMMU_PTE_CONT_SIZE <= end); | |
1233 | } | |
1234 | ||
1235 | static int arm_smmu_alloc_init_pte(struct arm_smmu_device *smmu, pmd_t *pmd, | |
1236 | unsigned long addr, unsigned long end, | |
b410aed9 | 1237 | unsigned long pfn, int prot, int stage) |
45ae7cff WD |
1238 | { |
1239 | pte_t *pte, *start; | |
cf2d45b1 | 1240 | pteval_t pteval = ARM_SMMU_PTE_PAGE | ARM_SMMU_PTE_AF | ARM_SMMU_PTE_XN; |
45ae7cff WD |
1241 | |
1242 | if (pmd_none(*pmd)) { | |
1243 | /* Allocate a new set of tables */ | |
c9d09e27 | 1244 | pgtable_t table = alloc_page(GFP_ATOMIC|__GFP_ZERO); |
2907320d | 1245 | |
45ae7cff WD |
1246 | if (!table) |
1247 | return -ENOMEM; | |
1248 | ||
6dd35f45 | 1249 | arm_smmu_flush_pgtable(smmu, page_address(table), PAGE_SIZE); |
01058e70 KS |
1250 | if (!pgtable_page_ctor(table)) { |
1251 | __free_page(table); | |
1252 | return -ENOMEM; | |
1253 | } | |
45ae7cff WD |
1254 | pmd_populate(NULL, pmd, table); |
1255 | arm_smmu_flush_pgtable(smmu, pmd, sizeof(*pmd)); | |
1256 | } | |
1257 | ||
1258 | if (stage == 1) { | |
1463fe44 | 1259 | pteval |= ARM_SMMU_PTE_AP_UNPRIV | ARM_SMMU_PTE_nG; |
b410aed9 | 1260 | if (!(prot & IOMMU_WRITE) && (prot & IOMMU_READ)) |
45ae7cff WD |
1261 | pteval |= ARM_SMMU_PTE_AP_RDONLY; |
1262 | ||
b410aed9 | 1263 | if (prot & IOMMU_CACHE) |
45ae7cff WD |
1264 | pteval |= (MAIR_ATTR_IDX_CACHE << |
1265 | ARM_SMMU_PTE_ATTRINDX_SHIFT); | |
1266 | } else { | |
1267 | pteval |= ARM_SMMU_PTE_HAP_FAULT; | |
b410aed9 | 1268 | if (prot & IOMMU_READ) |
45ae7cff | 1269 | pteval |= ARM_SMMU_PTE_HAP_READ; |
b410aed9 | 1270 | if (prot & IOMMU_WRITE) |
45ae7cff | 1271 | pteval |= ARM_SMMU_PTE_HAP_WRITE; |
b410aed9 | 1272 | if (prot & IOMMU_CACHE) |
45ae7cff WD |
1273 | pteval |= ARM_SMMU_PTE_MEMATTR_OIWB; |
1274 | else | |
1275 | pteval |= ARM_SMMU_PTE_MEMATTR_NC; | |
1276 | } | |
1277 | ||
1278 | /* If no access, create a faulting entry to avoid TLB fills */ | |
b410aed9 | 1279 | if (prot & IOMMU_EXEC) |
cf2d45b1 | 1280 | pteval &= ~ARM_SMMU_PTE_XN; |
b410aed9 | 1281 | else if (!(prot & (IOMMU_READ | IOMMU_WRITE))) |
45ae7cff WD |
1282 | pteval &= ~ARM_SMMU_PTE_PAGE; |
1283 | ||
1284 | pteval |= ARM_SMMU_PTE_SH_IS; | |
1285 | start = pmd_page_vaddr(*pmd) + pte_index(addr); | |
1286 | pte = start; | |
1287 | ||
1288 | /* | |
1289 | * Install the page table entries. This is fairly complicated | |
1290 | * since we attempt to make use of the contiguous hint in the | |
1291 | * ptes where possible. The contiguous hint indicates a series | |
1292 | * of ARM_SMMU_PTE_CONT_ENTRIES ptes mapping a physically | |
1293 | * contiguous region with the following constraints: | |
1294 | * | |
1295 | * - The region start is aligned to ARM_SMMU_PTE_CONT_SIZE | |
1296 | * - Each pte in the region has the contiguous hint bit set | |
1297 | * | |
1298 | * This complicates unmapping (also handled by this code, when | |
1299 | * neither IOMMU_READ or IOMMU_WRITE are set) because it is | |
1300 | * possible, yet highly unlikely, that a client may unmap only | |
1301 | * part of a contiguous range. This requires clearing of the | |
1302 | * contiguous hint bits in the range before installing the new | |
1303 | * faulting entries. | |
1304 | * | |
1305 | * Note that re-mapping an address range without first unmapping | |
1306 | * it is not supported, so TLB invalidation is not required here | |
1307 | * and is instead performed at unmap and domain-init time. | |
1308 | */ | |
1309 | do { | |
1310 | int i = 1; | |
2907320d | 1311 | |
45ae7cff WD |
1312 | pteval &= ~ARM_SMMU_PTE_CONT; |
1313 | ||
1314 | if (arm_smmu_pte_is_contiguous_range(addr, end)) { | |
1315 | i = ARM_SMMU_PTE_CONT_ENTRIES; | |
1316 | pteval |= ARM_SMMU_PTE_CONT; | |
1317 | } else if (pte_val(*pte) & | |
1318 | (ARM_SMMU_PTE_CONT | ARM_SMMU_PTE_PAGE)) { | |
1319 | int j; | |
1320 | pte_t *cont_start; | |
1321 | unsigned long idx = pte_index(addr); | |
1322 | ||
1323 | idx &= ~(ARM_SMMU_PTE_CONT_ENTRIES - 1); | |
1324 | cont_start = pmd_page_vaddr(*pmd) + idx; | |
1325 | for (j = 0; j < ARM_SMMU_PTE_CONT_ENTRIES; ++j) | |
2907320d MH |
1326 | pte_val(*(cont_start + j)) &= |
1327 | ~ARM_SMMU_PTE_CONT; | |
45ae7cff WD |
1328 | |
1329 | arm_smmu_flush_pgtable(smmu, cont_start, | |
1330 | sizeof(*pte) * | |
1331 | ARM_SMMU_PTE_CONT_ENTRIES); | |
1332 | } | |
1333 | ||
1334 | do { | |
1335 | *pte = pfn_pte(pfn, __pgprot(pteval)); | |
1336 | } while (pte++, pfn++, addr += PAGE_SIZE, --i); | |
1337 | } while (addr != end); | |
1338 | ||
1339 | arm_smmu_flush_pgtable(smmu, start, sizeof(*pte) * (pte - start)); | |
1340 | return 0; | |
1341 | } | |
1342 | ||
1343 | static int arm_smmu_alloc_init_pmd(struct arm_smmu_device *smmu, pud_t *pud, | |
1344 | unsigned long addr, unsigned long end, | |
b410aed9 | 1345 | phys_addr_t phys, int prot, int stage) |
45ae7cff WD |
1346 | { |
1347 | int ret; | |
1348 | pmd_t *pmd; | |
1349 | unsigned long next, pfn = __phys_to_pfn(phys); | |
1350 | ||
1351 | #ifndef __PAGETABLE_PMD_FOLDED | |
1352 | if (pud_none(*pud)) { | |
c9d09e27 | 1353 | pmd = (pmd_t *)get_zeroed_page(GFP_ATOMIC); |
45ae7cff WD |
1354 | if (!pmd) |
1355 | return -ENOMEM; | |
97a64420 | 1356 | |
6dd35f45 | 1357 | arm_smmu_flush_pgtable(smmu, pmd, PAGE_SIZE); |
97a64420 YZ |
1358 | pud_populate(NULL, pud, pmd); |
1359 | arm_smmu_flush_pgtable(smmu, pud, sizeof(*pud)); | |
1360 | ||
1361 | pmd += pmd_index(addr); | |
45ae7cff WD |
1362 | } else |
1363 | #endif | |
1364 | pmd = pmd_offset(pud, addr); | |
1365 | ||
1366 | do { | |
1367 | next = pmd_addr_end(addr, end); | |
aca1bc45 | 1368 | ret = arm_smmu_alloc_init_pte(smmu, pmd, addr, next, pfn, |
b410aed9 | 1369 | prot, stage); |
45ae7cff WD |
1370 | phys += next - addr; |
1371 | } while (pmd++, addr = next, addr < end); | |
1372 | ||
1373 | return ret; | |
1374 | } | |
1375 | ||
1376 | static int arm_smmu_alloc_init_pud(struct arm_smmu_device *smmu, pgd_t *pgd, | |
1377 | unsigned long addr, unsigned long end, | |
b410aed9 | 1378 | phys_addr_t phys, int prot, int stage) |
45ae7cff WD |
1379 | { |
1380 | int ret = 0; | |
1381 | pud_t *pud; | |
1382 | unsigned long next; | |
1383 | ||
1384 | #ifndef __PAGETABLE_PUD_FOLDED | |
1385 | if (pgd_none(*pgd)) { | |
c9d09e27 | 1386 | pud = (pud_t *)get_zeroed_page(GFP_ATOMIC); |
45ae7cff WD |
1387 | if (!pud) |
1388 | return -ENOMEM; | |
97a64420 | 1389 | |
6dd35f45 | 1390 | arm_smmu_flush_pgtable(smmu, pud, PAGE_SIZE); |
97a64420 YZ |
1391 | pgd_populate(NULL, pgd, pud); |
1392 | arm_smmu_flush_pgtable(smmu, pgd, sizeof(*pgd)); | |
1393 | ||
1394 | pud += pud_index(addr); | |
45ae7cff WD |
1395 | } else |
1396 | #endif | |
1397 | pud = pud_offset(pgd, addr); | |
1398 | ||
1399 | do { | |
1400 | next = pud_addr_end(addr, end); | |
1401 | ret = arm_smmu_alloc_init_pmd(smmu, pud, addr, next, phys, | |
b410aed9 | 1402 | prot, stage); |
45ae7cff WD |
1403 | phys += next - addr; |
1404 | } while (pud++, addr = next, addr < end); | |
1405 | ||
1406 | return ret; | |
1407 | } | |
1408 | ||
1409 | static int arm_smmu_handle_mapping(struct arm_smmu_domain *smmu_domain, | |
1410 | unsigned long iova, phys_addr_t paddr, | |
b410aed9 | 1411 | size_t size, int prot) |
45ae7cff WD |
1412 | { |
1413 | int ret, stage; | |
1414 | unsigned long end; | |
1415 | phys_addr_t input_mask, output_mask; | |
44680eed WD |
1416 | struct arm_smmu_device *smmu = smmu_domain->smmu; |
1417 | struct arm_smmu_cfg *cfg = &smmu_domain->cfg; | |
1418 | pgd_t *pgd = cfg->pgd; | |
b410aed9 | 1419 | unsigned long flags; |
45ae7cff | 1420 | |
44680eed | 1421 | if (cfg->cbar == CBAR_TYPE_S2_TRANS) { |
45ae7cff WD |
1422 | stage = 2; |
1423 | output_mask = (1ULL << smmu->s2_output_size) - 1; | |
1424 | } else { | |
1425 | stage = 1; | |
1426 | output_mask = (1ULL << smmu->s1_output_size) - 1; | |
1427 | } | |
1428 | ||
1429 | if (!pgd) | |
1430 | return -EINVAL; | |
1431 | ||
1432 | if (size & ~PAGE_MASK) | |
1433 | return -EINVAL; | |
1434 | ||
1435 | input_mask = (1ULL << smmu->input_size) - 1; | |
1436 | if ((phys_addr_t)iova & ~input_mask) | |
1437 | return -ERANGE; | |
1438 | ||
1439 | if (paddr & ~output_mask) | |
1440 | return -ERANGE; | |
1441 | ||
b410aed9 | 1442 | spin_lock_irqsave(&smmu_domain->lock, flags); |
45ae7cff WD |
1443 | pgd += pgd_index(iova); |
1444 | end = iova + size; | |
1445 | do { | |
1446 | unsigned long next = pgd_addr_end(iova, end); | |
1447 | ||
1448 | ret = arm_smmu_alloc_init_pud(smmu, pgd, iova, next, paddr, | |
b410aed9 | 1449 | prot, stage); |
45ae7cff WD |
1450 | if (ret) |
1451 | goto out_unlock; | |
1452 | ||
1453 | paddr += next - iova; | |
1454 | iova = next; | |
1455 | } while (pgd++, iova != end); | |
1456 | ||
1457 | out_unlock: | |
b410aed9 | 1458 | spin_unlock_irqrestore(&smmu_domain->lock, flags); |
45ae7cff | 1459 | |
45ae7cff WD |
1460 | return ret; |
1461 | } | |
1462 | ||
1463 | static int arm_smmu_map(struct iommu_domain *domain, unsigned long iova, | |
b410aed9 | 1464 | phys_addr_t paddr, size_t size, int prot) |
45ae7cff WD |
1465 | { |
1466 | struct arm_smmu_domain *smmu_domain = domain->priv; | |
45ae7cff | 1467 | |
5552ecdb | 1468 | if (!smmu_domain) |
45ae7cff WD |
1469 | return -ENODEV; |
1470 | ||
b410aed9 | 1471 | return arm_smmu_handle_mapping(smmu_domain, iova, paddr, size, prot); |
45ae7cff WD |
1472 | } |
1473 | ||
1474 | static size_t arm_smmu_unmap(struct iommu_domain *domain, unsigned long iova, | |
1475 | size_t size) | |
1476 | { | |
1477 | int ret; | |
1478 | struct arm_smmu_domain *smmu_domain = domain->priv; | |
45ae7cff WD |
1479 | |
1480 | ret = arm_smmu_handle_mapping(smmu_domain, iova, 0, size, 0); | |
44680eed | 1481 | arm_smmu_tlb_inv_context(smmu_domain); |
16c50dcf | 1482 | return ret ? 0 : size; |
45ae7cff WD |
1483 | } |
1484 | ||
1485 | static phys_addr_t arm_smmu_iova_to_phys(struct iommu_domain *domain, | |
1486 | dma_addr_t iova) | |
1487 | { | |
a44a9791 WD |
1488 | pgd_t *pgdp, pgd; |
1489 | pud_t pud; | |
1490 | pmd_t pmd; | |
1491 | pte_t pte; | |
45ae7cff | 1492 | struct arm_smmu_domain *smmu_domain = domain->priv; |
44680eed | 1493 | struct arm_smmu_cfg *cfg = &smmu_domain->cfg; |
45ae7cff | 1494 | |
44680eed | 1495 | pgdp = cfg->pgd; |
a44a9791 WD |
1496 | if (!pgdp) |
1497 | return 0; | |
45ae7cff | 1498 | |
a44a9791 WD |
1499 | pgd = *(pgdp + pgd_index(iova)); |
1500 | if (pgd_none(pgd)) | |
1501 | return 0; | |
45ae7cff | 1502 | |
a44a9791 WD |
1503 | pud = *pud_offset(&pgd, iova); |
1504 | if (pud_none(pud)) | |
1505 | return 0; | |
45ae7cff | 1506 | |
a44a9791 WD |
1507 | pmd = *pmd_offset(&pud, iova); |
1508 | if (pmd_none(pmd)) | |
1509 | return 0; | |
45ae7cff | 1510 | |
a44a9791 | 1511 | pte = *(pmd_page_vaddr(pmd) + pte_index(iova)); |
45ae7cff | 1512 | if (pte_none(pte)) |
a44a9791 | 1513 | return 0; |
45ae7cff | 1514 | |
a44a9791 | 1515 | return __pfn_to_phys(pte_pfn(pte)) | (iova & ~PAGE_MASK); |
45ae7cff WD |
1516 | } |
1517 | ||
1518 | static int arm_smmu_domain_has_cap(struct iommu_domain *domain, | |
1519 | unsigned long cap) | |
1520 | { | |
45ae7cff | 1521 | struct arm_smmu_domain *smmu_domain = domain->priv; |
d3bca166 WD |
1522 | struct arm_smmu_device *smmu = smmu_domain->smmu; |
1523 | u32 features = smmu ? smmu->features : 0; | |
d0948945 WD |
1524 | |
1525 | switch (cap) { | |
1526 | case IOMMU_CAP_CACHE_COHERENCY: | |
1527 | return features & ARM_SMMU_FEAT_COHERENT_WALK; | |
1528 | case IOMMU_CAP_INTR_REMAP: | |
1529 | return 1; /* MSIs are just memory writes */ | |
1530 | default: | |
1531 | return 0; | |
1532 | } | |
45ae7cff | 1533 | } |
45ae7cff | 1534 | |
a9a1b0b5 WD |
1535 | static int __arm_smmu_get_pci_sid(struct pci_dev *pdev, u16 alias, void *data) |
1536 | { | |
1537 | *((u16 *)data) = alias; | |
1538 | return 0; /* Continue walking */ | |
45ae7cff WD |
1539 | } |
1540 | ||
1541 | static int arm_smmu_add_device(struct device *dev) | |
1542 | { | |
a9a1b0b5 | 1543 | struct arm_smmu_device *smmu; |
5fc63a7c AM |
1544 | struct iommu_group *group; |
1545 | int ret; | |
1546 | ||
1547 | if (dev->archdata.iommu) { | |
1548 | dev_warn(dev, "IOMMU driver already assigned to device\n"); | |
1549 | return -EINVAL; | |
1550 | } | |
45ae7cff | 1551 | |
44680eed | 1552 | smmu = find_smmu_for_device(dev); |
a9a1b0b5 | 1553 | if (!smmu) |
45ae7cff WD |
1554 | return -ENODEV; |
1555 | ||
5fc63a7c AM |
1556 | group = iommu_group_alloc(); |
1557 | if (IS_ERR(group)) { | |
1558 | dev_err(dev, "Failed to allocate IOMMU group\n"); | |
1559 | return PTR_ERR(group); | |
1560 | } | |
1561 | ||
a9a1b0b5 WD |
1562 | if (dev_is_pci(dev)) { |
1563 | struct arm_smmu_master_cfg *cfg; | |
1564 | struct pci_dev *pdev = to_pci_dev(dev); | |
1565 | ||
1566 | cfg = kzalloc(sizeof(*cfg), GFP_KERNEL); | |
1567 | if (!cfg) { | |
1568 | ret = -ENOMEM; | |
1569 | goto out_put_group; | |
1570 | } | |
1571 | ||
1572 | cfg->num_streamids = 1; | |
1573 | /* | |
1574 | * Assume Stream ID == Requester ID for now. | |
1575 | * We need a way to describe the ID mappings in FDT. | |
1576 | */ | |
1577 | pci_for_each_dma_alias(pdev, __arm_smmu_get_pci_sid, | |
1578 | &cfg->streamids[0]); | |
1579 | dev->archdata.iommu = cfg; | |
1580 | } else { | |
1581 | dev->archdata.iommu = smmu; | |
1582 | } | |
1583 | ||
5fc63a7c | 1584 | ret = iommu_group_add_device(group, dev); |
5fc63a7c | 1585 | |
a9a1b0b5 WD |
1586 | out_put_group: |
1587 | iommu_group_put(group); | |
5fc63a7c | 1588 | return ret; |
45ae7cff WD |
1589 | } |
1590 | ||
1591 | static void arm_smmu_remove_device(struct device *dev) | |
1592 | { | |
a9a1b0b5 WD |
1593 | if (dev_is_pci(dev)) |
1594 | kfree(dev->archdata.iommu); | |
1595 | ||
45ae7cff | 1596 | dev->archdata.iommu = NULL; |
5fc63a7c | 1597 | iommu_group_remove_device(dev); |
45ae7cff WD |
1598 | } |
1599 | ||
b22f6434 | 1600 | static const struct iommu_ops arm_smmu_ops = { |
45ae7cff WD |
1601 | .domain_init = arm_smmu_domain_init, |
1602 | .domain_destroy = arm_smmu_domain_destroy, | |
1603 | .attach_dev = arm_smmu_attach_dev, | |
1604 | .detach_dev = arm_smmu_detach_dev, | |
1605 | .map = arm_smmu_map, | |
1606 | .unmap = arm_smmu_unmap, | |
1607 | .iova_to_phys = arm_smmu_iova_to_phys, | |
1608 | .domain_has_cap = arm_smmu_domain_has_cap, | |
1609 | .add_device = arm_smmu_add_device, | |
1610 | .remove_device = arm_smmu_remove_device, | |
1611 | .pgsize_bitmap = (SECTION_SIZE | | |
1612 | ARM_SMMU_PTE_CONT_SIZE | | |
1613 | PAGE_SIZE), | |
1614 | }; | |
1615 | ||
1616 | static void arm_smmu_device_reset(struct arm_smmu_device *smmu) | |
1617 | { | |
1618 | void __iomem *gr0_base = ARM_SMMU_GR0(smmu); | |
659db6f6 | 1619 | void __iomem *cb_base; |
45ae7cff | 1620 | int i = 0; |
659db6f6 AH |
1621 | u32 reg; |
1622 | ||
3a5df8ff AH |
1623 | /* clear global FSR */ |
1624 | reg = readl_relaxed(ARM_SMMU_GR0_NS(smmu) + ARM_SMMU_GR0_sGFSR); | |
1625 | writel(reg, ARM_SMMU_GR0_NS(smmu) + ARM_SMMU_GR0_sGFSR); | |
45ae7cff WD |
1626 | |
1627 | /* Mark all SMRn as invalid and all S2CRn as bypass */ | |
1628 | for (i = 0; i < smmu->num_mapping_groups; ++i) { | |
1629 | writel_relaxed(~SMR_VALID, gr0_base + ARM_SMMU_GR0_SMR(i)); | |
2907320d MH |
1630 | writel_relaxed(S2CR_TYPE_BYPASS, |
1631 | gr0_base + ARM_SMMU_GR0_S2CR(i)); | |
45ae7cff WD |
1632 | } |
1633 | ||
659db6f6 AH |
1634 | /* Make sure all context banks are disabled and clear CB_FSR */ |
1635 | for (i = 0; i < smmu->num_context_banks; ++i) { | |
1636 | cb_base = ARM_SMMU_CB_BASE(smmu) + ARM_SMMU_CB(smmu, i); | |
1637 | writel_relaxed(0, cb_base + ARM_SMMU_CB_SCTLR); | |
1638 | writel_relaxed(FSR_FAULT, cb_base + ARM_SMMU_CB_FSR); | |
1639 | } | |
1463fe44 | 1640 | |
45ae7cff WD |
1641 | /* Invalidate the TLB, just in case */ |
1642 | writel_relaxed(0, gr0_base + ARM_SMMU_GR0_STLBIALL); | |
1643 | writel_relaxed(0, gr0_base + ARM_SMMU_GR0_TLBIALLH); | |
1644 | writel_relaxed(0, gr0_base + ARM_SMMU_GR0_TLBIALLNSNH); | |
1645 | ||
3a5df8ff | 1646 | reg = readl_relaxed(ARM_SMMU_GR0_NS(smmu) + ARM_SMMU_GR0_sCR0); |
659db6f6 | 1647 | |
45ae7cff | 1648 | /* Enable fault reporting */ |
659db6f6 | 1649 | reg |= (sCR0_GFRE | sCR0_GFIE | sCR0_GCFGFRE | sCR0_GCFGFIE); |
45ae7cff WD |
1650 | |
1651 | /* Disable TLB broadcasting. */ | |
659db6f6 | 1652 | reg |= (sCR0_VMIDPNE | sCR0_PTM); |
45ae7cff WD |
1653 | |
1654 | /* Enable client access, but bypass when no mapping is found */ | |
659db6f6 | 1655 | reg &= ~(sCR0_CLIENTPD | sCR0_USFCFG); |
45ae7cff WD |
1656 | |
1657 | /* Disable forced broadcasting */ | |
659db6f6 | 1658 | reg &= ~sCR0_FB; |
45ae7cff WD |
1659 | |
1660 | /* Don't upgrade barriers */ | |
659db6f6 | 1661 | reg &= ~(sCR0_BSU_MASK << sCR0_BSU_SHIFT); |
45ae7cff WD |
1662 | |
1663 | /* Push the button */ | |
1664 | arm_smmu_tlb_sync(smmu); | |
3a5df8ff | 1665 | writel(reg, ARM_SMMU_GR0_NS(smmu) + ARM_SMMU_GR0_sCR0); |
45ae7cff WD |
1666 | } |
1667 | ||
1668 | static int arm_smmu_id_size_to_bits(int size) | |
1669 | { | |
1670 | switch (size) { | |
1671 | case 0: | |
1672 | return 32; | |
1673 | case 1: | |
1674 | return 36; | |
1675 | case 2: | |
1676 | return 40; | |
1677 | case 3: | |
1678 | return 42; | |
1679 | case 4: | |
1680 | return 44; | |
1681 | case 5: | |
1682 | default: | |
1683 | return 48; | |
1684 | } | |
1685 | } | |
1686 | ||
1687 | static int arm_smmu_device_cfg_probe(struct arm_smmu_device *smmu) | |
1688 | { | |
1689 | unsigned long size; | |
1690 | void __iomem *gr0_base = ARM_SMMU_GR0(smmu); | |
1691 | u32 id; | |
1692 | ||
1693 | dev_notice(smmu->dev, "probing hardware configuration...\n"); | |
1694 | ||
1695 | /* Primecell ID */ | |
1696 | id = readl_relaxed(gr0_base + ARM_SMMU_GR0_PIDR2); | |
1697 | smmu->version = ((id >> PIDR2_ARCH_SHIFT) & PIDR2_ARCH_MASK) + 1; | |
1698 | dev_notice(smmu->dev, "SMMUv%d with:\n", smmu->version); | |
1699 | ||
1700 | /* ID0 */ | |
1701 | id = readl_relaxed(gr0_base + ARM_SMMU_GR0_ID0); | |
1702 | #ifndef CONFIG_64BIT | |
1703 | if (((id >> ID0_PTFS_SHIFT) & ID0_PTFS_MASK) == ID0_PTFS_V8_ONLY) { | |
1704 | dev_err(smmu->dev, "\tno v7 descriptor support!\n"); | |
1705 | return -ENODEV; | |
1706 | } | |
1707 | #endif | |
1708 | if (id & ID0_S1TS) { | |
1709 | smmu->features |= ARM_SMMU_FEAT_TRANS_S1; | |
1710 | dev_notice(smmu->dev, "\tstage 1 translation\n"); | |
1711 | } | |
1712 | ||
1713 | if (id & ID0_S2TS) { | |
1714 | smmu->features |= ARM_SMMU_FEAT_TRANS_S2; | |
1715 | dev_notice(smmu->dev, "\tstage 2 translation\n"); | |
1716 | } | |
1717 | ||
1718 | if (id & ID0_NTS) { | |
1719 | smmu->features |= ARM_SMMU_FEAT_TRANS_NESTED; | |
1720 | dev_notice(smmu->dev, "\tnested translation\n"); | |
1721 | } | |
1722 | ||
1723 | if (!(smmu->features & | |
1724 | (ARM_SMMU_FEAT_TRANS_S1 | ARM_SMMU_FEAT_TRANS_S2 | | |
1725 | ARM_SMMU_FEAT_TRANS_NESTED))) { | |
1726 | dev_err(smmu->dev, "\tno translation support!\n"); | |
1727 | return -ENODEV; | |
1728 | } | |
1729 | ||
1730 | if (id & ID0_CTTW) { | |
1731 | smmu->features |= ARM_SMMU_FEAT_COHERENT_WALK; | |
1732 | dev_notice(smmu->dev, "\tcoherent table walk\n"); | |
1733 | } | |
1734 | ||
1735 | if (id & ID0_SMS) { | |
1736 | u32 smr, sid, mask; | |
1737 | ||
1738 | smmu->features |= ARM_SMMU_FEAT_STREAM_MATCH; | |
1739 | smmu->num_mapping_groups = (id >> ID0_NUMSMRG_SHIFT) & | |
1740 | ID0_NUMSMRG_MASK; | |
1741 | if (smmu->num_mapping_groups == 0) { | |
1742 | dev_err(smmu->dev, | |
1743 | "stream-matching supported, but no SMRs present!\n"); | |
1744 | return -ENODEV; | |
1745 | } | |
1746 | ||
1747 | smr = SMR_MASK_MASK << SMR_MASK_SHIFT; | |
1748 | smr |= (SMR_ID_MASK << SMR_ID_SHIFT); | |
1749 | writel_relaxed(smr, gr0_base + ARM_SMMU_GR0_SMR(0)); | |
1750 | smr = readl_relaxed(gr0_base + ARM_SMMU_GR0_SMR(0)); | |
1751 | ||
1752 | mask = (smr >> SMR_MASK_SHIFT) & SMR_MASK_MASK; | |
1753 | sid = (smr >> SMR_ID_SHIFT) & SMR_ID_MASK; | |
1754 | if ((mask & sid) != sid) { | |
1755 | dev_err(smmu->dev, | |
1756 | "SMR mask bits (0x%x) insufficient for ID field (0x%x)\n", | |
1757 | mask, sid); | |
1758 | return -ENODEV; | |
1759 | } | |
1760 | ||
1761 | dev_notice(smmu->dev, | |
1762 | "\tstream matching with %u register groups, mask 0x%x", | |
1763 | smmu->num_mapping_groups, mask); | |
1764 | } | |
1765 | ||
1766 | /* ID1 */ | |
1767 | id = readl_relaxed(gr0_base + ARM_SMMU_GR0_ID1); | |
1768 | smmu->pagesize = (id & ID1_PAGESIZE) ? SZ_64K : SZ_4K; | |
1769 | ||
c55af7f7 | 1770 | /* Check for size mismatch of SMMU address space from mapped region */ |
2907320d MH |
1771 | size = 1 << |
1772 | (((id >> ID1_NUMPAGENDXB_SHIFT) & ID1_NUMPAGENDXB_MASK) + 1); | |
45ae7cff | 1773 | size *= (smmu->pagesize << 1); |
c55af7f7 | 1774 | if (smmu->size != size) |
2907320d MH |
1775 | dev_warn(smmu->dev, |
1776 | "SMMU address space size (0x%lx) differs from mapped region size (0x%lx)!\n", | |
1777 | size, smmu->size); | |
45ae7cff WD |
1778 | |
1779 | smmu->num_s2_context_banks = (id >> ID1_NUMS2CB_SHIFT) & | |
1780 | ID1_NUMS2CB_MASK; | |
1781 | smmu->num_context_banks = (id >> ID1_NUMCB_SHIFT) & ID1_NUMCB_MASK; | |
1782 | if (smmu->num_s2_context_banks > smmu->num_context_banks) { | |
1783 | dev_err(smmu->dev, "impossible number of S2 context banks!\n"); | |
1784 | return -ENODEV; | |
1785 | } | |
1786 | dev_notice(smmu->dev, "\t%u context banks (%u stage-2 only)\n", | |
1787 | smmu->num_context_banks, smmu->num_s2_context_banks); | |
1788 | ||
1789 | /* ID2 */ | |
1790 | id = readl_relaxed(gr0_base + ARM_SMMU_GR0_ID2); | |
1791 | size = arm_smmu_id_size_to_bits((id >> ID2_IAS_SHIFT) & ID2_IAS_MASK); | |
1792 | ||
1793 | /* | |
1794 | * Stage-1 output limited by stage-2 input size due to pgd | |
1795 | * allocation (PTRS_PER_PGD). | |
1796 | */ | |
1797 | #ifdef CONFIG_64BIT | |
2907320d | 1798 | smmu->s1_output_size = min_t(unsigned long, VA_BITS, size); |
45ae7cff WD |
1799 | #else |
1800 | smmu->s1_output_size = min(32UL, size); | |
1801 | #endif | |
1802 | ||
1803 | /* The stage-2 output mask is also applied for bypass */ | |
1804 | size = arm_smmu_id_size_to_bits((id >> ID2_OAS_SHIFT) & ID2_OAS_MASK); | |
2907320d | 1805 | smmu->s2_output_size = min_t(unsigned long, PHYS_MASK_SHIFT, size); |
45ae7cff WD |
1806 | |
1807 | if (smmu->version == 1) { | |
1808 | smmu->input_size = 32; | |
1809 | } else { | |
1810 | #ifdef CONFIG_64BIT | |
1811 | size = (id >> ID2_UBS_SHIFT) & ID2_UBS_MASK; | |
06f983dd | 1812 | size = min(VA_BITS, arm_smmu_id_size_to_bits(size)); |
45ae7cff WD |
1813 | #else |
1814 | size = 32; | |
1815 | #endif | |
1816 | smmu->input_size = size; | |
1817 | ||
1818 | if ((PAGE_SIZE == SZ_4K && !(id & ID2_PTFS_4K)) || | |
1819 | (PAGE_SIZE == SZ_64K && !(id & ID2_PTFS_64K)) || | |
1820 | (PAGE_SIZE != SZ_4K && PAGE_SIZE != SZ_64K)) { | |
1821 | dev_err(smmu->dev, "CPU page size 0x%lx unsupported\n", | |
1822 | PAGE_SIZE); | |
1823 | return -ENODEV; | |
1824 | } | |
1825 | } | |
1826 | ||
1827 | dev_notice(smmu->dev, | |
1828 | "\t%lu-bit VA, %lu-bit IPA, %lu-bit PA\n", | |
2907320d MH |
1829 | smmu->input_size, smmu->s1_output_size, |
1830 | smmu->s2_output_size); | |
45ae7cff WD |
1831 | return 0; |
1832 | } | |
1833 | ||
1834 | static int arm_smmu_device_dt_probe(struct platform_device *pdev) | |
1835 | { | |
1836 | struct resource *res; | |
1837 | struct arm_smmu_device *smmu; | |
45ae7cff WD |
1838 | struct device *dev = &pdev->dev; |
1839 | struct rb_node *node; | |
1840 | struct of_phandle_args masterspec; | |
1841 | int num_irqs, i, err; | |
1842 | ||
1843 | smmu = devm_kzalloc(dev, sizeof(*smmu), GFP_KERNEL); | |
1844 | if (!smmu) { | |
1845 | dev_err(dev, "failed to allocate arm_smmu_device\n"); | |
1846 | return -ENOMEM; | |
1847 | } | |
1848 | smmu->dev = dev; | |
1849 | ||
1850 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
8a7f4312 JL |
1851 | smmu->base = devm_ioremap_resource(dev, res); |
1852 | if (IS_ERR(smmu->base)) | |
1853 | return PTR_ERR(smmu->base); | |
45ae7cff | 1854 | smmu->size = resource_size(res); |
45ae7cff WD |
1855 | |
1856 | if (of_property_read_u32(dev->of_node, "#global-interrupts", | |
1857 | &smmu->num_global_irqs)) { | |
1858 | dev_err(dev, "missing #global-interrupts property\n"); | |
1859 | return -ENODEV; | |
1860 | } | |
1861 | ||
1862 | num_irqs = 0; | |
1863 | while ((res = platform_get_resource(pdev, IORESOURCE_IRQ, num_irqs))) { | |
1864 | num_irqs++; | |
1865 | if (num_irqs > smmu->num_global_irqs) | |
1866 | smmu->num_context_irqs++; | |
1867 | } | |
1868 | ||
44a08de2 AH |
1869 | if (!smmu->num_context_irqs) { |
1870 | dev_err(dev, "found %d interrupts but expected at least %d\n", | |
1871 | num_irqs, smmu->num_global_irqs + 1); | |
1872 | return -ENODEV; | |
45ae7cff | 1873 | } |
45ae7cff WD |
1874 | |
1875 | smmu->irqs = devm_kzalloc(dev, sizeof(*smmu->irqs) * num_irqs, | |
1876 | GFP_KERNEL); | |
1877 | if (!smmu->irqs) { | |
1878 | dev_err(dev, "failed to allocate %d irqs\n", num_irqs); | |
1879 | return -ENOMEM; | |
1880 | } | |
1881 | ||
1882 | for (i = 0; i < num_irqs; ++i) { | |
1883 | int irq = platform_get_irq(pdev, i); | |
2907320d | 1884 | |
45ae7cff WD |
1885 | if (irq < 0) { |
1886 | dev_err(dev, "failed to get irq index %d\n", i); | |
1887 | return -ENODEV; | |
1888 | } | |
1889 | smmu->irqs[i] = irq; | |
1890 | } | |
1891 | ||
1892 | i = 0; | |
1893 | smmu->masters = RB_ROOT; | |
1894 | while (!of_parse_phandle_with_args(dev->of_node, "mmu-masters", | |
1895 | "#stream-id-cells", i, | |
1896 | &masterspec)) { | |
1897 | err = register_smmu_master(smmu, dev, &masterspec); | |
1898 | if (err) { | |
1899 | dev_err(dev, "failed to add master %s\n", | |
1900 | masterspec.np->name); | |
1901 | goto out_put_masters; | |
1902 | } | |
1903 | ||
1904 | i++; | |
1905 | } | |
1906 | dev_notice(dev, "registered %d master devices\n", i); | |
1907 | ||
45ae7cff WD |
1908 | err = arm_smmu_device_cfg_probe(smmu); |
1909 | if (err) | |
44680eed | 1910 | goto out_put_masters; |
45ae7cff | 1911 | |
3a5df8ff AH |
1912 | parse_driver_options(smmu); |
1913 | ||
45ae7cff WD |
1914 | if (smmu->version > 1 && |
1915 | smmu->num_context_banks != smmu->num_context_irqs) { | |
1916 | dev_err(dev, | |
1917 | "found only %d context interrupt(s) but %d required\n", | |
1918 | smmu->num_context_irqs, smmu->num_context_banks); | |
89a23cde | 1919 | err = -ENODEV; |
44680eed | 1920 | goto out_put_masters; |
45ae7cff WD |
1921 | } |
1922 | ||
45ae7cff WD |
1923 | for (i = 0; i < smmu->num_global_irqs; ++i) { |
1924 | err = request_irq(smmu->irqs[i], | |
1925 | arm_smmu_global_fault, | |
1926 | IRQF_SHARED, | |
1927 | "arm-smmu global fault", | |
1928 | smmu); | |
1929 | if (err) { | |
1930 | dev_err(dev, "failed to request global IRQ %d (%u)\n", | |
1931 | i, smmu->irqs[i]); | |
1932 | goto out_free_irqs; | |
1933 | } | |
1934 | } | |
1935 | ||
1936 | INIT_LIST_HEAD(&smmu->list); | |
1937 | spin_lock(&arm_smmu_devices_lock); | |
1938 | list_add(&smmu->list, &arm_smmu_devices); | |
1939 | spin_unlock(&arm_smmu_devices_lock); | |
fd90cecb WD |
1940 | |
1941 | arm_smmu_device_reset(smmu); | |
45ae7cff WD |
1942 | return 0; |
1943 | ||
1944 | out_free_irqs: | |
1945 | while (i--) | |
1946 | free_irq(smmu->irqs[i], smmu); | |
1947 | ||
45ae7cff WD |
1948 | out_put_masters: |
1949 | for (node = rb_first(&smmu->masters); node; node = rb_next(node)) { | |
2907320d MH |
1950 | struct arm_smmu_master *master |
1951 | = container_of(node, struct arm_smmu_master, node); | |
45ae7cff WD |
1952 | of_node_put(master->of_node); |
1953 | } | |
1954 | ||
1955 | return err; | |
1956 | } | |
1957 | ||
1958 | static int arm_smmu_device_remove(struct platform_device *pdev) | |
1959 | { | |
1960 | int i; | |
1961 | struct device *dev = &pdev->dev; | |
1962 | struct arm_smmu_device *curr, *smmu = NULL; | |
1963 | struct rb_node *node; | |
1964 | ||
1965 | spin_lock(&arm_smmu_devices_lock); | |
1966 | list_for_each_entry(curr, &arm_smmu_devices, list) { | |
1967 | if (curr->dev == dev) { | |
1968 | smmu = curr; | |
1969 | list_del(&smmu->list); | |
1970 | break; | |
1971 | } | |
1972 | } | |
1973 | spin_unlock(&arm_smmu_devices_lock); | |
1974 | ||
1975 | if (!smmu) | |
1976 | return -ENODEV; | |
1977 | ||
45ae7cff | 1978 | for (node = rb_first(&smmu->masters); node; node = rb_next(node)) { |
2907320d MH |
1979 | struct arm_smmu_master *master |
1980 | = container_of(node, struct arm_smmu_master, node); | |
45ae7cff WD |
1981 | of_node_put(master->of_node); |
1982 | } | |
1983 | ||
ecfadb6e | 1984 | if (!bitmap_empty(smmu->context_map, ARM_SMMU_MAX_CBS)) |
45ae7cff WD |
1985 | dev_err(dev, "removing device with active domains!\n"); |
1986 | ||
1987 | for (i = 0; i < smmu->num_global_irqs; ++i) | |
1988 | free_irq(smmu->irqs[i], smmu); | |
1989 | ||
1990 | /* Turn the thing off */ | |
2907320d | 1991 | writel(sCR0_CLIENTPD, ARM_SMMU_GR0_NS(smmu) + ARM_SMMU_GR0_sCR0); |
45ae7cff WD |
1992 | return 0; |
1993 | } | |
1994 | ||
1995 | #ifdef CONFIG_OF | |
1996 | static struct of_device_id arm_smmu_of_match[] = { | |
1997 | { .compatible = "arm,smmu-v1", }, | |
1998 | { .compatible = "arm,smmu-v2", }, | |
1999 | { .compatible = "arm,mmu-400", }, | |
2000 | { .compatible = "arm,mmu-500", }, | |
2001 | { }, | |
2002 | }; | |
2003 | MODULE_DEVICE_TABLE(of, arm_smmu_of_match); | |
2004 | #endif | |
2005 | ||
2006 | static struct platform_driver arm_smmu_driver = { | |
2007 | .driver = { | |
2008 | .owner = THIS_MODULE, | |
2009 | .name = "arm-smmu", | |
2010 | .of_match_table = of_match_ptr(arm_smmu_of_match), | |
2011 | }, | |
2012 | .probe = arm_smmu_device_dt_probe, | |
2013 | .remove = arm_smmu_device_remove, | |
2014 | }; | |
2015 | ||
2016 | static int __init arm_smmu_init(void) | |
2017 | { | |
2018 | int ret; | |
2019 | ||
2020 | ret = platform_driver_register(&arm_smmu_driver); | |
2021 | if (ret) | |
2022 | return ret; | |
2023 | ||
2024 | /* Oh, for a proper bus abstraction */ | |
6614ee77 | 2025 | if (!iommu_present(&platform_bus_type)) |
45ae7cff WD |
2026 | bus_set_iommu(&platform_bus_type, &arm_smmu_ops); |
2027 | ||
d123cf82 | 2028 | #ifdef CONFIG_ARM_AMBA |
6614ee77 | 2029 | if (!iommu_present(&amba_bustype)) |
45ae7cff | 2030 | bus_set_iommu(&amba_bustype, &arm_smmu_ops); |
d123cf82 | 2031 | #endif |
45ae7cff | 2032 | |
a9a1b0b5 WD |
2033 | #ifdef CONFIG_PCI |
2034 | if (!iommu_present(&pci_bus_type)) | |
2035 | bus_set_iommu(&pci_bus_type, &arm_smmu_ops); | |
2036 | #endif | |
2037 | ||
45ae7cff WD |
2038 | return 0; |
2039 | } | |
2040 | ||
2041 | static void __exit arm_smmu_exit(void) | |
2042 | { | |
2043 | return platform_driver_unregister(&arm_smmu_driver); | |
2044 | } | |
2045 | ||
b1950b27 | 2046 | subsys_initcall(arm_smmu_init); |
45ae7cff WD |
2047 | module_exit(arm_smmu_exit); |
2048 | ||
2049 | MODULE_DESCRIPTION("IOMMU API for ARM architected SMMU implementations"); | |
2050 | MODULE_AUTHOR("Will Deacon <will.deacon@arm.com>"); | |
2051 | MODULE_LICENSE("GPL v2"); |