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Commit | Line | Data |
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b2441318 | 1 | // SPDX-License-Identifier: GPL-2.0 |
9f10e5bf JR |
2 | |
3 | #define pr_fmt(fmt) "DMAR-IR: " fmt | |
4 | ||
5aeecaf4 | 5 | #include <linux/interrupt.h> |
ad3ad3f6 | 6 | #include <linux/dmar.h> |
2ae21010 | 7 | #include <linux/spinlock.h> |
5a0e3ad6 | 8 | #include <linux/slab.h> |
2ae21010 | 9 | #include <linux/jiffies.h> |
20f3097b | 10 | #include <linux/hpet.h> |
2ae21010 | 11 | #include <linux/pci.h> |
b6fcb33a | 12 | #include <linux/irq.h> |
8b48463f LZ |
13 | #include <linux/intel-iommu.h> |
14 | #include <linux/acpi.h> | |
b106ee63 | 15 | #include <linux/irqdomain.h> |
af3b358e | 16 | #include <linux/crash_dump.h> |
ad3ad3f6 | 17 | #include <asm/io_apic.h> |
17483a1f | 18 | #include <asm/smp.h> |
6d652ea1 | 19 | #include <asm/cpu.h> |
8a8f422d | 20 | #include <asm/irq_remapping.h> |
f007e99c | 21 | #include <asm/pci-direct.h> |
5e2b930b | 22 | #include <asm/msidef.h> |
ad3ad3f6 | 23 | |
8a8f422d | 24 | #include "irq_remapping.h" |
736baef4 | 25 | |
2705a3d2 FW |
26 | enum irq_mode { |
27 | IRQ_REMAPPING, | |
28 | IRQ_POSTING, | |
29 | }; | |
30 | ||
eef93fdb JR |
31 | struct ioapic_scope { |
32 | struct intel_iommu *iommu; | |
33 | unsigned int id; | |
34 | unsigned int bus; /* PCI bus number */ | |
35 | unsigned int devfn; /* PCI devfn number */ | |
36 | }; | |
37 | ||
38 | struct hpet_scope { | |
39 | struct intel_iommu *iommu; | |
40 | u8 id; | |
41 | unsigned int bus; | |
42 | unsigned int devfn; | |
43 | }; | |
44 | ||
099c5c03 JL |
45 | struct irq_2_iommu { |
46 | struct intel_iommu *iommu; | |
47 | u16 irte_index; | |
48 | u16 sub_handle; | |
49 | u8 irte_mask; | |
2705a3d2 | 50 | enum irq_mode mode; |
099c5c03 JL |
51 | }; |
52 | ||
b106ee63 JL |
53 | struct intel_ir_data { |
54 | struct irq_2_iommu irq_2_iommu; | |
55 | struct irte irte_entry; | |
56 | union { | |
57 | struct msi_msg msi_entry; | |
58 | }; | |
59 | }; | |
60 | ||
eef93fdb | 61 | #define IR_X2APIC_MODE(mode) (mode ? (1 << 11) : 0) |
13d09b66 | 62 | #define IRTE_DEST(dest) ((eim_mode) ? dest : dest << 8) |
eef93fdb | 63 | |
13d09b66 | 64 | static int __read_mostly eim_mode; |
ad3ad3f6 | 65 | static struct ioapic_scope ir_ioapic[MAX_IO_APICS]; |
20f3097b | 66 | static struct hpet_scope ir_hpet[MAX_HPET_TBS]; |
d1423d56 | 67 | |
3a5670e8 JL |
68 | /* |
69 | * Lock ordering: | |
70 | * ->dmar_global_lock | |
71 | * ->irq_2_ir_lock | |
72 | * ->qi->q_lock | |
73 | * ->iommu->register_lock | |
74 | * Note: | |
75 | * intel_irq_remap_ops.{supported,prepare,enable,disable,reenable} are called | |
76 | * in single-threaded environment with interrupt disabled, so no need to tabke | |
77 | * the dmar_global_lock. | |
78 | */ | |
96f8e98b | 79 | static DEFINE_RAW_SPINLOCK(irq_2_ir_lock); |
71bb620d | 80 | static const struct irq_domain_ops intel_ir_domain_ops; |
d585d060 | 81 | |
af3b358e | 82 | static void iommu_disable_irq_remapping(struct intel_iommu *iommu); |
694835dc JL |
83 | static int __init parse_ioapics_under_ir(void); |
84 | ||
af3b358e JR |
85 | static bool ir_pre_enabled(struct intel_iommu *iommu) |
86 | { | |
87 | return (iommu->flags & VTD_FLAG_IRQ_REMAP_PRE_ENABLED); | |
88 | } | |
89 | ||
90 | static void clear_ir_pre_enabled(struct intel_iommu *iommu) | |
91 | { | |
92 | iommu->flags &= ~VTD_FLAG_IRQ_REMAP_PRE_ENABLED; | |
93 | } | |
94 | ||
95 | static void init_ir_status(struct intel_iommu *iommu) | |
96 | { | |
97 | u32 gsts; | |
98 | ||
99 | gsts = readl(iommu->reg + DMAR_GSTS_REG); | |
100 | if (gsts & DMA_GSTS_IRES) | |
101 | iommu->flags |= VTD_FLAG_IRQ_REMAP_PRE_ENABLED; | |
102 | } | |
103 | ||
8dedf4cf JL |
104 | static int alloc_irte(struct intel_iommu *iommu, int irq, |
105 | struct irq_2_iommu *irq_iommu, u16 count) | |
b6fcb33a SS |
106 | { |
107 | struct ir_table *table = iommu->ir_table; | |
b6fcb33a | 108 | unsigned int mask = 0; |
4c5502b1 | 109 | unsigned long flags; |
9f4c7448 | 110 | int index; |
b6fcb33a | 111 | |
d585d060 | 112 | if (!count || !irq_iommu) |
e420dfb4 | 113 | return -1; |
e420dfb4 | 114 | |
b6fcb33a SS |
115 | if (count > 1) { |
116 | count = __roundup_pow_of_two(count); | |
117 | mask = ilog2(count); | |
118 | } | |
119 | ||
120 | if (mask > ecap_max_handle_mask(iommu->ecap)) { | |
9f10e5bf | 121 | pr_err("Requested mask %x exceeds the max invalidation handle" |
b6fcb33a SS |
122 | " mask value %Lx\n", mask, |
123 | ecap_max_handle_mask(iommu->ecap)); | |
124 | return -1; | |
125 | } | |
126 | ||
96f8e98b | 127 | raw_spin_lock_irqsave(&irq_2_ir_lock, flags); |
360eb3c5 JL |
128 | index = bitmap_find_free_region(table->bitmap, |
129 | INTR_REMAP_TABLE_ENTRIES, mask); | |
130 | if (index < 0) { | |
131 | pr_warn("IR%d: can't allocate an IRTE\n", iommu->seq_id); | |
132 | } else { | |
360eb3c5 JL |
133 | irq_iommu->iommu = iommu; |
134 | irq_iommu->irte_index = index; | |
135 | irq_iommu->sub_handle = 0; | |
136 | irq_iommu->irte_mask = mask; | |
2705a3d2 | 137 | irq_iommu->mode = IRQ_REMAPPING; |
360eb3c5 | 138 | } |
96f8e98b | 139 | raw_spin_unlock_irqrestore(&irq_2_ir_lock, flags); |
b6fcb33a SS |
140 | |
141 | return index; | |
142 | } | |
143 | ||
704126ad | 144 | static int qi_flush_iec(struct intel_iommu *iommu, int index, int mask) |
b6fcb33a SS |
145 | { |
146 | struct qi_desc desc; | |
147 | ||
148 | desc.low = QI_IEC_IIDEX(index) | QI_IEC_TYPE | QI_IEC_IM(mask) | |
149 | | QI_IEC_SELECTIVE; | |
150 | desc.high = 0; | |
151 | ||
704126ad | 152 | return qi_submit_sync(&desc, iommu); |
b6fcb33a SS |
153 | } |
154 | ||
8dedf4cf JL |
155 | static int modify_irte(struct irq_2_iommu *irq_iommu, |
156 | struct irte *irte_modified) | |
b6fcb33a | 157 | { |
b6fcb33a | 158 | struct intel_iommu *iommu; |
4c5502b1 | 159 | unsigned long flags; |
d585d060 TG |
160 | struct irte *irte; |
161 | int rc, index; | |
b6fcb33a | 162 | |
d585d060 | 163 | if (!irq_iommu) |
b6fcb33a | 164 | return -1; |
d585d060 | 165 | |
96f8e98b | 166 | raw_spin_lock_irqsave(&irq_2_ir_lock, flags); |
b6fcb33a | 167 | |
e420dfb4 | 168 | iommu = irq_iommu->iommu; |
b6fcb33a | 169 | |
e420dfb4 | 170 | index = irq_iommu->irte_index + irq_iommu->sub_handle; |
b6fcb33a SS |
171 | irte = &iommu->ir_table->base[index]; |
172 | ||
344cb4e0 FW |
173 | #if defined(CONFIG_HAVE_CMPXCHG_DOUBLE) |
174 | if ((irte->pst == 1) || (irte_modified->pst == 1)) { | |
175 | bool ret; | |
176 | ||
177 | ret = cmpxchg_double(&irte->low, &irte->high, | |
178 | irte->low, irte->high, | |
179 | irte_modified->low, irte_modified->high); | |
180 | /* | |
181 | * We use cmpxchg16 to atomically update the 128-bit IRTE, | |
182 | * and it cannot be updated by the hardware or other processors | |
183 | * behind us, so the return value of cmpxchg16 should be the | |
184 | * same as the old value. | |
185 | */ | |
186 | WARN_ON(!ret); | |
187 | } else | |
188 | #endif | |
189 | { | |
190 | set_64bit(&irte->low, irte_modified->low); | |
191 | set_64bit(&irte->high, irte_modified->high); | |
192 | } | |
b6fcb33a SS |
193 | __iommu_flush_cache(iommu, irte, sizeof(*irte)); |
194 | ||
704126ad | 195 | rc = qi_flush_iec(iommu, index, 0); |
2705a3d2 FW |
196 | |
197 | /* Update iommu mode according to the IRTE mode */ | |
198 | irq_iommu->mode = irte->pst ? IRQ_POSTING : IRQ_REMAPPING; | |
96f8e98b | 199 | raw_spin_unlock_irqrestore(&irq_2_ir_lock, flags); |
704126ad YZ |
200 | |
201 | return rc; | |
b6fcb33a SS |
202 | } |
203 | ||
263b5e86 | 204 | static struct intel_iommu *map_hpet_to_ir(u8 hpet_id) |
20f3097b SS |
205 | { |
206 | int i; | |
207 | ||
208 | for (i = 0; i < MAX_HPET_TBS; i++) | |
a7a3dad9 | 209 | if (ir_hpet[i].id == hpet_id && ir_hpet[i].iommu) |
20f3097b SS |
210 | return ir_hpet[i].iommu; |
211 | return NULL; | |
212 | } | |
213 | ||
263b5e86 | 214 | static struct intel_iommu *map_ioapic_to_ir(int apic) |
89027d35 SS |
215 | { |
216 | int i; | |
217 | ||
218 | for (i = 0; i < MAX_IO_APICS; i++) | |
a7a3dad9 | 219 | if (ir_ioapic[i].id == apic && ir_ioapic[i].iommu) |
89027d35 SS |
220 | return ir_ioapic[i].iommu; |
221 | return NULL; | |
222 | } | |
223 | ||
263b5e86 | 224 | static struct intel_iommu *map_dev_to_ir(struct pci_dev *dev) |
75c46fa6 SS |
225 | { |
226 | struct dmar_drhd_unit *drhd; | |
227 | ||
228 | drhd = dmar_find_matched_drhd_unit(dev); | |
229 | if (!drhd) | |
230 | return NULL; | |
231 | ||
232 | return drhd->iommu; | |
233 | } | |
234 | ||
c4658b4e WH |
235 | static int clear_entries(struct irq_2_iommu *irq_iommu) |
236 | { | |
237 | struct irte *start, *entry, *end; | |
238 | struct intel_iommu *iommu; | |
239 | int index; | |
240 | ||
241 | if (irq_iommu->sub_handle) | |
242 | return 0; | |
243 | ||
244 | iommu = irq_iommu->iommu; | |
8dedf4cf | 245 | index = irq_iommu->irte_index; |
c4658b4e WH |
246 | |
247 | start = iommu->ir_table->base + index; | |
248 | end = start + (1 << irq_iommu->irte_mask); | |
249 | ||
250 | for (entry = start; entry < end; entry++) { | |
c513b67e LT |
251 | set_64bit(&entry->low, 0); |
252 | set_64bit(&entry->high, 0); | |
c4658b4e | 253 | } |
360eb3c5 JL |
254 | bitmap_release_region(iommu->ir_table->bitmap, index, |
255 | irq_iommu->irte_mask); | |
c4658b4e WH |
256 | |
257 | return qi_flush_iec(iommu, index, irq_iommu->irte_mask); | |
258 | } | |
259 | ||
f007e99c WH |
260 | /* |
261 | * source validation type | |
262 | */ | |
263 | #define SVT_NO_VERIFY 0x0 /* no verification is required */ | |
25985edc | 264 | #define SVT_VERIFY_SID_SQ 0x1 /* verify using SID and SQ fields */ |
f007e99c WH |
265 | #define SVT_VERIFY_BUS 0x2 /* verify bus of request-id */ |
266 | ||
267 | /* | |
268 | * source-id qualifier | |
269 | */ | |
270 | #define SQ_ALL_16 0x0 /* verify all 16 bits of request-id */ | |
271 | #define SQ_13_IGNORE_1 0x1 /* verify most significant 13 bits, ignore | |
272 | * the third least significant bit | |
273 | */ | |
274 | #define SQ_13_IGNORE_2 0x2 /* verify most significant 13 bits, ignore | |
275 | * the second and third least significant bits | |
276 | */ | |
277 | #define SQ_13_IGNORE_3 0x3 /* verify most significant 13 bits, ignore | |
278 | * the least three significant bits | |
279 | */ | |
280 | ||
281 | /* | |
282 | * set SVT, SQ and SID fields of irte to verify | |
283 | * source ids of interrupt requests | |
284 | */ | |
285 | static void set_irte_sid(struct irte *irte, unsigned int svt, | |
286 | unsigned int sq, unsigned int sid) | |
287 | { | |
d1423d56 CW |
288 | if (disable_sourceid_checking) |
289 | svt = SVT_NO_VERIFY; | |
f007e99c WH |
290 | irte->svt = svt; |
291 | irte->sq = sq; | |
292 | irte->sid = sid; | |
293 | } | |
294 | ||
263b5e86 | 295 | static int set_ioapic_sid(struct irte *irte, int apic) |
f007e99c WH |
296 | { |
297 | int i; | |
298 | u16 sid = 0; | |
299 | ||
300 | if (!irte) | |
301 | return -1; | |
302 | ||
3a5670e8 | 303 | down_read(&dmar_global_lock); |
f007e99c | 304 | for (i = 0; i < MAX_IO_APICS; i++) { |
a7a3dad9 | 305 | if (ir_ioapic[i].iommu && ir_ioapic[i].id == apic) { |
f007e99c WH |
306 | sid = (ir_ioapic[i].bus << 8) | ir_ioapic[i].devfn; |
307 | break; | |
308 | } | |
309 | } | |
3a5670e8 | 310 | up_read(&dmar_global_lock); |
f007e99c WH |
311 | |
312 | if (sid == 0) { | |
9f10e5bf | 313 | pr_warn("Failed to set source-id of IOAPIC (%d)\n", apic); |
f007e99c WH |
314 | return -1; |
315 | } | |
316 | ||
2fe2c602 | 317 | set_irte_sid(irte, SVT_VERIFY_SID_SQ, SQ_ALL_16, sid); |
f007e99c WH |
318 | |
319 | return 0; | |
320 | } | |
321 | ||
263b5e86 | 322 | static int set_hpet_sid(struct irte *irte, u8 id) |
20f3097b SS |
323 | { |
324 | int i; | |
325 | u16 sid = 0; | |
326 | ||
327 | if (!irte) | |
328 | return -1; | |
329 | ||
3a5670e8 | 330 | down_read(&dmar_global_lock); |
20f3097b | 331 | for (i = 0; i < MAX_HPET_TBS; i++) { |
a7a3dad9 | 332 | if (ir_hpet[i].iommu && ir_hpet[i].id == id) { |
20f3097b SS |
333 | sid = (ir_hpet[i].bus << 8) | ir_hpet[i].devfn; |
334 | break; | |
335 | } | |
336 | } | |
3a5670e8 | 337 | up_read(&dmar_global_lock); |
20f3097b SS |
338 | |
339 | if (sid == 0) { | |
9f10e5bf | 340 | pr_warn("Failed to set source-id of HPET block (%d)\n", id); |
20f3097b SS |
341 | return -1; |
342 | } | |
343 | ||
344 | /* | |
345 | * Should really use SQ_ALL_16. Some platforms are broken. | |
346 | * While we figure out the right quirks for these broken platforms, use | |
347 | * SQ_13_IGNORE_3 for now. | |
348 | */ | |
349 | set_irte_sid(irte, SVT_VERIFY_SID_SQ, SQ_13_IGNORE_3, sid); | |
350 | ||
351 | return 0; | |
352 | } | |
353 | ||
579305f7 AW |
354 | struct set_msi_sid_data { |
355 | struct pci_dev *pdev; | |
356 | u16 alias; | |
357 | }; | |
358 | ||
359 | static int set_msi_sid_cb(struct pci_dev *pdev, u16 alias, void *opaque) | |
360 | { | |
361 | struct set_msi_sid_data *data = opaque; | |
362 | ||
363 | data->pdev = pdev; | |
364 | data->alias = alias; | |
365 | ||
366 | return 0; | |
367 | } | |
368 | ||
263b5e86 | 369 | static int set_msi_sid(struct irte *irte, struct pci_dev *dev) |
f007e99c | 370 | { |
579305f7 | 371 | struct set_msi_sid_data data; |
f007e99c WH |
372 | |
373 | if (!irte || !dev) | |
374 | return -1; | |
375 | ||
579305f7 | 376 | pci_for_each_dma_alias(dev, set_msi_sid_cb, &data); |
f007e99c | 377 | |
579305f7 AW |
378 | /* |
379 | * DMA alias provides us with a PCI device and alias. The only case | |
380 | * where the it will return an alias on a different bus than the | |
381 | * device is the case of a PCIe-to-PCI bridge, where the alias is for | |
382 | * the subordinate bus. In this case we can only verify the bus. | |
383 | * | |
384 | * If the alias device is on a different bus than our source device | |
385 | * then we have a topology based alias, use it. | |
386 | * | |
387 | * Otherwise, the alias is for a device DMA quirk and we cannot | |
388 | * assume that MSI uses the same requester ID. Therefore use the | |
389 | * original device. | |
390 | */ | |
391 | if (PCI_BUS_NUM(data.alias) != data.pdev->bus->number) | |
392 | set_irte_sid(irte, SVT_VERIFY_BUS, SQ_ALL_16, | |
393 | PCI_DEVID(PCI_BUS_NUM(data.alias), | |
394 | dev->bus->number)); | |
395 | else if (data.pdev->bus->number != dev->bus->number) | |
396 | set_irte_sid(irte, SVT_VERIFY_SID_SQ, SQ_ALL_16, data.alias); | |
397 | else | |
398 | set_irte_sid(irte, SVT_VERIFY_SID_SQ, SQ_ALL_16, | |
399 | PCI_DEVID(dev->bus->number, dev->devfn)); | |
f007e99c WH |
400 | |
401 | return 0; | |
402 | } | |
403 | ||
af3b358e JR |
404 | static int iommu_load_old_irte(struct intel_iommu *iommu) |
405 | { | |
dfddb969 | 406 | struct irte *old_ir_table; |
af3b358e | 407 | phys_addr_t irt_phys; |
7c3c9876 | 408 | unsigned int i; |
af3b358e JR |
409 | size_t size; |
410 | u64 irta; | |
411 | ||
af3b358e JR |
412 | /* Check whether the old ir-table has the same size as ours */ |
413 | irta = dmar_readq(iommu->reg + DMAR_IRTA_REG); | |
414 | if ((irta & INTR_REMAP_TABLE_REG_SIZE_MASK) | |
415 | != INTR_REMAP_TABLE_REG_SIZE) | |
416 | return -EINVAL; | |
417 | ||
418 | irt_phys = irta & VTD_PAGE_MASK; | |
419 | size = INTR_REMAP_TABLE_ENTRIES*sizeof(struct irte); | |
420 | ||
421 | /* Map the old IR table */ | |
dfddb969 | 422 | old_ir_table = memremap(irt_phys, size, MEMREMAP_WB); |
af3b358e JR |
423 | if (!old_ir_table) |
424 | return -ENOMEM; | |
425 | ||
426 | /* Copy data over */ | |
dfddb969 | 427 | memcpy(iommu->ir_table->base, old_ir_table, size); |
af3b358e JR |
428 | |
429 | __iommu_flush_cache(iommu, iommu->ir_table->base, size); | |
430 | ||
7c3c9876 JR |
431 | /* |
432 | * Now check the table for used entries and mark those as | |
433 | * allocated in the bitmap | |
434 | */ | |
435 | for (i = 0; i < INTR_REMAP_TABLE_ENTRIES; i++) { | |
436 | if (iommu->ir_table->base[i].present) | |
437 | bitmap_set(iommu->ir_table->bitmap, i, 1); | |
438 | } | |
439 | ||
dfddb969 | 440 | memunmap(old_ir_table); |
50690762 | 441 | |
af3b358e JR |
442 | return 0; |
443 | } | |
444 | ||
445 | ||
95a02e97 | 446 | static void iommu_set_irq_remapping(struct intel_iommu *iommu, int mode) |
2ae21010 | 447 | { |
d4d1c0f3 | 448 | unsigned long flags; |
2ae21010 | 449 | u64 addr; |
c416daa9 | 450 | u32 sts; |
2ae21010 SS |
451 | |
452 | addr = virt_to_phys((void *)iommu->ir_table->base); | |
453 | ||
1f5b3c3f | 454 | raw_spin_lock_irqsave(&iommu->register_lock, flags); |
2ae21010 SS |
455 | |
456 | dmar_writeq(iommu->reg + DMAR_IRTA_REG, | |
457 | (addr) | IR_X2APIC_MODE(mode) | INTR_REMAP_TABLE_REG_SIZE); | |
458 | ||
459 | /* Set interrupt-remapping table pointer */ | |
f63ef690 | 460 | writel(iommu->gcmd | DMA_GCMD_SIRTP, iommu->reg + DMAR_GCMD_REG); |
2ae21010 SS |
461 | |
462 | IOMMU_WAIT_OP(iommu, DMAR_GSTS_REG, | |
463 | readl, (sts & DMA_GSTS_IRTPS), sts); | |
1f5b3c3f | 464 | raw_spin_unlock_irqrestore(&iommu->register_lock, flags); |
2ae21010 SS |
465 | |
466 | /* | |
d4d1c0f3 JR |
467 | * Global invalidation of interrupt entry cache to make sure the |
468 | * hardware uses the new irq remapping table. | |
2ae21010 SS |
469 | */ |
470 | qi_global_iec(iommu); | |
d4d1c0f3 JR |
471 | } |
472 | ||
473 | static void iommu_enable_irq_remapping(struct intel_iommu *iommu) | |
474 | { | |
475 | unsigned long flags; | |
476 | u32 sts; | |
2ae21010 | 477 | |
1f5b3c3f | 478 | raw_spin_lock_irqsave(&iommu->register_lock, flags); |
2ae21010 SS |
479 | |
480 | /* Enable interrupt-remapping */ | |
2ae21010 | 481 | iommu->gcmd |= DMA_GCMD_IRE; |
af8d102f | 482 | iommu->gcmd &= ~DMA_GCMD_CFI; /* Block compatibility-format MSIs */ |
c416daa9 | 483 | writel(iommu->gcmd, iommu->reg + DMAR_GCMD_REG); |
2ae21010 SS |
484 | |
485 | IOMMU_WAIT_OP(iommu, DMAR_GSTS_REG, | |
486 | readl, (sts & DMA_GSTS_IRES), sts); | |
487 | ||
af8d102f AL |
488 | /* |
489 | * With CFI clear in the Global Command register, we should be | |
490 | * protected from dangerous (i.e. compatibility) interrupts | |
491 | * regardless of x2apic status. Check just to be sure. | |
492 | */ | |
493 | if (sts & DMA_GSTS_CFIS) | |
494 | WARN(1, KERN_WARNING | |
495 | "Compatibility-format IRQs enabled despite intr remapping;\n" | |
496 | "you are vulnerable to IRQ injection.\n"); | |
497 | ||
1f5b3c3f | 498 | raw_spin_unlock_irqrestore(&iommu->register_lock, flags); |
2ae21010 SS |
499 | } |
500 | ||
a7a3dad9 | 501 | static int intel_setup_irq_remapping(struct intel_iommu *iommu) |
2ae21010 SS |
502 | { |
503 | struct ir_table *ir_table; | |
cea29b65 | 504 | struct fwnode_handle *fn; |
360eb3c5 | 505 | unsigned long *bitmap; |
cea29b65 | 506 | struct page *pages; |
2ae21010 | 507 | |
a7a3dad9 JL |
508 | if (iommu->ir_table) |
509 | return 0; | |
2ae21010 | 510 | |
e3a981d6 | 511 | ir_table = kzalloc(sizeof(struct ir_table), GFP_KERNEL); |
a7a3dad9 | 512 | if (!ir_table) |
2ae21010 SS |
513 | return -ENOMEM; |
514 | ||
e3a981d6 | 515 | pages = alloc_pages_node(iommu->node, GFP_KERNEL | __GFP_ZERO, |
824cd75b | 516 | INTR_REMAP_PAGE_ORDER); |
2ae21010 | 517 | if (!pages) { |
360eb3c5 JL |
518 | pr_err("IR%d: failed to allocate pages of order %d\n", |
519 | iommu->seq_id, INTR_REMAP_PAGE_ORDER); | |
a7a3dad9 | 520 | goto out_free_table; |
2ae21010 SS |
521 | } |
522 | ||
360eb3c5 JL |
523 | bitmap = kcalloc(BITS_TO_LONGS(INTR_REMAP_TABLE_ENTRIES), |
524 | sizeof(long), GFP_ATOMIC); | |
525 | if (bitmap == NULL) { | |
526 | pr_err("IR%d: failed to allocate bitmap\n", iommu->seq_id); | |
a7a3dad9 | 527 | goto out_free_pages; |
360eb3c5 JL |
528 | } |
529 | ||
cea29b65 TG |
530 | fn = irq_domain_alloc_named_id_fwnode("INTEL-IR", iommu->seq_id); |
531 | if (!fn) | |
532 | goto out_free_bitmap; | |
533 | ||
534 | iommu->ir_domain = | |
535 | irq_domain_create_hierarchy(arch_get_ir_parent_domain(), | |
536 | 0, INTR_REMAP_TABLE_ENTRIES, | |
537 | fn, &intel_ir_domain_ops, | |
538 | iommu); | |
539 | irq_domain_free_fwnode(fn); | |
b106ee63 JL |
540 | if (!iommu->ir_domain) { |
541 | pr_err("IR%d: failed to allocate irqdomain\n", iommu->seq_id); | |
542 | goto out_free_bitmap; | |
543 | } | |
cea29b65 TG |
544 | iommu->ir_msi_domain = |
545 | arch_create_remap_msi_irq_domain(iommu->ir_domain, | |
546 | "INTEL-IR-MSI", | |
547 | iommu->seq_id); | |
b106ee63 | 548 | |
2ae21010 | 549 | ir_table->base = page_address(pages); |
360eb3c5 | 550 | ir_table->bitmap = bitmap; |
a7a3dad9 | 551 | iommu->ir_table = ir_table; |
9e4e49df JR |
552 | |
553 | /* | |
554 | * If the queued invalidation is already initialized, | |
555 | * shouldn't disable it. | |
556 | */ | |
557 | if (!iommu->qi) { | |
558 | /* | |
559 | * Clear previous faults. | |
560 | */ | |
561 | dmar_fault(-1, iommu); | |
562 | dmar_disable_qi(iommu); | |
563 | ||
564 | if (dmar_enable_qi(iommu)) { | |
565 | pr_err("Failed to enable queued invalidation\n"); | |
566 | goto out_free_bitmap; | |
567 | } | |
568 | } | |
569 | ||
af3b358e JR |
570 | init_ir_status(iommu); |
571 | ||
572 | if (ir_pre_enabled(iommu)) { | |
8e121884 QZ |
573 | if (!is_kdump_kernel()) { |
574 | pr_warn("IRQ remapping was enabled on %s but we are not in kdump mode\n", | |
575 | iommu->name); | |
576 | clear_ir_pre_enabled(iommu); | |
577 | iommu_disable_irq_remapping(iommu); | |
578 | } else if (iommu_load_old_irte(iommu)) | |
af3b358e JR |
579 | pr_err("Failed to copy IR table for %s from previous kernel\n", |
580 | iommu->name); | |
581 | else | |
582 | pr_info("Copied IR table for %s from previous kernel\n", | |
583 | iommu->name); | |
584 | } | |
585 | ||
d4d1c0f3 JR |
586 | iommu_set_irq_remapping(iommu, eim_mode); |
587 | ||
2ae21010 | 588 | return 0; |
a7a3dad9 | 589 | |
b106ee63 JL |
590 | out_free_bitmap: |
591 | kfree(bitmap); | |
a7a3dad9 JL |
592 | out_free_pages: |
593 | __free_pages(pages, INTR_REMAP_PAGE_ORDER); | |
594 | out_free_table: | |
595 | kfree(ir_table); | |
9e4e49df JR |
596 | |
597 | iommu->ir_table = NULL; | |
598 | ||
a7a3dad9 JL |
599 | return -ENOMEM; |
600 | } | |
601 | ||
602 | static void intel_teardown_irq_remapping(struct intel_iommu *iommu) | |
603 | { | |
604 | if (iommu && iommu->ir_table) { | |
b106ee63 JL |
605 | if (iommu->ir_msi_domain) { |
606 | irq_domain_remove(iommu->ir_msi_domain); | |
607 | iommu->ir_msi_domain = NULL; | |
608 | } | |
609 | if (iommu->ir_domain) { | |
610 | irq_domain_remove(iommu->ir_domain); | |
611 | iommu->ir_domain = NULL; | |
612 | } | |
a7a3dad9 JL |
613 | free_pages((unsigned long)iommu->ir_table->base, |
614 | INTR_REMAP_PAGE_ORDER); | |
615 | kfree(iommu->ir_table->bitmap); | |
616 | kfree(iommu->ir_table); | |
617 | iommu->ir_table = NULL; | |
618 | } | |
2ae21010 SS |
619 | } |
620 | ||
eba67e5d SS |
621 | /* |
622 | * Disable Interrupt Remapping. | |
623 | */ | |
95a02e97 | 624 | static void iommu_disable_irq_remapping(struct intel_iommu *iommu) |
eba67e5d SS |
625 | { |
626 | unsigned long flags; | |
627 | u32 sts; | |
628 | ||
629 | if (!ecap_ir_support(iommu->ecap)) | |
630 | return; | |
631 | ||
b24696bc FY |
632 | /* |
633 | * global invalidation of interrupt entry cache before disabling | |
634 | * interrupt-remapping. | |
635 | */ | |
636 | qi_global_iec(iommu); | |
637 | ||
1f5b3c3f | 638 | raw_spin_lock_irqsave(&iommu->register_lock, flags); |
eba67e5d | 639 | |
fda3bec1 | 640 | sts = readl(iommu->reg + DMAR_GSTS_REG); |
eba67e5d SS |
641 | if (!(sts & DMA_GSTS_IRES)) |
642 | goto end; | |
643 | ||
644 | iommu->gcmd &= ~DMA_GCMD_IRE; | |
645 | writel(iommu->gcmd, iommu->reg + DMAR_GCMD_REG); | |
646 | ||
647 | IOMMU_WAIT_OP(iommu, DMAR_GSTS_REG, | |
648 | readl, !(sts & DMA_GSTS_IRES), sts); | |
649 | ||
650 | end: | |
1f5b3c3f | 651 | raw_spin_unlock_irqrestore(&iommu->register_lock, flags); |
eba67e5d SS |
652 | } |
653 | ||
41750d31 SS |
654 | static int __init dmar_x2apic_optout(void) |
655 | { | |
656 | struct acpi_table_dmar *dmar; | |
657 | dmar = (struct acpi_table_dmar *)dmar_tbl; | |
658 | if (!dmar || no_x2apic_optout) | |
659 | return 0; | |
660 | return dmar->flags & DMAR_X2APIC_OPT_OUT; | |
661 | } | |
662 | ||
11190302 TG |
663 | static void __init intel_cleanup_irq_remapping(void) |
664 | { | |
665 | struct dmar_drhd_unit *drhd; | |
666 | struct intel_iommu *iommu; | |
667 | ||
668 | for_each_iommu(iommu, drhd) { | |
669 | if (ecap_ir_support(iommu->ecap)) { | |
670 | iommu_disable_irq_remapping(iommu); | |
671 | intel_teardown_irq_remapping(iommu); | |
672 | } | |
673 | } | |
674 | ||
675 | if (x2apic_supported()) | |
9f10e5bf | 676 | pr_warn("Failed to enable irq remapping. You are vulnerable to irq-injection attacks.\n"); |
11190302 TG |
677 | } |
678 | ||
679 | static int __init intel_prepare_irq_remapping(void) | |
2ae21010 SS |
680 | { |
681 | struct dmar_drhd_unit *drhd; | |
7c919779 | 682 | struct intel_iommu *iommu; |
23256d0b | 683 | int eim = 0; |
2ae21010 | 684 | |
2966d956 | 685 | if (irq_remap_broken) { |
9f10e5bf | 686 | pr_warn("This system BIOS has enabled interrupt remapping\n" |
2966d956 JL |
687 | "on a chipset that contains an erratum making that\n" |
688 | "feature unstable. To maintain system stability\n" | |
689 | "interrupt remapping is being disabled. Please\n" | |
690 | "contact your BIOS vendor for an update\n"); | |
691 | add_taint(TAINT_FIRMWARE_WORKAROUND, LOCKDEP_STILL_OK); | |
2966d956 JL |
692 | return -ENODEV; |
693 | } | |
694 | ||
11190302 | 695 | if (dmar_table_init() < 0) |
2966d956 JL |
696 | return -ENODEV; |
697 | ||
698 | if (!dmar_ir_support()) | |
699 | return -ENODEV; | |
af8d102f | 700 | |
b61e5e80 | 701 | if (parse_ioapics_under_ir()) { |
9f10e5bf | 702 | pr_info("Not enabling interrupt remapping\n"); |
af8d102f | 703 | goto error; |
e936d077 YS |
704 | } |
705 | ||
69cf1d8a | 706 | /* First make sure all IOMMUs support IRQ remapping */ |
2966d956 | 707 | for_each_iommu(iommu, drhd) |
69cf1d8a JR |
708 | if (!ecap_ir_support(iommu->ecap)) |
709 | goto error; | |
710 | ||
23256d0b JR |
711 | /* Detect remapping mode: lapic or x2apic */ |
712 | if (x2apic_supported()) { | |
713 | eim = !dmar_x2apic_optout(); | |
714 | if (!eim) { | |
715 | pr_info("x2apic is disabled because BIOS sets x2apic opt out bit."); | |
716 | pr_info("Use 'intremap=no_x2apic_optout' to override the BIOS setting.\n"); | |
717 | } | |
718 | } | |
719 | ||
720 | for_each_iommu(iommu, drhd) { | |
721 | if (eim && !ecap_eim_support(iommu->ecap)) { | |
722 | pr_info("%s does not support EIM\n", iommu->name); | |
723 | eim = 0; | |
724 | } | |
725 | } | |
726 | ||
727 | eim_mode = eim; | |
728 | if (eim) | |
729 | pr_info("Queued invalidation will be enabled to support x2apic and Intr-remapping.\n"); | |
730 | ||
9e4e49df JR |
731 | /* Do the initializations early */ |
732 | for_each_iommu(iommu, drhd) { | |
733 | if (intel_setup_irq_remapping(iommu)) { | |
734 | pr_err("Failed to setup irq remapping for %s\n", | |
735 | iommu->name); | |
11190302 | 736 | goto error; |
9e4e49df JR |
737 | } |
738 | } | |
69cf1d8a | 739 | |
11190302 | 740 | return 0; |
2966d956 | 741 | |
11190302 TG |
742 | error: |
743 | intel_cleanup_irq_remapping(); | |
2966d956 | 744 | return -ENODEV; |
11190302 TG |
745 | } |
746 | ||
3d9b98f4 FW |
747 | /* |
748 | * Set Posted-Interrupts capability. | |
749 | */ | |
750 | static inline void set_irq_posting_cap(void) | |
751 | { | |
752 | struct dmar_drhd_unit *drhd; | |
753 | struct intel_iommu *iommu; | |
754 | ||
755 | if (!disable_irq_post) { | |
344cb4e0 FW |
756 | /* |
757 | * If IRTE is in posted format, the 'pda' field goes across the | |
758 | * 64-bit boundary, we need use cmpxchg16b to atomically update | |
759 | * it. We only expose posted-interrupt when X86_FEATURE_CX16 | |
760 | * is supported. Actually, hardware platforms supporting PI | |
761 | * should have X86_FEATURE_CX16 support, this has been confirmed | |
762 | * with Intel hardware guys. | |
763 | */ | |
362f924b | 764 | if (boot_cpu_has(X86_FEATURE_CX16)) |
344cb4e0 | 765 | intel_irq_remap_ops.capability |= 1 << IRQ_POSTING_CAP; |
3d9b98f4 FW |
766 | |
767 | for_each_iommu(iommu, drhd) | |
768 | if (!cap_pi_support(iommu->cap)) { | |
769 | intel_irq_remap_ops.capability &= | |
770 | ~(1 << IRQ_POSTING_CAP); | |
771 | break; | |
772 | } | |
773 | } | |
774 | } | |
775 | ||
11190302 TG |
776 | static int __init intel_enable_irq_remapping(void) |
777 | { | |
778 | struct dmar_drhd_unit *drhd; | |
779 | struct intel_iommu *iommu; | |
2f119c78 | 780 | bool setup = false; |
2ae21010 SS |
781 | |
782 | /* | |
783 | * Setup Interrupt-remapping for all the DRHD's now. | |
784 | */ | |
7c919779 | 785 | for_each_iommu(iommu, drhd) { |
571dbbd4 JR |
786 | if (!ir_pre_enabled(iommu)) |
787 | iommu_enable_irq_remapping(iommu); | |
2f119c78 | 788 | setup = true; |
2ae21010 SS |
789 | } |
790 | ||
791 | if (!setup) | |
792 | goto error; | |
793 | ||
95a02e97 | 794 | irq_remapping_enabled = 1; |
afcc8a40 | 795 | |
3d9b98f4 FW |
796 | set_irq_posting_cap(); |
797 | ||
23256d0b | 798 | pr_info("Enabled IRQ remapping in %s mode\n", eim_mode ? "x2apic" : "xapic"); |
2ae21010 | 799 | |
23256d0b | 800 | return eim_mode ? IRQ_REMAP_X2APIC_MODE : IRQ_REMAP_XAPIC_MODE; |
2ae21010 SS |
801 | |
802 | error: | |
11190302 | 803 | intel_cleanup_irq_remapping(); |
2ae21010 SS |
804 | return -1; |
805 | } | |
ad3ad3f6 | 806 | |
a7a3dad9 JL |
807 | static int ir_parse_one_hpet_scope(struct acpi_dmar_device_scope *scope, |
808 | struct intel_iommu *iommu, | |
809 | struct acpi_dmar_hardware_unit *drhd) | |
20f3097b SS |
810 | { |
811 | struct acpi_dmar_pci_path *path; | |
812 | u8 bus; | |
a7a3dad9 | 813 | int count, free = -1; |
20f3097b SS |
814 | |
815 | bus = scope->bus; | |
816 | path = (struct acpi_dmar_pci_path *)(scope + 1); | |
817 | count = (scope->length - sizeof(struct acpi_dmar_device_scope)) | |
818 | / sizeof(struct acpi_dmar_pci_path); | |
819 | ||
820 | while (--count > 0) { | |
821 | /* | |
822 | * Access PCI directly due to the PCI | |
823 | * subsystem isn't initialized yet. | |
824 | */ | |
fa5f508f | 825 | bus = read_pci_config_byte(bus, path->device, path->function, |
20f3097b SS |
826 | PCI_SECONDARY_BUS); |
827 | path++; | |
828 | } | |
a7a3dad9 JL |
829 | |
830 | for (count = 0; count < MAX_HPET_TBS; count++) { | |
831 | if (ir_hpet[count].iommu == iommu && | |
832 | ir_hpet[count].id == scope->enumeration_id) | |
833 | return 0; | |
834 | else if (ir_hpet[count].iommu == NULL && free == -1) | |
835 | free = count; | |
836 | } | |
837 | if (free == -1) { | |
838 | pr_warn("Exceeded Max HPET blocks\n"); | |
839 | return -ENOSPC; | |
840 | } | |
841 | ||
842 | ir_hpet[free].iommu = iommu; | |
843 | ir_hpet[free].id = scope->enumeration_id; | |
844 | ir_hpet[free].bus = bus; | |
845 | ir_hpet[free].devfn = PCI_DEVFN(path->device, path->function); | |
846 | pr_info("HPET id %d under DRHD base 0x%Lx\n", | |
847 | scope->enumeration_id, drhd->address); | |
848 | ||
849 | return 0; | |
20f3097b SS |
850 | } |
851 | ||
a7a3dad9 JL |
852 | static int ir_parse_one_ioapic_scope(struct acpi_dmar_device_scope *scope, |
853 | struct intel_iommu *iommu, | |
854 | struct acpi_dmar_hardware_unit *drhd) | |
f007e99c WH |
855 | { |
856 | struct acpi_dmar_pci_path *path; | |
857 | u8 bus; | |
a7a3dad9 | 858 | int count, free = -1; |
f007e99c WH |
859 | |
860 | bus = scope->bus; | |
861 | path = (struct acpi_dmar_pci_path *)(scope + 1); | |
862 | count = (scope->length - sizeof(struct acpi_dmar_device_scope)) | |
863 | / sizeof(struct acpi_dmar_pci_path); | |
864 | ||
865 | while (--count > 0) { | |
866 | /* | |
867 | * Access PCI directly due to the PCI | |
868 | * subsystem isn't initialized yet. | |
869 | */ | |
fa5f508f | 870 | bus = read_pci_config_byte(bus, path->device, path->function, |
f007e99c WH |
871 | PCI_SECONDARY_BUS); |
872 | path++; | |
873 | } | |
874 | ||
a7a3dad9 JL |
875 | for (count = 0; count < MAX_IO_APICS; count++) { |
876 | if (ir_ioapic[count].iommu == iommu && | |
877 | ir_ioapic[count].id == scope->enumeration_id) | |
878 | return 0; | |
879 | else if (ir_ioapic[count].iommu == NULL && free == -1) | |
880 | free = count; | |
881 | } | |
882 | if (free == -1) { | |
883 | pr_warn("Exceeded Max IO APICS\n"); | |
884 | return -ENOSPC; | |
885 | } | |
886 | ||
887 | ir_ioapic[free].bus = bus; | |
888 | ir_ioapic[free].devfn = PCI_DEVFN(path->device, path->function); | |
889 | ir_ioapic[free].iommu = iommu; | |
890 | ir_ioapic[free].id = scope->enumeration_id; | |
891 | pr_info("IOAPIC id %d under DRHD base 0x%Lx IOMMU %d\n", | |
892 | scope->enumeration_id, drhd->address, iommu->seq_id); | |
893 | ||
894 | return 0; | |
f007e99c WH |
895 | } |
896 | ||
20f3097b SS |
897 | static int ir_parse_ioapic_hpet_scope(struct acpi_dmar_header *header, |
898 | struct intel_iommu *iommu) | |
ad3ad3f6 | 899 | { |
a7a3dad9 | 900 | int ret = 0; |
ad3ad3f6 SS |
901 | struct acpi_dmar_hardware_unit *drhd; |
902 | struct acpi_dmar_device_scope *scope; | |
903 | void *start, *end; | |
904 | ||
905 | drhd = (struct acpi_dmar_hardware_unit *)header; | |
ad3ad3f6 SS |
906 | start = (void *)(drhd + 1); |
907 | end = ((void *)drhd) + header->length; | |
908 | ||
a7a3dad9 | 909 | while (start < end && ret == 0) { |
ad3ad3f6 | 910 | scope = start; |
a7a3dad9 JL |
911 | if (scope->entry_type == ACPI_DMAR_SCOPE_TYPE_IOAPIC) |
912 | ret = ir_parse_one_ioapic_scope(scope, iommu, drhd); | |
913 | else if (scope->entry_type == ACPI_DMAR_SCOPE_TYPE_HPET) | |
914 | ret = ir_parse_one_hpet_scope(scope, iommu, drhd); | |
915 | start += scope->length; | |
916 | } | |
ad3ad3f6 | 917 | |
a7a3dad9 JL |
918 | return ret; |
919 | } | |
20f3097b | 920 | |
a7a3dad9 JL |
921 | static void ir_remove_ioapic_hpet_scope(struct intel_iommu *iommu) |
922 | { | |
923 | int i; | |
20f3097b | 924 | |
a7a3dad9 JL |
925 | for (i = 0; i < MAX_HPET_TBS; i++) |
926 | if (ir_hpet[i].iommu == iommu) | |
927 | ir_hpet[i].iommu = NULL; | |
ad3ad3f6 | 928 | |
a7a3dad9 JL |
929 | for (i = 0; i < MAX_IO_APICS; i++) |
930 | if (ir_ioapic[i].iommu == iommu) | |
931 | ir_ioapic[i].iommu = NULL; | |
ad3ad3f6 SS |
932 | } |
933 | ||
934 | /* | |
935 | * Finds the assocaition between IOAPIC's and its Interrupt-remapping | |
936 | * hardware unit. | |
937 | */ | |
694835dc | 938 | static int __init parse_ioapics_under_ir(void) |
ad3ad3f6 SS |
939 | { |
940 | struct dmar_drhd_unit *drhd; | |
7c919779 | 941 | struct intel_iommu *iommu; |
2f119c78 | 942 | bool ir_supported = false; |
32ab31e0 | 943 | int ioapic_idx; |
ad3ad3f6 | 944 | |
66ef950d JR |
945 | for_each_iommu(iommu, drhd) { |
946 | int ret; | |
ad3ad3f6 | 947 | |
66ef950d JR |
948 | if (!ecap_ir_support(iommu->ecap)) |
949 | continue; | |
950 | ||
951 | ret = ir_parse_ioapic_hpet_scope(drhd->hdr, iommu); | |
952 | if (ret) | |
953 | return ret; | |
954 | ||
955 | ir_supported = true; | |
956 | } | |
ad3ad3f6 | 957 | |
32ab31e0 | 958 | if (!ir_supported) |
a13c8f27 | 959 | return -ENODEV; |
32ab31e0 SF |
960 | |
961 | for (ioapic_idx = 0; ioapic_idx < nr_ioapics; ioapic_idx++) { | |
962 | int ioapic_id = mpc_ioapic_id(ioapic_idx); | |
963 | if (!map_ioapic_to_ir(ioapic_id)) { | |
964 | pr_err(FW_BUG "ioapic %d has no mapping iommu, " | |
965 | "interrupt remapping will be disabled\n", | |
966 | ioapic_id); | |
967 | return -1; | |
968 | } | |
ad3ad3f6 SS |
969 | } |
970 | ||
a13c8f27 | 971 | return 0; |
ad3ad3f6 | 972 | } |
b24696bc | 973 | |
6a7885c4 | 974 | static int __init ir_dev_scope_init(void) |
c2c7286a | 975 | { |
3a5670e8 JL |
976 | int ret; |
977 | ||
95a02e97 | 978 | if (!irq_remapping_enabled) |
c2c7286a SS |
979 | return 0; |
980 | ||
3a5670e8 JL |
981 | down_write(&dmar_global_lock); |
982 | ret = dmar_dev_scope_init(); | |
983 | up_write(&dmar_global_lock); | |
984 | ||
985 | return ret; | |
c2c7286a SS |
986 | } |
987 | rootfs_initcall(ir_dev_scope_init); | |
988 | ||
95a02e97 | 989 | static void disable_irq_remapping(void) |
b24696bc FY |
990 | { |
991 | struct dmar_drhd_unit *drhd; | |
992 | struct intel_iommu *iommu = NULL; | |
993 | ||
994 | /* | |
995 | * Disable Interrupt-remapping for all the DRHD's now. | |
996 | */ | |
997 | for_each_iommu(iommu, drhd) { | |
998 | if (!ecap_ir_support(iommu->ecap)) | |
999 | continue; | |
1000 | ||
95a02e97 | 1001 | iommu_disable_irq_remapping(iommu); |
b24696bc | 1002 | } |
3d9b98f4 FW |
1003 | |
1004 | /* | |
1005 | * Clear Posted-Interrupts capability. | |
1006 | */ | |
1007 | if (!disable_irq_post) | |
1008 | intel_irq_remap_ops.capability &= ~(1 << IRQ_POSTING_CAP); | |
b24696bc FY |
1009 | } |
1010 | ||
95a02e97 | 1011 | static int reenable_irq_remapping(int eim) |
b24696bc FY |
1012 | { |
1013 | struct dmar_drhd_unit *drhd; | |
2f119c78 | 1014 | bool setup = false; |
b24696bc FY |
1015 | struct intel_iommu *iommu = NULL; |
1016 | ||
1017 | for_each_iommu(iommu, drhd) | |
1018 | if (iommu->qi) | |
1019 | dmar_reenable_qi(iommu); | |
1020 | ||
1021 | /* | |
1022 | * Setup Interrupt-remapping for all the DRHD's now. | |
1023 | */ | |
1024 | for_each_iommu(iommu, drhd) { | |
1025 | if (!ecap_ir_support(iommu->ecap)) | |
1026 | continue; | |
1027 | ||
1028 | /* Set up interrupt remapping for iommu.*/ | |
95a02e97 | 1029 | iommu_set_irq_remapping(iommu, eim); |
d4d1c0f3 | 1030 | iommu_enable_irq_remapping(iommu); |
2f119c78 | 1031 | setup = true; |
b24696bc FY |
1032 | } |
1033 | ||
1034 | if (!setup) | |
1035 | goto error; | |
1036 | ||
3d9b98f4 FW |
1037 | set_irq_posting_cap(); |
1038 | ||
b24696bc FY |
1039 | return 0; |
1040 | ||
1041 | error: | |
1042 | /* | |
1043 | * handle error condition gracefully here! | |
1044 | */ | |
1045 | return -1; | |
1046 | } | |
1047 | ||
3c6e5675 | 1048 | static void prepare_irte(struct irte *irte, int vector, unsigned int dest) |
0c3f173a JR |
1049 | { |
1050 | memset(irte, 0, sizeof(*irte)); | |
1051 | ||
1052 | irte->present = 1; | |
1053 | irte->dst_mode = apic->irq_dest_mode; | |
1054 | /* | |
1055 | * Trigger mode in the IRTE will always be edge, and for IO-APIC, the | |
1056 | * actual level or edge trigger will be setup in the IO-APIC | |
1057 | * RTE. This will help simplify level triggered irq migration. | |
1058 | * For more details, see the comments (in io_apic.c) explainig IO-APIC | |
1059 | * irq migration in the presence of interrupt-remapping. | |
1060 | */ | |
1061 | irte->trigger_mode = 0; | |
1062 | irte->dlvry_mode = apic->irq_delivery_mode; | |
1063 | irte->vector = vector; | |
1064 | irte->dest_id = IRTE_DEST(dest); | |
1065 | irte->redir_hint = 1; | |
1066 | } | |
1067 | ||
b106ee63 JL |
1068 | static struct irq_domain *intel_get_ir_irq_domain(struct irq_alloc_info *info) |
1069 | { | |
1070 | struct intel_iommu *iommu = NULL; | |
1071 | ||
1072 | if (!info) | |
1073 | return NULL; | |
1074 | ||
1075 | switch (info->type) { | |
1076 | case X86_IRQ_ALLOC_TYPE_IOAPIC: | |
1077 | iommu = map_ioapic_to_ir(info->ioapic_id); | |
1078 | break; | |
1079 | case X86_IRQ_ALLOC_TYPE_HPET: | |
1080 | iommu = map_hpet_to_ir(info->hpet_id); | |
1081 | break; | |
1082 | case X86_IRQ_ALLOC_TYPE_MSI: | |
1083 | case X86_IRQ_ALLOC_TYPE_MSIX: | |
1084 | iommu = map_dev_to_ir(info->msi_dev); | |
1085 | break; | |
1086 | default: | |
1087 | BUG_ON(1); | |
1088 | break; | |
1089 | } | |
1090 | ||
1091 | return iommu ? iommu->ir_domain : NULL; | |
1092 | } | |
1093 | ||
1094 | static struct irq_domain *intel_get_irq_domain(struct irq_alloc_info *info) | |
1095 | { | |
1096 | struct intel_iommu *iommu; | |
1097 | ||
1098 | if (!info) | |
1099 | return NULL; | |
1100 | ||
1101 | switch (info->type) { | |
1102 | case X86_IRQ_ALLOC_TYPE_MSI: | |
1103 | case X86_IRQ_ALLOC_TYPE_MSIX: | |
1104 | iommu = map_dev_to_ir(info->msi_dev); | |
1105 | if (iommu) | |
1106 | return iommu->ir_msi_domain; | |
1107 | break; | |
1108 | default: | |
1109 | break; | |
1110 | } | |
1111 | ||
1112 | return NULL; | |
1113 | } | |
1114 | ||
736baef4 | 1115 | struct irq_remap_ops intel_irq_remap_ops = { |
11190302 | 1116 | .prepare = intel_prepare_irq_remapping, |
95a02e97 SS |
1117 | .enable = intel_enable_irq_remapping, |
1118 | .disable = disable_irq_remapping, | |
1119 | .reenable = reenable_irq_remapping, | |
4f3d8b67 | 1120 | .enable_faulting = enable_drhd_fault_handling, |
b106ee63 JL |
1121 | .get_ir_irq_domain = intel_get_ir_irq_domain, |
1122 | .get_irq_domain = intel_get_irq_domain, | |
1123 | }; | |
1124 | ||
d491bdff TG |
1125 | static void intel_ir_reconfigure_irte(struct irq_data *irqd, bool force) |
1126 | { | |
1127 | struct intel_ir_data *ir_data = irqd->chip_data; | |
1128 | struct irte *irte = &ir_data->irte_entry; | |
1129 | struct irq_cfg *cfg = irqd_cfg(irqd); | |
1130 | ||
1131 | /* | |
1132 | * Atomically updates the IRTE with the new destination, vector | |
1133 | * and flushes the interrupt entry cache. | |
1134 | */ | |
1135 | irte->vector = cfg->vector; | |
1136 | irte->dest_id = IRTE_DEST(cfg->dest_apicid); | |
1137 | ||
1138 | /* Update the hardware only if the interrupt is in remapped mode. */ | |
1139 | if (!force || ir_data->irq_2_iommu.mode == IRQ_REMAPPING) | |
1140 | modify_irte(&ir_data->irq_2_iommu, irte); | |
1141 | } | |
1142 | ||
b106ee63 JL |
1143 | /* |
1144 | * Migrate the IO-APIC irq in the presence of intr-remapping. | |
1145 | * | |
1146 | * For both level and edge triggered, irq migration is a simple atomic | |
1147 | * update(of vector and cpu destination) of IRTE and flush the hardware cache. | |
1148 | * | |
1149 | * For level triggered, we eliminate the io-apic RTE modification (with the | |
1150 | * updated vector information), by using a virtual vector (io-apic pin number). | |
1151 | * Real vector that is used for interrupting cpu will be coming from | |
1152 | * the interrupt-remapping table entry. | |
1153 | * | |
1154 | * As the migration is a simple atomic update of IRTE, the same mechanism | |
1155 | * is used to migrate MSI irq's in the presence of interrupt-remapping. | |
1156 | */ | |
1157 | static int | |
1158 | intel_ir_set_affinity(struct irq_data *data, const struct cpumask *mask, | |
1159 | bool force) | |
1160 | { | |
b106ee63 | 1161 | struct irq_data *parent = data->parent_data; |
d491bdff | 1162 | struct irq_cfg *cfg = irqd_cfg(data); |
b106ee63 JL |
1163 | int ret; |
1164 | ||
1165 | ret = parent->chip->irq_set_affinity(parent, mask, force); | |
1166 | if (ret < 0 || ret == IRQ_SET_MASK_OK_DONE) | |
1167 | return ret; | |
1168 | ||
d491bdff | 1169 | intel_ir_reconfigure_irte(data, false); |
b106ee63 JL |
1170 | /* |
1171 | * After this point, all the interrupts will start arriving | |
1172 | * at the new destination. So, time to cleanup the previous | |
1173 | * vector allocation. | |
1174 | */ | |
c6c2002b | 1175 | send_cleanup_vector(cfg); |
b106ee63 JL |
1176 | |
1177 | return IRQ_SET_MASK_OK_DONE; | |
1178 | } | |
1179 | ||
1180 | static void intel_ir_compose_msi_msg(struct irq_data *irq_data, | |
1181 | struct msi_msg *msg) | |
1182 | { | |
1183 | struct intel_ir_data *ir_data = irq_data->chip_data; | |
1184 | ||
1185 | *msg = ir_data->msi_entry; | |
1186 | } | |
1187 | ||
8541186f FW |
1188 | static int intel_ir_set_vcpu_affinity(struct irq_data *data, void *info) |
1189 | { | |
1190 | struct intel_ir_data *ir_data = data->chip_data; | |
1191 | struct vcpu_data *vcpu_pi_info = info; | |
1192 | ||
1193 | /* stop posting interrupts, back to remapping mode */ | |
1194 | if (!vcpu_pi_info) { | |
1195 | modify_irte(&ir_data->irq_2_iommu, &ir_data->irte_entry); | |
1196 | } else { | |
1197 | struct irte irte_pi; | |
1198 | ||
1199 | /* | |
1200 | * We are not caching the posted interrupt entry. We | |
1201 | * copy the data from the remapped entry and modify | |
1202 | * the fields which are relevant for posted mode. The | |
1203 | * cached remapped entry is used for switching back to | |
1204 | * remapped mode. | |
1205 | */ | |
1206 | memset(&irte_pi, 0, sizeof(irte_pi)); | |
1207 | dmar_copy_shared_irte(&irte_pi, &ir_data->irte_entry); | |
1208 | ||
1209 | /* Update the posted mode fields */ | |
1210 | irte_pi.p_pst = 1; | |
1211 | irte_pi.p_urgent = 0; | |
1212 | irte_pi.p_vector = vcpu_pi_info->vector; | |
1213 | irte_pi.pda_l = (vcpu_pi_info->pi_desc_addr >> | |
1214 | (32 - PDA_LOW_BIT)) & ~(-1UL << PDA_LOW_BIT); | |
1215 | irte_pi.pda_h = (vcpu_pi_info->pi_desc_addr >> 32) & | |
1216 | ~(-1UL << PDA_HIGH_BIT); | |
1217 | ||
1218 | modify_irte(&ir_data->irq_2_iommu, &irte_pi); | |
1219 | } | |
1220 | ||
1221 | return 0; | |
1222 | } | |
1223 | ||
b106ee63 | 1224 | static struct irq_chip intel_ir_chip = { |
1bb3a5a7 TG |
1225 | .name = "INTEL-IR", |
1226 | .irq_ack = ir_ack_apic_edge, | |
1227 | .irq_set_affinity = intel_ir_set_affinity, | |
1228 | .irq_compose_msi_msg = intel_ir_compose_msi_msg, | |
1229 | .irq_set_vcpu_affinity = intel_ir_set_vcpu_affinity, | |
b106ee63 JL |
1230 | }; |
1231 | ||
1232 | static void intel_irq_remapping_prepare_irte(struct intel_ir_data *data, | |
1233 | struct irq_cfg *irq_cfg, | |
1234 | struct irq_alloc_info *info, | |
1235 | int index, int sub_handle) | |
1236 | { | |
1237 | struct IR_IO_APIC_route_entry *entry; | |
1238 | struct irte *irte = &data->irte_entry; | |
1239 | struct msi_msg *msg = &data->msi_entry; | |
1240 | ||
1241 | prepare_irte(irte, irq_cfg->vector, irq_cfg->dest_apicid); | |
1242 | switch (info->type) { | |
1243 | case X86_IRQ_ALLOC_TYPE_IOAPIC: | |
1244 | /* Set source-id of interrupt request */ | |
1245 | set_ioapic_sid(irte, info->ioapic_id); | |
1246 | apic_printk(APIC_VERBOSE, KERN_DEBUG "IOAPIC[%d]: Set IRTE entry (P:%d FPD:%d Dst_Mode:%d Redir_hint:%d Trig_Mode:%d Dlvry_Mode:%X Avail:%X Vector:%02X Dest:%08X SID:%04X SQ:%X SVT:%X)\n", | |
1247 | info->ioapic_id, irte->present, irte->fpd, | |
1248 | irte->dst_mode, irte->redir_hint, | |
1249 | irte->trigger_mode, irte->dlvry_mode, | |
1250 | irte->avail, irte->vector, irte->dest_id, | |
1251 | irte->sid, irte->sq, irte->svt); | |
1252 | ||
1253 | entry = (struct IR_IO_APIC_route_entry *)info->ioapic_entry; | |
1254 | info->ioapic_entry = NULL; | |
1255 | memset(entry, 0, sizeof(*entry)); | |
1256 | entry->index2 = (index >> 15) & 0x1; | |
1257 | entry->zero = 0; | |
1258 | entry->format = 1; | |
1259 | entry->index = (index & 0x7fff); | |
1260 | /* | |
1261 | * IO-APIC RTE will be configured with virtual vector. | |
1262 | * irq handler will do the explicit EOI to the io-apic. | |
1263 | */ | |
1264 | entry->vector = info->ioapic_pin; | |
1265 | entry->mask = 0; /* enable IRQ */ | |
1266 | entry->trigger = info->ioapic_trigger; | |
1267 | entry->polarity = info->ioapic_polarity; | |
1268 | if (info->ioapic_trigger) | |
1269 | entry->mask = 1; /* Mask level triggered irqs. */ | |
1270 | break; | |
1271 | ||
1272 | case X86_IRQ_ALLOC_TYPE_HPET: | |
1273 | case X86_IRQ_ALLOC_TYPE_MSI: | |
1274 | case X86_IRQ_ALLOC_TYPE_MSIX: | |
1275 | if (info->type == X86_IRQ_ALLOC_TYPE_HPET) | |
1276 | set_hpet_sid(irte, info->hpet_id); | |
1277 | else | |
1278 | set_msi_sid(irte, info->msi_dev); | |
1279 | ||
1280 | msg->address_hi = MSI_ADDR_BASE_HI; | |
1281 | msg->data = sub_handle; | |
1282 | msg->address_lo = MSI_ADDR_BASE_LO | MSI_ADDR_IR_EXT_INT | | |
1283 | MSI_ADDR_IR_SHV | | |
1284 | MSI_ADDR_IR_INDEX1(index) | | |
1285 | MSI_ADDR_IR_INDEX2(index); | |
1286 | break; | |
1287 | ||
1288 | default: | |
1289 | BUG_ON(1); | |
1290 | break; | |
1291 | } | |
1292 | } | |
1293 | ||
1294 | static void intel_free_irq_resources(struct irq_domain *domain, | |
1295 | unsigned int virq, unsigned int nr_irqs) | |
1296 | { | |
1297 | struct irq_data *irq_data; | |
1298 | struct intel_ir_data *data; | |
1299 | struct irq_2_iommu *irq_iommu; | |
1300 | unsigned long flags; | |
1301 | int i; | |
b106ee63 JL |
1302 | for (i = 0; i < nr_irqs; i++) { |
1303 | irq_data = irq_domain_get_irq_data(domain, virq + i); | |
1304 | if (irq_data && irq_data->chip_data) { | |
1305 | data = irq_data->chip_data; | |
1306 | irq_iommu = &data->irq_2_iommu; | |
1307 | raw_spin_lock_irqsave(&irq_2_ir_lock, flags); | |
1308 | clear_entries(irq_iommu); | |
1309 | raw_spin_unlock_irqrestore(&irq_2_ir_lock, flags); | |
1310 | irq_domain_reset_irq_data(irq_data); | |
1311 | kfree(data); | |
1312 | } | |
1313 | } | |
1314 | } | |
1315 | ||
1316 | static int intel_irq_remapping_alloc(struct irq_domain *domain, | |
1317 | unsigned int virq, unsigned int nr_irqs, | |
1318 | void *arg) | |
1319 | { | |
1320 | struct intel_iommu *iommu = domain->host_data; | |
1321 | struct irq_alloc_info *info = arg; | |
9d4c0313 | 1322 | struct intel_ir_data *data, *ird; |
b106ee63 JL |
1323 | struct irq_data *irq_data; |
1324 | struct irq_cfg *irq_cfg; | |
1325 | int i, ret, index; | |
1326 | ||
1327 | if (!info || !iommu) | |
1328 | return -EINVAL; | |
1329 | if (nr_irqs > 1 && info->type != X86_IRQ_ALLOC_TYPE_MSI && | |
1330 | info->type != X86_IRQ_ALLOC_TYPE_MSIX) | |
1331 | return -EINVAL; | |
1332 | ||
1333 | /* | |
1334 | * With IRQ remapping enabled, don't need contiguous CPU vectors | |
1335 | * to support multiple MSI interrupts. | |
1336 | */ | |
1337 | if (info->type == X86_IRQ_ALLOC_TYPE_MSI) | |
1338 | info->flags &= ~X86_IRQ_ALLOC_CONTIGUOUS_VECTORS; | |
1339 | ||
1340 | ret = irq_domain_alloc_irqs_parent(domain, virq, nr_irqs, arg); | |
1341 | if (ret < 0) | |
1342 | return ret; | |
1343 | ||
1344 | ret = -ENOMEM; | |
1345 | data = kzalloc(sizeof(*data), GFP_KERNEL); | |
1346 | if (!data) | |
1347 | goto out_free_parent; | |
1348 | ||
1349 | down_read(&dmar_global_lock); | |
1350 | index = alloc_irte(iommu, virq, &data->irq_2_iommu, nr_irqs); | |
1351 | up_read(&dmar_global_lock); | |
1352 | if (index < 0) { | |
1353 | pr_warn("Failed to allocate IRTE\n"); | |
1354 | kfree(data); | |
1355 | goto out_free_parent; | |
1356 | } | |
1357 | ||
1358 | for (i = 0; i < nr_irqs; i++) { | |
1359 | irq_data = irq_domain_get_irq_data(domain, virq + i); | |
1360 | irq_cfg = irqd_cfg(irq_data); | |
1361 | if (!irq_data || !irq_cfg) { | |
1362 | ret = -EINVAL; | |
1363 | goto out_free_data; | |
1364 | } | |
1365 | ||
1366 | if (i > 0) { | |
9d4c0313 TG |
1367 | ird = kzalloc(sizeof(*ird), GFP_KERNEL); |
1368 | if (!ird) | |
b106ee63 | 1369 | goto out_free_data; |
9d4c0313 TG |
1370 | /* Initialize the common data */ |
1371 | ird->irq_2_iommu = data->irq_2_iommu; | |
1372 | ird->irq_2_iommu.sub_handle = i; | |
1373 | } else { | |
1374 | ird = data; | |
b106ee63 | 1375 | } |
9d4c0313 | 1376 | |
b106ee63 | 1377 | irq_data->hwirq = (index << 16) + i; |
9d4c0313 | 1378 | irq_data->chip_data = ird; |
b106ee63 | 1379 | irq_data->chip = &intel_ir_chip; |
9d4c0313 | 1380 | intel_irq_remapping_prepare_irte(ird, irq_cfg, info, index, i); |
b106ee63 JL |
1381 | irq_set_status_flags(virq + i, IRQ_MOVE_PCNTXT); |
1382 | } | |
1383 | return 0; | |
1384 | ||
1385 | out_free_data: | |
1386 | intel_free_irq_resources(domain, virq, i); | |
1387 | out_free_parent: | |
1388 | irq_domain_free_irqs_common(domain, virq, nr_irqs); | |
1389 | return ret; | |
1390 | } | |
1391 | ||
1392 | static void intel_irq_remapping_free(struct irq_domain *domain, | |
1393 | unsigned int virq, unsigned int nr_irqs) | |
1394 | { | |
1395 | intel_free_irq_resources(domain, virq, nr_irqs); | |
1396 | irq_domain_free_irqs_common(domain, virq, nr_irqs); | |
1397 | } | |
1398 | ||
72491643 | 1399 | static int intel_irq_remapping_activate(struct irq_domain *domain, |
702cb0a0 | 1400 | struct irq_data *irq_data, bool reserve) |
b106ee63 | 1401 | { |
d491bdff | 1402 | intel_ir_reconfigure_irte(irq_data, true); |
72491643 | 1403 | return 0; |
b106ee63 JL |
1404 | } |
1405 | ||
1406 | static void intel_irq_remapping_deactivate(struct irq_domain *domain, | |
1407 | struct irq_data *irq_data) | |
1408 | { | |
1409 | struct intel_ir_data *data = irq_data->chip_data; | |
1410 | struct irte entry; | |
1411 | ||
1412 | memset(&entry, 0, sizeof(entry)); | |
1413 | modify_irte(&data->irq_2_iommu, &entry); | |
1414 | } | |
1415 | ||
71bb620d | 1416 | static const struct irq_domain_ops intel_ir_domain_ops = { |
b106ee63 JL |
1417 | .alloc = intel_irq_remapping_alloc, |
1418 | .free = intel_irq_remapping_free, | |
1419 | .activate = intel_irq_remapping_activate, | |
1420 | .deactivate = intel_irq_remapping_deactivate, | |
736baef4 | 1421 | }; |
6b197249 | 1422 | |
a7a3dad9 JL |
1423 | /* |
1424 | * Support of Interrupt Remapping Unit Hotplug | |
1425 | */ | |
1426 | static int dmar_ir_add(struct dmar_drhd_unit *dmaru, struct intel_iommu *iommu) | |
1427 | { | |
1428 | int ret; | |
1429 | int eim = x2apic_enabled(); | |
1430 | ||
1431 | if (eim && !ecap_eim_support(iommu->ecap)) { | |
1432 | pr_info("DRHD %Lx: EIM not supported by DRHD, ecap %Lx\n", | |
1433 | iommu->reg_phys, iommu->ecap); | |
1434 | return -ENODEV; | |
1435 | } | |
1436 | ||
1437 | if (ir_parse_ioapic_hpet_scope(dmaru->hdr, iommu)) { | |
1438 | pr_warn("DRHD %Lx: failed to parse managed IOAPIC/HPET\n", | |
1439 | iommu->reg_phys); | |
1440 | return -ENODEV; | |
1441 | } | |
1442 | ||
1443 | /* TODO: check all IOAPICs are covered by IOMMU */ | |
1444 | ||
1445 | /* Setup Interrupt-remapping now. */ | |
1446 | ret = intel_setup_irq_remapping(iommu); | |
1447 | if (ret) { | |
9e4e49df JR |
1448 | pr_err("Failed to setup irq remapping for %s\n", |
1449 | iommu->name); | |
a7a3dad9 JL |
1450 | intel_teardown_irq_remapping(iommu); |
1451 | ir_remove_ioapic_hpet_scope(iommu); | |
9e4e49df | 1452 | } else { |
d4d1c0f3 | 1453 | iommu_enable_irq_remapping(iommu); |
a7a3dad9 JL |
1454 | } |
1455 | ||
1456 | return ret; | |
1457 | } | |
1458 | ||
6b197249 JL |
1459 | int dmar_ir_hotplug(struct dmar_drhd_unit *dmaru, bool insert) |
1460 | { | |
a7a3dad9 JL |
1461 | int ret = 0; |
1462 | struct intel_iommu *iommu = dmaru->iommu; | |
1463 | ||
1464 | if (!irq_remapping_enabled) | |
1465 | return 0; | |
1466 | if (iommu == NULL) | |
1467 | return -EINVAL; | |
1468 | if (!ecap_ir_support(iommu->ecap)) | |
1469 | return 0; | |
c1d99334 FW |
1470 | if (irq_remapping_cap(IRQ_POSTING_CAP) && |
1471 | !cap_pi_support(iommu->cap)) | |
1472 | return -EBUSY; | |
a7a3dad9 JL |
1473 | |
1474 | if (insert) { | |
1475 | if (!iommu->ir_table) | |
1476 | ret = dmar_ir_add(dmaru, iommu); | |
1477 | } else { | |
1478 | if (iommu->ir_table) { | |
1479 | if (!bitmap_empty(iommu->ir_table->bitmap, | |
1480 | INTR_REMAP_TABLE_ENTRIES)) { | |
1481 | ret = -EBUSY; | |
1482 | } else { | |
1483 | iommu_disable_irq_remapping(iommu); | |
1484 | intel_teardown_irq_remapping(iommu); | |
1485 | ir_remove_ioapic_hpet_scope(iommu); | |
1486 | } | |
1487 | } | |
1488 | } | |
1489 | ||
1490 | return ret; | |
6b197249 | 1491 | } |