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Commit | Line | Data |
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9f10e5bf JR |
1 | |
2 | #define pr_fmt(fmt) "DMAR-IR: " fmt | |
3 | ||
5aeecaf4 | 4 | #include <linux/interrupt.h> |
ad3ad3f6 | 5 | #include <linux/dmar.h> |
2ae21010 | 6 | #include <linux/spinlock.h> |
5a0e3ad6 | 7 | #include <linux/slab.h> |
2ae21010 | 8 | #include <linux/jiffies.h> |
20f3097b | 9 | #include <linux/hpet.h> |
2ae21010 | 10 | #include <linux/pci.h> |
b6fcb33a | 11 | #include <linux/irq.h> |
8b48463f LZ |
12 | #include <linux/intel-iommu.h> |
13 | #include <linux/acpi.h> | |
b106ee63 | 14 | #include <linux/irqdomain.h> |
af3b358e | 15 | #include <linux/crash_dump.h> |
ad3ad3f6 | 16 | #include <asm/io_apic.h> |
17483a1f | 17 | #include <asm/smp.h> |
6d652ea1 | 18 | #include <asm/cpu.h> |
8a8f422d | 19 | #include <asm/irq_remapping.h> |
f007e99c | 20 | #include <asm/pci-direct.h> |
5e2b930b | 21 | #include <asm/msidef.h> |
ad3ad3f6 | 22 | |
8a8f422d | 23 | #include "irq_remapping.h" |
736baef4 | 24 | |
2705a3d2 FW |
25 | enum irq_mode { |
26 | IRQ_REMAPPING, | |
27 | IRQ_POSTING, | |
28 | }; | |
29 | ||
eef93fdb JR |
30 | struct ioapic_scope { |
31 | struct intel_iommu *iommu; | |
32 | unsigned int id; | |
33 | unsigned int bus; /* PCI bus number */ | |
34 | unsigned int devfn; /* PCI devfn number */ | |
35 | }; | |
36 | ||
37 | struct hpet_scope { | |
38 | struct intel_iommu *iommu; | |
39 | u8 id; | |
40 | unsigned int bus; | |
41 | unsigned int devfn; | |
42 | }; | |
43 | ||
099c5c03 JL |
44 | struct irq_2_iommu { |
45 | struct intel_iommu *iommu; | |
46 | u16 irte_index; | |
47 | u16 sub_handle; | |
48 | u8 irte_mask; | |
2705a3d2 | 49 | enum irq_mode mode; |
099c5c03 JL |
50 | }; |
51 | ||
b106ee63 JL |
52 | struct intel_ir_data { |
53 | struct irq_2_iommu irq_2_iommu; | |
54 | struct irte irte_entry; | |
55 | union { | |
56 | struct msi_msg msi_entry; | |
57 | }; | |
58 | }; | |
59 | ||
eef93fdb | 60 | #define IR_X2APIC_MODE(mode) (mode ? (1 << 11) : 0) |
13d09b66 | 61 | #define IRTE_DEST(dest) ((eim_mode) ? dest : dest << 8) |
eef93fdb | 62 | |
13d09b66 | 63 | static int __read_mostly eim_mode; |
ad3ad3f6 | 64 | static struct ioapic_scope ir_ioapic[MAX_IO_APICS]; |
20f3097b | 65 | static struct hpet_scope ir_hpet[MAX_HPET_TBS]; |
d1423d56 | 66 | |
3a5670e8 JL |
67 | /* |
68 | * Lock ordering: | |
69 | * ->dmar_global_lock | |
70 | * ->irq_2_ir_lock | |
71 | * ->qi->q_lock | |
72 | * ->iommu->register_lock | |
73 | * Note: | |
74 | * intel_irq_remap_ops.{supported,prepare,enable,disable,reenable} are called | |
75 | * in single-threaded environment with interrupt disabled, so no need to tabke | |
76 | * the dmar_global_lock. | |
77 | */ | |
96f8e98b | 78 | static DEFINE_RAW_SPINLOCK(irq_2_ir_lock); |
b106ee63 | 79 | static struct irq_domain_ops intel_ir_domain_ops; |
d585d060 | 80 | |
af3b358e | 81 | static void iommu_disable_irq_remapping(struct intel_iommu *iommu); |
694835dc JL |
82 | static int __init parse_ioapics_under_ir(void); |
83 | ||
af3b358e JR |
84 | static bool ir_pre_enabled(struct intel_iommu *iommu) |
85 | { | |
86 | return (iommu->flags & VTD_FLAG_IRQ_REMAP_PRE_ENABLED); | |
87 | } | |
88 | ||
89 | static void clear_ir_pre_enabled(struct intel_iommu *iommu) | |
90 | { | |
91 | iommu->flags &= ~VTD_FLAG_IRQ_REMAP_PRE_ENABLED; | |
92 | } | |
93 | ||
94 | static void init_ir_status(struct intel_iommu *iommu) | |
95 | { | |
96 | u32 gsts; | |
97 | ||
98 | gsts = readl(iommu->reg + DMAR_GSTS_REG); | |
99 | if (gsts & DMA_GSTS_IRES) | |
100 | iommu->flags |= VTD_FLAG_IRQ_REMAP_PRE_ENABLED; | |
101 | } | |
102 | ||
8dedf4cf JL |
103 | static int alloc_irte(struct intel_iommu *iommu, int irq, |
104 | struct irq_2_iommu *irq_iommu, u16 count) | |
b6fcb33a SS |
105 | { |
106 | struct ir_table *table = iommu->ir_table; | |
b6fcb33a | 107 | unsigned int mask = 0; |
4c5502b1 | 108 | unsigned long flags; |
9f4c7448 | 109 | int index; |
b6fcb33a | 110 | |
d585d060 | 111 | if (!count || !irq_iommu) |
e420dfb4 | 112 | return -1; |
e420dfb4 | 113 | |
b6fcb33a SS |
114 | if (count > 1) { |
115 | count = __roundup_pow_of_two(count); | |
116 | mask = ilog2(count); | |
117 | } | |
118 | ||
119 | if (mask > ecap_max_handle_mask(iommu->ecap)) { | |
9f10e5bf | 120 | pr_err("Requested mask %x exceeds the max invalidation handle" |
b6fcb33a SS |
121 | " mask value %Lx\n", mask, |
122 | ecap_max_handle_mask(iommu->ecap)); | |
123 | return -1; | |
124 | } | |
125 | ||
96f8e98b | 126 | raw_spin_lock_irqsave(&irq_2_ir_lock, flags); |
360eb3c5 JL |
127 | index = bitmap_find_free_region(table->bitmap, |
128 | INTR_REMAP_TABLE_ENTRIES, mask); | |
129 | if (index < 0) { | |
130 | pr_warn("IR%d: can't allocate an IRTE\n", iommu->seq_id); | |
131 | } else { | |
360eb3c5 JL |
132 | irq_iommu->iommu = iommu; |
133 | irq_iommu->irte_index = index; | |
134 | irq_iommu->sub_handle = 0; | |
135 | irq_iommu->irte_mask = mask; | |
2705a3d2 | 136 | irq_iommu->mode = IRQ_REMAPPING; |
360eb3c5 | 137 | } |
96f8e98b | 138 | raw_spin_unlock_irqrestore(&irq_2_ir_lock, flags); |
b6fcb33a SS |
139 | |
140 | return index; | |
141 | } | |
142 | ||
704126ad | 143 | static int qi_flush_iec(struct intel_iommu *iommu, int index, int mask) |
b6fcb33a SS |
144 | { |
145 | struct qi_desc desc; | |
146 | ||
147 | desc.low = QI_IEC_IIDEX(index) | QI_IEC_TYPE | QI_IEC_IM(mask) | |
148 | | QI_IEC_SELECTIVE; | |
149 | desc.high = 0; | |
150 | ||
704126ad | 151 | return qi_submit_sync(&desc, iommu); |
b6fcb33a SS |
152 | } |
153 | ||
8dedf4cf JL |
154 | static int modify_irte(struct irq_2_iommu *irq_iommu, |
155 | struct irte *irte_modified) | |
b6fcb33a | 156 | { |
b6fcb33a | 157 | struct intel_iommu *iommu; |
4c5502b1 | 158 | unsigned long flags; |
d585d060 TG |
159 | struct irte *irte; |
160 | int rc, index; | |
b6fcb33a | 161 | |
d585d060 | 162 | if (!irq_iommu) |
b6fcb33a | 163 | return -1; |
d585d060 | 164 | |
96f8e98b | 165 | raw_spin_lock_irqsave(&irq_2_ir_lock, flags); |
b6fcb33a | 166 | |
e420dfb4 | 167 | iommu = irq_iommu->iommu; |
b6fcb33a | 168 | |
e420dfb4 | 169 | index = irq_iommu->irte_index + irq_iommu->sub_handle; |
b6fcb33a SS |
170 | irte = &iommu->ir_table->base[index]; |
171 | ||
344cb4e0 FW |
172 | #if defined(CONFIG_HAVE_CMPXCHG_DOUBLE) |
173 | if ((irte->pst == 1) || (irte_modified->pst == 1)) { | |
174 | bool ret; | |
175 | ||
176 | ret = cmpxchg_double(&irte->low, &irte->high, | |
177 | irte->low, irte->high, | |
178 | irte_modified->low, irte_modified->high); | |
179 | /* | |
180 | * We use cmpxchg16 to atomically update the 128-bit IRTE, | |
181 | * and it cannot be updated by the hardware or other processors | |
182 | * behind us, so the return value of cmpxchg16 should be the | |
183 | * same as the old value. | |
184 | */ | |
185 | WARN_ON(!ret); | |
186 | } else | |
187 | #endif | |
188 | { | |
189 | set_64bit(&irte->low, irte_modified->low); | |
190 | set_64bit(&irte->high, irte_modified->high); | |
191 | } | |
b6fcb33a SS |
192 | __iommu_flush_cache(iommu, irte, sizeof(*irte)); |
193 | ||
704126ad | 194 | rc = qi_flush_iec(iommu, index, 0); |
2705a3d2 FW |
195 | |
196 | /* Update iommu mode according to the IRTE mode */ | |
197 | irq_iommu->mode = irte->pst ? IRQ_POSTING : IRQ_REMAPPING; | |
96f8e98b | 198 | raw_spin_unlock_irqrestore(&irq_2_ir_lock, flags); |
704126ad YZ |
199 | |
200 | return rc; | |
b6fcb33a SS |
201 | } |
202 | ||
263b5e86 | 203 | static struct intel_iommu *map_hpet_to_ir(u8 hpet_id) |
20f3097b SS |
204 | { |
205 | int i; | |
206 | ||
207 | for (i = 0; i < MAX_HPET_TBS; i++) | |
a7a3dad9 | 208 | if (ir_hpet[i].id == hpet_id && ir_hpet[i].iommu) |
20f3097b SS |
209 | return ir_hpet[i].iommu; |
210 | return NULL; | |
211 | } | |
212 | ||
263b5e86 | 213 | static struct intel_iommu *map_ioapic_to_ir(int apic) |
89027d35 SS |
214 | { |
215 | int i; | |
216 | ||
217 | for (i = 0; i < MAX_IO_APICS; i++) | |
a7a3dad9 | 218 | if (ir_ioapic[i].id == apic && ir_ioapic[i].iommu) |
89027d35 SS |
219 | return ir_ioapic[i].iommu; |
220 | return NULL; | |
221 | } | |
222 | ||
263b5e86 | 223 | static struct intel_iommu *map_dev_to_ir(struct pci_dev *dev) |
75c46fa6 SS |
224 | { |
225 | struct dmar_drhd_unit *drhd; | |
226 | ||
227 | drhd = dmar_find_matched_drhd_unit(dev); | |
228 | if (!drhd) | |
229 | return NULL; | |
230 | ||
231 | return drhd->iommu; | |
232 | } | |
233 | ||
c4658b4e WH |
234 | static int clear_entries(struct irq_2_iommu *irq_iommu) |
235 | { | |
236 | struct irte *start, *entry, *end; | |
237 | struct intel_iommu *iommu; | |
238 | int index; | |
239 | ||
240 | if (irq_iommu->sub_handle) | |
241 | return 0; | |
242 | ||
243 | iommu = irq_iommu->iommu; | |
8dedf4cf | 244 | index = irq_iommu->irte_index; |
c4658b4e WH |
245 | |
246 | start = iommu->ir_table->base + index; | |
247 | end = start + (1 << irq_iommu->irte_mask); | |
248 | ||
249 | for (entry = start; entry < end; entry++) { | |
c513b67e LT |
250 | set_64bit(&entry->low, 0); |
251 | set_64bit(&entry->high, 0); | |
c4658b4e | 252 | } |
360eb3c5 JL |
253 | bitmap_release_region(iommu->ir_table->bitmap, index, |
254 | irq_iommu->irte_mask); | |
c4658b4e WH |
255 | |
256 | return qi_flush_iec(iommu, index, irq_iommu->irte_mask); | |
257 | } | |
258 | ||
f007e99c WH |
259 | /* |
260 | * source validation type | |
261 | */ | |
262 | #define SVT_NO_VERIFY 0x0 /* no verification is required */ | |
25985edc | 263 | #define SVT_VERIFY_SID_SQ 0x1 /* verify using SID and SQ fields */ |
f007e99c WH |
264 | #define SVT_VERIFY_BUS 0x2 /* verify bus of request-id */ |
265 | ||
266 | /* | |
267 | * source-id qualifier | |
268 | */ | |
269 | #define SQ_ALL_16 0x0 /* verify all 16 bits of request-id */ | |
270 | #define SQ_13_IGNORE_1 0x1 /* verify most significant 13 bits, ignore | |
271 | * the third least significant bit | |
272 | */ | |
273 | #define SQ_13_IGNORE_2 0x2 /* verify most significant 13 bits, ignore | |
274 | * the second and third least significant bits | |
275 | */ | |
276 | #define SQ_13_IGNORE_3 0x3 /* verify most significant 13 bits, ignore | |
277 | * the least three significant bits | |
278 | */ | |
279 | ||
280 | /* | |
281 | * set SVT, SQ and SID fields of irte to verify | |
282 | * source ids of interrupt requests | |
283 | */ | |
284 | static void set_irte_sid(struct irte *irte, unsigned int svt, | |
285 | unsigned int sq, unsigned int sid) | |
286 | { | |
d1423d56 CW |
287 | if (disable_sourceid_checking) |
288 | svt = SVT_NO_VERIFY; | |
f007e99c WH |
289 | irte->svt = svt; |
290 | irte->sq = sq; | |
291 | irte->sid = sid; | |
292 | } | |
293 | ||
263b5e86 | 294 | static int set_ioapic_sid(struct irte *irte, int apic) |
f007e99c WH |
295 | { |
296 | int i; | |
297 | u16 sid = 0; | |
298 | ||
299 | if (!irte) | |
300 | return -1; | |
301 | ||
3a5670e8 | 302 | down_read(&dmar_global_lock); |
f007e99c | 303 | for (i = 0; i < MAX_IO_APICS; i++) { |
a7a3dad9 | 304 | if (ir_ioapic[i].iommu && ir_ioapic[i].id == apic) { |
f007e99c WH |
305 | sid = (ir_ioapic[i].bus << 8) | ir_ioapic[i].devfn; |
306 | break; | |
307 | } | |
308 | } | |
3a5670e8 | 309 | up_read(&dmar_global_lock); |
f007e99c WH |
310 | |
311 | if (sid == 0) { | |
9f10e5bf | 312 | pr_warn("Failed to set source-id of IOAPIC (%d)\n", apic); |
f007e99c WH |
313 | return -1; |
314 | } | |
315 | ||
2fe2c602 | 316 | set_irte_sid(irte, SVT_VERIFY_SID_SQ, SQ_ALL_16, sid); |
f007e99c WH |
317 | |
318 | return 0; | |
319 | } | |
320 | ||
263b5e86 | 321 | static int set_hpet_sid(struct irte *irte, u8 id) |
20f3097b SS |
322 | { |
323 | int i; | |
324 | u16 sid = 0; | |
325 | ||
326 | if (!irte) | |
327 | return -1; | |
328 | ||
3a5670e8 | 329 | down_read(&dmar_global_lock); |
20f3097b | 330 | for (i = 0; i < MAX_HPET_TBS; i++) { |
a7a3dad9 | 331 | if (ir_hpet[i].iommu && ir_hpet[i].id == id) { |
20f3097b SS |
332 | sid = (ir_hpet[i].bus << 8) | ir_hpet[i].devfn; |
333 | break; | |
334 | } | |
335 | } | |
3a5670e8 | 336 | up_read(&dmar_global_lock); |
20f3097b SS |
337 | |
338 | if (sid == 0) { | |
9f10e5bf | 339 | pr_warn("Failed to set source-id of HPET block (%d)\n", id); |
20f3097b SS |
340 | return -1; |
341 | } | |
342 | ||
343 | /* | |
344 | * Should really use SQ_ALL_16. Some platforms are broken. | |
345 | * While we figure out the right quirks for these broken platforms, use | |
346 | * SQ_13_IGNORE_3 for now. | |
347 | */ | |
348 | set_irte_sid(irte, SVT_VERIFY_SID_SQ, SQ_13_IGNORE_3, sid); | |
349 | ||
350 | return 0; | |
351 | } | |
352 | ||
579305f7 AW |
353 | struct set_msi_sid_data { |
354 | struct pci_dev *pdev; | |
355 | u16 alias; | |
356 | }; | |
357 | ||
358 | static int set_msi_sid_cb(struct pci_dev *pdev, u16 alias, void *opaque) | |
359 | { | |
360 | struct set_msi_sid_data *data = opaque; | |
361 | ||
362 | data->pdev = pdev; | |
363 | data->alias = alias; | |
364 | ||
365 | return 0; | |
366 | } | |
367 | ||
263b5e86 | 368 | static int set_msi_sid(struct irte *irte, struct pci_dev *dev) |
f007e99c | 369 | { |
579305f7 | 370 | struct set_msi_sid_data data; |
f007e99c WH |
371 | |
372 | if (!irte || !dev) | |
373 | return -1; | |
374 | ||
579305f7 | 375 | pci_for_each_dma_alias(dev, set_msi_sid_cb, &data); |
f007e99c | 376 | |
579305f7 AW |
377 | /* |
378 | * DMA alias provides us with a PCI device and alias. The only case | |
379 | * where the it will return an alias on a different bus than the | |
380 | * device is the case of a PCIe-to-PCI bridge, where the alias is for | |
381 | * the subordinate bus. In this case we can only verify the bus. | |
382 | * | |
383 | * If the alias device is on a different bus than our source device | |
384 | * then we have a topology based alias, use it. | |
385 | * | |
386 | * Otherwise, the alias is for a device DMA quirk and we cannot | |
387 | * assume that MSI uses the same requester ID. Therefore use the | |
388 | * original device. | |
389 | */ | |
390 | if (PCI_BUS_NUM(data.alias) != data.pdev->bus->number) | |
391 | set_irte_sid(irte, SVT_VERIFY_BUS, SQ_ALL_16, | |
392 | PCI_DEVID(PCI_BUS_NUM(data.alias), | |
393 | dev->bus->number)); | |
394 | else if (data.pdev->bus->number != dev->bus->number) | |
395 | set_irte_sid(irte, SVT_VERIFY_SID_SQ, SQ_ALL_16, data.alias); | |
396 | else | |
397 | set_irte_sid(irte, SVT_VERIFY_SID_SQ, SQ_ALL_16, | |
398 | PCI_DEVID(dev->bus->number, dev->devfn)); | |
f007e99c WH |
399 | |
400 | return 0; | |
401 | } | |
402 | ||
af3b358e JR |
403 | static int iommu_load_old_irte(struct intel_iommu *iommu) |
404 | { | |
dfddb969 | 405 | struct irte *old_ir_table; |
af3b358e | 406 | phys_addr_t irt_phys; |
7c3c9876 | 407 | unsigned int i; |
af3b358e JR |
408 | size_t size; |
409 | u64 irta; | |
410 | ||
af3b358e JR |
411 | /* Check whether the old ir-table has the same size as ours */ |
412 | irta = dmar_readq(iommu->reg + DMAR_IRTA_REG); | |
413 | if ((irta & INTR_REMAP_TABLE_REG_SIZE_MASK) | |
414 | != INTR_REMAP_TABLE_REG_SIZE) | |
415 | return -EINVAL; | |
416 | ||
417 | irt_phys = irta & VTD_PAGE_MASK; | |
418 | size = INTR_REMAP_TABLE_ENTRIES*sizeof(struct irte); | |
419 | ||
420 | /* Map the old IR table */ | |
dfddb969 | 421 | old_ir_table = memremap(irt_phys, size, MEMREMAP_WB); |
af3b358e JR |
422 | if (!old_ir_table) |
423 | return -ENOMEM; | |
424 | ||
425 | /* Copy data over */ | |
dfddb969 | 426 | memcpy(iommu->ir_table->base, old_ir_table, size); |
af3b358e JR |
427 | |
428 | __iommu_flush_cache(iommu, iommu->ir_table->base, size); | |
429 | ||
7c3c9876 JR |
430 | /* |
431 | * Now check the table for used entries and mark those as | |
432 | * allocated in the bitmap | |
433 | */ | |
434 | for (i = 0; i < INTR_REMAP_TABLE_ENTRIES; i++) { | |
435 | if (iommu->ir_table->base[i].present) | |
436 | bitmap_set(iommu->ir_table->bitmap, i, 1); | |
437 | } | |
438 | ||
dfddb969 | 439 | memunmap(old_ir_table); |
50690762 | 440 | |
af3b358e JR |
441 | return 0; |
442 | } | |
443 | ||
444 | ||
95a02e97 | 445 | static void iommu_set_irq_remapping(struct intel_iommu *iommu, int mode) |
2ae21010 | 446 | { |
d4d1c0f3 | 447 | unsigned long flags; |
2ae21010 | 448 | u64 addr; |
c416daa9 | 449 | u32 sts; |
2ae21010 SS |
450 | |
451 | addr = virt_to_phys((void *)iommu->ir_table->base); | |
452 | ||
1f5b3c3f | 453 | raw_spin_lock_irqsave(&iommu->register_lock, flags); |
2ae21010 SS |
454 | |
455 | dmar_writeq(iommu->reg + DMAR_IRTA_REG, | |
456 | (addr) | IR_X2APIC_MODE(mode) | INTR_REMAP_TABLE_REG_SIZE); | |
457 | ||
458 | /* Set interrupt-remapping table pointer */ | |
f63ef690 | 459 | writel(iommu->gcmd | DMA_GCMD_SIRTP, iommu->reg + DMAR_GCMD_REG); |
2ae21010 SS |
460 | |
461 | IOMMU_WAIT_OP(iommu, DMAR_GSTS_REG, | |
462 | readl, (sts & DMA_GSTS_IRTPS), sts); | |
1f5b3c3f | 463 | raw_spin_unlock_irqrestore(&iommu->register_lock, flags); |
2ae21010 SS |
464 | |
465 | /* | |
d4d1c0f3 JR |
466 | * Global invalidation of interrupt entry cache to make sure the |
467 | * hardware uses the new irq remapping table. | |
2ae21010 SS |
468 | */ |
469 | qi_global_iec(iommu); | |
d4d1c0f3 JR |
470 | } |
471 | ||
472 | static void iommu_enable_irq_remapping(struct intel_iommu *iommu) | |
473 | { | |
474 | unsigned long flags; | |
475 | u32 sts; | |
2ae21010 | 476 | |
1f5b3c3f | 477 | raw_spin_lock_irqsave(&iommu->register_lock, flags); |
2ae21010 SS |
478 | |
479 | /* Enable interrupt-remapping */ | |
2ae21010 | 480 | iommu->gcmd |= DMA_GCMD_IRE; |
af8d102f | 481 | iommu->gcmd &= ~DMA_GCMD_CFI; /* Block compatibility-format MSIs */ |
c416daa9 | 482 | writel(iommu->gcmd, iommu->reg + DMAR_GCMD_REG); |
2ae21010 SS |
483 | |
484 | IOMMU_WAIT_OP(iommu, DMAR_GSTS_REG, | |
485 | readl, (sts & DMA_GSTS_IRES), sts); | |
486 | ||
af8d102f AL |
487 | /* |
488 | * With CFI clear in the Global Command register, we should be | |
489 | * protected from dangerous (i.e. compatibility) interrupts | |
490 | * regardless of x2apic status. Check just to be sure. | |
491 | */ | |
492 | if (sts & DMA_GSTS_CFIS) | |
493 | WARN(1, KERN_WARNING | |
494 | "Compatibility-format IRQs enabled despite intr remapping;\n" | |
495 | "you are vulnerable to IRQ injection.\n"); | |
496 | ||
1f5b3c3f | 497 | raw_spin_unlock_irqrestore(&iommu->register_lock, flags); |
2ae21010 SS |
498 | } |
499 | ||
a7a3dad9 | 500 | static int intel_setup_irq_remapping(struct intel_iommu *iommu) |
2ae21010 SS |
501 | { |
502 | struct ir_table *ir_table; | |
503 | struct page *pages; | |
360eb3c5 | 504 | unsigned long *bitmap; |
2ae21010 | 505 | |
a7a3dad9 JL |
506 | if (iommu->ir_table) |
507 | return 0; | |
2ae21010 | 508 | |
e3a981d6 | 509 | ir_table = kzalloc(sizeof(struct ir_table), GFP_KERNEL); |
a7a3dad9 | 510 | if (!ir_table) |
2ae21010 SS |
511 | return -ENOMEM; |
512 | ||
e3a981d6 | 513 | pages = alloc_pages_node(iommu->node, GFP_KERNEL | __GFP_ZERO, |
824cd75b | 514 | INTR_REMAP_PAGE_ORDER); |
2ae21010 | 515 | if (!pages) { |
360eb3c5 JL |
516 | pr_err("IR%d: failed to allocate pages of order %d\n", |
517 | iommu->seq_id, INTR_REMAP_PAGE_ORDER); | |
a7a3dad9 | 518 | goto out_free_table; |
2ae21010 SS |
519 | } |
520 | ||
360eb3c5 JL |
521 | bitmap = kcalloc(BITS_TO_LONGS(INTR_REMAP_TABLE_ENTRIES), |
522 | sizeof(long), GFP_ATOMIC); | |
523 | if (bitmap == NULL) { | |
524 | pr_err("IR%d: failed to allocate bitmap\n", iommu->seq_id); | |
a7a3dad9 | 525 | goto out_free_pages; |
360eb3c5 JL |
526 | } |
527 | ||
b106ee63 JL |
528 | iommu->ir_domain = irq_domain_add_hierarchy(arch_get_ir_parent_domain(), |
529 | 0, INTR_REMAP_TABLE_ENTRIES, | |
530 | NULL, &intel_ir_domain_ops, | |
531 | iommu); | |
532 | if (!iommu->ir_domain) { | |
533 | pr_err("IR%d: failed to allocate irqdomain\n", iommu->seq_id); | |
534 | goto out_free_bitmap; | |
535 | } | |
536 | iommu->ir_msi_domain = arch_create_msi_irq_domain(iommu->ir_domain); | |
537 | ||
2ae21010 | 538 | ir_table->base = page_address(pages); |
360eb3c5 | 539 | ir_table->bitmap = bitmap; |
a7a3dad9 | 540 | iommu->ir_table = ir_table; |
9e4e49df JR |
541 | |
542 | /* | |
543 | * If the queued invalidation is already initialized, | |
544 | * shouldn't disable it. | |
545 | */ | |
546 | if (!iommu->qi) { | |
547 | /* | |
548 | * Clear previous faults. | |
549 | */ | |
550 | dmar_fault(-1, iommu); | |
551 | dmar_disable_qi(iommu); | |
552 | ||
553 | if (dmar_enable_qi(iommu)) { | |
554 | pr_err("Failed to enable queued invalidation\n"); | |
555 | goto out_free_bitmap; | |
556 | } | |
557 | } | |
558 | ||
af3b358e JR |
559 | init_ir_status(iommu); |
560 | ||
561 | if (ir_pre_enabled(iommu)) { | |
8e121884 QZ |
562 | if (!is_kdump_kernel()) { |
563 | pr_warn("IRQ remapping was enabled on %s but we are not in kdump mode\n", | |
564 | iommu->name); | |
565 | clear_ir_pre_enabled(iommu); | |
566 | iommu_disable_irq_remapping(iommu); | |
567 | } else if (iommu_load_old_irte(iommu)) | |
af3b358e JR |
568 | pr_err("Failed to copy IR table for %s from previous kernel\n", |
569 | iommu->name); | |
570 | else | |
571 | pr_info("Copied IR table for %s from previous kernel\n", | |
572 | iommu->name); | |
573 | } | |
574 | ||
d4d1c0f3 JR |
575 | iommu_set_irq_remapping(iommu, eim_mode); |
576 | ||
2ae21010 | 577 | return 0; |
a7a3dad9 | 578 | |
b106ee63 JL |
579 | out_free_bitmap: |
580 | kfree(bitmap); | |
a7a3dad9 JL |
581 | out_free_pages: |
582 | __free_pages(pages, INTR_REMAP_PAGE_ORDER); | |
583 | out_free_table: | |
584 | kfree(ir_table); | |
9e4e49df JR |
585 | |
586 | iommu->ir_table = NULL; | |
587 | ||
a7a3dad9 JL |
588 | return -ENOMEM; |
589 | } | |
590 | ||
591 | static void intel_teardown_irq_remapping(struct intel_iommu *iommu) | |
592 | { | |
593 | if (iommu && iommu->ir_table) { | |
b106ee63 JL |
594 | if (iommu->ir_msi_domain) { |
595 | irq_domain_remove(iommu->ir_msi_domain); | |
596 | iommu->ir_msi_domain = NULL; | |
597 | } | |
598 | if (iommu->ir_domain) { | |
599 | irq_domain_remove(iommu->ir_domain); | |
600 | iommu->ir_domain = NULL; | |
601 | } | |
a7a3dad9 JL |
602 | free_pages((unsigned long)iommu->ir_table->base, |
603 | INTR_REMAP_PAGE_ORDER); | |
604 | kfree(iommu->ir_table->bitmap); | |
605 | kfree(iommu->ir_table); | |
606 | iommu->ir_table = NULL; | |
607 | } | |
2ae21010 SS |
608 | } |
609 | ||
eba67e5d SS |
610 | /* |
611 | * Disable Interrupt Remapping. | |
612 | */ | |
95a02e97 | 613 | static void iommu_disable_irq_remapping(struct intel_iommu *iommu) |
eba67e5d SS |
614 | { |
615 | unsigned long flags; | |
616 | u32 sts; | |
617 | ||
618 | if (!ecap_ir_support(iommu->ecap)) | |
619 | return; | |
620 | ||
b24696bc FY |
621 | /* |
622 | * global invalidation of interrupt entry cache before disabling | |
623 | * interrupt-remapping. | |
624 | */ | |
625 | qi_global_iec(iommu); | |
626 | ||
1f5b3c3f | 627 | raw_spin_lock_irqsave(&iommu->register_lock, flags); |
eba67e5d | 628 | |
fda3bec1 | 629 | sts = readl(iommu->reg + DMAR_GSTS_REG); |
eba67e5d SS |
630 | if (!(sts & DMA_GSTS_IRES)) |
631 | goto end; | |
632 | ||
633 | iommu->gcmd &= ~DMA_GCMD_IRE; | |
634 | writel(iommu->gcmd, iommu->reg + DMAR_GCMD_REG); | |
635 | ||
636 | IOMMU_WAIT_OP(iommu, DMAR_GSTS_REG, | |
637 | readl, !(sts & DMA_GSTS_IRES), sts); | |
638 | ||
639 | end: | |
1f5b3c3f | 640 | raw_spin_unlock_irqrestore(&iommu->register_lock, flags); |
eba67e5d SS |
641 | } |
642 | ||
41750d31 SS |
643 | static int __init dmar_x2apic_optout(void) |
644 | { | |
645 | struct acpi_table_dmar *dmar; | |
646 | dmar = (struct acpi_table_dmar *)dmar_tbl; | |
647 | if (!dmar || no_x2apic_optout) | |
648 | return 0; | |
649 | return dmar->flags & DMAR_X2APIC_OPT_OUT; | |
650 | } | |
651 | ||
11190302 TG |
652 | static void __init intel_cleanup_irq_remapping(void) |
653 | { | |
654 | struct dmar_drhd_unit *drhd; | |
655 | struct intel_iommu *iommu; | |
656 | ||
657 | for_each_iommu(iommu, drhd) { | |
658 | if (ecap_ir_support(iommu->ecap)) { | |
659 | iommu_disable_irq_remapping(iommu); | |
660 | intel_teardown_irq_remapping(iommu); | |
661 | } | |
662 | } | |
663 | ||
664 | if (x2apic_supported()) | |
9f10e5bf | 665 | pr_warn("Failed to enable irq remapping. You are vulnerable to irq-injection attacks.\n"); |
11190302 TG |
666 | } |
667 | ||
668 | static int __init intel_prepare_irq_remapping(void) | |
2ae21010 SS |
669 | { |
670 | struct dmar_drhd_unit *drhd; | |
7c919779 | 671 | struct intel_iommu *iommu; |
23256d0b | 672 | int eim = 0; |
2ae21010 | 673 | |
2966d956 | 674 | if (irq_remap_broken) { |
9f10e5bf | 675 | pr_warn("This system BIOS has enabled interrupt remapping\n" |
2966d956 JL |
676 | "on a chipset that contains an erratum making that\n" |
677 | "feature unstable. To maintain system stability\n" | |
678 | "interrupt remapping is being disabled. Please\n" | |
679 | "contact your BIOS vendor for an update\n"); | |
680 | add_taint(TAINT_FIRMWARE_WORKAROUND, LOCKDEP_STILL_OK); | |
2966d956 JL |
681 | return -ENODEV; |
682 | } | |
683 | ||
11190302 | 684 | if (dmar_table_init() < 0) |
2966d956 JL |
685 | return -ENODEV; |
686 | ||
687 | if (!dmar_ir_support()) | |
688 | return -ENODEV; | |
af8d102f | 689 | |
b61e5e80 | 690 | if (parse_ioapics_under_ir()) { |
9f10e5bf | 691 | pr_info("Not enabling interrupt remapping\n"); |
af8d102f | 692 | goto error; |
e936d077 YS |
693 | } |
694 | ||
69cf1d8a | 695 | /* First make sure all IOMMUs support IRQ remapping */ |
2966d956 | 696 | for_each_iommu(iommu, drhd) |
69cf1d8a JR |
697 | if (!ecap_ir_support(iommu->ecap)) |
698 | goto error; | |
699 | ||
23256d0b JR |
700 | /* Detect remapping mode: lapic or x2apic */ |
701 | if (x2apic_supported()) { | |
702 | eim = !dmar_x2apic_optout(); | |
703 | if (!eim) { | |
704 | pr_info("x2apic is disabled because BIOS sets x2apic opt out bit."); | |
705 | pr_info("Use 'intremap=no_x2apic_optout' to override the BIOS setting.\n"); | |
706 | } | |
707 | } | |
708 | ||
709 | for_each_iommu(iommu, drhd) { | |
710 | if (eim && !ecap_eim_support(iommu->ecap)) { | |
711 | pr_info("%s does not support EIM\n", iommu->name); | |
712 | eim = 0; | |
713 | } | |
714 | } | |
715 | ||
716 | eim_mode = eim; | |
717 | if (eim) | |
718 | pr_info("Queued invalidation will be enabled to support x2apic and Intr-remapping.\n"); | |
719 | ||
9e4e49df JR |
720 | /* Do the initializations early */ |
721 | for_each_iommu(iommu, drhd) { | |
722 | if (intel_setup_irq_remapping(iommu)) { | |
723 | pr_err("Failed to setup irq remapping for %s\n", | |
724 | iommu->name); | |
11190302 | 725 | goto error; |
9e4e49df JR |
726 | } |
727 | } | |
69cf1d8a | 728 | |
11190302 | 729 | return 0; |
2966d956 | 730 | |
11190302 TG |
731 | error: |
732 | intel_cleanup_irq_remapping(); | |
2966d956 | 733 | return -ENODEV; |
11190302 TG |
734 | } |
735 | ||
3d9b98f4 FW |
736 | /* |
737 | * Set Posted-Interrupts capability. | |
738 | */ | |
739 | static inline void set_irq_posting_cap(void) | |
740 | { | |
741 | struct dmar_drhd_unit *drhd; | |
742 | struct intel_iommu *iommu; | |
743 | ||
744 | if (!disable_irq_post) { | |
344cb4e0 FW |
745 | /* |
746 | * If IRTE is in posted format, the 'pda' field goes across the | |
747 | * 64-bit boundary, we need use cmpxchg16b to atomically update | |
748 | * it. We only expose posted-interrupt when X86_FEATURE_CX16 | |
749 | * is supported. Actually, hardware platforms supporting PI | |
750 | * should have X86_FEATURE_CX16 support, this has been confirmed | |
751 | * with Intel hardware guys. | |
752 | */ | |
362f924b | 753 | if (boot_cpu_has(X86_FEATURE_CX16)) |
344cb4e0 | 754 | intel_irq_remap_ops.capability |= 1 << IRQ_POSTING_CAP; |
3d9b98f4 FW |
755 | |
756 | for_each_iommu(iommu, drhd) | |
757 | if (!cap_pi_support(iommu->cap)) { | |
758 | intel_irq_remap_ops.capability &= | |
759 | ~(1 << IRQ_POSTING_CAP); | |
760 | break; | |
761 | } | |
762 | } | |
763 | } | |
764 | ||
11190302 TG |
765 | static int __init intel_enable_irq_remapping(void) |
766 | { | |
767 | struct dmar_drhd_unit *drhd; | |
768 | struct intel_iommu *iommu; | |
2f119c78 | 769 | bool setup = false; |
2ae21010 SS |
770 | |
771 | /* | |
772 | * Setup Interrupt-remapping for all the DRHD's now. | |
773 | */ | |
7c919779 | 774 | for_each_iommu(iommu, drhd) { |
571dbbd4 JR |
775 | if (!ir_pre_enabled(iommu)) |
776 | iommu_enable_irq_remapping(iommu); | |
2f119c78 | 777 | setup = true; |
2ae21010 SS |
778 | } |
779 | ||
780 | if (!setup) | |
781 | goto error; | |
782 | ||
95a02e97 | 783 | irq_remapping_enabled = 1; |
afcc8a40 | 784 | |
3d9b98f4 FW |
785 | set_irq_posting_cap(); |
786 | ||
23256d0b | 787 | pr_info("Enabled IRQ remapping in %s mode\n", eim_mode ? "x2apic" : "xapic"); |
2ae21010 | 788 | |
23256d0b | 789 | return eim_mode ? IRQ_REMAP_X2APIC_MODE : IRQ_REMAP_XAPIC_MODE; |
2ae21010 SS |
790 | |
791 | error: | |
11190302 | 792 | intel_cleanup_irq_remapping(); |
2ae21010 SS |
793 | return -1; |
794 | } | |
ad3ad3f6 | 795 | |
a7a3dad9 JL |
796 | static int ir_parse_one_hpet_scope(struct acpi_dmar_device_scope *scope, |
797 | struct intel_iommu *iommu, | |
798 | struct acpi_dmar_hardware_unit *drhd) | |
20f3097b SS |
799 | { |
800 | struct acpi_dmar_pci_path *path; | |
801 | u8 bus; | |
a7a3dad9 | 802 | int count, free = -1; |
20f3097b SS |
803 | |
804 | bus = scope->bus; | |
805 | path = (struct acpi_dmar_pci_path *)(scope + 1); | |
806 | count = (scope->length - sizeof(struct acpi_dmar_device_scope)) | |
807 | / sizeof(struct acpi_dmar_pci_path); | |
808 | ||
809 | while (--count > 0) { | |
810 | /* | |
811 | * Access PCI directly due to the PCI | |
812 | * subsystem isn't initialized yet. | |
813 | */ | |
fa5f508f | 814 | bus = read_pci_config_byte(bus, path->device, path->function, |
20f3097b SS |
815 | PCI_SECONDARY_BUS); |
816 | path++; | |
817 | } | |
a7a3dad9 JL |
818 | |
819 | for (count = 0; count < MAX_HPET_TBS; count++) { | |
820 | if (ir_hpet[count].iommu == iommu && | |
821 | ir_hpet[count].id == scope->enumeration_id) | |
822 | return 0; | |
823 | else if (ir_hpet[count].iommu == NULL && free == -1) | |
824 | free = count; | |
825 | } | |
826 | if (free == -1) { | |
827 | pr_warn("Exceeded Max HPET blocks\n"); | |
828 | return -ENOSPC; | |
829 | } | |
830 | ||
831 | ir_hpet[free].iommu = iommu; | |
832 | ir_hpet[free].id = scope->enumeration_id; | |
833 | ir_hpet[free].bus = bus; | |
834 | ir_hpet[free].devfn = PCI_DEVFN(path->device, path->function); | |
835 | pr_info("HPET id %d under DRHD base 0x%Lx\n", | |
836 | scope->enumeration_id, drhd->address); | |
837 | ||
838 | return 0; | |
20f3097b SS |
839 | } |
840 | ||
a7a3dad9 JL |
841 | static int ir_parse_one_ioapic_scope(struct acpi_dmar_device_scope *scope, |
842 | struct intel_iommu *iommu, | |
843 | struct acpi_dmar_hardware_unit *drhd) | |
f007e99c WH |
844 | { |
845 | struct acpi_dmar_pci_path *path; | |
846 | u8 bus; | |
a7a3dad9 | 847 | int count, free = -1; |
f007e99c WH |
848 | |
849 | bus = scope->bus; | |
850 | path = (struct acpi_dmar_pci_path *)(scope + 1); | |
851 | count = (scope->length - sizeof(struct acpi_dmar_device_scope)) | |
852 | / sizeof(struct acpi_dmar_pci_path); | |
853 | ||
854 | while (--count > 0) { | |
855 | /* | |
856 | * Access PCI directly due to the PCI | |
857 | * subsystem isn't initialized yet. | |
858 | */ | |
fa5f508f | 859 | bus = read_pci_config_byte(bus, path->device, path->function, |
f007e99c WH |
860 | PCI_SECONDARY_BUS); |
861 | path++; | |
862 | } | |
863 | ||
a7a3dad9 JL |
864 | for (count = 0; count < MAX_IO_APICS; count++) { |
865 | if (ir_ioapic[count].iommu == iommu && | |
866 | ir_ioapic[count].id == scope->enumeration_id) | |
867 | return 0; | |
868 | else if (ir_ioapic[count].iommu == NULL && free == -1) | |
869 | free = count; | |
870 | } | |
871 | if (free == -1) { | |
872 | pr_warn("Exceeded Max IO APICS\n"); | |
873 | return -ENOSPC; | |
874 | } | |
875 | ||
876 | ir_ioapic[free].bus = bus; | |
877 | ir_ioapic[free].devfn = PCI_DEVFN(path->device, path->function); | |
878 | ir_ioapic[free].iommu = iommu; | |
879 | ir_ioapic[free].id = scope->enumeration_id; | |
880 | pr_info("IOAPIC id %d under DRHD base 0x%Lx IOMMU %d\n", | |
881 | scope->enumeration_id, drhd->address, iommu->seq_id); | |
882 | ||
883 | return 0; | |
f007e99c WH |
884 | } |
885 | ||
20f3097b SS |
886 | static int ir_parse_ioapic_hpet_scope(struct acpi_dmar_header *header, |
887 | struct intel_iommu *iommu) | |
ad3ad3f6 | 888 | { |
a7a3dad9 | 889 | int ret = 0; |
ad3ad3f6 SS |
890 | struct acpi_dmar_hardware_unit *drhd; |
891 | struct acpi_dmar_device_scope *scope; | |
892 | void *start, *end; | |
893 | ||
894 | drhd = (struct acpi_dmar_hardware_unit *)header; | |
ad3ad3f6 SS |
895 | start = (void *)(drhd + 1); |
896 | end = ((void *)drhd) + header->length; | |
897 | ||
a7a3dad9 | 898 | while (start < end && ret == 0) { |
ad3ad3f6 | 899 | scope = start; |
a7a3dad9 JL |
900 | if (scope->entry_type == ACPI_DMAR_SCOPE_TYPE_IOAPIC) |
901 | ret = ir_parse_one_ioapic_scope(scope, iommu, drhd); | |
902 | else if (scope->entry_type == ACPI_DMAR_SCOPE_TYPE_HPET) | |
903 | ret = ir_parse_one_hpet_scope(scope, iommu, drhd); | |
904 | start += scope->length; | |
905 | } | |
ad3ad3f6 | 906 | |
a7a3dad9 JL |
907 | return ret; |
908 | } | |
20f3097b | 909 | |
a7a3dad9 JL |
910 | static void ir_remove_ioapic_hpet_scope(struct intel_iommu *iommu) |
911 | { | |
912 | int i; | |
20f3097b | 913 | |
a7a3dad9 JL |
914 | for (i = 0; i < MAX_HPET_TBS; i++) |
915 | if (ir_hpet[i].iommu == iommu) | |
916 | ir_hpet[i].iommu = NULL; | |
ad3ad3f6 | 917 | |
a7a3dad9 JL |
918 | for (i = 0; i < MAX_IO_APICS; i++) |
919 | if (ir_ioapic[i].iommu == iommu) | |
920 | ir_ioapic[i].iommu = NULL; | |
ad3ad3f6 SS |
921 | } |
922 | ||
923 | /* | |
924 | * Finds the assocaition between IOAPIC's and its Interrupt-remapping | |
925 | * hardware unit. | |
926 | */ | |
694835dc | 927 | static int __init parse_ioapics_under_ir(void) |
ad3ad3f6 SS |
928 | { |
929 | struct dmar_drhd_unit *drhd; | |
7c919779 | 930 | struct intel_iommu *iommu; |
2f119c78 | 931 | bool ir_supported = false; |
32ab31e0 | 932 | int ioapic_idx; |
ad3ad3f6 | 933 | |
66ef950d JR |
934 | for_each_iommu(iommu, drhd) { |
935 | int ret; | |
ad3ad3f6 | 936 | |
66ef950d JR |
937 | if (!ecap_ir_support(iommu->ecap)) |
938 | continue; | |
939 | ||
940 | ret = ir_parse_ioapic_hpet_scope(drhd->hdr, iommu); | |
941 | if (ret) | |
942 | return ret; | |
943 | ||
944 | ir_supported = true; | |
945 | } | |
ad3ad3f6 | 946 | |
32ab31e0 | 947 | if (!ir_supported) |
a13c8f27 | 948 | return -ENODEV; |
32ab31e0 SF |
949 | |
950 | for (ioapic_idx = 0; ioapic_idx < nr_ioapics; ioapic_idx++) { | |
951 | int ioapic_id = mpc_ioapic_id(ioapic_idx); | |
952 | if (!map_ioapic_to_ir(ioapic_id)) { | |
953 | pr_err(FW_BUG "ioapic %d has no mapping iommu, " | |
954 | "interrupt remapping will be disabled\n", | |
955 | ioapic_id); | |
956 | return -1; | |
957 | } | |
ad3ad3f6 SS |
958 | } |
959 | ||
a13c8f27 | 960 | return 0; |
ad3ad3f6 | 961 | } |
b24696bc | 962 | |
6a7885c4 | 963 | static int __init ir_dev_scope_init(void) |
c2c7286a | 964 | { |
3a5670e8 JL |
965 | int ret; |
966 | ||
95a02e97 | 967 | if (!irq_remapping_enabled) |
c2c7286a SS |
968 | return 0; |
969 | ||
3a5670e8 JL |
970 | down_write(&dmar_global_lock); |
971 | ret = dmar_dev_scope_init(); | |
972 | up_write(&dmar_global_lock); | |
973 | ||
974 | return ret; | |
c2c7286a SS |
975 | } |
976 | rootfs_initcall(ir_dev_scope_init); | |
977 | ||
95a02e97 | 978 | static void disable_irq_remapping(void) |
b24696bc FY |
979 | { |
980 | struct dmar_drhd_unit *drhd; | |
981 | struct intel_iommu *iommu = NULL; | |
982 | ||
983 | /* | |
984 | * Disable Interrupt-remapping for all the DRHD's now. | |
985 | */ | |
986 | for_each_iommu(iommu, drhd) { | |
987 | if (!ecap_ir_support(iommu->ecap)) | |
988 | continue; | |
989 | ||
95a02e97 | 990 | iommu_disable_irq_remapping(iommu); |
b24696bc | 991 | } |
3d9b98f4 FW |
992 | |
993 | /* | |
994 | * Clear Posted-Interrupts capability. | |
995 | */ | |
996 | if (!disable_irq_post) | |
997 | intel_irq_remap_ops.capability &= ~(1 << IRQ_POSTING_CAP); | |
b24696bc FY |
998 | } |
999 | ||
95a02e97 | 1000 | static int reenable_irq_remapping(int eim) |
b24696bc FY |
1001 | { |
1002 | struct dmar_drhd_unit *drhd; | |
2f119c78 | 1003 | bool setup = false; |
b24696bc FY |
1004 | struct intel_iommu *iommu = NULL; |
1005 | ||
1006 | for_each_iommu(iommu, drhd) | |
1007 | if (iommu->qi) | |
1008 | dmar_reenable_qi(iommu); | |
1009 | ||
1010 | /* | |
1011 | * Setup Interrupt-remapping for all the DRHD's now. | |
1012 | */ | |
1013 | for_each_iommu(iommu, drhd) { | |
1014 | if (!ecap_ir_support(iommu->ecap)) | |
1015 | continue; | |
1016 | ||
1017 | /* Set up interrupt remapping for iommu.*/ | |
95a02e97 | 1018 | iommu_set_irq_remapping(iommu, eim); |
d4d1c0f3 | 1019 | iommu_enable_irq_remapping(iommu); |
2f119c78 | 1020 | setup = true; |
b24696bc FY |
1021 | } |
1022 | ||
1023 | if (!setup) | |
1024 | goto error; | |
1025 | ||
3d9b98f4 FW |
1026 | set_irq_posting_cap(); |
1027 | ||
b24696bc FY |
1028 | return 0; |
1029 | ||
1030 | error: | |
1031 | /* | |
1032 | * handle error condition gracefully here! | |
1033 | */ | |
1034 | return -1; | |
1035 | } | |
1036 | ||
3c6e5675 | 1037 | static void prepare_irte(struct irte *irte, int vector, unsigned int dest) |
0c3f173a JR |
1038 | { |
1039 | memset(irte, 0, sizeof(*irte)); | |
1040 | ||
1041 | irte->present = 1; | |
1042 | irte->dst_mode = apic->irq_dest_mode; | |
1043 | /* | |
1044 | * Trigger mode in the IRTE will always be edge, and for IO-APIC, the | |
1045 | * actual level or edge trigger will be setup in the IO-APIC | |
1046 | * RTE. This will help simplify level triggered irq migration. | |
1047 | * For more details, see the comments (in io_apic.c) explainig IO-APIC | |
1048 | * irq migration in the presence of interrupt-remapping. | |
1049 | */ | |
1050 | irte->trigger_mode = 0; | |
1051 | irte->dlvry_mode = apic->irq_delivery_mode; | |
1052 | irte->vector = vector; | |
1053 | irte->dest_id = IRTE_DEST(dest); | |
1054 | irte->redir_hint = 1; | |
1055 | } | |
1056 | ||
b106ee63 JL |
1057 | static struct irq_domain *intel_get_ir_irq_domain(struct irq_alloc_info *info) |
1058 | { | |
1059 | struct intel_iommu *iommu = NULL; | |
1060 | ||
1061 | if (!info) | |
1062 | return NULL; | |
1063 | ||
1064 | switch (info->type) { | |
1065 | case X86_IRQ_ALLOC_TYPE_IOAPIC: | |
1066 | iommu = map_ioapic_to_ir(info->ioapic_id); | |
1067 | break; | |
1068 | case X86_IRQ_ALLOC_TYPE_HPET: | |
1069 | iommu = map_hpet_to_ir(info->hpet_id); | |
1070 | break; | |
1071 | case X86_IRQ_ALLOC_TYPE_MSI: | |
1072 | case X86_IRQ_ALLOC_TYPE_MSIX: | |
1073 | iommu = map_dev_to_ir(info->msi_dev); | |
1074 | break; | |
1075 | default: | |
1076 | BUG_ON(1); | |
1077 | break; | |
1078 | } | |
1079 | ||
1080 | return iommu ? iommu->ir_domain : NULL; | |
1081 | } | |
1082 | ||
1083 | static struct irq_domain *intel_get_irq_domain(struct irq_alloc_info *info) | |
1084 | { | |
1085 | struct intel_iommu *iommu; | |
1086 | ||
1087 | if (!info) | |
1088 | return NULL; | |
1089 | ||
1090 | switch (info->type) { | |
1091 | case X86_IRQ_ALLOC_TYPE_MSI: | |
1092 | case X86_IRQ_ALLOC_TYPE_MSIX: | |
1093 | iommu = map_dev_to_ir(info->msi_dev); | |
1094 | if (iommu) | |
1095 | return iommu->ir_msi_domain; | |
1096 | break; | |
1097 | default: | |
1098 | break; | |
1099 | } | |
1100 | ||
1101 | return NULL; | |
1102 | } | |
1103 | ||
736baef4 | 1104 | struct irq_remap_ops intel_irq_remap_ops = { |
11190302 | 1105 | .prepare = intel_prepare_irq_remapping, |
95a02e97 SS |
1106 | .enable = intel_enable_irq_remapping, |
1107 | .disable = disable_irq_remapping, | |
1108 | .reenable = reenable_irq_remapping, | |
4f3d8b67 | 1109 | .enable_faulting = enable_drhd_fault_handling, |
b106ee63 JL |
1110 | .get_ir_irq_domain = intel_get_ir_irq_domain, |
1111 | .get_irq_domain = intel_get_irq_domain, | |
1112 | }; | |
1113 | ||
1114 | /* | |
1115 | * Migrate the IO-APIC irq in the presence of intr-remapping. | |
1116 | * | |
1117 | * For both level and edge triggered, irq migration is a simple atomic | |
1118 | * update(of vector and cpu destination) of IRTE and flush the hardware cache. | |
1119 | * | |
1120 | * For level triggered, we eliminate the io-apic RTE modification (with the | |
1121 | * updated vector information), by using a virtual vector (io-apic pin number). | |
1122 | * Real vector that is used for interrupting cpu will be coming from | |
1123 | * the interrupt-remapping table entry. | |
1124 | * | |
1125 | * As the migration is a simple atomic update of IRTE, the same mechanism | |
1126 | * is used to migrate MSI irq's in the presence of interrupt-remapping. | |
1127 | */ | |
1128 | static int | |
1129 | intel_ir_set_affinity(struct irq_data *data, const struct cpumask *mask, | |
1130 | bool force) | |
1131 | { | |
1132 | struct intel_ir_data *ir_data = data->chip_data; | |
1133 | struct irte *irte = &ir_data->irte_entry; | |
1134 | struct irq_cfg *cfg = irqd_cfg(data); | |
1135 | struct irq_data *parent = data->parent_data; | |
1136 | int ret; | |
1137 | ||
1138 | ret = parent->chip->irq_set_affinity(parent, mask, force); | |
1139 | if (ret < 0 || ret == IRQ_SET_MASK_OK_DONE) | |
1140 | return ret; | |
1141 | ||
1142 | /* | |
1143 | * Atomically updates the IRTE with the new destination, vector | |
1144 | * and flushes the interrupt entry cache. | |
1145 | */ | |
1146 | irte->vector = cfg->vector; | |
1147 | irte->dest_id = IRTE_DEST(cfg->dest_apicid); | |
d75f152f FW |
1148 | |
1149 | /* Update the hardware only if the interrupt is in remapped mode. */ | |
1150 | if (ir_data->irq_2_iommu.mode == IRQ_REMAPPING) | |
1151 | modify_irte(&ir_data->irq_2_iommu, irte); | |
b106ee63 JL |
1152 | |
1153 | /* | |
1154 | * After this point, all the interrupts will start arriving | |
1155 | * at the new destination. So, time to cleanup the previous | |
1156 | * vector allocation. | |
1157 | */ | |
c6c2002b | 1158 | send_cleanup_vector(cfg); |
b106ee63 JL |
1159 | |
1160 | return IRQ_SET_MASK_OK_DONE; | |
1161 | } | |
1162 | ||
1163 | static void intel_ir_compose_msi_msg(struct irq_data *irq_data, | |
1164 | struct msi_msg *msg) | |
1165 | { | |
1166 | struct intel_ir_data *ir_data = irq_data->chip_data; | |
1167 | ||
1168 | *msg = ir_data->msi_entry; | |
1169 | } | |
1170 | ||
8541186f FW |
1171 | static int intel_ir_set_vcpu_affinity(struct irq_data *data, void *info) |
1172 | { | |
1173 | struct intel_ir_data *ir_data = data->chip_data; | |
1174 | struct vcpu_data *vcpu_pi_info = info; | |
1175 | ||
1176 | /* stop posting interrupts, back to remapping mode */ | |
1177 | if (!vcpu_pi_info) { | |
1178 | modify_irte(&ir_data->irq_2_iommu, &ir_data->irte_entry); | |
1179 | } else { | |
1180 | struct irte irte_pi; | |
1181 | ||
1182 | /* | |
1183 | * We are not caching the posted interrupt entry. We | |
1184 | * copy the data from the remapped entry and modify | |
1185 | * the fields which are relevant for posted mode. The | |
1186 | * cached remapped entry is used for switching back to | |
1187 | * remapped mode. | |
1188 | */ | |
1189 | memset(&irte_pi, 0, sizeof(irte_pi)); | |
1190 | dmar_copy_shared_irte(&irte_pi, &ir_data->irte_entry); | |
1191 | ||
1192 | /* Update the posted mode fields */ | |
1193 | irte_pi.p_pst = 1; | |
1194 | irte_pi.p_urgent = 0; | |
1195 | irte_pi.p_vector = vcpu_pi_info->vector; | |
1196 | irte_pi.pda_l = (vcpu_pi_info->pi_desc_addr >> | |
1197 | (32 - PDA_LOW_BIT)) & ~(-1UL << PDA_LOW_BIT); | |
1198 | irte_pi.pda_h = (vcpu_pi_info->pi_desc_addr >> 32) & | |
1199 | ~(-1UL << PDA_HIGH_BIT); | |
1200 | ||
1201 | modify_irte(&ir_data->irq_2_iommu, &irte_pi); | |
1202 | } | |
1203 | ||
1204 | return 0; | |
1205 | } | |
1206 | ||
b106ee63 JL |
1207 | static struct irq_chip intel_ir_chip = { |
1208 | .irq_ack = ir_ack_apic_edge, | |
1209 | .irq_set_affinity = intel_ir_set_affinity, | |
1210 | .irq_compose_msi_msg = intel_ir_compose_msi_msg, | |
8541186f | 1211 | .irq_set_vcpu_affinity = intel_ir_set_vcpu_affinity, |
b106ee63 JL |
1212 | }; |
1213 | ||
1214 | static void intel_irq_remapping_prepare_irte(struct intel_ir_data *data, | |
1215 | struct irq_cfg *irq_cfg, | |
1216 | struct irq_alloc_info *info, | |
1217 | int index, int sub_handle) | |
1218 | { | |
1219 | struct IR_IO_APIC_route_entry *entry; | |
1220 | struct irte *irte = &data->irte_entry; | |
1221 | struct msi_msg *msg = &data->msi_entry; | |
1222 | ||
1223 | prepare_irte(irte, irq_cfg->vector, irq_cfg->dest_apicid); | |
1224 | switch (info->type) { | |
1225 | case X86_IRQ_ALLOC_TYPE_IOAPIC: | |
1226 | /* Set source-id of interrupt request */ | |
1227 | set_ioapic_sid(irte, info->ioapic_id); | |
1228 | apic_printk(APIC_VERBOSE, KERN_DEBUG "IOAPIC[%d]: Set IRTE entry (P:%d FPD:%d Dst_Mode:%d Redir_hint:%d Trig_Mode:%d Dlvry_Mode:%X Avail:%X Vector:%02X Dest:%08X SID:%04X SQ:%X SVT:%X)\n", | |
1229 | info->ioapic_id, irte->present, irte->fpd, | |
1230 | irte->dst_mode, irte->redir_hint, | |
1231 | irte->trigger_mode, irte->dlvry_mode, | |
1232 | irte->avail, irte->vector, irte->dest_id, | |
1233 | irte->sid, irte->sq, irte->svt); | |
1234 | ||
1235 | entry = (struct IR_IO_APIC_route_entry *)info->ioapic_entry; | |
1236 | info->ioapic_entry = NULL; | |
1237 | memset(entry, 0, sizeof(*entry)); | |
1238 | entry->index2 = (index >> 15) & 0x1; | |
1239 | entry->zero = 0; | |
1240 | entry->format = 1; | |
1241 | entry->index = (index & 0x7fff); | |
1242 | /* | |
1243 | * IO-APIC RTE will be configured with virtual vector. | |
1244 | * irq handler will do the explicit EOI to the io-apic. | |
1245 | */ | |
1246 | entry->vector = info->ioapic_pin; | |
1247 | entry->mask = 0; /* enable IRQ */ | |
1248 | entry->trigger = info->ioapic_trigger; | |
1249 | entry->polarity = info->ioapic_polarity; | |
1250 | if (info->ioapic_trigger) | |
1251 | entry->mask = 1; /* Mask level triggered irqs. */ | |
1252 | break; | |
1253 | ||
1254 | case X86_IRQ_ALLOC_TYPE_HPET: | |
1255 | case X86_IRQ_ALLOC_TYPE_MSI: | |
1256 | case X86_IRQ_ALLOC_TYPE_MSIX: | |
1257 | if (info->type == X86_IRQ_ALLOC_TYPE_HPET) | |
1258 | set_hpet_sid(irte, info->hpet_id); | |
1259 | else | |
1260 | set_msi_sid(irte, info->msi_dev); | |
1261 | ||
1262 | msg->address_hi = MSI_ADDR_BASE_HI; | |
1263 | msg->data = sub_handle; | |
1264 | msg->address_lo = MSI_ADDR_BASE_LO | MSI_ADDR_IR_EXT_INT | | |
1265 | MSI_ADDR_IR_SHV | | |
1266 | MSI_ADDR_IR_INDEX1(index) | | |
1267 | MSI_ADDR_IR_INDEX2(index); | |
1268 | break; | |
1269 | ||
1270 | default: | |
1271 | BUG_ON(1); | |
1272 | break; | |
1273 | } | |
1274 | } | |
1275 | ||
1276 | static void intel_free_irq_resources(struct irq_domain *domain, | |
1277 | unsigned int virq, unsigned int nr_irqs) | |
1278 | { | |
1279 | struct irq_data *irq_data; | |
1280 | struct intel_ir_data *data; | |
1281 | struct irq_2_iommu *irq_iommu; | |
1282 | unsigned long flags; | |
1283 | int i; | |
b106ee63 JL |
1284 | for (i = 0; i < nr_irqs; i++) { |
1285 | irq_data = irq_domain_get_irq_data(domain, virq + i); | |
1286 | if (irq_data && irq_data->chip_data) { | |
1287 | data = irq_data->chip_data; | |
1288 | irq_iommu = &data->irq_2_iommu; | |
1289 | raw_spin_lock_irqsave(&irq_2_ir_lock, flags); | |
1290 | clear_entries(irq_iommu); | |
1291 | raw_spin_unlock_irqrestore(&irq_2_ir_lock, flags); | |
1292 | irq_domain_reset_irq_data(irq_data); | |
1293 | kfree(data); | |
1294 | } | |
1295 | } | |
1296 | } | |
1297 | ||
1298 | static int intel_irq_remapping_alloc(struct irq_domain *domain, | |
1299 | unsigned int virq, unsigned int nr_irqs, | |
1300 | void *arg) | |
1301 | { | |
1302 | struct intel_iommu *iommu = domain->host_data; | |
1303 | struct irq_alloc_info *info = arg; | |
9d4c0313 | 1304 | struct intel_ir_data *data, *ird; |
b106ee63 JL |
1305 | struct irq_data *irq_data; |
1306 | struct irq_cfg *irq_cfg; | |
1307 | int i, ret, index; | |
1308 | ||
1309 | if (!info || !iommu) | |
1310 | return -EINVAL; | |
1311 | if (nr_irqs > 1 && info->type != X86_IRQ_ALLOC_TYPE_MSI && | |
1312 | info->type != X86_IRQ_ALLOC_TYPE_MSIX) | |
1313 | return -EINVAL; | |
1314 | ||
1315 | /* | |
1316 | * With IRQ remapping enabled, don't need contiguous CPU vectors | |
1317 | * to support multiple MSI interrupts. | |
1318 | */ | |
1319 | if (info->type == X86_IRQ_ALLOC_TYPE_MSI) | |
1320 | info->flags &= ~X86_IRQ_ALLOC_CONTIGUOUS_VECTORS; | |
1321 | ||
1322 | ret = irq_domain_alloc_irqs_parent(domain, virq, nr_irqs, arg); | |
1323 | if (ret < 0) | |
1324 | return ret; | |
1325 | ||
1326 | ret = -ENOMEM; | |
1327 | data = kzalloc(sizeof(*data), GFP_KERNEL); | |
1328 | if (!data) | |
1329 | goto out_free_parent; | |
1330 | ||
1331 | down_read(&dmar_global_lock); | |
1332 | index = alloc_irte(iommu, virq, &data->irq_2_iommu, nr_irqs); | |
1333 | up_read(&dmar_global_lock); | |
1334 | if (index < 0) { | |
1335 | pr_warn("Failed to allocate IRTE\n"); | |
1336 | kfree(data); | |
1337 | goto out_free_parent; | |
1338 | } | |
1339 | ||
1340 | for (i = 0; i < nr_irqs; i++) { | |
1341 | irq_data = irq_domain_get_irq_data(domain, virq + i); | |
1342 | irq_cfg = irqd_cfg(irq_data); | |
1343 | if (!irq_data || !irq_cfg) { | |
1344 | ret = -EINVAL; | |
1345 | goto out_free_data; | |
1346 | } | |
1347 | ||
1348 | if (i > 0) { | |
9d4c0313 TG |
1349 | ird = kzalloc(sizeof(*ird), GFP_KERNEL); |
1350 | if (!ird) | |
b106ee63 | 1351 | goto out_free_data; |
9d4c0313 TG |
1352 | /* Initialize the common data */ |
1353 | ird->irq_2_iommu = data->irq_2_iommu; | |
1354 | ird->irq_2_iommu.sub_handle = i; | |
1355 | } else { | |
1356 | ird = data; | |
b106ee63 | 1357 | } |
9d4c0313 | 1358 | |
b106ee63 | 1359 | irq_data->hwirq = (index << 16) + i; |
9d4c0313 | 1360 | irq_data->chip_data = ird; |
b106ee63 | 1361 | irq_data->chip = &intel_ir_chip; |
9d4c0313 | 1362 | intel_irq_remapping_prepare_irte(ird, irq_cfg, info, index, i); |
b106ee63 JL |
1363 | irq_set_status_flags(virq + i, IRQ_MOVE_PCNTXT); |
1364 | } | |
1365 | return 0; | |
1366 | ||
1367 | out_free_data: | |
1368 | intel_free_irq_resources(domain, virq, i); | |
1369 | out_free_parent: | |
1370 | irq_domain_free_irqs_common(domain, virq, nr_irqs); | |
1371 | return ret; | |
1372 | } | |
1373 | ||
1374 | static void intel_irq_remapping_free(struct irq_domain *domain, | |
1375 | unsigned int virq, unsigned int nr_irqs) | |
1376 | { | |
1377 | intel_free_irq_resources(domain, virq, nr_irqs); | |
1378 | irq_domain_free_irqs_common(domain, virq, nr_irqs); | |
1379 | } | |
1380 | ||
1381 | static void intel_irq_remapping_activate(struct irq_domain *domain, | |
1382 | struct irq_data *irq_data) | |
1383 | { | |
1384 | struct intel_ir_data *data = irq_data->chip_data; | |
1385 | ||
1386 | modify_irte(&data->irq_2_iommu, &data->irte_entry); | |
1387 | } | |
1388 | ||
1389 | static void intel_irq_remapping_deactivate(struct irq_domain *domain, | |
1390 | struct irq_data *irq_data) | |
1391 | { | |
1392 | struct intel_ir_data *data = irq_data->chip_data; | |
1393 | struct irte entry; | |
1394 | ||
1395 | memset(&entry, 0, sizeof(entry)); | |
1396 | modify_irte(&data->irq_2_iommu, &entry); | |
1397 | } | |
1398 | ||
1399 | static struct irq_domain_ops intel_ir_domain_ops = { | |
1400 | .alloc = intel_irq_remapping_alloc, | |
1401 | .free = intel_irq_remapping_free, | |
1402 | .activate = intel_irq_remapping_activate, | |
1403 | .deactivate = intel_irq_remapping_deactivate, | |
736baef4 | 1404 | }; |
6b197249 | 1405 | |
a7a3dad9 JL |
1406 | /* |
1407 | * Support of Interrupt Remapping Unit Hotplug | |
1408 | */ | |
1409 | static int dmar_ir_add(struct dmar_drhd_unit *dmaru, struct intel_iommu *iommu) | |
1410 | { | |
1411 | int ret; | |
1412 | int eim = x2apic_enabled(); | |
1413 | ||
1414 | if (eim && !ecap_eim_support(iommu->ecap)) { | |
1415 | pr_info("DRHD %Lx: EIM not supported by DRHD, ecap %Lx\n", | |
1416 | iommu->reg_phys, iommu->ecap); | |
1417 | return -ENODEV; | |
1418 | } | |
1419 | ||
1420 | if (ir_parse_ioapic_hpet_scope(dmaru->hdr, iommu)) { | |
1421 | pr_warn("DRHD %Lx: failed to parse managed IOAPIC/HPET\n", | |
1422 | iommu->reg_phys); | |
1423 | return -ENODEV; | |
1424 | } | |
1425 | ||
1426 | /* TODO: check all IOAPICs are covered by IOMMU */ | |
1427 | ||
1428 | /* Setup Interrupt-remapping now. */ | |
1429 | ret = intel_setup_irq_remapping(iommu); | |
1430 | if (ret) { | |
9e4e49df JR |
1431 | pr_err("Failed to setup irq remapping for %s\n", |
1432 | iommu->name); | |
a7a3dad9 JL |
1433 | intel_teardown_irq_remapping(iommu); |
1434 | ir_remove_ioapic_hpet_scope(iommu); | |
9e4e49df | 1435 | } else { |
d4d1c0f3 | 1436 | iommu_enable_irq_remapping(iommu); |
a7a3dad9 JL |
1437 | } |
1438 | ||
1439 | return ret; | |
1440 | } | |
1441 | ||
6b197249 JL |
1442 | int dmar_ir_hotplug(struct dmar_drhd_unit *dmaru, bool insert) |
1443 | { | |
a7a3dad9 JL |
1444 | int ret = 0; |
1445 | struct intel_iommu *iommu = dmaru->iommu; | |
1446 | ||
1447 | if (!irq_remapping_enabled) | |
1448 | return 0; | |
1449 | if (iommu == NULL) | |
1450 | return -EINVAL; | |
1451 | if (!ecap_ir_support(iommu->ecap)) | |
1452 | return 0; | |
c1d99334 FW |
1453 | if (irq_remapping_cap(IRQ_POSTING_CAP) && |
1454 | !cap_pi_support(iommu->cap)) | |
1455 | return -EBUSY; | |
a7a3dad9 JL |
1456 | |
1457 | if (insert) { | |
1458 | if (!iommu->ir_table) | |
1459 | ret = dmar_ir_add(dmaru, iommu); | |
1460 | } else { | |
1461 | if (iommu->ir_table) { | |
1462 | if (!bitmap_empty(iommu->ir_table->bitmap, | |
1463 | INTR_REMAP_TABLE_ENTRIES)) { | |
1464 | ret = -EBUSY; | |
1465 | } else { | |
1466 | iommu_disable_irq_remapping(iommu); | |
1467 | intel_teardown_irq_remapping(iommu); | |
1468 | ir_remove_ioapic_hpet_scope(iommu); | |
1469 | } | |
1470 | } | |
1471 | } | |
1472 | ||
1473 | return ret; | |
6b197249 | 1474 | } |