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1802d0be | 1 | // SPDX-License-Identifier: GPL-2.0-only |
0df4fabe YW |
2 | /* |
3 | * Copyright (c) 2015-2016 MediaTek Inc. | |
4 | * Author: Yong Wu <yong.wu@mediatek.com> | |
0df4fabe YW |
5 | */ |
6 | #include <linux/bug.h> | |
7 | #include <linux/clk.h> | |
8 | #include <linux/component.h> | |
9 | #include <linux/device.h> | |
10 | #include <linux/dma-iommu.h> | |
11 | #include <linux/err.h> | |
12 | #include <linux/interrupt.h> | |
13 | #include <linux/io.h> | |
14 | #include <linux/iommu.h> | |
15 | #include <linux/iopoll.h> | |
16 | #include <linux/list.h> | |
c2c59456 | 17 | #include <linux/mfd/syscon.h> |
0df4fabe YW |
18 | #include <linux/of_address.h> |
19 | #include <linux/of_iommu.h> | |
20 | #include <linux/of_irq.h> | |
21 | #include <linux/of_platform.h> | |
22 | #include <linux/platform_device.h> | |
baf94e6e | 23 | #include <linux/pm_runtime.h> |
c2c59456 | 24 | #include <linux/regmap.h> |
0df4fabe YW |
25 | #include <linux/slab.h> |
26 | #include <linux/spinlock.h> | |
c2c59456 | 27 | #include <linux/soc/mediatek/infracfg.h> |
0df4fabe | 28 | #include <asm/barrier.h> |
0df4fabe YW |
29 | #include <soc/mediatek/smi.h> |
30 | ||
9ca340c9 | 31 | #include "mtk_iommu.h" |
0df4fabe YW |
32 | |
33 | #define REG_MMU_PT_BASE_ADDR 0x000 | |
907ba6a1 | 34 | #define MMU_PT_ADDR_MASK GENMASK(31, 7) |
0df4fabe YW |
35 | |
36 | #define REG_MMU_INVALIDATE 0x020 | |
37 | #define F_ALL_INVLD 0x2 | |
38 | #define F_MMU_INV_RANGE 0x1 | |
39 | ||
40 | #define REG_MMU_INVLD_START_A 0x024 | |
41 | #define REG_MMU_INVLD_END_A 0x028 | |
42 | ||
068c86e9 | 43 | #define REG_MMU_INV_SEL_GEN2 0x02c |
b053bc71 | 44 | #define REG_MMU_INV_SEL_GEN1 0x038 |
0df4fabe YW |
45 | #define F_INVLD_EN0 BIT(0) |
46 | #define F_INVLD_EN1 BIT(1) | |
47 | ||
75eed350 | 48 | #define REG_MMU_MISC_CTRL 0x048 |
4bb2bf4c CH |
49 | #define F_MMU_IN_ORDER_WR_EN_MASK (BIT(1) | BIT(17)) |
50 | #define F_MMU_STANDARD_AXI_MODE_MASK (BIT(3) | BIT(19)) | |
51 | ||
0df4fabe | 52 | #define REG_MMU_DCM_DIS 0x050 |
35c1b48d CH |
53 | #define REG_MMU_WR_LEN_CTRL 0x054 |
54 | #define F_MMU_WR_THROT_DIS_MASK (BIT(5) | BIT(21)) | |
0df4fabe YW |
55 | |
56 | #define REG_MMU_CTRL_REG 0x110 | |
acb3c92a | 57 | #define F_MMU_TF_PROT_TO_PROGRAM_ADDR (2 << 4) |
0df4fabe | 58 | #define F_MMU_PREFETCH_RT_REPLACE_MOD BIT(4) |
acb3c92a | 59 | #define F_MMU_TF_PROT_TO_PROGRAM_ADDR_MT8173 (2 << 5) |
0df4fabe YW |
60 | |
61 | #define REG_MMU_IVRP_PADDR 0x114 | |
70ca608b | 62 | |
30e2fccf YW |
63 | #define REG_MMU_VLD_PA_RNG 0x118 |
64 | #define F_MMU_VLD_PA_RNG(EA, SA) (((EA) << 8) | (SA)) | |
0df4fabe YW |
65 | |
66 | #define REG_MMU_INT_CONTROL0 0x120 | |
67 | #define F_L2_MULIT_HIT_EN BIT(0) | |
68 | #define F_TABLE_WALK_FAULT_INT_EN BIT(1) | |
69 | #define F_PREETCH_FIFO_OVERFLOW_INT_EN BIT(2) | |
70 | #define F_MISS_FIFO_OVERFLOW_INT_EN BIT(3) | |
71 | #define F_PREFETCH_FIFO_ERR_INT_EN BIT(5) | |
72 | #define F_MISS_FIFO_ERR_INT_EN BIT(6) | |
73 | #define F_INT_CLR_BIT BIT(12) | |
74 | ||
75 | #define REG_MMU_INT_MAIN_CONTROL 0x124 | |
15a01f4c YW |
76 | /* mmu0 | mmu1 */ |
77 | #define F_INT_TRANSLATION_FAULT (BIT(0) | BIT(7)) | |
78 | #define F_INT_MAIN_MULTI_HIT_FAULT (BIT(1) | BIT(8)) | |
79 | #define F_INT_INVALID_PA_FAULT (BIT(2) | BIT(9)) | |
80 | #define F_INT_ENTRY_REPLACEMENT_FAULT (BIT(3) | BIT(10)) | |
81 | #define F_INT_TLB_MISS_FAULT (BIT(4) | BIT(11)) | |
82 | #define F_INT_MISS_TRANSACTION_FIFO_FAULT (BIT(5) | BIT(12)) | |
83 | #define F_INT_PRETETCH_TRANSATION_FIFO_FAULT (BIT(6) | BIT(13)) | |
0df4fabe YW |
84 | |
85 | #define REG_MMU_CPE_DONE 0x12C | |
86 | ||
87 | #define REG_MMU_FAULT_ST1 0x134 | |
15a01f4c YW |
88 | #define F_REG_MMU0_FAULT_MASK GENMASK(6, 0) |
89 | #define F_REG_MMU1_FAULT_MASK GENMASK(13, 7) | |
0df4fabe | 90 | |
15a01f4c | 91 | #define REG_MMU0_FAULT_VA 0x13c |
0df4fabe YW |
92 | #define F_MMU_FAULT_VA_WRITE_BIT BIT(1) |
93 | #define F_MMU_FAULT_VA_LAYER_BIT BIT(0) | |
94 | ||
15a01f4c YW |
95 | #define REG_MMU0_INVLD_PA 0x140 |
96 | #define REG_MMU1_FAULT_VA 0x144 | |
97 | #define REG_MMU1_INVLD_PA 0x148 | |
98 | #define REG_MMU0_INT_ID 0x150 | |
99 | #define REG_MMU1_INT_ID 0x154 | |
37276e00 CH |
100 | #define F_MMU_INT_ID_COMM_ID(a) (((a) >> 9) & 0x7) |
101 | #define F_MMU_INT_ID_SUB_COMM_ID(a) (((a) >> 7) & 0x3) | |
15a01f4c YW |
102 | #define F_MMU_INT_ID_LARB_ID(a) (((a) >> 7) & 0x7) |
103 | #define F_MMU_INT_ID_PORT_ID(a) (((a) >> 2) & 0x1f) | |
0df4fabe | 104 | |
829316b3 | 105 | #define MTK_PROTECT_PA_ALIGN 256 |
0df4fabe | 106 | |
6b717796 CH |
107 | #define HAS_4GB_MODE BIT(0) |
108 | /* HW will use the EMI clock if there isn't the "bclk". */ | |
109 | #define HAS_BCLK BIT(1) | |
110 | #define HAS_VLD_PA_RNG BIT(2) | |
111 | #define RESET_AXI BIT(3) | |
4bb2bf4c | 112 | #define OUT_ORDER_WR_EN BIT(4) |
37276e00 | 113 | #define HAS_SUB_COMM BIT(5) |
35c1b48d | 114 | #define WR_THROT_EN BIT(6) |
d1b5ef00 | 115 | #define HAS_LEGACY_IVRP_PADDR BIT(7) |
2f317da4 | 116 | #define IOVA_34_EN BIT(8) |
6b717796 CH |
117 | |
118 | #define MTK_IOMMU_HAS_FLAG(pdata, _x) \ | |
119 | ((((pdata)->flags) & (_x)) == (_x)) | |
120 | ||
0df4fabe | 121 | struct mtk_iommu_domain { |
0df4fabe YW |
122 | struct io_pgtable_cfg cfg; |
123 | struct io_pgtable_ops *iop; | |
124 | ||
125 | struct iommu_domain domain; | |
126 | }; | |
127 | ||
b65f5016 | 128 | static const struct iommu_ops mtk_iommu_ops; |
0df4fabe | 129 | |
7f37a91d YW |
130 | static int mtk_iommu_hw_init(const struct mtk_iommu_data *data); |
131 | ||
76ce6546 YW |
132 | /* |
133 | * In M4U 4GB mode, the physical address is remapped as below: | |
134 | * | |
135 | * CPU Physical address: | |
136 | * ==================== | |
137 | * | |
138 | * 0 1G 2G 3G 4G 5G | |
139 | * |---A---|---B---|---C---|---D---|---E---| | |
140 | * +--I/O--+------------Memory-------------+ | |
141 | * | |
142 | * IOMMU output physical address: | |
143 | * ============================= | |
144 | * | |
145 | * 4G 5G 6G 7G 8G | |
146 | * |---E---|---B---|---C---|---D---| | |
147 | * +------------Memory-------------+ | |
148 | * | |
149 | * The Region 'A'(I/O) can NOT be mapped by M4U; For Region 'B'/'C'/'D', the | |
150 | * bit32 of the CPU physical address always is needed to set, and for Region | |
151 | * 'E', the CPU physical address keep as is. | |
152 | * Additionally, The iommu consumers always use the CPU phyiscal address. | |
153 | */ | |
b4dad40e | 154 | #define MTK_IOMMU_4GB_MODE_REMAP_BASE 0x140000000UL |
76ce6546 | 155 | |
7c3a2ec0 YW |
156 | static LIST_HEAD(m4ulist); /* List all the M4U HWs */ |
157 | ||
158 | #define for_each_m4u(data) list_for_each_entry(data, &m4ulist, list) | |
159 | ||
160 | /* | |
161 | * There may be 1 or 2 M4U HWs, But we always expect they are in the same domain | |
162 | * for the performance. | |
163 | * | |
164 | * Here always return the mtk_iommu_data of the first probed M4U where the | |
165 | * iommu domain information is recorded. | |
166 | */ | |
167 | static struct mtk_iommu_data *mtk_iommu_get_m4u_data(void) | |
168 | { | |
169 | struct mtk_iommu_data *data; | |
170 | ||
171 | for_each_m4u(data) | |
172 | return data; | |
173 | ||
174 | return NULL; | |
175 | } | |
176 | ||
0df4fabe YW |
177 | static struct mtk_iommu_domain *to_mtk_domain(struct iommu_domain *dom) |
178 | { | |
179 | return container_of(dom, struct mtk_iommu_domain, domain); | |
180 | } | |
181 | ||
0954d61a | 182 | static void mtk_iommu_tlb_flush_all(struct mtk_iommu_data *data) |
0df4fabe | 183 | { |
7c3a2ec0 YW |
184 | for_each_m4u(data) { |
185 | writel_relaxed(F_INVLD_EN1 | F_INVLD_EN0, | |
b053bc71 | 186 | data->base + data->plat_data->inv_sel_reg); |
7c3a2ec0 YW |
187 | writel_relaxed(F_ALL_INVLD, data->base + REG_MMU_INVALIDATE); |
188 | wmb(); /* Make sure the tlb flush all done */ | |
189 | } | |
0df4fabe YW |
190 | } |
191 | ||
1f4fd624 | 192 | static void mtk_iommu_tlb_flush_range_sync(unsigned long iova, size_t size, |
0954d61a YW |
193 | size_t granule, |
194 | struct mtk_iommu_data *data) | |
0df4fabe | 195 | { |
1f4fd624 YW |
196 | unsigned long flags; |
197 | int ret; | |
198 | u32 tmp; | |
0df4fabe | 199 | |
7c3a2ec0 | 200 | for_each_m4u(data) { |
1f4fd624 | 201 | spin_lock_irqsave(&data->tlb_lock, flags); |
7c3a2ec0 | 202 | writel_relaxed(F_INVLD_EN1 | F_INVLD_EN0, |
b053bc71 | 203 | data->base + data->plat_data->inv_sel_reg); |
0df4fabe | 204 | |
7c3a2ec0 YW |
205 | writel_relaxed(iova, data->base + REG_MMU_INVLD_START_A); |
206 | writel_relaxed(iova + size - 1, | |
207 | data->base + REG_MMU_INVLD_END_A); | |
208 | writel_relaxed(F_MMU_INV_RANGE, | |
209 | data->base + REG_MMU_INVALIDATE); | |
98a8f63e | 210 | |
1f4fd624 | 211 | /* tlb sync */ |
7c3a2ec0 | 212 | ret = readl_poll_timeout_atomic(data->base + REG_MMU_CPE_DONE, |
c90ae4a6 | 213 | tmp, tmp != 0, 10, 1000); |
7c3a2ec0 YW |
214 | if (ret) { |
215 | dev_warn(data->dev, | |
216 | "Partial TLB flush timed out, falling back to full flush\n"); | |
0954d61a | 217 | mtk_iommu_tlb_flush_all(data); |
7c3a2ec0 YW |
218 | } |
219 | /* Clear the CPE status */ | |
220 | writel_relaxed(0, data->base + REG_MMU_CPE_DONE); | |
1f4fd624 | 221 | spin_unlock_irqrestore(&data->tlb_lock, flags); |
0df4fabe | 222 | } |
0df4fabe YW |
223 | } |
224 | ||
0df4fabe YW |
225 | static irqreturn_t mtk_iommu_isr(int irq, void *dev_id) |
226 | { | |
227 | struct mtk_iommu_data *data = dev_id; | |
228 | struct mtk_iommu_domain *dom = data->m4u_dom; | |
229 | u32 int_state, regval, fault_iova, fault_pa; | |
37276e00 | 230 | unsigned int fault_larb, fault_port, sub_comm = 0; |
0df4fabe YW |
231 | bool layer, write; |
232 | ||
233 | /* Read error info from registers */ | |
234 | int_state = readl_relaxed(data->base + REG_MMU_FAULT_ST1); | |
15a01f4c YW |
235 | if (int_state & F_REG_MMU0_FAULT_MASK) { |
236 | regval = readl_relaxed(data->base + REG_MMU0_INT_ID); | |
237 | fault_iova = readl_relaxed(data->base + REG_MMU0_FAULT_VA); | |
238 | fault_pa = readl_relaxed(data->base + REG_MMU0_INVLD_PA); | |
239 | } else { | |
240 | regval = readl_relaxed(data->base + REG_MMU1_INT_ID); | |
241 | fault_iova = readl_relaxed(data->base + REG_MMU1_FAULT_VA); | |
242 | fault_pa = readl_relaxed(data->base + REG_MMU1_INVLD_PA); | |
243 | } | |
0df4fabe YW |
244 | layer = fault_iova & F_MMU_FAULT_VA_LAYER_BIT; |
245 | write = fault_iova & F_MMU_FAULT_VA_WRITE_BIT; | |
15a01f4c | 246 | fault_port = F_MMU_INT_ID_PORT_ID(regval); |
37276e00 CH |
247 | if (MTK_IOMMU_HAS_FLAG(data->plat_data, HAS_SUB_COMM)) { |
248 | fault_larb = F_MMU_INT_ID_COMM_ID(regval); | |
249 | sub_comm = F_MMU_INT_ID_SUB_COMM_ID(regval); | |
250 | } else { | |
251 | fault_larb = F_MMU_INT_ID_LARB_ID(regval); | |
252 | } | |
253 | fault_larb = data->plat_data->larbid_remap[fault_larb][sub_comm]; | |
b3e5eee7 | 254 | |
0df4fabe YW |
255 | if (report_iommu_fault(&dom->domain, data->dev, fault_iova, |
256 | write ? IOMMU_FAULT_WRITE : IOMMU_FAULT_READ)) { | |
257 | dev_err_ratelimited( | |
258 | data->dev, | |
259 | "fault type=0x%x iova=0x%x pa=0x%x larb=%d port=%d layer=%d %s\n", | |
260 | int_state, fault_iova, fault_pa, fault_larb, fault_port, | |
261 | layer, write ? "write" : "read"); | |
262 | } | |
263 | ||
264 | /* Interrupt clear */ | |
265 | regval = readl_relaxed(data->base + REG_MMU_INT_CONTROL0); | |
266 | regval |= F_INT_CLR_BIT; | |
267 | writel_relaxed(regval, data->base + REG_MMU_INT_CONTROL0); | |
268 | ||
269 | mtk_iommu_tlb_flush_all(data); | |
270 | ||
271 | return IRQ_HANDLED; | |
272 | } | |
273 | ||
274 | static void mtk_iommu_config(struct mtk_iommu_data *data, | |
275 | struct device *dev, bool enable) | |
276 | { | |
0df4fabe YW |
277 | struct mtk_smi_larb_iommu *larb_mmu; |
278 | unsigned int larbid, portid; | |
a9bf2eec | 279 | struct iommu_fwspec *fwspec = dev_iommu_fwspec_get(dev); |
58f0d1d5 | 280 | int i; |
0df4fabe | 281 | |
58f0d1d5 RM |
282 | for (i = 0; i < fwspec->num_ids; ++i) { |
283 | larbid = MTK_M4U_TO_LARB(fwspec->ids[i]); | |
284 | portid = MTK_M4U_TO_PORT(fwspec->ids[i]); | |
1ee9feb2 | 285 | larb_mmu = &data->larb_imu[larbid]; |
0df4fabe YW |
286 | |
287 | dev_dbg(dev, "%s iommu port: %d\n", | |
288 | enable ? "enable" : "disable", portid); | |
289 | ||
290 | if (enable) | |
291 | larb_mmu->mmu |= MTK_SMI_MMU_EN(portid); | |
292 | else | |
293 | larb_mmu->mmu &= ~MTK_SMI_MMU_EN(portid); | |
294 | } | |
295 | } | |
296 | ||
4b00f5ac | 297 | static int mtk_iommu_domain_finalise(struct mtk_iommu_domain *dom) |
0df4fabe | 298 | { |
4b00f5ac | 299 | struct mtk_iommu_data *data = mtk_iommu_get_m4u_data(); |
0df4fabe | 300 | |
0df4fabe YW |
301 | dom->cfg = (struct io_pgtable_cfg) { |
302 | .quirks = IO_PGTABLE_QUIRK_ARM_NS | | |
303 | IO_PGTABLE_QUIRK_NO_PERMS | | |
b4dad40e | 304 | IO_PGTABLE_QUIRK_ARM_MTK_EXT, |
0df4fabe | 305 | .pgsize_bitmap = mtk_iommu_ops.pgsize_bitmap, |
2f317da4 | 306 | .ias = MTK_IOMMU_HAS_FLAG(data->plat_data, IOVA_34_EN) ? 34 : 32, |
0df4fabe YW |
307 | .iommu_dev = data->dev, |
308 | }; | |
309 | ||
9bdfe4c1 YW |
310 | if (MTK_IOMMU_HAS_FLAG(data->plat_data, HAS_4GB_MODE)) |
311 | dom->cfg.oas = data->enable_4GB ? 33 : 32; | |
312 | else | |
313 | dom->cfg.oas = 35; | |
314 | ||
0df4fabe YW |
315 | dom->iop = alloc_io_pgtable_ops(ARM_V7S, &dom->cfg, data); |
316 | if (!dom->iop) { | |
317 | dev_err(data->dev, "Failed to alloc io pgtable\n"); | |
318 | return -EINVAL; | |
319 | } | |
320 | ||
321 | /* Update our support page sizes bitmap */ | |
d16e0faa | 322 | dom->domain.pgsize_bitmap = dom->cfg.pgsize_bitmap; |
0df4fabe YW |
323 | return 0; |
324 | } | |
325 | ||
326 | static struct iommu_domain *mtk_iommu_domain_alloc(unsigned type) | |
327 | { | |
328 | struct mtk_iommu_domain *dom; | |
329 | ||
330 | if (type != IOMMU_DOMAIN_DMA) | |
331 | return NULL; | |
332 | ||
333 | dom = kzalloc(sizeof(*dom), GFP_KERNEL); | |
334 | if (!dom) | |
335 | return NULL; | |
336 | ||
4b00f5ac YW |
337 | if (iommu_get_dma_cookie(&dom->domain)) |
338 | goto free_dom; | |
339 | ||
340 | if (mtk_iommu_domain_finalise(dom)) | |
341 | goto put_dma_cookie; | |
0df4fabe YW |
342 | |
343 | dom->domain.geometry.aperture_start = 0; | |
344 | dom->domain.geometry.aperture_end = DMA_BIT_MASK(32); | |
345 | dom->domain.geometry.force_aperture = true; | |
346 | ||
347 | return &dom->domain; | |
4b00f5ac YW |
348 | |
349 | put_dma_cookie: | |
350 | iommu_put_dma_cookie(&dom->domain); | |
351 | free_dom: | |
352 | kfree(dom); | |
353 | return NULL; | |
0df4fabe YW |
354 | } |
355 | ||
356 | static void mtk_iommu_domain_free(struct iommu_domain *domain) | |
357 | { | |
4b00f5ac YW |
358 | struct mtk_iommu_domain *dom = to_mtk_domain(domain); |
359 | ||
360 | free_io_pgtable_ops(dom->iop); | |
0df4fabe YW |
361 | iommu_put_dma_cookie(domain); |
362 | kfree(to_mtk_domain(domain)); | |
363 | } | |
364 | ||
365 | static int mtk_iommu_attach_device(struct iommu_domain *domain, | |
366 | struct device *dev) | |
367 | { | |
3524b559 | 368 | struct mtk_iommu_data *data = dev_iommu_priv_get(dev); |
0df4fabe | 369 | struct mtk_iommu_domain *dom = to_mtk_domain(domain); |
7f37a91d | 370 | int ret; |
0df4fabe | 371 | |
4b00f5ac | 372 | if (!data) |
0df4fabe YW |
373 | return -ENODEV; |
374 | ||
7f37a91d YW |
375 | if (!data->m4u_dom) { /* Initialize the M4U HW */ |
376 | ret = mtk_iommu_hw_init(data); | |
377 | if (ret) | |
378 | return ret; | |
0df4fabe | 379 | data->m4u_dom = dom; |
d1e5f26f | 380 | writel(dom->cfg.arm_v7s_cfg.ttbr & MMU_PT_ADDR_MASK, |
4b00f5ac | 381 | data->base + REG_MMU_PT_BASE_ADDR); |
7c3a2ec0 YW |
382 | } |
383 | ||
4b00f5ac | 384 | mtk_iommu_config(data, dev, true); |
0df4fabe YW |
385 | return 0; |
386 | } | |
387 | ||
388 | static void mtk_iommu_detach_device(struct iommu_domain *domain, | |
389 | struct device *dev) | |
390 | { | |
3524b559 | 391 | struct mtk_iommu_data *data = dev_iommu_priv_get(dev); |
0df4fabe | 392 | |
58f0d1d5 | 393 | if (!data) |
0df4fabe YW |
394 | return; |
395 | ||
0df4fabe YW |
396 | mtk_iommu_config(data, dev, false); |
397 | } | |
398 | ||
399 | static int mtk_iommu_map(struct iommu_domain *domain, unsigned long iova, | |
781ca2de | 400 | phys_addr_t paddr, size_t size, int prot, gfp_t gfp) |
0df4fabe YW |
401 | { |
402 | struct mtk_iommu_domain *dom = to_mtk_domain(domain); | |
b4dad40e | 403 | struct mtk_iommu_data *data = mtk_iommu_get_m4u_data(); |
0df4fabe | 404 | |
b4dad40e YW |
405 | /* The "4GB mode" M4U physically can not use the lower remap of Dram. */ |
406 | if (data->enable_4GB) | |
407 | paddr |= BIT_ULL(32); | |
408 | ||
60829b4d | 409 | /* Synchronize with the tlb_lock */ |
f34ce7a7 | 410 | return dom->iop->map(dom->iop, iova, paddr, size, prot, gfp); |
0df4fabe YW |
411 | } |
412 | ||
413 | static size_t mtk_iommu_unmap(struct iommu_domain *domain, | |
56f8af5e WD |
414 | unsigned long iova, size_t size, |
415 | struct iommu_iotlb_gather *gather) | |
0df4fabe YW |
416 | { |
417 | struct mtk_iommu_domain *dom = to_mtk_domain(domain); | |
f21ae3b1 | 418 | unsigned long end = iova + size - 1; |
0df4fabe | 419 | |
f21ae3b1 YW |
420 | if (gather->start > iova) |
421 | gather->start = iova; | |
422 | if (gather->end < end) | |
423 | gather->end = end; | |
60829b4d | 424 | return dom->iop->unmap(dom->iop, iova, size, gather); |
0df4fabe YW |
425 | } |
426 | ||
56f8af5e WD |
427 | static void mtk_iommu_flush_iotlb_all(struct iommu_domain *domain) |
428 | { | |
2009122f | 429 | mtk_iommu_tlb_flush_all(mtk_iommu_get_m4u_data()); |
56f8af5e WD |
430 | } |
431 | ||
432 | static void mtk_iommu_iotlb_sync(struct iommu_domain *domain, | |
433 | struct iommu_iotlb_gather *gather) | |
4d689b61 | 434 | { |
da3cc91b | 435 | struct mtk_iommu_data *data = mtk_iommu_get_m4u_data(); |
862c3715 | 436 | size_t length = gather->end - gather->start + 1; |
da3cc91b | 437 | |
1f4fd624 | 438 | mtk_iommu_tlb_flush_range_sync(gather->start, length, gather->pgsize, |
67caf7e2 | 439 | data); |
4d689b61 RM |
440 | } |
441 | ||
20143451 YW |
442 | static void mtk_iommu_sync_map(struct iommu_domain *domain, unsigned long iova, |
443 | size_t size) | |
444 | { | |
445 | struct mtk_iommu_data *data = mtk_iommu_get_m4u_data(); | |
446 | ||
447 | mtk_iommu_tlb_flush_range_sync(iova, size, size, data); | |
448 | } | |
449 | ||
0df4fabe YW |
450 | static phys_addr_t mtk_iommu_iova_to_phys(struct iommu_domain *domain, |
451 | dma_addr_t iova) | |
452 | { | |
453 | struct mtk_iommu_domain *dom = to_mtk_domain(domain); | |
30e2fccf | 454 | struct mtk_iommu_data *data = mtk_iommu_get_m4u_data(); |
0df4fabe YW |
455 | phys_addr_t pa; |
456 | ||
0df4fabe | 457 | pa = dom->iop->iova_to_phys(dom->iop, iova); |
b4dad40e YW |
458 | if (data->enable_4GB && pa >= MTK_IOMMU_4GB_MODE_REMAP_BASE) |
459 | pa &= ~BIT_ULL(32); | |
30e2fccf | 460 | |
0df4fabe YW |
461 | return pa; |
462 | } | |
463 | ||
80e4592a | 464 | static struct iommu_device *mtk_iommu_probe_device(struct device *dev) |
0df4fabe | 465 | { |
a9bf2eec | 466 | struct iommu_fwspec *fwspec = dev_iommu_fwspec_get(dev); |
b16c0170 | 467 | struct mtk_iommu_data *data; |
0df4fabe | 468 | |
a9bf2eec | 469 | if (!fwspec || fwspec->ops != &mtk_iommu_ops) |
80e4592a | 470 | return ERR_PTR(-ENODEV); /* Not a iommu client device */ |
0df4fabe | 471 | |
3524b559 | 472 | data = dev_iommu_priv_get(dev); |
b16c0170 | 473 | |
80e4592a | 474 | return &data->iommu; |
0df4fabe YW |
475 | } |
476 | ||
80e4592a | 477 | static void mtk_iommu_release_device(struct device *dev) |
0df4fabe | 478 | { |
a9bf2eec | 479 | struct iommu_fwspec *fwspec = dev_iommu_fwspec_get(dev); |
b16c0170 | 480 | |
a9bf2eec | 481 | if (!fwspec || fwspec->ops != &mtk_iommu_ops) |
0df4fabe YW |
482 | return; |
483 | ||
58f0d1d5 | 484 | iommu_fwspec_free(dev); |
0df4fabe YW |
485 | } |
486 | ||
487 | static struct iommu_group *mtk_iommu_device_group(struct device *dev) | |
488 | { | |
7c3a2ec0 | 489 | struct mtk_iommu_data *data = mtk_iommu_get_m4u_data(); |
0df4fabe | 490 | |
58f0d1d5 | 491 | if (!data) |
0df4fabe YW |
492 | return ERR_PTR(-ENODEV); |
493 | ||
494 | /* All the client devices are in the same m4u iommu-group */ | |
0df4fabe YW |
495 | if (!data->m4u_group) { |
496 | data->m4u_group = iommu_group_alloc(); | |
497 | if (IS_ERR(data->m4u_group)) | |
498 | dev_err(dev, "Failed to allocate M4U IOMMU group\n"); | |
3a8d40b6 RM |
499 | } else { |
500 | iommu_group_ref_get(data->m4u_group); | |
0df4fabe YW |
501 | } |
502 | return data->m4u_group; | |
503 | } | |
504 | ||
505 | static int mtk_iommu_of_xlate(struct device *dev, struct of_phandle_args *args) | |
506 | { | |
0df4fabe YW |
507 | struct platform_device *m4updev; |
508 | ||
509 | if (args->args_count != 1) { | |
510 | dev_err(dev, "invalid #iommu-cells(%d) property for IOMMU\n", | |
511 | args->args_count); | |
512 | return -EINVAL; | |
513 | } | |
514 | ||
3524b559 | 515 | if (!dev_iommu_priv_get(dev)) { |
0df4fabe YW |
516 | /* Get the m4u device */ |
517 | m4updev = of_find_device_by_node(args->np); | |
0df4fabe YW |
518 | if (WARN_ON(!m4updev)) |
519 | return -EINVAL; | |
520 | ||
3524b559 | 521 | dev_iommu_priv_set(dev, platform_get_drvdata(m4updev)); |
0df4fabe YW |
522 | } |
523 | ||
58f0d1d5 | 524 | return iommu_fwspec_add_ids(dev, args->args, 1); |
0df4fabe YW |
525 | } |
526 | ||
b65f5016 | 527 | static const struct iommu_ops mtk_iommu_ops = { |
0df4fabe YW |
528 | .domain_alloc = mtk_iommu_domain_alloc, |
529 | .domain_free = mtk_iommu_domain_free, | |
530 | .attach_dev = mtk_iommu_attach_device, | |
531 | .detach_dev = mtk_iommu_detach_device, | |
532 | .map = mtk_iommu_map, | |
533 | .unmap = mtk_iommu_unmap, | |
56f8af5e | 534 | .flush_iotlb_all = mtk_iommu_flush_iotlb_all, |
4d689b61 | 535 | .iotlb_sync = mtk_iommu_iotlb_sync, |
20143451 | 536 | .iotlb_sync_map = mtk_iommu_sync_map, |
0df4fabe | 537 | .iova_to_phys = mtk_iommu_iova_to_phys, |
80e4592a JR |
538 | .probe_device = mtk_iommu_probe_device, |
539 | .release_device = mtk_iommu_release_device, | |
0df4fabe YW |
540 | .device_group = mtk_iommu_device_group, |
541 | .of_xlate = mtk_iommu_of_xlate, | |
542 | .pgsize_bitmap = SZ_4K | SZ_64K | SZ_1M | SZ_16M, | |
543 | }; | |
544 | ||
545 | static int mtk_iommu_hw_init(const struct mtk_iommu_data *data) | |
546 | { | |
547 | u32 regval; | |
548 | int ret; | |
549 | ||
550 | ret = clk_prepare_enable(data->bclk); | |
551 | if (ret) { | |
552 | dev_err(data->dev, "Failed to enable iommu bclk(%d)\n", ret); | |
553 | return ret; | |
554 | } | |
555 | ||
86444413 | 556 | if (data->plat_data->m4u_plat == M4U_MT8173) { |
acb3c92a YW |
557 | regval = F_MMU_PREFETCH_RT_REPLACE_MOD | |
558 | F_MMU_TF_PROT_TO_PROGRAM_ADDR_MT8173; | |
86444413 CH |
559 | } else { |
560 | regval = readl_relaxed(data->base + REG_MMU_CTRL_REG); | |
561 | regval |= F_MMU_TF_PROT_TO_PROGRAM_ADDR; | |
562 | } | |
0df4fabe YW |
563 | writel_relaxed(regval, data->base + REG_MMU_CTRL_REG); |
564 | ||
565 | regval = F_L2_MULIT_HIT_EN | | |
566 | F_TABLE_WALK_FAULT_INT_EN | | |
567 | F_PREETCH_FIFO_OVERFLOW_INT_EN | | |
568 | F_MISS_FIFO_OVERFLOW_INT_EN | | |
569 | F_PREFETCH_FIFO_ERR_INT_EN | | |
570 | F_MISS_FIFO_ERR_INT_EN; | |
571 | writel_relaxed(regval, data->base + REG_MMU_INT_CONTROL0); | |
572 | ||
573 | regval = F_INT_TRANSLATION_FAULT | | |
574 | F_INT_MAIN_MULTI_HIT_FAULT | | |
575 | F_INT_INVALID_PA_FAULT | | |
576 | F_INT_ENTRY_REPLACEMENT_FAULT | | |
577 | F_INT_TLB_MISS_FAULT | | |
578 | F_INT_MISS_TRANSACTION_FIFO_FAULT | | |
579 | F_INT_PRETETCH_TRANSATION_FIFO_FAULT; | |
580 | writel_relaxed(regval, data->base + REG_MMU_INT_MAIN_CONTROL); | |
581 | ||
d1b5ef00 | 582 | if (MTK_IOMMU_HAS_FLAG(data->plat_data, HAS_LEGACY_IVRP_PADDR)) |
70ca608b YW |
583 | regval = (data->protect_base >> 1) | (data->enable_4GB << 31); |
584 | else | |
585 | regval = lower_32_bits(data->protect_base) | | |
586 | upper_32_bits(data->protect_base); | |
587 | writel_relaxed(regval, data->base + REG_MMU_IVRP_PADDR); | |
588 | ||
6b717796 CH |
589 | if (data->enable_4GB && |
590 | MTK_IOMMU_HAS_FLAG(data->plat_data, HAS_VLD_PA_RNG)) { | |
30e2fccf YW |
591 | /* |
592 | * If 4GB mode is enabled, the validate PA range is from | |
593 | * 0x1_0000_0000 to 0x1_ffff_ffff. here record bit[32:30]. | |
594 | */ | |
595 | regval = F_MMU_VLD_PA_RNG(7, 4); | |
596 | writel_relaxed(regval, data->base + REG_MMU_VLD_PA_RNG); | |
597 | } | |
0df4fabe | 598 | writel_relaxed(0, data->base + REG_MMU_DCM_DIS); |
35c1b48d CH |
599 | if (MTK_IOMMU_HAS_FLAG(data->plat_data, WR_THROT_EN)) { |
600 | /* write command throttling mode */ | |
601 | regval = readl_relaxed(data->base + REG_MMU_WR_LEN_CTRL); | |
602 | regval &= ~F_MMU_WR_THROT_DIS_MASK; | |
603 | writel_relaxed(regval, data->base + REG_MMU_WR_LEN_CTRL); | |
604 | } | |
e6dec923 | 605 | |
6b717796 | 606 | if (MTK_IOMMU_HAS_FLAG(data->plat_data, RESET_AXI)) { |
75eed350 | 607 | /* The register is called STANDARD_AXI_MODE in this case */ |
4bb2bf4c CH |
608 | regval = 0; |
609 | } else { | |
610 | regval = readl_relaxed(data->base + REG_MMU_MISC_CTRL); | |
611 | regval &= ~F_MMU_STANDARD_AXI_MODE_MASK; | |
612 | if (MTK_IOMMU_HAS_FLAG(data->plat_data, OUT_ORDER_WR_EN)) | |
613 | regval &= ~F_MMU_IN_ORDER_WR_EN_MASK; | |
75eed350 | 614 | } |
4bb2bf4c | 615 | writel_relaxed(regval, data->base + REG_MMU_MISC_CTRL); |
0df4fabe YW |
616 | |
617 | if (devm_request_irq(data->dev, data->irq, mtk_iommu_isr, 0, | |
618 | dev_name(data->dev), (void *)data)) { | |
619 | writel_relaxed(0, data->base + REG_MMU_PT_BASE_ADDR); | |
620 | clk_disable_unprepare(data->bclk); | |
621 | dev_err(data->dev, "Failed @ IRQ-%d Request\n", data->irq); | |
622 | return -ENODEV; | |
623 | } | |
624 | ||
625 | return 0; | |
626 | } | |
627 | ||
0df4fabe YW |
628 | static const struct component_master_ops mtk_iommu_com_ops = { |
629 | .bind = mtk_iommu_bind, | |
630 | .unbind = mtk_iommu_unbind, | |
631 | }; | |
632 | ||
633 | static int mtk_iommu_probe(struct platform_device *pdev) | |
634 | { | |
635 | struct mtk_iommu_data *data; | |
636 | struct device *dev = &pdev->dev; | |
baf94e6e YW |
637 | struct device_node *larbnode, *smicomm_node; |
638 | struct platform_device *plarbdev; | |
639 | struct device_link *link; | |
0df4fabe | 640 | struct resource *res; |
b16c0170 | 641 | resource_size_t ioaddr; |
0df4fabe | 642 | struct component_match *match = NULL; |
c2c59456 | 643 | struct regmap *infracfg; |
0df4fabe | 644 | void *protect; |
0b6c0ad3 | 645 | int i, larb_nr, ret; |
c2c59456 MC |
646 | u32 val; |
647 | char *p; | |
0df4fabe YW |
648 | |
649 | data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL); | |
650 | if (!data) | |
651 | return -ENOMEM; | |
652 | data->dev = dev; | |
cecdce9d | 653 | data->plat_data = of_device_get_match_data(dev); |
0df4fabe YW |
654 | |
655 | /* Protect memory. HW will access here while translation fault.*/ | |
656 | protect = devm_kzalloc(dev, MTK_PROTECT_PA_ALIGN * 2, GFP_KERNEL); | |
657 | if (!protect) | |
658 | return -ENOMEM; | |
659 | data->protect_base = ALIGN(virt_to_phys(protect), MTK_PROTECT_PA_ALIGN); | |
660 | ||
c2c59456 MC |
661 | if (MTK_IOMMU_HAS_FLAG(data->plat_data, HAS_4GB_MODE)) { |
662 | switch (data->plat_data->m4u_plat) { | |
663 | case M4U_MT2712: | |
664 | p = "mediatek,mt2712-infracfg"; | |
665 | break; | |
666 | case M4U_MT8173: | |
667 | p = "mediatek,mt8173-infracfg"; | |
668 | break; | |
669 | default: | |
670 | p = NULL; | |
671 | } | |
672 | ||
673 | infracfg = syscon_regmap_lookup_by_compatible(p); | |
674 | ||
675 | if (IS_ERR(infracfg)) | |
676 | return PTR_ERR(infracfg); | |
677 | ||
678 | ret = regmap_read(infracfg, REG_INFRA_MISC, &val); | |
679 | if (ret) | |
680 | return ret; | |
681 | data->enable_4GB = !!(val & F_DDR_4GB_SUPPORT_EN); | |
682 | } | |
01e23c93 | 683 | |
0df4fabe YW |
684 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
685 | data->base = devm_ioremap_resource(dev, res); | |
686 | if (IS_ERR(data->base)) | |
687 | return PTR_ERR(data->base); | |
b16c0170 | 688 | ioaddr = res->start; |
0df4fabe YW |
689 | |
690 | data->irq = platform_get_irq(pdev, 0); | |
691 | if (data->irq < 0) | |
692 | return data->irq; | |
693 | ||
6b717796 | 694 | if (MTK_IOMMU_HAS_FLAG(data->plat_data, HAS_BCLK)) { |
2aa4c259 YW |
695 | data->bclk = devm_clk_get(dev, "bclk"); |
696 | if (IS_ERR(data->bclk)) | |
697 | return PTR_ERR(data->bclk); | |
698 | } | |
0df4fabe YW |
699 | |
700 | larb_nr = of_count_phandle_with_args(dev->of_node, | |
701 | "mediatek,larbs", NULL); | |
702 | if (larb_nr < 0) | |
703 | return larb_nr; | |
0df4fabe YW |
704 | |
705 | for (i = 0; i < larb_nr; i++) { | |
e6dec923 | 706 | u32 id; |
0df4fabe YW |
707 | |
708 | larbnode = of_parse_phandle(dev->of_node, "mediatek,larbs", i); | |
709 | if (!larbnode) | |
710 | return -EINVAL; | |
711 | ||
1eb8e4e2 WY |
712 | if (!of_device_is_available(larbnode)) { |
713 | of_node_put(larbnode); | |
0df4fabe | 714 | continue; |
1eb8e4e2 | 715 | } |
0df4fabe | 716 | |
e6dec923 YW |
717 | ret = of_property_read_u32(larbnode, "mediatek,larb-id", &id); |
718 | if (ret)/* The id is consecutive if there is no this property */ | |
719 | id = i; | |
720 | ||
0df4fabe | 721 | plarbdev = of_find_device_by_node(larbnode); |
1eb8e4e2 WY |
722 | if (!plarbdev) { |
723 | of_node_put(larbnode); | |
e6dec923 | 724 | return -EPROBE_DEFER; |
1eb8e4e2 | 725 | } |
1ee9feb2 | 726 | data->larb_imu[id].dev = &plarbdev->dev; |
0df4fabe | 727 | |
00c7c81f RK |
728 | component_match_add_release(dev, &match, release_of, |
729 | compare_of, larbnode); | |
0df4fabe YW |
730 | } |
731 | ||
baf94e6e YW |
732 | /* Get smi-common dev from the last larb. */ |
733 | smicomm_node = of_parse_phandle(larbnode, "mediatek,smi", 0); | |
734 | if (!smicomm_node) | |
735 | return -EINVAL; | |
736 | ||
737 | plarbdev = of_find_device_by_node(smicomm_node); | |
738 | of_node_put(smicomm_node); | |
739 | data->smicomm_dev = &plarbdev->dev; | |
740 | ||
741 | link = device_link_add(data->smicomm_dev, dev, | |
742 | DL_FLAG_STATELESS | DL_FLAG_PM_RUNTIME); | |
743 | if (!link) { | |
744 | dev_err(dev, "Unable link %s.\n", dev_name(data->smicomm_dev)); | |
745 | return -EINVAL; | |
746 | } | |
747 | ||
0df4fabe YW |
748 | platform_set_drvdata(pdev, data); |
749 | ||
b16c0170 JR |
750 | ret = iommu_device_sysfs_add(&data->iommu, dev, NULL, |
751 | "mtk-iommu.%pa", &ioaddr); | |
752 | if (ret) | |
baf94e6e | 753 | goto out_link_remove; |
b16c0170 JR |
754 | |
755 | iommu_device_set_ops(&data->iommu, &mtk_iommu_ops); | |
756 | iommu_device_set_fwnode(&data->iommu, &pdev->dev.of_node->fwnode); | |
757 | ||
758 | ret = iommu_device_register(&data->iommu); | |
759 | if (ret) | |
986d9ec5 | 760 | goto out_sysfs_remove; |
b16c0170 | 761 | |
da3cc91b | 762 | spin_lock_init(&data->tlb_lock); |
7c3a2ec0 YW |
763 | list_add_tail(&data->list, &m4ulist); |
764 | ||
986d9ec5 YW |
765 | if (!iommu_present(&platform_bus_type)) { |
766 | ret = bus_set_iommu(&platform_bus_type, &mtk_iommu_ops); | |
767 | if (ret) | |
768 | goto out_list_del; | |
769 | } | |
0df4fabe | 770 | |
986d9ec5 YW |
771 | ret = component_master_add_with_match(dev, &mtk_iommu_com_ops, match); |
772 | if (ret) | |
773 | goto out_bus_set_null; | |
774 | return ret; | |
775 | ||
776 | out_bus_set_null: | |
777 | bus_set_iommu(&platform_bus_type, NULL); | |
778 | out_list_del: | |
779 | list_del(&data->list); | |
780 | iommu_device_unregister(&data->iommu); | |
781 | out_sysfs_remove: | |
782 | iommu_device_sysfs_remove(&data->iommu); | |
baf94e6e YW |
783 | out_link_remove: |
784 | device_link_remove(data->smicomm_dev, dev); | |
986d9ec5 | 785 | return ret; |
0df4fabe YW |
786 | } |
787 | ||
788 | static int mtk_iommu_remove(struct platform_device *pdev) | |
789 | { | |
790 | struct mtk_iommu_data *data = platform_get_drvdata(pdev); | |
791 | ||
b16c0170 JR |
792 | iommu_device_sysfs_remove(&data->iommu); |
793 | iommu_device_unregister(&data->iommu); | |
794 | ||
0df4fabe YW |
795 | if (iommu_present(&platform_bus_type)) |
796 | bus_set_iommu(&platform_bus_type, NULL); | |
797 | ||
0df4fabe | 798 | clk_disable_unprepare(data->bclk); |
baf94e6e | 799 | device_link_remove(data->smicomm_dev, &pdev->dev); |
0df4fabe YW |
800 | devm_free_irq(&pdev->dev, data->irq, data); |
801 | component_master_del(&pdev->dev, &mtk_iommu_com_ops); | |
802 | return 0; | |
803 | } | |
804 | ||
fd99f796 | 805 | static int __maybe_unused mtk_iommu_suspend(struct device *dev) |
0df4fabe YW |
806 | { |
807 | struct mtk_iommu_data *data = dev_get_drvdata(dev); | |
808 | struct mtk_iommu_suspend_reg *reg = &data->reg; | |
809 | void __iomem *base = data->base; | |
810 | ||
35c1b48d | 811 | reg->wr_len_ctrl = readl_relaxed(base + REG_MMU_WR_LEN_CTRL); |
75eed350 | 812 | reg->misc_ctrl = readl_relaxed(base + REG_MMU_MISC_CTRL); |
0df4fabe YW |
813 | reg->dcm_dis = readl_relaxed(base + REG_MMU_DCM_DIS); |
814 | reg->ctrl_reg = readl_relaxed(base + REG_MMU_CTRL_REG); | |
815 | reg->int_control0 = readl_relaxed(base + REG_MMU_INT_CONTROL0); | |
816 | reg->int_main_control = readl_relaxed(base + REG_MMU_INT_MAIN_CONTROL); | |
70ca608b | 817 | reg->ivrp_paddr = readl_relaxed(base + REG_MMU_IVRP_PADDR); |
b9475b34 | 818 | reg->vld_pa_rng = readl_relaxed(base + REG_MMU_VLD_PA_RNG); |
6254b64f | 819 | clk_disable_unprepare(data->bclk); |
0df4fabe YW |
820 | return 0; |
821 | } | |
822 | ||
fd99f796 | 823 | static int __maybe_unused mtk_iommu_resume(struct device *dev) |
0df4fabe YW |
824 | { |
825 | struct mtk_iommu_data *data = dev_get_drvdata(dev); | |
826 | struct mtk_iommu_suspend_reg *reg = &data->reg; | |
907ba6a1 | 827 | struct mtk_iommu_domain *m4u_dom = data->m4u_dom; |
0df4fabe | 828 | void __iomem *base = data->base; |
6254b64f | 829 | int ret; |
0df4fabe | 830 | |
6254b64f YW |
831 | ret = clk_prepare_enable(data->bclk); |
832 | if (ret) { | |
833 | dev_err(data->dev, "Failed to enable clk(%d) in resume\n", ret); | |
834 | return ret; | |
835 | } | |
35c1b48d | 836 | writel_relaxed(reg->wr_len_ctrl, base + REG_MMU_WR_LEN_CTRL); |
75eed350 | 837 | writel_relaxed(reg->misc_ctrl, base + REG_MMU_MISC_CTRL); |
0df4fabe YW |
838 | writel_relaxed(reg->dcm_dis, base + REG_MMU_DCM_DIS); |
839 | writel_relaxed(reg->ctrl_reg, base + REG_MMU_CTRL_REG); | |
840 | writel_relaxed(reg->int_control0, base + REG_MMU_INT_CONTROL0); | |
841 | writel_relaxed(reg->int_main_control, base + REG_MMU_INT_MAIN_CONTROL); | |
70ca608b | 842 | writel_relaxed(reg->ivrp_paddr, base + REG_MMU_IVRP_PADDR); |
b9475b34 | 843 | writel_relaxed(reg->vld_pa_rng, base + REG_MMU_VLD_PA_RNG); |
907ba6a1 | 844 | if (m4u_dom) |
d1e5f26f | 845 | writel(m4u_dom->cfg.arm_v7s_cfg.ttbr & MMU_PT_ADDR_MASK, |
e6dec923 | 846 | base + REG_MMU_PT_BASE_ADDR); |
0df4fabe YW |
847 | return 0; |
848 | } | |
849 | ||
e6dec923 | 850 | static const struct dev_pm_ops mtk_iommu_pm_ops = { |
6254b64f | 851 | SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(mtk_iommu_suspend, mtk_iommu_resume) |
0df4fabe YW |
852 | }; |
853 | ||
cecdce9d YW |
854 | static const struct mtk_iommu_plat_data mt2712_data = { |
855 | .m4u_plat = M4U_MT2712, | |
6b717796 | 856 | .flags = HAS_4GB_MODE | HAS_BCLK | HAS_VLD_PA_RNG, |
b053bc71 | 857 | .inv_sel_reg = REG_MMU_INV_SEL_GEN1, |
37276e00 | 858 | .larbid_remap = {{0}, {1}, {2}, {3}, {4}, {5}, {6}, {7}}, |
cecdce9d YW |
859 | }; |
860 | ||
068c86e9 CH |
861 | static const struct mtk_iommu_plat_data mt6779_data = { |
862 | .m4u_plat = M4U_MT6779, | |
863 | .flags = HAS_SUB_COMM | OUT_ORDER_WR_EN | WR_THROT_EN, | |
864 | .inv_sel_reg = REG_MMU_INV_SEL_GEN2, | |
865 | .larbid_remap = {{0}, {1}, {2}, {3}, {5}, {7, 8}, {10}, {9}}, | |
cecdce9d YW |
866 | }; |
867 | ||
3c213562 FP |
868 | static const struct mtk_iommu_plat_data mt8167_data = { |
869 | .m4u_plat = M4U_MT8167, | |
870 | .flags = RESET_AXI | HAS_LEGACY_IVRP_PADDR, | |
871 | .inv_sel_reg = REG_MMU_INV_SEL_GEN1, | |
872 | .larbid_remap = {{0}, {1}, {2}}, /* Linear mapping. */ | |
873 | }; | |
874 | ||
cecdce9d YW |
875 | static const struct mtk_iommu_plat_data mt8173_data = { |
876 | .m4u_plat = M4U_MT8173, | |
d1b5ef00 FP |
877 | .flags = HAS_4GB_MODE | HAS_BCLK | RESET_AXI | |
878 | HAS_LEGACY_IVRP_PADDR, | |
b053bc71 | 879 | .inv_sel_reg = REG_MMU_INV_SEL_GEN1, |
37276e00 | 880 | .larbid_remap = {{0}, {1}, {2}, {3}, {4}, {5}}, /* Linear mapping. */ |
cecdce9d YW |
881 | }; |
882 | ||
907ba6a1 YW |
883 | static const struct mtk_iommu_plat_data mt8183_data = { |
884 | .m4u_plat = M4U_MT8183, | |
6b717796 | 885 | .flags = RESET_AXI, |
b053bc71 | 886 | .inv_sel_reg = REG_MMU_INV_SEL_GEN1, |
37276e00 | 887 | .larbid_remap = {{0}, {4}, {5}, {6}, {7}, {2}, {3}, {1}}, |
907ba6a1 YW |
888 | }; |
889 | ||
0df4fabe | 890 | static const struct of_device_id mtk_iommu_of_ids[] = { |
cecdce9d | 891 | { .compatible = "mediatek,mt2712-m4u", .data = &mt2712_data}, |
068c86e9 | 892 | { .compatible = "mediatek,mt6779-m4u", .data = &mt6779_data}, |
3c213562 | 893 | { .compatible = "mediatek,mt8167-m4u", .data = &mt8167_data}, |
cecdce9d | 894 | { .compatible = "mediatek,mt8173-m4u", .data = &mt8173_data}, |
907ba6a1 | 895 | { .compatible = "mediatek,mt8183-m4u", .data = &mt8183_data}, |
0df4fabe YW |
896 | {} |
897 | }; | |
898 | ||
899 | static struct platform_driver mtk_iommu_driver = { | |
900 | .probe = mtk_iommu_probe, | |
901 | .remove = mtk_iommu_remove, | |
902 | .driver = { | |
903 | .name = "mtk-iommu", | |
f53dd978 | 904 | .of_match_table = mtk_iommu_of_ids, |
0df4fabe YW |
905 | .pm = &mtk_iommu_pm_ops, |
906 | } | |
907 | }; | |
908 | ||
e6dec923 | 909 | static int __init mtk_iommu_init(void) |
0df4fabe YW |
910 | { |
911 | int ret; | |
0df4fabe YW |
912 | |
913 | ret = platform_driver_register(&mtk_iommu_driver); | |
e6dec923 YW |
914 | if (ret != 0) |
915 | pr_err("Failed to register MTK IOMMU driver\n"); | |
0df4fabe | 916 | |
e6dec923 | 917 | return ret; |
0df4fabe YW |
918 | } |
919 | ||
e6dec923 | 920 | subsys_initcall(mtk_iommu_init) |