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1802d0be | 1 | // SPDX-License-Identifier: GPL-2.0-only |
0df4fabe YW |
2 | /* |
3 | * Copyright (c) 2015-2016 MediaTek Inc. | |
4 | * Author: Yong Wu <yong.wu@mediatek.com> | |
0df4fabe YW |
5 | */ |
6 | #include <linux/bug.h> | |
7 | #include <linux/clk.h> | |
8 | #include <linux/component.h> | |
9 | #include <linux/device.h> | |
10 | #include <linux/dma-iommu.h> | |
11 | #include <linux/err.h> | |
12 | #include <linux/interrupt.h> | |
13 | #include <linux/io.h> | |
14 | #include <linux/iommu.h> | |
15 | #include <linux/iopoll.h> | |
16 | #include <linux/list.h> | |
c2c59456 | 17 | #include <linux/mfd/syscon.h> |
0df4fabe YW |
18 | #include <linux/of_address.h> |
19 | #include <linux/of_iommu.h> | |
20 | #include <linux/of_irq.h> | |
21 | #include <linux/of_platform.h> | |
22 | #include <linux/platform_device.h> | |
c2c59456 | 23 | #include <linux/regmap.h> |
0df4fabe YW |
24 | #include <linux/slab.h> |
25 | #include <linux/spinlock.h> | |
c2c59456 | 26 | #include <linux/soc/mediatek/infracfg.h> |
0df4fabe | 27 | #include <asm/barrier.h> |
0df4fabe YW |
28 | #include <soc/mediatek/smi.h> |
29 | ||
9ca340c9 | 30 | #include "mtk_iommu.h" |
0df4fabe YW |
31 | |
32 | #define REG_MMU_PT_BASE_ADDR 0x000 | |
907ba6a1 | 33 | #define MMU_PT_ADDR_MASK GENMASK(31, 7) |
0df4fabe YW |
34 | |
35 | #define REG_MMU_INVALIDATE 0x020 | |
36 | #define F_ALL_INVLD 0x2 | |
37 | #define F_MMU_INV_RANGE 0x1 | |
38 | ||
39 | #define REG_MMU_INVLD_START_A 0x024 | |
40 | #define REG_MMU_INVLD_END_A 0x028 | |
41 | ||
068c86e9 | 42 | #define REG_MMU_INV_SEL_GEN2 0x02c |
b053bc71 | 43 | #define REG_MMU_INV_SEL_GEN1 0x038 |
0df4fabe YW |
44 | #define F_INVLD_EN0 BIT(0) |
45 | #define F_INVLD_EN1 BIT(1) | |
46 | ||
75eed350 | 47 | #define REG_MMU_MISC_CTRL 0x048 |
4bb2bf4c CH |
48 | #define F_MMU_IN_ORDER_WR_EN_MASK (BIT(1) | BIT(17)) |
49 | #define F_MMU_STANDARD_AXI_MODE_MASK (BIT(3) | BIT(19)) | |
50 | ||
0df4fabe | 51 | #define REG_MMU_DCM_DIS 0x050 |
35c1b48d CH |
52 | #define REG_MMU_WR_LEN_CTRL 0x054 |
53 | #define F_MMU_WR_THROT_DIS_MASK (BIT(5) | BIT(21)) | |
0df4fabe YW |
54 | |
55 | #define REG_MMU_CTRL_REG 0x110 | |
acb3c92a | 56 | #define F_MMU_TF_PROT_TO_PROGRAM_ADDR (2 << 4) |
0df4fabe | 57 | #define F_MMU_PREFETCH_RT_REPLACE_MOD BIT(4) |
acb3c92a | 58 | #define F_MMU_TF_PROT_TO_PROGRAM_ADDR_MT8173 (2 << 5) |
0df4fabe YW |
59 | |
60 | #define REG_MMU_IVRP_PADDR 0x114 | |
70ca608b | 61 | |
30e2fccf YW |
62 | #define REG_MMU_VLD_PA_RNG 0x118 |
63 | #define F_MMU_VLD_PA_RNG(EA, SA) (((EA) << 8) | (SA)) | |
0df4fabe YW |
64 | |
65 | #define REG_MMU_INT_CONTROL0 0x120 | |
66 | #define F_L2_MULIT_HIT_EN BIT(0) | |
67 | #define F_TABLE_WALK_FAULT_INT_EN BIT(1) | |
68 | #define F_PREETCH_FIFO_OVERFLOW_INT_EN BIT(2) | |
69 | #define F_MISS_FIFO_OVERFLOW_INT_EN BIT(3) | |
70 | #define F_PREFETCH_FIFO_ERR_INT_EN BIT(5) | |
71 | #define F_MISS_FIFO_ERR_INT_EN BIT(6) | |
72 | #define F_INT_CLR_BIT BIT(12) | |
73 | ||
74 | #define REG_MMU_INT_MAIN_CONTROL 0x124 | |
15a01f4c YW |
75 | /* mmu0 | mmu1 */ |
76 | #define F_INT_TRANSLATION_FAULT (BIT(0) | BIT(7)) | |
77 | #define F_INT_MAIN_MULTI_HIT_FAULT (BIT(1) | BIT(8)) | |
78 | #define F_INT_INVALID_PA_FAULT (BIT(2) | BIT(9)) | |
79 | #define F_INT_ENTRY_REPLACEMENT_FAULT (BIT(3) | BIT(10)) | |
80 | #define F_INT_TLB_MISS_FAULT (BIT(4) | BIT(11)) | |
81 | #define F_INT_MISS_TRANSACTION_FIFO_FAULT (BIT(5) | BIT(12)) | |
82 | #define F_INT_PRETETCH_TRANSATION_FIFO_FAULT (BIT(6) | BIT(13)) | |
0df4fabe YW |
83 | |
84 | #define REG_MMU_CPE_DONE 0x12C | |
85 | ||
86 | #define REG_MMU_FAULT_ST1 0x134 | |
15a01f4c YW |
87 | #define F_REG_MMU0_FAULT_MASK GENMASK(6, 0) |
88 | #define F_REG_MMU1_FAULT_MASK GENMASK(13, 7) | |
0df4fabe | 89 | |
15a01f4c | 90 | #define REG_MMU0_FAULT_VA 0x13c |
0df4fabe YW |
91 | #define F_MMU_FAULT_VA_WRITE_BIT BIT(1) |
92 | #define F_MMU_FAULT_VA_LAYER_BIT BIT(0) | |
93 | ||
15a01f4c YW |
94 | #define REG_MMU0_INVLD_PA 0x140 |
95 | #define REG_MMU1_FAULT_VA 0x144 | |
96 | #define REG_MMU1_INVLD_PA 0x148 | |
97 | #define REG_MMU0_INT_ID 0x150 | |
98 | #define REG_MMU1_INT_ID 0x154 | |
37276e00 CH |
99 | #define F_MMU_INT_ID_COMM_ID(a) (((a) >> 9) & 0x7) |
100 | #define F_MMU_INT_ID_SUB_COMM_ID(a) (((a) >> 7) & 0x3) | |
15a01f4c YW |
101 | #define F_MMU_INT_ID_LARB_ID(a) (((a) >> 7) & 0x7) |
102 | #define F_MMU_INT_ID_PORT_ID(a) (((a) >> 2) & 0x1f) | |
0df4fabe | 103 | |
829316b3 | 104 | #define MTK_PROTECT_PA_ALIGN 256 |
0df4fabe | 105 | |
a9467d95 YW |
106 | /* |
107 | * Get the local arbiter ID and the portid within the larb arbiter | |
108 | * from mtk_m4u_id which is defined by MTK_M4U_ID. | |
109 | */ | |
e6dec923 | 110 | #define MTK_M4U_TO_LARB(id) (((id) >> 5) & 0xf) |
a9467d95 YW |
111 | #define MTK_M4U_TO_PORT(id) ((id) & 0x1f) |
112 | ||
6b717796 CH |
113 | #define HAS_4GB_MODE BIT(0) |
114 | /* HW will use the EMI clock if there isn't the "bclk". */ | |
115 | #define HAS_BCLK BIT(1) | |
116 | #define HAS_VLD_PA_RNG BIT(2) | |
117 | #define RESET_AXI BIT(3) | |
4bb2bf4c | 118 | #define OUT_ORDER_WR_EN BIT(4) |
37276e00 | 119 | #define HAS_SUB_COMM BIT(5) |
35c1b48d | 120 | #define WR_THROT_EN BIT(6) |
d1b5ef00 | 121 | #define HAS_LEGACY_IVRP_PADDR BIT(7) |
6b717796 CH |
122 | |
123 | #define MTK_IOMMU_HAS_FLAG(pdata, _x) \ | |
124 | ((((pdata)->flags) & (_x)) == (_x)) | |
125 | ||
0df4fabe | 126 | struct mtk_iommu_domain { |
0df4fabe YW |
127 | struct io_pgtable_cfg cfg; |
128 | struct io_pgtable_ops *iop; | |
129 | ||
130 | struct iommu_domain domain; | |
131 | }; | |
132 | ||
b65f5016 | 133 | static const struct iommu_ops mtk_iommu_ops; |
0df4fabe | 134 | |
76ce6546 YW |
135 | /* |
136 | * In M4U 4GB mode, the physical address is remapped as below: | |
137 | * | |
138 | * CPU Physical address: | |
139 | * ==================== | |
140 | * | |
141 | * 0 1G 2G 3G 4G 5G | |
142 | * |---A---|---B---|---C---|---D---|---E---| | |
143 | * +--I/O--+------------Memory-------------+ | |
144 | * | |
145 | * IOMMU output physical address: | |
146 | * ============================= | |
147 | * | |
148 | * 4G 5G 6G 7G 8G | |
149 | * |---E---|---B---|---C---|---D---| | |
150 | * +------------Memory-------------+ | |
151 | * | |
152 | * The Region 'A'(I/O) can NOT be mapped by M4U; For Region 'B'/'C'/'D', the | |
153 | * bit32 of the CPU physical address always is needed to set, and for Region | |
154 | * 'E', the CPU physical address keep as is. | |
155 | * Additionally, The iommu consumers always use the CPU phyiscal address. | |
156 | */ | |
b4dad40e | 157 | #define MTK_IOMMU_4GB_MODE_REMAP_BASE 0x140000000UL |
76ce6546 | 158 | |
7c3a2ec0 YW |
159 | static LIST_HEAD(m4ulist); /* List all the M4U HWs */ |
160 | ||
161 | #define for_each_m4u(data) list_for_each_entry(data, &m4ulist, list) | |
162 | ||
163 | /* | |
164 | * There may be 1 or 2 M4U HWs, But we always expect they are in the same domain | |
165 | * for the performance. | |
166 | * | |
167 | * Here always return the mtk_iommu_data of the first probed M4U where the | |
168 | * iommu domain information is recorded. | |
169 | */ | |
170 | static struct mtk_iommu_data *mtk_iommu_get_m4u_data(void) | |
171 | { | |
172 | struct mtk_iommu_data *data; | |
173 | ||
174 | for_each_m4u(data) | |
175 | return data; | |
176 | ||
177 | return NULL; | |
178 | } | |
179 | ||
0df4fabe YW |
180 | static struct mtk_iommu_domain *to_mtk_domain(struct iommu_domain *dom) |
181 | { | |
182 | return container_of(dom, struct mtk_iommu_domain, domain); | |
183 | } | |
184 | ||
185 | static void mtk_iommu_tlb_flush_all(void *cookie) | |
186 | { | |
187 | struct mtk_iommu_data *data = cookie; | |
188 | ||
7c3a2ec0 YW |
189 | for_each_m4u(data) { |
190 | writel_relaxed(F_INVLD_EN1 | F_INVLD_EN0, | |
b053bc71 | 191 | data->base + data->plat_data->inv_sel_reg); |
7c3a2ec0 YW |
192 | writel_relaxed(F_ALL_INVLD, data->base + REG_MMU_INVALIDATE); |
193 | wmb(); /* Make sure the tlb flush all done */ | |
194 | } | |
0df4fabe YW |
195 | } |
196 | ||
1f4fd624 | 197 | static void mtk_iommu_tlb_flush_range_sync(unsigned long iova, size_t size, |
67caf7e2 | 198 | size_t granule, void *cookie) |
0df4fabe YW |
199 | { |
200 | struct mtk_iommu_data *data = cookie; | |
1f4fd624 YW |
201 | unsigned long flags; |
202 | int ret; | |
203 | u32 tmp; | |
0df4fabe | 204 | |
7c3a2ec0 | 205 | for_each_m4u(data) { |
1f4fd624 | 206 | spin_lock_irqsave(&data->tlb_lock, flags); |
7c3a2ec0 | 207 | writel_relaxed(F_INVLD_EN1 | F_INVLD_EN0, |
b053bc71 | 208 | data->base + data->plat_data->inv_sel_reg); |
0df4fabe | 209 | |
7c3a2ec0 YW |
210 | writel_relaxed(iova, data->base + REG_MMU_INVLD_START_A); |
211 | writel_relaxed(iova + size - 1, | |
212 | data->base + REG_MMU_INVLD_END_A); | |
213 | writel_relaxed(F_MMU_INV_RANGE, | |
214 | data->base + REG_MMU_INVALIDATE); | |
98a8f63e | 215 | |
1f4fd624 | 216 | /* tlb sync */ |
7c3a2ec0 | 217 | ret = readl_poll_timeout_atomic(data->base + REG_MMU_CPE_DONE, |
c90ae4a6 | 218 | tmp, tmp != 0, 10, 1000); |
7c3a2ec0 YW |
219 | if (ret) { |
220 | dev_warn(data->dev, | |
221 | "Partial TLB flush timed out, falling back to full flush\n"); | |
222 | mtk_iommu_tlb_flush_all(cookie); | |
223 | } | |
224 | /* Clear the CPE status */ | |
225 | writel_relaxed(0, data->base + REG_MMU_CPE_DONE); | |
1f4fd624 | 226 | spin_unlock_irqrestore(&data->tlb_lock, flags); |
0df4fabe | 227 | } |
0df4fabe YW |
228 | } |
229 | ||
3951c41a WD |
230 | static void mtk_iommu_tlb_flush_page_nosync(struct iommu_iotlb_gather *gather, |
231 | unsigned long iova, size_t granule, | |
abfd6fe0 WD |
232 | void *cookie) |
233 | { | |
da3cc91b | 234 | struct mtk_iommu_data *data = cookie; |
a7a04ea3 | 235 | struct iommu_domain *domain = &data->m4u_dom->domain; |
da3cc91b | 236 | |
a7a04ea3 | 237 | iommu_iotlb_gather_add_page(domain, gather, iova, granule); |
abfd6fe0 WD |
238 | } |
239 | ||
298f7889 | 240 | static const struct iommu_flush_ops mtk_iommu_flush_ops = { |
0df4fabe | 241 | .tlb_flush_all = mtk_iommu_tlb_flush_all, |
1f4fd624 YW |
242 | .tlb_flush_walk = mtk_iommu_tlb_flush_range_sync, |
243 | .tlb_flush_leaf = mtk_iommu_tlb_flush_range_sync, | |
abfd6fe0 | 244 | .tlb_add_page = mtk_iommu_tlb_flush_page_nosync, |
0df4fabe YW |
245 | }; |
246 | ||
247 | static irqreturn_t mtk_iommu_isr(int irq, void *dev_id) | |
248 | { | |
249 | struct mtk_iommu_data *data = dev_id; | |
250 | struct mtk_iommu_domain *dom = data->m4u_dom; | |
251 | u32 int_state, regval, fault_iova, fault_pa; | |
37276e00 | 252 | unsigned int fault_larb, fault_port, sub_comm = 0; |
0df4fabe YW |
253 | bool layer, write; |
254 | ||
255 | /* Read error info from registers */ | |
256 | int_state = readl_relaxed(data->base + REG_MMU_FAULT_ST1); | |
15a01f4c YW |
257 | if (int_state & F_REG_MMU0_FAULT_MASK) { |
258 | regval = readl_relaxed(data->base + REG_MMU0_INT_ID); | |
259 | fault_iova = readl_relaxed(data->base + REG_MMU0_FAULT_VA); | |
260 | fault_pa = readl_relaxed(data->base + REG_MMU0_INVLD_PA); | |
261 | } else { | |
262 | regval = readl_relaxed(data->base + REG_MMU1_INT_ID); | |
263 | fault_iova = readl_relaxed(data->base + REG_MMU1_FAULT_VA); | |
264 | fault_pa = readl_relaxed(data->base + REG_MMU1_INVLD_PA); | |
265 | } | |
0df4fabe YW |
266 | layer = fault_iova & F_MMU_FAULT_VA_LAYER_BIT; |
267 | write = fault_iova & F_MMU_FAULT_VA_WRITE_BIT; | |
15a01f4c | 268 | fault_port = F_MMU_INT_ID_PORT_ID(regval); |
37276e00 CH |
269 | if (MTK_IOMMU_HAS_FLAG(data->plat_data, HAS_SUB_COMM)) { |
270 | fault_larb = F_MMU_INT_ID_COMM_ID(regval); | |
271 | sub_comm = F_MMU_INT_ID_SUB_COMM_ID(regval); | |
272 | } else { | |
273 | fault_larb = F_MMU_INT_ID_LARB_ID(regval); | |
274 | } | |
275 | fault_larb = data->plat_data->larbid_remap[fault_larb][sub_comm]; | |
b3e5eee7 | 276 | |
0df4fabe YW |
277 | if (report_iommu_fault(&dom->domain, data->dev, fault_iova, |
278 | write ? IOMMU_FAULT_WRITE : IOMMU_FAULT_READ)) { | |
279 | dev_err_ratelimited( | |
280 | data->dev, | |
281 | "fault type=0x%x iova=0x%x pa=0x%x larb=%d port=%d layer=%d %s\n", | |
282 | int_state, fault_iova, fault_pa, fault_larb, fault_port, | |
283 | layer, write ? "write" : "read"); | |
284 | } | |
285 | ||
286 | /* Interrupt clear */ | |
287 | regval = readl_relaxed(data->base + REG_MMU_INT_CONTROL0); | |
288 | regval |= F_INT_CLR_BIT; | |
289 | writel_relaxed(regval, data->base + REG_MMU_INT_CONTROL0); | |
290 | ||
291 | mtk_iommu_tlb_flush_all(data); | |
292 | ||
293 | return IRQ_HANDLED; | |
294 | } | |
295 | ||
296 | static void mtk_iommu_config(struct mtk_iommu_data *data, | |
297 | struct device *dev, bool enable) | |
298 | { | |
0df4fabe YW |
299 | struct mtk_smi_larb_iommu *larb_mmu; |
300 | unsigned int larbid, portid; | |
a9bf2eec | 301 | struct iommu_fwspec *fwspec = dev_iommu_fwspec_get(dev); |
58f0d1d5 | 302 | int i; |
0df4fabe | 303 | |
58f0d1d5 RM |
304 | for (i = 0; i < fwspec->num_ids; ++i) { |
305 | larbid = MTK_M4U_TO_LARB(fwspec->ids[i]); | |
306 | portid = MTK_M4U_TO_PORT(fwspec->ids[i]); | |
1ee9feb2 | 307 | larb_mmu = &data->larb_imu[larbid]; |
0df4fabe YW |
308 | |
309 | dev_dbg(dev, "%s iommu port: %d\n", | |
310 | enable ? "enable" : "disable", portid); | |
311 | ||
312 | if (enable) | |
313 | larb_mmu->mmu |= MTK_SMI_MMU_EN(portid); | |
314 | else | |
315 | larb_mmu->mmu &= ~MTK_SMI_MMU_EN(portid); | |
316 | } | |
317 | } | |
318 | ||
4b00f5ac | 319 | static int mtk_iommu_domain_finalise(struct mtk_iommu_domain *dom) |
0df4fabe | 320 | { |
4b00f5ac | 321 | struct mtk_iommu_data *data = mtk_iommu_get_m4u_data(); |
0df4fabe | 322 | |
0df4fabe YW |
323 | dom->cfg = (struct io_pgtable_cfg) { |
324 | .quirks = IO_PGTABLE_QUIRK_ARM_NS | | |
325 | IO_PGTABLE_QUIRK_NO_PERMS | | |
b4dad40e YW |
326 | IO_PGTABLE_QUIRK_TLBI_ON_MAP | |
327 | IO_PGTABLE_QUIRK_ARM_MTK_EXT, | |
0df4fabe YW |
328 | .pgsize_bitmap = mtk_iommu_ops.pgsize_bitmap, |
329 | .ias = 32, | |
b4dad40e | 330 | .oas = 34, |
298f7889 | 331 | .tlb = &mtk_iommu_flush_ops, |
0df4fabe YW |
332 | .iommu_dev = data->dev, |
333 | }; | |
334 | ||
335 | dom->iop = alloc_io_pgtable_ops(ARM_V7S, &dom->cfg, data); | |
336 | if (!dom->iop) { | |
337 | dev_err(data->dev, "Failed to alloc io pgtable\n"); | |
338 | return -EINVAL; | |
339 | } | |
340 | ||
341 | /* Update our support page sizes bitmap */ | |
d16e0faa | 342 | dom->domain.pgsize_bitmap = dom->cfg.pgsize_bitmap; |
0df4fabe YW |
343 | return 0; |
344 | } | |
345 | ||
346 | static struct iommu_domain *mtk_iommu_domain_alloc(unsigned type) | |
347 | { | |
348 | struct mtk_iommu_domain *dom; | |
349 | ||
350 | if (type != IOMMU_DOMAIN_DMA) | |
351 | return NULL; | |
352 | ||
353 | dom = kzalloc(sizeof(*dom), GFP_KERNEL); | |
354 | if (!dom) | |
355 | return NULL; | |
356 | ||
4b00f5ac YW |
357 | if (iommu_get_dma_cookie(&dom->domain)) |
358 | goto free_dom; | |
359 | ||
360 | if (mtk_iommu_domain_finalise(dom)) | |
361 | goto put_dma_cookie; | |
0df4fabe YW |
362 | |
363 | dom->domain.geometry.aperture_start = 0; | |
364 | dom->domain.geometry.aperture_end = DMA_BIT_MASK(32); | |
365 | dom->domain.geometry.force_aperture = true; | |
366 | ||
367 | return &dom->domain; | |
4b00f5ac YW |
368 | |
369 | put_dma_cookie: | |
370 | iommu_put_dma_cookie(&dom->domain); | |
371 | free_dom: | |
372 | kfree(dom); | |
373 | return NULL; | |
0df4fabe YW |
374 | } |
375 | ||
376 | static void mtk_iommu_domain_free(struct iommu_domain *domain) | |
377 | { | |
4b00f5ac YW |
378 | struct mtk_iommu_domain *dom = to_mtk_domain(domain); |
379 | ||
380 | free_io_pgtable_ops(dom->iop); | |
0df4fabe YW |
381 | iommu_put_dma_cookie(domain); |
382 | kfree(to_mtk_domain(domain)); | |
383 | } | |
384 | ||
385 | static int mtk_iommu_attach_device(struct iommu_domain *domain, | |
386 | struct device *dev) | |
387 | { | |
3524b559 | 388 | struct mtk_iommu_data *data = dev_iommu_priv_get(dev); |
0df4fabe | 389 | struct mtk_iommu_domain *dom = to_mtk_domain(domain); |
0df4fabe | 390 | |
4b00f5ac | 391 | if (!data) |
0df4fabe YW |
392 | return -ENODEV; |
393 | ||
4b00f5ac | 394 | /* Update the pgtable base address register of the M4U HW */ |
0df4fabe YW |
395 | if (!data->m4u_dom) { |
396 | data->m4u_dom = dom; | |
d1e5f26f | 397 | writel(dom->cfg.arm_v7s_cfg.ttbr & MMU_PT_ADDR_MASK, |
4b00f5ac | 398 | data->base + REG_MMU_PT_BASE_ADDR); |
7c3a2ec0 YW |
399 | } |
400 | ||
4b00f5ac | 401 | mtk_iommu_config(data, dev, true); |
0df4fabe YW |
402 | return 0; |
403 | } | |
404 | ||
405 | static void mtk_iommu_detach_device(struct iommu_domain *domain, | |
406 | struct device *dev) | |
407 | { | |
3524b559 | 408 | struct mtk_iommu_data *data = dev_iommu_priv_get(dev); |
0df4fabe | 409 | |
58f0d1d5 | 410 | if (!data) |
0df4fabe YW |
411 | return; |
412 | ||
0df4fabe YW |
413 | mtk_iommu_config(data, dev, false); |
414 | } | |
415 | ||
416 | static int mtk_iommu_map(struct iommu_domain *domain, unsigned long iova, | |
781ca2de | 417 | phys_addr_t paddr, size_t size, int prot, gfp_t gfp) |
0df4fabe YW |
418 | { |
419 | struct mtk_iommu_domain *dom = to_mtk_domain(domain); | |
b4dad40e | 420 | struct mtk_iommu_data *data = mtk_iommu_get_m4u_data(); |
0df4fabe | 421 | |
b4dad40e YW |
422 | /* The "4GB mode" M4U physically can not use the lower remap of Dram. */ |
423 | if (data->enable_4GB) | |
424 | paddr |= BIT_ULL(32); | |
425 | ||
60829b4d | 426 | /* Synchronize with the tlb_lock */ |
f34ce7a7 | 427 | return dom->iop->map(dom->iop, iova, paddr, size, prot, gfp); |
0df4fabe YW |
428 | } |
429 | ||
430 | static size_t mtk_iommu_unmap(struct iommu_domain *domain, | |
56f8af5e WD |
431 | unsigned long iova, size_t size, |
432 | struct iommu_iotlb_gather *gather) | |
0df4fabe YW |
433 | { |
434 | struct mtk_iommu_domain *dom = to_mtk_domain(domain); | |
0df4fabe | 435 | |
60829b4d | 436 | return dom->iop->unmap(dom->iop, iova, size, gather); |
0df4fabe YW |
437 | } |
438 | ||
56f8af5e WD |
439 | static void mtk_iommu_flush_iotlb_all(struct iommu_domain *domain) |
440 | { | |
2009122f | 441 | mtk_iommu_tlb_flush_all(mtk_iommu_get_m4u_data()); |
56f8af5e WD |
442 | } |
443 | ||
444 | static void mtk_iommu_iotlb_sync(struct iommu_domain *domain, | |
445 | struct iommu_iotlb_gather *gather) | |
4d689b61 | 446 | { |
da3cc91b | 447 | struct mtk_iommu_data *data = mtk_iommu_get_m4u_data(); |
a7a04ea3 | 448 | size_t length = gather->end - gather->start; |
da3cc91b | 449 | |
a7a04ea3 YW |
450 | if (gather->start == ULONG_MAX) |
451 | return; | |
452 | ||
1f4fd624 | 453 | mtk_iommu_tlb_flush_range_sync(gather->start, length, gather->pgsize, |
67caf7e2 | 454 | data); |
4d689b61 RM |
455 | } |
456 | ||
0df4fabe YW |
457 | static phys_addr_t mtk_iommu_iova_to_phys(struct iommu_domain *domain, |
458 | dma_addr_t iova) | |
459 | { | |
460 | struct mtk_iommu_domain *dom = to_mtk_domain(domain); | |
30e2fccf | 461 | struct mtk_iommu_data *data = mtk_iommu_get_m4u_data(); |
0df4fabe YW |
462 | phys_addr_t pa; |
463 | ||
0df4fabe | 464 | pa = dom->iop->iova_to_phys(dom->iop, iova); |
b4dad40e YW |
465 | if (data->enable_4GB && pa >= MTK_IOMMU_4GB_MODE_REMAP_BASE) |
466 | pa &= ~BIT_ULL(32); | |
30e2fccf | 467 | |
0df4fabe YW |
468 | return pa; |
469 | } | |
470 | ||
80e4592a | 471 | static struct iommu_device *mtk_iommu_probe_device(struct device *dev) |
0df4fabe | 472 | { |
a9bf2eec | 473 | struct iommu_fwspec *fwspec = dev_iommu_fwspec_get(dev); |
b16c0170 | 474 | struct mtk_iommu_data *data; |
0df4fabe | 475 | |
a9bf2eec | 476 | if (!fwspec || fwspec->ops != &mtk_iommu_ops) |
80e4592a | 477 | return ERR_PTR(-ENODEV); /* Not a iommu client device */ |
0df4fabe | 478 | |
3524b559 | 479 | data = dev_iommu_priv_get(dev); |
b16c0170 | 480 | |
80e4592a | 481 | return &data->iommu; |
0df4fabe YW |
482 | } |
483 | ||
80e4592a | 484 | static void mtk_iommu_release_device(struct device *dev) |
0df4fabe | 485 | { |
a9bf2eec | 486 | struct iommu_fwspec *fwspec = dev_iommu_fwspec_get(dev); |
b16c0170 | 487 | |
a9bf2eec | 488 | if (!fwspec || fwspec->ops != &mtk_iommu_ops) |
0df4fabe YW |
489 | return; |
490 | ||
58f0d1d5 | 491 | iommu_fwspec_free(dev); |
0df4fabe YW |
492 | } |
493 | ||
494 | static struct iommu_group *mtk_iommu_device_group(struct device *dev) | |
495 | { | |
7c3a2ec0 | 496 | struct mtk_iommu_data *data = mtk_iommu_get_m4u_data(); |
0df4fabe | 497 | |
58f0d1d5 | 498 | if (!data) |
0df4fabe YW |
499 | return ERR_PTR(-ENODEV); |
500 | ||
501 | /* All the client devices are in the same m4u iommu-group */ | |
0df4fabe YW |
502 | if (!data->m4u_group) { |
503 | data->m4u_group = iommu_group_alloc(); | |
504 | if (IS_ERR(data->m4u_group)) | |
505 | dev_err(dev, "Failed to allocate M4U IOMMU group\n"); | |
3a8d40b6 RM |
506 | } else { |
507 | iommu_group_ref_get(data->m4u_group); | |
0df4fabe YW |
508 | } |
509 | return data->m4u_group; | |
510 | } | |
511 | ||
512 | static int mtk_iommu_of_xlate(struct device *dev, struct of_phandle_args *args) | |
513 | { | |
0df4fabe YW |
514 | struct platform_device *m4updev; |
515 | ||
516 | if (args->args_count != 1) { | |
517 | dev_err(dev, "invalid #iommu-cells(%d) property for IOMMU\n", | |
518 | args->args_count); | |
519 | return -EINVAL; | |
520 | } | |
521 | ||
3524b559 | 522 | if (!dev_iommu_priv_get(dev)) { |
0df4fabe YW |
523 | /* Get the m4u device */ |
524 | m4updev = of_find_device_by_node(args->np); | |
0df4fabe YW |
525 | if (WARN_ON(!m4updev)) |
526 | return -EINVAL; | |
527 | ||
3524b559 | 528 | dev_iommu_priv_set(dev, platform_get_drvdata(m4updev)); |
0df4fabe YW |
529 | } |
530 | ||
58f0d1d5 | 531 | return iommu_fwspec_add_ids(dev, args->args, 1); |
0df4fabe YW |
532 | } |
533 | ||
b65f5016 | 534 | static const struct iommu_ops mtk_iommu_ops = { |
0df4fabe YW |
535 | .domain_alloc = mtk_iommu_domain_alloc, |
536 | .domain_free = mtk_iommu_domain_free, | |
537 | .attach_dev = mtk_iommu_attach_device, | |
538 | .detach_dev = mtk_iommu_detach_device, | |
539 | .map = mtk_iommu_map, | |
540 | .unmap = mtk_iommu_unmap, | |
56f8af5e | 541 | .flush_iotlb_all = mtk_iommu_flush_iotlb_all, |
4d689b61 | 542 | .iotlb_sync = mtk_iommu_iotlb_sync, |
0df4fabe | 543 | .iova_to_phys = mtk_iommu_iova_to_phys, |
80e4592a JR |
544 | .probe_device = mtk_iommu_probe_device, |
545 | .release_device = mtk_iommu_release_device, | |
0df4fabe YW |
546 | .device_group = mtk_iommu_device_group, |
547 | .of_xlate = mtk_iommu_of_xlate, | |
548 | .pgsize_bitmap = SZ_4K | SZ_64K | SZ_1M | SZ_16M, | |
549 | }; | |
550 | ||
551 | static int mtk_iommu_hw_init(const struct mtk_iommu_data *data) | |
552 | { | |
553 | u32 regval; | |
554 | int ret; | |
555 | ||
556 | ret = clk_prepare_enable(data->bclk); | |
557 | if (ret) { | |
558 | dev_err(data->dev, "Failed to enable iommu bclk(%d)\n", ret); | |
559 | return ret; | |
560 | } | |
561 | ||
86444413 | 562 | if (data->plat_data->m4u_plat == M4U_MT8173) { |
acb3c92a YW |
563 | regval = F_MMU_PREFETCH_RT_REPLACE_MOD | |
564 | F_MMU_TF_PROT_TO_PROGRAM_ADDR_MT8173; | |
86444413 CH |
565 | } else { |
566 | regval = readl_relaxed(data->base + REG_MMU_CTRL_REG); | |
567 | regval |= F_MMU_TF_PROT_TO_PROGRAM_ADDR; | |
568 | } | |
0df4fabe YW |
569 | writel_relaxed(regval, data->base + REG_MMU_CTRL_REG); |
570 | ||
571 | regval = F_L2_MULIT_HIT_EN | | |
572 | F_TABLE_WALK_FAULT_INT_EN | | |
573 | F_PREETCH_FIFO_OVERFLOW_INT_EN | | |
574 | F_MISS_FIFO_OVERFLOW_INT_EN | | |
575 | F_PREFETCH_FIFO_ERR_INT_EN | | |
576 | F_MISS_FIFO_ERR_INT_EN; | |
577 | writel_relaxed(regval, data->base + REG_MMU_INT_CONTROL0); | |
578 | ||
579 | regval = F_INT_TRANSLATION_FAULT | | |
580 | F_INT_MAIN_MULTI_HIT_FAULT | | |
581 | F_INT_INVALID_PA_FAULT | | |
582 | F_INT_ENTRY_REPLACEMENT_FAULT | | |
583 | F_INT_TLB_MISS_FAULT | | |
584 | F_INT_MISS_TRANSACTION_FIFO_FAULT | | |
585 | F_INT_PRETETCH_TRANSATION_FIFO_FAULT; | |
586 | writel_relaxed(regval, data->base + REG_MMU_INT_MAIN_CONTROL); | |
587 | ||
d1b5ef00 | 588 | if (MTK_IOMMU_HAS_FLAG(data->plat_data, HAS_LEGACY_IVRP_PADDR)) |
70ca608b YW |
589 | regval = (data->protect_base >> 1) | (data->enable_4GB << 31); |
590 | else | |
591 | regval = lower_32_bits(data->protect_base) | | |
592 | upper_32_bits(data->protect_base); | |
593 | writel_relaxed(regval, data->base + REG_MMU_IVRP_PADDR); | |
594 | ||
6b717796 CH |
595 | if (data->enable_4GB && |
596 | MTK_IOMMU_HAS_FLAG(data->plat_data, HAS_VLD_PA_RNG)) { | |
30e2fccf YW |
597 | /* |
598 | * If 4GB mode is enabled, the validate PA range is from | |
599 | * 0x1_0000_0000 to 0x1_ffff_ffff. here record bit[32:30]. | |
600 | */ | |
601 | regval = F_MMU_VLD_PA_RNG(7, 4); | |
602 | writel_relaxed(regval, data->base + REG_MMU_VLD_PA_RNG); | |
603 | } | |
0df4fabe | 604 | writel_relaxed(0, data->base + REG_MMU_DCM_DIS); |
35c1b48d CH |
605 | if (MTK_IOMMU_HAS_FLAG(data->plat_data, WR_THROT_EN)) { |
606 | /* write command throttling mode */ | |
607 | regval = readl_relaxed(data->base + REG_MMU_WR_LEN_CTRL); | |
608 | regval &= ~F_MMU_WR_THROT_DIS_MASK; | |
609 | writel_relaxed(regval, data->base + REG_MMU_WR_LEN_CTRL); | |
610 | } | |
e6dec923 | 611 | |
6b717796 | 612 | if (MTK_IOMMU_HAS_FLAG(data->plat_data, RESET_AXI)) { |
75eed350 | 613 | /* The register is called STANDARD_AXI_MODE in this case */ |
4bb2bf4c CH |
614 | regval = 0; |
615 | } else { | |
616 | regval = readl_relaxed(data->base + REG_MMU_MISC_CTRL); | |
617 | regval &= ~F_MMU_STANDARD_AXI_MODE_MASK; | |
618 | if (MTK_IOMMU_HAS_FLAG(data->plat_data, OUT_ORDER_WR_EN)) | |
619 | regval &= ~F_MMU_IN_ORDER_WR_EN_MASK; | |
75eed350 | 620 | } |
4bb2bf4c | 621 | writel_relaxed(regval, data->base + REG_MMU_MISC_CTRL); |
0df4fabe YW |
622 | |
623 | if (devm_request_irq(data->dev, data->irq, mtk_iommu_isr, 0, | |
624 | dev_name(data->dev), (void *)data)) { | |
625 | writel_relaxed(0, data->base + REG_MMU_PT_BASE_ADDR); | |
626 | clk_disable_unprepare(data->bclk); | |
627 | dev_err(data->dev, "Failed @ IRQ-%d Request\n", data->irq); | |
628 | return -ENODEV; | |
629 | } | |
630 | ||
631 | return 0; | |
632 | } | |
633 | ||
0df4fabe YW |
634 | static const struct component_master_ops mtk_iommu_com_ops = { |
635 | .bind = mtk_iommu_bind, | |
636 | .unbind = mtk_iommu_unbind, | |
637 | }; | |
638 | ||
639 | static int mtk_iommu_probe(struct platform_device *pdev) | |
640 | { | |
641 | struct mtk_iommu_data *data; | |
642 | struct device *dev = &pdev->dev; | |
643 | struct resource *res; | |
b16c0170 | 644 | resource_size_t ioaddr; |
0df4fabe | 645 | struct component_match *match = NULL; |
c2c59456 | 646 | struct regmap *infracfg; |
0df4fabe | 647 | void *protect; |
0b6c0ad3 | 648 | int i, larb_nr, ret; |
c2c59456 MC |
649 | u32 val; |
650 | char *p; | |
0df4fabe YW |
651 | |
652 | data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL); | |
653 | if (!data) | |
654 | return -ENOMEM; | |
655 | data->dev = dev; | |
cecdce9d | 656 | data->plat_data = of_device_get_match_data(dev); |
0df4fabe YW |
657 | |
658 | /* Protect memory. HW will access here while translation fault.*/ | |
659 | protect = devm_kzalloc(dev, MTK_PROTECT_PA_ALIGN * 2, GFP_KERNEL); | |
660 | if (!protect) | |
661 | return -ENOMEM; | |
662 | data->protect_base = ALIGN(virt_to_phys(protect), MTK_PROTECT_PA_ALIGN); | |
663 | ||
c2c59456 MC |
664 | if (MTK_IOMMU_HAS_FLAG(data->plat_data, HAS_4GB_MODE)) { |
665 | switch (data->plat_data->m4u_plat) { | |
666 | case M4U_MT2712: | |
667 | p = "mediatek,mt2712-infracfg"; | |
668 | break; | |
669 | case M4U_MT8173: | |
670 | p = "mediatek,mt8173-infracfg"; | |
671 | break; | |
672 | default: | |
673 | p = NULL; | |
674 | } | |
675 | ||
676 | infracfg = syscon_regmap_lookup_by_compatible(p); | |
677 | ||
678 | if (IS_ERR(infracfg)) | |
679 | return PTR_ERR(infracfg); | |
680 | ||
681 | ret = regmap_read(infracfg, REG_INFRA_MISC, &val); | |
682 | if (ret) | |
683 | return ret; | |
684 | data->enable_4GB = !!(val & F_DDR_4GB_SUPPORT_EN); | |
685 | } | |
01e23c93 | 686 | |
0df4fabe YW |
687 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
688 | data->base = devm_ioremap_resource(dev, res); | |
689 | if (IS_ERR(data->base)) | |
690 | return PTR_ERR(data->base); | |
b16c0170 | 691 | ioaddr = res->start; |
0df4fabe YW |
692 | |
693 | data->irq = platform_get_irq(pdev, 0); | |
694 | if (data->irq < 0) | |
695 | return data->irq; | |
696 | ||
6b717796 | 697 | if (MTK_IOMMU_HAS_FLAG(data->plat_data, HAS_BCLK)) { |
2aa4c259 YW |
698 | data->bclk = devm_clk_get(dev, "bclk"); |
699 | if (IS_ERR(data->bclk)) | |
700 | return PTR_ERR(data->bclk); | |
701 | } | |
0df4fabe YW |
702 | |
703 | larb_nr = of_count_phandle_with_args(dev->of_node, | |
704 | "mediatek,larbs", NULL); | |
705 | if (larb_nr < 0) | |
706 | return larb_nr; | |
0df4fabe YW |
707 | |
708 | for (i = 0; i < larb_nr; i++) { | |
709 | struct device_node *larbnode; | |
710 | struct platform_device *plarbdev; | |
e6dec923 | 711 | u32 id; |
0df4fabe YW |
712 | |
713 | larbnode = of_parse_phandle(dev->of_node, "mediatek,larbs", i); | |
714 | if (!larbnode) | |
715 | return -EINVAL; | |
716 | ||
1eb8e4e2 WY |
717 | if (!of_device_is_available(larbnode)) { |
718 | of_node_put(larbnode); | |
0df4fabe | 719 | continue; |
1eb8e4e2 | 720 | } |
0df4fabe | 721 | |
e6dec923 YW |
722 | ret = of_property_read_u32(larbnode, "mediatek,larb-id", &id); |
723 | if (ret)/* The id is consecutive if there is no this property */ | |
724 | id = i; | |
725 | ||
0df4fabe | 726 | plarbdev = of_find_device_by_node(larbnode); |
1eb8e4e2 WY |
727 | if (!plarbdev) { |
728 | of_node_put(larbnode); | |
e6dec923 | 729 | return -EPROBE_DEFER; |
1eb8e4e2 | 730 | } |
1ee9feb2 | 731 | data->larb_imu[id].dev = &plarbdev->dev; |
0df4fabe | 732 | |
00c7c81f RK |
733 | component_match_add_release(dev, &match, release_of, |
734 | compare_of, larbnode); | |
0df4fabe YW |
735 | } |
736 | ||
737 | platform_set_drvdata(pdev, data); | |
738 | ||
739 | ret = mtk_iommu_hw_init(data); | |
740 | if (ret) | |
741 | return ret; | |
742 | ||
b16c0170 JR |
743 | ret = iommu_device_sysfs_add(&data->iommu, dev, NULL, |
744 | "mtk-iommu.%pa", &ioaddr); | |
745 | if (ret) | |
746 | return ret; | |
747 | ||
748 | iommu_device_set_ops(&data->iommu, &mtk_iommu_ops); | |
749 | iommu_device_set_fwnode(&data->iommu, &pdev->dev.of_node->fwnode); | |
750 | ||
751 | ret = iommu_device_register(&data->iommu); | |
752 | if (ret) | |
753 | return ret; | |
754 | ||
da3cc91b | 755 | spin_lock_init(&data->tlb_lock); |
7c3a2ec0 YW |
756 | list_add_tail(&data->list, &m4ulist); |
757 | ||
0df4fabe YW |
758 | if (!iommu_present(&platform_bus_type)) |
759 | bus_set_iommu(&platform_bus_type, &mtk_iommu_ops); | |
760 | ||
761 | return component_master_add_with_match(dev, &mtk_iommu_com_ops, match); | |
762 | } | |
763 | ||
764 | static int mtk_iommu_remove(struct platform_device *pdev) | |
765 | { | |
766 | struct mtk_iommu_data *data = platform_get_drvdata(pdev); | |
767 | ||
b16c0170 JR |
768 | iommu_device_sysfs_remove(&data->iommu); |
769 | iommu_device_unregister(&data->iommu); | |
770 | ||
0df4fabe YW |
771 | if (iommu_present(&platform_bus_type)) |
772 | bus_set_iommu(&platform_bus_type, NULL); | |
773 | ||
0df4fabe YW |
774 | clk_disable_unprepare(data->bclk); |
775 | devm_free_irq(&pdev->dev, data->irq, data); | |
776 | component_master_del(&pdev->dev, &mtk_iommu_com_ops); | |
777 | return 0; | |
778 | } | |
779 | ||
fd99f796 | 780 | static int __maybe_unused mtk_iommu_suspend(struct device *dev) |
0df4fabe YW |
781 | { |
782 | struct mtk_iommu_data *data = dev_get_drvdata(dev); | |
783 | struct mtk_iommu_suspend_reg *reg = &data->reg; | |
784 | void __iomem *base = data->base; | |
785 | ||
35c1b48d | 786 | reg->wr_len_ctrl = readl_relaxed(base + REG_MMU_WR_LEN_CTRL); |
75eed350 | 787 | reg->misc_ctrl = readl_relaxed(base + REG_MMU_MISC_CTRL); |
0df4fabe YW |
788 | reg->dcm_dis = readl_relaxed(base + REG_MMU_DCM_DIS); |
789 | reg->ctrl_reg = readl_relaxed(base + REG_MMU_CTRL_REG); | |
790 | reg->int_control0 = readl_relaxed(base + REG_MMU_INT_CONTROL0); | |
791 | reg->int_main_control = readl_relaxed(base + REG_MMU_INT_MAIN_CONTROL); | |
70ca608b | 792 | reg->ivrp_paddr = readl_relaxed(base + REG_MMU_IVRP_PADDR); |
b9475b34 | 793 | reg->vld_pa_rng = readl_relaxed(base + REG_MMU_VLD_PA_RNG); |
6254b64f | 794 | clk_disable_unprepare(data->bclk); |
0df4fabe YW |
795 | return 0; |
796 | } | |
797 | ||
fd99f796 | 798 | static int __maybe_unused mtk_iommu_resume(struct device *dev) |
0df4fabe YW |
799 | { |
800 | struct mtk_iommu_data *data = dev_get_drvdata(dev); | |
801 | struct mtk_iommu_suspend_reg *reg = &data->reg; | |
907ba6a1 | 802 | struct mtk_iommu_domain *m4u_dom = data->m4u_dom; |
0df4fabe | 803 | void __iomem *base = data->base; |
6254b64f | 804 | int ret; |
0df4fabe | 805 | |
6254b64f YW |
806 | ret = clk_prepare_enable(data->bclk); |
807 | if (ret) { | |
808 | dev_err(data->dev, "Failed to enable clk(%d) in resume\n", ret); | |
809 | return ret; | |
810 | } | |
35c1b48d | 811 | writel_relaxed(reg->wr_len_ctrl, base + REG_MMU_WR_LEN_CTRL); |
75eed350 | 812 | writel_relaxed(reg->misc_ctrl, base + REG_MMU_MISC_CTRL); |
0df4fabe YW |
813 | writel_relaxed(reg->dcm_dis, base + REG_MMU_DCM_DIS); |
814 | writel_relaxed(reg->ctrl_reg, base + REG_MMU_CTRL_REG); | |
815 | writel_relaxed(reg->int_control0, base + REG_MMU_INT_CONTROL0); | |
816 | writel_relaxed(reg->int_main_control, base + REG_MMU_INT_MAIN_CONTROL); | |
70ca608b | 817 | writel_relaxed(reg->ivrp_paddr, base + REG_MMU_IVRP_PADDR); |
b9475b34 | 818 | writel_relaxed(reg->vld_pa_rng, base + REG_MMU_VLD_PA_RNG); |
907ba6a1 | 819 | if (m4u_dom) |
d1e5f26f | 820 | writel(m4u_dom->cfg.arm_v7s_cfg.ttbr & MMU_PT_ADDR_MASK, |
e6dec923 | 821 | base + REG_MMU_PT_BASE_ADDR); |
0df4fabe YW |
822 | return 0; |
823 | } | |
824 | ||
e6dec923 | 825 | static const struct dev_pm_ops mtk_iommu_pm_ops = { |
6254b64f | 826 | SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(mtk_iommu_suspend, mtk_iommu_resume) |
0df4fabe YW |
827 | }; |
828 | ||
cecdce9d YW |
829 | static const struct mtk_iommu_plat_data mt2712_data = { |
830 | .m4u_plat = M4U_MT2712, | |
6b717796 | 831 | .flags = HAS_4GB_MODE | HAS_BCLK | HAS_VLD_PA_RNG, |
b053bc71 | 832 | .inv_sel_reg = REG_MMU_INV_SEL_GEN1, |
37276e00 | 833 | .larbid_remap = {{0}, {1}, {2}, {3}, {4}, {5}, {6}, {7}}, |
cecdce9d YW |
834 | }; |
835 | ||
068c86e9 CH |
836 | static const struct mtk_iommu_plat_data mt6779_data = { |
837 | .m4u_plat = M4U_MT6779, | |
838 | .flags = HAS_SUB_COMM | OUT_ORDER_WR_EN | WR_THROT_EN, | |
839 | .inv_sel_reg = REG_MMU_INV_SEL_GEN2, | |
840 | .larbid_remap = {{0}, {1}, {2}, {3}, {5}, {7, 8}, {10}, {9}}, | |
cecdce9d YW |
841 | }; |
842 | ||
843 | static const struct mtk_iommu_plat_data mt8173_data = { | |
844 | .m4u_plat = M4U_MT8173, | |
d1b5ef00 FP |
845 | .flags = HAS_4GB_MODE | HAS_BCLK | RESET_AXI | |
846 | HAS_LEGACY_IVRP_PADDR, | |
b053bc71 | 847 | .inv_sel_reg = REG_MMU_INV_SEL_GEN1, |
37276e00 | 848 | .larbid_remap = {{0}, {1}, {2}, {3}, {4}, {5}}, /* Linear mapping. */ |
cecdce9d YW |
849 | }; |
850 | ||
907ba6a1 YW |
851 | static const struct mtk_iommu_plat_data mt8183_data = { |
852 | .m4u_plat = M4U_MT8183, | |
6b717796 | 853 | .flags = RESET_AXI, |
b053bc71 | 854 | .inv_sel_reg = REG_MMU_INV_SEL_GEN1, |
37276e00 | 855 | .larbid_remap = {{0}, {4}, {5}, {6}, {7}, {2}, {3}, {1}}, |
907ba6a1 YW |
856 | }; |
857 | ||
0df4fabe | 858 | static const struct of_device_id mtk_iommu_of_ids[] = { |
cecdce9d | 859 | { .compatible = "mediatek,mt2712-m4u", .data = &mt2712_data}, |
068c86e9 | 860 | { .compatible = "mediatek,mt6779-m4u", .data = &mt6779_data}, |
cecdce9d | 861 | { .compatible = "mediatek,mt8173-m4u", .data = &mt8173_data}, |
907ba6a1 | 862 | { .compatible = "mediatek,mt8183-m4u", .data = &mt8183_data}, |
0df4fabe YW |
863 | {} |
864 | }; | |
865 | ||
866 | static struct platform_driver mtk_iommu_driver = { | |
867 | .probe = mtk_iommu_probe, | |
868 | .remove = mtk_iommu_remove, | |
869 | .driver = { | |
870 | .name = "mtk-iommu", | |
f53dd978 | 871 | .of_match_table = mtk_iommu_of_ids, |
0df4fabe YW |
872 | .pm = &mtk_iommu_pm_ops, |
873 | } | |
874 | }; | |
875 | ||
e6dec923 | 876 | static int __init mtk_iommu_init(void) |
0df4fabe YW |
877 | { |
878 | int ret; | |
0df4fabe YW |
879 | |
880 | ret = platform_driver_register(&mtk_iommu_driver); | |
e6dec923 YW |
881 | if (ret != 0) |
882 | pr_err("Failed to register MTK IOMMU driver\n"); | |
0df4fabe | 883 | |
e6dec923 | 884 | return ret; |
0df4fabe YW |
885 | } |
886 | ||
e6dec923 | 887 | subsys_initcall(mtk_iommu_init) |