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Commit | Line | Data |
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a9dcad5e HD |
1 | /* |
2 | * omap iommu: tlb and pagetable primitives | |
3 | * | |
c127c7dc | 4 | * Copyright (C) 2008-2010 Nokia Corporation |
a9dcad5e HD |
5 | * |
6 | * Written by Hiroshi DOYU <Hiroshi.DOYU@nokia.com>, | |
7 | * Paul Mundt and Toshihiro Kobayashi | |
8 | * | |
9 | * This program is free software; you can redistribute it and/or modify | |
10 | * it under the terms of the GNU General Public License version 2 as | |
11 | * published by the Free Software Foundation. | |
12 | */ | |
13 | ||
14 | #include <linux/err.h> | |
15 | #include <linux/module.h> | |
5a0e3ad6 | 16 | #include <linux/slab.h> |
a9dcad5e HD |
17 | #include <linux/interrupt.h> |
18 | #include <linux/ioport.h> | |
19 | #include <linux/clk.h> | |
20 | #include <linux/platform_device.h> | |
f626b52d OBC |
21 | #include <linux/iommu.h> |
22 | #include <linux/mutex.h> | |
23 | #include <linux/spinlock.h> | |
a9dcad5e HD |
24 | |
25 | #include <asm/cacheflush.h> | |
26 | ||
ce491cf8 | 27 | #include <plat/iommu.h> |
a9dcad5e | 28 | |
fcf3a6ef | 29 | #include <plat/iopgtable.h> |
a9dcad5e | 30 | |
37c2836c HD |
31 | #define for_each_iotlb_cr(obj, n, __i, cr) \ |
32 | for (__i = 0; \ | |
33 | (__i < (n)) && (cr = __iotlb_read_cr((obj), __i), true); \ | |
34 | __i++) | |
35 | ||
f626b52d OBC |
36 | /** |
37 | * struct omap_iommu_domain - omap iommu domain | |
38 | * @pgtable: the page table | |
39 | * @iommu_dev: an omap iommu device attached to this domain. only a single | |
40 | * iommu device can be attached for now. | |
41 | * @lock: domain lock, should be taken when attaching/detaching | |
42 | */ | |
43 | struct omap_iommu_domain { | |
44 | u32 *pgtable; | |
6c32df43 | 45 | struct omap_iommu *iommu_dev; |
f626b52d OBC |
46 | spinlock_t lock; |
47 | }; | |
48 | ||
a9dcad5e HD |
49 | /* accommodate the difference between omap1 and omap2/3 */ |
50 | static const struct iommu_functions *arch_iommu; | |
51 | ||
52 | static struct platform_driver omap_iommu_driver; | |
53 | static struct kmem_cache *iopte_cachep; | |
54 | ||
55 | /** | |
6c32df43 | 56 | * omap_install_iommu_arch - Install archtecure specific iommu functions |
a9dcad5e HD |
57 | * @ops: a pointer to architecture specific iommu functions |
58 | * | |
59 | * There are several kind of iommu algorithm(tlb, pagetable) among | |
60 | * omap series. This interface installs such an iommu algorighm. | |
61 | **/ | |
6c32df43 | 62 | int omap_install_iommu_arch(const struct iommu_functions *ops) |
a9dcad5e HD |
63 | { |
64 | if (arch_iommu) | |
65 | return -EBUSY; | |
66 | ||
67 | arch_iommu = ops; | |
68 | return 0; | |
69 | } | |
6c32df43 | 70 | EXPORT_SYMBOL_GPL(omap_install_iommu_arch); |
a9dcad5e HD |
71 | |
72 | /** | |
6c32df43 | 73 | * omap_uninstall_iommu_arch - Uninstall archtecure specific iommu functions |
a9dcad5e HD |
74 | * @ops: a pointer to architecture specific iommu functions |
75 | * | |
76 | * This interface uninstalls the iommu algorighm installed previously. | |
77 | **/ | |
6c32df43 | 78 | void omap_uninstall_iommu_arch(const struct iommu_functions *ops) |
a9dcad5e HD |
79 | { |
80 | if (arch_iommu != ops) | |
81 | pr_err("%s: not your arch\n", __func__); | |
82 | ||
83 | arch_iommu = NULL; | |
84 | } | |
6c32df43 | 85 | EXPORT_SYMBOL_GPL(omap_uninstall_iommu_arch); |
a9dcad5e HD |
86 | |
87 | /** | |
6c32df43 | 88 | * omap_iommu_save_ctx - Save registers for pm off-mode support |
a9dcad5e HD |
89 | * @obj: target iommu |
90 | **/ | |
6c32df43 | 91 | void omap_iommu_save_ctx(struct omap_iommu *obj) |
a9dcad5e HD |
92 | { |
93 | arch_iommu->save_ctx(obj); | |
94 | } | |
6c32df43 | 95 | EXPORT_SYMBOL_GPL(omap_iommu_save_ctx); |
a9dcad5e HD |
96 | |
97 | /** | |
6c32df43 | 98 | * omap_iommu_restore_ctx - Restore registers for pm off-mode support |
a9dcad5e HD |
99 | * @obj: target iommu |
100 | **/ | |
6c32df43 | 101 | void omap_iommu_restore_ctx(struct omap_iommu *obj) |
a9dcad5e HD |
102 | { |
103 | arch_iommu->restore_ctx(obj); | |
104 | } | |
6c32df43 | 105 | EXPORT_SYMBOL_GPL(omap_iommu_restore_ctx); |
a9dcad5e HD |
106 | |
107 | /** | |
6c32df43 | 108 | * omap_iommu_arch_version - Return running iommu arch version |
a9dcad5e | 109 | **/ |
6c32df43 | 110 | u32 omap_iommu_arch_version(void) |
a9dcad5e HD |
111 | { |
112 | return arch_iommu->version; | |
113 | } | |
6c32df43 | 114 | EXPORT_SYMBOL_GPL(omap_iommu_arch_version); |
a9dcad5e | 115 | |
6c32df43 | 116 | static int iommu_enable(struct omap_iommu *obj) |
a9dcad5e HD |
117 | { |
118 | int err; | |
119 | ||
120 | if (!obj) | |
121 | return -EINVAL; | |
122 | ||
ef4815ab MH |
123 | if (!arch_iommu) |
124 | return -ENODEV; | |
125 | ||
a9dcad5e HD |
126 | clk_enable(obj->clk); |
127 | ||
128 | err = arch_iommu->enable(obj); | |
129 | ||
130 | clk_disable(obj->clk); | |
131 | return err; | |
132 | } | |
133 | ||
6c32df43 | 134 | static void iommu_disable(struct omap_iommu *obj) |
a9dcad5e HD |
135 | { |
136 | if (!obj) | |
137 | return; | |
138 | ||
139 | clk_enable(obj->clk); | |
140 | ||
141 | arch_iommu->disable(obj); | |
142 | ||
143 | clk_disable(obj->clk); | |
144 | } | |
145 | ||
146 | /* | |
147 | * TLB operations | |
148 | */ | |
6c32df43 | 149 | void omap_iotlb_cr_to_e(struct cr_regs *cr, struct iotlb_entry *e) |
a9dcad5e HD |
150 | { |
151 | BUG_ON(!cr || !e); | |
152 | ||
153 | arch_iommu->cr_to_e(cr, e); | |
154 | } | |
6c32df43 | 155 | EXPORT_SYMBOL_GPL(omap_iotlb_cr_to_e); |
a9dcad5e HD |
156 | |
157 | static inline int iotlb_cr_valid(struct cr_regs *cr) | |
158 | { | |
159 | if (!cr) | |
160 | return -EINVAL; | |
161 | ||
162 | return arch_iommu->cr_valid(cr); | |
163 | } | |
164 | ||
6c32df43 | 165 | static inline struct cr_regs *iotlb_alloc_cr(struct omap_iommu *obj, |
a9dcad5e HD |
166 | struct iotlb_entry *e) |
167 | { | |
168 | if (!e) | |
169 | return NULL; | |
170 | ||
171 | return arch_iommu->alloc_cr(obj, e); | |
172 | } | |
173 | ||
e1f23813 | 174 | static u32 iotlb_cr_to_virt(struct cr_regs *cr) |
a9dcad5e HD |
175 | { |
176 | return arch_iommu->cr_to_virt(cr); | |
177 | } | |
a9dcad5e HD |
178 | |
179 | static u32 get_iopte_attr(struct iotlb_entry *e) | |
180 | { | |
181 | return arch_iommu->get_pte_attr(e); | |
182 | } | |
183 | ||
6c32df43 | 184 | static u32 iommu_report_fault(struct omap_iommu *obj, u32 *da) |
a9dcad5e HD |
185 | { |
186 | return arch_iommu->fault_isr(obj, da); | |
187 | } | |
188 | ||
6c32df43 | 189 | static void iotlb_lock_get(struct omap_iommu *obj, struct iotlb_lock *l) |
a9dcad5e HD |
190 | { |
191 | u32 val; | |
192 | ||
193 | val = iommu_read_reg(obj, MMU_LOCK); | |
194 | ||
195 | l->base = MMU_LOCK_BASE(val); | |
196 | l->vict = MMU_LOCK_VICT(val); | |
197 | ||
a9dcad5e HD |
198 | } |
199 | ||
6c32df43 | 200 | static void iotlb_lock_set(struct omap_iommu *obj, struct iotlb_lock *l) |
a9dcad5e HD |
201 | { |
202 | u32 val; | |
203 | ||
a9dcad5e HD |
204 | val = (l->base << MMU_LOCK_BASE_SHIFT); |
205 | val |= (l->vict << MMU_LOCK_VICT_SHIFT); | |
206 | ||
207 | iommu_write_reg(obj, val, MMU_LOCK); | |
208 | } | |
209 | ||
6c32df43 | 210 | static void iotlb_read_cr(struct omap_iommu *obj, struct cr_regs *cr) |
a9dcad5e HD |
211 | { |
212 | arch_iommu->tlb_read_cr(obj, cr); | |
213 | } | |
214 | ||
6c32df43 | 215 | static void iotlb_load_cr(struct omap_iommu *obj, struct cr_regs *cr) |
a9dcad5e HD |
216 | { |
217 | arch_iommu->tlb_load_cr(obj, cr); | |
218 | ||
219 | iommu_write_reg(obj, 1, MMU_FLUSH_ENTRY); | |
220 | iommu_write_reg(obj, 1, MMU_LD_TLB); | |
221 | } | |
222 | ||
223 | /** | |
224 | * iotlb_dump_cr - Dump an iommu tlb entry into buf | |
225 | * @obj: target iommu | |
226 | * @cr: contents of cam and ram register | |
227 | * @buf: output buffer | |
228 | **/ | |
6c32df43 | 229 | static inline ssize_t iotlb_dump_cr(struct omap_iommu *obj, struct cr_regs *cr, |
a9dcad5e HD |
230 | char *buf) |
231 | { | |
232 | BUG_ON(!cr || !buf); | |
233 | ||
234 | return arch_iommu->dump_cr(obj, cr, buf); | |
235 | } | |
236 | ||
37c2836c | 237 | /* only used in iotlb iteration for-loop */ |
6c32df43 | 238 | static struct cr_regs __iotlb_read_cr(struct omap_iommu *obj, int n) |
37c2836c HD |
239 | { |
240 | struct cr_regs cr; | |
241 | struct iotlb_lock l; | |
242 | ||
243 | iotlb_lock_get(obj, &l); | |
244 | l.vict = n; | |
245 | iotlb_lock_set(obj, &l); | |
246 | iotlb_read_cr(obj, &cr); | |
247 | ||
248 | return cr; | |
249 | } | |
250 | ||
a9dcad5e HD |
251 | /** |
252 | * load_iotlb_entry - Set an iommu tlb entry | |
253 | * @obj: target iommu | |
254 | * @e: an iommu tlb entry info | |
255 | **/ | |
5da14a47 | 256 | #ifdef PREFETCH_IOTLB |
6c32df43 | 257 | static int load_iotlb_entry(struct omap_iommu *obj, struct iotlb_entry *e) |
a9dcad5e | 258 | { |
a9dcad5e HD |
259 | int err = 0; |
260 | struct iotlb_lock l; | |
261 | struct cr_regs *cr; | |
262 | ||
263 | if (!obj || !obj->nr_tlb_entries || !e) | |
264 | return -EINVAL; | |
265 | ||
266 | clk_enable(obj->clk); | |
267 | ||
be6d8026 KH |
268 | iotlb_lock_get(obj, &l); |
269 | if (l.base == obj->nr_tlb_entries) { | |
270 | dev_warn(obj->dev, "%s: preserve entries full\n", __func__); | |
a9dcad5e HD |
271 | err = -EBUSY; |
272 | goto out; | |
273 | } | |
be6d8026 | 274 | if (!e->prsvd) { |
37c2836c HD |
275 | int i; |
276 | struct cr_regs tmp; | |
be6d8026 | 277 | |
37c2836c | 278 | for_each_iotlb_cr(obj, obj->nr_tlb_entries, i, tmp) |
be6d8026 KH |
279 | if (!iotlb_cr_valid(&tmp)) |
280 | break; | |
37c2836c | 281 | |
be6d8026 KH |
282 | if (i == obj->nr_tlb_entries) { |
283 | dev_dbg(obj->dev, "%s: full: no entry\n", __func__); | |
284 | err = -EBUSY; | |
285 | goto out; | |
286 | } | |
37c2836c HD |
287 | |
288 | iotlb_lock_get(obj, &l); | |
be6d8026 KH |
289 | } else { |
290 | l.vict = l.base; | |
291 | iotlb_lock_set(obj, &l); | |
292 | } | |
a9dcad5e HD |
293 | |
294 | cr = iotlb_alloc_cr(obj, e); | |
295 | if (IS_ERR(cr)) { | |
296 | clk_disable(obj->clk); | |
297 | return PTR_ERR(cr); | |
298 | } | |
299 | ||
300 | iotlb_load_cr(obj, cr); | |
301 | kfree(cr); | |
302 | ||
be6d8026 KH |
303 | if (e->prsvd) |
304 | l.base++; | |
a9dcad5e HD |
305 | /* increment victim for next tlb load */ |
306 | if (++l.vict == obj->nr_tlb_entries) | |
be6d8026 | 307 | l.vict = l.base; |
a9dcad5e HD |
308 | iotlb_lock_set(obj, &l); |
309 | out: | |
310 | clk_disable(obj->clk); | |
311 | return err; | |
312 | } | |
a9dcad5e | 313 | |
5da14a47 OBC |
314 | #else /* !PREFETCH_IOTLB */ |
315 | ||
6c32df43 | 316 | static int load_iotlb_entry(struct omap_iommu *obj, struct iotlb_entry *e) |
5da14a47 OBC |
317 | { |
318 | return 0; | |
319 | } | |
320 | ||
321 | #endif /* !PREFETCH_IOTLB */ | |
322 | ||
6c32df43 | 323 | static int prefetch_iotlb_entry(struct omap_iommu *obj, struct iotlb_entry *e) |
5da14a47 OBC |
324 | { |
325 | return load_iotlb_entry(obj, e); | |
326 | } | |
327 | ||
a9dcad5e HD |
328 | /** |
329 | * flush_iotlb_page - Clear an iommu tlb entry | |
330 | * @obj: target iommu | |
331 | * @da: iommu device virtual address | |
332 | * | |
333 | * Clear an iommu tlb entry which includes 'da' address. | |
334 | **/ | |
6c32df43 | 335 | static void flush_iotlb_page(struct omap_iommu *obj, u32 da) |
a9dcad5e | 336 | { |
a9dcad5e | 337 | int i; |
37c2836c | 338 | struct cr_regs cr; |
a9dcad5e HD |
339 | |
340 | clk_enable(obj->clk); | |
341 | ||
37c2836c | 342 | for_each_iotlb_cr(obj, obj->nr_tlb_entries, i, cr) { |
a9dcad5e HD |
343 | u32 start; |
344 | size_t bytes; | |
345 | ||
a9dcad5e HD |
346 | if (!iotlb_cr_valid(&cr)) |
347 | continue; | |
348 | ||
349 | start = iotlb_cr_to_virt(&cr); | |
350 | bytes = iopgsz_to_bytes(cr.cam & 3); | |
351 | ||
352 | if ((start <= da) && (da < start + bytes)) { | |
353 | dev_dbg(obj->dev, "%s: %08x<=%08x(%x)\n", | |
354 | __func__, start, da, bytes); | |
0fa035e5 | 355 | iotlb_load_cr(obj, &cr); |
a9dcad5e HD |
356 | iommu_write_reg(obj, 1, MMU_FLUSH_ENTRY); |
357 | } | |
358 | } | |
359 | clk_disable(obj->clk); | |
360 | ||
361 | if (i == obj->nr_tlb_entries) | |
362 | dev_dbg(obj->dev, "%s: no page for %08x\n", __func__, da); | |
363 | } | |
a9dcad5e | 364 | |
a9dcad5e HD |
365 | /** |
366 | * flush_iotlb_all - Clear all iommu tlb entries | |
367 | * @obj: target iommu | |
368 | **/ | |
6c32df43 | 369 | static void flush_iotlb_all(struct omap_iommu *obj) |
a9dcad5e HD |
370 | { |
371 | struct iotlb_lock l; | |
372 | ||
373 | clk_enable(obj->clk); | |
374 | ||
375 | l.base = 0; | |
376 | l.vict = 0; | |
377 | iotlb_lock_set(obj, &l); | |
378 | ||
379 | iommu_write_reg(obj, 1, MMU_GFLUSH); | |
380 | ||
381 | clk_disable(obj->clk); | |
382 | } | |
a9dcad5e HD |
383 | |
384 | #if defined(CONFIG_OMAP_IOMMU_DEBUG_MODULE) | |
385 | ||
6c32df43 | 386 | ssize_t omap_iommu_dump_ctx(struct omap_iommu *obj, char *buf, ssize_t bytes) |
a9dcad5e | 387 | { |
a9dcad5e HD |
388 | if (!obj || !buf) |
389 | return -EINVAL; | |
390 | ||
391 | clk_enable(obj->clk); | |
392 | ||
14e0e679 | 393 | bytes = arch_iommu->dump_ctx(obj, buf, bytes); |
a9dcad5e HD |
394 | |
395 | clk_disable(obj->clk); | |
396 | ||
397 | return bytes; | |
398 | } | |
6c32df43 | 399 | EXPORT_SYMBOL_GPL(omap_iommu_dump_ctx); |
a9dcad5e | 400 | |
6c32df43 OBC |
401 | static int |
402 | __dump_tlb_entries(struct omap_iommu *obj, struct cr_regs *crs, int num) | |
a9dcad5e HD |
403 | { |
404 | int i; | |
37c2836c HD |
405 | struct iotlb_lock saved; |
406 | struct cr_regs tmp; | |
a9dcad5e HD |
407 | struct cr_regs *p = crs; |
408 | ||
409 | clk_enable(obj->clk); | |
a9dcad5e | 410 | iotlb_lock_get(obj, &saved); |
a9dcad5e | 411 | |
37c2836c | 412 | for_each_iotlb_cr(obj, num, i, tmp) { |
a9dcad5e HD |
413 | if (!iotlb_cr_valid(&tmp)) |
414 | continue; | |
a9dcad5e HD |
415 | *p++ = tmp; |
416 | } | |
37c2836c | 417 | |
a9dcad5e HD |
418 | iotlb_lock_set(obj, &saved); |
419 | clk_disable(obj->clk); | |
420 | ||
421 | return p - crs; | |
422 | } | |
423 | ||
424 | /** | |
6c32df43 | 425 | * omap_dump_tlb_entries - dump cr arrays to given buffer |
a9dcad5e HD |
426 | * @obj: target iommu |
427 | * @buf: output buffer | |
428 | **/ | |
6c32df43 | 429 | size_t omap_dump_tlb_entries(struct omap_iommu *obj, char *buf, ssize_t bytes) |
a9dcad5e | 430 | { |
14e0e679 | 431 | int i, num; |
a9dcad5e HD |
432 | struct cr_regs *cr; |
433 | char *p = buf; | |
434 | ||
14e0e679 HD |
435 | num = bytes / sizeof(*cr); |
436 | num = min(obj->nr_tlb_entries, num); | |
437 | ||
438 | cr = kcalloc(num, sizeof(*cr), GFP_KERNEL); | |
a9dcad5e HD |
439 | if (!cr) |
440 | return 0; | |
441 | ||
14e0e679 HD |
442 | num = __dump_tlb_entries(obj, cr, num); |
443 | for (i = 0; i < num; i++) | |
a9dcad5e HD |
444 | p += iotlb_dump_cr(obj, cr + i, p); |
445 | kfree(cr); | |
446 | ||
447 | return p - buf; | |
448 | } | |
6c32df43 | 449 | EXPORT_SYMBOL_GPL(omap_dump_tlb_entries); |
a9dcad5e | 450 | |
6c32df43 | 451 | int omap_foreach_iommu_device(void *data, int (*fn)(struct device *, void *)) |
a9dcad5e HD |
452 | { |
453 | return driver_for_each_device(&omap_iommu_driver.driver, | |
454 | NULL, data, fn); | |
455 | } | |
6c32df43 | 456 | EXPORT_SYMBOL_GPL(omap_foreach_iommu_device); |
a9dcad5e HD |
457 | |
458 | #endif /* CONFIG_OMAP_IOMMU_DEBUG_MODULE */ | |
459 | ||
460 | /* | |
461 | * H/W pagetable operations | |
462 | */ | |
463 | static void flush_iopgd_range(u32 *first, u32 *last) | |
464 | { | |
465 | /* FIXME: L2 cache should be taken care of if it exists */ | |
466 | do { | |
467 | asm("mcr p15, 0, %0, c7, c10, 1 @ flush_pgd" | |
468 | : : "r" (first)); | |
469 | first += L1_CACHE_BYTES / sizeof(*first); | |
470 | } while (first <= last); | |
471 | } | |
472 | ||
473 | static void flush_iopte_range(u32 *first, u32 *last) | |
474 | { | |
475 | /* FIXME: L2 cache should be taken care of if it exists */ | |
476 | do { | |
477 | asm("mcr p15, 0, %0, c7, c10, 1 @ flush_pte" | |
478 | : : "r" (first)); | |
479 | first += L1_CACHE_BYTES / sizeof(*first); | |
480 | } while (first <= last); | |
481 | } | |
482 | ||
483 | static void iopte_free(u32 *iopte) | |
484 | { | |
485 | /* Note: freed iopte's must be clean ready for re-use */ | |
486 | kmem_cache_free(iopte_cachep, iopte); | |
487 | } | |
488 | ||
6c32df43 | 489 | static u32 *iopte_alloc(struct omap_iommu *obj, u32 *iopgd, u32 da) |
a9dcad5e HD |
490 | { |
491 | u32 *iopte; | |
492 | ||
493 | /* a table has already existed */ | |
494 | if (*iopgd) | |
495 | goto pte_ready; | |
496 | ||
497 | /* | |
498 | * do the allocation outside the page table lock | |
499 | */ | |
500 | spin_unlock(&obj->page_table_lock); | |
501 | iopte = kmem_cache_zalloc(iopte_cachep, GFP_KERNEL); | |
502 | spin_lock(&obj->page_table_lock); | |
503 | ||
504 | if (!*iopgd) { | |
505 | if (!iopte) | |
506 | return ERR_PTR(-ENOMEM); | |
507 | ||
508 | *iopgd = virt_to_phys(iopte) | IOPGD_TABLE; | |
509 | flush_iopgd_range(iopgd, iopgd); | |
510 | ||
511 | dev_vdbg(obj->dev, "%s: a new pte:%p\n", __func__, iopte); | |
512 | } else { | |
513 | /* We raced, free the reduniovant table */ | |
514 | iopte_free(iopte); | |
515 | } | |
516 | ||
517 | pte_ready: | |
518 | iopte = iopte_offset(iopgd, da); | |
519 | ||
520 | dev_vdbg(obj->dev, | |
521 | "%s: da:%08x pgd:%p *pgd:%08x pte:%p *pte:%08x\n", | |
522 | __func__, da, iopgd, *iopgd, iopte, *iopte); | |
523 | ||
524 | return iopte; | |
525 | } | |
526 | ||
6c32df43 | 527 | static int iopgd_alloc_section(struct omap_iommu *obj, u32 da, u32 pa, u32 prot) |
a9dcad5e HD |
528 | { |
529 | u32 *iopgd = iopgd_offset(obj, da); | |
530 | ||
4abb7617 HD |
531 | if ((da | pa) & ~IOSECTION_MASK) { |
532 | dev_err(obj->dev, "%s: %08x:%08x should aligned on %08lx\n", | |
533 | __func__, da, pa, IOSECTION_SIZE); | |
534 | return -EINVAL; | |
535 | } | |
536 | ||
a9dcad5e HD |
537 | *iopgd = (pa & IOSECTION_MASK) | prot | IOPGD_SECTION; |
538 | flush_iopgd_range(iopgd, iopgd); | |
539 | return 0; | |
540 | } | |
541 | ||
6c32df43 | 542 | static int iopgd_alloc_super(struct omap_iommu *obj, u32 da, u32 pa, u32 prot) |
a9dcad5e HD |
543 | { |
544 | u32 *iopgd = iopgd_offset(obj, da); | |
545 | int i; | |
546 | ||
4abb7617 HD |
547 | if ((da | pa) & ~IOSUPER_MASK) { |
548 | dev_err(obj->dev, "%s: %08x:%08x should aligned on %08lx\n", | |
549 | __func__, da, pa, IOSUPER_SIZE); | |
550 | return -EINVAL; | |
551 | } | |
552 | ||
a9dcad5e HD |
553 | for (i = 0; i < 16; i++) |
554 | *(iopgd + i) = (pa & IOSUPER_MASK) | prot | IOPGD_SUPER; | |
555 | flush_iopgd_range(iopgd, iopgd + 15); | |
556 | return 0; | |
557 | } | |
558 | ||
6c32df43 | 559 | static int iopte_alloc_page(struct omap_iommu *obj, u32 da, u32 pa, u32 prot) |
a9dcad5e HD |
560 | { |
561 | u32 *iopgd = iopgd_offset(obj, da); | |
562 | u32 *iopte = iopte_alloc(obj, iopgd, da); | |
563 | ||
564 | if (IS_ERR(iopte)) | |
565 | return PTR_ERR(iopte); | |
566 | ||
567 | *iopte = (pa & IOPAGE_MASK) | prot | IOPTE_SMALL; | |
568 | flush_iopte_range(iopte, iopte); | |
569 | ||
570 | dev_vdbg(obj->dev, "%s: da:%08x pa:%08x pte:%p *pte:%08x\n", | |
571 | __func__, da, pa, iopte, *iopte); | |
572 | ||
573 | return 0; | |
574 | } | |
575 | ||
6c32df43 | 576 | static int iopte_alloc_large(struct omap_iommu *obj, u32 da, u32 pa, u32 prot) |
a9dcad5e HD |
577 | { |
578 | u32 *iopgd = iopgd_offset(obj, da); | |
579 | u32 *iopte = iopte_alloc(obj, iopgd, da); | |
580 | int i; | |
581 | ||
4abb7617 HD |
582 | if ((da | pa) & ~IOLARGE_MASK) { |
583 | dev_err(obj->dev, "%s: %08x:%08x should aligned on %08lx\n", | |
584 | __func__, da, pa, IOLARGE_SIZE); | |
585 | return -EINVAL; | |
586 | } | |
587 | ||
a9dcad5e HD |
588 | if (IS_ERR(iopte)) |
589 | return PTR_ERR(iopte); | |
590 | ||
591 | for (i = 0; i < 16; i++) | |
592 | *(iopte + i) = (pa & IOLARGE_MASK) | prot | IOPTE_LARGE; | |
593 | flush_iopte_range(iopte, iopte + 15); | |
594 | return 0; | |
595 | } | |
596 | ||
6c32df43 OBC |
597 | static int |
598 | iopgtable_store_entry_core(struct omap_iommu *obj, struct iotlb_entry *e) | |
a9dcad5e | 599 | { |
6c32df43 | 600 | int (*fn)(struct omap_iommu *, u32, u32, u32); |
a9dcad5e HD |
601 | u32 prot; |
602 | int err; | |
603 | ||
604 | if (!obj || !e) | |
605 | return -EINVAL; | |
606 | ||
607 | switch (e->pgsz) { | |
608 | case MMU_CAM_PGSZ_16M: | |
609 | fn = iopgd_alloc_super; | |
610 | break; | |
611 | case MMU_CAM_PGSZ_1M: | |
612 | fn = iopgd_alloc_section; | |
613 | break; | |
614 | case MMU_CAM_PGSZ_64K: | |
615 | fn = iopte_alloc_large; | |
616 | break; | |
617 | case MMU_CAM_PGSZ_4K: | |
618 | fn = iopte_alloc_page; | |
619 | break; | |
620 | default: | |
621 | fn = NULL; | |
622 | BUG(); | |
623 | break; | |
624 | } | |
625 | ||
626 | prot = get_iopte_attr(e); | |
627 | ||
628 | spin_lock(&obj->page_table_lock); | |
629 | err = fn(obj, e->da, e->pa, prot); | |
630 | spin_unlock(&obj->page_table_lock); | |
631 | ||
632 | return err; | |
633 | } | |
634 | ||
635 | /** | |
6c32df43 | 636 | * omap_iopgtable_store_entry - Make an iommu pte entry |
a9dcad5e HD |
637 | * @obj: target iommu |
638 | * @e: an iommu tlb entry info | |
639 | **/ | |
6c32df43 | 640 | int omap_iopgtable_store_entry(struct omap_iommu *obj, struct iotlb_entry *e) |
a9dcad5e HD |
641 | { |
642 | int err; | |
643 | ||
644 | flush_iotlb_page(obj, e->da); | |
645 | err = iopgtable_store_entry_core(obj, e); | |
a9dcad5e | 646 | if (!err) |
5da14a47 | 647 | prefetch_iotlb_entry(obj, e); |
a9dcad5e HD |
648 | return err; |
649 | } | |
6c32df43 | 650 | EXPORT_SYMBOL_GPL(omap_iopgtable_store_entry); |
a9dcad5e HD |
651 | |
652 | /** | |
653 | * iopgtable_lookup_entry - Lookup an iommu pte entry | |
654 | * @obj: target iommu | |
655 | * @da: iommu device virtual address | |
656 | * @ppgd: iommu pgd entry pointer to be returned | |
657 | * @ppte: iommu pte entry pointer to be returned | |
658 | **/ | |
e1f23813 OBC |
659 | static void |
660 | iopgtable_lookup_entry(struct omap_iommu *obj, u32 da, u32 **ppgd, u32 **ppte) | |
a9dcad5e HD |
661 | { |
662 | u32 *iopgd, *iopte = NULL; | |
663 | ||
664 | iopgd = iopgd_offset(obj, da); | |
665 | if (!*iopgd) | |
666 | goto out; | |
667 | ||
a1a54456 | 668 | if (iopgd_is_table(*iopgd)) |
a9dcad5e HD |
669 | iopte = iopte_offset(iopgd, da); |
670 | out: | |
671 | *ppgd = iopgd; | |
672 | *ppte = iopte; | |
673 | } | |
a9dcad5e | 674 | |
6c32df43 | 675 | static size_t iopgtable_clear_entry_core(struct omap_iommu *obj, u32 da) |
a9dcad5e HD |
676 | { |
677 | size_t bytes; | |
678 | u32 *iopgd = iopgd_offset(obj, da); | |
679 | int nent = 1; | |
680 | ||
681 | if (!*iopgd) | |
682 | return 0; | |
683 | ||
a1a54456 | 684 | if (iopgd_is_table(*iopgd)) { |
a9dcad5e HD |
685 | int i; |
686 | u32 *iopte = iopte_offset(iopgd, da); | |
687 | ||
688 | bytes = IOPTE_SIZE; | |
689 | if (*iopte & IOPTE_LARGE) { | |
690 | nent *= 16; | |
691 | /* rewind to the 1st entry */ | |
c127c7dc | 692 | iopte = iopte_offset(iopgd, (da & IOLARGE_MASK)); |
a9dcad5e HD |
693 | } |
694 | bytes *= nent; | |
695 | memset(iopte, 0, nent * sizeof(*iopte)); | |
696 | flush_iopte_range(iopte, iopte + (nent - 1) * sizeof(*iopte)); | |
697 | ||
698 | /* | |
699 | * do table walk to check if this table is necessary or not | |
700 | */ | |
701 | iopte = iopte_offset(iopgd, 0); | |
702 | for (i = 0; i < PTRS_PER_IOPTE; i++) | |
703 | if (iopte[i]) | |
704 | goto out; | |
705 | ||
706 | iopte_free(iopte); | |
707 | nent = 1; /* for the next L1 entry */ | |
708 | } else { | |
709 | bytes = IOPGD_SIZE; | |
dcc730dc | 710 | if ((*iopgd & IOPGD_SUPER) == IOPGD_SUPER) { |
a9dcad5e HD |
711 | nent *= 16; |
712 | /* rewind to the 1st entry */ | |
8d33ea58 | 713 | iopgd = iopgd_offset(obj, (da & IOSUPER_MASK)); |
a9dcad5e HD |
714 | } |
715 | bytes *= nent; | |
716 | } | |
717 | memset(iopgd, 0, nent * sizeof(*iopgd)); | |
718 | flush_iopgd_range(iopgd, iopgd + (nent - 1) * sizeof(*iopgd)); | |
719 | out: | |
720 | return bytes; | |
721 | } | |
722 | ||
723 | /** | |
724 | * iopgtable_clear_entry - Remove an iommu pte entry | |
725 | * @obj: target iommu | |
726 | * @da: iommu device virtual address | |
727 | **/ | |
6c32df43 | 728 | static size_t iopgtable_clear_entry(struct omap_iommu *obj, u32 da) |
a9dcad5e HD |
729 | { |
730 | size_t bytes; | |
731 | ||
732 | spin_lock(&obj->page_table_lock); | |
733 | ||
734 | bytes = iopgtable_clear_entry_core(obj, da); | |
735 | flush_iotlb_page(obj, da); | |
736 | ||
737 | spin_unlock(&obj->page_table_lock); | |
738 | ||
739 | return bytes; | |
740 | } | |
a9dcad5e | 741 | |
6c32df43 | 742 | static void iopgtable_clear_entry_all(struct omap_iommu *obj) |
a9dcad5e HD |
743 | { |
744 | int i; | |
745 | ||
746 | spin_lock(&obj->page_table_lock); | |
747 | ||
748 | for (i = 0; i < PTRS_PER_IOPGD; i++) { | |
749 | u32 da; | |
750 | u32 *iopgd; | |
751 | ||
752 | da = i << IOPGD_SHIFT; | |
753 | iopgd = iopgd_offset(obj, da); | |
754 | ||
755 | if (!*iopgd) | |
756 | continue; | |
757 | ||
a1a54456 | 758 | if (iopgd_is_table(*iopgd)) |
a9dcad5e HD |
759 | iopte_free(iopte_offset(iopgd, 0)); |
760 | ||
761 | *iopgd = 0; | |
762 | flush_iopgd_range(iopgd, iopgd); | |
763 | } | |
764 | ||
765 | flush_iotlb_all(obj); | |
766 | ||
767 | spin_unlock(&obj->page_table_lock); | |
768 | } | |
769 | ||
770 | /* | |
771 | * Device IOMMU generic operations | |
772 | */ | |
773 | static irqreturn_t iommu_fault_handler(int irq, void *data) | |
774 | { | |
d594f1f3 | 775 | u32 da, errs; |
a9dcad5e | 776 | u32 *iopgd, *iopte; |
6c32df43 | 777 | struct omap_iommu *obj = data; |
a9dcad5e HD |
778 | |
779 | if (!obj->refcount) | |
780 | return IRQ_NONE; | |
781 | ||
a9dcad5e | 782 | clk_enable(obj->clk); |
d594f1f3 | 783 | errs = iommu_report_fault(obj, &da); |
a9dcad5e | 784 | clk_disable(obj->clk); |
c56b2ddd LP |
785 | if (errs == 0) |
786 | return IRQ_HANDLED; | |
d594f1f3 DC |
787 | |
788 | /* Fault callback or TLB/PTE Dynamic loading */ | |
789 | if (obj->isr && !obj->isr(obj, da, errs, obj->isr_priv)) | |
a9dcad5e HD |
790 | return IRQ_HANDLED; |
791 | ||
37b29810 HD |
792 | iommu_disable(obj); |
793 | ||
a9dcad5e HD |
794 | iopgd = iopgd_offset(obj, da); |
795 | ||
a1a54456 | 796 | if (!iopgd_is_table(*iopgd)) { |
d594f1f3 DC |
797 | dev_err(obj->dev, "%s: errs:0x%08x da:0x%08x pgd:0x%p " |
798 | "*pgd:px%08x\n", obj->name, errs, da, iopgd, *iopgd); | |
a9dcad5e HD |
799 | return IRQ_NONE; |
800 | } | |
801 | ||
802 | iopte = iopte_offset(iopgd, da); | |
803 | ||
d594f1f3 DC |
804 | dev_err(obj->dev, "%s: errs:0x%08x da:0x%08x pgd:0x%p *pgd:0x%08x " |
805 | "pte:0x%p *pte:0x%08x\n", obj->name, errs, da, iopgd, *iopgd, | |
806 | iopte, *iopte); | |
a9dcad5e HD |
807 | |
808 | return IRQ_NONE; | |
809 | } | |
810 | ||
811 | static int device_match_by_alias(struct device *dev, void *data) | |
812 | { | |
6c32df43 | 813 | struct omap_iommu *obj = to_iommu(dev); |
a9dcad5e HD |
814 | const char *name = data; |
815 | ||
816 | pr_debug("%s: %s %s\n", __func__, obj->name, name); | |
817 | ||
818 | return strcmp(obj->name, name) == 0; | |
819 | } | |
820 | ||
821 | /** | |
f626b52d OBC |
822 | * omap_find_iommu_device() - find an omap iommu device by name |
823 | * @name: name of the iommu device | |
824 | * | |
825 | * The generic iommu API requires the caller to provide the device | |
826 | * he wishes to attach to a certain iommu domain. | |
827 | * | |
828 | * Drivers generally should not bother with this as it should just | |
829 | * be taken care of by the DMA-API using dev_archdata. | |
830 | * | |
831 | * This function is provided as an interim solution until the latter | |
832 | * materializes, and omap3isp is fully migrated to the DMA-API. | |
833 | */ | |
834 | struct device *omap_find_iommu_device(const char *name) | |
835 | { | |
836 | return driver_find_device(&omap_iommu_driver.driver, NULL, | |
837 | (void *)name, | |
838 | device_match_by_alias); | |
839 | } | |
840 | EXPORT_SYMBOL_GPL(omap_find_iommu_device); | |
841 | ||
842 | /** | |
843 | * omap_iommu_attach() - attach iommu device to an iommu domain | |
844 | * @dev: target omap iommu device | |
845 | * @iopgd: page table | |
a9dcad5e | 846 | **/ |
6c32df43 | 847 | static struct omap_iommu *omap_iommu_attach(struct device *dev, u32 *iopgd) |
a9dcad5e HD |
848 | { |
849 | int err = -ENOMEM; | |
6c32df43 | 850 | struct omap_iommu *obj = to_iommu(dev); |
a9dcad5e | 851 | |
f626b52d | 852 | spin_lock(&obj->iommu_lock); |
a9dcad5e | 853 | |
f626b52d OBC |
854 | /* an iommu device can only be attached once */ |
855 | if (++obj->refcount > 1) { | |
856 | dev_err(dev, "%s: already attached!\n", obj->name); | |
857 | err = -EBUSY; | |
858 | goto err_enable; | |
a9dcad5e HD |
859 | } |
860 | ||
f626b52d OBC |
861 | obj->iopgd = iopgd; |
862 | err = iommu_enable(obj); | |
863 | if (err) | |
864 | goto err_enable; | |
865 | flush_iotlb_all(obj); | |
866 | ||
a9dcad5e HD |
867 | if (!try_module_get(obj->owner)) |
868 | goto err_module; | |
869 | ||
f626b52d | 870 | spin_unlock(&obj->iommu_lock); |
a9dcad5e HD |
871 | |
872 | dev_dbg(obj->dev, "%s: %s\n", __func__, obj->name); | |
873 | return obj; | |
874 | ||
875 | err_module: | |
876 | if (obj->refcount == 1) | |
877 | iommu_disable(obj); | |
878 | err_enable: | |
879 | obj->refcount--; | |
f626b52d | 880 | spin_unlock(&obj->iommu_lock); |
a9dcad5e HD |
881 | return ERR_PTR(err); |
882 | } | |
a9dcad5e HD |
883 | |
884 | /** | |
f626b52d | 885 | * omap_iommu_detach - release iommu device |
a9dcad5e HD |
886 | * @obj: target iommu |
887 | **/ | |
6c32df43 | 888 | static void omap_iommu_detach(struct omap_iommu *obj) |
a9dcad5e | 889 | { |
acf9d467 | 890 | if (!obj || IS_ERR(obj)) |
a9dcad5e HD |
891 | return; |
892 | ||
f626b52d | 893 | spin_lock(&obj->iommu_lock); |
a9dcad5e HD |
894 | |
895 | if (--obj->refcount == 0) | |
896 | iommu_disable(obj); | |
897 | ||
898 | module_put(obj->owner); | |
899 | ||
f626b52d OBC |
900 | obj->iopgd = NULL; |
901 | ||
902 | spin_unlock(&obj->iommu_lock); | |
a9dcad5e HD |
903 | |
904 | dev_dbg(obj->dev, "%s: %s\n", __func__, obj->name); | |
905 | } | |
a9dcad5e | 906 | |
6c32df43 OBC |
907 | int omap_iommu_set_isr(const char *name, |
908 | int (*isr)(struct omap_iommu *obj, u32 da, u32 iommu_errs, | |
d594f1f3 DC |
909 | void *priv), |
910 | void *isr_priv) | |
911 | { | |
912 | struct device *dev; | |
6c32df43 | 913 | struct omap_iommu *obj; |
d594f1f3 DC |
914 | |
915 | dev = driver_find_device(&omap_iommu_driver.driver, NULL, (void *)name, | |
916 | device_match_by_alias); | |
917 | if (!dev) | |
918 | return -ENODEV; | |
919 | ||
920 | obj = to_iommu(dev); | |
4234541f | 921 | spin_lock(&obj->iommu_lock); |
d594f1f3 | 922 | if (obj->refcount != 0) { |
4234541f | 923 | spin_unlock(&obj->iommu_lock); |
d594f1f3 DC |
924 | return -EBUSY; |
925 | } | |
926 | obj->isr = isr; | |
927 | obj->isr_priv = isr_priv; | |
4234541f | 928 | spin_unlock(&obj->iommu_lock); |
d594f1f3 DC |
929 | |
930 | return 0; | |
931 | } | |
6c32df43 | 932 | EXPORT_SYMBOL_GPL(omap_iommu_set_isr); |
d594f1f3 | 933 | |
a9dcad5e HD |
934 | /* |
935 | * OMAP Device MMU(IOMMU) detection | |
936 | */ | |
937 | static int __devinit omap_iommu_probe(struct platform_device *pdev) | |
938 | { | |
939 | int err = -ENODEV; | |
a9dcad5e | 940 | int irq; |
6c32df43 | 941 | struct omap_iommu *obj; |
a9dcad5e HD |
942 | struct resource *res; |
943 | struct iommu_platform_data *pdata = pdev->dev.platform_data; | |
944 | ||
945 | if (pdev->num_resources != 2) | |
946 | return -EINVAL; | |
947 | ||
948 | obj = kzalloc(sizeof(*obj) + MMU_REG_SIZE, GFP_KERNEL); | |
949 | if (!obj) | |
950 | return -ENOMEM; | |
951 | ||
952 | obj->clk = clk_get(&pdev->dev, pdata->clk_name); | |
953 | if (IS_ERR(obj->clk)) | |
954 | goto err_clk; | |
955 | ||
956 | obj->nr_tlb_entries = pdata->nr_tlb_entries; | |
957 | obj->name = pdata->name; | |
958 | obj->dev = &pdev->dev; | |
959 | obj->ctx = (void *)obj + sizeof(*obj); | |
c7f4ab26 GLF |
960 | obj->da_start = pdata->da_start; |
961 | obj->da_end = pdata->da_end; | |
a9dcad5e | 962 | |
f626b52d | 963 | spin_lock_init(&obj->iommu_lock); |
a9dcad5e HD |
964 | mutex_init(&obj->mmap_lock); |
965 | spin_lock_init(&obj->page_table_lock); | |
966 | INIT_LIST_HEAD(&obj->mmap); | |
967 | ||
968 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
969 | if (!res) { | |
970 | err = -ENODEV; | |
971 | goto err_mem; | |
972 | } | |
a9dcad5e HD |
973 | |
974 | res = request_mem_region(res->start, resource_size(res), | |
975 | dev_name(&pdev->dev)); | |
976 | if (!res) { | |
977 | err = -EIO; | |
978 | goto err_mem; | |
979 | } | |
980 | ||
da4a0f76 AK |
981 | obj->regbase = ioremap(res->start, resource_size(res)); |
982 | if (!obj->regbase) { | |
983 | err = -ENOMEM; | |
984 | goto err_ioremap; | |
985 | } | |
986 | ||
a9dcad5e HD |
987 | irq = platform_get_irq(pdev, 0); |
988 | if (irq < 0) { | |
989 | err = -ENODEV; | |
990 | goto err_irq; | |
991 | } | |
992 | err = request_irq(irq, iommu_fault_handler, IRQF_SHARED, | |
993 | dev_name(&pdev->dev), obj); | |
994 | if (err < 0) | |
995 | goto err_irq; | |
996 | platform_set_drvdata(pdev, obj); | |
997 | ||
a9dcad5e HD |
998 | dev_info(&pdev->dev, "%s registered\n", obj->name); |
999 | return 0; | |
1000 | ||
a9dcad5e | 1001 | err_irq: |
a9dcad5e | 1002 | iounmap(obj->regbase); |
da4a0f76 AK |
1003 | err_ioremap: |
1004 | release_mem_region(res->start, resource_size(res)); | |
a9dcad5e HD |
1005 | err_mem: |
1006 | clk_put(obj->clk); | |
1007 | err_clk: | |
1008 | kfree(obj); | |
1009 | return err; | |
1010 | } | |
1011 | ||
1012 | static int __devexit omap_iommu_remove(struct platform_device *pdev) | |
1013 | { | |
1014 | int irq; | |
1015 | struct resource *res; | |
6c32df43 | 1016 | struct omap_iommu *obj = platform_get_drvdata(pdev); |
a9dcad5e HD |
1017 | |
1018 | platform_set_drvdata(pdev, NULL); | |
1019 | ||
1020 | iopgtable_clear_entry_all(obj); | |
a9dcad5e HD |
1021 | |
1022 | irq = platform_get_irq(pdev, 0); | |
1023 | free_irq(irq, obj); | |
1024 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
1025 | release_mem_region(res->start, resource_size(res)); | |
1026 | iounmap(obj->regbase); | |
1027 | ||
1028 | clk_put(obj->clk); | |
1029 | dev_info(&pdev->dev, "%s removed\n", obj->name); | |
1030 | kfree(obj); | |
1031 | return 0; | |
1032 | } | |
1033 | ||
1034 | static struct platform_driver omap_iommu_driver = { | |
1035 | .probe = omap_iommu_probe, | |
1036 | .remove = __devexit_p(omap_iommu_remove), | |
1037 | .driver = { | |
1038 | .name = "omap-iommu", | |
1039 | }, | |
1040 | }; | |
1041 | ||
1042 | static void iopte_cachep_ctor(void *iopte) | |
1043 | { | |
1044 | clean_dcache_area(iopte, IOPTE_TABLE_SIZE); | |
1045 | } | |
1046 | ||
f626b52d OBC |
1047 | static int omap_iommu_map(struct iommu_domain *domain, unsigned long da, |
1048 | phys_addr_t pa, int order, int prot) | |
1049 | { | |
1050 | struct omap_iommu_domain *omap_domain = domain->priv; | |
6c32df43 | 1051 | struct omap_iommu *oiommu = omap_domain->iommu_dev; |
f626b52d OBC |
1052 | struct device *dev = oiommu->dev; |
1053 | size_t bytes = PAGE_SIZE << order; | |
1054 | struct iotlb_entry e; | |
1055 | int omap_pgsz; | |
1056 | u32 ret, flags; | |
1057 | ||
1058 | /* we only support mapping a single iommu page for now */ | |
1059 | omap_pgsz = bytes_to_iopgsz(bytes); | |
1060 | if (omap_pgsz < 0) { | |
1061 | dev_err(dev, "invalid size to map: %d\n", bytes); | |
1062 | return -EINVAL; | |
1063 | } | |
1064 | ||
1065 | dev_dbg(dev, "mapping da 0x%lx to pa 0x%x size 0x%x\n", da, pa, bytes); | |
1066 | ||
1067 | flags = omap_pgsz | prot; | |
1068 | ||
1069 | iotlb_init_entry(&e, da, pa, flags); | |
1070 | ||
6c32df43 | 1071 | ret = omap_iopgtable_store_entry(oiommu, &e); |
b4550d41 | 1072 | if (ret) |
6c32df43 | 1073 | dev_err(dev, "omap_iopgtable_store_entry failed: %d\n", ret); |
f626b52d | 1074 | |
b4550d41 | 1075 | return ret; |
f626b52d OBC |
1076 | } |
1077 | ||
1078 | static int omap_iommu_unmap(struct iommu_domain *domain, unsigned long da, | |
1079 | int order) | |
1080 | { | |
1081 | struct omap_iommu_domain *omap_domain = domain->priv; | |
6c32df43 | 1082 | struct omap_iommu *oiommu = omap_domain->iommu_dev; |
f626b52d | 1083 | struct device *dev = oiommu->dev; |
5e1b612c | 1084 | size_t unmap_size; |
f626b52d | 1085 | |
5e1b612c | 1086 | dev_dbg(dev, "unmapping da 0x%lx order %d\n", da, order); |
f626b52d | 1087 | |
5e1b612c | 1088 | unmap_size = iopgtable_clear_entry(oiommu, da); |
f626b52d | 1089 | |
5e1b612c | 1090 | return unmap_size ? get_order(unmap_size) : -EINVAL; |
f626b52d OBC |
1091 | } |
1092 | ||
1093 | static int | |
1094 | omap_iommu_attach_dev(struct iommu_domain *domain, struct device *dev) | |
1095 | { | |
1096 | struct omap_iommu_domain *omap_domain = domain->priv; | |
6c32df43 | 1097 | struct omap_iommu *oiommu; |
f626b52d OBC |
1098 | int ret = 0; |
1099 | ||
1100 | spin_lock(&omap_domain->lock); | |
1101 | ||
1102 | /* only a single device is supported per domain for now */ | |
1103 | if (omap_domain->iommu_dev) { | |
1104 | dev_err(dev, "iommu domain is already attached\n"); | |
1105 | ret = -EBUSY; | |
1106 | goto out; | |
1107 | } | |
1108 | ||
1109 | /* get a handle to and enable the omap iommu */ | |
1110 | oiommu = omap_iommu_attach(dev, omap_domain->pgtable); | |
1111 | if (IS_ERR(oiommu)) { | |
1112 | ret = PTR_ERR(oiommu); | |
1113 | dev_err(dev, "can't get omap iommu: %d\n", ret); | |
1114 | goto out; | |
1115 | } | |
1116 | ||
1117 | omap_domain->iommu_dev = oiommu; | |
1118 | ||
1119 | out: | |
1120 | spin_unlock(&omap_domain->lock); | |
1121 | return ret; | |
1122 | } | |
1123 | ||
1124 | static void omap_iommu_detach_dev(struct iommu_domain *domain, | |
1125 | struct device *dev) | |
1126 | { | |
1127 | struct omap_iommu_domain *omap_domain = domain->priv; | |
6c32df43 | 1128 | struct omap_iommu *oiommu = to_iommu(dev); |
f626b52d OBC |
1129 | |
1130 | spin_lock(&omap_domain->lock); | |
1131 | ||
1132 | /* only a single device is supported per domain for now */ | |
1133 | if (omap_domain->iommu_dev != oiommu) { | |
1134 | dev_err(dev, "invalid iommu device\n"); | |
1135 | goto out; | |
1136 | } | |
1137 | ||
1138 | iopgtable_clear_entry_all(oiommu); | |
1139 | ||
1140 | omap_iommu_detach(oiommu); | |
1141 | ||
1142 | omap_domain->iommu_dev = NULL; | |
1143 | ||
1144 | out: | |
1145 | spin_unlock(&omap_domain->lock); | |
1146 | } | |
1147 | ||
1148 | static int omap_iommu_domain_init(struct iommu_domain *domain) | |
1149 | { | |
1150 | struct omap_iommu_domain *omap_domain; | |
1151 | ||
1152 | omap_domain = kzalloc(sizeof(*omap_domain), GFP_KERNEL); | |
1153 | if (!omap_domain) { | |
1154 | pr_err("kzalloc failed\n"); | |
1155 | goto out; | |
1156 | } | |
1157 | ||
1158 | omap_domain->pgtable = kzalloc(IOPGD_TABLE_SIZE, GFP_KERNEL); | |
1159 | if (!omap_domain->pgtable) { | |
1160 | pr_err("kzalloc failed\n"); | |
1161 | goto fail_nomem; | |
1162 | } | |
1163 | ||
1164 | /* | |
1165 | * should never fail, but please keep this around to ensure | |
1166 | * we keep the hardware happy | |
1167 | */ | |
1168 | BUG_ON(!IS_ALIGNED((long)omap_domain->pgtable, IOPGD_TABLE_SIZE)); | |
1169 | ||
1170 | clean_dcache_area(omap_domain->pgtable, IOPGD_TABLE_SIZE); | |
1171 | spin_lock_init(&omap_domain->lock); | |
1172 | ||
1173 | domain->priv = omap_domain; | |
1174 | ||
1175 | return 0; | |
1176 | ||
1177 | fail_nomem: | |
1178 | kfree(omap_domain); | |
1179 | out: | |
1180 | return -ENOMEM; | |
1181 | } | |
1182 | ||
1183 | /* assume device was already detached */ | |
1184 | static void omap_iommu_domain_destroy(struct iommu_domain *domain) | |
1185 | { | |
1186 | struct omap_iommu_domain *omap_domain = domain->priv; | |
1187 | ||
1188 | domain->priv = NULL; | |
1189 | ||
1190 | kfree(omap_domain->pgtable); | |
1191 | kfree(omap_domain); | |
1192 | } | |
1193 | ||
1194 | static phys_addr_t omap_iommu_iova_to_phys(struct iommu_domain *domain, | |
1195 | unsigned long da) | |
1196 | { | |
1197 | struct omap_iommu_domain *omap_domain = domain->priv; | |
6c32df43 | 1198 | struct omap_iommu *oiommu = omap_domain->iommu_dev; |
f626b52d OBC |
1199 | struct device *dev = oiommu->dev; |
1200 | u32 *pgd, *pte; | |
1201 | phys_addr_t ret = 0; | |
1202 | ||
1203 | iopgtable_lookup_entry(oiommu, da, &pgd, &pte); | |
1204 | ||
1205 | if (pte) { | |
1206 | if (iopte_is_small(*pte)) | |
1207 | ret = omap_iommu_translate(*pte, da, IOPTE_MASK); | |
1208 | else if (iopte_is_large(*pte)) | |
1209 | ret = omap_iommu_translate(*pte, da, IOLARGE_MASK); | |
1210 | else | |
1211 | dev_err(dev, "bogus pte 0x%x", *pte); | |
1212 | } else { | |
1213 | if (iopgd_is_section(*pgd)) | |
1214 | ret = omap_iommu_translate(*pgd, da, IOSECTION_MASK); | |
1215 | else if (iopgd_is_super(*pgd)) | |
1216 | ret = omap_iommu_translate(*pgd, da, IOSUPER_MASK); | |
1217 | else | |
1218 | dev_err(dev, "bogus pgd 0x%x", *pgd); | |
1219 | } | |
1220 | ||
1221 | return ret; | |
1222 | } | |
1223 | ||
1224 | static int omap_iommu_domain_has_cap(struct iommu_domain *domain, | |
1225 | unsigned long cap) | |
1226 | { | |
1227 | return 0; | |
1228 | } | |
1229 | ||
1230 | static struct iommu_ops omap_iommu_ops = { | |
1231 | .domain_init = omap_iommu_domain_init, | |
1232 | .domain_destroy = omap_iommu_domain_destroy, | |
1233 | .attach_dev = omap_iommu_attach_dev, | |
1234 | .detach_dev = omap_iommu_detach_dev, | |
1235 | .map = omap_iommu_map, | |
1236 | .unmap = omap_iommu_unmap, | |
1237 | .iova_to_phys = omap_iommu_iova_to_phys, | |
1238 | .domain_has_cap = omap_iommu_domain_has_cap, | |
1239 | }; | |
1240 | ||
a9dcad5e HD |
1241 | static int __init omap_iommu_init(void) |
1242 | { | |
1243 | struct kmem_cache *p; | |
1244 | const unsigned long flags = SLAB_HWCACHE_ALIGN; | |
1245 | size_t align = 1 << 10; /* L2 pagetable alignement */ | |
1246 | ||
1247 | p = kmem_cache_create("iopte_cache", IOPTE_TABLE_SIZE, align, flags, | |
1248 | iopte_cachep_ctor); | |
1249 | if (!p) | |
1250 | return -ENOMEM; | |
1251 | iopte_cachep = p; | |
1252 | ||
f626b52d OBC |
1253 | register_iommu(&omap_iommu_ops); |
1254 | ||
a9dcad5e HD |
1255 | return platform_driver_register(&omap_iommu_driver); |
1256 | } | |
1257 | module_init(omap_iommu_init); | |
1258 | ||
1259 | static void __exit omap_iommu_exit(void) | |
1260 | { | |
1261 | kmem_cache_destroy(iopte_cachep); | |
1262 | ||
1263 | platform_driver_unregister(&omap_iommu_driver); | |
1264 | } | |
1265 | module_exit(omap_iommu_exit); | |
1266 | ||
1267 | MODULE_DESCRIPTION("omap iommu: tlb and pagetable primitives"); | |
1268 | MODULE_ALIAS("platform:omap-iommu"); | |
1269 | MODULE_AUTHOR("Hiroshi DOYU, Paul Mundt and Toshihiro Kobayashi"); | |
1270 | MODULE_LICENSE("GPL v2"); |