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cc2d3216 MZ |
1 | /* |
2 | * Copyright (C) 2013, 2014 ARM Limited, All Rights Reserved. | |
3 | * Author: Marc Zyngier <marc.zyngier@arm.com> | |
4 | * | |
5 | * This program is free software; you can redistribute it and/or modify | |
6 | * it under the terms of the GNU General Public License version 2 as | |
7 | * published by the Free Software Foundation. | |
8 | * | |
9 | * This program is distributed in the hope that it will be useful, | |
10 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
11 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
12 | * GNU General Public License for more details. | |
13 | * | |
14 | * You should have received a copy of the GNU General Public License | |
15 | * along with this program. If not, see <http://www.gnu.org/licenses/>. | |
16 | */ | |
17 | ||
18 | #include <linux/bitmap.h> | |
19 | #include <linux/cpu.h> | |
20 | #include <linux/delay.h> | |
21 | #include <linux/interrupt.h> | |
22 | #include <linux/log2.h> | |
23 | #include <linux/mm.h> | |
24 | #include <linux/msi.h> | |
25 | #include <linux/of.h> | |
26 | #include <linux/of_address.h> | |
27 | #include <linux/of_irq.h> | |
28 | #include <linux/of_pci.h> | |
29 | #include <linux/of_platform.h> | |
30 | #include <linux/percpu.h> | |
31 | #include <linux/slab.h> | |
32 | ||
41a83e06 | 33 | #include <linux/irqchip.h> |
cc2d3216 MZ |
34 | #include <linux/irqchip/arm-gic-v3.h> |
35 | ||
36 | #include <asm/cacheflush.h> | |
37 | #include <asm/cputype.h> | |
38 | #include <asm/exception.h> | |
39 | ||
67510cca RR |
40 | #include "irq-gic-common.h" |
41 | ||
94100970 RR |
42 | #define ITS_FLAGS_CMDQ_NEEDS_FLUSHING (1ULL << 0) |
43 | #define ITS_FLAGS_WORKAROUND_CAVIUM_22375 (1ULL << 1) | |
fbf8f40e | 44 | #define ITS_FLAGS_WORKAROUND_CAVIUM_23144 (1ULL << 2) |
cc2d3216 | 45 | |
c48ed51c MZ |
46 | #define RDIST_FLAGS_PROPBASE_NEEDS_FLUSHING (1 << 0) |
47 | ||
cc2d3216 MZ |
48 | /* |
49 | * Collection structure - just an ID, and a redistributor address to | |
50 | * ping. We use one per CPU as a bag of interrupts assigned to this | |
51 | * CPU. | |
52 | */ | |
53 | struct its_collection { | |
54 | u64 target_address; | |
55 | u16 col_id; | |
56 | }; | |
57 | ||
466b7d16 | 58 | /* |
9347359a SD |
59 | * The ITS_BASER structure - contains memory information, cached |
60 | * value of BASER register configuration and ITS page size. | |
466b7d16 SD |
61 | */ |
62 | struct its_baser { | |
63 | void *base; | |
64 | u64 val; | |
65 | u32 order; | |
9347359a | 66 | u32 psz; |
466b7d16 SD |
67 | }; |
68 | ||
cc2d3216 MZ |
69 | /* |
70 | * The ITS structure - contains most of the infrastructure, with the | |
841514ab MZ |
71 | * top-level MSI domain, the command queue, the collections, and the |
72 | * list of devices writing to it. | |
cc2d3216 MZ |
73 | */ |
74 | struct its_node { | |
75 | raw_spinlock_t lock; | |
76 | struct list_head entry; | |
cc2d3216 | 77 | void __iomem *base; |
db40f0a7 | 78 | phys_addr_t phys_base; |
cc2d3216 MZ |
79 | struct its_cmd_block *cmd_base; |
80 | struct its_cmd_block *cmd_write; | |
466b7d16 | 81 | struct its_baser tables[GITS_BASER_NR_REGS]; |
cc2d3216 MZ |
82 | struct its_collection *collections; |
83 | struct list_head its_device_list; | |
84 | u64 flags; | |
85 | u32 ite_size; | |
466b7d16 | 86 | u32 device_ids; |
fbf8f40e | 87 | int numa_node; |
cc2d3216 MZ |
88 | }; |
89 | ||
90 | #define ITS_ITT_ALIGN SZ_256 | |
91 | ||
2eca0d6c SD |
92 | /* Convert page order to size in bytes */ |
93 | #define PAGE_ORDER_TO_SIZE(o) (PAGE_SIZE << (o)) | |
94 | ||
591e5bec MZ |
95 | struct event_lpi_map { |
96 | unsigned long *lpi_map; | |
97 | u16 *col_map; | |
98 | irq_hw_number_t lpi_base; | |
99 | int nr_lpis; | |
100 | }; | |
101 | ||
cc2d3216 MZ |
102 | /* |
103 | * The ITS view of a device - belongs to an ITS, a collection, owns an | |
104 | * interrupt translation table, and a list of interrupts. | |
105 | */ | |
106 | struct its_device { | |
107 | struct list_head entry; | |
108 | struct its_node *its; | |
591e5bec | 109 | struct event_lpi_map event_map; |
cc2d3216 | 110 | void *itt; |
cc2d3216 MZ |
111 | u32 nr_ites; |
112 | u32 device_id; | |
113 | }; | |
114 | ||
1ac19ca6 MZ |
115 | static LIST_HEAD(its_nodes); |
116 | static DEFINE_SPINLOCK(its_lock); | |
1ac19ca6 | 117 | static struct rdists *gic_rdists; |
db40f0a7 | 118 | static struct irq_domain *its_parent; |
1ac19ca6 MZ |
119 | |
120 | #define gic_data_rdist() (raw_cpu_ptr(gic_rdists->rdist)) | |
121 | #define gic_data_rdist_rd_base() (gic_data_rdist()->rd_base) | |
122 | ||
591e5bec MZ |
123 | static struct its_collection *dev_event_to_col(struct its_device *its_dev, |
124 | u32 event) | |
125 | { | |
126 | struct its_node *its = its_dev->its; | |
127 | ||
128 | return its->collections + its_dev->event_map.col_map[event]; | |
129 | } | |
130 | ||
cc2d3216 MZ |
131 | /* |
132 | * ITS command descriptors - parameters to be encoded in a command | |
133 | * block. | |
134 | */ | |
135 | struct its_cmd_desc { | |
136 | union { | |
137 | struct { | |
138 | struct its_device *dev; | |
139 | u32 event_id; | |
140 | } its_inv_cmd; | |
141 | ||
142 | struct { | |
143 | struct its_device *dev; | |
144 | u32 event_id; | |
145 | } its_int_cmd; | |
146 | ||
147 | struct { | |
148 | struct its_device *dev; | |
149 | int valid; | |
150 | } its_mapd_cmd; | |
151 | ||
152 | struct { | |
153 | struct its_collection *col; | |
154 | int valid; | |
155 | } its_mapc_cmd; | |
156 | ||
157 | struct { | |
158 | struct its_device *dev; | |
159 | u32 phys_id; | |
160 | u32 event_id; | |
161 | } its_mapvi_cmd; | |
162 | ||
163 | struct { | |
164 | struct its_device *dev; | |
165 | struct its_collection *col; | |
591e5bec | 166 | u32 event_id; |
cc2d3216 MZ |
167 | } its_movi_cmd; |
168 | ||
169 | struct { | |
170 | struct its_device *dev; | |
171 | u32 event_id; | |
172 | } its_discard_cmd; | |
173 | ||
174 | struct { | |
175 | struct its_collection *col; | |
176 | } its_invall_cmd; | |
177 | }; | |
178 | }; | |
179 | ||
180 | /* | |
181 | * The ITS command block, which is what the ITS actually parses. | |
182 | */ | |
183 | struct its_cmd_block { | |
184 | u64 raw_cmd[4]; | |
185 | }; | |
186 | ||
187 | #define ITS_CMD_QUEUE_SZ SZ_64K | |
188 | #define ITS_CMD_QUEUE_NR_ENTRIES (ITS_CMD_QUEUE_SZ / sizeof(struct its_cmd_block)) | |
189 | ||
190 | typedef struct its_collection *(*its_cmd_builder_t)(struct its_cmd_block *, | |
191 | struct its_cmd_desc *); | |
192 | ||
193 | static void its_encode_cmd(struct its_cmd_block *cmd, u8 cmd_nr) | |
194 | { | |
195 | cmd->raw_cmd[0] &= ~0xffUL; | |
196 | cmd->raw_cmd[0] |= cmd_nr; | |
197 | } | |
198 | ||
199 | static void its_encode_devid(struct its_cmd_block *cmd, u32 devid) | |
200 | { | |
7e195ba0 | 201 | cmd->raw_cmd[0] &= BIT_ULL(32) - 1; |
cc2d3216 MZ |
202 | cmd->raw_cmd[0] |= ((u64)devid) << 32; |
203 | } | |
204 | ||
205 | static void its_encode_event_id(struct its_cmd_block *cmd, u32 id) | |
206 | { | |
207 | cmd->raw_cmd[1] &= ~0xffffffffUL; | |
208 | cmd->raw_cmd[1] |= id; | |
209 | } | |
210 | ||
211 | static void its_encode_phys_id(struct its_cmd_block *cmd, u32 phys_id) | |
212 | { | |
213 | cmd->raw_cmd[1] &= 0xffffffffUL; | |
214 | cmd->raw_cmd[1] |= ((u64)phys_id) << 32; | |
215 | } | |
216 | ||
217 | static void its_encode_size(struct its_cmd_block *cmd, u8 size) | |
218 | { | |
219 | cmd->raw_cmd[1] &= ~0x1fUL; | |
220 | cmd->raw_cmd[1] |= size & 0x1f; | |
221 | } | |
222 | ||
223 | static void its_encode_itt(struct its_cmd_block *cmd, u64 itt_addr) | |
224 | { | |
225 | cmd->raw_cmd[2] &= ~0xffffffffffffUL; | |
226 | cmd->raw_cmd[2] |= itt_addr & 0xffffffffff00UL; | |
227 | } | |
228 | ||
229 | static void its_encode_valid(struct its_cmd_block *cmd, int valid) | |
230 | { | |
231 | cmd->raw_cmd[2] &= ~(1UL << 63); | |
232 | cmd->raw_cmd[2] |= ((u64)!!valid) << 63; | |
233 | } | |
234 | ||
235 | static void its_encode_target(struct its_cmd_block *cmd, u64 target_addr) | |
236 | { | |
237 | cmd->raw_cmd[2] &= ~(0xffffffffUL << 16); | |
238 | cmd->raw_cmd[2] |= (target_addr & (0xffffffffUL << 16)); | |
239 | } | |
240 | ||
241 | static void its_encode_collection(struct its_cmd_block *cmd, u16 col) | |
242 | { | |
243 | cmd->raw_cmd[2] &= ~0xffffUL; | |
244 | cmd->raw_cmd[2] |= col; | |
245 | } | |
246 | ||
247 | static inline void its_fixup_cmd(struct its_cmd_block *cmd) | |
248 | { | |
249 | /* Let's fixup BE commands */ | |
250 | cmd->raw_cmd[0] = cpu_to_le64(cmd->raw_cmd[0]); | |
251 | cmd->raw_cmd[1] = cpu_to_le64(cmd->raw_cmd[1]); | |
252 | cmd->raw_cmd[2] = cpu_to_le64(cmd->raw_cmd[2]); | |
253 | cmd->raw_cmd[3] = cpu_to_le64(cmd->raw_cmd[3]); | |
254 | } | |
255 | ||
256 | static struct its_collection *its_build_mapd_cmd(struct its_cmd_block *cmd, | |
257 | struct its_cmd_desc *desc) | |
258 | { | |
259 | unsigned long itt_addr; | |
c8481267 | 260 | u8 size = ilog2(desc->its_mapd_cmd.dev->nr_ites); |
cc2d3216 MZ |
261 | |
262 | itt_addr = virt_to_phys(desc->its_mapd_cmd.dev->itt); | |
263 | itt_addr = ALIGN(itt_addr, ITS_ITT_ALIGN); | |
264 | ||
265 | its_encode_cmd(cmd, GITS_CMD_MAPD); | |
266 | its_encode_devid(cmd, desc->its_mapd_cmd.dev->device_id); | |
267 | its_encode_size(cmd, size - 1); | |
268 | its_encode_itt(cmd, itt_addr); | |
269 | its_encode_valid(cmd, desc->its_mapd_cmd.valid); | |
270 | ||
271 | its_fixup_cmd(cmd); | |
272 | ||
591e5bec | 273 | return NULL; |
cc2d3216 MZ |
274 | } |
275 | ||
276 | static struct its_collection *its_build_mapc_cmd(struct its_cmd_block *cmd, | |
277 | struct its_cmd_desc *desc) | |
278 | { | |
279 | its_encode_cmd(cmd, GITS_CMD_MAPC); | |
280 | its_encode_collection(cmd, desc->its_mapc_cmd.col->col_id); | |
281 | its_encode_target(cmd, desc->its_mapc_cmd.col->target_address); | |
282 | its_encode_valid(cmd, desc->its_mapc_cmd.valid); | |
283 | ||
284 | its_fixup_cmd(cmd); | |
285 | ||
286 | return desc->its_mapc_cmd.col; | |
287 | } | |
288 | ||
289 | static struct its_collection *its_build_mapvi_cmd(struct its_cmd_block *cmd, | |
290 | struct its_cmd_desc *desc) | |
291 | { | |
591e5bec MZ |
292 | struct its_collection *col; |
293 | ||
294 | col = dev_event_to_col(desc->its_mapvi_cmd.dev, | |
295 | desc->its_mapvi_cmd.event_id); | |
296 | ||
cc2d3216 MZ |
297 | its_encode_cmd(cmd, GITS_CMD_MAPVI); |
298 | its_encode_devid(cmd, desc->its_mapvi_cmd.dev->device_id); | |
299 | its_encode_event_id(cmd, desc->its_mapvi_cmd.event_id); | |
300 | its_encode_phys_id(cmd, desc->its_mapvi_cmd.phys_id); | |
591e5bec | 301 | its_encode_collection(cmd, col->col_id); |
cc2d3216 MZ |
302 | |
303 | its_fixup_cmd(cmd); | |
304 | ||
591e5bec | 305 | return col; |
cc2d3216 MZ |
306 | } |
307 | ||
308 | static struct its_collection *its_build_movi_cmd(struct its_cmd_block *cmd, | |
309 | struct its_cmd_desc *desc) | |
310 | { | |
591e5bec MZ |
311 | struct its_collection *col; |
312 | ||
313 | col = dev_event_to_col(desc->its_movi_cmd.dev, | |
314 | desc->its_movi_cmd.event_id); | |
315 | ||
cc2d3216 MZ |
316 | its_encode_cmd(cmd, GITS_CMD_MOVI); |
317 | its_encode_devid(cmd, desc->its_movi_cmd.dev->device_id); | |
591e5bec | 318 | its_encode_event_id(cmd, desc->its_movi_cmd.event_id); |
cc2d3216 MZ |
319 | its_encode_collection(cmd, desc->its_movi_cmd.col->col_id); |
320 | ||
321 | its_fixup_cmd(cmd); | |
322 | ||
591e5bec | 323 | return col; |
cc2d3216 MZ |
324 | } |
325 | ||
326 | static struct its_collection *its_build_discard_cmd(struct its_cmd_block *cmd, | |
327 | struct its_cmd_desc *desc) | |
328 | { | |
591e5bec MZ |
329 | struct its_collection *col; |
330 | ||
331 | col = dev_event_to_col(desc->its_discard_cmd.dev, | |
332 | desc->its_discard_cmd.event_id); | |
333 | ||
cc2d3216 MZ |
334 | its_encode_cmd(cmd, GITS_CMD_DISCARD); |
335 | its_encode_devid(cmd, desc->its_discard_cmd.dev->device_id); | |
336 | its_encode_event_id(cmd, desc->its_discard_cmd.event_id); | |
337 | ||
338 | its_fixup_cmd(cmd); | |
339 | ||
591e5bec | 340 | return col; |
cc2d3216 MZ |
341 | } |
342 | ||
343 | static struct its_collection *its_build_inv_cmd(struct its_cmd_block *cmd, | |
344 | struct its_cmd_desc *desc) | |
345 | { | |
591e5bec MZ |
346 | struct its_collection *col; |
347 | ||
348 | col = dev_event_to_col(desc->its_inv_cmd.dev, | |
349 | desc->its_inv_cmd.event_id); | |
350 | ||
cc2d3216 MZ |
351 | its_encode_cmd(cmd, GITS_CMD_INV); |
352 | its_encode_devid(cmd, desc->its_inv_cmd.dev->device_id); | |
353 | its_encode_event_id(cmd, desc->its_inv_cmd.event_id); | |
354 | ||
355 | its_fixup_cmd(cmd); | |
356 | ||
591e5bec | 357 | return col; |
cc2d3216 MZ |
358 | } |
359 | ||
360 | static struct its_collection *its_build_invall_cmd(struct its_cmd_block *cmd, | |
361 | struct its_cmd_desc *desc) | |
362 | { | |
363 | its_encode_cmd(cmd, GITS_CMD_INVALL); | |
364 | its_encode_collection(cmd, desc->its_mapc_cmd.col->col_id); | |
365 | ||
366 | its_fixup_cmd(cmd); | |
367 | ||
368 | return NULL; | |
369 | } | |
370 | ||
371 | static u64 its_cmd_ptr_to_offset(struct its_node *its, | |
372 | struct its_cmd_block *ptr) | |
373 | { | |
374 | return (ptr - its->cmd_base) * sizeof(*ptr); | |
375 | } | |
376 | ||
377 | static int its_queue_full(struct its_node *its) | |
378 | { | |
379 | int widx; | |
380 | int ridx; | |
381 | ||
382 | widx = its->cmd_write - its->cmd_base; | |
383 | ridx = readl_relaxed(its->base + GITS_CREADR) / sizeof(struct its_cmd_block); | |
384 | ||
385 | /* This is incredibly unlikely to happen, unless the ITS locks up. */ | |
386 | if (((widx + 1) % ITS_CMD_QUEUE_NR_ENTRIES) == ridx) | |
387 | return 1; | |
388 | ||
389 | return 0; | |
390 | } | |
391 | ||
392 | static struct its_cmd_block *its_allocate_entry(struct its_node *its) | |
393 | { | |
394 | struct its_cmd_block *cmd; | |
395 | u32 count = 1000000; /* 1s! */ | |
396 | ||
397 | while (its_queue_full(its)) { | |
398 | count--; | |
399 | if (!count) { | |
400 | pr_err_ratelimited("ITS queue not draining\n"); | |
401 | return NULL; | |
402 | } | |
403 | cpu_relax(); | |
404 | udelay(1); | |
405 | } | |
406 | ||
407 | cmd = its->cmd_write++; | |
408 | ||
409 | /* Handle queue wrapping */ | |
410 | if (its->cmd_write == (its->cmd_base + ITS_CMD_QUEUE_NR_ENTRIES)) | |
411 | its->cmd_write = its->cmd_base; | |
412 | ||
413 | return cmd; | |
414 | } | |
415 | ||
416 | static struct its_cmd_block *its_post_commands(struct its_node *its) | |
417 | { | |
418 | u64 wr = its_cmd_ptr_to_offset(its, its->cmd_write); | |
419 | ||
420 | writel_relaxed(wr, its->base + GITS_CWRITER); | |
421 | ||
422 | return its->cmd_write; | |
423 | } | |
424 | ||
425 | static void its_flush_cmd(struct its_node *its, struct its_cmd_block *cmd) | |
426 | { | |
427 | /* | |
428 | * Make sure the commands written to memory are observable by | |
429 | * the ITS. | |
430 | */ | |
431 | if (its->flags & ITS_FLAGS_CMDQ_NEEDS_FLUSHING) | |
432 | __flush_dcache_area(cmd, sizeof(*cmd)); | |
433 | else | |
434 | dsb(ishst); | |
435 | } | |
436 | ||
437 | static void its_wait_for_range_completion(struct its_node *its, | |
438 | struct its_cmd_block *from, | |
439 | struct its_cmd_block *to) | |
440 | { | |
441 | u64 rd_idx, from_idx, to_idx; | |
442 | u32 count = 1000000; /* 1s! */ | |
443 | ||
444 | from_idx = its_cmd_ptr_to_offset(its, from); | |
445 | to_idx = its_cmd_ptr_to_offset(its, to); | |
446 | ||
447 | while (1) { | |
448 | rd_idx = readl_relaxed(its->base + GITS_CREADR); | |
449 | if (rd_idx >= to_idx || rd_idx < from_idx) | |
450 | break; | |
451 | ||
452 | count--; | |
453 | if (!count) { | |
454 | pr_err_ratelimited("ITS queue timeout\n"); | |
455 | return; | |
456 | } | |
457 | cpu_relax(); | |
458 | udelay(1); | |
459 | } | |
460 | } | |
461 | ||
462 | static void its_send_single_command(struct its_node *its, | |
463 | its_cmd_builder_t builder, | |
464 | struct its_cmd_desc *desc) | |
465 | { | |
466 | struct its_cmd_block *cmd, *sync_cmd, *next_cmd; | |
467 | struct its_collection *sync_col; | |
3e39e8f5 | 468 | unsigned long flags; |
cc2d3216 | 469 | |
3e39e8f5 | 470 | raw_spin_lock_irqsave(&its->lock, flags); |
cc2d3216 MZ |
471 | |
472 | cmd = its_allocate_entry(its); | |
473 | if (!cmd) { /* We're soooooo screewed... */ | |
474 | pr_err_ratelimited("ITS can't allocate, dropping command\n"); | |
3e39e8f5 | 475 | raw_spin_unlock_irqrestore(&its->lock, flags); |
cc2d3216 MZ |
476 | return; |
477 | } | |
478 | sync_col = builder(cmd, desc); | |
479 | its_flush_cmd(its, cmd); | |
480 | ||
481 | if (sync_col) { | |
482 | sync_cmd = its_allocate_entry(its); | |
483 | if (!sync_cmd) { | |
484 | pr_err_ratelimited("ITS can't SYNC, skipping\n"); | |
485 | goto post; | |
486 | } | |
487 | its_encode_cmd(sync_cmd, GITS_CMD_SYNC); | |
488 | its_encode_target(sync_cmd, sync_col->target_address); | |
489 | its_fixup_cmd(sync_cmd); | |
490 | its_flush_cmd(its, sync_cmd); | |
491 | } | |
492 | ||
493 | post: | |
494 | next_cmd = its_post_commands(its); | |
3e39e8f5 | 495 | raw_spin_unlock_irqrestore(&its->lock, flags); |
cc2d3216 MZ |
496 | |
497 | its_wait_for_range_completion(its, cmd, next_cmd); | |
498 | } | |
499 | ||
500 | static void its_send_inv(struct its_device *dev, u32 event_id) | |
501 | { | |
502 | struct its_cmd_desc desc; | |
503 | ||
504 | desc.its_inv_cmd.dev = dev; | |
505 | desc.its_inv_cmd.event_id = event_id; | |
506 | ||
507 | its_send_single_command(dev->its, its_build_inv_cmd, &desc); | |
508 | } | |
509 | ||
510 | static void its_send_mapd(struct its_device *dev, int valid) | |
511 | { | |
512 | struct its_cmd_desc desc; | |
513 | ||
514 | desc.its_mapd_cmd.dev = dev; | |
515 | desc.its_mapd_cmd.valid = !!valid; | |
516 | ||
517 | its_send_single_command(dev->its, its_build_mapd_cmd, &desc); | |
518 | } | |
519 | ||
520 | static void its_send_mapc(struct its_node *its, struct its_collection *col, | |
521 | int valid) | |
522 | { | |
523 | struct its_cmd_desc desc; | |
524 | ||
525 | desc.its_mapc_cmd.col = col; | |
526 | desc.its_mapc_cmd.valid = !!valid; | |
527 | ||
528 | its_send_single_command(its, its_build_mapc_cmd, &desc); | |
529 | } | |
530 | ||
531 | static void its_send_mapvi(struct its_device *dev, u32 irq_id, u32 id) | |
532 | { | |
533 | struct its_cmd_desc desc; | |
534 | ||
535 | desc.its_mapvi_cmd.dev = dev; | |
536 | desc.its_mapvi_cmd.phys_id = irq_id; | |
537 | desc.its_mapvi_cmd.event_id = id; | |
538 | ||
539 | its_send_single_command(dev->its, its_build_mapvi_cmd, &desc); | |
540 | } | |
541 | ||
542 | static void its_send_movi(struct its_device *dev, | |
543 | struct its_collection *col, u32 id) | |
544 | { | |
545 | struct its_cmd_desc desc; | |
546 | ||
547 | desc.its_movi_cmd.dev = dev; | |
548 | desc.its_movi_cmd.col = col; | |
591e5bec | 549 | desc.its_movi_cmd.event_id = id; |
cc2d3216 MZ |
550 | |
551 | its_send_single_command(dev->its, its_build_movi_cmd, &desc); | |
552 | } | |
553 | ||
554 | static void its_send_discard(struct its_device *dev, u32 id) | |
555 | { | |
556 | struct its_cmd_desc desc; | |
557 | ||
558 | desc.its_discard_cmd.dev = dev; | |
559 | desc.its_discard_cmd.event_id = id; | |
560 | ||
561 | its_send_single_command(dev->its, its_build_discard_cmd, &desc); | |
562 | } | |
563 | ||
564 | static void its_send_invall(struct its_node *its, struct its_collection *col) | |
565 | { | |
566 | struct its_cmd_desc desc; | |
567 | ||
568 | desc.its_invall_cmd.col = col; | |
569 | ||
570 | its_send_single_command(its, its_build_invall_cmd, &desc); | |
571 | } | |
c48ed51c MZ |
572 | |
573 | /* | |
574 | * irqchip functions - assumes MSI, mostly. | |
575 | */ | |
576 | ||
577 | static inline u32 its_get_event_id(struct irq_data *d) | |
578 | { | |
579 | struct its_device *its_dev = irq_data_get_irq_chip_data(d); | |
591e5bec | 580 | return d->hwirq - its_dev->event_map.lpi_base; |
c48ed51c MZ |
581 | } |
582 | ||
583 | static void lpi_set_config(struct irq_data *d, bool enable) | |
584 | { | |
585 | struct its_device *its_dev = irq_data_get_irq_chip_data(d); | |
586 | irq_hw_number_t hwirq = d->hwirq; | |
587 | u32 id = its_get_event_id(d); | |
588 | u8 *cfg = page_address(gic_rdists->prop_page) + hwirq - 8192; | |
589 | ||
590 | if (enable) | |
591 | *cfg |= LPI_PROP_ENABLED; | |
592 | else | |
593 | *cfg &= ~LPI_PROP_ENABLED; | |
594 | ||
595 | /* | |
596 | * Make the above write visible to the redistributors. | |
597 | * And yes, we're flushing exactly: One. Single. Byte. | |
598 | * Humpf... | |
599 | */ | |
600 | if (gic_rdists->flags & RDIST_FLAGS_PROPBASE_NEEDS_FLUSHING) | |
601 | __flush_dcache_area(cfg, sizeof(*cfg)); | |
602 | else | |
603 | dsb(ishst); | |
604 | its_send_inv(its_dev, id); | |
605 | } | |
606 | ||
607 | static void its_mask_irq(struct irq_data *d) | |
608 | { | |
609 | lpi_set_config(d, false); | |
610 | } | |
611 | ||
612 | static void its_unmask_irq(struct irq_data *d) | |
613 | { | |
614 | lpi_set_config(d, true); | |
615 | } | |
616 | ||
c48ed51c MZ |
617 | static int its_set_affinity(struct irq_data *d, const struct cpumask *mask_val, |
618 | bool force) | |
619 | { | |
fbf8f40e GK |
620 | unsigned int cpu; |
621 | const struct cpumask *cpu_mask = cpu_online_mask; | |
c48ed51c MZ |
622 | struct its_device *its_dev = irq_data_get_irq_chip_data(d); |
623 | struct its_collection *target_col; | |
624 | u32 id = its_get_event_id(d); | |
625 | ||
fbf8f40e GK |
626 | /* lpi cannot be routed to a redistributor that is on a foreign node */ |
627 | if (its_dev->its->flags & ITS_FLAGS_WORKAROUND_CAVIUM_23144) { | |
628 | if (its_dev->its->numa_node >= 0) { | |
629 | cpu_mask = cpumask_of_node(its_dev->its->numa_node); | |
630 | if (!cpumask_intersects(mask_val, cpu_mask)) | |
631 | return -EINVAL; | |
632 | } | |
633 | } | |
634 | ||
635 | cpu = cpumask_any_and(mask_val, cpu_mask); | |
636 | ||
c48ed51c MZ |
637 | if (cpu >= nr_cpu_ids) |
638 | return -EINVAL; | |
639 | ||
640 | target_col = &its_dev->its->collections[cpu]; | |
641 | its_send_movi(its_dev, target_col, id); | |
591e5bec | 642 | its_dev->event_map.col_map[id] = cpu; |
c48ed51c MZ |
643 | |
644 | return IRQ_SET_MASK_OK_DONE; | |
645 | } | |
646 | ||
b48ac83d MZ |
647 | static void its_irq_compose_msi_msg(struct irq_data *d, struct msi_msg *msg) |
648 | { | |
649 | struct its_device *its_dev = irq_data_get_irq_chip_data(d); | |
650 | struct its_node *its; | |
651 | u64 addr; | |
652 | ||
653 | its = its_dev->its; | |
654 | addr = its->phys_base + GITS_TRANSLATER; | |
655 | ||
656 | msg->address_lo = addr & ((1UL << 32) - 1); | |
657 | msg->address_hi = addr >> 32; | |
658 | msg->data = its_get_event_id(d); | |
659 | } | |
660 | ||
c48ed51c MZ |
661 | static struct irq_chip its_irq_chip = { |
662 | .name = "ITS", | |
663 | .irq_mask = its_mask_irq, | |
664 | .irq_unmask = its_unmask_irq, | |
004fa08d | 665 | .irq_eoi = irq_chip_eoi_parent, |
c48ed51c | 666 | .irq_set_affinity = its_set_affinity, |
b48ac83d MZ |
667 | .irq_compose_msi_msg = its_irq_compose_msi_msg, |
668 | }; | |
669 | ||
bf9529f8 MZ |
670 | /* |
671 | * How we allocate LPIs: | |
672 | * | |
673 | * The GIC has id_bits bits for interrupt identifiers. From there, we | |
674 | * must subtract 8192 which are reserved for SGIs/PPIs/SPIs. Then, as | |
675 | * we allocate LPIs by chunks of 32, we can shift the whole thing by 5 | |
676 | * bits to the right. | |
677 | * | |
678 | * This gives us (((1UL << id_bits) - 8192) >> 5) possible allocations. | |
679 | */ | |
680 | #define IRQS_PER_CHUNK_SHIFT 5 | |
681 | #define IRQS_PER_CHUNK (1 << IRQS_PER_CHUNK_SHIFT) | |
682 | ||
683 | static unsigned long *lpi_bitmap; | |
684 | static u32 lpi_chunks; | |
685 | static DEFINE_SPINLOCK(lpi_lock); | |
686 | ||
687 | static int its_lpi_to_chunk(int lpi) | |
688 | { | |
689 | return (lpi - 8192) >> IRQS_PER_CHUNK_SHIFT; | |
690 | } | |
691 | ||
692 | static int its_chunk_to_lpi(int chunk) | |
693 | { | |
694 | return (chunk << IRQS_PER_CHUNK_SHIFT) + 8192; | |
695 | } | |
696 | ||
04a0e4de | 697 | static int __init its_lpi_init(u32 id_bits) |
bf9529f8 MZ |
698 | { |
699 | lpi_chunks = its_lpi_to_chunk(1UL << id_bits); | |
700 | ||
701 | lpi_bitmap = kzalloc(BITS_TO_LONGS(lpi_chunks) * sizeof(long), | |
702 | GFP_KERNEL); | |
703 | if (!lpi_bitmap) { | |
704 | lpi_chunks = 0; | |
705 | return -ENOMEM; | |
706 | } | |
707 | ||
708 | pr_info("ITS: Allocated %d chunks for LPIs\n", (int)lpi_chunks); | |
709 | return 0; | |
710 | } | |
711 | ||
712 | static unsigned long *its_lpi_alloc_chunks(int nr_irqs, int *base, int *nr_ids) | |
713 | { | |
714 | unsigned long *bitmap = NULL; | |
715 | int chunk_id; | |
716 | int nr_chunks; | |
717 | int i; | |
718 | ||
719 | nr_chunks = DIV_ROUND_UP(nr_irqs, IRQS_PER_CHUNK); | |
720 | ||
721 | spin_lock(&lpi_lock); | |
722 | ||
723 | do { | |
724 | chunk_id = bitmap_find_next_zero_area(lpi_bitmap, lpi_chunks, | |
725 | 0, nr_chunks, 0); | |
726 | if (chunk_id < lpi_chunks) | |
727 | break; | |
728 | ||
729 | nr_chunks--; | |
730 | } while (nr_chunks > 0); | |
731 | ||
732 | if (!nr_chunks) | |
733 | goto out; | |
734 | ||
735 | bitmap = kzalloc(BITS_TO_LONGS(nr_chunks * IRQS_PER_CHUNK) * sizeof (long), | |
736 | GFP_ATOMIC); | |
737 | if (!bitmap) | |
738 | goto out; | |
739 | ||
740 | for (i = 0; i < nr_chunks; i++) | |
741 | set_bit(chunk_id + i, lpi_bitmap); | |
742 | ||
743 | *base = its_chunk_to_lpi(chunk_id); | |
744 | *nr_ids = nr_chunks * IRQS_PER_CHUNK; | |
745 | ||
746 | out: | |
747 | spin_unlock(&lpi_lock); | |
748 | ||
c8415b94 MZ |
749 | if (!bitmap) |
750 | *base = *nr_ids = 0; | |
751 | ||
bf9529f8 MZ |
752 | return bitmap; |
753 | } | |
754 | ||
591e5bec | 755 | static void its_lpi_free(struct event_lpi_map *map) |
bf9529f8 | 756 | { |
591e5bec MZ |
757 | int base = map->lpi_base; |
758 | int nr_ids = map->nr_lpis; | |
bf9529f8 MZ |
759 | int lpi; |
760 | ||
761 | spin_lock(&lpi_lock); | |
762 | ||
763 | for (lpi = base; lpi < (base + nr_ids); lpi += IRQS_PER_CHUNK) { | |
764 | int chunk = its_lpi_to_chunk(lpi); | |
765 | BUG_ON(chunk > lpi_chunks); | |
766 | if (test_bit(chunk, lpi_bitmap)) { | |
767 | clear_bit(chunk, lpi_bitmap); | |
768 | } else { | |
769 | pr_err("Bad LPI chunk %d\n", chunk); | |
770 | } | |
771 | } | |
772 | ||
773 | spin_unlock(&lpi_lock); | |
774 | ||
591e5bec MZ |
775 | kfree(map->lpi_map); |
776 | kfree(map->col_map); | |
bf9529f8 | 777 | } |
1ac19ca6 MZ |
778 | |
779 | /* | |
780 | * We allocate 64kB for PROPBASE. That gives us at most 64K LPIs to | |
781 | * deal with (one configuration byte per interrupt). PENDBASE has to | |
782 | * be 64kB aligned (one bit per LPI, plus 8192 bits for SPI/PPI/SGI). | |
783 | */ | |
784 | #define LPI_PROPBASE_SZ SZ_64K | |
785 | #define LPI_PENDBASE_SZ (LPI_PROPBASE_SZ / 8 + SZ_1K) | |
786 | ||
787 | /* | |
788 | * This is how many bits of ID we need, including the useless ones. | |
789 | */ | |
790 | #define LPI_NRBITS ilog2(LPI_PROPBASE_SZ + SZ_8K) | |
791 | ||
792 | #define LPI_PROP_DEFAULT_PRIO 0xa0 | |
793 | ||
794 | static int __init its_alloc_lpi_tables(void) | |
795 | { | |
796 | phys_addr_t paddr; | |
797 | ||
798 | gic_rdists->prop_page = alloc_pages(GFP_NOWAIT, | |
799 | get_order(LPI_PROPBASE_SZ)); | |
800 | if (!gic_rdists->prop_page) { | |
801 | pr_err("Failed to allocate PROPBASE\n"); | |
802 | return -ENOMEM; | |
803 | } | |
804 | ||
805 | paddr = page_to_phys(gic_rdists->prop_page); | |
806 | pr_info("GIC: using LPI property table @%pa\n", &paddr); | |
807 | ||
808 | /* Priority 0xa0, Group-1, disabled */ | |
809 | memset(page_address(gic_rdists->prop_page), | |
810 | LPI_PROP_DEFAULT_PRIO | LPI_PROP_GROUP1, | |
811 | LPI_PROPBASE_SZ); | |
812 | ||
813 | /* Make sure the GIC will observe the written configuration */ | |
814 | __flush_dcache_area(page_address(gic_rdists->prop_page), LPI_PROPBASE_SZ); | |
815 | ||
816 | return 0; | |
817 | } | |
818 | ||
819 | static const char *its_base_type_string[] = { | |
820 | [GITS_BASER_TYPE_DEVICE] = "Devices", | |
821 | [GITS_BASER_TYPE_VCPU] = "Virtual CPUs", | |
822 | [GITS_BASER_TYPE_CPU] = "Physical CPUs", | |
823 | [GITS_BASER_TYPE_COLLECTION] = "Interrupt Collections", | |
824 | [GITS_BASER_TYPE_RESERVED5] = "Reserved (5)", | |
825 | [GITS_BASER_TYPE_RESERVED6] = "Reserved (6)", | |
826 | [GITS_BASER_TYPE_RESERVED7] = "Reserved (7)", | |
827 | }; | |
828 | ||
2d81d425 SD |
829 | static u64 its_read_baser(struct its_node *its, struct its_baser *baser) |
830 | { | |
831 | u32 idx = baser - its->tables; | |
832 | ||
833 | return readq_relaxed(its->base + GITS_BASER + (idx << 3)); | |
834 | } | |
835 | ||
836 | static void its_write_baser(struct its_node *its, struct its_baser *baser, | |
837 | u64 val) | |
838 | { | |
839 | u32 idx = baser - its->tables; | |
840 | ||
841 | writeq_relaxed(val, its->base + GITS_BASER + (idx << 3)); | |
842 | baser->val = its_read_baser(its, baser); | |
843 | } | |
844 | ||
9347359a | 845 | static int its_setup_baser(struct its_node *its, struct its_baser *baser, |
3faf24ea SD |
846 | u64 cache, u64 shr, u32 psz, u32 order, |
847 | bool indirect) | |
9347359a SD |
848 | { |
849 | u64 val = its_read_baser(its, baser); | |
850 | u64 esz = GITS_BASER_ENTRY_SIZE(val); | |
851 | u64 type = GITS_BASER_TYPE(val); | |
852 | u32 alloc_pages; | |
853 | void *base; | |
854 | u64 tmp; | |
855 | ||
856 | retry_alloc_baser: | |
857 | alloc_pages = (PAGE_ORDER_TO_SIZE(order) / psz); | |
858 | if (alloc_pages > GITS_BASER_PAGES_MAX) { | |
859 | pr_warn("ITS@%pa: %s too large, reduce ITS pages %u->%u\n", | |
860 | &its->phys_base, its_base_type_string[type], | |
861 | alloc_pages, GITS_BASER_PAGES_MAX); | |
862 | alloc_pages = GITS_BASER_PAGES_MAX; | |
863 | order = get_order(GITS_BASER_PAGES_MAX * psz); | |
864 | } | |
865 | ||
866 | base = (void *)__get_free_pages(GFP_KERNEL | __GFP_ZERO, order); | |
867 | if (!base) | |
868 | return -ENOMEM; | |
869 | ||
870 | retry_baser: | |
871 | val = (virt_to_phys(base) | | |
872 | (type << GITS_BASER_TYPE_SHIFT) | | |
873 | ((esz - 1) << GITS_BASER_ENTRY_SIZE_SHIFT) | | |
874 | ((alloc_pages - 1) << GITS_BASER_PAGES_SHIFT) | | |
875 | cache | | |
876 | shr | | |
877 | GITS_BASER_VALID); | |
878 | ||
3faf24ea SD |
879 | val |= indirect ? GITS_BASER_INDIRECT : 0x0; |
880 | ||
9347359a SD |
881 | switch (psz) { |
882 | case SZ_4K: | |
883 | val |= GITS_BASER_PAGE_SIZE_4K; | |
884 | break; | |
885 | case SZ_16K: | |
886 | val |= GITS_BASER_PAGE_SIZE_16K; | |
887 | break; | |
888 | case SZ_64K: | |
889 | val |= GITS_BASER_PAGE_SIZE_64K; | |
890 | break; | |
891 | } | |
892 | ||
893 | its_write_baser(its, baser, val); | |
894 | tmp = baser->val; | |
895 | ||
896 | if ((val ^ tmp) & GITS_BASER_SHAREABILITY_MASK) { | |
897 | /* | |
898 | * Shareability didn't stick. Just use | |
899 | * whatever the read reported, which is likely | |
900 | * to be the only thing this redistributor | |
901 | * supports. If that's zero, make it | |
902 | * non-cacheable as well. | |
903 | */ | |
904 | shr = tmp & GITS_BASER_SHAREABILITY_MASK; | |
905 | if (!shr) { | |
906 | cache = GITS_BASER_nC; | |
907 | __flush_dcache_area(base, PAGE_ORDER_TO_SIZE(order)); | |
908 | } | |
909 | goto retry_baser; | |
910 | } | |
911 | ||
912 | if ((val ^ tmp) & GITS_BASER_PAGE_SIZE_MASK) { | |
913 | /* | |
914 | * Page size didn't stick. Let's try a smaller | |
915 | * size and retry. If we reach 4K, then | |
916 | * something is horribly wrong... | |
917 | */ | |
918 | free_pages((unsigned long)base, order); | |
919 | baser->base = NULL; | |
920 | ||
921 | switch (psz) { | |
922 | case SZ_16K: | |
923 | psz = SZ_4K; | |
924 | goto retry_alloc_baser; | |
925 | case SZ_64K: | |
926 | psz = SZ_16K; | |
927 | goto retry_alloc_baser; | |
928 | } | |
929 | } | |
930 | ||
931 | if (val != tmp) { | |
932 | pr_err("ITS@%pa: %s doesn't stick: %lx %lx\n", | |
933 | &its->phys_base, its_base_type_string[type], | |
934 | (unsigned long) val, (unsigned long) tmp); | |
935 | free_pages((unsigned long)base, order); | |
936 | return -ENXIO; | |
937 | } | |
938 | ||
939 | baser->order = order; | |
940 | baser->base = base; | |
941 | baser->psz = psz; | |
3faf24ea | 942 | tmp = indirect ? GITS_LVL1_ENTRY_SIZE : esz; |
9347359a | 943 | |
3faf24ea SD |
944 | pr_info("ITS@%pa: allocated %d %s @%lx (%s, esz %d, psz %dK, shr %d)\n", |
945 | &its->phys_base, (int)(PAGE_ORDER_TO_SIZE(order) / tmp), | |
9347359a SD |
946 | its_base_type_string[type], |
947 | (unsigned long)virt_to_phys(base), | |
3faf24ea | 948 | indirect ? "indirect" : "flat", (int)esz, |
9347359a SD |
949 | psz / SZ_1K, (int)shr >> GITS_BASER_SHAREABILITY_SHIFT); |
950 | ||
951 | return 0; | |
952 | } | |
953 | ||
3faf24ea SD |
954 | static bool its_parse_baser_device(struct its_node *its, struct its_baser *baser, |
955 | u32 psz, u32 *order) | |
4b75c459 SD |
956 | { |
957 | u64 esz = GITS_BASER_ENTRY_SIZE(its_read_baser(its, baser)); | |
3faf24ea | 958 | u64 val = GITS_BASER_InnerShareable | GITS_BASER_WaWb; |
4b75c459 SD |
959 | u32 ids = its->device_ids; |
960 | u32 new_order = *order; | |
3faf24ea SD |
961 | bool indirect = false; |
962 | ||
963 | /* No need to enable Indirection if memory requirement < (psz*2)bytes */ | |
964 | if ((esz << ids) > (psz * 2)) { | |
965 | /* | |
966 | * Find out whether hw supports a single or two-level table by | |
967 | * table by reading bit at offset '62' after writing '1' to it. | |
968 | */ | |
969 | its_write_baser(its, baser, val | GITS_BASER_INDIRECT); | |
970 | indirect = !!(baser->val & GITS_BASER_INDIRECT); | |
971 | ||
972 | if (indirect) { | |
973 | /* | |
974 | * The size of the lvl2 table is equal to ITS page size | |
975 | * which is 'psz'. For computing lvl1 table size, | |
976 | * subtract ID bits that sparse lvl2 table from 'ids' | |
977 | * which is reported by ITS hardware times lvl1 table | |
978 | * entry size. | |
979 | */ | |
980 | ids -= ilog2(psz / esz); | |
981 | esz = GITS_LVL1_ENTRY_SIZE; | |
982 | } | |
983 | } | |
4b75c459 SD |
984 | |
985 | /* | |
986 | * Allocate as many entries as required to fit the | |
987 | * range of device IDs that the ITS can grok... The ID | |
988 | * space being incredibly sparse, this results in a | |
3faf24ea SD |
989 | * massive waste of memory if two-level device table |
990 | * feature is not supported by hardware. | |
4b75c459 SD |
991 | */ |
992 | new_order = max_t(u32, get_order(esz << ids), new_order); | |
993 | if (new_order >= MAX_ORDER) { | |
994 | new_order = MAX_ORDER - 1; | |
995 | ids = ilog2(PAGE_ORDER_TO_SIZE(new_order) / esz); | |
996 | pr_warn("ITS@%pa: Device Table too large, reduce ids %u->%u\n", | |
997 | &its->phys_base, its->device_ids, ids); | |
998 | } | |
999 | ||
1000 | *order = new_order; | |
3faf24ea SD |
1001 | |
1002 | return indirect; | |
4b75c459 SD |
1003 | } |
1004 | ||
1ac19ca6 MZ |
1005 | static void its_free_tables(struct its_node *its) |
1006 | { | |
1007 | int i; | |
1008 | ||
1009 | for (i = 0; i < GITS_BASER_NR_REGS; i++) { | |
1a485f4d SD |
1010 | if (its->tables[i].base) { |
1011 | free_pages((unsigned long)its->tables[i].base, | |
1012 | its->tables[i].order); | |
1013 | its->tables[i].base = NULL; | |
1ac19ca6 MZ |
1014 | } |
1015 | } | |
1016 | } | |
1017 | ||
0e0b0f69 | 1018 | static int its_alloc_tables(struct its_node *its) |
1ac19ca6 | 1019 | { |
9347359a SD |
1020 | u64 typer = readq_relaxed(its->base + GITS_TYPER); |
1021 | u32 ids = GITS_TYPER_DEVBITS(typer); | |
1ac19ca6 | 1022 | u64 shr = GITS_BASER_InnerShareable; |
9347359a SD |
1023 | u64 cache = GITS_BASER_WaWb; |
1024 | u32 psz = SZ_64K; | |
1025 | int err, i; | |
94100970 RR |
1026 | |
1027 | if (its->flags & ITS_FLAGS_WORKAROUND_CAVIUM_22375) { | |
1028 | /* | |
9347359a SD |
1029 | * erratum 22375: only alloc 8MB table size |
1030 | * erratum 24313: ignore memory access type | |
1031 | */ | |
1032 | cache = GITS_BASER_nCnB; | |
1033 | ids = 0x14; /* 20 bits, 8MB */ | |
94100970 | 1034 | } |
1ac19ca6 | 1035 | |
466b7d16 SD |
1036 | its->device_ids = ids; |
1037 | ||
1ac19ca6 | 1038 | for (i = 0; i < GITS_BASER_NR_REGS; i++) { |
2d81d425 SD |
1039 | struct its_baser *baser = its->tables + i; |
1040 | u64 val = its_read_baser(its, baser); | |
1ac19ca6 | 1041 | u64 type = GITS_BASER_TYPE(val); |
9347359a | 1042 | u32 order = get_order(psz); |
3faf24ea | 1043 | bool indirect = false; |
1ac19ca6 MZ |
1044 | |
1045 | if (type == GITS_BASER_TYPE_NONE) | |
1046 | continue; | |
1047 | ||
4b75c459 | 1048 | if (type == GITS_BASER_TYPE_DEVICE) |
3faf24ea | 1049 | indirect = its_parse_baser_device(its, baser, psz, &order); |
f54b97ed | 1050 | |
3faf24ea | 1051 | err = its_setup_baser(its, baser, cache, shr, psz, order, indirect); |
9347359a SD |
1052 | if (err < 0) { |
1053 | its_free_tables(its); | |
1054 | return err; | |
1ac19ca6 MZ |
1055 | } |
1056 | ||
9347359a SD |
1057 | /* Update settings which will be used for next BASERn */ |
1058 | psz = baser->psz; | |
1059 | cache = baser->val & GITS_BASER_CACHEABILITY_MASK; | |
1060 | shr = baser->val & GITS_BASER_SHAREABILITY_MASK; | |
1ac19ca6 MZ |
1061 | } |
1062 | ||
1063 | return 0; | |
1ac19ca6 MZ |
1064 | } |
1065 | ||
1066 | static int its_alloc_collections(struct its_node *its) | |
1067 | { | |
1068 | its->collections = kzalloc(nr_cpu_ids * sizeof(*its->collections), | |
1069 | GFP_KERNEL); | |
1070 | if (!its->collections) | |
1071 | return -ENOMEM; | |
1072 | ||
1073 | return 0; | |
1074 | } | |
1075 | ||
1076 | static void its_cpu_init_lpis(void) | |
1077 | { | |
1078 | void __iomem *rbase = gic_data_rdist_rd_base(); | |
1079 | struct page *pend_page; | |
1080 | u64 val, tmp; | |
1081 | ||
1082 | /* If we didn't allocate the pending table yet, do it now */ | |
1083 | pend_page = gic_data_rdist()->pend_page; | |
1084 | if (!pend_page) { | |
1085 | phys_addr_t paddr; | |
1086 | /* | |
1087 | * The pending pages have to be at least 64kB aligned, | |
1088 | * hence the 'max(LPI_PENDBASE_SZ, SZ_64K)' below. | |
1089 | */ | |
1090 | pend_page = alloc_pages(GFP_NOWAIT | __GFP_ZERO, | |
1091 | get_order(max(LPI_PENDBASE_SZ, SZ_64K))); | |
1092 | if (!pend_page) { | |
1093 | pr_err("Failed to allocate PENDBASE for CPU%d\n", | |
1094 | smp_processor_id()); | |
1095 | return; | |
1096 | } | |
1097 | ||
1098 | /* Make sure the GIC will observe the zero-ed page */ | |
1099 | __flush_dcache_area(page_address(pend_page), LPI_PENDBASE_SZ); | |
1100 | ||
1101 | paddr = page_to_phys(pend_page); | |
1102 | pr_info("CPU%d: using LPI pending table @%pa\n", | |
1103 | smp_processor_id(), &paddr); | |
1104 | gic_data_rdist()->pend_page = pend_page; | |
1105 | } | |
1106 | ||
1107 | /* Disable LPIs */ | |
1108 | val = readl_relaxed(rbase + GICR_CTLR); | |
1109 | val &= ~GICR_CTLR_ENABLE_LPIS; | |
1110 | writel_relaxed(val, rbase + GICR_CTLR); | |
1111 | ||
1112 | /* | |
1113 | * Make sure any change to the table is observable by the GIC. | |
1114 | */ | |
1115 | dsb(sy); | |
1116 | ||
1117 | /* set PROPBASE */ | |
1118 | val = (page_to_phys(gic_rdists->prop_page) | | |
1119 | GICR_PROPBASER_InnerShareable | | |
1120 | GICR_PROPBASER_WaWb | | |
1121 | ((LPI_NRBITS - 1) & GICR_PROPBASER_IDBITS_MASK)); | |
1122 | ||
1123 | writeq_relaxed(val, rbase + GICR_PROPBASER); | |
1124 | tmp = readq_relaxed(rbase + GICR_PROPBASER); | |
1125 | ||
1126 | if ((tmp ^ val) & GICR_PROPBASER_SHAREABILITY_MASK) { | |
241a386c MZ |
1127 | if (!(tmp & GICR_PROPBASER_SHAREABILITY_MASK)) { |
1128 | /* | |
1129 | * The HW reports non-shareable, we must | |
1130 | * remove the cacheability attributes as | |
1131 | * well. | |
1132 | */ | |
1133 | val &= ~(GICR_PROPBASER_SHAREABILITY_MASK | | |
1134 | GICR_PROPBASER_CACHEABILITY_MASK); | |
1135 | val |= GICR_PROPBASER_nC; | |
1136 | writeq_relaxed(val, rbase + GICR_PROPBASER); | |
1137 | } | |
1ac19ca6 MZ |
1138 | pr_info_once("GIC: using cache flushing for LPI property table\n"); |
1139 | gic_rdists->flags |= RDIST_FLAGS_PROPBASE_NEEDS_FLUSHING; | |
1140 | } | |
1141 | ||
1142 | /* set PENDBASE */ | |
1143 | val = (page_to_phys(pend_page) | | |
4ad3e363 MZ |
1144 | GICR_PENDBASER_InnerShareable | |
1145 | GICR_PENDBASER_WaWb); | |
1ac19ca6 MZ |
1146 | |
1147 | writeq_relaxed(val, rbase + GICR_PENDBASER); | |
241a386c MZ |
1148 | tmp = readq_relaxed(rbase + GICR_PENDBASER); |
1149 | ||
1150 | if (!(tmp & GICR_PENDBASER_SHAREABILITY_MASK)) { | |
1151 | /* | |
1152 | * The HW reports non-shareable, we must remove the | |
1153 | * cacheability attributes as well. | |
1154 | */ | |
1155 | val &= ~(GICR_PENDBASER_SHAREABILITY_MASK | | |
1156 | GICR_PENDBASER_CACHEABILITY_MASK); | |
1157 | val |= GICR_PENDBASER_nC; | |
1158 | writeq_relaxed(val, rbase + GICR_PENDBASER); | |
1159 | } | |
1ac19ca6 MZ |
1160 | |
1161 | /* Enable LPIs */ | |
1162 | val = readl_relaxed(rbase + GICR_CTLR); | |
1163 | val |= GICR_CTLR_ENABLE_LPIS; | |
1164 | writel_relaxed(val, rbase + GICR_CTLR); | |
1165 | ||
1166 | /* Make sure the GIC has seen the above */ | |
1167 | dsb(sy); | |
1168 | } | |
1169 | ||
1170 | static void its_cpu_init_collection(void) | |
1171 | { | |
1172 | struct its_node *its; | |
1173 | int cpu; | |
1174 | ||
1175 | spin_lock(&its_lock); | |
1176 | cpu = smp_processor_id(); | |
1177 | ||
1178 | list_for_each_entry(its, &its_nodes, entry) { | |
1179 | u64 target; | |
1180 | ||
fbf8f40e GK |
1181 | /* avoid cross node collections and its mapping */ |
1182 | if (its->flags & ITS_FLAGS_WORKAROUND_CAVIUM_23144) { | |
1183 | struct device_node *cpu_node; | |
1184 | ||
1185 | cpu_node = of_get_cpu_node(cpu, NULL); | |
1186 | if (its->numa_node != NUMA_NO_NODE && | |
1187 | its->numa_node != of_node_to_nid(cpu_node)) | |
1188 | continue; | |
1189 | } | |
1190 | ||
1ac19ca6 MZ |
1191 | /* |
1192 | * We now have to bind each collection to its target | |
1193 | * redistributor. | |
1194 | */ | |
1195 | if (readq_relaxed(its->base + GITS_TYPER) & GITS_TYPER_PTA) { | |
1196 | /* | |
1197 | * This ITS wants the physical address of the | |
1198 | * redistributor. | |
1199 | */ | |
1200 | target = gic_data_rdist()->phys_base; | |
1201 | } else { | |
1202 | /* | |
1203 | * This ITS wants a linear CPU number. | |
1204 | */ | |
1205 | target = readq_relaxed(gic_data_rdist_rd_base() + GICR_TYPER); | |
263fcd31 | 1206 | target = GICR_TYPER_CPU_NUMBER(target) << 16; |
1ac19ca6 MZ |
1207 | } |
1208 | ||
1209 | /* Perform collection mapping */ | |
1210 | its->collections[cpu].target_address = target; | |
1211 | its->collections[cpu].col_id = cpu; | |
1212 | ||
1213 | its_send_mapc(its, &its->collections[cpu], 1); | |
1214 | its_send_invall(its, &its->collections[cpu]); | |
1215 | } | |
1216 | ||
1217 | spin_unlock(&its_lock); | |
1218 | } | |
84a6a2e7 MZ |
1219 | |
1220 | static struct its_device *its_find_device(struct its_node *its, u32 dev_id) | |
1221 | { | |
1222 | struct its_device *its_dev = NULL, *tmp; | |
3e39e8f5 | 1223 | unsigned long flags; |
84a6a2e7 | 1224 | |
3e39e8f5 | 1225 | raw_spin_lock_irqsave(&its->lock, flags); |
84a6a2e7 MZ |
1226 | |
1227 | list_for_each_entry(tmp, &its->its_device_list, entry) { | |
1228 | if (tmp->device_id == dev_id) { | |
1229 | its_dev = tmp; | |
1230 | break; | |
1231 | } | |
1232 | } | |
1233 | ||
3e39e8f5 | 1234 | raw_spin_unlock_irqrestore(&its->lock, flags); |
84a6a2e7 MZ |
1235 | |
1236 | return its_dev; | |
1237 | } | |
1238 | ||
466b7d16 SD |
1239 | static struct its_baser *its_get_baser(struct its_node *its, u32 type) |
1240 | { | |
1241 | int i; | |
1242 | ||
1243 | for (i = 0; i < GITS_BASER_NR_REGS; i++) { | |
1244 | if (GITS_BASER_TYPE(its->tables[i].val) == type) | |
1245 | return &its->tables[i]; | |
1246 | } | |
1247 | ||
1248 | return NULL; | |
1249 | } | |
1250 | ||
3faf24ea SD |
1251 | static bool its_alloc_device_table(struct its_node *its, u32 dev_id) |
1252 | { | |
1253 | struct its_baser *baser; | |
1254 | struct page *page; | |
1255 | u32 esz, idx; | |
1256 | __le64 *table; | |
1257 | ||
1258 | baser = its_get_baser(its, GITS_BASER_TYPE_DEVICE); | |
1259 | ||
1260 | /* Don't allow device id that exceeds ITS hardware limit */ | |
1261 | if (!baser) | |
1262 | return (ilog2(dev_id) < its->device_ids); | |
1263 | ||
1264 | /* Don't allow device id that exceeds single, flat table limit */ | |
1265 | esz = GITS_BASER_ENTRY_SIZE(baser->val); | |
1266 | if (!(baser->val & GITS_BASER_INDIRECT)) | |
1267 | return (dev_id < (PAGE_ORDER_TO_SIZE(baser->order) / esz)); | |
1268 | ||
1269 | /* Compute 1st level table index & check if that exceeds table limit */ | |
1270 | idx = dev_id >> ilog2(baser->psz / esz); | |
1271 | if (idx >= (PAGE_ORDER_TO_SIZE(baser->order) / GITS_LVL1_ENTRY_SIZE)) | |
1272 | return false; | |
1273 | ||
1274 | table = baser->base; | |
1275 | ||
1276 | /* Allocate memory for 2nd level table */ | |
1277 | if (!table[idx]) { | |
1278 | page = alloc_pages(GFP_KERNEL | __GFP_ZERO, get_order(baser->psz)); | |
1279 | if (!page) | |
1280 | return false; | |
1281 | ||
1282 | /* Flush Lvl2 table to PoC if hw doesn't support coherency */ | |
1283 | if (!(baser->val & GITS_BASER_SHAREABILITY_MASK)) | |
1284 | __flush_dcache_area(page_address(page), baser->psz); | |
1285 | ||
1286 | table[idx] = cpu_to_le64(page_to_phys(page) | GITS_BASER_VALID); | |
1287 | ||
1288 | /* Flush Lvl1 entry to PoC if hw doesn't support coherency */ | |
1289 | if (!(baser->val & GITS_BASER_SHAREABILITY_MASK)) | |
1290 | __flush_dcache_area(table + idx, GITS_LVL1_ENTRY_SIZE); | |
1291 | ||
1292 | /* Ensure updated table contents are visible to ITS hardware */ | |
1293 | dsb(sy); | |
1294 | } | |
1295 | ||
1296 | return true; | |
1297 | } | |
1298 | ||
84a6a2e7 MZ |
1299 | static struct its_device *its_create_device(struct its_node *its, u32 dev_id, |
1300 | int nvecs) | |
1301 | { | |
1302 | struct its_device *dev; | |
1303 | unsigned long *lpi_map; | |
3e39e8f5 | 1304 | unsigned long flags; |
591e5bec | 1305 | u16 *col_map = NULL; |
84a6a2e7 MZ |
1306 | void *itt; |
1307 | int lpi_base; | |
1308 | int nr_lpis; | |
c8481267 | 1309 | int nr_ites; |
84a6a2e7 MZ |
1310 | int sz; |
1311 | ||
3faf24ea | 1312 | if (!its_alloc_device_table(its, dev_id)) |
466b7d16 SD |
1313 | return NULL; |
1314 | ||
84a6a2e7 | 1315 | dev = kzalloc(sizeof(*dev), GFP_KERNEL); |
c8481267 MZ |
1316 | /* |
1317 | * At least one bit of EventID is being used, hence a minimum | |
1318 | * of two entries. No, the architecture doesn't let you | |
1319 | * express an ITT with a single entry. | |
1320 | */ | |
96555c47 | 1321 | nr_ites = max(2UL, roundup_pow_of_two(nvecs)); |
c8481267 | 1322 | sz = nr_ites * its->ite_size; |
84a6a2e7 | 1323 | sz = max(sz, ITS_ITT_ALIGN) + ITS_ITT_ALIGN - 1; |
6c834125 | 1324 | itt = kzalloc(sz, GFP_KERNEL); |
84a6a2e7 | 1325 | lpi_map = its_lpi_alloc_chunks(nvecs, &lpi_base, &nr_lpis); |
591e5bec MZ |
1326 | if (lpi_map) |
1327 | col_map = kzalloc(sizeof(*col_map) * nr_lpis, GFP_KERNEL); | |
84a6a2e7 | 1328 | |
591e5bec | 1329 | if (!dev || !itt || !lpi_map || !col_map) { |
84a6a2e7 MZ |
1330 | kfree(dev); |
1331 | kfree(itt); | |
1332 | kfree(lpi_map); | |
591e5bec | 1333 | kfree(col_map); |
84a6a2e7 MZ |
1334 | return NULL; |
1335 | } | |
1336 | ||
5a9a8915 MZ |
1337 | __flush_dcache_area(itt, sz); |
1338 | ||
84a6a2e7 MZ |
1339 | dev->its = its; |
1340 | dev->itt = itt; | |
c8481267 | 1341 | dev->nr_ites = nr_ites; |
591e5bec MZ |
1342 | dev->event_map.lpi_map = lpi_map; |
1343 | dev->event_map.col_map = col_map; | |
1344 | dev->event_map.lpi_base = lpi_base; | |
1345 | dev->event_map.nr_lpis = nr_lpis; | |
84a6a2e7 MZ |
1346 | dev->device_id = dev_id; |
1347 | INIT_LIST_HEAD(&dev->entry); | |
1348 | ||
3e39e8f5 | 1349 | raw_spin_lock_irqsave(&its->lock, flags); |
84a6a2e7 | 1350 | list_add(&dev->entry, &its->its_device_list); |
3e39e8f5 | 1351 | raw_spin_unlock_irqrestore(&its->lock, flags); |
84a6a2e7 | 1352 | |
84a6a2e7 MZ |
1353 | /* Map device to its ITT */ |
1354 | its_send_mapd(dev, 1); | |
1355 | ||
1356 | return dev; | |
1357 | } | |
1358 | ||
1359 | static void its_free_device(struct its_device *its_dev) | |
1360 | { | |
3e39e8f5 MZ |
1361 | unsigned long flags; |
1362 | ||
1363 | raw_spin_lock_irqsave(&its_dev->its->lock, flags); | |
84a6a2e7 | 1364 | list_del(&its_dev->entry); |
3e39e8f5 | 1365 | raw_spin_unlock_irqrestore(&its_dev->its->lock, flags); |
84a6a2e7 MZ |
1366 | kfree(its_dev->itt); |
1367 | kfree(its_dev); | |
1368 | } | |
b48ac83d MZ |
1369 | |
1370 | static int its_alloc_device_irq(struct its_device *dev, irq_hw_number_t *hwirq) | |
1371 | { | |
1372 | int idx; | |
1373 | ||
591e5bec MZ |
1374 | idx = find_first_zero_bit(dev->event_map.lpi_map, |
1375 | dev->event_map.nr_lpis); | |
1376 | if (idx == dev->event_map.nr_lpis) | |
b48ac83d MZ |
1377 | return -ENOSPC; |
1378 | ||
591e5bec MZ |
1379 | *hwirq = dev->event_map.lpi_base + idx; |
1380 | set_bit(idx, dev->event_map.lpi_map); | |
b48ac83d | 1381 | |
b48ac83d MZ |
1382 | return 0; |
1383 | } | |
1384 | ||
54456db9 MZ |
1385 | static int its_msi_prepare(struct irq_domain *domain, struct device *dev, |
1386 | int nvec, msi_alloc_info_t *info) | |
e8137f4f | 1387 | { |
b48ac83d | 1388 | struct its_node *its; |
b48ac83d | 1389 | struct its_device *its_dev; |
54456db9 MZ |
1390 | struct msi_domain_info *msi_info; |
1391 | u32 dev_id; | |
1392 | ||
1393 | /* | |
1394 | * We ignore "dev" entierely, and rely on the dev_id that has | |
1395 | * been passed via the scratchpad. This limits this domain's | |
1396 | * usefulness to upper layers that definitely know that they | |
1397 | * are built on top of the ITS. | |
1398 | */ | |
1399 | dev_id = info->scratchpad[0].ul; | |
1400 | ||
1401 | msi_info = msi_get_domain_info(domain); | |
1402 | its = msi_info->data; | |
e8137f4f | 1403 | |
f130420e | 1404 | its_dev = its_find_device(its, dev_id); |
e8137f4f MZ |
1405 | if (its_dev) { |
1406 | /* | |
1407 | * We already have seen this ID, probably through | |
1408 | * another alias (PCI bridge of some sort). No need to | |
1409 | * create the device. | |
1410 | */ | |
f130420e | 1411 | pr_debug("Reusing ITT for devID %x\n", dev_id); |
e8137f4f MZ |
1412 | goto out; |
1413 | } | |
b48ac83d | 1414 | |
f130420e | 1415 | its_dev = its_create_device(its, dev_id, nvec); |
b48ac83d MZ |
1416 | if (!its_dev) |
1417 | return -ENOMEM; | |
1418 | ||
f130420e | 1419 | pr_debug("ITT %d entries, %d bits\n", nvec, ilog2(nvec)); |
e8137f4f | 1420 | out: |
b48ac83d | 1421 | info->scratchpad[0].ptr = its_dev; |
b48ac83d MZ |
1422 | return 0; |
1423 | } | |
1424 | ||
54456db9 MZ |
1425 | static struct msi_domain_ops its_msi_domain_ops = { |
1426 | .msi_prepare = its_msi_prepare, | |
1427 | }; | |
1428 | ||
b48ac83d MZ |
1429 | static int its_irq_gic_domain_alloc(struct irq_domain *domain, |
1430 | unsigned int virq, | |
1431 | irq_hw_number_t hwirq) | |
1432 | { | |
f833f57f MZ |
1433 | struct irq_fwspec fwspec; |
1434 | ||
1435 | if (irq_domain_get_of_node(domain->parent)) { | |
1436 | fwspec.fwnode = domain->parent->fwnode; | |
1437 | fwspec.param_count = 3; | |
1438 | fwspec.param[0] = GIC_IRQ_TYPE_LPI; | |
1439 | fwspec.param[1] = hwirq; | |
1440 | fwspec.param[2] = IRQ_TYPE_EDGE_RISING; | |
1441 | } else { | |
1442 | return -EINVAL; | |
1443 | } | |
b48ac83d | 1444 | |
f833f57f | 1445 | return irq_domain_alloc_irqs_parent(domain, virq, 1, &fwspec); |
b48ac83d MZ |
1446 | } |
1447 | ||
1448 | static int its_irq_domain_alloc(struct irq_domain *domain, unsigned int virq, | |
1449 | unsigned int nr_irqs, void *args) | |
1450 | { | |
1451 | msi_alloc_info_t *info = args; | |
1452 | struct its_device *its_dev = info->scratchpad[0].ptr; | |
1453 | irq_hw_number_t hwirq; | |
1454 | int err; | |
1455 | int i; | |
1456 | ||
1457 | for (i = 0; i < nr_irqs; i++) { | |
1458 | err = its_alloc_device_irq(its_dev, &hwirq); | |
1459 | if (err) | |
1460 | return err; | |
1461 | ||
1462 | err = its_irq_gic_domain_alloc(domain, virq + i, hwirq); | |
1463 | if (err) | |
1464 | return err; | |
1465 | ||
1466 | irq_domain_set_hwirq_and_chip(domain, virq + i, | |
1467 | hwirq, &its_irq_chip, its_dev); | |
f130420e MZ |
1468 | pr_debug("ID:%d pID:%d vID:%d\n", |
1469 | (int)(hwirq - its_dev->event_map.lpi_base), | |
1470 | (int) hwirq, virq + i); | |
b48ac83d MZ |
1471 | } |
1472 | ||
1473 | return 0; | |
1474 | } | |
1475 | ||
aca268df MZ |
1476 | static void its_irq_domain_activate(struct irq_domain *domain, |
1477 | struct irq_data *d) | |
1478 | { | |
1479 | struct its_device *its_dev = irq_data_get_irq_chip_data(d); | |
1480 | u32 event = its_get_event_id(d); | |
fbf8f40e GK |
1481 | const struct cpumask *cpu_mask = cpu_online_mask; |
1482 | ||
1483 | /* get the cpu_mask of local node */ | |
1484 | if (its_dev->its->numa_node >= 0) | |
1485 | cpu_mask = cpumask_of_node(its_dev->its->numa_node); | |
aca268df | 1486 | |
591e5bec | 1487 | /* Bind the LPI to the first possible CPU */ |
fbf8f40e | 1488 | its_dev->event_map.col_map[event] = cpumask_first(cpu_mask); |
591e5bec | 1489 | |
aca268df MZ |
1490 | /* Map the GIC IRQ and event to the device */ |
1491 | its_send_mapvi(its_dev, d->hwirq, event); | |
1492 | } | |
1493 | ||
1494 | static void its_irq_domain_deactivate(struct irq_domain *domain, | |
1495 | struct irq_data *d) | |
1496 | { | |
1497 | struct its_device *its_dev = irq_data_get_irq_chip_data(d); | |
1498 | u32 event = its_get_event_id(d); | |
1499 | ||
1500 | /* Stop the delivery of interrupts */ | |
1501 | its_send_discard(its_dev, event); | |
1502 | } | |
1503 | ||
b48ac83d MZ |
1504 | static void its_irq_domain_free(struct irq_domain *domain, unsigned int virq, |
1505 | unsigned int nr_irqs) | |
1506 | { | |
1507 | struct irq_data *d = irq_domain_get_irq_data(domain, virq); | |
1508 | struct its_device *its_dev = irq_data_get_irq_chip_data(d); | |
1509 | int i; | |
1510 | ||
1511 | for (i = 0; i < nr_irqs; i++) { | |
1512 | struct irq_data *data = irq_domain_get_irq_data(domain, | |
1513 | virq + i); | |
aca268df | 1514 | u32 event = its_get_event_id(data); |
b48ac83d MZ |
1515 | |
1516 | /* Mark interrupt index as unused */ | |
591e5bec | 1517 | clear_bit(event, its_dev->event_map.lpi_map); |
b48ac83d MZ |
1518 | |
1519 | /* Nuke the entry in the domain */ | |
2da39949 | 1520 | irq_domain_reset_irq_data(data); |
b48ac83d MZ |
1521 | } |
1522 | ||
1523 | /* If all interrupts have been freed, start mopping the floor */ | |
591e5bec MZ |
1524 | if (bitmap_empty(its_dev->event_map.lpi_map, |
1525 | its_dev->event_map.nr_lpis)) { | |
1526 | its_lpi_free(&its_dev->event_map); | |
b48ac83d MZ |
1527 | |
1528 | /* Unmap device/itt */ | |
1529 | its_send_mapd(its_dev, 0); | |
1530 | its_free_device(its_dev); | |
1531 | } | |
1532 | ||
1533 | irq_domain_free_irqs_parent(domain, virq, nr_irqs); | |
1534 | } | |
1535 | ||
1536 | static const struct irq_domain_ops its_domain_ops = { | |
1537 | .alloc = its_irq_domain_alloc, | |
1538 | .free = its_irq_domain_free, | |
aca268df MZ |
1539 | .activate = its_irq_domain_activate, |
1540 | .deactivate = its_irq_domain_deactivate, | |
b48ac83d | 1541 | }; |
4c21f3c2 | 1542 | |
4559fbb3 YW |
1543 | static int its_force_quiescent(void __iomem *base) |
1544 | { | |
1545 | u32 count = 1000000; /* 1s */ | |
1546 | u32 val; | |
1547 | ||
1548 | val = readl_relaxed(base + GITS_CTLR); | |
7611da86 DD |
1549 | /* |
1550 | * GIC architecture specification requires the ITS to be both | |
1551 | * disabled and quiescent for writes to GITS_BASER<n> or | |
1552 | * GITS_CBASER to not have UNPREDICTABLE results. | |
1553 | */ | |
1554 | if ((val & GITS_CTLR_QUIESCENT) && !(val & GITS_CTLR_ENABLE)) | |
4559fbb3 YW |
1555 | return 0; |
1556 | ||
1557 | /* Disable the generation of all interrupts to this ITS */ | |
1558 | val &= ~GITS_CTLR_ENABLE; | |
1559 | writel_relaxed(val, base + GITS_CTLR); | |
1560 | ||
1561 | /* Poll GITS_CTLR and wait until ITS becomes quiescent */ | |
1562 | while (1) { | |
1563 | val = readl_relaxed(base + GITS_CTLR); | |
1564 | if (val & GITS_CTLR_QUIESCENT) | |
1565 | return 0; | |
1566 | ||
1567 | count--; | |
1568 | if (!count) | |
1569 | return -EBUSY; | |
1570 | ||
1571 | cpu_relax(); | |
1572 | udelay(1); | |
1573 | } | |
1574 | } | |
1575 | ||
94100970 RR |
1576 | static void __maybe_unused its_enable_quirk_cavium_22375(void *data) |
1577 | { | |
1578 | struct its_node *its = data; | |
1579 | ||
1580 | its->flags |= ITS_FLAGS_WORKAROUND_CAVIUM_22375; | |
1581 | } | |
1582 | ||
fbf8f40e GK |
1583 | static void __maybe_unused its_enable_quirk_cavium_23144(void *data) |
1584 | { | |
1585 | struct its_node *its = data; | |
1586 | ||
1587 | its->flags |= ITS_FLAGS_WORKAROUND_CAVIUM_23144; | |
1588 | } | |
1589 | ||
67510cca | 1590 | static const struct gic_quirk its_quirks[] = { |
94100970 RR |
1591 | #ifdef CONFIG_CAVIUM_ERRATUM_22375 |
1592 | { | |
1593 | .desc = "ITS: Cavium errata 22375, 24313", | |
1594 | .iidr = 0xa100034c, /* ThunderX pass 1.x */ | |
1595 | .mask = 0xffff0fff, | |
1596 | .init = its_enable_quirk_cavium_22375, | |
1597 | }, | |
fbf8f40e GK |
1598 | #endif |
1599 | #ifdef CONFIG_CAVIUM_ERRATUM_23144 | |
1600 | { | |
1601 | .desc = "ITS: Cavium erratum 23144", | |
1602 | .iidr = 0xa100034c, /* ThunderX pass 1.x */ | |
1603 | .mask = 0xffff0fff, | |
1604 | .init = its_enable_quirk_cavium_23144, | |
1605 | }, | |
94100970 | 1606 | #endif |
67510cca RR |
1607 | { |
1608 | } | |
1609 | }; | |
1610 | ||
1611 | static void its_enable_quirks(struct its_node *its) | |
1612 | { | |
1613 | u32 iidr = readl_relaxed(its->base + GITS_IIDR); | |
1614 | ||
1615 | gic_enable_quirks(iidr, its_quirks, its); | |
1616 | } | |
1617 | ||
db40f0a7 | 1618 | static int its_init_domain(struct fwnode_handle *handle, struct its_node *its) |
d14ae5e6 TN |
1619 | { |
1620 | struct irq_domain *inner_domain; | |
1621 | struct msi_domain_info *info; | |
1622 | ||
1623 | info = kzalloc(sizeof(*info), GFP_KERNEL); | |
1624 | if (!info) | |
1625 | return -ENOMEM; | |
1626 | ||
db40f0a7 | 1627 | inner_domain = irq_domain_create_tree(handle, &its_domain_ops, its); |
d14ae5e6 TN |
1628 | if (!inner_domain) { |
1629 | kfree(info); | |
1630 | return -ENOMEM; | |
1631 | } | |
1632 | ||
db40f0a7 | 1633 | inner_domain->parent = its_parent; |
d14ae5e6 TN |
1634 | inner_domain->bus_token = DOMAIN_BUS_NEXUS; |
1635 | info->ops = &its_msi_domain_ops; | |
1636 | info->data = its; | |
1637 | inner_domain->host_data = info; | |
1638 | ||
1639 | return 0; | |
1640 | } | |
1641 | ||
db40f0a7 TN |
1642 | static int __init its_probe_one(struct resource *res, |
1643 | struct fwnode_handle *handle, int numa_node) | |
4c21f3c2 | 1644 | { |
4c21f3c2 MZ |
1645 | struct its_node *its; |
1646 | void __iomem *its_base; | |
1647 | u32 val; | |
1648 | u64 baser, tmp; | |
1649 | int err; | |
1650 | ||
db40f0a7 | 1651 | its_base = ioremap(res->start, resource_size(res)); |
4c21f3c2 | 1652 | if (!its_base) { |
db40f0a7 | 1653 | pr_warn("ITS@%pa: Unable to map ITS registers\n", &res->start); |
4c21f3c2 MZ |
1654 | return -ENOMEM; |
1655 | } | |
1656 | ||
1657 | val = readl_relaxed(its_base + GITS_PIDR2) & GIC_PIDR2_ARCH_MASK; | |
1658 | if (val != 0x30 && val != 0x40) { | |
db40f0a7 | 1659 | pr_warn("ITS@%pa: No ITS detected, giving up\n", &res->start); |
4c21f3c2 MZ |
1660 | err = -ENODEV; |
1661 | goto out_unmap; | |
1662 | } | |
1663 | ||
4559fbb3 YW |
1664 | err = its_force_quiescent(its_base); |
1665 | if (err) { | |
db40f0a7 | 1666 | pr_warn("ITS@%pa: Failed to quiesce, giving up\n", &res->start); |
4559fbb3 YW |
1667 | goto out_unmap; |
1668 | } | |
1669 | ||
db40f0a7 | 1670 | pr_info("ITS %pR\n", res); |
4c21f3c2 MZ |
1671 | |
1672 | its = kzalloc(sizeof(*its), GFP_KERNEL); | |
1673 | if (!its) { | |
1674 | err = -ENOMEM; | |
1675 | goto out_unmap; | |
1676 | } | |
1677 | ||
1678 | raw_spin_lock_init(&its->lock); | |
1679 | INIT_LIST_HEAD(&its->entry); | |
1680 | INIT_LIST_HEAD(&its->its_device_list); | |
1681 | its->base = its_base; | |
db40f0a7 | 1682 | its->phys_base = res->start; |
4c21f3c2 | 1683 | its->ite_size = ((readl_relaxed(its_base + GITS_TYPER) >> 4) & 0xf) + 1; |
db40f0a7 | 1684 | its->numa_node = numa_node; |
4c21f3c2 MZ |
1685 | |
1686 | its->cmd_base = kzalloc(ITS_CMD_QUEUE_SZ, GFP_KERNEL); | |
1687 | if (!its->cmd_base) { | |
1688 | err = -ENOMEM; | |
1689 | goto out_free_its; | |
1690 | } | |
1691 | its->cmd_write = its->cmd_base; | |
1692 | ||
67510cca RR |
1693 | its_enable_quirks(its); |
1694 | ||
0e0b0f69 | 1695 | err = its_alloc_tables(its); |
4c21f3c2 MZ |
1696 | if (err) |
1697 | goto out_free_cmd; | |
1698 | ||
1699 | err = its_alloc_collections(its); | |
1700 | if (err) | |
1701 | goto out_free_tables; | |
1702 | ||
1703 | baser = (virt_to_phys(its->cmd_base) | | |
1704 | GITS_CBASER_WaWb | | |
1705 | GITS_CBASER_InnerShareable | | |
1706 | (ITS_CMD_QUEUE_SZ / SZ_4K - 1) | | |
1707 | GITS_CBASER_VALID); | |
1708 | ||
1709 | writeq_relaxed(baser, its->base + GITS_CBASER); | |
1710 | tmp = readq_relaxed(its->base + GITS_CBASER); | |
4c21f3c2 | 1711 | |
4ad3e363 | 1712 | if ((tmp ^ baser) & GITS_CBASER_SHAREABILITY_MASK) { |
241a386c MZ |
1713 | if (!(tmp & GITS_CBASER_SHAREABILITY_MASK)) { |
1714 | /* | |
1715 | * The HW reports non-shareable, we must | |
1716 | * remove the cacheability attributes as | |
1717 | * well. | |
1718 | */ | |
1719 | baser &= ~(GITS_CBASER_SHAREABILITY_MASK | | |
1720 | GITS_CBASER_CACHEABILITY_MASK); | |
1721 | baser |= GITS_CBASER_nC; | |
1722 | writeq_relaxed(baser, its->base + GITS_CBASER); | |
1723 | } | |
4c21f3c2 MZ |
1724 | pr_info("ITS: using cache flushing for cmd queue\n"); |
1725 | its->flags |= ITS_FLAGS_CMDQ_NEEDS_FLUSHING; | |
1726 | } | |
1727 | ||
241a386c MZ |
1728 | writeq_relaxed(0, its->base + GITS_CWRITER); |
1729 | writel_relaxed(GITS_CTLR_ENABLE, its->base + GITS_CTLR); | |
1730 | ||
db40f0a7 | 1731 | err = its_init_domain(handle, its); |
d14ae5e6 TN |
1732 | if (err) |
1733 | goto out_free_tables; | |
4c21f3c2 MZ |
1734 | |
1735 | spin_lock(&its_lock); | |
1736 | list_add(&its->entry, &its_nodes); | |
1737 | spin_unlock(&its_lock); | |
1738 | ||
1739 | return 0; | |
1740 | ||
4c21f3c2 MZ |
1741 | out_free_tables: |
1742 | its_free_tables(its); | |
1743 | out_free_cmd: | |
1744 | kfree(its->cmd_base); | |
1745 | out_free_its: | |
1746 | kfree(its); | |
1747 | out_unmap: | |
1748 | iounmap(its_base); | |
db40f0a7 | 1749 | pr_err("ITS@%pa: failed probing (%d)\n", &res->start, err); |
4c21f3c2 MZ |
1750 | return err; |
1751 | } | |
1752 | ||
1753 | static bool gic_rdists_supports_plpis(void) | |
1754 | { | |
1755 | return !!(readl_relaxed(gic_data_rdist_rd_base() + GICR_TYPER) & GICR_TYPER_PLPIS); | |
1756 | } | |
1757 | ||
1758 | int its_cpu_init(void) | |
1759 | { | |
4c21f3c2 | 1760 | if (!list_empty(&its_nodes)) { |
16acae72 VM |
1761 | if (!gic_rdists_supports_plpis()) { |
1762 | pr_info("CPU%d: LPIs not supported\n", smp_processor_id()); | |
1763 | return -ENXIO; | |
1764 | } | |
4c21f3c2 MZ |
1765 | its_cpu_init_lpis(); |
1766 | its_cpu_init_collection(); | |
1767 | } | |
1768 | ||
1769 | return 0; | |
1770 | } | |
1771 | ||
1772 | static struct of_device_id its_device_id[] = { | |
1773 | { .compatible = "arm,gic-v3-its", }, | |
1774 | {}, | |
1775 | }; | |
1776 | ||
db40f0a7 | 1777 | static int __init its_of_probe(struct device_node *node) |
4c21f3c2 MZ |
1778 | { |
1779 | struct device_node *np; | |
db40f0a7 | 1780 | struct resource res; |
4c21f3c2 MZ |
1781 | |
1782 | for (np = of_find_matching_node(node, its_device_id); np; | |
1783 | np = of_find_matching_node(np, its_device_id)) { | |
d14ae5e6 TN |
1784 | if (!of_property_read_bool(np, "msi-controller")) { |
1785 | pr_warn("%s: no msi-controller property, ITS ignored\n", | |
1786 | np->full_name); | |
1787 | continue; | |
1788 | } | |
1789 | ||
db40f0a7 TN |
1790 | if (of_address_to_resource(np, 0, &res)) { |
1791 | pr_warn("%s: no regs?\n", np->full_name); | |
1792 | continue; | |
1793 | } | |
1794 | ||
1795 | its_probe_one(&res, &np->fwnode, of_node_to_nid(np)); | |
4c21f3c2 | 1796 | } |
db40f0a7 TN |
1797 | return 0; |
1798 | } | |
1799 | ||
1800 | int __init its_init(struct fwnode_handle *handle, struct rdists *rdists, | |
1801 | struct irq_domain *parent_domain) | |
1802 | { | |
1803 | struct device_node *of_node; | |
1804 | ||
1805 | its_parent = parent_domain; | |
1806 | of_node = to_of_node(handle); | |
1807 | if (of_node) | |
1808 | its_of_probe(of_node); | |
1809 | else | |
1810 | return -ENODEV; | |
4c21f3c2 MZ |
1811 | |
1812 | if (list_empty(&its_nodes)) { | |
1813 | pr_warn("ITS: No ITS available, not enabling LPIs\n"); | |
1814 | return -ENXIO; | |
1815 | } | |
1816 | ||
1817 | gic_rdists = rdists; | |
4c21f3c2 MZ |
1818 | its_alloc_lpi_tables(); |
1819 | its_lpi_init(rdists->id_bits); | |
1820 | ||
1821 | return 0; | |
1822 | } |