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Commit | Line | Data |
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1c1e45d1 HV |
1 | /* |
2 | * cx18 ADEC audio functions | |
3 | * | |
4 | * Derived from cx25840-core.c | |
5 | * | |
6 | * Copyright (C) 2007 Hans Verkuil <hverkuil@xs4all.nl> | |
6afdeaf8 | 7 | * Copyright (C) 2008 Andy Walls <awalls@md.metrocast.net> |
1c1e45d1 HV |
8 | * |
9 | * This program is free software; you can redistribute it and/or | |
10 | * modify it under the terms of the GNU General Public License | |
11 | * as published by the Free Software Foundation; either version 2 | |
12 | * of the License, or (at your option) any later version. | |
13 | * | |
14 | * This program is distributed in the hope that it will be useful, | |
15 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
17 | * GNU General Public License for more details. | |
18 | * | |
19 | * You should have received a copy of the GNU General Public License | |
20 | * along with this program; if not, write to the Free Software | |
21 | * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA | |
22 | * 02110-1301, USA. | |
23 | */ | |
24 | ||
25 | #include "cx18-driver.h" | |
b1526421 | 26 | #include "cx18-io.h" |
1a267046 | 27 | #include "cx18-cards.h" |
1c1e45d1 HV |
28 | |
29 | int cx18_av_write(struct cx18 *cx, u16 addr, u8 value) | |
30 | { | |
b1526421 | 31 | u32 reg = 0xc40000 + (addr & ~3); |
1c1e45d1 HV |
32 | u32 mask = 0xff; |
33 | int shift = (addr & 3) * 8; | |
b1526421 | 34 | u32 x = cx18_read_reg(cx, reg); |
1c1e45d1 HV |
35 | |
36 | x = (x & ~(mask << shift)) | ((u32)value << shift); | |
b1526421 | 37 | cx18_write_reg(cx, x, reg); |
1c1e45d1 HV |
38 | return 0; |
39 | } | |
40 | ||
ced07371 AW |
41 | int cx18_av_write_expect(struct cx18 *cx, u16 addr, u8 value, u8 eval, u8 mask) |
42 | { | |
43 | u32 reg = 0xc40000 + (addr & ~3); | |
44 | int shift = (addr & 3) * 8; | |
45 | u32 x = cx18_read_reg(cx, reg); | |
46 | ||
47 | x = (x & ~((u32)0xff << shift)) | ((u32)value << shift); | |
48 | cx18_write_reg_expect(cx, x, reg, | |
49 | ((u32)eval << shift), ((u32)mask << shift)); | |
50 | return 0; | |
51 | } | |
52 | ||
1c1e45d1 HV |
53 | int cx18_av_write4(struct cx18 *cx, u16 addr, u32 value) |
54 | { | |
b1526421 | 55 | cx18_write_reg(cx, value, 0xc40000 + addr); |
1c1e45d1 HV |
56 | return 0; |
57 | } | |
58 | ||
ced07371 AW |
59 | int |
60 | cx18_av_write4_expect(struct cx18 *cx, u16 addr, u32 value, u32 eval, u32 mask) | |
61 | { | |
62 | cx18_write_reg_expect(cx, value, 0xc40000 + addr, eval, mask); | |
63 | return 0; | |
64 | } | |
65 | ||
d267d851 AW |
66 | int cx18_av_write4_noretry(struct cx18 *cx, u16 addr, u32 value) |
67 | { | |
68 | cx18_write_reg_noretry(cx, value, 0xc40000 + addr); | |
69 | return 0; | |
70 | } | |
71 | ||
1c1e45d1 HV |
72 | u8 cx18_av_read(struct cx18 *cx, u16 addr) |
73 | { | |
b1526421 | 74 | u32 x = cx18_read_reg(cx, 0xc40000 + (addr & ~3)); |
1c1e45d1 HV |
75 | int shift = (addr & 3) * 8; |
76 | ||
77 | return (x >> shift) & 0xff; | |
78 | } | |
79 | ||
80 | u32 cx18_av_read4(struct cx18 *cx, u16 addr) | |
81 | { | |
b1526421 | 82 | return cx18_read_reg(cx, 0xc40000 + addr); |
1c1e45d1 HV |
83 | } |
84 | ||
85 | int cx18_av_and_or(struct cx18 *cx, u16 addr, unsigned and_mask, | |
86 | u8 or_value) | |
87 | { | |
88 | return cx18_av_write(cx, addr, | |
89 | (cx18_av_read(cx, addr) & and_mask) | | |
90 | or_value); | |
91 | } | |
92 | ||
93 | int cx18_av_and_or4(struct cx18 *cx, u16 addr, u32 and_mask, | |
94 | u32 or_value) | |
95 | { | |
96 | return cx18_av_write4(cx, addr, | |
97 | (cx18_av_read4(cx, addr) & and_mask) | | |
98 | or_value); | |
99 | } | |
100 | ||
7f3ea4de | 101 | static void cx18_av_init(struct cx18 *cx) |
1c1e45d1 | 102 | { |
f4672dff AW |
103 | /* |
104 | * The crystal freq used in calculations in this driver will be | |
105 | * 28.636360 MHz. | |
106 | * Aim to run the PLLs' VCOs near 400 MHz to minimze errors. | |
107 | */ | |
108 | ||
109 | /* | |
110 | * VDCLK Integer = 0x0f, Post Divider = 0x04 | |
111 | * AIMCLK Integer = 0x0e, Post Divider = 0x16 | |
112 | */ | |
113 | cx18_av_write4(cx, CXADEC_PLL_CTRL1, 0x160e040f); | |
114 | ||
115 | /* VDCLK Fraction = 0x2be2fe */ | |
116 | /* xtal * 0xf.15f17f0/4 = 108 MHz: 432 MHz before post divide */ | |
117 | cx18_av_write4(cx, CXADEC_VID_PLL_FRAC, 0x002be2fe); | |
118 | ||
119 | /* AIMCLK Fraction = 0x05227ad */ | |
120 | /* xtal * 0xe.2913d68/0x16 = 48000 * 384: 406 MHz pre post-div*/ | |
121 | cx18_av_write4(cx, CXADEC_AUX_PLL_FRAC, 0x005227ad); | |
122 | ||
123 | /* SA_MCLK_SEL=1, SA_MCLK_DIV=0x16 */ | |
124 | cx18_av_write(cx, CXADEC_I2S_MCLK, 0x56); | |
f4672dff AW |
125 | } |
126 | ||
127 | static void cx18_av_initialize(struct v4l2_subdev *sd) | |
128 | { | |
129 | struct cx18_av_state *state = to_cx18_av_state(sd); | |
130 | struct cx18 *cx = v4l2_get_subdevdata(sd); | |
a75b9be1 | 131 | int default_volume; |
1c1e45d1 HV |
132 | u32 v; |
133 | ||
134 | cx18_av_loadfw(cx); | |
135 | /* Stop 8051 code execution */ | |
ced07371 AW |
136 | cx18_av_write4_expect(cx, CXADEC_DL_CTL, 0x03000000, |
137 | 0x03000000, 0x13000000); | |
1c1e45d1 HV |
138 | |
139 | /* initallize the PLL by toggling sleep bit */ | |
140 | v = cx18_av_read4(cx, CXADEC_HOST_REG1); | |
ced07371 AW |
141 | /* enable sleep mode - register appears to be read only... */ |
142 | cx18_av_write4_expect(cx, CXADEC_HOST_REG1, v | 1, v, 0xfffe); | |
1c1e45d1 | 143 | /* disable sleep mode */ |
ced07371 AW |
144 | cx18_av_write4_expect(cx, CXADEC_HOST_REG1, v & 0xfffe, |
145 | v & 0xfffe, 0xffff); | |
1c1e45d1 HV |
146 | |
147 | /* initialize DLLs */ | |
148 | v = cx18_av_read4(cx, CXADEC_DLL1_DIAG_CTRL) & 0xE1FFFEFF; | |
149 | /* disable FLD */ | |
150 | cx18_av_write4(cx, CXADEC_DLL1_DIAG_CTRL, v); | |
151 | /* enable FLD */ | |
152 | cx18_av_write4(cx, CXADEC_DLL1_DIAG_CTRL, v | 0x10000100); | |
153 | ||
154 | v = cx18_av_read4(cx, CXADEC_DLL2_DIAG_CTRL) & 0xE1FFFEFF; | |
155 | /* disable FLD */ | |
156 | cx18_av_write4(cx, CXADEC_DLL2_DIAG_CTRL, v); | |
157 | /* enable FLD */ | |
158 | cx18_av_write4(cx, CXADEC_DLL2_DIAG_CTRL, v | 0x06000100); | |
159 | ||
160 | /* set analog bias currents. Set Vreg to 1.20V. */ | |
161 | cx18_av_write4(cx, CXADEC_AFE_DIAG_CTRL1, 0x000A1802); | |
162 | ||
163 | v = cx18_av_read4(cx, CXADEC_AFE_DIAG_CTRL3) | 1; | |
164 | /* enable TUNE_FIL_RST */ | |
ced07371 | 165 | cx18_av_write4_expect(cx, CXADEC_AFE_DIAG_CTRL3, v, v, 0x03009F0F); |
1c1e45d1 | 166 | /* disable TUNE_FIL_RST */ |
ced07371 AW |
167 | cx18_av_write4_expect(cx, CXADEC_AFE_DIAG_CTRL3, |
168 | v & 0xFFFFFFFE, v & 0xFFFFFFFE, 0x03009F0F); | |
1c1e45d1 HV |
169 | |
170 | /* enable 656 output */ | |
171 | cx18_av_and_or4(cx, CXADEC_PIN_CTRL1, ~0, 0x040C00); | |
172 | ||
173 | /* video output drive strength */ | |
174 | cx18_av_and_or4(cx, CXADEC_PIN_CTRL2, ~0, 0x2); | |
175 | ||
176 | /* reset video */ | |
177 | cx18_av_write4(cx, CXADEC_SOFT_RST_CTRL, 0x8000); | |
178 | cx18_av_write4(cx, CXADEC_SOFT_RST_CTRL, 0); | |
179 | ||
f4672dff AW |
180 | /* |
181 | * Disable Video Auto-config of the Analog Front End and Video PLL. | |
182 | * | |
183 | * Since we only use BT.656 pixel mode, which works for both 525 and 625 | |
184 | * line systems, it's just easier for us to set registers | |
185 | * 0x102 (CXADEC_CHIP_CTRL), 0x104-0x106 (CXADEC_AFE_CTRL), | |
186 | * 0x108-0x109 (CXADEC_PLL_CTRL1), and 0x10c-0x10f (CXADEC_VID_PLL_FRAC) | |
187 | * ourselves, than to run around cleaning up after the auto-config. | |
188 | * | |
189 | * (Note: my CX23418 chip doesn't seem to let the ACFG_DIS bit | |
190 | * get set to 1, but OTOH, it doesn't seem to do AFE and VID PLL | |
191 | * autoconfig either.) | |
192 | * | |
193 | * As a default, also turn off Dual mode for ADC2 and set ADC2 to CH3. | |
194 | */ | |
195 | cx18_av_and_or4(cx, CXADEC_CHIP_CTRL, 0xFFFBFFFF, 0x00120000); | |
196 | ||
197 | /* Setup the Video and and Aux/Audio PLLs */ | |
7f3ea4de | 198 | cx18_av_init(cx); |
f4672dff | 199 | |
1c1e45d1 HV |
200 | /* set video to auto-detect */ |
201 | /* Clear bits 11-12 to enable slow locking mode. Set autodetect mode */ | |
202 | /* set the comb notch = 1 */ | |
203 | cx18_av_and_or4(cx, CXADEC_MODE_CTRL, 0xFFF7E7F0, 0x02040800); | |
204 | ||
205 | /* Enable wtw_en in CRUSH_CTRL (Set bit 22) */ | |
206 | /* Enable maj_sel in CRUSH_CTRL (Set bit 20) */ | |
207 | cx18_av_and_or4(cx, CXADEC_CRUSH_CTRL, ~0, 0x00500000); | |
208 | ||
209 | /* Set VGA_TRACK_RANGE to 0x20 */ | |
210 | cx18_av_and_or4(cx, CXADEC_DFE_CTRL2, 0xFFFF00FF, 0x00002000); | |
211 | ||
302df970 AW |
212 | /* |
213 | * Initial VBI setup | |
214 | * VIP-1.1, 10 bit mode, enable Raw, disable sliced, | |
812b1f9d AW |
215 | * don't clamp raw samples when codes are in use, 1 byte user D-words, |
216 | * IDID0 has line #, RP code V bit transition on VBLANK, data during | |
302df970 AW |
217 | * blanking intervals |
218 | */ | |
812b1f9d | 219 | cx18_av_write4(cx, CXADEC_OUT_CTRL1, 0x4013252e); |
1c1e45d1 HV |
220 | |
221 | /* Set the video input. | |
222 | The setting in MODE_CTRL gets lost when we do the above setup */ | |
223 | /* EncSetSignalStd(dwDevNum, pEnc->dwSigStd); */ | |
224 | /* EncSetVideoInput(dwDevNum, pEnc->VidIndSelection); */ | |
225 | ||
f4672dff AW |
226 | /* |
227 | * Analog Front End (AFE) | |
228 | * Default to luma on ch1/ADC1, chroma on ch2/ADC2, SIF on ch3/ADC2 | |
229 | * bypass_ch[1-3] use filter | |
230 | * droop_comp_ch[1-3] disable | |
231 | * clamp_en_ch[1-3] disable | |
232 | * aud_in_sel ADC2 | |
233 | * luma_in_sel ADC1 | |
234 | * chroma_in_sel ADC2 | |
235 | * clamp_sel_ch[2-3] midcode | |
236 | * clamp_sel_ch1 video decoder | |
237 | * vga_sel_ch3 audio decoder | |
238 | * vga_sel_ch[1-2] video decoder | |
239 | * half_bw_ch[1-3] disable | |
240 | * +12db_ch[1-3] disable | |
241 | */ | |
242 | cx18_av_and_or4(cx, CXADEC_AFE_CTRL, 0xFF000000, 0x00005D00); | |
1c1e45d1 HV |
243 | |
244 | /* if(dwEnable && dw3DCombAvailable) { */ | |
245 | /* CxDevWrReg(CXADEC_SRC_COMB_CFG, 0x7728021F); */ | |
246 | /* } else { */ | |
247 | /* CxDevWrReg(CXADEC_SRC_COMB_CFG, 0x6628021F); */ | |
248 | /* } */ | |
249 | cx18_av_write4(cx, CXADEC_SRC_COMB_CFG, 0x6628021F); | |
a75b9be1 HV |
250 | default_volume = cx18_av_read(cx, 0x8d4); |
251 | /* | |
252 | * Enforce the legacy volume scale mapping limits to avoid | |
253 | * -ERANGE errors when initializing the volume control | |
254 | */ | |
255 | if (default_volume > 228) { | |
256 | /* Bottom out at -96 dB, v4l2 vol range 0x2e00-0x2fff */ | |
257 | default_volume = 228; | |
258 | cx18_av_write(cx, 0x8d4, 228); | |
259 | } else if (default_volume < 20) { | |
260 | /* Top out at + 8 dB, v4l2 vol range 0xfe00-0xffff */ | |
261 | default_volume = 20; | |
262 | cx18_av_write(cx, 0x8d4, 20); | |
263 | } | |
264 | default_volume = (((228 - default_volume) >> 1) + 23) << 9; | |
265 | state->volume->cur.val = state->volume->default_value = default_volume; | |
266 | v4l2_ctrl_handler_setup(&state->hdl); | |
1c1e45d1 HV |
267 | } |
268 | ||
1a267046 AW |
269 | static int cx18_av_reset(struct v4l2_subdev *sd, u32 val) |
270 | { | |
f4672dff | 271 | cx18_av_initialize(sd); |
cc26b076 HV |
272 | return 0; |
273 | } | |
fa3e7036 | 274 | |
cc26b076 HV |
275 | static int cx18_av_load_fw(struct v4l2_subdev *sd) |
276 | { | |
277 | struct cx18_av_state *state = to_cx18_av_state(sd); | |
cc26b076 HV |
278 | |
279 | if (!state->is_initialized) { | |
280 | /* initialize on first use */ | |
281 | state->is_initialized = 1; | |
f4672dff | 282 | cx18_av_initialize(sd); |
1a267046 AW |
283 | } |
284 | return 0; | |
285 | } | |
1c1e45d1 | 286 | |
03b52c36 HV |
287 | void cx18_av_std_setup(struct cx18 *cx) |
288 | { | |
289 | struct cx18_av_state *state = &cx->av_state; | |
6246d4e1 | 290 | struct v4l2_subdev *sd = &state->sd; |
03b52c36 | 291 | v4l2_std_id std = state->std; |
86bc85b3 AW |
292 | |
293 | /* | |
294 | * Video ADC crystal clock to pixel clock SRC decimation ratio | |
295 | * 28.636360 MHz/13.5 Mpps * 256 = 0x21f.07b | |
296 | */ | |
297 | const int src_decimation = 0x21f; | |
298 | ||
03b52c36 | 299 | int hblank, hactive, burst, vblank, vactive, sc; |
86bc85b3 | 300 | int vblank656; |
03b52c36 HV |
301 | int luma_lpf, uv_lpf, comb; |
302 | u32 pll_int, pll_frac, pll_post; | |
303 | ||
304 | /* datasheet startup, step 8d */ | |
305 | if (std & ~V4L2_STD_NTSC) | |
306 | cx18_av_write(cx, 0x49f, 0x11); | |
307 | else | |
308 | cx18_av_write(cx, 0x49f, 0x14); | |
309 | ||
5ab74052 AW |
310 | /* |
311 | * Note: At the end of a field, there are 3 sets of half line duration | |
312 | * (double horizontal rate) pulses: | |
313 | * | |
314 | * 5 (625) or 6 (525) half-lines to blank for the vertical retrace | |
315 | * 5 (625) or 6 (525) vertical sync pulses of half line duration | |
316 | * 5 (625) or 6 (525) half-lines of equalization pulses | |
317 | */ | |
03b52c36 | 318 | if (std & V4L2_STD_625_50) { |
5ab74052 AW |
319 | /* |
320 | * The following relationships of half line counts should hold: | |
929a3ad1 | 321 | * 625 = vblank656 + vactive |
5ab74052 AW |
322 | * 10 = vblank656 - vblank = vsync pulses + equalization pulses |
323 | * | |
324 | * vblank656: half lines after line 625/mid-313 of blanked video | |
325 | * vblank: half lines, after line 5/317, of blanked video | |
929a3ad1 AW |
326 | * vactive: half lines of active video + |
327 | * 5 half lines after the end of active video | |
5ab74052 AW |
328 | * |
329 | * As far as I can tell: | |
330 | * vblank656 starts counting from the falling edge of the first | |
331 | * vsync pulse (start of line 1 or mid-313) | |
332 | * vblank starts counting from the after the 5 vsync pulses and | |
333 | * 5 or 4 equalization pulses (start of line 6 or 318) | |
334 | * | |
335 | * For 625 line systems the driver will extract VBI information | |
336 | * from lines 6-23 and lines 318-335 (but the slicer can only | |
337 | * handle 17 lines, not the 18 in the vblank region). | |
929a3ad1 AW |
338 | * In addition, we need vblank656 and vblank to be one whole |
339 | * line longer, to cover line 24 and 336, so the SAV/EAV RP | |
340 | * codes get generated such that the encoder can actually | |
341 | * extract line 23 & 335 (WSS). We'll lose 1 line in each field | |
342 | * at the top of the screen. | |
343 | * | |
344 | * It appears the 5 half lines that happen after active | |
345 | * video must be included in vactive (579 instead of 574), | |
346 | * otherwise the colors get badly displayed in various regions | |
347 | * of the screen. I guess the chroma comb filter gets confused | |
348 | * without them (at least when a PVR-350 is the PAL source). | |
5ab74052 | 349 | */ |
929a3ad1 AW |
350 | vblank656 = 48; /* lines 1 - 24 & 313 - 336 */ |
351 | vblank = 38; /* lines 6 - 24 & 318 - 336 */ | |
352 | vactive = 579; /* lines 24 - 313 & 337 - 626 */ | |
5ab74052 AW |
353 | |
354 | /* | |
355 | * For a 13.5 Mpps clock and 15,625 Hz line rate, a line is | |
356 | * is 864 pixels = 720 active + 144 blanking. ITU-R BT.601 | |
357 | * specifies 12 luma clock periods or ~ 0.9 * 13.5 Mpps after | |
358 | * the end of active video to start a horizontal line, so that | |
359 | * leaves 132 pixels of hblank to ignore. | |
360 | */ | |
03b52c36 HV |
361 | hblank = 132; |
362 | hactive = 720; | |
03b52c36 | 363 | |
86bc85b3 AW |
364 | /* |
365 | * Burst gate delay (for 625 line systems) | |
366 | * Hsync leading edge to color burst rise = 5.6 us | |
367 | * Color burst width = 2.25 us | |
368 | * Gate width = 4 pixel clocks | |
369 | * (5.6 us + 2.25/2 us) * 13.5 Mpps + 4/2 clocks = 92.79 clocks | |
370 | */ | |
5ab74052 | 371 | burst = 93; |
03b52c36 HV |
372 | luma_lpf = 2; |
373 | if (std & V4L2_STD_PAL) { | |
374 | uv_lpf = 1; | |
375 | comb = 0x20; | |
86bc85b3 AW |
376 | /* sc = 4433618.75 * src_decimation/28636360 * 2^13 */ |
377 | sc = 688700; | |
03b52c36 HV |
378 | } else if (std == V4L2_STD_PAL_Nc) { |
379 | uv_lpf = 1; | |
380 | comb = 0x20; | |
86bc85b3 AW |
381 | /* sc = 3582056.25 * src_decimation/28636360 * 2^13 */ |
382 | sc = 556422; | |
03b52c36 HV |
383 | } else { /* SECAM */ |
384 | uv_lpf = 0; | |
385 | comb = 0; | |
86bc85b3 AW |
386 | /* (fr + fb)/2 = (4406260 + 4250000)/2 = 4328130 */ |
387 | /* sc = 4328130 * src_decimation/28636360 * 2^13 */ | |
388 | sc = 672314; | |
03b52c36 HV |
389 | } |
390 | } else { | |
812b1f9d AW |
391 | /* |
392 | * The following relationships of half line counts should hold: | |
5ab74052 AW |
393 | * 525 = prevsync + vblank656 + vactive |
394 | * 12 = vblank656 - vblank = vsync pulses + equalization pulses | |
812b1f9d | 395 | * |
5ab74052 | 396 | * prevsync: 6 half-lines before the vsync pulses |
af7c58b1 AW |
397 | * vblank656: half lines, after line 3/mid-266, of blanked video |
398 | * vblank: half lines, after line 9/272, of blanked video | |
5ab74052 | 399 | * vactive: half lines of active video |
812b1f9d | 400 | * |
af7c58b1 | 401 | * As far as I can tell: |
812b1f9d | 402 | * vblank656 starts counting from the falling edge of the first |
af7c58b1 | 403 | * vsync pulse (start of line 4 or mid-266) |
812b1f9d | 404 | * vblank starts counting from the after the 6 vsync pulses and |
af7c58b1 | 405 | * 6 or 5 equalization pulses (start of line 10 or 272) |
812b1f9d AW |
406 | * |
407 | * For 525 line systems the driver will extract VBI information | |
af7c58b1 | 408 | * from lines 10-21 and lines 273-284. |
812b1f9d | 409 | */ |
af7c58b1 AW |
410 | vblank656 = 38; /* lines 4 - 22 & 266 - 284 */ |
411 | vblank = 26; /* lines 10 - 22 & 272 - 284 */ | |
412 | vactive = 481; /* lines 23 - 263 & 285 - 525 */ | |
812b1f9d | 413 | |
af7c58b1 AW |
414 | /* |
415 | * For a 13.5 Mpps clock and 15,734.26 Hz line rate, a line is | |
416 | * is 858 pixels = 720 active + 138 blanking. The Hsync leading | |
417 | * edge should happen 1.2 us * 13.5 Mpps ~= 16 pixels after the | |
418 | * end of active video, leaving 122 pixels of hblank to ignore | |
419 | * before active video starts. | |
420 | */ | |
03b52c36 HV |
421 | hactive = 720; |
422 | hblank = 122; | |
03b52c36 HV |
423 | luma_lpf = 1; |
424 | uv_lpf = 1; | |
03b52c36 | 425 | |
86bc85b3 AW |
426 | /* |
427 | * Burst gate delay (for 525 line systems) | |
428 | * Hsync leading edge to color burst rise = 5.3 us | |
429 | * Color burst width = 2.5 us | |
430 | * Gate width = 4 pixel clocks | |
431 | * (5.3 us + 2.5/2 us) * 13.5 Mpps + 4/2 clocks = 90.425 clocks | |
432 | */ | |
03b52c36 | 433 | if (std == V4L2_STD_PAL_60) { |
86bc85b3 | 434 | burst = 90; |
03b52c36 HV |
435 | luma_lpf = 2; |
436 | comb = 0x20; | |
86bc85b3 AW |
437 | /* sc = 4433618.75 * src_decimation/28636360 * 2^13 */ |
438 | sc = 688700; | |
03b52c36 | 439 | } else if (std == V4L2_STD_PAL_M) { |
86bc85b3 AW |
440 | /* The 97 needs to be verified against PAL-M timings */ |
441 | burst = 97; | |
03b52c36 | 442 | comb = 0x20; |
86bc85b3 AW |
443 | /* sc = 3575611.49 * src_decimation/28636360 * 2^13 */ |
444 | sc = 555421; | |
03b52c36 | 445 | } else { |
86bc85b3 | 446 | burst = 90; |
03b52c36 | 447 | comb = 0x66; |
86bc85b3 AW |
448 | /* sc = 3579545.45.. * src_decimation/28636360 * 2^13 */ |
449 | sc = 556032; | |
03b52c36 HV |
450 | } |
451 | } | |
452 | ||
453 | /* DEBUG: Displays configured PLL frequency */ | |
454 | pll_int = cx18_av_read(cx, 0x108); | |
455 | pll_frac = cx18_av_read4(cx, 0x10c) & 0x1ffffff; | |
456 | pll_post = cx18_av_read(cx, 0x109); | |
6246d4e1 AW |
457 | CX18_DEBUG_INFO_DEV(sd, "PLL regs = int: %u, frac: %u, post: %u\n", |
458 | pll_int, pll_frac, pll_post); | |
03b52c36 HV |
459 | |
460 | if (pll_post) { | |
86bc85b3 | 461 | int fsc, pll; |
9ad4c655 | 462 | u64 tmp; |
03b52c36 | 463 | |
55d81aa5 | 464 | pll = (28636360L * ((((u64)pll_int) << 25) + pll_frac)) >> 25; |
03b52c36 | 465 | pll /= pll_post; |
86bc85b3 | 466 | CX18_DEBUG_INFO_DEV(sd, "Video PLL = %d.%06d MHz\n", |
6246d4e1 | 467 | pll / 1000000, pll % 1000000); |
86bc85b3 | 468 | CX18_DEBUG_INFO_DEV(sd, "Pixel rate = %d.%06d Mpixel/sec\n", |
6246d4e1 | 469 | pll / 8000000, (pll / 8) % 1000000); |
03b52c36 | 470 | |
6beb1388 MCC |
471 | CX18_DEBUG_INFO_DEV(sd, "ADC XTAL/pixel clock decimation ratio = %d.%03d\n", |
472 | src_decimation / 256, | |
86bc85b3 | 473 | ((src_decimation % 256) * 1000) / 256); |
03b52c36 | 474 | |
9ad4c655 AW |
475 | tmp = 28636360 * (u64) sc; |
476 | do_div(tmp, src_decimation); | |
477 | fsc = tmp >> 13; | |
6246d4e1 | 478 | CX18_DEBUG_INFO_DEV(sd, |
6beb1388 MCC |
479 | "Chroma sub-carrier initial freq = %d.%06d MHz\n", |
480 | fsc / 1000000, fsc % 1000000); | |
6246d4e1 | 481 | |
6beb1388 MCC |
482 | CX18_DEBUG_INFO_DEV(sd, |
483 | "hblank %i, hactive %i, vblank %i, vactive %i, vblank656 %i, src_dec %i, burst 0x%02x, luma_lpf %i, uv_lpf %i, comb 0x%02x, sc 0x%06x\n", | |
6246d4e1 AW |
484 | hblank, hactive, vblank, vactive, vblank656, |
485 | src_decimation, burst, luma_lpf, uv_lpf, | |
486 | comb, sc); | |
03b52c36 HV |
487 | } |
488 | ||
489 | /* Sets horizontal blanking delay and active lines */ | |
490 | cx18_av_write(cx, 0x470, hblank); | |
85273c38 JP |
491 | cx18_av_write(cx, 0x471, |
492 | (((hblank >> 8) & 0x3) | (hactive << 4)) & 0xff); | |
03b52c36 HV |
493 | cx18_av_write(cx, 0x472, hactive >> 4); |
494 | ||
495 | /* Sets burst gate delay */ | |
496 | cx18_av_write(cx, 0x473, burst); | |
497 | ||
498 | /* Sets vertical blanking delay and active duration */ | |
499 | cx18_av_write(cx, 0x474, vblank); | |
85273c38 JP |
500 | cx18_av_write(cx, 0x475, |
501 | (((vblank >> 8) & 0x3) | (vactive << 4)) & 0xff); | |
03b52c36 HV |
502 | cx18_av_write(cx, 0x476, vactive >> 4); |
503 | cx18_av_write(cx, 0x477, vblank656); | |
504 | ||
505 | /* Sets src decimation rate */ | |
85273c38 JP |
506 | cx18_av_write(cx, 0x478, src_decimation & 0xff); |
507 | cx18_av_write(cx, 0x479, (src_decimation >> 8) & 0xff); | |
03b52c36 HV |
508 | |
509 | /* Sets Luma and UV Low pass filters */ | |
510 | cx18_av_write(cx, 0x47a, luma_lpf << 6 | ((uv_lpf << 4) & 0x30)); | |
511 | ||
512 | /* Enables comb filters */ | |
513 | cx18_av_write(cx, 0x47b, comb); | |
514 | ||
515 | /* Sets SC Step*/ | |
516 | cx18_av_write(cx, 0x47c, sc); | |
85273c38 JP |
517 | cx18_av_write(cx, 0x47d, (sc >> 8) & 0xff); |
518 | cx18_av_write(cx, 0x47e, (sc >> 16) & 0xff); | |
03b52c36 | 519 | |
03b52c36 | 520 | if (std & V4L2_STD_625_50) { |
812b1f9d AW |
521 | state->slicer_line_delay = 1; |
522 | state->slicer_line_offset = (6 + state->slicer_line_delay - 2); | |
03b52c36 | 523 | } else { |
812b1f9d AW |
524 | state->slicer_line_delay = 0; |
525 | state->slicer_line_offset = (10 + state->slicer_line_delay - 2); | |
03b52c36 | 526 | } |
812b1f9d | 527 | cx18_av_write(cx, 0x47f, state->slicer_line_delay); |
03b52c36 HV |
528 | } |
529 | ||
1c1e45d1 HV |
530 | static void input_change(struct cx18 *cx) |
531 | { | |
532 | struct cx18_av_state *state = &cx->av_state; | |
533 | v4l2_std_id std = state->std; | |
ced07371 | 534 | u8 v; |
1c1e45d1 HV |
535 | |
536 | /* Follow step 8c and 8d of section 3.16 in the cx18_av datasheet */ | |
c1738904 HV |
537 | cx18_av_write(cx, 0x49f, (std & V4L2_STD_NTSC) ? 0x14 : 0x11); |
538 | cx18_av_and_or(cx, 0x401, ~0x60, 0); | |
539 | cx18_av_and_or(cx, 0x401, ~0x60, 0x60); | |
1c1e45d1 HV |
540 | |
541 | if (std & V4L2_STD_525_60) { | |
542 | if (std == V4L2_STD_NTSC_M_JP) { | |
543 | /* Japan uses EIAJ audio standard */ | |
ced07371 AW |
544 | cx18_av_write_expect(cx, 0x808, 0xf7, 0xf7, 0xff); |
545 | cx18_av_write_expect(cx, 0x80b, 0x02, 0x02, 0x3f); | |
1c1e45d1 HV |
546 | } else if (std == V4L2_STD_NTSC_M_KR) { |
547 | /* South Korea uses A2 audio standard */ | |
ced07371 AW |
548 | cx18_av_write_expect(cx, 0x808, 0xf8, 0xf8, 0xff); |
549 | cx18_av_write_expect(cx, 0x80b, 0x03, 0x03, 0x3f); | |
1c1e45d1 HV |
550 | } else { |
551 | /* Others use the BTSC audio standard */ | |
ced07371 AW |
552 | cx18_av_write_expect(cx, 0x808, 0xf6, 0xf6, 0xff); |
553 | cx18_av_write_expect(cx, 0x80b, 0x01, 0x01, 0x3f); | |
1c1e45d1 | 554 | } |
1c1e45d1 HV |
555 | } else if (std & V4L2_STD_PAL) { |
556 | /* Follow tuner change procedure for PAL */ | |
ced07371 AW |
557 | cx18_av_write_expect(cx, 0x808, 0xff, 0xff, 0xff); |
558 | cx18_av_write_expect(cx, 0x80b, 0x03, 0x03, 0x3f); | |
1c1e45d1 HV |
559 | } else if (std & V4L2_STD_SECAM) { |
560 | /* Select autodetect for SECAM */ | |
ced07371 AW |
561 | cx18_av_write_expect(cx, 0x808, 0xff, 0xff, 0xff); |
562 | cx18_av_write_expect(cx, 0x80b, 0x03, 0x03, 0x3f); | |
1c1e45d1 HV |
563 | } |
564 | ||
ced07371 AW |
565 | v = cx18_av_read(cx, 0x803); |
566 | if (v & 0x10) { | |
1c1e45d1 | 567 | /* restart audio decoder microcontroller */ |
ced07371 AW |
568 | v &= ~0x10; |
569 | cx18_av_write_expect(cx, 0x803, v, v, 0x1f); | |
570 | v |= 0x10; | |
571 | cx18_av_write_expect(cx, 0x803, v, v, 0x1f); | |
1c1e45d1 HV |
572 | } |
573 | } | |
574 | ||
1a267046 | 575 | static int cx18_av_s_frequency(struct v4l2_subdev *sd, |
b530a447 | 576 | const struct v4l2_frequency *freq) |
1a267046 AW |
577 | { |
578 | struct cx18 *cx = v4l2_get_subdevdata(sd); | |
579 | input_change(cx); | |
580 | return 0; | |
581 | } | |
582 | ||
1c1e45d1 HV |
583 | static int set_input(struct cx18 *cx, enum cx18_av_video_input vid_input, |
584 | enum cx18_av_audio_input aud_input) | |
585 | { | |
586 | struct cx18_av_state *state = &cx->av_state; | |
6246d4e1 | 587 | struct v4l2_subdev *sd = &state->sd; |
f4672dff AW |
588 | |
589 | enum analog_signal_type { | |
590 | NONE, CVBS, Y, C, SIF, Pb, Pr | |
591 | } ch[3] = {NONE, NONE, NONE}; | |
592 | ||
593 | u8 afe_mux_cfg; | |
594 | u8 adc2_cfg; | |
d9a325a8 | 595 | u8 input_mode; |
f4672dff AW |
596 | u32 afe_cfg; |
597 | int i; | |
1c1e45d1 | 598 | |
6246d4e1 AW |
599 | CX18_DEBUG_INFO_DEV(sd, "decoder set video input %d, audio input %d\n", |
600 | vid_input, aud_input); | |
1c1e45d1 | 601 | |
f4672dff AW |
602 | if (vid_input >= CX18_AV_COMPOSITE1 && |
603 | vid_input <= CX18_AV_COMPOSITE8) { | |
604 | afe_mux_cfg = 0xf0 + (vid_input - CX18_AV_COMPOSITE1); | |
605 | ch[0] = CVBS; | |
d9a325a8 AW |
606 | input_mode = 0x0; |
607 | } else if (vid_input >= CX18_AV_COMPONENT_LUMA1) { | |
608 | int luma = vid_input & 0xf000; | |
609 | int r_chroma = vid_input & 0xf0000; | |
610 | int b_chroma = vid_input & 0xf00000; | |
611 | ||
612 | if ((vid_input & ~0xfff000) || | |
613 | luma < CX18_AV_COMPONENT_LUMA1 || | |
614 | luma > CX18_AV_COMPONENT_LUMA8 || | |
615 | r_chroma < CX18_AV_COMPONENT_R_CHROMA4 || | |
616 | r_chroma > CX18_AV_COMPONENT_R_CHROMA6 || | |
617 | b_chroma < CX18_AV_COMPONENT_B_CHROMA7 || | |
618 | b_chroma > CX18_AV_COMPONENT_B_CHROMA8) { | |
619 | CX18_ERR_DEV(sd, "0x%06x is not a valid video input!\n", | |
620 | vid_input); | |
621 | return -EINVAL; | |
622 | } | |
623 | afe_mux_cfg = (luma - CX18_AV_COMPONENT_LUMA1) >> 12; | |
624 | ch[0] = Y; | |
625 | afe_mux_cfg |= (r_chroma - CX18_AV_COMPONENT_R_CHROMA4) >> 12; | |
626 | ch[1] = Pr; | |
627 | afe_mux_cfg |= (b_chroma - CX18_AV_COMPONENT_B_CHROMA7) >> 14; | |
628 | ch[2] = Pb; | |
629 | input_mode = 0x6; | |
1c1e45d1 HV |
630 | } else { |
631 | int luma = vid_input & 0xf0; | |
632 | int chroma = vid_input & 0xf00; | |
633 | ||
634 | if ((vid_input & ~0xff0) || | |
635 | luma < CX18_AV_SVIDEO_LUMA1 || | |
45270a15 | 636 | luma > CX18_AV_SVIDEO_LUMA8 || |
1c1e45d1 HV |
637 | chroma < CX18_AV_SVIDEO_CHROMA4 || |
638 | chroma > CX18_AV_SVIDEO_CHROMA8) { | |
d9a325a8 | 639 | CX18_ERR_DEV(sd, "0x%06x is not a valid video input!\n", |
6246d4e1 | 640 | vid_input); |
1c1e45d1 HV |
641 | return -EINVAL; |
642 | } | |
f4672dff AW |
643 | afe_mux_cfg = 0xf0 + ((luma - CX18_AV_SVIDEO_LUMA1) >> 4); |
644 | ch[0] = Y; | |
1c1e45d1 | 645 | if (chroma >= CX18_AV_SVIDEO_CHROMA7) { |
f4672dff AW |
646 | afe_mux_cfg &= 0x3f; |
647 | afe_mux_cfg |= (chroma - CX18_AV_SVIDEO_CHROMA7) >> 2; | |
648 | ch[2] = C; | |
1c1e45d1 | 649 | } else { |
f4672dff AW |
650 | afe_mux_cfg &= 0xcf; |
651 | afe_mux_cfg |= (chroma - CX18_AV_SVIDEO_CHROMA4) >> 4; | |
652 | ch[1] = C; | |
1c1e45d1 | 653 | } |
d9a325a8 | 654 | input_mode = 0x2; |
1c1e45d1 HV |
655 | } |
656 | ||
657 | switch (aud_input) { | |
81cb727d HV |
658 | case CX18_AV_AUDIO_SERIAL1: |
659 | case CX18_AV_AUDIO_SERIAL2: | |
1c1e45d1 HV |
660 | /* do nothing, use serial audio input */ |
661 | break; | |
f4672dff AW |
662 | case CX18_AV_AUDIO4: |
663 | afe_mux_cfg &= ~0x30; | |
664 | ch[1] = SIF; | |
665 | break; | |
666 | case CX18_AV_AUDIO5: | |
667 | afe_mux_cfg = (afe_mux_cfg & ~0x30) | 0x10; | |
668 | ch[1] = SIF; | |
669 | break; | |
670 | case CX18_AV_AUDIO6: | |
671 | afe_mux_cfg = (afe_mux_cfg & ~0x30) | 0x20; | |
672 | ch[1] = SIF; | |
673 | break; | |
674 | case CX18_AV_AUDIO7: | |
675 | afe_mux_cfg &= ~0xc0; | |
676 | ch[2] = SIF; | |
677 | break; | |
678 | case CX18_AV_AUDIO8: | |
679 | afe_mux_cfg = (afe_mux_cfg & ~0xc0) | 0x40; | |
680 | ch[2] = SIF; | |
681 | break; | |
1c1e45d1 HV |
682 | |
683 | default: | |
6246d4e1 AW |
684 | CX18_ERR_DEV(sd, "0x%04x is not a valid audio input!\n", |
685 | aud_input); | |
1c1e45d1 HV |
686 | return -EINVAL; |
687 | } | |
688 | ||
f4672dff AW |
689 | /* Set up analog front end multiplexers */ |
690 | cx18_av_write_expect(cx, 0x103, afe_mux_cfg, afe_mux_cfg, 0xf7); | |
d9a325a8 AW |
691 | /* Set INPUT_MODE to Composite, S-Video, or Component */ |
692 | cx18_av_and_or(cx, 0x401, ~0x6, input_mode); | |
ced07371 | 693 | |
1c1e45d1 | 694 | /* Set CH_SEL_ADC2 to 1 if input comes from CH3 */ |
f4672dff AW |
695 | adc2_cfg = cx18_av_read(cx, 0x102); |
696 | if (ch[2] == NONE) | |
697 | adc2_cfg &= ~0x2; /* No sig on CH3, set ADC2 to CH2 for input */ | |
ced07371 | 698 | else |
f4672dff AW |
699 | adc2_cfg |= 0x2; /* Signal on CH3, set ADC2 to CH3 for input */ |
700 | ||
1c1e45d1 | 701 | /* Set DUAL_MODE_ADC2 to 1 if input comes from both CH2 and CH3 */ |
f4672dff AW |
702 | if (ch[1] != NONE && ch[2] != NONE) |
703 | adc2_cfg |= 0x4; /* Set dual mode */ | |
1c1e45d1 | 704 | else |
f4672dff AW |
705 | adc2_cfg &= ~0x4; /* Clear dual mode */ |
706 | cx18_av_write_expect(cx, 0x102, adc2_cfg, adc2_cfg, 0x17); | |
707 | ||
708 | /* Configure the analog front end */ | |
709 | afe_cfg = cx18_av_read4(cx, CXADEC_AFE_CTRL); | |
710 | afe_cfg &= 0xff000000; | |
711 | afe_cfg |= 0x00005000; /* CHROMA_IN, AUD_IN: ADC2; LUMA_IN: ADC1 */ | |
712 | if (ch[1] != NONE && ch[2] != NONE) | |
713 | afe_cfg |= 0x00000030; /* half_bw_ch[2-3] since in dual mode */ | |
714 | ||
715 | for (i = 0; i < 3; i++) { | |
716 | switch (ch[i]) { | |
717 | default: | |
718 | case NONE: | |
719 | /* CLAMP_SEL = Fixed to midcode clamp level */ | |
720 | afe_cfg |= (0x00000200 << i); | |
721 | break; | |
722 | case CVBS: | |
723 | case Y: | |
724 | if (i > 0) | |
725 | afe_cfg |= 0x00002000; /* LUMA_IN_SEL: ADC2 */ | |
726 | break; | |
727 | case C: | |
728 | case Pb: | |
729 | case Pr: | |
730 | /* CLAMP_SEL = Fixed to midcode clamp level */ | |
731 | afe_cfg |= (0x00000200 << i); | |
732 | if (i == 0 && ch[i] == C) | |
733 | afe_cfg &= ~0x00001000; /* CHROMA_IN_SEL ADC1 */ | |
734 | break; | |
735 | case SIF: | |
736 | /* | |
737 | * VGA_GAIN_SEL = Audio Decoder | |
738 | * CLAMP_SEL = Fixed to midcode clamp level | |
739 | */ | |
740 | afe_cfg |= (0x00000240 << i); | |
741 | if (i == 0) | |
742 | afe_cfg &= ~0x00004000; /* AUD_IN_SEL ADC1 */ | |
743 | break; | |
744 | } | |
745 | } | |
ced07371 | 746 | |
f4672dff | 747 | cx18_av_write4(cx, CXADEC_AFE_CTRL, afe_cfg); |
1c1e45d1 HV |
748 | |
749 | state->vid_input = vid_input; | |
750 | state->aud_input = aud_input; | |
751 | cx18_av_audio_set_path(cx); | |
752 | input_change(cx); | |
753 | return 0; | |
754 | } | |
755 | ||
1a267046 | 756 | static int cx18_av_s_video_routing(struct v4l2_subdev *sd, |
5325b427 | 757 | u32 input, u32 output, u32 config) |
1a267046 AW |
758 | { |
759 | struct cx18_av_state *state = to_cx18_av_state(sd); | |
760 | struct cx18 *cx = v4l2_get_subdevdata(sd); | |
5325b427 | 761 | return set_input(cx, input, state->aud_input); |
1a267046 | 762 | } |
1c1e45d1 | 763 | |
1a267046 | 764 | static int cx18_av_s_audio_routing(struct v4l2_subdev *sd, |
5325b427 | 765 | u32 input, u32 output, u32 config) |
1c1e45d1 | 766 | { |
1a267046 AW |
767 | struct cx18_av_state *state = to_cx18_av_state(sd); |
768 | struct cx18 *cx = v4l2_get_subdevdata(sd); | |
5325b427 | 769 | return set_input(cx, state->vid_input, input); |
1a267046 AW |
770 | } |
771 | ||
772 | static int cx18_av_g_tuner(struct v4l2_subdev *sd, struct v4l2_tuner *vt) | |
773 | { | |
774 | struct cx18_av_state *state = to_cx18_av_state(sd); | |
775 | struct cx18 *cx = v4l2_get_subdevdata(sd); | |
776 | u8 vpres; | |
777 | u8 mode; | |
778 | int val = 0; | |
779 | ||
780 | if (state->radio) | |
781 | return 0; | |
782 | ||
783 | vpres = cx18_av_read(cx, 0x40e) & 0x20; | |
784 | vt->signal = vpres ? 0xffff : 0x0; | |
785 | ||
786 | vt->capability |= | |
787 | V4L2_TUNER_CAP_STEREO | V4L2_TUNER_CAP_LANG1 | | |
788 | V4L2_TUNER_CAP_LANG2 | V4L2_TUNER_CAP_SAP; | |
789 | ||
790 | mode = cx18_av_read(cx, 0x804); | |
791 | ||
792 | /* get rxsubchans and audmode */ | |
793 | if ((mode & 0xf) == 1) | |
794 | val |= V4L2_TUNER_SUB_STEREO; | |
795 | else | |
796 | val |= V4L2_TUNER_SUB_MONO; | |
797 | ||
798 | if (mode == 2 || mode == 4) | |
799 | val = V4L2_TUNER_SUB_LANG1 | V4L2_TUNER_SUB_LANG2; | |
800 | ||
801 | if (mode & 0x10) | |
802 | val |= V4L2_TUNER_SUB_SAP; | |
803 | ||
804 | vt->rxsubchans = val; | |
805 | vt->audmode = state->audmode; | |
806 | return 0; | |
807 | } | |
808 | ||
2f73c7c5 | 809 | static int cx18_av_s_tuner(struct v4l2_subdev *sd, const struct v4l2_tuner *vt) |
1a267046 AW |
810 | { |
811 | struct cx18_av_state *state = to_cx18_av_state(sd); | |
812 | struct cx18 *cx = v4l2_get_subdevdata(sd); | |
813 | u8 v; | |
814 | ||
815 | if (state->radio) | |
816 | return 0; | |
817 | ||
818 | v = cx18_av_read(cx, 0x809); | |
819 | v &= ~0xf; | |
820 | ||
821 | switch (vt->audmode) { | |
822 | case V4L2_TUNER_MODE_MONO: | |
823 | /* mono -> mono | |
824 | stereo -> mono | |
825 | bilingual -> lang1 */ | |
826 | break; | |
827 | case V4L2_TUNER_MODE_STEREO: | |
828 | case V4L2_TUNER_MODE_LANG1: | |
829 | /* mono -> mono | |
830 | stereo -> stereo | |
831 | bilingual -> lang1 */ | |
832 | v |= 0x4; | |
833 | break; | |
834 | case V4L2_TUNER_MODE_LANG1_LANG2: | |
835 | /* mono -> mono | |
836 | stereo -> stereo | |
837 | bilingual -> lang1/lang2 */ | |
838 | v |= 0x7; | |
839 | break; | |
840 | case V4L2_TUNER_MODE_LANG2: | |
841 | /* mono -> mono | |
842 | stereo -> stereo | |
843 | bilingual -> lang2 */ | |
844 | v |= 0x1; | |
845 | break; | |
846 | default: | |
847 | return -EINVAL; | |
848 | } | |
849 | cx18_av_write_expect(cx, 0x809, v, v, 0xff); | |
850 | state->audmode = vt->audmode; | |
851 | return 0; | |
852 | } | |
853 | ||
854 | static int cx18_av_s_std(struct v4l2_subdev *sd, v4l2_std_id norm) | |
855 | { | |
856 | struct cx18_av_state *state = to_cx18_av_state(sd); | |
857 | struct cx18 *cx = v4l2_get_subdevdata(sd); | |
858 | ||
1c1e45d1 HV |
859 | u8 fmt = 0; /* zero is autodetect */ |
860 | u8 pal_m = 0; | |
861 | ||
1a267046 AW |
862 | if (state->radio == 0 && state->std == norm) |
863 | return 0; | |
864 | ||
865 | state->radio = 0; | |
866 | state->std = norm; | |
867 | ||
1c1e45d1 HV |
868 | /* First tests should be against specific std */ |
869 | if (state->std == V4L2_STD_NTSC_M_JP) { | |
870 | fmt = 0x2; | |
871 | } else if (state->std == V4L2_STD_NTSC_443) { | |
872 | fmt = 0x3; | |
873 | } else if (state->std == V4L2_STD_PAL_M) { | |
874 | pal_m = 1; | |
875 | fmt = 0x5; | |
876 | } else if (state->std == V4L2_STD_PAL_N) { | |
877 | fmt = 0x6; | |
878 | } else if (state->std == V4L2_STD_PAL_Nc) { | |
879 | fmt = 0x7; | |
880 | } else if (state->std == V4L2_STD_PAL_60) { | |
881 | fmt = 0x8; | |
882 | } else { | |
883 | /* Then, test against generic ones */ | |
884 | if (state->std & V4L2_STD_NTSC) | |
885 | fmt = 0x1; | |
886 | else if (state->std & V4L2_STD_PAL) | |
887 | fmt = 0x4; | |
888 | else if (state->std & V4L2_STD_SECAM) | |
889 | fmt = 0xc; | |
890 | } | |
891 | ||
6246d4e1 | 892 | CX18_DEBUG_INFO_DEV(sd, "changing video std to fmt %i\n", fmt); |
1c1e45d1 HV |
893 | |
894 | /* Follow step 9 of section 3.16 in the cx18_av datasheet. | |
895 | Without this PAL may display a vertical ghosting effect. | |
896 | This happens for example with the Yuan MPC622. */ | |
897 | if (fmt >= 4 && fmt < 8) { | |
898 | /* Set format to NTSC-M */ | |
c1738904 | 899 | cx18_av_and_or(cx, 0x400, ~0xf, 1); |
1c1e45d1 HV |
900 | /* Turn off LCOMB */ |
901 | cx18_av_and_or(cx, 0x47b, ~6, 0); | |
902 | } | |
c1738904 HV |
903 | cx18_av_and_or(cx, 0x400, ~0x2f, fmt | 0x20); |
904 | cx18_av_and_or(cx, 0x403, ~0x3, pal_m); | |
03b52c36 | 905 | cx18_av_std_setup(cx); |
1c1e45d1 HV |
906 | input_change(cx); |
907 | return 0; | |
908 | } | |
909 | ||
1a267046 AW |
910 | static int cx18_av_s_radio(struct v4l2_subdev *sd) |
911 | { | |
912 | struct cx18_av_state *state = to_cx18_av_state(sd); | |
913 | state->radio = 1; | |
914 | return 0; | |
915 | } | |
1c1e45d1 | 916 | |
a75b9be1 | 917 | static int cx18_av_s_ctrl(struct v4l2_ctrl *ctrl) |
1c1e45d1 | 918 | { |
a75b9be1 | 919 | struct v4l2_subdev *sd = to_sd(ctrl); |
1a267046 AW |
920 | struct cx18 *cx = v4l2_get_subdevdata(sd); |
921 | ||
1c1e45d1 HV |
922 | switch (ctrl->id) { |
923 | case V4L2_CID_BRIGHTNESS: | |
a75b9be1 | 924 | cx18_av_write(cx, 0x414, ctrl->val - 128); |
1c1e45d1 HV |
925 | break; |
926 | ||
927 | case V4L2_CID_CONTRAST: | |
a75b9be1 | 928 | cx18_av_write(cx, 0x415, ctrl->val << 1); |
1c1e45d1 HV |
929 | break; |
930 | ||
931 | case V4L2_CID_SATURATION: | |
a75b9be1 HV |
932 | cx18_av_write(cx, 0x420, ctrl->val << 1); |
933 | cx18_av_write(cx, 0x421, ctrl->val << 1); | |
1c1e45d1 HV |
934 | break; |
935 | ||
936 | case V4L2_CID_HUE: | |
a75b9be1 | 937 | cx18_av_write(cx, 0x422, ctrl->val); |
1c1e45d1 HV |
938 | break; |
939 | ||
1c1e45d1 HV |
940 | default: |
941 | return -EINVAL; | |
942 | } | |
1c1e45d1 HV |
943 | return 0; |
944 | } | |
945 | ||
6e80c473 HV |
946 | static int cx18_av_set_fmt(struct v4l2_subdev *sd, |
947 | struct v4l2_subdev_pad_config *cfg, | |
948 | struct v4l2_subdev_format *format) | |
1c1e45d1 | 949 | { |
6e80c473 | 950 | struct v4l2_mbus_framefmt *fmt = &format->format; |
1a267046 AW |
951 | struct cx18_av_state *state = to_cx18_av_state(sd); |
952 | struct cx18 *cx = v4l2_get_subdevdata(sd); | |
1c1e45d1 HV |
953 | int HSC, VSC, Vsrc, Hsrc, filter, Vlines; |
954 | int is_50Hz = !(state->std & V4L2_STD_525_60); | |
955 | ||
6e80c473 | 956 | if (format->pad || fmt->code != MEDIA_BUS_FMT_FIXED) |
e17ad1de | 957 | return -EINVAL; |
1c1e45d1 | 958 | |
e17ad1de HV |
959 | fmt->field = V4L2_FIELD_INTERLACED; |
960 | fmt->colorspace = V4L2_COLORSPACE_SMPTE170M; | |
1c1e45d1 | 961 | |
e17ad1de HV |
962 | Vsrc = (cx18_av_read(cx, 0x476) & 0x3f) << 4; |
963 | Vsrc |= (cx18_av_read(cx, 0x475) & 0xf0) >> 4; | |
1c1e45d1 | 964 | |
e17ad1de HV |
965 | Hsrc = (cx18_av_read(cx, 0x472) & 0x3f) << 4; |
966 | Hsrc |= (cx18_av_read(cx, 0x471) & 0xf0) >> 4; | |
1c1e45d1 | 967 | |
e17ad1de HV |
968 | /* |
969 | * This adjustment reflects the excess of vactive, set in | |
970 | * cx18_av_std_setup(), above standard values: | |
971 | * | |
972 | * 480 + 1 for 60 Hz systems | |
973 | * 576 + 3 for 50 Hz systems | |
974 | */ | |
975 | Vlines = fmt->height + (is_50Hz ? 3 : 1); | |
1c1e45d1 | 976 | |
e17ad1de HV |
977 | /* |
978 | * Invalid height and width scaling requests are: | |
979 | * 1. width less than 1/16 of the source width | |
980 | * 2. width greater than the source width | |
981 | * 3. height less than 1/8 of the source height | |
982 | * 4. height greater than the source height | |
983 | */ | |
984 | if ((fmt->width * 16 < Hsrc) || (Hsrc < fmt->width) || | |
985 | (Vlines * 8 < Vsrc) || (Vsrc < Vlines)) { | |
986 | CX18_ERR_DEV(sd, "%dx%d is not a valid size!\n", | |
987 | fmt->width, fmt->height); | |
988 | return -ERANGE; | |
989 | } | |
1c1e45d1 | 990 | |
6e80c473 HV |
991 | if (format->which == V4L2_SUBDEV_FORMAT_TRY) |
992 | return 0; | |
993 | ||
e17ad1de HV |
994 | HSC = (Hsrc * (1 << 20)) / fmt->width - (1 << 20); |
995 | VSC = (1 << 16) - (Vsrc * (1 << 9) / Vlines - (1 << 9)); | |
996 | VSC &= 0x1fff; | |
1c1e45d1 | 997 | |
e17ad1de HV |
998 | if (fmt->width >= 385) |
999 | filter = 0; | |
1000 | else if (fmt->width > 192) | |
1001 | filter = 1; | |
1002 | else if (fmt->width > 96) | |
1003 | filter = 2; | |
1004 | else | |
1005 | filter = 3; | |
1006 | ||
1007 | CX18_DEBUG_INFO_DEV(sd, | |
1008 | "decoder set size %dx%d -> scale %ux%u\n", | |
1009 | fmt->width, fmt->height, HSC, VSC); | |
1010 | ||
1011 | /* HSCALE=HSC */ | |
1012 | cx18_av_write(cx, 0x418, HSC & 0xff); | |
1013 | cx18_av_write(cx, 0x419, (HSC >> 8) & 0xff); | |
1014 | cx18_av_write(cx, 0x41a, HSC >> 16); | |
1015 | /* VSCALE=VSC */ | |
1016 | cx18_av_write(cx, 0x41c, VSC & 0xff); | |
1017 | cx18_av_write(cx, 0x41d, VSC >> 8); | |
1018 | /* VS_INTRLACE=1 VFILT=filter */ | |
1019 | cx18_av_write(cx, 0x41e, 0x8 | filter); | |
1020 | return 0; | |
1021 | } | |
1022 | ||
1a267046 | 1023 | static int cx18_av_s_stream(struct v4l2_subdev *sd, int enable) |
e474200d | 1024 | { |
1a267046 | 1025 | struct cx18 *cx = v4l2_get_subdevdata(sd); |
1c1e45d1 | 1026 | |
6246d4e1 | 1027 | CX18_DEBUG_INFO_DEV(sd, "%s output\n", enable ? "enable" : "disable"); |
1a267046 | 1028 | if (enable) { |
1c1e45d1 HV |
1029 | cx18_av_write(cx, 0x115, 0x8c); |
1030 | cx18_av_write(cx, 0x116, 0x07); | |
1a267046 | 1031 | } else { |
1c1e45d1 HV |
1032 | cx18_av_write(cx, 0x115, 0x00); |
1033 | cx18_av_write(cx, 0x116, 0x00); | |
1c1e45d1 | 1034 | } |
1c1e45d1 HV |
1035 | return 0; |
1036 | } | |
1037 | ||
1c1e45d1 HV |
1038 | static void log_video_status(struct cx18 *cx) |
1039 | { | |
1040 | static const char *const fmt_strs[] = { | |
1041 | "0x0", | |
1042 | "NTSC-M", "NTSC-J", "NTSC-4.43", | |
1043 | "PAL-BDGHI", "PAL-M", "PAL-N", "PAL-Nc", "PAL-60", | |
1044 | "0x9", "0xA", "0xB", | |
1045 | "SECAM", | |
1046 | "0xD", "0xE", "0xF" | |
1047 | }; | |
1048 | ||
1049 | struct cx18_av_state *state = &cx->av_state; | |
6246d4e1 | 1050 | struct v4l2_subdev *sd = &state->sd; |
1c1e45d1 HV |
1051 | u8 vidfmt_sel = cx18_av_read(cx, 0x400) & 0xf; |
1052 | u8 gen_stat1 = cx18_av_read(cx, 0x40d); | |
1053 | u8 gen_stat2 = cx18_av_read(cx, 0x40e); | |
1054 | int vid_input = state->vid_input; | |
1055 | ||
6246d4e1 AW |
1056 | CX18_INFO_DEV(sd, "Video signal: %spresent\n", |
1057 | (gen_stat2 & 0x20) ? "" : "not "); | |
1058 | CX18_INFO_DEV(sd, "Detected format: %s\n", | |
1059 | fmt_strs[gen_stat1 & 0xf]); | |
1c1e45d1 | 1060 | |
6246d4e1 AW |
1061 | CX18_INFO_DEV(sd, "Specified standard: %s\n", |
1062 | vidfmt_sel ? fmt_strs[vidfmt_sel] | |
1063 | : "automatic detection"); | |
1c1e45d1 HV |
1064 | |
1065 | if (vid_input >= CX18_AV_COMPOSITE1 && | |
1066 | vid_input <= CX18_AV_COMPOSITE8) { | |
6246d4e1 AW |
1067 | CX18_INFO_DEV(sd, "Specified video input: Composite %d\n", |
1068 | vid_input - CX18_AV_COMPOSITE1 + 1); | |
1c1e45d1 | 1069 | } else { |
6beb1388 | 1070 | CX18_INFO_DEV(sd, "Specified video input: S-Video (Luma In%d, Chroma In%d)\n", |
6246d4e1 AW |
1071 | (vid_input & 0xf0) >> 4, |
1072 | (vid_input & 0xf00) >> 8); | |
1c1e45d1 HV |
1073 | } |
1074 | ||
6246d4e1 AW |
1075 | CX18_INFO_DEV(sd, "Specified audioclock freq: %d Hz\n", |
1076 | state->audclk_freq); | |
1c1e45d1 HV |
1077 | } |
1078 | ||
1c1e45d1 HV |
1079 | static void log_audio_status(struct cx18 *cx) |
1080 | { | |
1081 | struct cx18_av_state *state = &cx->av_state; | |
6246d4e1 | 1082 | struct v4l2_subdev *sd = &state->sd; |
1c1e45d1 | 1083 | u8 download_ctl = cx18_av_read(cx, 0x803); |
63b8c709 HV |
1084 | u8 mod_det_stat0 = cx18_av_read(cx, 0x804); |
1085 | u8 mod_det_stat1 = cx18_av_read(cx, 0x805); | |
1c1e45d1 HV |
1086 | u8 audio_config = cx18_av_read(cx, 0x808); |
1087 | u8 pref_mode = cx18_av_read(cx, 0x809); | |
1088 | u8 afc0 = cx18_av_read(cx, 0x80b); | |
1089 | u8 mute_ctl = cx18_av_read(cx, 0x8d3); | |
1090 | int aud_input = state->aud_input; | |
1091 | char *p; | |
1092 | ||
1093 | switch (mod_det_stat0) { | |
1094 | case 0x00: p = "mono"; break; | |
1095 | case 0x01: p = "stereo"; break; | |
1096 | case 0x02: p = "dual"; break; | |
1097 | case 0x04: p = "tri"; break; | |
1098 | case 0x10: p = "mono with SAP"; break; | |
1099 | case 0x11: p = "stereo with SAP"; break; | |
1100 | case 0x12: p = "dual with SAP"; break; | |
1101 | case 0x14: p = "tri with SAP"; break; | |
1102 | case 0xfe: p = "forced mode"; break; | |
63b8c709 | 1103 | default: p = "not defined"; break; |
1c1e45d1 | 1104 | } |
6246d4e1 | 1105 | CX18_INFO_DEV(sd, "Detected audio mode: %s\n", p); |
1c1e45d1 HV |
1106 | |
1107 | switch (mod_det_stat1) { | |
63b8c709 | 1108 | case 0x00: p = "not defined"; break; |
1c1e45d1 HV |
1109 | case 0x01: p = "EIAJ"; break; |
1110 | case 0x02: p = "A2-M"; break; | |
1111 | case 0x03: p = "A2-BG"; break; | |
1112 | case 0x04: p = "A2-DK1"; break; | |
1113 | case 0x05: p = "A2-DK2"; break; | |
1114 | case 0x06: p = "A2-DK3"; break; | |
1115 | case 0x07: p = "A1 (6.0 MHz FM Mono)"; break; | |
1116 | case 0x08: p = "AM-L"; break; | |
1117 | case 0x09: p = "NICAM-BG"; break; | |
1118 | case 0x0a: p = "NICAM-DK"; break; | |
1119 | case 0x0b: p = "NICAM-I"; break; | |
1120 | case 0x0c: p = "NICAM-L"; break; | |
1121 | case 0x0d: p = "BTSC/EIAJ/A2-M Mono (4.5 MHz FMMono)"; break; | |
63b8c709 HV |
1122 | case 0x0e: p = "IF FM Radio"; break; |
1123 | case 0x0f: p = "BTSC"; break; | |
1124 | case 0x10: p = "detected chrominance"; break; | |
1125 | case 0xfd: p = "unknown audio standard"; break; | |
1126 | case 0xfe: p = "forced audio standard"; break; | |
1c1e45d1 | 1127 | case 0xff: p = "no detected audio standard"; break; |
63b8c709 | 1128 | default: p = "not defined"; break; |
1c1e45d1 | 1129 | } |
6246d4e1 AW |
1130 | CX18_INFO_DEV(sd, "Detected audio standard: %s\n", p); |
1131 | CX18_INFO_DEV(sd, "Audio muted: %s\n", | |
1132 | (mute_ctl & 0x2) ? "yes" : "no"); | |
1133 | CX18_INFO_DEV(sd, "Audio microcontroller: %s\n", | |
1134 | (download_ctl & 0x10) ? "running" : "stopped"); | |
1c1e45d1 HV |
1135 | |
1136 | switch (audio_config >> 4) { | |
63b8c709 HV |
1137 | case 0x00: p = "undefined"; break; |
1138 | case 0x01: p = "BTSC"; break; | |
1139 | case 0x02: p = "EIAJ"; break; | |
1140 | case 0x03: p = "A2-M"; break; | |
1141 | case 0x04: p = "A2-BG"; break; | |
1142 | case 0x05: p = "A2-DK1"; break; | |
1143 | case 0x06: p = "A2-DK2"; break; | |
1144 | case 0x07: p = "A2-DK3"; break; | |
1145 | case 0x08: p = "A1 (6.0 MHz FM Mono)"; break; | |
1146 | case 0x09: p = "AM-L"; break; | |
1147 | case 0x0a: p = "NICAM-BG"; break; | |
1148 | case 0x0b: p = "NICAM-DK"; break; | |
1149 | case 0x0c: p = "NICAM-I"; break; | |
1150 | case 0x0d: p = "NICAM-L"; break; | |
1151 | case 0x0e: p = "FM radio"; break; | |
1c1e45d1 | 1152 | case 0x0f: p = "automatic detection"; break; |
63b8c709 | 1153 | default: p = "undefined"; break; |
1c1e45d1 | 1154 | } |
6246d4e1 | 1155 | CX18_INFO_DEV(sd, "Configured audio standard: %s\n", p); |
1c1e45d1 HV |
1156 | |
1157 | if ((audio_config >> 4) < 0xF) { | |
1158 | switch (audio_config & 0xF) { | |
1159 | case 0x00: p = "MONO1 (LANGUAGE A/Mono L+R channel for BTSC, EIAJ, A2)"; break; | |
1160 | case 0x01: p = "MONO2 (LANGUAGE B)"; break; | |
1161 | case 0x02: p = "MONO3 (STEREO forced MONO)"; break; | |
1162 | case 0x03: p = "MONO4 (NICAM ANALOG-Language C/Analog Fallback)"; break; | |
1163 | case 0x04: p = "STEREO"; break; | |
63b8c709 HV |
1164 | case 0x05: p = "DUAL1 (AC)"; break; |
1165 | case 0x06: p = "DUAL2 (BC)"; break; | |
1166 | case 0x07: p = "DUAL3 (AB)"; break; | |
1c1e45d1 HV |
1167 | default: p = "undefined"; |
1168 | } | |
6246d4e1 | 1169 | CX18_INFO_DEV(sd, "Configured audio mode: %s\n", p); |
1c1e45d1 HV |
1170 | } else { |
1171 | switch (audio_config & 0xF) { | |
1172 | case 0x00: p = "BG"; break; | |
1173 | case 0x01: p = "DK1"; break; | |
1174 | case 0x02: p = "DK2"; break; | |
1175 | case 0x03: p = "DK3"; break; | |
1176 | case 0x04: p = "I"; break; | |
1177 | case 0x05: p = "L"; break; | |
1178 | case 0x06: p = "BTSC"; break; | |
1179 | case 0x07: p = "EIAJ"; break; | |
1180 | case 0x08: p = "A2-M"; break; | |
63b8c709 HV |
1181 | case 0x09: p = "FM Radio (4.5 MHz)"; break; |
1182 | case 0x0a: p = "FM Radio (5.5 MHz)"; break; | |
1183 | case 0x0b: p = "S-Video"; break; | |
1c1e45d1 | 1184 | case 0x0f: p = "automatic standard and mode detection"; break; |
63b8c709 | 1185 | default: p = "undefined"; break; |
1c1e45d1 | 1186 | } |
6246d4e1 | 1187 | CX18_INFO_DEV(sd, "Configured audio system: %s\n", p); |
1c1e45d1 HV |
1188 | } |
1189 | ||
1190 | if (aud_input) | |
6246d4e1 AW |
1191 | CX18_INFO_DEV(sd, "Specified audio input: Tuner (In%d)\n", |
1192 | aud_input); | |
1c1e45d1 | 1193 | else |
6246d4e1 | 1194 | CX18_INFO_DEV(sd, "Specified audio input: External\n"); |
1c1e45d1 HV |
1195 | |
1196 | switch (pref_mode & 0xf) { | |
1197 | case 0: p = "mono/language A"; break; | |
1198 | case 1: p = "language B"; break; | |
1199 | case 2: p = "language C"; break; | |
1200 | case 3: p = "analog fallback"; break; | |
1201 | case 4: p = "stereo"; break; | |
1202 | case 5: p = "language AC"; break; | |
1203 | case 6: p = "language BC"; break; | |
1204 | case 7: p = "language AB"; break; | |
63b8c709 | 1205 | default: p = "undefined"; break; |
1c1e45d1 | 1206 | } |
6246d4e1 | 1207 | CX18_INFO_DEV(sd, "Preferred audio mode: %s\n", p); |
1c1e45d1 HV |
1208 | |
1209 | if ((audio_config & 0xf) == 0xf) { | |
63b8c709 | 1210 | switch ((afc0 >> 3) & 0x1) { |
1c1e45d1 HV |
1211 | case 0: p = "system DK"; break; |
1212 | case 1: p = "system L"; break; | |
1213 | } | |
6246d4e1 | 1214 | CX18_INFO_DEV(sd, "Selected 65 MHz format: %s\n", p); |
1c1e45d1 | 1215 | |
63b8c709 HV |
1216 | switch (afc0 & 0x7) { |
1217 | case 0: p = "Chroma"; break; | |
1218 | case 1: p = "BTSC"; break; | |
1219 | case 2: p = "EIAJ"; break; | |
1220 | case 3: p = "A2-M"; break; | |
1221 | case 4: p = "autodetect"; break; | |
1222 | default: p = "undefined"; break; | |
1c1e45d1 | 1223 | } |
6246d4e1 | 1224 | CX18_INFO_DEV(sd, "Selected 45 MHz format: %s\n", p); |
1c1e45d1 HV |
1225 | } |
1226 | } | |
1a267046 AW |
1227 | |
1228 | static int cx18_av_log_status(struct v4l2_subdev *sd) | |
1229 | { | |
1230 | struct cx18 *cx = v4l2_get_subdevdata(sd); | |
1231 | log_video_status(cx); | |
1232 | log_audio_status(cx); | |
1233 | return 0; | |
1234 | } | |
1235 | ||
1a267046 AW |
1236 | #ifdef CONFIG_VIDEO_ADV_DEBUG |
1237 | static int cx18_av_g_register(struct v4l2_subdev *sd, | |
1238 | struct v4l2_dbg_register *reg) | |
1239 | { | |
1240 | struct cx18 *cx = v4l2_get_subdevdata(sd); | |
1241 | ||
1a267046 AW |
1242 | if ((reg->reg & 0x3) != 0) |
1243 | return -EINVAL; | |
1a267046 AW |
1244 | reg->size = 4; |
1245 | reg->val = cx18_av_read4(cx, reg->reg & 0x00000ffc); | |
1246 | return 0; | |
1247 | } | |
1248 | ||
1249 | static int cx18_av_s_register(struct v4l2_subdev *sd, | |
977ba3b1 | 1250 | const struct v4l2_dbg_register *reg) |
1a267046 AW |
1251 | { |
1252 | struct cx18 *cx = v4l2_get_subdevdata(sd); | |
1253 | ||
1a267046 AW |
1254 | if ((reg->reg & 0x3) != 0) |
1255 | return -EINVAL; | |
1a267046 AW |
1256 | cx18_av_write4(cx, reg->reg & 0x00000ffc, reg->val); |
1257 | return 0; | |
1258 | } | |
1259 | #endif | |
1260 | ||
a75b9be1 HV |
1261 | static const struct v4l2_ctrl_ops cx18_av_ctrl_ops = { |
1262 | .s_ctrl = cx18_av_s_ctrl, | |
1263 | }; | |
1264 | ||
1a267046 | 1265 | static const struct v4l2_subdev_core_ops cx18_av_general_ops = { |
1a267046 | 1266 | .log_status = cx18_av_log_status, |
cc26b076 | 1267 | .load_fw = cx18_av_load_fw, |
1a267046 | 1268 | .reset = cx18_av_reset, |
1a267046 AW |
1269 | #ifdef CONFIG_VIDEO_ADV_DEBUG |
1270 | .g_register = cx18_av_g_register, | |
1271 | .s_register = cx18_av_s_register, | |
1272 | #endif | |
1273 | }; | |
1274 | ||
1275 | static const struct v4l2_subdev_tuner_ops cx18_av_tuner_ops = { | |
1276 | .s_radio = cx18_av_s_radio, | |
1277 | .s_frequency = cx18_av_s_frequency, | |
1278 | .g_tuner = cx18_av_g_tuner, | |
1279 | .s_tuner = cx18_av_s_tuner, | |
1a267046 AW |
1280 | }; |
1281 | ||
1282 | static const struct v4l2_subdev_audio_ops cx18_av_audio_ops = { | |
1283 | .s_clock_freq = cx18_av_s_clock_freq, | |
1284 | .s_routing = cx18_av_s_audio_routing, | |
1285 | }; | |
1286 | ||
1287 | static const struct v4l2_subdev_video_ops cx18_av_video_ops = { | |
8774bed9 | 1288 | .s_std = cx18_av_s_std, |
1a267046 | 1289 | .s_routing = cx18_av_s_video_routing, |
1a267046 | 1290 | .s_stream = cx18_av_s_stream, |
1a267046 AW |
1291 | }; |
1292 | ||
32cd527f HV |
1293 | static const struct v4l2_subdev_vbi_ops cx18_av_vbi_ops = { |
1294 | .decode_vbi_line = cx18_av_decode_vbi_line, | |
1585927d HV |
1295 | .g_sliced_fmt = cx18_av_g_sliced_fmt, |
1296 | .s_sliced_fmt = cx18_av_s_sliced_fmt, | |
1297 | .s_raw_fmt = cx18_av_s_raw_fmt, | |
32cd527f HV |
1298 | }; |
1299 | ||
6e80c473 HV |
1300 | static const struct v4l2_subdev_pad_ops cx18_av_pad_ops = { |
1301 | .set_fmt = cx18_av_set_fmt, | |
1302 | }; | |
1303 | ||
1a267046 AW |
1304 | static const struct v4l2_subdev_ops cx18_av_ops = { |
1305 | .core = &cx18_av_general_ops, | |
1306 | .tuner = &cx18_av_tuner_ops, | |
1307 | .audio = &cx18_av_audio_ops, | |
1308 | .video = &cx18_av_video_ops, | |
32cd527f | 1309 | .vbi = &cx18_av_vbi_ops, |
6e80c473 | 1310 | .pad = &cx18_av_pad_ops, |
1a267046 AW |
1311 | }; |
1312 | ||
ff2a2001 | 1313 | int cx18_av_probe(struct cx18 *cx) |
1a267046 | 1314 | { |
fa3e7036 | 1315 | struct cx18_av_state *state = &cx->av_state; |
ff2a2001 | 1316 | struct v4l2_subdev *sd; |
7f3ea4de | 1317 | int err; |
fa3e7036 AW |
1318 | |
1319 | state->rev = cx18_av_read4(cx, CXADEC_CHIP_CTRL) & 0xffff; | |
fa3e7036 AW |
1320 | |
1321 | state->vid_input = CX18_AV_COMPOSITE7; | |
1322 | state->aud_input = CX18_AV_AUDIO8; | |
1323 | state->audclk_freq = 48000; | |
1324 | state->audmode = V4L2_TUNER_MODE_LANG1; | |
1325 | state->slicer_line_delay = 0; | |
1326 | state->slicer_line_offset = (10 + state->slicer_line_delay - 2); | |
1327 | ||
ff2a2001 AW |
1328 | sd = &state->sd; |
1329 | v4l2_subdev_init(sd, &cx18_av_ops); | |
1330 | v4l2_set_subdevdata(sd, cx); | |
1331 | snprintf(sd->name, sizeof(sd->name), | |
6246d4e1 | 1332 | "%s %03x", cx->v4l2_dev.name, (state->rev >> 4)); |
ff2a2001 | 1333 | sd->grp_id = CX18_HW_418_AV; |
a75b9be1 HV |
1334 | v4l2_ctrl_handler_init(&state->hdl, 9); |
1335 | v4l2_ctrl_new_std(&state->hdl, &cx18_av_ctrl_ops, | |
1336 | V4L2_CID_BRIGHTNESS, 0, 255, 1, 128); | |
1337 | v4l2_ctrl_new_std(&state->hdl, &cx18_av_ctrl_ops, | |
1338 | V4L2_CID_CONTRAST, 0, 127, 1, 64); | |
1339 | v4l2_ctrl_new_std(&state->hdl, &cx18_av_ctrl_ops, | |
1340 | V4L2_CID_SATURATION, 0, 127, 1, 64); | |
1341 | v4l2_ctrl_new_std(&state->hdl, &cx18_av_ctrl_ops, | |
1342 | V4L2_CID_HUE, -128, 127, 1, 0); | |
1343 | ||
1344 | state->volume = v4l2_ctrl_new_std(&state->hdl, | |
1345 | &cx18_av_audio_ctrl_ops, V4L2_CID_AUDIO_VOLUME, | |
1346 | 0, 65535, 65535 / 100, 0); | |
1347 | v4l2_ctrl_new_std(&state->hdl, | |
1348 | &cx18_av_audio_ctrl_ops, V4L2_CID_AUDIO_MUTE, | |
1349 | 0, 1, 1, 0); | |
1350 | v4l2_ctrl_new_std(&state->hdl, &cx18_av_audio_ctrl_ops, | |
1351 | V4L2_CID_AUDIO_BALANCE, | |
1352 | 0, 65535, 65535 / 100, 32768); | |
1353 | v4l2_ctrl_new_std(&state->hdl, &cx18_av_audio_ctrl_ops, | |
1354 | V4L2_CID_AUDIO_BASS, | |
1355 | 0, 65535, 65535 / 100, 32768); | |
1356 | v4l2_ctrl_new_std(&state->hdl, &cx18_av_audio_ctrl_ops, | |
1357 | V4L2_CID_AUDIO_TREBLE, | |
1358 | 0, 65535, 65535 / 100, 32768); | |
1359 | sd->ctrl_handler = &state->hdl; | |
1360 | if (state->hdl.error) { | |
1361 | int err = state->hdl.error; | |
1362 | ||
1363 | v4l2_ctrl_handler_free(&state->hdl); | |
1364 | return err; | |
1365 | } | |
7f3ea4de | 1366 | err = v4l2_device_register_subdev(&cx->v4l2_dev, sd); |
a75b9be1 HV |
1367 | if (err) |
1368 | v4l2_ctrl_handler_free(&state->hdl); | |
1369 | else | |
7f3ea4de HV |
1370 | cx18_av_init(cx); |
1371 | return err; | |
1a267046 | 1372 | } |