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9ea53b74 | 1 | /* |
11b64d31 | 2 | * driver for ENE KB3926 B/C/D/E/F CIR (also known as ENE0XXX) |
9ea53b74 ML |
3 | * |
4 | * Copyright (C) 2010 Maxim Levitsky <maximlevitsky@gmail.com> | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or | |
7 | * modify it under the terms of the GNU General Public License as | |
8 | * published by the Free Software Foundation; either version 2 of the | |
9 | * License, or (at your option) any later version. | |
10 | * | |
11 | * This program is distributed in the hope that it will be useful, but | |
12 | * WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
14 | * General Public License for more details. | |
9ea53b74 ML |
15 | */ |
16 | #include <linux/spinlock.h> | |
931e39a1 | 17 | |
9ea53b74 ML |
18 | |
19 | /* hardware address */ | |
20 | #define ENE_STATUS 0 /* hardware status - unused */ | |
21 | #define ENE_ADDR_HI 1 /* hi byte of register address */ | |
22 | #define ENE_ADDR_LO 2 /* low byte of register address */ | |
23 | #define ENE_IO 3 /* read/write window */ | |
11b64d31 ML |
24 | #define ENE_IO_SIZE 4 |
25 | ||
26 | /* 8 bytes of samples, divided in 2 packets*/ | |
27 | #define ENE_FW_SAMPLE_BUFFER 0xF8F0 /* sample buffer */ | |
28 | #define ENE_FW_SAMPLE_SPACE 0x80 /* sample is space */ | |
29 | #define ENE_FW_PACKET_SIZE 4 | |
30 | ||
31 | /* first firmware flag register */ | |
32 | #define ENE_FW1 0xF8F8 /* flagr */ | |
9ea53b74 ML |
33 | #define ENE_FW1_ENABLE 0x01 /* enable fw processing */ |
34 | #define ENE_FW1_TXIRQ 0x02 /* TX interrupt pending */ | |
11b64d31 ML |
35 | #define ENE_FW1_HAS_EXTRA_BUF 0x04 /* fw uses extra buffer*/ |
36 | #define ENE_FW1_EXTRA_BUF_HND 0x08 /* extra buffer handshake bit*/ | |
37 | #define ENE_FW1_LED_ON 0x10 /* turn on a led */ | |
38 | ||
39 | #define ENE_FW1_WPATTERN 0x20 /* enable wake pattern */ | |
9ea53b74 ML |
40 | #define ENE_FW1_WAKE 0x40 /* enable wake from S3 */ |
41 | #define ENE_FW1_IRQ 0x80 /* enable interrupt */ | |
42 | ||
11b64d31 ML |
43 | /* second firmware flag register */ |
44 | #define ENE_FW2 0xF8F9 /* flagw */ | |
45 | #define ENE_FW2_BUF_WPTR 0x01 /* which half of the buffer to read */ | |
46 | #define ENE_FW2_RXIRQ 0x04 /* RX IRQ pending*/ | |
47 | #define ENE_FW2_GP0A 0x08 /* Use GPIO0A for demodulated input */ | |
48 | #define ENE_FW2_EMMITER1_CONN 0x10 /* TX emmiter 1 connected */ | |
49 | #define ENE_FW2_EMMITER2_CONN 0x20 /* TX emmiter 2 connected */ | |
50 | ||
51 | #define ENE_FW2_FAN_INPUT 0x40 /* fan input used for demodulated data*/ | |
9ea53b74 ML |
52 | #define ENE_FW2_LEARNING 0x80 /* hardware supports learning and TX */ |
53 | ||
11b64d31 ML |
54 | /* firmware RX pointer for new style buffer */ |
55 | #define ENE_FW_RX_POINTER 0xF8FA | |
56 | ||
57 | /* high parts of samples for fan input (8 samples)*/ | |
58 | #define ENE_FW_SMPL_BUF_FAN 0xF8FB | |
59 | #define ENE_FW_SMPL_BUF_FAN_PLS 0x8000 /* combined sample is pulse */ | |
60 | #define ENE_FW_SMPL_BUF_FAN_MSK 0x0FFF /* combined sample maximum value */ | |
61 | #define ENE_FW_SAMPLE_PERIOD_FAN 61 /* fan input has fixed sample period */ | |
62 | ||
9ea53b74 | 63 | /* transmitter ports */ |
11b64d31 ML |
64 | #define ENE_GPIOFS1 0xFC01 |
65 | #define ENE_GPIOFS1_GPIO0D 0x20 /* enable tx output on GPIO0D */ | |
66 | #define ENE_GPIOFS8 0xFC08 | |
67 | #define ENE_GPIOFS8_GPIO41 0x02 /* enable tx output on GPIO40 */ | |
9ea53b74 ML |
68 | |
69 | /* IRQ registers block (for revision B) */ | |
70 | #define ENEB_IRQ 0xFD09 /* IRQ number */ | |
71 | #define ENEB_IRQ_UNK1 0xFD17 /* unknown setting = 1 */ | |
72 | #define ENEB_IRQ_STATUS 0xFD80 /* irq status */ | |
73 | #define ENEB_IRQ_STATUS_IR 0x20 /* IR irq */ | |
74 | ||
11b64d31 | 75 | /* fan as input settings */ |
9ea53b74 ML |
76 | #define ENE_FAN_AS_IN1 0xFE30 /* fan init reg 1 */ |
77 | #define ENE_FAN_AS_IN1_EN 0xCD | |
78 | #define ENE_FAN_AS_IN2 0xFE31 /* fan init reg 2 */ | |
79 | #define ENE_FAN_AS_IN2_EN 0x03 | |
9ea53b74 ML |
80 | |
81 | /* IRQ registers block (for revision C,D) */ | |
11b64d31 ML |
82 | #define ENE_IRQ 0xFE9B /* new irq settings register */ |
83 | #define ENE_IRQ_MASK 0x0F /* irq number mask */ | |
84 | #define ENE_IRQ_UNK_EN 0x10 /* always enabled */ | |
85 | #define ENE_IRQ_STATUS 0x20 /* irq status and ACK */ | |
86 | ||
87 | /* CIR Config register #1 */ | |
88 | #define ENE_CIRCFG 0xFEC0 | |
89 | #define ENE_CIRCFG_RX_EN 0x01 /* RX enable */ | |
90 | #define ENE_CIRCFG_RX_IRQ 0x02 /* Enable hardware interrupt */ | |
91 | #define ENE_CIRCFG_REV_POL 0x04 /* Input polarity reversed */ | |
92 | #define ENE_CIRCFG_CARR_DEMOD 0x08 /* Enable carrier demodulator */ | |
93 | ||
94 | #define ENE_CIRCFG_TX_EN 0x10 /* TX enable */ | |
95 | #define ENE_CIRCFG_TX_IRQ 0x20 /* Send interrupt on TX done */ | |
96 | #define ENE_CIRCFG_TX_POL_REV 0x40 /* TX polarity reversed */ | |
97 | #define ENE_CIRCFG_TX_CARR 0x80 /* send TX carrier or not */ | |
98 | ||
99 | /* CIR config register #2 */ | |
100 | #define ENE_CIRCFG2 0xFEC1 | |
101 | #define ENE_CIRCFG2_RLC 0x00 | |
102 | #define ENE_CIRCFG2_RC5 0x01 | |
103 | #define ENE_CIRCFG2_RC6 0x02 | |
104 | #define ENE_CIRCFG2_NEC 0x03 | |
105 | #define ENE_CIRCFG2_CARR_DETECT 0x10 /* Enable carrier detection */ | |
106 | #define ENE_CIRCFG2_GPIO0A 0x20 /* Use GPIO0A instead of GPIO40 for input */ | |
107 | #define ENE_CIRCFG2_FAST_SAMPL1 0x40 /* Fast leading pulse detection for RC6 */ | |
108 | #define ENE_CIRCFG2_FAST_SAMPL2 0x80 /* Fast data detection for RC6 */ | |
109 | ||
110 | /* Knobs for protocol decoding - will document when/if will use them */ | |
111 | #define ENE_CIRPF 0xFEC2 | |
112 | #define ENE_CIRHIGH 0xFEC3 | |
113 | #define ENE_CIRBIT 0xFEC4 | |
114 | #define ENE_CIRSTART 0xFEC5 | |
115 | #define ENE_CIRSTART2 0xFEC6 | |
116 | ||
117 | /* Actual register which contains RLC RX data - read by firmware */ | |
118 | #define ENE_CIRDAT_IN 0xFEC7 | |
119 | ||
120 | ||
121 | /* RLC configuration - sample period (1us resulution) + idle mode */ | |
122 | #define ENE_CIRRLC_CFG 0xFEC8 | |
123 | #define ENE_CIRRLC_CFG_OVERFLOW 0x80 /* interrupt on overflows if set */ | |
124 | #define ENE_DEFAULT_SAMPLE_PERIOD 50 | |
125 | ||
126 | /* Two byte RLC TX buffer */ | |
127 | #define ENE_CIRRLC_OUT0 0xFEC9 | |
128 | #define ENE_CIRRLC_OUT1 0xFECA | |
129 | #define ENE_CIRRLC_OUT_PULSE 0x80 /* Transmitted sample is pulse */ | |
130 | #define ENE_CIRRLC_OUT_MASK 0x7F | |
131 | ||
132 | ||
133 | /* Carrier detect setting | |
134 | * Low nibble - number of carrier pulses to average | |
135 | * High nibble - number of initial carrier pulses to discard | |
136 | */ | |
137 | #define ENE_CIRCAR_PULS 0xFECB | |
9ea53b74 | 138 | |
11b64d31 ML |
139 | /* detected RX carrier period (resolution: 500 ns) */ |
140 | #define ENE_CIRCAR_PRD 0xFECC | |
141 | #define ENE_CIRCAR_PRD_VALID 0x80 /* data valid content valid */ | |
9ea53b74 | 142 | |
11b64d31 ML |
143 | /* detected RX carrier pulse width (resolution: 500 ns) */ |
144 | #define ENE_CIRCAR_HPRD 0xFECD | |
9ea53b74 | 145 | |
11b64d31 ML |
146 | /* TX period (resolution: 500 ns, minimum 2)*/ |
147 | #define ENE_CIRMOD_PRD 0xFECE | |
148 | #define ENE_CIRMOD_PRD_POL 0x80 /* TX carrier polarity*/ | |
9ea53b74 | 149 | |
11b64d31 ML |
150 | #define ENE_CIRMOD_PRD_MAX 0x7F /* 15.87 kHz */ |
151 | #define ENE_CIRMOD_PRD_MIN 0x02 /* 1 Mhz */ | |
9ea53b74 | 152 | |
11b64d31 ML |
153 | /* TX pulse width (resolution: 500 ns)*/ |
154 | #define ENE_CIRMOD_HPRD 0xFECF | |
9ea53b74 ML |
155 | |
156 | /* Hardware versions */ | |
11b64d31 | 157 | #define ENE_ECHV 0xFF00 /* hardware revision */ |
931e39a1 ML |
158 | #define ENE_PLLFRH 0xFF16 |
159 | #define ENE_PLLFRL 0xFF17 | |
11b64d31 | 160 | #define ENE_DEFAULT_PLL_FREQ 1000 |
931e39a1 | 161 | |
11b64d31 ML |
162 | #define ENE_ECSTS 0xFF1D |
163 | #define ENE_ECSTS_RSRVD 0x04 | |
9ea53b74 | 164 | |
11b64d31 ML |
165 | #define ENE_ECVER_MAJOR 0xFF1E /* chip version */ |
166 | #define ENE_ECVER_MINOR 0xFF1F | |
167 | #define ENE_HW_VER_OLD 0xFD00 | |
9ea53b74 ML |
168 | |
169 | /******************************************************************************/ | |
170 | ||
931e39a1 | 171 | #define ENE_DRIVER_NAME "ene_ir" |
9ea53b74 ML |
172 | |
173 | #define ENE_IRQ_RX 1 | |
174 | #define ENE_IRQ_TX 2 | |
175 | ||
176 | #define ENE_HW_B 1 /* 3926B */ | |
177 | #define ENE_HW_C 2 /* 3926C */ | |
11b64d31 | 178 | #define ENE_HW_D 3 /* 3926D or later */ |
9ea53b74 | 179 | |
7de3461c JP |
180 | #define __dbg(level, format, ...) \ |
181 | do { \ | |
182 | if (debug >= level) \ | |
408ed992 | 183 | pr_info(format "\n", ## __VA_ARGS__); \ |
7de3461c | 184 | } while (0) |
11b64d31 ML |
185 | |
186 | #define dbg(format, ...) __dbg(1, format, ## __VA_ARGS__) | |
187 | #define dbg_verbose(format, ...) __dbg(2, format, ## __VA_ARGS__) | |
188 | #define dbg_regs(format, ...) __dbg(3, format, ## __VA_ARGS__) | |
189 | ||
9ea53b74 ML |
190 | struct ene_device { |
191 | struct pnp_dev *pnp_dev; | |
d8b4b582 | 192 | struct rc_dev *rdev; |
9ea53b74 ML |
193 | |
194 | /* hw IO settings */ | |
11b64d31 | 195 | long hw_io; |
9ea53b74 ML |
196 | int irq; |
197 | spinlock_t hw_lock; | |
198 | ||
199 | /* HW features */ | |
200 | int hw_revision; /* hardware revision */ | |
c29bc4d7 | 201 | bool hw_use_gpio_0a; /* gpio0a is demodulated input*/ |
11b64d31 ML |
202 | bool hw_extra_buffer; /* hardware has 'extra buffer' */ |
203 | bool hw_fan_input; /* fan input is IR data source */ | |
204 | bool hw_learning_and_tx_capable; /* learning & tx capable */ | |
205 | int pll_freq; | |
206 | int buffer_len; | |
207 | ||
208 | /* Extra RX buffer location */ | |
209 | int extra_buf1_address; | |
210 | int extra_buf1_len; | |
211 | int extra_buf2_address; | |
212 | int extra_buf2_len; | |
213 | ||
9ea53b74 | 214 | /* HW state*/ |
11b64d31 ML |
215 | int r_pointer; /* pointer to next sample to read */ |
216 | int w_pointer; /* pointer to next sample hw will write */ | |
931e39a1 | 217 | bool rx_fan_input_inuse; /* is fan input in use for rx*/ |
9ea53b74 ML |
218 | int tx_reg; /* current reg used for TX */ |
219 | u8 saved_conf1; /* saved FEC0 reg */ | |
9ea53b74 | 220 | unsigned int tx_sample; /* current sample for TX */ |
931e39a1 | 221 | bool tx_sample_pulse; /* current sample is pulse */ |
9ea53b74 ML |
222 | |
223 | /* TX buffer */ | |
5588dc2b | 224 | unsigned *tx_buffer; /* input samples buffer*/ |
90802ed9 | 225 | int tx_pos; /* position in that buffer */ |
9ea53b74 | 226 | int tx_len; /* current len of tx buffer */ |
9ea53b74 ML |
227 | int tx_done; /* done transmitting */ |
228 | /* one more sample pending*/ | |
229 | struct completion tx_complete; /* TX completion */ | |
230 | struct timer_list tx_sim_timer; | |
231 | ||
931e39a1 | 232 | /* TX settings */ |
9ea53b74 ML |
233 | int tx_period; |
234 | int tx_duty_cycle; | |
235 | int transmitter_mask; | |
931e39a1 ML |
236 | |
237 | /* RX settings */ | |
c29bc4d7 | 238 | bool learning_mode_enabled; /* learning input enabled */ |
931e39a1 ML |
239 | bool carrier_detect_enabled; /* carrier detect enabled */ |
240 | int rx_period_adjust; | |
11b64d31 | 241 | bool rx_enabled; |
9ea53b74 | 242 | }; |
11b64d31 ML |
243 | |
244 | static int ene_irq_status(struct ene_device *dev); | |
c29bc4d7 | 245 | static void ene_rx_read_hw_pointer(struct ene_device *dev); |