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Commit | Line | Data |
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1da177e4 | 1 | /* |
1da177e4 LT |
2 | * |
3 | * (c) 2004 Gerd Knorr <kraxel@bytesex.org> [SuSE Labs] | |
4 | * | |
86ddd96f MCC |
5 | * Extended 3 / 2005 by Hartmut Hackmann to support various |
6 | * cards with the tda10046 DVB-T channel decoder | |
7 | * | |
1da177e4 LT |
8 | * This program is free software; you can redistribute it and/or modify |
9 | * it under the terms of the GNU General Public License as published by | |
10 | * the Free Software Foundation; either version 2 of the License, or | |
11 | * (at your option) any later version. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, | |
14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | * GNU General Public License for more details. | |
17 | * | |
18 | * You should have received a copy of the GNU General Public License | |
19 | * along with this program; if not, write to the Free Software | |
20 | * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. | |
21 | */ | |
22 | ||
23 | #include <linux/init.h> | |
24 | #include <linux/list.h> | |
25 | #include <linux/module.h> | |
26 | #include <linux/kernel.h> | |
27 | #include <linux/slab.h> | |
28 | #include <linux/delay.h> | |
29 | #include <linux/kthread.h> | |
30 | #include <linux/suspend.h> | |
31 | ||
32 | #include "saa7134-reg.h" | |
33 | #include "saa7134.h" | |
5e453dc7 | 34 | #include <media/v4l2-common.h> |
a78d0bfa | 35 | #include "dvb-pll.h" |
1da177e4 | 36 | |
29780bb7 | 37 | #ifdef HAVE_MT352 |
86ddd96f MCC |
38 | # include "mt352.h" |
39 | # include "mt352_priv.h" /* FIXME */ | |
40 | #endif | |
29780bb7 | 41 | #ifdef HAVE_TDA1004X |
86ddd96f MCC |
42 | # include "tda1004x.h" |
43 | #endif | |
3b64e8e2 MK |
44 | #ifdef HAVE_NXT200X |
45 | # include "nxt200x.h" | |
3b64e8e2 | 46 | #endif |
1da177e4 LT |
47 | |
48 | MODULE_AUTHOR("Gerd Knorr <kraxel@bytesex.org> [SuSE Labs]"); | |
49 | MODULE_LICENSE("GPL"); | |
50 | ||
51 | static unsigned int antenna_pwr = 0; | |
86ddd96f | 52 | |
1da177e4 LT |
53 | module_param(antenna_pwr, int, 0444); |
54 | MODULE_PARM_DESC(antenna_pwr,"enable antenna power (Pinnacle 300i)"); | |
55 | ||
56 | /* ------------------------------------------------------------------ */ | |
57 | ||
29780bb7 | 58 | #ifdef HAVE_MT352 |
1da177e4 LT |
59 | static int pinnacle_antenna_pwr(struct saa7134_dev *dev, int on) |
60 | { | |
61 | u32 ok; | |
62 | ||
63 | if (!on) { | |
64 | saa_setl(SAA7134_GPIO_GPMODE0 >> 2, (1 << 26)); | |
65 | saa_clearl(SAA7134_GPIO_GPSTATUS0 >> 2, (1 << 26)); | |
66 | return 0; | |
67 | } | |
68 | ||
69 | saa_setl(SAA7134_GPIO_GPMODE0 >> 2, (1 << 26)); | |
70 | saa_setl(SAA7134_GPIO_GPSTATUS0 >> 2, (1 << 26)); | |
71 | udelay(10); | |
72 | ||
73 | saa_setl(SAA7134_GPIO_GPMODE0 >> 2, (1 << 28)); | |
74 | saa_clearl(SAA7134_GPIO_GPSTATUS0 >> 2, (1 << 28)); | |
75 | udelay(10); | |
76 | saa_setl(SAA7134_GPIO_GPSTATUS0 >> 2, (1 << 28)); | |
77 | udelay(10); | |
78 | ok = saa_readl(SAA7134_GPIO_GPSTATUS0) & (1 << 27); | |
79 | printk("%s: %s %s\n", dev->name, __FUNCTION__, | |
80 | ok ? "on" : "off"); | |
81 | ||
82 | if (!ok) | |
83 | saa_clearl(SAA7134_GPIO_GPSTATUS0 >> 2, (1 << 26)); | |
84 | return ok; | |
85 | } | |
86 | ||
87 | static int mt352_pinnacle_init(struct dvb_frontend* fe) | |
88 | { | |
89 | static u8 clock_config [] = { CLOCK_CTL, 0x3d, 0x28 }; | |
90 | static u8 reset [] = { RESET, 0x80 }; | |
91 | static u8 adc_ctl_1_cfg [] = { ADC_CTL_1, 0x40 }; | |
92 | static u8 agc_cfg [] = { AGC_TARGET, 0x28, 0xa0 }; | |
93 | static u8 capt_range_cfg[] = { CAPT_RANGE, 0x31 }; | |
94 | static u8 fsm_ctl_cfg[] = { 0x7b, 0x04 }; | |
95 | static u8 gpp_ctl_cfg [] = { GPP_CTL, 0x0f }; | |
96 | static u8 scan_ctl_cfg [] = { SCAN_CTL, 0x0d }; | |
97 | static u8 irq_cfg [] = { INTERRUPT_EN_0, 0x00, 0x00, 0x00, 0x00 }; | |
98 | struct saa7134_dev *dev= fe->dvb->priv; | |
99 | ||
100 | printk("%s: %s called\n",dev->name,__FUNCTION__); | |
101 | ||
102 | mt352_write(fe, clock_config, sizeof(clock_config)); | |
103 | udelay(200); | |
104 | mt352_write(fe, reset, sizeof(reset)); | |
105 | mt352_write(fe, adc_ctl_1_cfg, sizeof(adc_ctl_1_cfg)); | |
106 | mt352_write(fe, agc_cfg, sizeof(agc_cfg)); | |
107 | mt352_write(fe, capt_range_cfg, sizeof(capt_range_cfg)); | |
108 | mt352_write(fe, gpp_ctl_cfg, sizeof(gpp_ctl_cfg)); | |
109 | ||
110 | mt352_write(fe, fsm_ctl_cfg, sizeof(fsm_ctl_cfg)); | |
111 | mt352_write(fe, scan_ctl_cfg, sizeof(scan_ctl_cfg)); | |
112 | mt352_write(fe, irq_cfg, sizeof(irq_cfg)); | |
df8cf706 | 113 | |
1da177e4 LT |
114 | return 0; |
115 | } | |
116 | ||
a78d0bfa JAR |
117 | static int mt352_aver777_init(struct dvb_frontend* fe) |
118 | { | |
119 | static u8 clock_config [] = { CLOCK_CTL, 0x38, 0x2d }; | |
120 | static u8 reset [] = { RESET, 0x80 }; | |
121 | static u8 adc_ctl_1_cfg [] = { ADC_CTL_1, 0x40 }; | |
122 | static u8 agc_cfg [] = { AGC_TARGET, 0x28, 0xa0 }; | |
123 | static u8 capt_range_cfg[] = { CAPT_RANGE, 0x33 }; | |
124 | ||
125 | mt352_write(fe, clock_config, sizeof(clock_config)); | |
126 | udelay(200); | |
127 | mt352_write(fe, reset, sizeof(reset)); | |
128 | mt352_write(fe, adc_ctl_1_cfg, sizeof(adc_ctl_1_cfg)); | |
129 | mt352_write(fe, agc_cfg, sizeof(agc_cfg)); | |
130 | mt352_write(fe, capt_range_cfg, sizeof(capt_range_cfg)); | |
131 | ||
132 | return 0; | |
133 | } | |
134 | ||
0463f12c AQ |
135 | static int mt352_pinnacle_tuner_set_params(struct dvb_frontend* fe, |
136 | struct dvb_frontend_parameters* params) | |
1da177e4 | 137 | { |
df8cf706 HH |
138 | u8 off[] = { 0x00, 0xf1}; |
139 | u8 on[] = { 0x00, 0x71}; | |
140 | struct i2c_msg msg = {.addr=0x43, .flags=0, .buf=off, .len = sizeof(off)}; | |
141 | ||
1da177e4 LT |
142 | struct saa7134_dev *dev = fe->dvb->priv; |
143 | struct v4l2_frequency f; | |
144 | ||
145 | /* set frequency (mt2050) */ | |
146 | f.tuner = 0; | |
147 | f.type = V4L2_TUNER_DIGITAL_TV; | |
148 | f.frequency = params->frequency / 1000 * 16 / 1000; | |
dea74869 PB |
149 | if (fe->ops.i2c_gate_ctrl) |
150 | fe->ops.i2c_gate_ctrl(fe, 1); | |
df8cf706 | 151 | i2c_transfer(&dev->i2c_adap, &msg, 1); |
1da177e4 | 152 | saa7134_i2c_call_clients(dev,VIDIOC_S_FREQUENCY,&f); |
df8cf706 | 153 | msg.buf = on; |
dea74869 PB |
154 | if (fe->ops.i2c_gate_ctrl) |
155 | fe->ops.i2c_gate_ctrl(fe, 1); | |
df8cf706 | 156 | i2c_transfer(&dev->i2c_adap, &msg, 1); |
1da177e4 LT |
157 | |
158 | pinnacle_antenna_pwr(dev, antenna_pwr); | |
159 | ||
160 | /* mt352 setup */ | |
0463f12c | 161 | return mt352_pinnacle_init(fe); |
1da177e4 LT |
162 | } |
163 | ||
bd4956b8 | 164 | static int mt352_aver777_tuner_calc_regs(struct dvb_frontend *fe, struct dvb_frontend_parameters *params, u8* pllbuf, int buf_len) |
a78d0bfa | 165 | { |
a79ddae9 AQ |
166 | if (buf_len < 5) |
167 | return -EINVAL; | |
168 | ||
169 | pllbuf[0] = 0x61; | |
a78d0bfa JAR |
170 | dvb_pll_configure(&dvb_pll_philips_td1316, pllbuf+1, |
171 | params->frequency, | |
172 | params->u.ofdm.bandwidth); | |
a79ddae9 | 173 | return 5; |
a78d0bfa JAR |
174 | } |
175 | ||
1da177e4 LT |
176 | static struct mt352_config pinnacle_300i = { |
177 | .demod_address = 0x3c >> 1, | |
178 | .adc_clock = 20333, | |
179 | .if2 = 36150, | |
180 | .no_tuner = 1, | |
181 | .demod_init = mt352_pinnacle_init, | |
1da177e4 | 182 | }; |
a78d0bfa JAR |
183 | |
184 | static struct mt352_config avermedia_777 = { | |
185 | .demod_address = 0xf, | |
186 | .demod_init = mt352_aver777_init, | |
a78d0bfa | 187 | }; |
86ddd96f | 188 | #endif |
1da177e4 LT |
189 | |
190 | /* ------------------------------------------------------------------ */ | |
191 | ||
29780bb7 | 192 | #ifdef HAVE_TDA1004X |
1da177e4 | 193 | |
2cf36ac4 | 194 | static int philips_tda6651_pll_set(u8 addr, struct dvb_frontend *fe, struct dvb_frontend_parameters *params) |
1da177e4 LT |
195 | { |
196 | struct saa7134_dev *dev = fe->dvb->priv; | |
86ddd96f | 197 | u8 tuner_buf[4]; |
2cf36ac4 | 198 | struct i2c_msg tuner_msg = {.addr = addr,.flags = 0,.buf = tuner_buf,.len = |
86ddd96f MCC |
199 | sizeof(tuner_buf) }; |
200 | int tuner_frequency = 0; | |
201 | u8 band, cp, filter; | |
202 | ||
203 | /* determine charge pump */ | |
204 | tuner_frequency = params->frequency + 36166000; | |
205 | if (tuner_frequency < 87000000) | |
206 | return -EINVAL; | |
207 | else if (tuner_frequency < 130000000) | |
208 | cp = 3; | |
209 | else if (tuner_frequency < 160000000) | |
210 | cp = 5; | |
211 | else if (tuner_frequency < 200000000) | |
212 | cp = 6; | |
213 | else if (tuner_frequency < 290000000) | |
214 | cp = 3; | |
215 | else if (tuner_frequency < 420000000) | |
216 | cp = 5; | |
217 | else if (tuner_frequency < 480000000) | |
218 | cp = 6; | |
219 | else if (tuner_frequency < 620000000) | |
220 | cp = 3; | |
221 | else if (tuner_frequency < 830000000) | |
222 | cp = 5; | |
223 | else if (tuner_frequency < 895000000) | |
224 | cp = 7; | |
225 | else | |
226 | return -EINVAL; | |
227 | ||
228 | /* determine band */ | |
229 | if (params->frequency < 49000000) | |
230 | return -EINVAL; | |
231 | else if (params->frequency < 161000000) | |
232 | band = 1; | |
233 | else if (params->frequency < 444000000) | |
234 | band = 2; | |
235 | else if (params->frequency < 861000000) | |
236 | band = 4; | |
237 | else | |
238 | return -EINVAL; | |
239 | ||
240 | /* setup PLL filter */ | |
241 | switch (params->u.ofdm.bandwidth) { | |
242 | case BANDWIDTH_6_MHZ: | |
243 | filter = 0; | |
244 | break; | |
245 | ||
246 | case BANDWIDTH_7_MHZ: | |
247 | filter = 0; | |
248 | break; | |
249 | ||
250 | case BANDWIDTH_8_MHZ: | |
251 | filter = 1; | |
252 | break; | |
1da177e4 | 253 | |
86ddd96f MCC |
254 | default: |
255 | return -EINVAL; | |
256 | } | |
257 | ||
258 | /* calculate divisor | |
259 | * ((36166000+((1000000/6)/2)) + Finput)/(1000000/6) | |
1da177e4 | 260 | */ |
86ddd96f MCC |
261 | tuner_frequency = (((params->frequency / 1000) * 6) + 217496) / 1000; |
262 | ||
263 | /* setup tuner buffer */ | |
264 | tuner_buf[0] = (tuner_frequency >> 8) & 0x7f; | |
265 | tuner_buf[1] = tuner_frequency & 0xff; | |
266 | tuner_buf[2] = 0xca; | |
267 | tuner_buf[3] = (cp << 5) | (filter << 3) | band; | |
268 | ||
dea74869 PB |
269 | if (fe->ops.i2c_gate_ctrl) |
270 | fe->ops.i2c_gate_ctrl(fe, 1); | |
86ddd96f MCC |
271 | if (i2c_transfer(&dev->i2c_adap, &tuner_msg, 1) != 1) |
272 | return -EIO; | |
2cf36ac4 HH |
273 | msleep(1); |
274 | return 0; | |
275 | } | |
276 | ||
277 | static int philips_tda6651_pll_init(u8 addr, struct dvb_frontend *fe) | |
278 | { | |
279 | struct saa7134_dev *dev = fe->dvb->priv; | |
280 | static u8 tu1216_init[] = { 0x0b, 0xf5, 0x85, 0xab }; | |
281 | struct i2c_msg tuner_msg = {.addr = addr,.flags = 0,.buf = tu1216_init,.len = sizeof(tu1216_init) }; | |
86ddd96f | 282 | |
2cf36ac4 | 283 | /* setup PLL configuration */ |
dea74869 PB |
284 | if (fe->ops.i2c_gate_ctrl) |
285 | fe->ops.i2c_gate_ctrl(fe, 1); | |
2cf36ac4 HH |
286 | if (i2c_transfer(&dev->i2c_adap, &tuner_msg, 1) != 1) |
287 | return -EIO; | |
86ddd96f | 288 | msleep(1); |
2cf36ac4 | 289 | |
1da177e4 LT |
290 | return 0; |
291 | } | |
292 | ||
2cf36ac4 HH |
293 | /* ------------------------------------------------------------------ */ |
294 | ||
a79ddae9 | 295 | static int philips_tu1216_tuner_60_init(struct dvb_frontend *fe) |
2cf36ac4 HH |
296 | { |
297 | return philips_tda6651_pll_init(0x60, fe); | |
298 | } | |
299 | ||
a79ddae9 | 300 | static int philips_tu1216_tuner_60_set_params(struct dvb_frontend *fe, struct dvb_frontend_parameters *params) |
2cf36ac4 HH |
301 | { |
302 | return philips_tda6651_pll_set(0x60, fe, params); | |
303 | } | |
304 | ||
86ddd96f MCC |
305 | static int philips_tu1216_request_firmware(struct dvb_frontend *fe, |
306 | const struct firmware **fw, char *name) | |
1da177e4 LT |
307 | { |
308 | struct saa7134_dev *dev = fe->dvb->priv; | |
309 | return request_firmware(fw, name, &dev->pci->dev); | |
310 | } | |
311 | ||
2cf36ac4 | 312 | static struct tda1004x_config philips_tu1216_60_config = { |
86ddd96f MCC |
313 | |
314 | .demod_address = 0x8, | |
315 | .invert = 1, | |
2cf36ac4 | 316 | .invert_oclk = 0, |
86ddd96f MCC |
317 | .xtal_freq = TDA10046_XTAL_4M, |
318 | .agc_config = TDA10046_AGC_DEFAULT, | |
319 | .if_freq = TDA10046_FREQ_3617, | |
86ddd96f MCC |
320 | .request_firmware = philips_tu1216_request_firmware, |
321 | }; | |
322 | ||
323 | /* ------------------------------------------------------------------ */ | |
324 | ||
a79ddae9 | 325 | static int philips_tu1216_tuner_61_init(struct dvb_frontend *fe) |
2cf36ac4 HH |
326 | { |
327 | return philips_tda6651_pll_init(0x61, fe); | |
328 | } | |
329 | ||
a79ddae9 | 330 | static int philips_tu1216_tuner_61_set_params(struct dvb_frontend *fe, struct dvb_frontend_parameters *params) |
2cf36ac4 HH |
331 | { |
332 | return philips_tda6651_pll_set(0x61, fe, params); | |
333 | } | |
334 | ||
335 | static struct tda1004x_config philips_tu1216_61_config = { | |
336 | ||
337 | .demod_address = 0x8, | |
338 | .invert = 1, | |
339 | .invert_oclk = 0, | |
340 | .xtal_freq = TDA10046_XTAL_4M, | |
341 | .agc_config = TDA10046_AGC_DEFAULT, | |
342 | .if_freq = TDA10046_FREQ_3617, | |
2cf36ac4 HH |
343 | .request_firmware = philips_tu1216_request_firmware, |
344 | }; | |
345 | ||
346 | /* ------------------------------------------------------------------ */ | |
347 | ||
a79ddae9 | 348 | static int philips_europa_tuner_init(struct dvb_frontend *fe) |
2cf36ac4 HH |
349 | { |
350 | struct saa7134_dev *dev = fe->dvb->priv; | |
351 | static u8 msg[] = { 0x0b, 0xf5, 0x86, 0xab }; | |
352 | struct i2c_msg init_msg = {.addr = 0x61,.flags = 0,.buf = msg,.len = sizeof(msg) }; | |
353 | ||
354 | /* setup PLL configuration */ | |
dea74869 PB |
355 | if (fe->ops.i2c_gate_ctrl) |
356 | fe->ops.i2c_gate_ctrl(fe, 1); | |
2cf36ac4 HH |
357 | if (i2c_transfer(&dev->i2c_adap, &init_msg, 1) != 1) |
358 | return -EIO; | |
359 | msleep(1); | |
360 | ||
361 | /* switch the board to dvb mode */ | |
362 | init_msg.addr = 0x43; | |
363 | init_msg.len = 0x02; | |
364 | msg[0] = 0x00; | |
365 | msg[1] = 0x40; | |
dea74869 PB |
366 | if (fe->ops.i2c_gate_ctrl) |
367 | fe->ops.i2c_gate_ctrl(fe, 1); | |
2cf36ac4 HH |
368 | if (i2c_transfer(&dev->i2c_adap, &init_msg, 1) != 1) |
369 | return -EIO; | |
370 | ||
371 | return 0; | |
372 | } | |
373 | ||
a79ddae9 | 374 | static int philips_td1316_tuner_set_params(struct dvb_frontend *fe, struct dvb_frontend_parameters *params) |
2cf36ac4 HH |
375 | { |
376 | return philips_tda6651_pll_set(0x61, fe, params); | |
377 | } | |
378 | ||
a79ddae9 | 379 | static int philips_europa_tuner_sleep(struct dvb_frontend *fe) |
2cf36ac4 HH |
380 | { |
381 | struct saa7134_dev *dev = fe->dvb->priv; | |
382 | /* this message actually turns the tuner back to analog mode */ | |
383 | static u8 msg[] = { 0x0b, 0xdc, 0x86, 0xa4 }; | |
384 | struct i2c_msg analog_msg = {.addr = 0x61,.flags = 0,.buf = msg,.len = sizeof(msg) }; | |
385 | ||
386 | i2c_transfer(&dev->i2c_adap, &analog_msg, 1); | |
387 | msleep(1); | |
388 | ||
389 | /* switch the board to analog mode */ | |
390 | analog_msg.addr = 0x43; | |
391 | analog_msg.len = 0x02; | |
392 | msg[0] = 0x00; | |
393 | msg[1] = 0x14; | |
dea74869 PB |
394 | if (fe->ops.i2c_gate_ctrl) |
395 | fe->ops.i2c_gate_ctrl(fe, 1); | |
2cf36ac4 | 396 | i2c_transfer(&dev->i2c_adap, &analog_msg, 1); |
a79ddae9 AQ |
397 | return 0; |
398 | } | |
399 | ||
400 | static int philips_europa_demod_sleep(struct dvb_frontend *fe) | |
401 | { | |
402 | struct saa7134_dev *dev = fe->dvb->priv; | |
403 | ||
404 | if (dev->original_demod_sleep) | |
405 | dev->original_demod_sleep(fe); | |
dea74869 | 406 | fe->ops.i2c_gate_ctrl(fe, 1); |
a79ddae9 | 407 | return 0; |
2cf36ac4 HH |
408 | } |
409 | ||
410 | static struct tda1004x_config philips_europa_config = { | |
411 | ||
412 | .demod_address = 0x8, | |
413 | .invert = 0, | |
414 | .invert_oclk = 0, | |
415 | .xtal_freq = TDA10046_XTAL_4M, | |
416 | .agc_config = TDA10046_AGC_IFO_AUTO_POS, | |
417 | .if_freq = TDA10046_FREQ_052, | |
2cf36ac4 HH |
418 | .request_firmware = NULL, |
419 | }; | |
420 | ||
421 | /* ------------------------------------------------------------------ */ | |
86ddd96f | 422 | |
a79ddae9 | 423 | static int philips_fmd1216_tuner_init(struct dvb_frontend *fe) |
86ddd96f MCC |
424 | { |
425 | struct saa7134_dev *dev = fe->dvb->priv; | |
426 | /* this message is to set up ATC and ALC */ | |
427 | static u8 fmd1216_init[] = { 0x0b, 0xdc, 0x9c, 0xa0 }; | |
428 | struct i2c_msg tuner_msg = {.addr = 0x61,.flags = 0,.buf = fmd1216_init,.len = sizeof(fmd1216_init) }; | |
429 | ||
dea74869 PB |
430 | if (fe->ops.i2c_gate_ctrl) |
431 | fe->ops.i2c_gate_ctrl(fe, 1); | |
86ddd96f MCC |
432 | if (i2c_transfer(&dev->i2c_adap, &tuner_msg, 1) != 1) |
433 | return -EIO; | |
434 | msleep(1); | |
435 | ||
436 | return 0; | |
437 | } | |
438 | ||
a79ddae9 | 439 | static int philips_fmd1216_tuner_sleep(struct dvb_frontend *fe) |
86ddd96f MCC |
440 | { |
441 | struct saa7134_dev *dev = fe->dvb->priv; | |
442 | /* this message actually turns the tuner back to analog mode */ | |
443 | static u8 fmd1216_init[] = { 0x0b, 0xdc, 0x9c, 0x60 }; | |
444 | struct i2c_msg tuner_msg = {.addr = 0x61,.flags = 0,.buf = fmd1216_init,.len = sizeof(fmd1216_init) }; | |
445 | ||
dea74869 PB |
446 | if (fe->ops.i2c_gate_ctrl) |
447 | fe->ops.i2c_gate_ctrl(fe, 1); | |
86ddd96f MCC |
448 | i2c_transfer(&dev->i2c_adap, &tuner_msg, 1); |
449 | msleep(1); | |
450 | fmd1216_init[2] = 0x86; | |
451 | fmd1216_init[3] = 0x54; | |
dea74869 PB |
452 | if (fe->ops.i2c_gate_ctrl) |
453 | fe->ops.i2c_gate_ctrl(fe, 1); | |
86ddd96f MCC |
454 | i2c_transfer(&dev->i2c_adap, &tuner_msg, 1); |
455 | msleep(1); | |
a79ddae9 | 456 | return 0; |
86ddd96f MCC |
457 | } |
458 | ||
a79ddae9 | 459 | static int philips_fmd1216_tuner_set_params(struct dvb_frontend *fe, struct dvb_frontend_parameters *params) |
86ddd96f MCC |
460 | { |
461 | struct saa7134_dev *dev = fe->dvb->priv; | |
462 | u8 tuner_buf[4]; | |
463 | struct i2c_msg tuner_msg = {.addr = 0x61,.flags = 0,.buf = tuner_buf,.len = | |
464 | sizeof(tuner_buf) }; | |
465 | int tuner_frequency = 0; | |
466 | int divider = 0; | |
467 | u8 band, mode, cp; | |
468 | ||
469 | /* determine charge pump */ | |
470 | tuner_frequency = params->frequency + 36130000; | |
471 | if (tuner_frequency < 87000000) | |
472 | return -EINVAL; | |
473 | /* low band */ | |
474 | else if (tuner_frequency < 180000000) { | |
475 | band = 1; | |
476 | mode = 7; | |
477 | cp = 0; | |
478 | } else if (tuner_frequency < 195000000) { | |
479 | band = 1; | |
480 | mode = 6; | |
481 | cp = 1; | |
482 | /* mid band */ | |
483 | } else if (tuner_frequency < 366000000) { | |
484 | if (params->u.ofdm.bandwidth == BANDWIDTH_8_MHZ) { | |
485 | band = 10; | |
486 | } else { | |
487 | band = 2; | |
488 | } | |
489 | mode = 7; | |
490 | cp = 0; | |
491 | } else if (tuner_frequency < 478000000) { | |
492 | if (params->u.ofdm.bandwidth == BANDWIDTH_8_MHZ) { | |
493 | band = 10; | |
494 | } else { | |
495 | band = 2; | |
496 | } | |
497 | mode = 6; | |
498 | cp = 1; | |
499 | /* high band */ | |
500 | } else if (tuner_frequency < 662000000) { | |
501 | if (params->u.ofdm.bandwidth == BANDWIDTH_8_MHZ) { | |
502 | band = 12; | |
503 | } else { | |
504 | band = 4; | |
505 | } | |
506 | mode = 7; | |
507 | cp = 0; | |
508 | } else if (tuner_frequency < 840000000) { | |
509 | if (params->u.ofdm.bandwidth == BANDWIDTH_8_MHZ) { | |
510 | band = 12; | |
511 | } else { | |
512 | band = 4; | |
513 | } | |
514 | mode = 6; | |
515 | cp = 1; | |
516 | } else { | |
517 | if (params->u.ofdm.bandwidth == BANDWIDTH_8_MHZ) { | |
518 | band = 12; | |
519 | } else { | |
520 | band = 4; | |
521 | } | |
522 | mode = 7; | |
523 | cp = 1; | |
524 | ||
525 | } | |
526 | /* calculate divisor */ | |
527 | /* ((36166000 + Finput) / 166666) rounded! */ | |
528 | divider = (tuner_frequency + 83333) / 166667; | |
529 | ||
530 | /* setup tuner buffer */ | |
531 | tuner_buf[0] = (divider >> 8) & 0x7f; | |
532 | tuner_buf[1] = divider & 0xff; | |
533 | tuner_buf[2] = 0x80 | (cp << 6) | (mode << 3) | 4; | |
534 | tuner_buf[3] = 0x40 | band; | |
535 | ||
dea74869 PB |
536 | if (fe->ops.i2c_gate_ctrl) |
537 | fe->ops.i2c_gate_ctrl(fe, 1); | |
86ddd96f MCC |
538 | if (i2c_transfer(&dev->i2c_adap, &tuner_msg, 1) != 1) |
539 | return -EIO; | |
540 | return 0; | |
541 | } | |
542 | ||
408b664a | 543 | static struct tda1004x_config medion_cardbus = { |
86ddd96f MCC |
544 | .demod_address = 0x08, |
545 | .invert = 1, | |
546 | .invert_oclk = 0, | |
547 | .xtal_freq = TDA10046_XTAL_16M, | |
548 | .agc_config = TDA10046_AGC_IFO_AUTO_NEG, | |
549 | .if_freq = TDA10046_FREQ_3613, | |
86ddd96f MCC |
550 | .request_firmware = NULL, |
551 | }; | |
552 | ||
553 | /* ------------------------------------------------------------------ */ | |
554 | ||
555 | struct tda827x_data { | |
556 | u32 lomax; | |
557 | u8 spd; | |
558 | u8 bs; | |
559 | u8 bp; | |
560 | u8 cp; | |
561 | u8 gc3; | |
562 | u8 div1p5; | |
563 | }; | |
564 | ||
565 | static struct tda827x_data tda827x_dvbt[] = { | |
566 | { .lomax = 62000000, .spd = 3, .bs = 2, .bp = 0, .cp = 0, .gc3 = 3, .div1p5 = 1}, | |
567 | { .lomax = 66000000, .spd = 3, .bs = 3, .bp = 0, .cp = 0, .gc3 = 3, .div1p5 = 1}, | |
568 | { .lomax = 76000000, .spd = 3, .bs = 1, .bp = 0, .cp = 0, .gc3 = 3, .div1p5 = 0}, | |
569 | { .lomax = 84000000, .spd = 3, .bs = 2, .bp = 0, .cp = 0, .gc3 = 3, .div1p5 = 0}, | |
570 | { .lomax = 93000000, .spd = 3, .bs = 2, .bp = 0, .cp = 0, .gc3 = 1, .div1p5 = 0}, | |
571 | { .lomax = 98000000, .spd = 3, .bs = 3, .bp = 0, .cp = 0, .gc3 = 1, .div1p5 = 0}, | |
572 | { .lomax = 109000000, .spd = 3, .bs = 3, .bp = 1, .cp = 0, .gc3 = 1, .div1p5 = 0}, | |
573 | { .lomax = 123000000, .spd = 2, .bs = 2, .bp = 1, .cp = 0, .gc3 = 1, .div1p5 = 1}, | |
574 | { .lomax = 133000000, .spd = 2, .bs = 3, .bp = 1, .cp = 0, .gc3 = 1, .div1p5 = 1}, | |
575 | { .lomax = 151000000, .spd = 2, .bs = 1, .bp = 1, .cp = 0, .gc3 = 1, .div1p5 = 0}, | |
576 | { .lomax = 154000000, .spd = 2, .bs = 2, .bp = 1, .cp = 0, .gc3 = 1, .div1p5 = 0}, | |
577 | { .lomax = 181000000, .spd = 2, .bs = 2, .bp = 1, .cp = 0, .gc3 = 0, .div1p5 = 0}, | |
578 | { .lomax = 185000000, .spd = 2, .bs = 2, .bp = 2, .cp = 0, .gc3 = 1, .div1p5 = 0}, | |
579 | { .lomax = 217000000, .spd = 2, .bs = 3, .bp = 2, .cp = 0, .gc3 = 1, .div1p5 = 0}, | |
580 | { .lomax = 244000000, .spd = 1, .bs = 2, .bp = 2, .cp = 0, .gc3 = 1, .div1p5 = 1}, | |
581 | { .lomax = 265000000, .spd = 1, .bs = 3, .bp = 2, .cp = 0, .gc3 = 1, .div1p5 = 1}, | |
582 | { .lomax = 302000000, .spd = 1, .bs = 1, .bp = 2, .cp = 0, .gc3 = 1, .div1p5 = 0}, | |
583 | { .lomax = 324000000, .spd = 1, .bs = 2, .bp = 2, .cp = 0, .gc3 = 1, .div1p5 = 0}, | |
584 | { .lomax = 370000000, .spd = 1, .bs = 2, .bp = 3, .cp = 0, .gc3 = 1, .div1p5 = 0}, | |
585 | { .lomax = 454000000, .spd = 1, .bs = 3, .bp = 3, .cp = 0, .gc3 = 1, .div1p5 = 0}, | |
586 | { .lomax = 493000000, .spd = 0, .bs = 2, .bp = 3, .cp = 0, .gc3 = 1, .div1p5 = 1}, | |
587 | { .lomax = 530000000, .spd = 0, .bs = 3, .bp = 3, .cp = 0, .gc3 = 1, .div1p5 = 1}, | |
588 | { .lomax = 554000000, .spd = 0, .bs = 1, .bp = 3, .cp = 0, .gc3 = 1, .div1p5 = 0}, | |
589 | { .lomax = 604000000, .spd = 0, .bs = 1, .bp = 4, .cp = 0, .gc3 = 0, .div1p5 = 0}, | |
590 | { .lomax = 696000000, .spd = 0, .bs = 2, .bp = 4, .cp = 0, .gc3 = 0, .div1p5 = 0}, | |
591 | { .lomax = 740000000, .spd = 0, .bs = 2, .bp = 4, .cp = 1, .gc3 = 0, .div1p5 = 0}, | |
592 | { .lomax = 820000000, .spd = 0, .bs = 3, .bp = 4, .cp = 0, .gc3 = 0, .div1p5 = 0}, | |
593 | { .lomax = 865000000, .spd = 0, .bs = 3, .bp = 4, .cp = 1, .gc3 = 0, .div1p5 = 0}, | |
594 | { .lomax = 0, .spd = 0, .bs = 0, .bp = 0, .cp = 0, .gc3 = 0, .div1p5 = 0} | |
595 | }; | |
596 | ||
a79ddae9 | 597 | static int philips_tda827x_tuner_init(struct dvb_frontend *fe) |
86ddd96f MCC |
598 | { |
599 | return 0; | |
600 | } | |
601 | ||
a79ddae9 | 602 | static int philips_tda827x_tuner_set_params(struct dvb_frontend *fe, struct dvb_frontend_parameters *params) |
86ddd96f MCC |
603 | { |
604 | struct saa7134_dev *dev = fe->dvb->priv; | |
605 | u8 tuner_buf[14]; | |
606 | ||
607 | struct i2c_msg tuner_msg = {.addr = 0x60,.flags = 0,.buf = tuner_buf, | |
f2421ca3 | 608 | .len = sizeof(tuner_buf) }; |
86ddd96f MCC |
609 | int i, tuner_freq, if_freq; |
610 | u32 N; | |
611 | switch (params->u.ofdm.bandwidth) { | |
612 | case BANDWIDTH_6_MHZ: | |
613 | if_freq = 4000000; | |
614 | break; | |
615 | case BANDWIDTH_7_MHZ: | |
616 | if_freq = 4500000; | |
617 | break; | |
618 | default: /* 8 MHz or Auto */ | |
619 | if_freq = 5000000; | |
620 | break; | |
621 | } | |
622 | tuner_freq = params->frequency + if_freq; | |
623 | ||
624 | i = 0; | |
625 | while (tda827x_dvbt[i].lomax < tuner_freq) { | |
626 | if(tda827x_dvbt[i + 1].lomax == 0) | |
627 | break; | |
628 | i++; | |
629 | } | |
630 | ||
631 | N = ((tuner_freq + 125000) / 250000) << (tda827x_dvbt[i].spd + 2); | |
632 | tuner_buf[0] = 0; | |
633 | tuner_buf[1] = (N>>8) | 0x40; | |
634 | tuner_buf[2] = N & 0xff; | |
635 | tuner_buf[3] = 0; | |
636 | tuner_buf[4] = 0x52; | |
637 | tuner_buf[5] = (tda827x_dvbt[i].spd << 6) + (tda827x_dvbt[i].div1p5 << 5) + | |
638 | (tda827x_dvbt[i].bs << 3) + tda827x_dvbt[i].bp; | |
639 | tuner_buf[6] = (tda827x_dvbt[i].gc3 << 4) + 0x8f; | |
640 | tuner_buf[7] = 0xbf; | |
641 | tuner_buf[8] = 0x2a; | |
642 | tuner_buf[9] = 0x05; | |
643 | tuner_buf[10] = 0xff; | |
644 | tuner_buf[11] = 0x00; | |
645 | tuner_buf[12] = 0x00; | |
646 | tuner_buf[13] = 0x40; | |
647 | ||
648 | tuner_msg.len = 14; | |
dea74869 PB |
649 | if (fe->ops.i2c_gate_ctrl) |
650 | fe->ops.i2c_gate_ctrl(fe, 1); | |
86ddd96f MCC |
651 | if (i2c_transfer(&dev->i2c_adap, &tuner_msg, 1) != 1) |
652 | return -EIO; | |
653 | ||
654 | msleep(500); | |
655 | /* correct CP value */ | |
656 | tuner_buf[0] = 0x30; | |
657 | tuner_buf[1] = 0x50 + tda827x_dvbt[i].cp; | |
658 | tuner_msg.len = 2; | |
dea74869 PB |
659 | if (fe->ops.i2c_gate_ctrl) |
660 | fe->ops.i2c_gate_ctrl(fe, 1); | |
86ddd96f MCC |
661 | i2c_transfer(&dev->i2c_adap, &tuner_msg, 1); |
662 | ||
663 | return 0; | |
664 | } | |
665 | ||
a79ddae9 | 666 | static int philips_tda827x_tuner_sleep(struct dvb_frontend *fe) |
86ddd96f MCC |
667 | { |
668 | struct saa7134_dev *dev = fe->dvb->priv; | |
669 | static u8 tda827x_sleep[] = { 0x30, 0xd0}; | |
670 | struct i2c_msg tuner_msg = {.addr = 0x60,.flags = 0,.buf = tda827x_sleep, | |
f2421ca3 | 671 | .len = sizeof(tda827x_sleep) }; |
dea74869 PB |
672 | if (fe->ops.i2c_gate_ctrl) |
673 | fe->ops.i2c_gate_ctrl(fe, 1); | |
86ddd96f | 674 | i2c_transfer(&dev->i2c_adap, &tuner_msg, 1); |
a79ddae9 | 675 | return 0; |
86ddd96f MCC |
676 | } |
677 | ||
678 | static struct tda1004x_config tda827x_lifeview_config = { | |
679 | .demod_address = 0x08, | |
680 | .invert = 1, | |
681 | .invert_oclk = 0, | |
682 | .xtal_freq = TDA10046_XTAL_16M, | |
683 | .agc_config = TDA10046_AGC_TDA827X, | |
684 | .if_freq = TDA10046_FREQ_045, | |
86ddd96f | 685 | .request_firmware = NULL, |
1da177e4 | 686 | }; |
90e9df7f HH |
687 | |
688 | /* ------------------------------------------------------------------ */ | |
689 | ||
690 | struct tda827xa_data { | |
691 | u32 lomax; | |
692 | u8 svco; | |
693 | u8 spd; | |
694 | u8 scr; | |
695 | u8 sbs; | |
696 | u8 gc3; | |
697 | }; | |
698 | ||
699 | static struct tda827xa_data tda827xa_dvbt[] = { | |
700 | { .lomax = 56875000, .svco = 3, .spd = 4, .scr = 0, .sbs = 0, .gc3 = 1}, | |
701 | { .lomax = 67250000, .svco = 0, .spd = 3, .scr = 0, .sbs = 0, .gc3 = 1}, | |
702 | { .lomax = 81250000, .svco = 1, .spd = 3, .scr = 0, .sbs = 0, .gc3 = 1}, | |
703 | { .lomax = 97500000, .svco = 2, .spd = 3, .scr = 0, .sbs = 0, .gc3 = 1}, | |
704 | { .lomax = 113750000, .svco = 3, .spd = 3, .scr = 0, .sbs = 1, .gc3 = 1}, | |
705 | { .lomax = 134500000, .svco = 0, .spd = 2, .scr = 0, .sbs = 1, .gc3 = 1}, | |
706 | { .lomax = 154000000, .svco = 1, .spd = 2, .scr = 0, .sbs = 1, .gc3 = 1}, | |
707 | { .lomax = 162500000, .svco = 1, .spd = 2, .scr = 0, .sbs = 1, .gc3 = 1}, | |
708 | { .lomax = 183000000, .svco = 2, .spd = 2, .scr = 0, .sbs = 1, .gc3 = 1}, | |
709 | { .lomax = 195000000, .svco = 2, .spd = 2, .scr = 0, .sbs = 2, .gc3 = 1}, | |
710 | { .lomax = 227500000, .svco = 3, .spd = 2, .scr = 0, .sbs = 2, .gc3 = 1}, | |
711 | { .lomax = 269000000, .svco = 0, .spd = 1, .scr = 0, .sbs = 2, .gc3 = 1}, | |
712 | { .lomax = 290000000, .svco = 1, .spd = 1, .scr = 0, .sbs = 2, .gc3 = 1}, | |
713 | { .lomax = 325000000, .svco = 1, .spd = 1, .scr = 0, .sbs = 3, .gc3 = 1}, | |
714 | { .lomax = 390000000, .svco = 2, .spd = 1, .scr = 0, .sbs = 3, .gc3 = 1}, | |
715 | { .lomax = 455000000, .svco = 3, .spd = 1, .scr = 0, .sbs = 3, .gc3 = 1}, | |
716 | { .lomax = 520000000, .svco = 0, .spd = 0, .scr = 0, .sbs = 3, .gc3 = 1}, | |
717 | { .lomax = 538000000, .svco = 0, .spd = 0, .scr = 1, .sbs = 3, .gc3 = 1}, | |
718 | { .lomax = 550000000, .svco = 1, .spd = 0, .scr = 0, .sbs = 3, .gc3 = 1}, | |
719 | { .lomax = 620000000, .svco = 1, .spd = 0, .scr = 0, .sbs = 4, .gc3 = 0}, | |
720 | { .lomax = 650000000, .svco = 1, .spd = 0, .scr = 1, .sbs = 4, .gc3 = 0}, | |
721 | { .lomax = 700000000, .svco = 2, .spd = 0, .scr = 0, .sbs = 4, .gc3 = 0}, | |
722 | { .lomax = 780000000, .svco = 2, .spd = 0, .scr = 1, .sbs = 4, .gc3 = 0}, | |
723 | { .lomax = 820000000, .svco = 3, .spd = 0, .scr = 0, .sbs = 4, .gc3 = 0}, | |
724 | { .lomax = 870000000, .svco = 3, .spd = 0, .scr = 1, .sbs = 4, .gc3 = 0}, | |
725 | { .lomax = 911000000, .svco = 3, .spd = 0, .scr = 2, .sbs = 4, .gc3 = 0}, | |
726 | { .lomax = 0, .svco = 0, .spd = 0, .scr = 0, .sbs = 0, .gc3 = 0}}; | |
727 | ||
728 | ||
729 | static int philips_tda827xa_pll_set(u8 addr, struct dvb_frontend *fe, struct dvb_frontend_parameters *params) | |
730 | { | |
731 | struct saa7134_dev *dev = fe->dvb->priv; | |
732 | u8 tuner_buf[14]; | |
733 | unsigned char reg2[2]; | |
734 | ||
735 | struct i2c_msg msg = {.addr = addr,.flags = 0,.buf = tuner_buf}; | |
736 | int i, tuner_freq, if_freq; | |
737 | u32 N; | |
738 | ||
739 | switch (params->u.ofdm.bandwidth) { | |
740 | case BANDWIDTH_6_MHZ: | |
741 | if_freq = 4000000; | |
742 | break; | |
743 | case BANDWIDTH_7_MHZ: | |
744 | if_freq = 4500000; | |
745 | break; | |
746 | default: /* 8 MHz or Auto */ | |
747 | if_freq = 5000000; | |
748 | break; | |
749 | } | |
750 | tuner_freq = params->frequency + if_freq; | |
751 | ||
752 | i = 0; | |
753 | while (tda827xa_dvbt[i].lomax < tuner_freq) { | |
754 | if(tda827xa_dvbt[i + 1].lomax == 0) | |
755 | break; | |
756 | i++; | |
757 | } | |
758 | ||
759 | N = ((tuner_freq + 31250) / 62500) << tda827xa_dvbt[i].spd; | |
760 | tuner_buf[0] = 0; // subaddress | |
761 | tuner_buf[1] = N >> 8; | |
762 | tuner_buf[2] = N & 0xff; | |
763 | tuner_buf[3] = 0; | |
764 | tuner_buf[4] = 0x16; | |
765 | tuner_buf[5] = (tda827xa_dvbt[i].spd << 5) + (tda827xa_dvbt[i].svco << 3) + | |
766 | tda827xa_dvbt[i].sbs; | |
767 | tuner_buf[6] = 0x4b + (tda827xa_dvbt[i].gc3 << 4); | |
768 | tuner_buf[7] = 0x0c; | |
769 | tuner_buf[8] = 0x06; | |
770 | tuner_buf[9] = 0x24; | |
771 | tuner_buf[10] = 0xff; | |
772 | tuner_buf[11] = 0x60; | |
773 | tuner_buf[12] = 0x00; | |
774 | tuner_buf[13] = 0x39; // lpsel | |
775 | msg.len = 14; | |
dea74869 PB |
776 | if (fe->ops.i2c_gate_ctrl) |
777 | fe->ops.i2c_gate_ctrl(fe, 1); | |
90e9df7f HH |
778 | if (i2c_transfer(&dev->i2c_adap, &msg, 1) != 1) |
779 | return -EIO; | |
780 | ||
781 | msg.buf= reg2; | |
782 | msg.len = 2; | |
783 | reg2[0] = 0x60; | |
784 | reg2[1] = 0x3c; | |
dea74869 PB |
785 | if (fe->ops.i2c_gate_ctrl) |
786 | fe->ops.i2c_gate_ctrl(fe, 1); | |
90e9df7f HH |
787 | i2c_transfer(&dev->i2c_adap, &msg, 1); |
788 | ||
789 | reg2[0] = 0xa0; | |
790 | reg2[1] = 0x40; | |
dea74869 PB |
791 | if (fe->ops.i2c_gate_ctrl) |
792 | fe->ops.i2c_gate_ctrl(fe, 1); | |
90e9df7f HH |
793 | i2c_transfer(&dev->i2c_adap, &msg, 1); |
794 | ||
795 | msleep(2); | |
796 | /* correct CP value */ | |
797 | reg2[0] = 0x30; | |
798 | reg2[1] = 0x10 + tda827xa_dvbt[i].scr; | |
799 | msg.len = 2; | |
dea74869 PB |
800 | if (fe->ops.i2c_gate_ctrl) |
801 | fe->ops.i2c_gate_ctrl(fe, 1); | |
90e9df7f HH |
802 | i2c_transfer(&dev->i2c_adap, &msg, 1); |
803 | ||
804 | msleep(550); | |
805 | reg2[0] = 0x50; | |
806 | reg2[1] = 0x4f + (tda827xa_dvbt[i].gc3 << 4); | |
dea74869 PB |
807 | if (fe->ops.i2c_gate_ctrl) |
808 | fe->ops.i2c_gate_ctrl(fe, 1); | |
90e9df7f HH |
809 | i2c_transfer(&dev->i2c_adap, &msg, 1); |
810 | ||
811 | return 0; | |
812 | ||
813 | } | |
814 | ||
a79ddae9 | 815 | static int philips_tda827xa_tuner_sleep(u8 addr, struct dvb_frontend *fe) |
90e9df7f HH |
816 | { |
817 | struct saa7134_dev *dev = fe->dvb->priv; | |
818 | static u8 tda827xa_sleep[] = { 0x30, 0x90}; | |
819 | struct i2c_msg tuner_msg = {.addr = addr,.flags = 0,.buf = tda827xa_sleep, | |
f1bcef88 | 820 | .len = sizeof(tda827xa_sleep) }; |
dea74869 PB |
821 | if (fe->ops.i2c_gate_ctrl) |
822 | fe->ops.i2c_gate_ctrl(fe, 1); | |
90e9df7f | 823 | i2c_transfer(&dev->i2c_adap, &tuner_msg, 1); |
a79ddae9 | 824 | return 0; |
90e9df7f HH |
825 | } |
826 | ||
827 | /* ------------------------------------------------------------------ */ | |
828 | ||
a79ddae9 | 829 | static int philips_tiger_tuner_set_params(struct dvb_frontend *fe, struct dvb_frontend_parameters *params) |
90e9df7f HH |
830 | { |
831 | int ret; | |
832 | struct saa7134_dev *dev = fe->dvb->priv; | |
833 | static u8 tda8290_close[] = { 0x21, 0xc0}; | |
834 | static u8 tda8290_open[] = { 0x21, 0x80}; | |
835 | struct i2c_msg tda8290_msg = {.addr = 0x4b,.flags = 0, .len = 2}; | |
a79ddae9 | 836 | |
90e9df7f HH |
837 | /* close tda8290 i2c bridge */ |
838 | tda8290_msg.buf = tda8290_close; | |
839 | ret = i2c_transfer(&dev->i2c_adap, &tda8290_msg, 1); | |
840 | if (ret != 1) | |
841 | return -EIO; | |
842 | msleep(20); | |
843 | ret = philips_tda827xa_pll_set(0x61, fe, params); | |
844 | if (ret != 0) | |
845 | return ret; | |
846 | /* open tda8290 i2c bridge */ | |
847 | tda8290_msg.buf = tda8290_open; | |
848 | i2c_transfer(&dev->i2c_adap, &tda8290_msg, 1); | |
849 | return ret; | |
2d6b5f62 | 850 | } |
90e9df7f | 851 | |
a79ddae9 | 852 | static int philips_tiger_tuner_init(struct dvb_frontend *fe) |
90e9df7f HH |
853 | { |
854 | struct saa7134_dev *dev = fe->dvb->priv; | |
855 | static u8 data[] = { 0x3c, 0x33, 0x6a}; | |
856 | struct i2c_msg msg = {.addr=0x08, .flags=0, .buf=data, .len = sizeof(data)}; | |
857 | ||
858 | if (i2c_transfer(&dev->i2c_adap, &msg, 1) != 1) | |
859 | return -EIO; | |
860 | return 0; | |
861 | } | |
862 | ||
a79ddae9 | 863 | static int philips_tiger_tuner_sleep(struct dvb_frontend *fe) |
90e9df7f HH |
864 | { |
865 | struct saa7134_dev *dev = fe->dvb->priv; | |
866 | static u8 data[] = { 0x3c, 0x33, 0x68}; | |
867 | struct i2c_msg msg = {.addr=0x08, .flags=0, .buf=data, .len = sizeof(data)}; | |
868 | ||
869 | i2c_transfer(&dev->i2c_adap, &msg, 1); | |
a79ddae9 AQ |
870 | philips_tda827xa_tuner_sleep( 0x61, fe); |
871 | return 0; | |
90e9df7f HH |
872 | } |
873 | ||
874 | static struct tda1004x_config philips_tiger_config = { | |
875 | .demod_address = 0x08, | |
876 | .invert = 1, | |
877 | .invert_oclk = 0, | |
878 | .xtal_freq = TDA10046_XTAL_16M, | |
879 | .agc_config = TDA10046_AGC_TDA827X, | |
880 | .if_freq = TDA10046_FREQ_045, | |
90e9df7f HH |
881 | .request_firmware = NULL, |
882 | }; | |
883 | ||
df42eaf2 HH |
884 | /* ------------------------------------------------------------------ */ |
885 | ||
a79ddae9 | 886 | static int lifeview_trio_tuner_set_params(struct dvb_frontend *fe, struct dvb_frontend_parameters *params) |
420f32fe NS |
887 | { |
888 | int ret; | |
889 | ||
890 | ret = philips_tda827xa_pll_set(0x60, fe, params); | |
891 | return ret; | |
892 | } | |
893 | ||
a79ddae9 | 894 | static int lifeview_trio_tuner_sleep(struct dvb_frontend *fe) |
420f32fe | 895 | { |
a79ddae9 | 896 | philips_tda827xa_tuner_sleep(0x60, fe); |
420f32fe NS |
897 | return 0; |
898 | } | |
899 | ||
420f32fe NS |
900 | static struct tda1004x_config lifeview_trio_config = { |
901 | .demod_address = 0x09, | |
902 | .invert = 1, | |
903 | .invert_oclk = 0, | |
904 | .xtal_freq = TDA10046_XTAL_16M, | |
905 | .agc_config = TDA10046_AGC_TDA827X_GPL, | |
906 | .if_freq = TDA10046_FREQ_045, | |
420f32fe NS |
907 | .request_firmware = NULL, |
908 | }; | |
909 | ||
910 | /* ------------------------------------------------------------------ */ | |
911 | ||
a79ddae9 | 912 | static int ads_duo_tuner_set_params(struct dvb_frontend *fe, struct dvb_frontend_parameters *params) |
df42eaf2 HH |
913 | { |
914 | int ret; | |
915 | ||
916 | ret = philips_tda827xa_pll_set(0x61, fe, params); | |
917 | return ret; | |
2d6b5f62 | 918 | } |
df42eaf2 | 919 | |
a79ddae9 | 920 | static int ads_duo_tuner_init(struct dvb_frontend *fe) |
df42eaf2 HH |
921 | { |
922 | struct saa7134_dev *dev = fe->dvb->priv; | |
923 | /* route TDA8275a AGC input to the channel decoder */ | |
924 | saa_writeb(SAA7134_GPIO_GPSTATUS2, 0x60); | |
925 | return 0; | |
926 | } | |
927 | ||
a79ddae9 | 928 | static int ads_duo_tuner_sleep(struct dvb_frontend *fe) |
df42eaf2 HH |
929 | { |
930 | struct saa7134_dev *dev = fe->dvb->priv; | |
931 | /* route TDA8275a AGC input to the analog IF chip*/ | |
932 | saa_writeb(SAA7134_GPIO_GPSTATUS2, 0x20); | |
a79ddae9 AQ |
933 | philips_tda827xa_tuner_sleep( 0x61, fe); |
934 | return 0; | |
df42eaf2 HH |
935 | } |
936 | ||
937 | static struct tda1004x_config ads_tech_duo_config = { | |
938 | .demod_address = 0x08, | |
939 | .invert = 1, | |
940 | .invert_oclk = 0, | |
941 | .xtal_freq = TDA10046_XTAL_16M, | |
942 | .agc_config = TDA10046_AGC_TDA827X_GPL, | |
943 | .if_freq = TDA10046_FREQ_045, | |
df42eaf2 HH |
944 | .request_firmware = NULL, |
945 | }; | |
946 | ||
3dfb729f PH |
947 | /* ------------------------------------------------------------------ */ |
948 | ||
a79ddae9 | 949 | static int tevion_dvb220rf_tuner_set_params(struct dvb_frontend *fe, struct dvb_frontend_parameters *params) |
3dfb729f PH |
950 | { |
951 | int ret; | |
952 | ret = philips_tda827xa_pll_set(0x60, fe, params); | |
953 | return ret; | |
954 | } | |
955 | ||
a79ddae9 | 956 | static int tevion_dvb220rf_tuner_sleep(struct dvb_frontend *fe) |
3dfb729f | 957 | { |
a79ddae9 | 958 | philips_tda827xa_tuner_sleep( 0x61, fe); |
3dfb729f PH |
959 | return 0; |
960 | } | |
961 | ||
3dfb729f PH |
962 | static struct tda1004x_config tevion_dvbt220rf_config = { |
963 | .demod_address = 0x08, | |
964 | .invert = 1, | |
965 | .invert_oclk = 0, | |
966 | .xtal_freq = TDA10046_XTAL_16M, | |
967 | .agc_config = TDA10046_AGC_TDA827X, | |
968 | .if_freq = TDA10046_FREQ_045, | |
3dfb729f PH |
969 | .request_firmware = NULL, |
970 | }; | |
971 | ||
86ddd96f | 972 | #endif |
1da177e4 | 973 | |
90e9df7f HH |
974 | /* ------------------------------------------------------------------ */ |
975 | ||
3b64e8e2 MK |
976 | #ifdef HAVE_NXT200X |
977 | static struct nxt200x_config avertvhda180 = { | |
978 | .demod_address = 0x0a, | |
3b64e8e2 | 979 | }; |
3e1410ad | 980 | |
fbc81c07 CM |
981 | static int nxt200x_set_pll_input(u8 *buf, int input) |
982 | { | |
983 | if (input) | |
984 | buf[3] |= 0x08; | |
985 | else | |
986 | buf[3] &= ~0x08; | |
987 | return 0; | |
988 | } | |
989 | ||
3e1410ad AB |
990 | static struct nxt200x_config kworldatsc110 = { |
991 | .demod_address = 0x0a, | |
fbc81c07 | 992 | .set_pll_input = nxt200x_set_pll_input, |
3e1410ad | 993 | }; |
3b64e8e2 MK |
994 | #endif |
995 | ||
1da177e4 LT |
996 | /* ------------------------------------------------------------------ */ |
997 | ||
998 | static int dvb_init(struct saa7134_dev *dev) | |
999 | { | |
1000 | /* init struct videobuf_dvb */ | |
1001 | dev->ts.nr_bufs = 32; | |
1002 | dev->ts.nr_packets = 32*4; | |
1003 | dev->dvb.name = dev->name; | |
1004 | videobuf_queue_init(&dev->dvb.dvbq, &saa7134_ts_qops, | |
1005 | dev->pci, &dev->slock, | |
1006 | V4L2_BUF_TYPE_VIDEO_CAPTURE, | |
1007 | V4L2_FIELD_ALTERNATE, | |
1008 | sizeof(struct saa7134_buf), | |
1009 | dev); | |
1010 | ||
1011 | switch (dev->board) { | |
29780bb7 | 1012 | #ifdef HAVE_MT352 |
1da177e4 LT |
1013 | case SAA7134_BOARD_PINNACLE_300I_DVBT_PAL: |
1014 | printk("%s: pinnacle 300i dvb setup\n",dev->name); | |
1015 | dev->dvb.frontend = mt352_attach(&pinnacle_300i, | |
1016 | &dev->i2c_adap); | |
6b3ccab7 | 1017 | if (dev->dvb.frontend) { |
dea74869 | 1018 | dev->dvb.frontend->ops.tuner_ops.set_params = mt352_pinnacle_tuner_set_params; |
6b3ccab7 | 1019 | } |
1da177e4 | 1020 | break; |
a78d0bfa JAR |
1021 | |
1022 | case SAA7134_BOARD_AVERMEDIA_777: | |
1023 | printk("%s: avertv 777 dvb setup\n",dev->name); | |
1024 | dev->dvb.frontend = mt352_attach(&avermedia_777, | |
1025 | &dev->i2c_adap); | |
6b3ccab7 | 1026 | if (dev->dvb.frontend) { |
dea74869 | 1027 | dev->dvb.frontend->ops.tuner_ops.calc_regs = mt352_aver777_tuner_calc_regs; |
6b3ccab7 | 1028 | } |
a78d0bfa | 1029 | break; |
86ddd96f | 1030 | #endif |
29780bb7 | 1031 | #ifdef HAVE_TDA1004X |
1da177e4 LT |
1032 | case SAA7134_BOARD_MD7134: |
1033 | dev->dvb.frontend = tda10046_attach(&medion_cardbus, | |
1034 | &dev->i2c_adap); | |
6b3ccab7 | 1035 | if (dev->dvb.frontend) { |
dea74869 PB |
1036 | dev->dvb.frontend->ops.tuner_ops.init = philips_fmd1216_tuner_init; |
1037 | dev->dvb.frontend->ops.tuner_ops.sleep = philips_fmd1216_tuner_sleep; | |
1038 | dev->dvb.frontend->ops.tuner_ops.set_params = philips_fmd1216_tuner_set_params; | |
6b3ccab7 | 1039 | } |
1da177e4 | 1040 | break; |
86ddd96f | 1041 | case SAA7134_BOARD_PHILIPS_TOUGH: |
2cf36ac4 | 1042 | dev->dvb.frontend = tda10046_attach(&philips_tu1216_60_config, |
86ddd96f | 1043 | &dev->i2c_adap); |
6b3ccab7 | 1044 | if (dev->dvb.frontend) { |
dea74869 PB |
1045 | dev->dvb.frontend->ops.tuner_ops.init = philips_tu1216_tuner_60_init; |
1046 | dev->dvb.frontend->ops.tuner_ops.set_params = philips_tu1216_tuner_60_set_params; | |
6b3ccab7 | 1047 | } |
86ddd96f MCC |
1048 | break; |
1049 | case SAA7134_BOARD_FLYDVBTDUO: | |
1050 | dev->dvb.frontend = tda10046_attach(&tda827x_lifeview_config, | |
1051 | &dev->i2c_adap); | |
6b3ccab7 | 1052 | if (dev->dvb.frontend) { |
dea74869 PB |
1053 | dev->dvb.frontend->ops.tuner_ops.init = philips_tda827x_tuner_init; |
1054 | dev->dvb.frontend->ops.tuner_ops.sleep = philips_tda827x_tuner_sleep; | |
1055 | dev->dvb.frontend->ops.tuner_ops.set_params = philips_tda827x_tuner_set_params; | |
6b3ccab7 | 1056 | } |
86ddd96f | 1057 | break; |
10b7a903 | 1058 | case SAA7134_BOARD_FLYDVBT_DUO_CARDBUS: |
86ddd96f MCC |
1059 | dev->dvb.frontend = tda10046_attach(&tda827x_lifeview_config, |
1060 | &dev->i2c_adap); | |
6b3ccab7 | 1061 | if (dev->dvb.frontend) { |
dea74869 PB |
1062 | dev->dvb.frontend->ops.tuner_ops.init = philips_tda827x_tuner_init; |
1063 | dev->dvb.frontend->ops.tuner_ops.sleep = philips_tda827x_tuner_sleep; | |
1064 | dev->dvb.frontend->ops.tuner_ops.set_params = philips_tda827x_tuner_set_params; | |
6b3ccab7 | 1065 | } |
86ddd96f | 1066 | break; |
2cf36ac4 HH |
1067 | case SAA7134_BOARD_PHILIPS_EUROPA: |
1068 | dev->dvb.frontend = tda10046_attach(&philips_europa_config, | |
1069 | &dev->i2c_adap); | |
6b3ccab7 | 1070 | if (dev->dvb.frontend) { |
dea74869 PB |
1071 | dev->original_demod_sleep = dev->dvb.frontend->ops.sleep; |
1072 | dev->dvb.frontend->ops.sleep = philips_europa_demod_sleep; | |
1073 | dev->dvb.frontend->ops.tuner_ops.init = philips_europa_tuner_init; | |
1074 | dev->dvb.frontend->ops.tuner_ops.sleep = philips_europa_tuner_sleep; | |
1075 | dev->dvb.frontend->ops.tuner_ops.set_params = philips_td1316_tuner_set_params; | |
6b3ccab7 | 1076 | } |
2cf36ac4 HH |
1077 | break; |
1078 | case SAA7134_BOARD_VIDEOMATE_DVBT_300: | |
1079 | dev->dvb.frontend = tda10046_attach(&philips_europa_config, | |
1080 | &dev->i2c_adap); | |
6b3ccab7 | 1081 | if (dev->dvb.frontend) { |
dea74869 PB |
1082 | dev->dvb.frontend->ops.tuner_ops.init = philips_europa_tuner_init; |
1083 | dev->dvb.frontend->ops.tuner_ops.sleep = philips_europa_tuner_sleep; | |
1084 | dev->dvb.frontend->ops.tuner_ops.set_params = philips_td1316_tuner_set_params; | |
6b3ccab7 | 1085 | } |
2cf36ac4 HH |
1086 | break; |
1087 | case SAA7134_BOARD_VIDEOMATE_DVBT_200: | |
1088 | dev->dvb.frontend = tda10046_attach(&philips_tu1216_61_config, | |
1089 | &dev->i2c_adap); | |
6b3ccab7 | 1090 | if (dev->dvb.frontend) { |
dea74869 PB |
1091 | dev->dvb.frontend->ops.tuner_ops.init = philips_tu1216_tuner_61_init; |
1092 | dev->dvb.frontend->ops.tuner_ops.set_params = philips_tu1216_tuner_61_set_params; | |
6b3ccab7 | 1093 | } |
2cf36ac4 | 1094 | break; |
90e9df7f HH |
1095 | case SAA7134_BOARD_PHILIPS_TIGER: |
1096 | dev->dvb.frontend = tda10046_attach(&philips_tiger_config, | |
1097 | &dev->i2c_adap); | |
6b3ccab7 | 1098 | if (dev->dvb.frontend) { |
dea74869 PB |
1099 | dev->dvb.frontend->ops.tuner_ops.init = philips_tiger_tuner_init; |
1100 | dev->dvb.frontend->ops.tuner_ops.sleep = philips_tiger_tuner_sleep; | |
1101 | dev->dvb.frontend->ops.tuner_ops.set_params = philips_tiger_tuner_set_params; | |
6b3ccab7 | 1102 | } |
90e9df7f | 1103 | break; |
d4b0aba4 HH |
1104 | case SAA7134_BOARD_ASUSTeK_P7131_DUAL: |
1105 | dev->dvb.frontend = tda10046_attach(&philips_tiger_config, | |
1106 | &dev->i2c_adap); | |
6b3ccab7 | 1107 | if (dev->dvb.frontend) { |
dea74869 PB |
1108 | dev->dvb.frontend->ops.tuner_ops.init = philips_tiger_tuner_init; |
1109 | dev->dvb.frontend->ops.tuner_ops.sleep = philips_tiger_tuner_sleep; | |
1110 | dev->dvb.frontend->ops.tuner_ops.set_params = philips_tiger_tuner_set_params; | |
6b3ccab7 | 1111 | } |
d4b0aba4 | 1112 | break; |
3d8466ec GG |
1113 | case SAA7134_BOARD_FLYDVBT_LR301: |
1114 | dev->dvb.frontend = tda10046_attach(&tda827x_lifeview_config, | |
1115 | &dev->i2c_adap); | |
6b3ccab7 | 1116 | if (dev->dvb.frontend) { |
dea74869 PB |
1117 | dev->dvb.frontend->ops.tuner_ops.init = philips_tda827x_tuner_init; |
1118 | dev->dvb.frontend->ops.tuner_ops.sleep = philips_tda827x_tuner_sleep; | |
1119 | dev->dvb.frontend->ops.tuner_ops.set_params = philips_tda827x_tuner_set_params; | |
6b3ccab7 | 1120 | } |
3d8466ec | 1121 | break; |
420f32fe NS |
1122 | case SAA7134_BOARD_FLYDVB_TRIO: |
1123 | dev->dvb.frontend = tda10046_attach(&lifeview_trio_config, | |
1124 | &dev->i2c_adap); | |
6b3ccab7 | 1125 | if (dev->dvb.frontend) { |
dea74869 PB |
1126 | dev->dvb.frontend->ops.tuner_ops.sleep = lifeview_trio_tuner_sleep; |
1127 | dev->dvb.frontend->ops.tuner_ops.set_params = lifeview_trio_tuner_set_params; | |
6b3ccab7 | 1128 | } |
420f32fe | 1129 | break; |
df42eaf2 HH |
1130 | case SAA7134_BOARD_ADS_DUO_CARDBUS_PTV331: |
1131 | dev->dvb.frontend = tda10046_attach(&ads_tech_duo_config, | |
1132 | &dev->i2c_adap); | |
6b3ccab7 | 1133 | if (dev->dvb.frontend) { |
dea74869 PB |
1134 | dev->dvb.frontend->ops.tuner_ops.init = ads_duo_tuner_init; |
1135 | dev->dvb.frontend->ops.tuner_ops.sleep = ads_duo_tuner_sleep; | |
1136 | dev->dvb.frontend->ops.tuner_ops.set_params = ads_duo_tuner_set_params; | |
6b3ccab7 | 1137 | } |
df42eaf2 | 1138 | break; |
3dfb729f PH |
1139 | case SAA7134_BOARD_TEVION_DVBT_220RF: |
1140 | dev->dvb.frontend = tda10046_attach(&tevion_dvbt220rf_config, | |
1141 | &dev->i2c_adap); | |
6b3ccab7 | 1142 | if (dev->dvb.frontend) { |
dea74869 PB |
1143 | dev->dvb.frontend->ops.tuner_ops.sleep = tevion_dvb220rf_tuner_sleep; |
1144 | dev->dvb.frontend->ops.tuner_ops.set_params = tevion_dvb220rf_tuner_set_params; | |
6b3ccab7 | 1145 | } |
3dfb729f | 1146 | break; |
d95b8942 HH |
1147 | case SAA7134_BOARD_FLYDVBT_HYBRID_CARDBUS: |
1148 | dev->dvb.frontend = tda10046_attach(&ads_tech_duo_config, | |
1149 | &dev->i2c_adap); | |
6b3ccab7 | 1150 | if (dev->dvb.frontend) { |
dea74869 PB |
1151 | dev->dvb.frontend->ops.tuner_ops.init = ads_duo_tuner_init; |
1152 | dev->dvb.frontend->ops.tuner_ops.sleep = ads_duo_tuner_sleep; | |
1153 | dev->dvb.frontend->ops.tuner_ops.set_params = ads_duo_tuner_set_params; | |
6b3ccab7 | 1154 | } |
d95b8942 | 1155 | break; |
3b64e8e2 MK |
1156 | #endif |
1157 | #ifdef HAVE_NXT200X | |
1158 | case SAA7134_BOARD_AVERMEDIA_AVERTVHD_A180: | |
1159 | dev->dvb.frontend = nxt200x_attach(&avertvhda180, &dev->i2c_adap); | |
a79ddae9 AQ |
1160 | if (dev->dvb.frontend) { |
1161 | dvb_pll_attach(dev->dvb.frontend, 0x61, &dev->i2c_adap, &dvb_pll_tdhu2); | |
1162 | } | |
3b64e8e2 | 1163 | break; |
3e1410ad AB |
1164 | case SAA7134_BOARD_KWORLD_ATSC110: |
1165 | dev->dvb.frontend = nxt200x_attach(&kworldatsc110, &dev->i2c_adap); | |
a79ddae9 AQ |
1166 | if (dev->dvb.frontend) { |
1167 | dvb_pll_attach(dev->dvb.frontend, 0x61, &dev->i2c_adap, &dvb_pll_tuv1236d); | |
1168 | } | |
3e1410ad | 1169 | break; |
86ddd96f | 1170 | #endif |
1da177e4 LT |
1171 | default: |
1172 | printk("%s: Huh? unknown DVB card?\n",dev->name); | |
1173 | break; | |
1174 | } | |
1175 | ||
1176 | if (NULL == dev->dvb.frontend) { | |
1177 | printk("%s: frontend initialization failed\n",dev->name); | |
1178 | return -1; | |
1179 | } | |
1180 | ||
1181 | /* register everything else */ | |
d09dbf92 | 1182 | return videobuf_dvb_register(&dev->dvb, THIS_MODULE, dev, &dev->pci->dev); |
1da177e4 LT |
1183 | } |
1184 | ||
1185 | static int dvb_fini(struct saa7134_dev *dev) | |
1186 | { | |
1187 | static int on = TDA9887_PRESENT | TDA9887_PORT2_INACTIVE; | |
1188 | ||
1da177e4 LT |
1189 | switch (dev->board) { |
1190 | case SAA7134_BOARD_PINNACLE_300I_DVBT_PAL: | |
1191 | /* otherwise we don't detect the tuner on next insmod */ | |
1192 | saa7134_i2c_call_clients(dev,TDA9887_SET_CONFIG,&on); | |
1193 | break; | |
1194 | }; | |
1195 | videobuf_dvb_unregister(&dev->dvb); | |
1196 | return 0; | |
1197 | } | |
1198 | ||
1199 | static struct saa7134_mpeg_ops dvb_ops = { | |
1200 | .type = SAA7134_MPEG_DVB, | |
1201 | .init = dvb_init, | |
1202 | .fini = dvb_fini, | |
1203 | }; | |
1204 | ||
1205 | static int __init dvb_register(void) | |
1206 | { | |
1207 | return saa7134_ts_register(&dvb_ops); | |
1208 | } | |
1209 | ||
1210 | static void __exit dvb_unregister(void) | |
1211 | { | |
1212 | saa7134_ts_unregister(&dvb_ops); | |
1213 | } | |
1214 | ||
1215 | module_init(dvb_register); | |
1216 | module_exit(dvb_unregister); | |
1217 | ||
1218 | /* ------------------------------------------------------------------ */ | |
1219 | /* | |
1220 | * Local variables: | |
1221 | * c-basic-offset: 8 | |
1222 | * End: | |
1223 | */ |