[mirror_ubuntu-bionic-kernel.git] / drivers / mfd / intel-lpss.c

/*
 * Intel Sunrisepoint LPSS core support.
 *
 * Copyright (C) 2015, Intel Corporation
 *
 * Authors: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
 *          Mika Westerberg <mika.westerberg@linux.intel.com>
 *          Heikki Krogerus <heikki.krogerus@linux.intel.com>
 *          Jarkko Nikula <jarkko.nikula@linux.intel.com>
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */

#include <linux/clk.h>
#include <linux/clkdev.h>
#include <linux/clk-provider.h>
#include <linux/debugfs.h>
#include <linux/dmi.h>
#include <linux/idr.h>
#include <linux/ioport.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/mfd/core.h>
#include <linux/pm_qos.h>
#include <linux/pm_runtime.h>
#include <linux/property.h>
#include <linux/seq_file.h>
#include <linux/io-64-nonatomic-lo-hi.h>

#include "intel-lpss.h"

#define LPSS_DEV_OFFSET		0x000
#define LPSS_DEV_SIZE		0x200
#define LPSS_PRIV_OFFSET	0x200
#define LPSS_PRIV_SIZE		0x100
#define LPSS_PRIV_REG_COUNT	(LPSS_PRIV_SIZE / 4)
#define LPSS_IDMA64_OFFSET	0x800
#define LPSS_IDMA64_SIZE	0x800

/* Offsets from lpss->priv */
#define LPSS_PRIV_RESETS		0x04
#define LPSS_PRIV_RESETS_FUNC		BIT(2)
#define LPSS_PRIV_RESETS_IDMA		0x3

#define LPSS_PRIV_ACTIVELTR		0x10
#define LPSS_PRIV_IDLELTR		0x14

#define LPSS_PRIV_LTR_REQ		BIT(15)
#define LPSS_PRIV_LTR_SCALE_MASK	0xc00
#define LPSS_PRIV_LTR_SCALE_1US		0x800
#define LPSS_PRIV_LTR_SCALE_32US	0xc00
#define LPSS_PRIV_LTR_VALUE_MASK	0x3ff

#define LPSS_PRIV_SSP_REG		0x20
#define LPSS_PRIV_SSP_REG_DIS_DMA_FIN	BIT(0)

#define LPSS_PRIV_REMAP_ADDR		0x40

#define LPSS_PRIV_CAPS			0xfc
#define LPSS_PRIV_CAPS_NO_IDMA		BIT(8)
#define LPSS_PRIV_CAPS_TYPE_SHIFT	4
#define LPSS_PRIV_CAPS_TYPE_MASK	(0xf << LPSS_PRIV_CAPS_TYPE_SHIFT)

/* This matches the type field in CAPS register */
enum intel_lpss_dev_type {
	LPSS_DEV_I2C = 0,
	LPSS_DEV_UART,
	LPSS_DEV_SPI,
};

struct intel_lpss {
	const struct intel_lpss_platform_info *info;
	enum intel_lpss_dev_type type;
	struct clk *clk;
	struct clk_lookup *clock;
	struct mfd_cell *cell;
	struct device *dev;
	void __iomem *priv;
	u32 priv_ctx[LPSS_PRIV_REG_COUNT];
	int devid;
	u32 caps;
	u32 active_ltr;
	u32 idle_ltr;
	struct dentry *debugfs;
};

static const struct resource intel_lpss_dev_resources[] = {
	DEFINE_RES_MEM_NAMED(LPSS_DEV_OFFSET, LPSS_DEV_SIZE, "lpss_dev"),
	DEFINE_RES_MEM_NAMED(LPSS_PRIV_OFFSET, LPSS_PRIV_SIZE, "lpss_priv"),
	DEFINE_RES_IRQ(0),
};

static const struct resource intel_lpss_idma64_resources[] = {
	DEFINE_RES_MEM(LPSS_IDMA64_OFFSET, LPSS_IDMA64_SIZE),
	DEFINE_RES_IRQ(0),
};

#define LPSS_IDMA64_DRIVER_NAME		"idma64"

/*
 * Cells needs to be ordered so that the iDMA is created first. This is
 * because we need to be sure the DMA is available when the host controller
 * driver is probed.
 */
static const struct mfd_cell intel_lpss_idma64_cell = {
	.name = LPSS_IDMA64_DRIVER_NAME,
	.num_resources = ARRAY_SIZE(intel_lpss_idma64_resources),
	.resources = intel_lpss_idma64_resources,
};

static const struct mfd_cell intel_lpss_i2c_cell = {
	.name = "i2c_designware",
	.num_resources = ARRAY_SIZE(intel_lpss_dev_resources),
	.resources = intel_lpss_dev_resources,
};

static const struct mfd_cell intel_lpss_uart_cell = {
	.name = "dw-apb-uart",
	.num_resources = ARRAY_SIZE(intel_lpss_dev_resources),
	.resources = intel_lpss_dev_resources,
};

static const struct mfd_cell intel_lpss_spi_cell = {
	.name = "pxa2xx-spi",
	.num_resources = ARRAY_SIZE(intel_lpss_dev_resources),
	.resources = intel_lpss_dev_resources,
};

static DEFINE_IDA(intel_lpss_devid_ida);
static struct dentry *intel_lpss_debugfs;

static const struct dmi_system_id mtrr_large_wc_region[] = {
	{
		.ident = "Dell Computer Corporation",
		.matches = {
			DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
			DMI_MATCH(DMI_PRODUCT_NAME, "XPS 13 7390 2-in-1"),
		},
	},
	{ }
};

static int intel_lpss_request_dma_module(const char *name)
{
	static bool intel_lpss_dma_requested;

	if (intel_lpss_dma_requested)
		return 0;

	intel_lpss_dma_requested = true;
	return request_module("%s", name);
}

static void intel_lpss_cache_ltr(struct intel_lpss *lpss)
{
	lpss->active_ltr = readl(lpss->priv + LPSS_PRIV_ACTIVELTR);
	lpss->idle_ltr = readl(lpss->priv + LPSS_PRIV_IDLELTR);
}

static int intel_lpss_debugfs_add(struct intel_lpss *lpss)
{
	struct dentry *dir;

	dir = debugfs_create_dir(dev_name(lpss->dev), intel_lpss_debugfs);
	if (IS_ERR(dir))
		return PTR_ERR(dir);

	/* Cache the values into lpss structure */
	intel_lpss_cache_ltr(lpss);

	debugfs_create_x32("capabilities", S_IRUGO, dir, &lpss->caps);
	debugfs_create_x32("active_ltr", S_IRUGO, dir, &lpss->active_ltr);
	debugfs_create_x32("idle_ltr", S_IRUGO, dir, &lpss->idle_ltr);

	lpss->debugfs = dir;
	return 0;
}

static void intel_lpss_debugfs_remove(struct intel_lpss *lpss)
{
	debugfs_remove_recursive(lpss->debugfs);
}

static void intel_lpss_ltr_set(struct device *dev, s32 val)
{
	struct intel_lpss *lpss = dev_get_drvdata(dev);
	u32 ltr;

	/*
	 * Program latency tolerance (LTR) accordingly what has been asked
	 * by the PM QoS layer or disable it in case we were passed
	 * negative value or PM_QOS_LATENCY_ANY.
	 */
	ltr = readl(lpss->priv + LPSS_PRIV_ACTIVELTR);

	if (val == PM_QOS_LATENCY_ANY || val < 0) {
		ltr &= ~LPSS_PRIV_LTR_REQ;
	} else {
		ltr |= LPSS_PRIV_LTR_REQ;
		ltr &= ~LPSS_PRIV_LTR_SCALE_MASK;
		ltr &= ~LPSS_PRIV_LTR_VALUE_MASK;

		if (val > LPSS_PRIV_LTR_VALUE_MASK)
			ltr |= LPSS_PRIV_LTR_SCALE_32US | val >> 5;
		else
			ltr |= LPSS_PRIV_LTR_SCALE_1US | val;
	}

	if (ltr == lpss->active_ltr)
		return;

	writel(ltr, lpss->priv + LPSS_PRIV_ACTIVELTR);
	writel(ltr, lpss->priv + LPSS_PRIV_IDLELTR);

	/* Cache the values into lpss structure */
	intel_lpss_cache_ltr(lpss);
}

static void intel_lpss_ltr_expose(struct intel_lpss *lpss)
{
	lpss->dev->power.set_latency_tolerance = intel_lpss_ltr_set;
	dev_pm_qos_expose_latency_tolerance(lpss->dev);
}

static void intel_lpss_ltr_hide(struct intel_lpss *lpss)
{
	dev_pm_qos_hide_latency_tolerance(lpss->dev);
	lpss->dev->power.set_latency_tolerance = NULL;
}

static int intel_lpss_assign_devs(struct intel_lpss *lpss)
{
	const struct mfd_cell *cell;
	unsigned int type;

	type = lpss->caps & LPSS_PRIV_CAPS_TYPE_MASK;
	type >>= LPSS_PRIV_CAPS_TYPE_SHIFT;

	switch (type) {
	case LPSS_DEV_I2C:
		cell = &intel_lpss_i2c_cell;
		break;
	case LPSS_DEV_UART:
		cell = &intel_lpss_uart_cell;
		break;
	case LPSS_DEV_SPI:
		cell = &intel_lpss_spi_cell;
		break;
	default:
		return -ENODEV;
	}

	lpss->cell = devm_kmemdup(lpss->dev, cell, sizeof(*cell), GFP_KERNEL);
	if (!lpss->cell)
		return -ENOMEM;

	lpss->type = type;

	return 0;
}

static bool intel_lpss_has_idma(const struct intel_lpss *lpss)
{
	return (lpss->caps & LPSS_PRIV_CAPS_NO_IDMA) == 0;
}

static void intel_lpss_set_remap_addr(const struct intel_lpss *lpss)
{
	resource_size_t addr = lpss->info->mem->start;

	lo_hi_writeq(addr, lpss->priv + LPSS_PRIV_REMAP_ADDR);
}

static void intel_lpss_deassert_reset(const struct intel_lpss *lpss)
{
	u32 value = LPSS_PRIV_RESETS_FUNC | LPSS_PRIV_RESETS_IDMA;

	/* Bring out the device from reset */
	writel(value, lpss->priv + LPSS_PRIV_RESETS);
}

static void intel_lpss_init_dev(const struct intel_lpss *lpss)
{
	u32 value = LPSS_PRIV_SSP_REG_DIS_DMA_FIN;

	/* Set the device in reset state */
	writel(0, lpss->priv + LPSS_PRIV_RESETS);

	intel_lpss_deassert_reset(lpss);

	intel_lpss_set_remap_addr(lpss);

	if (!intel_lpss_has_idma(lpss))
		return;

	/* Make sure that SPI multiblock DMA transfers are re-enabled */
	if (lpss->type == LPSS_DEV_SPI)
		writel(value, lpss->priv + LPSS_PRIV_SSP_REG);
}

static void intel_lpss_unregister_clock_tree(struct clk *clk)
{
	struct clk *parent;

	while (clk) {
		parent = clk_get_parent(clk);
		clk_unregister(clk);
		clk = parent;
	}
}

static int intel_lpss_register_clock_divider(struct intel_lpss *lpss,
					     const char *devname,
					     struct clk **clk)
{
	char name[32];
	struct clk *tmp = *clk;

	snprintf(name, sizeof(name), "%s-enable", devname);
	tmp = clk_register_gate(NULL, name, __clk_get_name(tmp), 0,
				lpss->priv, 0, 0, NULL);
	if (IS_ERR(tmp))
		return PTR_ERR(tmp);

	snprintf(name, sizeof(name), "%s-div", devname);
	tmp = clk_register_fractional_divider(NULL, name, __clk_get_name(tmp),
					      0, lpss->priv, 1, 15, 16, 15, 0,
					      NULL);
	if (IS_ERR(tmp))
		return PTR_ERR(tmp);
	*clk = tmp;

	snprintf(name, sizeof(name), "%s-update", devname);
	tmp = clk_register_gate(NULL, name, __clk_get_name(tmp),
				CLK_SET_RATE_PARENT, lpss->priv, 31, 0, NULL);
	if (IS_ERR(tmp))
		return PTR_ERR(tmp);
	*clk = tmp;

	return 0;
}

static int intel_lpss_register_clock(struct intel_lpss *lpss)
{
	const struct mfd_cell *cell = lpss->cell;
	struct clk *clk;
	char devname[24];
	int ret;

	if (!lpss->info->clk_rate)
		return 0;

	/* Root clock */
	clk = clk_register_fixed_rate(NULL, dev_name(lpss->dev), NULL, 0,
				      lpss->info->clk_rate);
	if (IS_ERR(clk))
		return PTR_ERR(clk);

	snprintf(devname, sizeof(devname), "%s.%d", cell->name, lpss->devid);

	/*
	 * Support for clock divider only if it has some preset value.
	 * Otherwise we assume that the divider is not used.
	 */
	if (lpss->type != LPSS_DEV_I2C) {
		ret = intel_lpss_register_clock_divider(lpss, devname, &clk);
		if (ret)
			goto err_clk_register;
	}

	ret = -ENOMEM;

	/* Clock for the host controller */
	lpss->clock = clkdev_create(clk, lpss->info->clk_con_id, "%s", devname);
	if (!lpss->clock)
		goto err_clk_register;

	lpss->clk = clk;

	return 0;

err_clk_register:
	intel_lpss_unregister_clock_tree(clk);

	return ret;
}

static void intel_lpss_unregister_clock(struct intel_lpss *lpss)
{
	if (IS_ERR_OR_NULL(lpss->clk))
		return;

	clkdev_drop(lpss->clock);
	intel_lpss_unregister_clock_tree(lpss->clk);
}

int intel_lpss_probe(struct device *dev,
		     const struct intel_lpss_platform_info *info)
{
	struct intel_lpss *lpss;
	int ret;

	if (!info || !info->mem || info->irq <= 0)
		return -EINVAL;

	lpss = devm_kzalloc(dev, sizeof(*lpss), GFP_KERNEL);
	if (!lpss)
		return -ENOMEM;

	if (dmi_check_system(mtrr_large_wc_region))
		lpss->priv = devm_ioremap_uc(dev, info->mem->start + LPSS_PRIV_OFFSET,
					     LPSS_PRIV_SIZE);
	else
		lpss->priv = devm_ioremap(dev, info->mem->start + LPSS_PRIV_OFFSET,
					  LPSS_PRIV_SIZE);
	if (!lpss->priv)
		return -ENOMEM;

	lpss->info = info;
	lpss->dev = dev;
	lpss->caps = readl(lpss->priv + LPSS_PRIV_CAPS);

	dev_set_drvdata(dev, lpss);

	ret = intel_lpss_assign_devs(lpss);
	if (ret)
		return ret;

	lpss->cell->properties = info->properties;

	intel_lpss_init_dev(lpss);

	lpss->devid = ida_simple_get(&intel_lpss_devid_ida, 0, 0, GFP_KERNEL);
	if (lpss->devid < 0)
		return lpss->devid;

	ret = intel_lpss_register_clock(lpss);
	if (ret)
		goto err_clk_register;

	intel_lpss_ltr_expose(lpss);

	ret = intel_lpss_debugfs_add(lpss);
	if (ret)
		dev_warn(dev, "Failed to create debugfs entries\n");

	if (intel_lpss_has_idma(lpss)) {
		/*
		 * Ensure the DMA driver is loaded before the host
		 * controller device appears, so that the host controller
		 * driver can request its DMA channels as early as
		 * possible.
		 *
		 * If the DMA module is not there that's OK as well.
		 */
		intel_lpss_request_dma_module(LPSS_IDMA64_DRIVER_NAME);

		ret = mfd_add_devices(dev, lpss->devid, &intel_lpss_idma64_cell,
				      1, info->mem, info->irq, NULL);
		if (ret)
			dev_warn(dev, "Failed to add %s, fallback to PIO\n",
				 LPSS_IDMA64_DRIVER_NAME);
	}

	ret = mfd_add_devices(dev, lpss->devid, lpss->cell,
			      1, info->mem, info->irq, NULL);
	if (ret)
		goto err_remove_ltr;

	return 0;

err_remove_ltr:
	intel_lpss_debugfs_remove(lpss);
	intel_lpss_ltr_hide(lpss);
	intel_lpss_unregister_clock(lpss);

err_clk_register:
	ida_simple_remove(&intel_lpss_devid_ida, lpss->devid);

	return ret;
}
EXPORT_SYMBOL_GPL(intel_lpss_probe);

void intel_lpss_remove(struct device *dev)
{
	struct intel_lpss *lpss = dev_get_drvdata(dev);

	mfd_remove_devices(dev);
	intel_lpss_debugfs_remove(lpss);
	intel_lpss_ltr_hide(lpss);
	intel_lpss_unregister_clock(lpss);
	ida_simple_remove(&intel_lpss_devid_ida, lpss->devid);
}
EXPORT_SYMBOL_GPL(intel_lpss_remove);

static int resume_lpss_device(struct device *dev, void *data)
{
	pm_runtime_resume(dev);
	return 0;
}

int intel_lpss_prepare(struct device *dev)
{
	/*
	 * Resume both child devices before entering system sleep. This
	 * ensures that they are in proper state before they get suspended.
	 */
	device_for_each_child_reverse(dev, NULL, resume_lpss_device);
	return 0;
}
EXPORT_SYMBOL_GPL(intel_lpss_prepare);

int intel_lpss_suspend(struct device *dev)
{
	struct intel_lpss *lpss = dev_get_drvdata(dev);
	unsigned int i;

	/* Save device context */
	for (i = 0; i < LPSS_PRIV_REG_COUNT; i++)
		lpss->priv_ctx[i] = readl(lpss->priv + i * 4);

	/*
	 * If the device type is not UART, then put the controller into
	 * reset. UART cannot be put into reset since S3/S0ix fail when
	 * no_console_suspend flag is enabled.
	 */
	if (lpss->type != LPSS_DEV_UART)
		writel(0, lpss->priv + LPSS_PRIV_RESETS);

	return 0;
}
EXPORT_SYMBOL_GPL(intel_lpss_suspend);

int intel_lpss_resume(struct device *dev)
{
	struct intel_lpss *lpss = dev_get_drvdata(dev);
	unsigned int i;

	intel_lpss_deassert_reset(lpss);

	/* Restore device context */
	for (i = 0; i < LPSS_PRIV_REG_COUNT; i++)
		writel(lpss->priv_ctx[i], lpss->priv + i * 4);

	return 0;
}
EXPORT_SYMBOL_GPL(intel_lpss_resume);

static int __init intel_lpss_init(void)
{
	intel_lpss_debugfs = debugfs_create_dir("intel_lpss", NULL);
	return 0;
}
module_init(intel_lpss_init);

static void __exit intel_lpss_exit(void)
{
	ida_destroy(&intel_lpss_devid_ida);
	debugfs_remove(intel_lpss_debugfs);
}
module_exit(intel_lpss_exit);

MODULE_AUTHOR("Andy Shevchenko <andriy.shevchenko@linux.intel.com>");
MODULE_AUTHOR("Mika Westerberg <mika.westerberg@linux.intel.com>");
MODULE_AUTHOR("Heikki Krogerus <heikki.krogerus@linux.intel.com>");
MODULE_AUTHOR("Jarkko Nikula <jarkko.nikula@linux.intel.com>");
MODULE_DESCRIPTION("Intel LPSS core driver");
MODULE_LICENSE("GPL v2");
Commit	Line	Data
4b45efe8 AS	1	/*
	2	* Intel Sunrisepoint LPSS core support.
	3	*
	4	* Copyright (C) 2015, Intel Corporation
	5	*
	6	* Authors: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
	7	* Mika Westerberg <mika.westerberg@linux.intel.com>
	8	* Heikki Krogerus <heikki.krogerus@linux.intel.com>
	9	* Jarkko Nikula <jarkko.nikula@linux.intel.com>
	10	*
	11	* This program is free software; you can redistribute it and/or modify
	12	* it under the terms of the GNU General Public License version 2 as
	13	* published by the Free Software Foundation.
	14	*/
	15
	16	#include <linux/clk.h>
	17	#include <linux/clkdev.h>
	18	#include <linux/clk-provider.h>
	19	#include <linux/debugfs.h>
933d4644	20	#include <linux/dmi.h>
4b45efe8 AS	21	#include <linux/idr.h>
	22	#include <linux/ioport.h>
	23	#include <linux/kernel.h>
	24	#include <linux/module.h>
	25	#include <linux/mfd/core.h>
	26	#include <linux/pm_qos.h>
	27	#include <linux/pm_runtime.h>
e15ad215	28	#include <linux/property.h>
4b45efe8	29	#include <linux/seq_file.h>
9cf5c095	30	#include <linux/io-64-nonatomic-lo-hi.h>
689d4453	31
4b45efe8 AS	32	#include "intel-lpss.h"
	33
	34	#define LPSS_DEV_OFFSET 0x000
	35	#define LPSS_DEV_SIZE 0x200
	36	#define LPSS_PRIV_OFFSET 0x200
	37	#define LPSS_PRIV_SIZE 0x100
41a3da2b	38	#define LPSS_PRIV_REG_COUNT (LPSS_PRIV_SIZE / 4)
4b45efe8 AS	39	#define LPSS_IDMA64_OFFSET 0x800
	40	#define LPSS_IDMA64_SIZE 0x800
	41
	42	/* Offsets from lpss->priv */
	43	#define LPSS_PRIV_RESETS 0x04
	44	#define LPSS_PRIV_RESETS_FUNC BIT(2)
	45	#define LPSS_PRIV_RESETS_IDMA 0x3
	46
	47	#define LPSS_PRIV_ACTIVELTR 0x10
	48	#define LPSS_PRIV_IDLELTR 0x14
	49
	50	#define LPSS_PRIV_LTR_REQ BIT(15)
	51	#define LPSS_PRIV_LTR_SCALE_MASK 0xc00
	52	#define LPSS_PRIV_LTR_SCALE_1US 0x800
	53	#define LPSS_PRIV_LTR_SCALE_32US 0xc00
	54	#define LPSS_PRIV_LTR_VALUE_MASK 0x3ff
	55
	56	#define LPSS_PRIV_SSP_REG 0x20
	57	#define LPSS_PRIV_SSP_REG_DIS_DMA_FIN BIT(0)
	58
689d4453	59	#define LPSS_PRIV_REMAP_ADDR 0x40
4b45efe8 AS	60
	61	#define LPSS_PRIV_CAPS 0xfc
	62	#define LPSS_PRIV_CAPS_NO_IDMA BIT(8)
	63	#define LPSS_PRIV_CAPS_TYPE_SHIFT 4
	64	#define LPSS_PRIV_CAPS_TYPE_MASK (0xf << LPSS_PRIV_CAPS_TYPE_SHIFT)
	65
	66	/* This matches the type field in CAPS register */
	67	enum intel_lpss_dev_type {
	68	LPSS_DEV_I2C = 0,
	69	LPSS_DEV_UART,
	70	LPSS_DEV_SPI,
	71	};
	72
	73	struct intel_lpss {
	74	const struct intel_lpss_platform_info *info;
	75	enum intel_lpss_dev_type type;
	76	struct clk *clk;
	77	struct clk_lookup *clock;
e15ad215	78	struct mfd_cell *cell;
4b45efe8 AS	79	struct device *dev;
4b45efe8 AS	80	void __iomem *priv;
41a3da2b	81	u32 priv_ctx[LPSS_PRIV_REG_COUNT];
4b45efe8 AS	82	int devid;
	83	u32 caps;
	84	u32 active_ltr;
	85	u32 idle_ltr;
	86	struct dentry *debugfs;
	87	};
	88
	89	static const struct resource intel_lpss_dev_resources[] = {
	90	DEFINE_RES_MEM_NAMED(LPSS_DEV_OFFSET, LPSS_DEV_SIZE, "lpss_dev"),
	91	DEFINE_RES_MEM_NAMED(LPSS_PRIV_OFFSET, LPSS_PRIV_SIZE, "lpss_priv"),
	92	DEFINE_RES_IRQ(0),
	93	};
	94
	95	static const struct resource intel_lpss_idma64_resources[] = {
	96	DEFINE_RES_MEM(LPSS_IDMA64_OFFSET, LPSS_IDMA64_SIZE),
	97	DEFINE_RES_IRQ(0),
	98	};
	99
	100	#define LPSS_IDMA64_DRIVER_NAME "idma64"
	101
	102	/*
	103	* Cells needs to be ordered so that the iDMA is created first. This is
	104	* because we need to be sure the DMA is available when the host controller
	105	* driver is probed.
	106	*/
	107	static const struct mfd_cell intel_lpss_idma64_cell = {
	108	.name = LPSS_IDMA64_DRIVER_NAME,
	109	.num_resources = ARRAY_SIZE(intel_lpss_idma64_resources),
	110	.resources = intel_lpss_idma64_resources,
	111	};
	112
	113	static const struct mfd_cell intel_lpss_i2c_cell = {
	114	.name = "i2c_designware",
	115	.num_resources = ARRAY_SIZE(intel_lpss_dev_resources),
	116	.resources = intel_lpss_dev_resources,
	117	};
	118
	119	static const struct mfd_cell intel_lpss_uart_cell = {
	120	.name = "dw-apb-uart",
	121	.num_resources = ARRAY_SIZE(intel_lpss_dev_resources),
	122	.resources = intel_lpss_dev_resources,
	123	};
	124
	125	static const struct mfd_cell intel_lpss_spi_cell = {
	126	.name = "pxa2xx-spi",
	127	.num_resources = ARRAY_SIZE(intel_lpss_dev_resources),
	128	.resources = intel_lpss_dev_resources,
	129	};
	130
	131	static DEFINE_IDA(intel_lpss_devid_ida);
	132	static struct dentry *intel_lpss_debugfs;
	133
933d4644 AK	134	static const struct dmi_system_id mtrr_large_wc_region[] = {
	135	{
	136	.ident = "Dell Computer Corporation",
	137	.matches = {
	138	DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
	139	DMI_MATCH(DMI_PRODUCT_NAME, "XPS 13 7390 2-in-1"),
	140	},
	141	},
	142	{ }
	143	};
	144
4b45efe8 AS	145	static int intel_lpss_request_dma_module(const char *name)
	146	{
	147	static bool intel_lpss_dma_requested;
	148
	149	if (intel_lpss_dma_requested)
	150	return 0;
	151
	152	intel_lpss_dma_requested = true;
	153	return request_module("%s", name);
	154	}
	155
	156	static void intel_lpss_cache_ltr(struct intel_lpss *lpss)
	157	{
	158	lpss->active_ltr = readl(lpss->priv + LPSS_PRIV_ACTIVELTR);
	159	lpss->idle_ltr = readl(lpss->priv + LPSS_PRIV_IDLELTR);
	160	}
	161
	162	static int intel_lpss_debugfs_add(struct intel_lpss *lpss)
	163	{
	164	struct dentry *dir;
	165
	166	dir = debugfs_create_dir(dev_name(lpss->dev), intel_lpss_debugfs);
	167	if (IS_ERR(dir))
	168	return PTR_ERR(dir);
	169
	170	/* Cache the values into lpss structure */
	171	intel_lpss_cache_ltr(lpss);
	172
	173	debugfs_create_x32("capabilities", S_IRUGO, dir, &lpss->caps);
	174	debugfs_create_x32("active_ltr", S_IRUGO, dir, &lpss->active_ltr);
	175	debugfs_create_x32("idle_ltr", S_IRUGO, dir, &lpss->idle_ltr);
	176
	177	lpss->debugfs = dir;
	178	return 0;
	179	}
	180
	181	static void intel_lpss_debugfs_remove(struct intel_lpss *lpss)
	182	{
	183	debugfs_remove_recursive(lpss->debugfs);
	184	}
	185
	186	static void intel_lpss_ltr_set(struct device *dev, s32 val)
	187	{
	188	struct intel_lpss *lpss = dev_get_drvdata(dev);
	189	u32 ltr;
	190
	191	/*
	192	* Program latency tolerance (LTR) accordingly what has been asked
	193	* by the PM QoS layer or disable it in case we were passed
	194	* negative value or PM_QOS_LATENCY_ANY.
	195	*/
	196	ltr = readl(lpss->priv + LPSS_PRIV_ACTIVELTR);
	197
	198	if (val == PM_QOS_LATENCY_ANY \|\| val < 0) {
	199	ltr &= ~LPSS_PRIV_LTR_REQ;
	200	} else {
	201	ltr \|= LPSS_PRIV_LTR_REQ;
	202	ltr &= ~LPSS_PRIV_LTR_SCALE_MASK;
	203	ltr &= ~LPSS_PRIV_LTR_VALUE_MASK;
	204
	205	if (val > LPSS_PRIV_LTR_VALUE_MASK)
	206	ltr \|= LPSS_PRIV_LTR_SCALE_32US \| val >> 5;
	207	else
	208	ltr \|= LPSS_PRIV_LTR_SCALE_1US \| val;
209	}
210
211	if (ltr == lpss->active_ltr)
212	return;
213
214	writel(ltr, lpss->priv + LPSS_PRIV_ACTIVELTR);
215	writel(ltr, lpss->priv + LPSS_PRIV_IDLELTR);
216
217	/* Cache the values into lpss structure */
218	intel_lpss_cache_ltr(lpss);
219	}
220
221	static void intel_lpss_ltr_expose(struct intel_lpss *lpss)
222	{
223	lpss->dev->power.set_latency_tolerance = intel_lpss_ltr_set;
224	dev_pm_qos_expose_latency_tolerance(lpss->dev);
225	}
226
227	static void intel_lpss_ltr_hide(struct intel_lpss *lpss)
228	{
229	dev_pm_qos_hide_latency_tolerance(lpss->dev);
230	lpss->dev->power.set_latency_tolerance = NULL;
231	}
232
233	static int intel_lpss_assign_devs(struct intel_lpss *lpss)
234	{
e15ad215	235	const struct mfd_cell *cell;
4b45efe8 AS	236	unsigned int type;
	237
	238	type = lpss->caps & LPSS_PRIV_CAPS_TYPE_MASK;
	239	type >>= LPSS_PRIV_CAPS_TYPE_SHIFT;
	240
	241	switch (type) {
	242	case LPSS_DEV_I2C:
e15ad215	243	cell = &intel_lpss_i2c_cell;
4b45efe8 AS	244	break;
4b45efe8 AS	245	case LPSS_DEV_UART:
e15ad215	246	cell = &intel_lpss_uart_cell;
4b45efe8 AS	247	break;
4b45efe8 AS	248	case LPSS_DEV_SPI:
e15ad215	249	cell = &intel_lpss_spi_cell;
4b45efe8 AS	250	break;
	251	default:
	252	return -ENODEV;
	253	}
	254
e15ad215 MW	255	lpss->cell = devm_kmemdup(lpss->dev, cell, sizeof(*cell), GFP_KERNEL);
	256	if (!lpss->cell)
	257	return -ENOMEM;
	258
4b45efe8 AS	259	lpss->type = type;
	260
	261	return 0;
	262	}
	263
	264	static bool intel_lpss_has_idma(const struct intel_lpss *lpss)
	265	{
	266	return (lpss->caps & LPSS_PRIV_CAPS_NO_IDMA) == 0;
	267	}
	268
	269	static void intel_lpss_set_remap_addr(const struct intel_lpss *lpss)
	270	{
	271	resource_size_t addr = lpss->info->mem->start;
	272
689d4453	273	lo_hi_writeq(addr, lpss->priv + LPSS_PRIV_REMAP_ADDR);
4b45efe8 AS	274	}
	275
	276	static void intel_lpss_deassert_reset(const struct intel_lpss *lpss)
	277	{
	278	u32 value = LPSS_PRIV_RESETS_FUNC \| LPSS_PRIV_RESETS_IDMA;
	279
	280	/* Bring out the device from reset */
	281	writel(value, lpss->priv + LPSS_PRIV_RESETS);
	282	}
	283
	284	static void intel_lpss_init_dev(const struct intel_lpss *lpss)
	285	{
	286	u32 value = LPSS_PRIV_SSP_REG_DIS_DMA_FIN;
	287
80b1f03d BW	288	/* Set the device in reset state */
	289	writel(0, lpss->priv + LPSS_PRIV_RESETS);
	290
4b45efe8 AS	291	intel_lpss_deassert_reset(lpss);
4b45efe8 AS	292
83386ac4 AS	293	intel_lpss_set_remap_addr(lpss);
83386ac4 AS	294
4b45efe8 AS	295	if (!intel_lpss_has_idma(lpss))
	296	return;
	297
4b45efe8 AS	298	/* Make sure that SPI multiblock DMA transfers are re-enabled */
	299	if (lpss->type == LPSS_DEV_SPI)
	300	writel(value, lpss->priv + LPSS_PRIV_SSP_REG);
	301	}
	302
	303	static void intel_lpss_unregister_clock_tree(struct clk *clk)
	304	{
	305	struct clk *parent;
	306
	307	while (clk) {
	308	parent = clk_get_parent(clk);
	309	clk_unregister(clk);
	310	clk = parent;
	311	}
	312	}
	313
	314	static int intel_lpss_register_clock_divider(struct intel_lpss *lpss,
	315	const char *devname,
	316	struct clk **clk)
	317	{
	318	char name[32];
	319	struct clk tmp = clk;
	320
	321	snprintf(name, sizeof(name), "%s-enable", devname);
	322	tmp = clk_register_gate(NULL, name, __clk_get_name(tmp), 0,
	323	lpss->priv, 0, 0, NULL);
	324	if (IS_ERR(tmp))
	325	return PTR_ERR(tmp);
	326
	327	snprintf(name, sizeof(name), "%s-div", devname);
	328	tmp = clk_register_fractional_divider(NULL, name, __clk_get_name(tmp),
	329	0, lpss->priv, 1, 15, 16, 15, 0,
	330	NULL);
	331	if (IS_ERR(tmp))
	332	return PTR_ERR(tmp);
	333	*clk = tmp;
	334
	335	snprintf(name, sizeof(name), "%s-update", devname);
	336	tmp = clk_register_gate(NULL, name, __clk_get_name(tmp),
	337	CLK_SET_RATE_PARENT, lpss->priv, 31, 0, NULL);
	338	if (IS_ERR(tmp))
	339	return PTR_ERR(tmp);
	340	*clk = tmp;
	341
	342	return 0;
	343	}
	344
	345	static int intel_lpss_register_clock(struct intel_lpss *lpss)
	346	{
	347	const struct mfd_cell *cell = lpss->cell;
	348	struct clk *clk;
	349	char devname[24];
	350	int ret;
	351
	352	if (!lpss->info->clk_rate)
	353	return 0;
	354
	355	/* Root clock */
0f7e70e7 SB	356	clk = clk_register_fixed_rate(NULL, dev_name(lpss->dev), NULL, 0,
0f7e70e7 SB	357	lpss->info->clk_rate);
4b45efe8 AS	358	if (IS_ERR(clk))
	359	return PTR_ERR(clk);
	360
	361	snprintf(devname, sizeof(devname), "%s.%d", cell->name, lpss->devid);
	362
	363	/*
	364	* Support for clock divider only if it has some preset value.
	365	* Otherwise we assume that the divider is not used.
	366	*/
	367	if (lpss->type != LPSS_DEV_I2C) {
	368	ret = intel_lpss_register_clock_divider(lpss, devname, &clk);
	369	if (ret)
	370	goto err_clk_register;
	371	}
	372
	373	ret = -ENOMEM;
	374
	375	/* Clock for the host controller */
	376	lpss->clock = clkdev_create(clk, lpss->info->clk_con_id, "%s", devname);
	377	if (!lpss->clock)
	378	goto err_clk_register;
	379
	380	lpss->clk = clk;
	381
	382	return 0;
	383
	384	err_clk_register:
	385	intel_lpss_unregister_clock_tree(clk);
	386
	387	return ret;
	388	}
	389
	390	static void intel_lpss_unregister_clock(struct intel_lpss *lpss)
	391	{
	392	if (IS_ERR_OR_NULL(lpss->clk))
	393	return;
	394
	395	clkdev_drop(lpss->clock);
	396	intel_lpss_unregister_clock_tree(lpss->clk);
	397	}
	398
	399	int intel_lpss_probe(struct device *dev,
	400	const struct intel_lpss_platform_info *info)
	401	{
	402	struct intel_lpss *lpss;
	403	int ret;
	404
	405	if (!info \|\| !info->mem \|\| info->irq <= 0)
	406	return -EINVAL;
	407
	408	lpss = devm_kzalloc(dev, sizeof(*lpss), GFP_KERNEL);
	409	if (!lpss)
	410	return -ENOMEM;
	411
933d4644 AK	412	if (dmi_check_system(mtrr_large_wc_region))
	413	lpss->priv = devm_ioremap_uc(dev, info->mem->start + LPSS_PRIV_OFFSET,
	414	LPSS_PRIV_SIZE);
	415	else
	416	lpss->priv = devm_ioremap(dev, info->mem->start + LPSS_PRIV_OFFSET,
	417	LPSS_PRIV_SIZE);
4b45efe8 AS	418	if (!lpss->priv)
	419	return -ENOMEM;
	420
	421	lpss->info = info;
	422	lpss->dev = dev;
	423	lpss->caps = readl(lpss->priv + LPSS_PRIV_CAPS);
	424
	425	dev_set_drvdata(dev, lpss);
	426
	427	ret = intel_lpss_assign_devs(lpss);
	428	if (ret)
	429	return ret;
	430
f4d05266	431	lpss->cell->properties = info->properties;
e15ad215	432
4b45efe8 AS	433	intel_lpss_init_dev(lpss);
	434
	435	lpss->devid = ida_simple_get(&intel_lpss_devid_ida, 0, 0, GFP_KERNEL);
	436	if (lpss->devid < 0)
	437	return lpss->devid;
	438
	439	ret = intel_lpss_register_clock(lpss);
	440	if (ret)
	441	goto err_clk_register;
	442
	443	intel_lpss_ltr_expose(lpss);
	444
	445	ret = intel_lpss_debugfs_add(lpss);
	446	if (ret)
	447	dev_warn(dev, "Failed to create debugfs entries\n");
	448
	449	if (intel_lpss_has_idma(lpss)) {
	450	/*
	451	* Ensure the DMA driver is loaded before the host
	452	* controller device appears, so that the host controller
	453	* driver can request its DMA channels as early as
	454	* possible.
	455	*
	456	* If the DMA module is not there that's OK as well.
	457	*/
	458	intel_lpss_request_dma_module(LPSS_IDMA64_DRIVER_NAME);
	459
	460	ret = mfd_add_devices(dev, lpss->devid, &intel_lpss_idma64_cell,
	461	1, info->mem, info->irq, NULL);
	462	if (ret)
	463	dev_warn(dev, "Failed to add %s, fallback to PIO\n",
	464	LPSS_IDMA64_DRIVER_NAME);
	465	}
	466
	467	ret = mfd_add_devices(dev, lpss->devid, lpss->cell,
	468	1, info->mem, info->irq, NULL);
	469	if (ret)
	470	goto err_remove_ltr;
	471
	472	return 0;
	473
	474	err_remove_ltr:
	475	intel_lpss_debugfs_remove(lpss);
	476	intel_lpss_ltr_hide(lpss);
84cb36ca	477	intel_lpss_unregister_clock(lpss);
4b45efe8 AS	478
	479	err_clk_register:
	480	ida_simple_remove(&intel_lpss_devid_ida, lpss->devid);
	481
	482	return ret;
	483	}
	484	EXPORT_SYMBOL_GPL(intel_lpss_probe);
	485
	486	void intel_lpss_remove(struct device *dev)
	487	{
	488	struct intel_lpss *lpss = dev_get_drvdata(dev);
	489
	490	mfd_remove_devices(dev);
	491	intel_lpss_debugfs_remove(lpss);
	492	intel_lpss_ltr_hide(lpss);
	493	intel_lpss_unregister_clock(lpss);
	494	ida_simple_remove(&intel_lpss_devid_ida, lpss->devid);
	495	}
	496	EXPORT_SYMBOL_GPL(intel_lpss_remove);
	497
	498	static int resume_lpss_device(struct device dev, void data)
	499	{
	500	pm_runtime_resume(dev);
	501	return 0;
	502	}
	503
	504	int intel_lpss_prepare(struct device *dev)
	505	{
	506	/*
	507	* Resume both child devices before entering system sleep. This
	508	* ensures that they are in proper state before they get suspended.
	509	*/
	510	device_for_each_child_reverse(dev, NULL, resume_lpss_device);
	511	return 0;
	512	}
	513	EXPORT_SYMBOL_GPL(intel_lpss_prepare);
	514
	515	int intel_lpss_suspend(struct device *dev)
	516	{
41a3da2b HK	517	struct intel_lpss *lpss = dev_get_drvdata(dev);
	518	unsigned int i;
	519
	520	/* Save device context */
	521	for (i = 0; i < LPSS_PRIV_REG_COUNT; i++)
	522	lpss->priv_ctx[i] = readl(lpss->priv + i * 4);
	523
0b471aaa FS	524	/*
	525	* If the device type is not UART, then put the controller into
	526	* reset. UART cannot be put into reset since S3/S0ix fail when
	527	* no_console_suspend flag is enabled.
	528	*/
	529	if (lpss->type != LPSS_DEV_UART)
	530	writel(0, lpss->priv + LPSS_PRIV_RESETS);
	531
4b45efe8 AS	532	return 0;
	533	}
	534	EXPORT_SYMBOL_GPL(intel_lpss_suspend);
	535
	536	int intel_lpss_resume(struct device *dev)
	537	{
	538	struct intel_lpss *lpss = dev_get_drvdata(dev);
41a3da2b	539	unsigned int i;
4b45efe8	540
41a3da2b HK	541	intel_lpss_deassert_reset(lpss);
	542
	543	/* Restore device context */
	544	for (i = 0; i < LPSS_PRIV_REG_COUNT; i++)
	545	writel(lpss->priv_ctx[i], lpss->priv + i * 4);
4b45efe8 AS	546
	547	return 0;
	548	}
	549	EXPORT_SYMBOL_GPL(intel_lpss_resume);
	550
	551	static int __init intel_lpss_init(void)
	552	{
	553	intel_lpss_debugfs = debugfs_create_dir("intel_lpss", NULL);
	554	return 0;
	555	}
	556	module_init(intel_lpss_init);
	557
	558	static void __exit intel_lpss_exit(void)
	559	{
b2f9710a	560	ida_destroy(&intel_lpss_devid_ida);
4b45efe8 AS	561	debugfs_remove(intel_lpss_debugfs);
	562	}
	563	module_exit(intel_lpss_exit);
	564
	565	MODULE_AUTHOR("Andy Shevchenko <andriy.shevchenko@linux.intel.com>");
	566	MODULE_AUTHOR("Mika Westerberg <mika.westerberg@linux.intel.com>");
	567	MODULE_AUTHOR("Heikki Krogerus <heikki.krogerus@linux.intel.com>");
	568	MODULE_AUTHOR("Jarkko Nikula <jarkko.nikula@linux.intel.com>");
	569	MODULE_DESCRIPTION("Intel LPSS core driver");
	570	MODULE_LICENSE("GPL v2");