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Commit | Line | Data |
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01636eb9 PR |
1 | /* |
2 | * TI Touch Screen / ADC MFD driver | |
3 | * | |
4 | * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/ | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or | |
7 | * modify it under the terms of the GNU General Public License as | |
8 | * published by the Free Software Foundation version 2. | |
9 | * | |
10 | * This program is distributed "as is" WITHOUT ANY WARRANTY of any | |
11 | * kind, whether express or implied; without even the implied warranty | |
12 | * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
13 | * GNU General Public License for more details. | |
14 | */ | |
15 | ||
16 | #include <linux/module.h> | |
01636eb9 PR |
17 | #include <linux/slab.h> |
18 | #include <linux/err.h> | |
19 | #include <linux/io.h> | |
20 | #include <linux/clk.h> | |
21 | #include <linux/regmap.h> | |
22 | #include <linux/mfd/core.h> | |
23 | #include <linux/pm_runtime.h> | |
a6543a1c PR |
24 | #include <linux/of.h> |
25 | #include <linux/of_device.h> | |
7ca6740c | 26 | #include <linux/sched.h> |
01636eb9 PR |
27 | |
28 | #include <linux/mfd/ti_am335x_tscadc.h> | |
29 | ||
01636eb9 PR |
30 | static const struct regmap_config tscadc_regmap_config = { |
31 | .name = "ti_tscadc", | |
32 | .reg_bits = 32, | |
33 | .reg_stride = 4, | |
34 | .val_bits = 32, | |
35 | }; | |
36 | ||
a318b7d0 | 37 | void am335x_tsc_se_set_cache(struct ti_tscadc_dev *tscadc, u32 val) |
abeccee4 | 38 | { |
317b2099 SAS |
39 | unsigned long flags; |
40 | ||
a318b7d0 AD |
41 | spin_lock_irqsave(&tscadc->reg_lock, flags); |
42 | tscadc->reg_se_cache |= val; | |
43 | if (tscadc->adc_waiting) | |
44 | wake_up(&tscadc->reg_se_wait); | |
45 | else if (!tscadc->adc_in_use) | |
0d3a7cce | 46 | regmap_write(tscadc->regmap, REG_SE, tscadc->reg_se_cache); |
7ca6740c | 47 | |
a318b7d0 | 48 | spin_unlock_irqrestore(&tscadc->reg_lock, flags); |
abeccee4 | 49 | } |
7e170c6e SAS |
50 | EXPORT_SYMBOL_GPL(am335x_tsc_se_set_cache); |
51 | ||
a318b7d0 | 52 | static void am335x_tscadc_need_adc(struct ti_tscadc_dev *tscadc) |
7ca6740c SAS |
53 | { |
54 | DEFINE_WAIT(wait); | |
55 | u32 reg; | |
56 | ||
0d3a7cce | 57 | regmap_read(tscadc->regmap, REG_ADCFSM, ®); |
7ca6740c | 58 | if (reg & SEQ_STATUS) { |
a318b7d0 AD |
59 | tscadc->adc_waiting = true; |
60 | prepare_to_wait(&tscadc->reg_se_wait, &wait, | |
7ca6740c | 61 | TASK_UNINTERRUPTIBLE); |
a318b7d0 | 62 | spin_unlock_irq(&tscadc->reg_lock); |
7ca6740c SAS |
63 | |
64 | schedule(); | |
65 | ||
a318b7d0 AD |
66 | spin_lock_irq(&tscadc->reg_lock); |
67 | finish_wait(&tscadc->reg_se_wait, &wait); | |
7ca6740c | 68 | |
b10848e6 V |
69 | /* |
70 | * Sequencer should either be idle or | |
71 | * busy applying the charge step. | |
72 | */ | |
0d3a7cce | 73 | regmap_read(tscadc->regmap, REG_ADCFSM, ®); |
b10848e6 | 74 | WARN_ON((reg & SEQ_STATUS) && !(reg & CHARGE_STEP)); |
a318b7d0 | 75 | tscadc->adc_waiting = false; |
7ca6740c | 76 | } |
a318b7d0 | 77 | tscadc->adc_in_use = true; |
7ca6740c SAS |
78 | } |
79 | ||
a318b7d0 | 80 | void am335x_tsc_se_set_once(struct ti_tscadc_dev *tscadc, u32 val) |
7ca6740c | 81 | { |
a318b7d0 AD |
82 | spin_lock_irq(&tscadc->reg_lock); |
83 | am335x_tscadc_need_adc(tscadc); | |
7ca6740c | 84 | |
0d3a7cce | 85 | regmap_write(tscadc->regmap, REG_SE, val); |
a318b7d0 | 86 | spin_unlock_irq(&tscadc->reg_lock); |
7ca6740c SAS |
87 | } |
88 | EXPORT_SYMBOL_GPL(am335x_tsc_se_set_once); | |
89 | ||
a318b7d0 | 90 | void am335x_tsc_se_adc_done(struct ti_tscadc_dev *tscadc) |
7e170c6e SAS |
91 | { |
92 | unsigned long flags; | |
93 | ||
a318b7d0 AD |
94 | spin_lock_irqsave(&tscadc->reg_lock, flags); |
95 | tscadc->adc_in_use = false; | |
0d3a7cce | 96 | regmap_write(tscadc->regmap, REG_SE, tscadc->reg_se_cache); |
a318b7d0 | 97 | spin_unlock_irqrestore(&tscadc->reg_lock, flags); |
7e170c6e | 98 | } |
7ca6740c | 99 | EXPORT_SYMBOL_GPL(am335x_tsc_se_adc_done); |
abeccee4 | 100 | |
a318b7d0 | 101 | void am335x_tsc_se_clr(struct ti_tscadc_dev *tscadc, u32 val) |
abeccee4 | 102 | { |
317b2099 SAS |
103 | unsigned long flags; |
104 | ||
a318b7d0 AD |
105 | spin_lock_irqsave(&tscadc->reg_lock, flags); |
106 | tscadc->reg_se_cache &= ~val; | |
0d3a7cce | 107 | regmap_write(tscadc->regmap, REG_SE, tscadc->reg_se_cache); |
a318b7d0 | 108 | spin_unlock_irqrestore(&tscadc->reg_lock, flags); |
abeccee4 PR |
109 | } |
110 | EXPORT_SYMBOL_GPL(am335x_tsc_se_clr); | |
111 | ||
a318b7d0 | 112 | static void tscadc_idle_config(struct ti_tscadc_dev *tscadc) |
01636eb9 PR |
113 | { |
114 | unsigned int idleconfig; | |
115 | ||
116 | idleconfig = STEPCONFIG_YNN | STEPCONFIG_INM_ADCREFM | | |
117 | STEPCONFIG_INP_ADCREFM | STEPCONFIG_YPN; | |
118 | ||
0d3a7cce | 119 | regmap_write(tscadc->regmap, REG_IDLECONFIG, idleconfig); |
01636eb9 PR |
120 | } |
121 | ||
612b95cd | 122 | static int ti_tscadc_probe(struct platform_device *pdev) |
01636eb9 PR |
123 | { |
124 | struct ti_tscadc_dev *tscadc; | |
125 | struct resource *res; | |
126 | struct clk *clk; | |
a6543a1c | 127 | struct device_node *node = pdev->dev.of_node; |
2b99bafa | 128 | struct mfd_cell *cell; |
18926ede SAS |
129 | struct property *prop; |
130 | const __be32 *cur; | |
131 | u32 val; | |
01636eb9 | 132 | int err, ctrl; |
e90f8754 | 133 | int clock_rate; |
a6543a1c | 134 | int tsc_wires = 0, adc_channels = 0, total_channels; |
18926ede | 135 | int readouts = 0; |
01636eb9 | 136 | |
9e5775f3 SAS |
137 | if (!pdev->dev.of_node) { |
138 | dev_err(&pdev->dev, "Could not find valid DT data.\n"); | |
01636eb9 PR |
139 | return -EINVAL; |
140 | } | |
141 | ||
9e5775f3 SAS |
142 | node = of_get_child_by_name(pdev->dev.of_node, "tsc"); |
143 | of_property_read_u32(node, "ti,wires", &tsc_wires); | |
18926ede | 144 | of_property_read_u32(node, "ti,coordiante-readouts", &readouts); |
a6543a1c | 145 | |
9e5775f3 | 146 | node = of_get_child_by_name(pdev->dev.of_node, "adc"); |
18926ede SAS |
147 | of_property_for_each_u32(node, "ti,adc-channels", prop, cur, val) { |
148 | adc_channels++; | |
149 | if (val > 7) { | |
150 | dev_err(&pdev->dev, " PIN numbers are 0..7 (not %d)\n", | |
151 | val); | |
152 | return -EINVAL; | |
153 | } | |
154 | } | |
5e53a69b | 155 | total_channels = tsc_wires + adc_channels; |
5e53a69b PR |
156 | if (total_channels > 8) { |
157 | dev_err(&pdev->dev, "Number of i/p channels more than 8\n"); | |
158 | return -EINVAL; | |
159 | } | |
24d5c82f PA |
160 | if (total_channels == 0) { |
161 | dev_err(&pdev->dev, "Need atleast one channel.\n"); | |
162 | return -EINVAL; | |
163 | } | |
2b99bafa | 164 | |
18926ede SAS |
165 | if (readouts * 2 + 2 + adc_channels > 16) { |
166 | dev_err(&pdev->dev, "Too many step configurations requested\n"); | |
167 | return -EINVAL; | |
168 | } | |
169 | ||
01636eb9 | 170 | /* Allocate memory for device */ |
dea1c703 | 171 | tscadc = devm_kzalloc(&pdev->dev, sizeof(*tscadc), GFP_KERNEL); |
01636eb9 PR |
172 | if (!tscadc) { |
173 | dev_err(&pdev->dev, "failed to allocate memory.\n"); | |
174 | return -ENOMEM; | |
175 | } | |
176 | tscadc->dev = &pdev->dev; | |
3c39c9c6 PR |
177 | |
178 | err = platform_get_irq(pdev, 0); | |
179 | if (err < 0) { | |
180 | dev_err(&pdev->dev, "no irq ID is specified.\n"); | |
181 | goto ret; | |
182 | } else | |
183 | tscadc->irq = err; | |
01636eb9 | 184 | |
924ff918 JH |
185 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
186 | tscadc->tscadc_base = devm_ioremap_resource(&pdev->dev, res); | |
187 | if (IS_ERR(tscadc->tscadc_base)) | |
188 | return PTR_ERR(tscadc->tscadc_base); | |
01636eb9 | 189 | |
0d3a7cce | 190 | tscadc->regmap = devm_regmap_init_mmio(&pdev->dev, |
01636eb9 | 191 | tscadc->tscadc_base, &tscadc_regmap_config); |
0d3a7cce | 192 | if (IS_ERR(tscadc->regmap)) { |
01636eb9 | 193 | dev_err(&pdev->dev, "regmap init failed\n"); |
0d3a7cce | 194 | err = PTR_ERR(tscadc->regmap); |
3c39c9c6 | 195 | goto ret; |
01636eb9 PR |
196 | } |
197 | ||
abeccee4 | 198 | spin_lock_init(&tscadc->reg_lock); |
7ca6740c SAS |
199 | init_waitqueue_head(&tscadc->reg_se_wait); |
200 | ||
01636eb9 PR |
201 | pm_runtime_enable(&pdev->dev); |
202 | pm_runtime_get_sync(&pdev->dev); | |
203 | ||
204 | /* | |
205 | * The TSC_ADC_Subsystem has 2 clock domains | |
206 | * OCP_CLK and ADC_CLK. | |
207 | * The ADC clock is expected to run at target of 3MHz, | |
208 | * and expected to capture 12-bit data at a rate of 200 KSPS. | |
209 | * The TSC_ADC_SS controller design assumes the OCP clock is | |
210 | * at least 6x faster than the ADC clock. | |
211 | */ | |
212 | clk = clk_get(&pdev->dev, "adc_tsc_fck"); | |
213 | if (IS_ERR(clk)) { | |
214 | dev_err(&pdev->dev, "failed to get TSC fck\n"); | |
215 | err = PTR_ERR(clk); | |
216 | goto err_disable_clk; | |
217 | } | |
218 | clock_rate = clk_get_rate(clk); | |
219 | clk_put(clk); | |
e90f8754 | 220 | tscadc->clk_div = clock_rate / ADC_CLK; |
efe3126a | 221 | |
01636eb9 | 222 | /* TSCADC_CLKDIV needs to be configured to the value minus 1 */ |
e90f8754 | 223 | tscadc->clk_div--; |
0d3a7cce | 224 | regmap_write(tscadc->regmap, REG_CLKDIV, tscadc->clk_div); |
01636eb9 PR |
225 | |
226 | /* Set the control register bits */ | |
f0933a60 | 227 | ctrl = CNTRLREG_STEPCONFIGWRT | CNTRLREG_STEPID; |
0d3a7cce | 228 | regmap_write(tscadc->regmap, REG_CTRL, ctrl); |
01636eb9 PR |
229 | |
230 | /* Set register bits for Idle Config Mode */ | |
f0933a60 JL |
231 | if (tsc_wires > 0) { |
232 | tscadc->tsc_wires = tsc_wires; | |
233 | if (tsc_wires == 5) | |
234 | ctrl |= CNTRLREG_5WIRE | CNTRLREG_TSCENB; | |
235 | else | |
236 | ctrl |= CNTRLREG_4WIRE | CNTRLREG_TSCENB; | |
b5f8b763 | 237 | tscadc_idle_config(tscadc); |
f0933a60 | 238 | } |
01636eb9 PR |
239 | |
240 | /* Enable the TSC module enable bit */ | |
01636eb9 | 241 | ctrl |= CNTRLREG_TSCSSENB; |
0d3a7cce | 242 | regmap_write(tscadc->regmap, REG_CTRL, ctrl); |
01636eb9 | 243 | |
24d5c82f PA |
244 | tscadc->used_cells = 0; |
245 | tscadc->tsc_cell = -1; | |
246 | tscadc->adc_cell = -1; | |
247 | ||
2b99bafa | 248 | /* TSC Cell */ |
24d5c82f PA |
249 | if (tsc_wires > 0) { |
250 | tscadc->tsc_cell = tscadc->used_cells; | |
251 | cell = &tscadc->cells[tscadc->used_cells++]; | |
5f184e63 | 252 | cell->name = "TI-am335x-tsc"; |
24d5c82f PA |
253 | cell->of_compatible = "ti,am3359-tsc"; |
254 | cell->platform_data = &tscadc; | |
255 | cell->pdata_size = sizeof(tscadc); | |
256 | } | |
2b99bafa | 257 | |
5e53a69b | 258 | /* ADC Cell */ |
24d5c82f PA |
259 | if (adc_channels > 0) { |
260 | tscadc->adc_cell = tscadc->used_cells; | |
261 | cell = &tscadc->cells[tscadc->used_cells++]; | |
9f99928f | 262 | cell->name = "TI-am335x-adc"; |
24d5c82f PA |
263 | cell->of_compatible = "ti,am3359-adc"; |
264 | cell->platform_data = &tscadc; | |
265 | cell->pdata_size = sizeof(tscadc); | |
266 | } | |
5e53a69b | 267 | |
01636eb9 | 268 | err = mfd_add_devices(&pdev->dev, pdev->id, tscadc->cells, |
24d5c82f | 269 | tscadc->used_cells, NULL, 0, NULL); |
01636eb9 PR |
270 | if (err < 0) |
271 | goto err_disable_clk; | |
272 | ||
273 | device_init_wakeup(&pdev->dev, true); | |
274 | platform_set_drvdata(pdev, tscadc); | |
01636eb9 PR |
275 | return 0; |
276 | ||
277 | err_disable_clk: | |
278 | pm_runtime_put_sync(&pdev->dev); | |
279 | pm_runtime_disable(&pdev->dev); | |
3c39c9c6 | 280 | ret: |
01636eb9 PR |
281 | return err; |
282 | } | |
283 | ||
612b95cd | 284 | static int ti_tscadc_remove(struct platform_device *pdev) |
01636eb9 PR |
285 | { |
286 | struct ti_tscadc_dev *tscadc = platform_get_drvdata(pdev); | |
287 | ||
0d3a7cce | 288 | regmap_write(tscadc->regmap, REG_SE, 0x00); |
01636eb9 PR |
289 | |
290 | pm_runtime_put_sync(&pdev->dev); | |
291 | pm_runtime_disable(&pdev->dev); | |
292 | ||
293 | mfd_remove_devices(tscadc->dev); | |
294 | ||
295 | return 0; | |
296 | } | |
297 | ||
dae936a0 | 298 | static int __maybe_unused tscadc_suspend(struct device *dev) |
01636eb9 | 299 | { |
a318b7d0 | 300 | struct ti_tscadc_dev *tscadc = dev_get_drvdata(dev); |
01636eb9 | 301 | |
0d3a7cce | 302 | regmap_write(tscadc->regmap, REG_SE, 0x00); |
01636eb9 PR |
303 | pm_runtime_put_sync(dev); |
304 | ||
305 | return 0; | |
306 | } | |
307 | ||
dae936a0 | 308 | static int __maybe_unused tscadc_resume(struct device *dev) |
01636eb9 | 309 | { |
a318b7d0 | 310 | struct ti_tscadc_dev *tscadc = dev_get_drvdata(dev); |
f0933a60 | 311 | u32 ctrl; |
01636eb9 PR |
312 | |
313 | pm_runtime_get_sync(dev); | |
314 | ||
315 | /* context restore */ | |
b5f8b763 | 316 | ctrl = CNTRLREG_STEPCONFIGWRT | CNTRLREG_STEPID; |
0d3a7cce | 317 | regmap_write(tscadc->regmap, REG_CTRL, ctrl); |
b5f8b763 | 318 | |
a318b7d0 AD |
319 | if (tscadc->tsc_cell != -1) { |
320 | if (tscadc->tsc_wires == 5) | |
f0933a60 JL |
321 | ctrl |= CNTRLREG_5WIRE | CNTRLREG_TSCENB; |
322 | else | |
323 | ctrl |= CNTRLREG_4WIRE | CNTRLREG_TSCENB; | |
a318b7d0 | 324 | tscadc_idle_config(tscadc); |
f0933a60 JL |
325 | } |
326 | ctrl |= CNTRLREG_TSCSSENB; | |
0d3a7cce | 327 | regmap_write(tscadc->regmap, REG_CTRL, ctrl); |
01636eb9 | 328 | |
0d3a7cce | 329 | regmap_write(tscadc->regmap, REG_CLKDIV, tscadc->clk_div); |
e90f8754 | 330 | |
01636eb9 PR |
331 | return 0; |
332 | } | |
333 | ||
dae936a0 | 334 | static SIMPLE_DEV_PM_OPS(tscadc_pm_ops, tscadc_suspend, tscadc_resume); |
01636eb9 | 335 | |
a6543a1c PR |
336 | static const struct of_device_id ti_tscadc_dt_ids[] = { |
337 | { .compatible = "ti,am3359-tscadc", }, | |
338 | { } | |
339 | }; | |
340 | MODULE_DEVICE_TABLE(of, ti_tscadc_dt_ids); | |
341 | ||
01636eb9 PR |
342 | static struct platform_driver ti_tscadc_driver = { |
343 | .driver = { | |
a6543a1c | 344 | .name = "ti_am3359-tscadc", |
dae936a0 | 345 | .pm = &tscadc_pm_ops, |
131221bc | 346 | .of_match_table = ti_tscadc_dt_ids, |
01636eb9 PR |
347 | }, |
348 | .probe = ti_tscadc_probe, | |
612b95cd | 349 | .remove = ti_tscadc_remove, |
01636eb9 PR |
350 | |
351 | }; | |
352 | ||
353 | module_platform_driver(ti_tscadc_driver); | |
354 | ||
355 | MODULE_DESCRIPTION("TI touchscreen / ADC MFD controller driver"); | |
356 | MODULE_AUTHOR("Rachna Patil <rachna@ti.com>"); | |
357 | MODULE_LICENSE("GPL"); |