]>
Commit | Line | Data |
---|---|---|
cf4ece53 | 1 | /* |
1a738dcf | 2 | * Copyright (C) 2010 OKI SEMICONDUCTOR CO., LTD. |
cf4ece53 MO |
3 | * |
4 | * This program is free software; you can redistribute it and/or modify | |
5 | * it under the terms of the GNU General Public License as published by | |
6 | * the Free Software Foundation; version 2 of the License. | |
7 | * | |
8 | * This program is distributed in the hope that it will be useful, | |
9 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
10 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
11 | * GNU General Public License for more details. | |
12 | * | |
13 | * You should have received a copy of the GNU General Public License | |
14 | * along with this program; if not, write to the Free Software | |
15 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA. | |
16 | */ | |
17 | ||
18 | #include <linux/module.h> | |
19 | #include <linux/kernel.h> | |
20 | #include <linux/types.h> | |
21 | #include <linux/fs.h> | |
22 | #include <linux/uaccess.h> | |
23 | #include <linux/string.h> | |
24 | #include <linux/pci.h> | |
25 | #include <linux/io.h> | |
26 | #include <linux/delay.h> | |
27 | #include <linux/mutex.h> | |
28 | #include <linux/if_ether.h> | |
29 | #include <linux/ctype.h> | |
30 | ||
31 | #define PHUB_STATUS 0x00 /* Status Register offset */ | |
32 | #define PHUB_CONTROL 0x04 /* Control Register offset */ | |
33 | #define PHUB_TIMEOUT 0x05 /* Time out value for Status Register */ | |
34 | #define PCH_PHUB_ROM_WRITE_ENABLE 0x01 /* Enabling for writing ROM */ | |
35 | #define PCH_PHUB_ROM_WRITE_DISABLE 0x00 /* Disabling for writing ROM */ | |
1a738dcf TM |
36 | #define PCH_PHUB_MAC_START_ADDR 0x20C /* MAC data area start address offset */ |
37 | #define PCH_PHUB_ROM_START_ADDR_EG20T 0x14 /* ROM data area start address offset | |
38 | (Intel EG20T PCH)*/ | |
39 | #define PCH_PHUB_ROM_START_ADDR_ML7213 0x400 /* ROM data area start address | |
40 | offset(OKI SEMICONDUCTOR ML7213) | |
41 | */ | |
cf4ece53 MO |
42 | |
43 | /* MAX number of INT_REDUCE_CONTROL registers */ | |
44 | #define MAX_NUM_INT_REDUCE_CONTROL_REG 128 | |
45 | #define PCI_DEVICE_ID_PCH1_PHUB 0x8801 | |
46 | #define PCH_MINOR_NOS 1 | |
47 | #define CLKCFG_CAN_50MHZ 0x12000000 | |
48 | #define CLKCFG_CANCLK_MASK 0xFF000000 | |
49 | ||
1a738dcf TM |
50 | /* Macros for ML7213 */ |
51 | #define PCI_VENDOR_ID_ROHM 0x10db | |
52 | #define PCI_DEVICE_ID_ROHM_ML7213_PHUB 0x801A | |
53 | ||
cf4ece53 MO |
54 | /* SROM ACCESS Macro */ |
55 | #define PCH_WORD_ADDR_MASK (~((1 << 2) - 1)) | |
56 | ||
57 | /* Registers address offset */ | |
58 | #define PCH_PHUB_ID_REG 0x0000 | |
59 | #define PCH_PHUB_QUEUE_PRI_VAL_REG 0x0004 | |
60 | #define PCH_PHUB_RC_QUEUE_MAXSIZE_REG 0x0008 | |
61 | #define PCH_PHUB_BRI_QUEUE_MAXSIZE_REG 0x000C | |
62 | #define PCH_PHUB_COMP_RESP_TIMEOUT_REG 0x0010 | |
63 | #define PCH_PHUB_BUS_SLAVE_CONTROL_REG 0x0014 | |
64 | #define PCH_PHUB_DEADLOCK_AVOID_TYPE_REG 0x0018 | |
65 | #define PCH_PHUB_INTPIN_REG_WPERMIT_REG0 0x0020 | |
66 | #define PCH_PHUB_INTPIN_REG_WPERMIT_REG1 0x0024 | |
67 | #define PCH_PHUB_INTPIN_REG_WPERMIT_REG2 0x0028 | |
68 | #define PCH_PHUB_INTPIN_REG_WPERMIT_REG3 0x002C | |
69 | #define PCH_PHUB_INT_REDUCE_CONTROL_REG_BASE 0x0040 | |
70 | #define CLKCFG_REG_OFFSET 0x500 | |
71 | ||
72 | #define PCH_PHUB_OROM_SIZE 15360 | |
73 | ||
74 | /** | |
75 | * struct pch_phub_reg - PHUB register structure | |
76 | * @phub_id_reg: PHUB_ID register val | |
77 | * @q_pri_val_reg: QUEUE_PRI_VAL register val | |
78 | * @rc_q_maxsize_reg: RC_QUEUE_MAXSIZE register val | |
79 | * @bri_q_maxsize_reg: BRI_QUEUE_MAXSIZE register val | |
80 | * @comp_resp_timeout_reg: COMP_RESP_TIMEOUT register val | |
81 | * @bus_slave_control_reg: BUS_SLAVE_CONTROL_REG register val | |
82 | * @deadlock_avoid_type_reg: DEADLOCK_AVOID_TYPE register val | |
83 | * @intpin_reg_wpermit_reg0: INTPIN_REG_WPERMIT register 0 val | |
84 | * @intpin_reg_wpermit_reg1: INTPIN_REG_WPERMIT register 1 val | |
85 | * @intpin_reg_wpermit_reg2: INTPIN_REG_WPERMIT register 2 val | |
86 | * @intpin_reg_wpermit_reg3: INTPIN_REG_WPERMIT register 3 val | |
87 | * @int_reduce_control_reg: INT_REDUCE_CONTROL registers val | |
88 | * @clkcfg_reg: CLK CFG register val | |
89 | * @pch_phub_base_address: Register base address | |
90 | * @pch_phub_extrom_base_address: external rom base address | |
91 | */ | |
92 | struct pch_phub_reg { | |
93 | u32 phub_id_reg; | |
94 | u32 q_pri_val_reg; | |
95 | u32 rc_q_maxsize_reg; | |
96 | u32 bri_q_maxsize_reg; | |
97 | u32 comp_resp_timeout_reg; | |
98 | u32 bus_slave_control_reg; | |
99 | u32 deadlock_avoid_type_reg; | |
100 | u32 intpin_reg_wpermit_reg0; | |
101 | u32 intpin_reg_wpermit_reg1; | |
102 | u32 intpin_reg_wpermit_reg2; | |
103 | u32 intpin_reg_wpermit_reg3; | |
104 | u32 int_reduce_control_reg[MAX_NUM_INT_REDUCE_CONTROL_REG]; | |
105 | u32 clkcfg_reg; | |
106 | void __iomem *pch_phub_base_address; | |
107 | void __iomem *pch_phub_extrom_base_address; | |
108 | }; | |
109 | ||
110 | /* SROM SPEC for MAC address assignment offset */ | |
111 | static const int pch_phub_mac_offset[ETH_ALEN] = {0x3, 0x2, 0x1, 0x0, 0xb, 0xa}; | |
112 | ||
113 | static DEFINE_MUTEX(pch_phub_mutex); | |
114 | ||
115 | /** | |
116 | * pch_phub_read_modify_write_reg() - Reading modifying and writing register | |
117 | * @reg_addr_offset: Register offset address value. | |
118 | * @data: Writing value. | |
119 | * @mask: Mask value. | |
120 | */ | |
121 | static void pch_phub_read_modify_write_reg(struct pch_phub_reg *chip, | |
122 | unsigned int reg_addr_offset, | |
123 | unsigned int data, unsigned int mask) | |
124 | { | |
125 | void __iomem *reg_addr = chip->pch_phub_base_address + reg_addr_offset; | |
126 | iowrite32(((ioread32(reg_addr) & ~mask)) | data, reg_addr); | |
127 | } | |
128 | ||
129 | /* pch_phub_save_reg_conf - saves register configuration */ | |
130 | static void pch_phub_save_reg_conf(struct pci_dev *pdev) | |
131 | { | |
132 | unsigned int i; | |
133 | struct pch_phub_reg *chip = pci_get_drvdata(pdev); | |
134 | ||
135 | void __iomem *p = chip->pch_phub_base_address; | |
136 | ||
137 | chip->phub_id_reg = ioread32(p + PCH_PHUB_ID_REG); | |
138 | chip->q_pri_val_reg = ioread32(p + PCH_PHUB_QUEUE_PRI_VAL_REG); | |
139 | chip->rc_q_maxsize_reg = ioread32(p + PCH_PHUB_RC_QUEUE_MAXSIZE_REG); | |
140 | chip->bri_q_maxsize_reg = ioread32(p + PCH_PHUB_BRI_QUEUE_MAXSIZE_REG); | |
141 | chip->comp_resp_timeout_reg = | |
142 | ioread32(p + PCH_PHUB_COMP_RESP_TIMEOUT_REG); | |
143 | chip->bus_slave_control_reg = | |
144 | ioread32(p + PCH_PHUB_BUS_SLAVE_CONTROL_REG); | |
145 | chip->deadlock_avoid_type_reg = | |
146 | ioread32(p + PCH_PHUB_DEADLOCK_AVOID_TYPE_REG); | |
147 | chip->intpin_reg_wpermit_reg0 = | |
148 | ioread32(p + PCH_PHUB_INTPIN_REG_WPERMIT_REG0); | |
149 | chip->intpin_reg_wpermit_reg1 = | |
150 | ioread32(p + PCH_PHUB_INTPIN_REG_WPERMIT_REG1); | |
151 | chip->intpin_reg_wpermit_reg2 = | |
152 | ioread32(p + PCH_PHUB_INTPIN_REG_WPERMIT_REG2); | |
153 | chip->intpin_reg_wpermit_reg3 = | |
154 | ioread32(p + PCH_PHUB_INTPIN_REG_WPERMIT_REG3); | |
155 | dev_dbg(&pdev->dev, "%s : " | |
156 | "chip->phub_id_reg=%x, " | |
157 | "chip->q_pri_val_reg=%x, " | |
158 | "chip->rc_q_maxsize_reg=%x, " | |
159 | "chip->bri_q_maxsize_reg=%x, " | |
160 | "chip->comp_resp_timeout_reg=%x, " | |
161 | "chip->bus_slave_control_reg=%x, " | |
162 | "chip->deadlock_avoid_type_reg=%x, " | |
163 | "chip->intpin_reg_wpermit_reg0=%x, " | |
164 | "chip->intpin_reg_wpermit_reg1=%x, " | |
165 | "chip->intpin_reg_wpermit_reg2=%x, " | |
166 | "chip->intpin_reg_wpermit_reg3=%x\n", __func__, | |
167 | chip->phub_id_reg, | |
168 | chip->q_pri_val_reg, | |
169 | chip->rc_q_maxsize_reg, | |
170 | chip->bri_q_maxsize_reg, | |
171 | chip->comp_resp_timeout_reg, | |
172 | chip->bus_slave_control_reg, | |
173 | chip->deadlock_avoid_type_reg, | |
174 | chip->intpin_reg_wpermit_reg0, | |
175 | chip->intpin_reg_wpermit_reg1, | |
176 | chip->intpin_reg_wpermit_reg2, | |
177 | chip->intpin_reg_wpermit_reg3); | |
178 | for (i = 0; i < MAX_NUM_INT_REDUCE_CONTROL_REG; i++) { | |
179 | chip->int_reduce_control_reg[i] = | |
180 | ioread32(p + PCH_PHUB_INT_REDUCE_CONTROL_REG_BASE + 4 * i); | |
181 | dev_dbg(&pdev->dev, "%s : " | |
182 | "chip->int_reduce_control_reg[%d]=%x\n", | |
183 | __func__, i, chip->int_reduce_control_reg[i]); | |
184 | } | |
185 | chip->clkcfg_reg = ioread32(p + CLKCFG_REG_OFFSET); | |
186 | } | |
187 | ||
188 | /* pch_phub_restore_reg_conf - restore register configuration */ | |
189 | static void pch_phub_restore_reg_conf(struct pci_dev *pdev) | |
190 | { | |
191 | unsigned int i; | |
192 | struct pch_phub_reg *chip = pci_get_drvdata(pdev); | |
193 | void __iomem *p; | |
194 | p = chip->pch_phub_base_address; | |
195 | ||
196 | iowrite32(chip->phub_id_reg, p + PCH_PHUB_ID_REG); | |
197 | iowrite32(chip->q_pri_val_reg, p + PCH_PHUB_QUEUE_PRI_VAL_REG); | |
198 | iowrite32(chip->rc_q_maxsize_reg, p + PCH_PHUB_RC_QUEUE_MAXSIZE_REG); | |
199 | iowrite32(chip->bri_q_maxsize_reg, p + PCH_PHUB_BRI_QUEUE_MAXSIZE_REG); | |
200 | iowrite32(chip->comp_resp_timeout_reg, | |
201 | p + PCH_PHUB_COMP_RESP_TIMEOUT_REG); | |
202 | iowrite32(chip->bus_slave_control_reg, | |
203 | p + PCH_PHUB_BUS_SLAVE_CONTROL_REG); | |
204 | iowrite32(chip->deadlock_avoid_type_reg, | |
205 | p + PCH_PHUB_DEADLOCK_AVOID_TYPE_REG); | |
206 | iowrite32(chip->intpin_reg_wpermit_reg0, | |
207 | p + PCH_PHUB_INTPIN_REG_WPERMIT_REG0); | |
208 | iowrite32(chip->intpin_reg_wpermit_reg1, | |
209 | p + PCH_PHUB_INTPIN_REG_WPERMIT_REG1); | |
210 | iowrite32(chip->intpin_reg_wpermit_reg2, | |
211 | p + PCH_PHUB_INTPIN_REG_WPERMIT_REG2); | |
212 | iowrite32(chip->intpin_reg_wpermit_reg3, | |
213 | p + PCH_PHUB_INTPIN_REG_WPERMIT_REG3); | |
214 | dev_dbg(&pdev->dev, "%s : " | |
215 | "chip->phub_id_reg=%x, " | |
216 | "chip->q_pri_val_reg=%x, " | |
217 | "chip->rc_q_maxsize_reg=%x, " | |
218 | "chip->bri_q_maxsize_reg=%x, " | |
219 | "chip->comp_resp_timeout_reg=%x, " | |
220 | "chip->bus_slave_control_reg=%x, " | |
221 | "chip->deadlock_avoid_type_reg=%x, " | |
222 | "chip->intpin_reg_wpermit_reg0=%x, " | |
223 | "chip->intpin_reg_wpermit_reg1=%x, " | |
224 | "chip->intpin_reg_wpermit_reg2=%x, " | |
225 | "chip->intpin_reg_wpermit_reg3=%x\n", __func__, | |
226 | chip->phub_id_reg, | |
227 | chip->q_pri_val_reg, | |
228 | chip->rc_q_maxsize_reg, | |
229 | chip->bri_q_maxsize_reg, | |
230 | chip->comp_resp_timeout_reg, | |
231 | chip->bus_slave_control_reg, | |
232 | chip->deadlock_avoid_type_reg, | |
233 | chip->intpin_reg_wpermit_reg0, | |
234 | chip->intpin_reg_wpermit_reg1, | |
235 | chip->intpin_reg_wpermit_reg2, | |
236 | chip->intpin_reg_wpermit_reg3); | |
237 | for (i = 0; i < MAX_NUM_INT_REDUCE_CONTROL_REG; i++) { | |
238 | iowrite32(chip->int_reduce_control_reg[i], | |
239 | p + PCH_PHUB_INT_REDUCE_CONTROL_REG_BASE + 4 * i); | |
240 | dev_dbg(&pdev->dev, "%s : " | |
241 | "chip->int_reduce_control_reg[%d]=%x\n", | |
242 | __func__, i, chip->int_reduce_control_reg[i]); | |
243 | } | |
244 | ||
245 | iowrite32(chip->clkcfg_reg, p + CLKCFG_REG_OFFSET); | |
246 | } | |
247 | ||
248 | /** | |
249 | * pch_phub_read_serial_rom() - Reading Serial ROM | |
250 | * @offset_address: Serial ROM offset address to read. | |
251 | * @data: Read buffer for specified Serial ROM value. | |
252 | */ | |
253 | static void pch_phub_read_serial_rom(struct pch_phub_reg *chip, | |
254 | unsigned int offset_address, u8 *data) | |
255 | { | |
256 | void __iomem *mem_addr = chip->pch_phub_extrom_base_address + | |
257 | offset_address; | |
258 | ||
259 | *data = ioread8(mem_addr); | |
260 | } | |
261 | ||
262 | /** | |
263 | * pch_phub_write_serial_rom() - Writing Serial ROM | |
264 | * @offset_address: Serial ROM offset address. | |
265 | * @data: Serial ROM value to write. | |
266 | */ | |
267 | static int pch_phub_write_serial_rom(struct pch_phub_reg *chip, | |
268 | unsigned int offset_address, u8 data) | |
269 | { | |
270 | void __iomem *mem_addr = chip->pch_phub_extrom_base_address + | |
271 | (offset_address & PCH_WORD_ADDR_MASK); | |
272 | int i; | |
273 | unsigned int word_data; | |
274 | unsigned int pos; | |
275 | unsigned int mask; | |
276 | pos = (offset_address % 4) * 8; | |
277 | mask = ~(0xFF << pos); | |
278 | ||
279 | iowrite32(PCH_PHUB_ROM_WRITE_ENABLE, | |
280 | chip->pch_phub_extrom_base_address + PHUB_CONTROL); | |
281 | ||
282 | word_data = ioread32(mem_addr); | |
283 | iowrite32((word_data & mask) | (u32)data << pos, mem_addr); | |
284 | ||
285 | i = 0; | |
286 | while (ioread8(chip->pch_phub_extrom_base_address + | |
287 | PHUB_STATUS) != 0x00) { | |
288 | msleep(1); | |
289 | if (i == PHUB_TIMEOUT) | |
290 | return -ETIMEDOUT; | |
291 | i++; | |
292 | } | |
293 | ||
294 | iowrite32(PCH_PHUB_ROM_WRITE_DISABLE, | |
295 | chip->pch_phub_extrom_base_address + PHUB_CONTROL); | |
296 | ||
297 | return 0; | |
298 | } | |
299 | ||
300 | /** | |
301 | * pch_phub_read_serial_rom_val() - Read Serial ROM value | |
302 | * @offset_address: Serial ROM address offset value. | |
303 | * @data: Serial ROM value to read. | |
304 | */ | |
305 | static void pch_phub_read_serial_rom_val(struct pch_phub_reg *chip, | |
306 | unsigned int offset_address, u8 *data) | |
307 | { | |
308 | unsigned int mem_addr; | |
309 | ||
1a738dcf | 310 | mem_addr = PCH_PHUB_ROM_START_ADDR_EG20T + |
cf4ece53 MO |
311 | pch_phub_mac_offset[offset_address]; |
312 | ||
313 | pch_phub_read_serial_rom(chip, mem_addr, data); | |
314 | } | |
315 | ||
316 | /** | |
317 | * pch_phub_write_serial_rom_val() - writing Serial ROM value | |
318 | * @offset_address: Serial ROM address offset value. | |
319 | * @data: Serial ROM value. | |
320 | */ | |
321 | static int pch_phub_write_serial_rom_val(struct pch_phub_reg *chip, | |
322 | unsigned int offset_address, u8 data) | |
323 | { | |
324 | int retval; | |
325 | unsigned int mem_addr; | |
326 | ||
1a738dcf | 327 | mem_addr = PCH_PHUB_ROM_START_ADDR_EG20T + |
cf4ece53 MO |
328 | pch_phub_mac_offset[offset_address]; |
329 | ||
330 | retval = pch_phub_write_serial_rom(chip, mem_addr, data); | |
331 | ||
332 | return retval; | |
333 | } | |
334 | ||
335 | /* pch_phub_gbe_serial_rom_conf - makes Serial ROM header format configuration | |
336 | * for Gigabit Ethernet MAC address | |
337 | */ | |
338 | static int pch_phub_gbe_serial_rom_conf(struct pch_phub_reg *chip) | |
339 | { | |
340 | int retval; | |
341 | ||
342 | retval = pch_phub_write_serial_rom(chip, 0x0b, 0xbc); | |
343 | retval |= pch_phub_write_serial_rom(chip, 0x0a, 0x10); | |
344 | retval |= pch_phub_write_serial_rom(chip, 0x09, 0x01); | |
345 | retval |= pch_phub_write_serial_rom(chip, 0x08, 0x02); | |
346 | ||
347 | retval |= pch_phub_write_serial_rom(chip, 0x0f, 0x00); | |
348 | retval |= pch_phub_write_serial_rom(chip, 0x0e, 0x00); | |
349 | retval |= pch_phub_write_serial_rom(chip, 0x0d, 0x00); | |
350 | retval |= pch_phub_write_serial_rom(chip, 0x0c, 0x80); | |
351 | ||
352 | retval |= pch_phub_write_serial_rom(chip, 0x13, 0xbc); | |
353 | retval |= pch_phub_write_serial_rom(chip, 0x12, 0x10); | |
354 | retval |= pch_phub_write_serial_rom(chip, 0x11, 0x01); | |
355 | retval |= pch_phub_write_serial_rom(chip, 0x10, 0x18); | |
356 | ||
357 | retval |= pch_phub_write_serial_rom(chip, 0x1b, 0xbc); | |
358 | retval |= pch_phub_write_serial_rom(chip, 0x1a, 0x10); | |
359 | retval |= pch_phub_write_serial_rom(chip, 0x19, 0x01); | |
360 | retval |= pch_phub_write_serial_rom(chip, 0x18, 0x19); | |
361 | ||
362 | retval |= pch_phub_write_serial_rom(chip, 0x23, 0xbc); | |
363 | retval |= pch_phub_write_serial_rom(chip, 0x22, 0x10); | |
364 | retval |= pch_phub_write_serial_rom(chip, 0x21, 0x01); | |
365 | retval |= pch_phub_write_serial_rom(chip, 0x20, 0x3a); | |
366 | ||
367 | retval |= pch_phub_write_serial_rom(chip, 0x27, 0x01); | |
368 | retval |= pch_phub_write_serial_rom(chip, 0x26, 0x00); | |
369 | retval |= pch_phub_write_serial_rom(chip, 0x25, 0x00); | |
370 | retval |= pch_phub_write_serial_rom(chip, 0x24, 0x00); | |
371 | ||
372 | return retval; | |
373 | } | |
374 | ||
375 | /** | |
376 | * pch_phub_read_gbe_mac_addr() - Read Gigabit Ethernet MAC address | |
377 | * @offset_address: Gigabit Ethernet MAC address offset value. | |
378 | * @data: Buffer of the Gigabit Ethernet MAC address value. | |
379 | */ | |
380 | static void pch_phub_read_gbe_mac_addr(struct pch_phub_reg *chip, u8 *data) | |
381 | { | |
382 | int i; | |
383 | for (i = 0; i < ETH_ALEN; i++) | |
384 | pch_phub_read_serial_rom_val(chip, i, &data[i]); | |
385 | } | |
386 | ||
387 | /** | |
388 | * pch_phub_write_gbe_mac_addr() - Write MAC address | |
389 | * @offset_address: Gigabit Ethernet MAC address offset value. | |
390 | * @data: Gigabit Ethernet MAC address value. | |
391 | */ | |
392 | static int pch_phub_write_gbe_mac_addr(struct pch_phub_reg *chip, u8 *data) | |
393 | { | |
394 | int retval; | |
395 | int i; | |
396 | ||
397 | retval = pch_phub_gbe_serial_rom_conf(chip); | |
398 | if (retval) | |
399 | return retval; | |
400 | ||
401 | for (i = 0; i < ETH_ALEN; i++) { | |
402 | retval = pch_phub_write_serial_rom_val(chip, i, data[i]); | |
403 | if (retval) | |
404 | return retval; | |
405 | } | |
406 | ||
407 | return retval; | |
408 | } | |
409 | ||
410 | static ssize_t pch_phub_bin_read(struct file *filp, struct kobject *kobj, | |
411 | struct bin_attribute *attr, char *buf, | |
412 | loff_t off, size_t count) | |
413 | { | |
414 | unsigned int rom_signature; | |
415 | unsigned char rom_length; | |
416 | unsigned int tmp; | |
417 | unsigned int addr_offset; | |
418 | unsigned int orom_size; | |
419 | int ret; | |
420 | int err; | |
421 | ||
422 | struct pch_phub_reg *chip = | |
423 | dev_get_drvdata(container_of(kobj, struct device, kobj)); | |
424 | ||
425 | ret = mutex_lock_interruptible(&pch_phub_mutex); | |
426 | if (ret) { | |
427 | err = -ERESTARTSYS; | |
428 | goto return_err_nomutex; | |
429 | } | |
430 | ||
431 | /* Get Rom signature */ | |
432 | pch_phub_read_serial_rom(chip, 0x80, (unsigned char *)&rom_signature); | |
433 | rom_signature &= 0xff; | |
434 | pch_phub_read_serial_rom(chip, 0x81, (unsigned char *)&tmp); | |
435 | rom_signature |= (tmp & 0xff) << 8; | |
436 | if (rom_signature == 0xAA55) { | |
437 | pch_phub_read_serial_rom(chip, 0x82, &rom_length); | |
438 | orom_size = rom_length * 512; | |
439 | if (orom_size < off) { | |
440 | addr_offset = 0; | |
441 | goto return_ok; | |
442 | } | |
443 | if (orom_size < count) { | |
444 | addr_offset = 0; | |
445 | goto return_ok; | |
446 | } | |
447 | ||
448 | for (addr_offset = 0; addr_offset < count; addr_offset++) { | |
449 | pch_phub_read_serial_rom(chip, 0x80 + addr_offset + off, | |
450 | &buf[addr_offset]); | |
451 | } | |
452 | } else { | |
453 | err = -ENODATA; | |
454 | goto return_err; | |
455 | } | |
456 | return_ok: | |
457 | mutex_unlock(&pch_phub_mutex); | |
458 | return addr_offset; | |
459 | ||
460 | return_err: | |
461 | mutex_unlock(&pch_phub_mutex); | |
462 | return_err_nomutex: | |
463 | return err; | |
464 | } | |
465 | ||
466 | static ssize_t pch_phub_bin_write(struct file *filp, struct kobject *kobj, | |
467 | struct bin_attribute *attr, | |
468 | char *buf, loff_t off, size_t count) | |
469 | { | |
470 | int err; | |
471 | unsigned int addr_offset; | |
472 | int ret; | |
473 | struct pch_phub_reg *chip = | |
474 | dev_get_drvdata(container_of(kobj, struct device, kobj)); | |
475 | ||
476 | ret = mutex_lock_interruptible(&pch_phub_mutex); | |
477 | if (ret) | |
478 | return -ERESTARTSYS; | |
479 | ||
480 | if (off > PCH_PHUB_OROM_SIZE) { | |
481 | addr_offset = 0; | |
482 | goto return_ok; | |
483 | } | |
484 | if (count > PCH_PHUB_OROM_SIZE) { | |
485 | addr_offset = 0; | |
486 | goto return_ok; | |
487 | } | |
488 | ||
489 | for (addr_offset = 0; addr_offset < count; addr_offset++) { | |
490 | if (PCH_PHUB_OROM_SIZE < off + addr_offset) | |
491 | goto return_ok; | |
492 | ||
493 | ret = pch_phub_write_serial_rom(chip, 0x80 + addr_offset + off, | |
494 | buf[addr_offset]); | |
495 | if (ret) { | |
496 | err = ret; | |
497 | goto return_err; | |
498 | } | |
499 | } | |
500 | ||
501 | return_ok: | |
502 | mutex_unlock(&pch_phub_mutex); | |
503 | return addr_offset; | |
504 | ||
505 | return_err: | |
506 | mutex_unlock(&pch_phub_mutex); | |
507 | return err; | |
508 | } | |
509 | ||
510 | static ssize_t show_pch_mac(struct device *dev, struct device_attribute *attr, | |
511 | char *buf) | |
512 | { | |
513 | u8 mac[8]; | |
514 | struct pch_phub_reg *chip = dev_get_drvdata(dev); | |
515 | ||
516 | pch_phub_read_gbe_mac_addr(chip, mac); | |
517 | ||
518 | return sprintf(buf, "%02x:%02x:%02x:%02x:%02x:%02x\n", | |
519 | mac[0], mac[1], mac[2], mac[3], mac[4], mac[5]); | |
520 | } | |
521 | ||
522 | static ssize_t store_pch_mac(struct device *dev, struct device_attribute *attr, | |
523 | const char *buf, size_t count) | |
524 | { | |
525 | u8 mac[6]; | |
526 | struct pch_phub_reg *chip = dev_get_drvdata(dev); | |
527 | ||
528 | if (count != 18) | |
529 | return -EINVAL; | |
530 | ||
531 | sscanf(buf, "%02x:%02x:%02x:%02x:%02x:%02x", | |
532 | (u32 *)&mac[0], (u32 *)&mac[1], (u32 *)&mac[2], (u32 *)&mac[3], | |
533 | (u32 *)&mac[4], (u32 *)&mac[5]); | |
534 | ||
535 | pch_phub_write_gbe_mac_addr(chip, mac); | |
536 | ||
537 | return count; | |
538 | } | |
539 | ||
540 | static DEVICE_ATTR(pch_mac, S_IRUGO | S_IWUSR, show_pch_mac, store_pch_mac); | |
541 | ||
542 | static struct bin_attribute pch_bin_attr = { | |
543 | .attr = { | |
544 | .name = "pch_firmware", | |
545 | .mode = S_IRUGO | S_IWUSR, | |
546 | }, | |
547 | .size = PCH_PHUB_OROM_SIZE + 1, | |
548 | .read = pch_phub_bin_read, | |
549 | .write = pch_phub_bin_write, | |
550 | }; | |
551 | ||
552 | static int __devinit pch_phub_probe(struct pci_dev *pdev, | |
553 | const struct pci_device_id *id) | |
554 | { | |
555 | int retval; | |
556 | ||
557 | int ret; | |
da0d7f98 | 558 | ssize_t rom_size; |
cf4ece53 MO |
559 | struct pch_phub_reg *chip; |
560 | ||
561 | chip = kzalloc(sizeof(struct pch_phub_reg), GFP_KERNEL); | |
562 | if (chip == NULL) | |
563 | return -ENOMEM; | |
564 | ||
565 | ret = pci_enable_device(pdev); | |
566 | if (ret) { | |
567 | dev_err(&pdev->dev, | |
568 | "%s : pci_enable_device FAILED(ret=%d)", __func__, ret); | |
569 | goto err_pci_enable_dev; | |
570 | } | |
571 | dev_dbg(&pdev->dev, "%s : pci_enable_device returns %d\n", __func__, | |
572 | ret); | |
573 | ||
574 | ret = pci_request_regions(pdev, KBUILD_MODNAME); | |
575 | if (ret) { | |
576 | dev_err(&pdev->dev, | |
577 | "%s : pci_request_regions FAILED(ret=%d)", __func__, ret); | |
578 | goto err_req_regions; | |
579 | } | |
580 | dev_dbg(&pdev->dev, "%s : " | |
581 | "pci_request_regions returns %d\n", __func__, ret); | |
582 | ||
583 | chip->pch_phub_base_address = pci_iomap(pdev, 1, 0); | |
584 | ||
585 | ||
586 | if (chip->pch_phub_base_address == 0) { | |
587 | dev_err(&pdev->dev, "%s : pci_iomap FAILED", __func__); | |
588 | ret = -ENOMEM; | |
589 | goto err_pci_iomap; | |
590 | } | |
591 | dev_dbg(&pdev->dev, "%s : pci_iomap SUCCESS and value " | |
da0d7f98 GKH |
592 | "in pch_phub_base_address variable is %p\n", __func__, |
593 | chip->pch_phub_base_address); | |
cf4ece53 MO |
594 | chip->pch_phub_extrom_base_address = pci_map_rom(pdev, &rom_size); |
595 | ||
596 | if (chip->pch_phub_extrom_base_address == 0) { | |
597 | dev_err(&pdev->dev, "%s : pci_map_rom FAILED", __func__); | |
598 | ret = -ENOMEM; | |
599 | goto err_pci_map; | |
600 | } | |
601 | dev_dbg(&pdev->dev, "%s : " | |
602 | "pci_map_rom SUCCESS and value in " | |
da0d7f98 GKH |
603 | "pch_phub_extrom_base_address variable is %p\n", __func__, |
604 | chip->pch_phub_extrom_base_address); | |
cf4ece53 | 605 | |
1a738dcf TM |
606 | if (id->driver_data == 1) { |
607 | retval = sysfs_create_file(&pdev->dev.kobj, | |
608 | &dev_attr_pch_mac.attr); | |
609 | if (retval) | |
610 | goto err_sysfs_create; | |
cf4ece53 | 611 | |
1a738dcf TM |
612 | retval = sysfs_create_bin_file(&pdev->dev.kobj, &pch_bin_attr); |
613 | if (retval) | |
614 | goto exit_bin_attr; | |
615 | ||
616 | pch_phub_read_modify_write_reg(chip, | |
617 | (unsigned int)CLKCFG_REG_OFFSET, | |
618 | CLKCFG_CAN_50MHZ, | |
619 | CLKCFG_CANCLK_MASK); | |
620 | ||
621 | /* set the prefech value */ | |
622 | iowrite32(0x000affaa, chip->pch_phub_base_address + 0x14); | |
623 | /* set the interrupt delay value */ | |
624 | iowrite32(0x25, chip->pch_phub_base_address + 0x44); | |
625 | } else if (id->driver_data == 2) { | |
626 | retval = sysfs_create_bin_file(&pdev->dev.kobj, &pch_bin_attr); | |
627 | if (retval) | |
628 | goto err_sysfs_create; | |
629 | /* set the prefech value | |
630 | * Device2(USB OHCI #1/ USB EHCI #1/ USB Device):a | |
631 | * Device4(SDIO #0,1,2):f | |
632 | * Device6(SATA 2):f | |
633 | * Device8(USB OHCI #0/ USB EHCI #0):a | |
634 | */ | |
635 | iowrite32(0x000affa0, chip->pch_phub_base_address + 0x14); | |
636 | } | |
637 | pci_set_drvdata(pdev, chip); | |
cf4ece53 MO |
638 | |
639 | return 0; | |
640 | exit_bin_attr: | |
641 | sysfs_remove_file(&pdev->dev.kobj, &dev_attr_pch_mac.attr); | |
642 | ||
643 | err_sysfs_create: | |
644 | pci_unmap_rom(pdev, chip->pch_phub_extrom_base_address); | |
645 | err_pci_map: | |
646 | pci_iounmap(pdev, chip->pch_phub_base_address); | |
647 | err_pci_iomap: | |
648 | pci_release_regions(pdev); | |
649 | err_req_regions: | |
650 | pci_disable_device(pdev); | |
651 | err_pci_enable_dev: | |
652 | kfree(chip); | |
653 | dev_err(&pdev->dev, "%s returns %d\n", __func__, ret); | |
654 | return ret; | |
655 | } | |
656 | ||
657 | static void __devexit pch_phub_remove(struct pci_dev *pdev) | |
658 | { | |
659 | struct pch_phub_reg *chip = pci_get_drvdata(pdev); | |
660 | ||
661 | sysfs_remove_file(&pdev->dev.kobj, &dev_attr_pch_mac.attr); | |
662 | sysfs_remove_bin_file(&pdev->dev.kobj, &pch_bin_attr); | |
663 | pci_unmap_rom(pdev, chip->pch_phub_extrom_base_address); | |
664 | pci_iounmap(pdev, chip->pch_phub_base_address); | |
665 | pci_release_regions(pdev); | |
666 | pci_disable_device(pdev); | |
667 | kfree(chip); | |
668 | } | |
669 | ||
670 | #ifdef CONFIG_PM | |
671 | ||
672 | static int pch_phub_suspend(struct pci_dev *pdev, pm_message_t state) | |
673 | { | |
674 | int ret; | |
675 | ||
676 | pch_phub_save_reg_conf(pdev); | |
677 | ret = pci_save_state(pdev); | |
678 | if (ret) { | |
679 | dev_err(&pdev->dev, | |
680 | " %s -pci_save_state returns %d\n", __func__, ret); | |
681 | return ret; | |
682 | } | |
683 | pci_enable_wake(pdev, PCI_D3hot, 0); | |
684 | pci_disable_device(pdev); | |
685 | pci_set_power_state(pdev, pci_choose_state(pdev, state)); | |
686 | ||
687 | return 0; | |
688 | } | |
689 | ||
690 | static int pch_phub_resume(struct pci_dev *pdev) | |
691 | { | |
692 | int ret; | |
693 | ||
694 | pci_set_power_state(pdev, PCI_D0); | |
695 | pci_restore_state(pdev); | |
696 | ret = pci_enable_device(pdev); | |
697 | if (ret) { | |
698 | dev_err(&pdev->dev, | |
699 | "%s-pci_enable_device failed(ret=%d) ", __func__, ret); | |
700 | return ret; | |
701 | } | |
702 | ||
703 | pci_enable_wake(pdev, PCI_D3hot, 0); | |
704 | pch_phub_restore_reg_conf(pdev); | |
705 | ||
706 | return 0; | |
707 | } | |
708 | #else | |
709 | #define pch_phub_suspend NULL | |
710 | #define pch_phub_resume NULL | |
711 | #endif /* CONFIG_PM */ | |
712 | ||
713 | static struct pci_device_id pch_phub_pcidev_id[] = { | |
1a738dcf TM |
714 | { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_PCH1_PHUB), 1, }, |
715 | { PCI_VDEVICE(ROHM, PCI_DEVICE_ID_ROHM_ML7213_PHUB), 2, }, | |
716 | { } | |
cf4ece53 MO |
717 | }; |
718 | ||
719 | static struct pci_driver pch_phub_driver = { | |
720 | .name = "pch_phub", | |
721 | .id_table = pch_phub_pcidev_id, | |
722 | .probe = pch_phub_probe, | |
723 | .remove = __devexit_p(pch_phub_remove), | |
724 | .suspend = pch_phub_suspend, | |
725 | .resume = pch_phub_resume | |
726 | }; | |
727 | ||
728 | static int __init pch_phub_pci_init(void) | |
729 | { | |
730 | return pci_register_driver(&pch_phub_driver); | |
731 | } | |
732 | ||
733 | static void __exit pch_phub_pci_exit(void) | |
734 | { | |
735 | pci_unregister_driver(&pch_phub_driver); | |
736 | } | |
737 | ||
738 | module_init(pch_phub_pci_init); | |
739 | module_exit(pch_phub_pci_exit); | |
740 | ||
741 | MODULE_DESCRIPTION("PCH Packet Hub PCI Driver"); | |
742 | MODULE_LICENSE("GPL"); |