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7d2be074 HS |
1 | /* |
2 | * Atmel MultiMedia Card Interface driver | |
3 | * | |
4 | * Copyright (C) 2004-2008 Atmel Corporation | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify | |
7 | * it under the terms of the GNU General Public License version 2 as | |
8 | * published by the Free Software Foundation. | |
9 | */ | |
10 | #include <linux/blkdev.h> | |
11 | #include <linux/clk.h> | |
deec9ae3 | 12 | #include <linux/debugfs.h> |
7d2be074 | 13 | #include <linux/device.h> |
65e8b083 HS |
14 | #include <linux/dmaengine.h> |
15 | #include <linux/dma-mapping.h> | |
fbfca4b8 | 16 | #include <linux/err.h> |
3c26e170 | 17 | #include <linux/gpio.h> |
7d2be074 HS |
18 | #include <linux/init.h> |
19 | #include <linux/interrupt.h> | |
20 | #include <linux/ioport.h> | |
21 | #include <linux/module.h> | |
e919fd20 LD |
22 | #include <linux/of.h> |
23 | #include <linux/of_device.h> | |
24 | #include <linux/of_gpio.h> | |
7d2be074 HS |
25 | #include <linux/platform_device.h> |
26 | #include <linux/scatterlist.h> | |
deec9ae3 | 27 | #include <linux/seq_file.h> |
5a0e3ad6 | 28 | #include <linux/slab.h> |
deec9ae3 | 29 | #include <linux/stat.h> |
e2b35f3d | 30 | #include <linux/types.h> |
bcd2360c | 31 | #include <linux/platform_data/atmel.h> |
7d2be074 HS |
32 | |
33 | #include <linux/mmc/host.h> | |
2f1d7918 | 34 | #include <linux/mmc/sdio.h> |
2635d1ba NF |
35 | |
36 | #include <mach/atmel-mci.h> | |
c42aa775 | 37 | #include <linux/atmel-mci.h> |
796211b7 | 38 | #include <linux/atmel_pdc.h> |
7d2be074 | 39 | |
7d2be074 HS |
40 | #include <asm/io.h> |
41 | #include <asm/unaligned.h> | |
42 | ||
7d2be074 HS |
43 | #include "atmel-mci-regs.h" |
44 | ||
2c96a293 | 45 | #define ATMCI_DATA_ERROR_FLAGS (ATMCI_DCRCE | ATMCI_DTOE | ATMCI_OVRE | ATMCI_UNRE) |
65e8b083 | 46 | #define ATMCI_DMA_THRESHOLD 16 |
7d2be074 HS |
47 | |
48 | enum { | |
f5177547 | 49 | EVENT_CMD_RDY = 0, |
7d2be074 | 50 | EVENT_XFER_COMPLETE, |
f5177547 | 51 | EVENT_NOTBUSY, |
c06ad258 HS |
52 | EVENT_DATA_ERROR, |
53 | }; | |
54 | ||
55 | enum atmel_mci_state { | |
965ebf33 HS |
56 | STATE_IDLE = 0, |
57 | STATE_SENDING_CMD, | |
f5177547 LD |
58 | STATE_DATA_XFER, |
59 | STATE_WAITING_NOTBUSY, | |
c06ad258 | 60 | STATE_SENDING_STOP, |
f5177547 | 61 | STATE_END_REQUEST, |
7d2be074 HS |
62 | }; |
63 | ||
796211b7 LD |
64 | enum atmci_xfer_dir { |
65 | XFER_RECEIVE = 0, | |
66 | XFER_TRANSMIT, | |
67 | }; | |
68 | ||
69 | enum atmci_pdc_buf { | |
70 | PDC_FIRST_BUF = 0, | |
71 | PDC_SECOND_BUF, | |
72 | }; | |
73 | ||
74 | struct atmel_mci_caps { | |
ccdfe612 | 75 | bool has_dma_conf_reg; |
796211b7 LD |
76 | bool has_pdc; |
77 | bool has_cfg_reg; | |
78 | bool has_cstor_reg; | |
79 | bool has_highspeed; | |
80 | bool has_rwproof; | |
faf8180b | 81 | bool has_odd_clk_div; |
24011f34 LD |
82 | bool has_bad_data_ordering; |
83 | bool need_reset_after_xfer; | |
84 | bool need_blksz_mul_4; | |
077d4073 | 85 | bool need_notbusy_for_read_ops; |
796211b7 LD |
86 | }; |
87 | ||
65e8b083 | 88 | struct atmel_mci_dma { |
65e8b083 HS |
89 | struct dma_chan *chan; |
90 | struct dma_async_tx_descriptor *data_desc; | |
65e8b083 HS |
91 | }; |
92 | ||
965ebf33 HS |
93 | /** |
94 | * struct atmel_mci - MMC controller state shared between all slots | |
95 | * @lock: Spinlock protecting the queue and associated data. | |
96 | * @regs: Pointer to MMIO registers. | |
796211b7 | 97 | * @sg: Scatterlist entry currently being processed by PIO or PDC code. |
965ebf33 | 98 | * @pio_offset: Offset into the current scatterlist entry. |
7a90dcc2 LD |
99 | * @buffer: Buffer used if we don't have the r/w proof capability. We |
100 | * don't have the time to switch pdc buffers so we have to use only | |
101 | * one buffer for the full transaction. | |
102 | * @buf_size: size of the buffer. | |
103 | * @phys_buf_addr: buffer address needed for pdc. | |
965ebf33 HS |
104 | * @cur_slot: The slot which is currently using the controller. |
105 | * @mrq: The request currently being processed on @cur_slot, | |
106 | * or NULL if the controller is idle. | |
107 | * @cmd: The command currently being sent to the card, or NULL. | |
108 | * @data: The data currently being transferred, or NULL if no data | |
109 | * transfer is in progress. | |
796211b7 | 110 | * @data_size: just data->blocks * data->blksz. |
65e8b083 HS |
111 | * @dma: DMA client state. |
112 | * @data_chan: DMA channel being used for the current data transfer. | |
965ebf33 HS |
113 | * @cmd_status: Snapshot of SR taken upon completion of the current |
114 | * command. Only valid when EVENT_CMD_COMPLETE is pending. | |
115 | * @data_status: Snapshot of SR taken upon completion of the current | |
116 | * data transfer. Only valid when EVENT_DATA_COMPLETE or | |
117 | * EVENT_DATA_ERROR is pending. | |
118 | * @stop_cmdr: Value to be loaded into CMDR when the stop command is | |
119 | * to be sent. | |
120 | * @tasklet: Tasklet running the request state machine. | |
121 | * @pending_events: Bitmask of events flagged by the interrupt handler | |
122 | * to be processed by the tasklet. | |
123 | * @completed_events: Bitmask of events which the state machine has | |
124 | * processed. | |
125 | * @state: Tasklet state. | |
126 | * @queue: List of slots waiting for access to the controller. | |
127 | * @need_clock_update: Update the clock rate before the next request. | |
128 | * @need_reset: Reset controller before next request. | |
24011f34 | 129 | * @timer: Timer to balance the data timeout error flag which cannot rise. |
965ebf33 | 130 | * @mode_reg: Value of the MR register. |
74791a2d | 131 | * @cfg_reg: Value of the CFG register. |
965ebf33 HS |
132 | * @bus_hz: The rate of @mck in Hz. This forms the basis for MMC bus |
133 | * rate and timeout calculations. | |
134 | * @mapbase: Physical address of the MMIO registers. | |
135 | * @mck: The peripheral bus clock hooked up to the MMC controller. | |
136 | * @pdev: Platform device associated with the MMC controller. | |
137 | * @slot: Slots sharing this MMC controller. | |
796211b7 LD |
138 | * @caps: MCI capabilities depending on MCI version. |
139 | * @prepare_data: function to setup MCI before data transfer which | |
140 | * depends on MCI capabilities. | |
141 | * @submit_data: function to start data transfer which depends on MCI | |
142 | * capabilities. | |
143 | * @stop_transfer: function to stop data transfer which depends on MCI | |
144 | * capabilities. | |
965ebf33 HS |
145 | * |
146 | * Locking | |
147 | * ======= | |
148 | * | |
149 | * @lock is a softirq-safe spinlock protecting @queue as well as | |
150 | * @cur_slot, @mrq and @state. These must always be updated | |
151 | * at the same time while holding @lock. | |
152 | * | |
153 | * @lock also protects mode_reg and need_clock_update since these are | |
154 | * used to synchronize mode register updates with the queue | |
155 | * processing. | |
156 | * | |
157 | * The @mrq field of struct atmel_mci_slot is also protected by @lock, | |
158 | * and must always be written at the same time as the slot is added to | |
159 | * @queue. | |
160 | * | |
161 | * @pending_events and @completed_events are accessed using atomic bit | |
162 | * operations, so they don't need any locking. | |
163 | * | |
164 | * None of the fields touched by the interrupt handler need any | |
165 | * locking. However, ordering is important: Before EVENT_DATA_ERROR or | |
166 | * EVENT_DATA_COMPLETE is set in @pending_events, all data-related | |
167 | * interrupts must be disabled and @data_status updated with a | |
168 | * snapshot of SR. Similarly, before EVENT_CMD_COMPLETE is set, the | |
25985edc | 169 | * CMDRDY interrupt must be disabled and @cmd_status updated with a |
965ebf33 HS |
170 | * snapshot of SR, and before EVENT_XFER_COMPLETE can be set, the |
171 | * bytes_xfered field of @data must be written. This is ensured by | |
172 | * using barriers. | |
173 | */ | |
7d2be074 | 174 | struct atmel_mci { |
965ebf33 | 175 | spinlock_t lock; |
7d2be074 HS |
176 | void __iomem *regs; |
177 | ||
178 | struct scatterlist *sg; | |
bdbc5d0c | 179 | unsigned int sg_len; |
7d2be074 | 180 | unsigned int pio_offset; |
7a90dcc2 LD |
181 | unsigned int *buffer; |
182 | unsigned int buf_size; | |
183 | dma_addr_t buf_phys_addr; | |
7d2be074 | 184 | |
965ebf33 | 185 | struct atmel_mci_slot *cur_slot; |
7d2be074 HS |
186 | struct mmc_request *mrq; |
187 | struct mmc_command *cmd; | |
188 | struct mmc_data *data; | |
796211b7 | 189 | unsigned int data_size; |
7d2be074 | 190 | |
65e8b083 HS |
191 | struct atmel_mci_dma dma; |
192 | struct dma_chan *data_chan; | |
e2b35f3d | 193 | struct dma_slave_config dma_conf; |
65e8b083 | 194 | |
7d2be074 HS |
195 | u32 cmd_status; |
196 | u32 data_status; | |
7d2be074 HS |
197 | u32 stop_cmdr; |
198 | ||
7d2be074 HS |
199 | struct tasklet_struct tasklet; |
200 | unsigned long pending_events; | |
201 | unsigned long completed_events; | |
c06ad258 | 202 | enum atmel_mci_state state; |
965ebf33 | 203 | struct list_head queue; |
7d2be074 | 204 | |
965ebf33 HS |
205 | bool need_clock_update; |
206 | bool need_reset; | |
24011f34 | 207 | struct timer_list timer; |
965ebf33 | 208 | u32 mode_reg; |
74791a2d | 209 | u32 cfg_reg; |
7d2be074 HS |
210 | unsigned long bus_hz; |
211 | unsigned long mapbase; | |
212 | struct clk *mck; | |
213 | struct platform_device *pdev; | |
965ebf33 | 214 | |
2c96a293 | 215 | struct atmel_mci_slot *slot[ATMCI_MAX_NR_SLOTS]; |
796211b7 LD |
216 | |
217 | struct atmel_mci_caps caps; | |
218 | ||
219 | u32 (*prepare_data)(struct atmel_mci *host, struct mmc_data *data); | |
220 | void (*submit_data)(struct atmel_mci *host, struct mmc_data *data); | |
221 | void (*stop_transfer)(struct atmel_mci *host); | |
965ebf33 HS |
222 | }; |
223 | ||
224 | /** | |
225 | * struct atmel_mci_slot - MMC slot state | |
226 | * @mmc: The mmc_host representing this slot. | |
227 | * @host: The MMC controller this slot is using. | |
228 | * @sdc_reg: Value of SDCR to be written before using this slot. | |
88ff82ed | 229 | * @sdio_irq: SDIO irq mask for this slot. |
965ebf33 HS |
230 | * @mrq: mmc_request currently being processed or waiting to be |
231 | * processed, or NULL when the slot is idle. | |
232 | * @queue_node: List node for placing this node in the @queue list of | |
233 | * &struct atmel_mci. | |
234 | * @clock: Clock rate configured by set_ios(). Protected by host->lock. | |
235 | * @flags: Random state bits associated with the slot. | |
236 | * @detect_pin: GPIO pin used for card detection, or negative if not | |
237 | * available. | |
238 | * @wp_pin: GPIO pin used for card write protect sending, or negative | |
239 | * if not available. | |
1c1452be | 240 | * @detect_is_active_high: The state of the detect pin when it is active. |
965ebf33 HS |
241 | * @detect_timer: Timer used for debouncing @detect_pin interrupts. |
242 | */ | |
243 | struct atmel_mci_slot { | |
244 | struct mmc_host *mmc; | |
245 | struct atmel_mci *host; | |
246 | ||
247 | u32 sdc_reg; | |
88ff82ed | 248 | u32 sdio_irq; |
965ebf33 HS |
249 | |
250 | struct mmc_request *mrq; | |
251 | struct list_head queue_node; | |
252 | ||
253 | unsigned int clock; | |
254 | unsigned long flags; | |
255 | #define ATMCI_CARD_PRESENT 0 | |
256 | #define ATMCI_CARD_NEED_INIT 1 | |
257 | #define ATMCI_SHUTDOWN 2 | |
5c2f2b9b | 258 | #define ATMCI_SUSPENDED 3 |
965ebf33 HS |
259 | |
260 | int detect_pin; | |
261 | int wp_pin; | |
1c1452be | 262 | bool detect_is_active_high; |
965ebf33 HS |
263 | |
264 | struct timer_list detect_timer; | |
7d2be074 HS |
265 | }; |
266 | ||
7d2be074 HS |
267 | #define atmci_test_and_clear_pending(host, event) \ |
268 | test_and_clear_bit(event, &host->pending_events) | |
7d2be074 HS |
269 | #define atmci_set_completed(host, event) \ |
270 | set_bit(event, &host->completed_events) | |
271 | #define atmci_set_pending(host, event) \ | |
272 | set_bit(event, &host->pending_events) | |
7d2be074 | 273 | |
deec9ae3 HS |
274 | /* |
275 | * The debugfs stuff below is mostly optimized away when | |
276 | * CONFIG_DEBUG_FS is not set. | |
277 | */ | |
278 | static int atmci_req_show(struct seq_file *s, void *v) | |
279 | { | |
965ebf33 HS |
280 | struct atmel_mci_slot *slot = s->private; |
281 | struct mmc_request *mrq; | |
deec9ae3 HS |
282 | struct mmc_command *cmd; |
283 | struct mmc_command *stop; | |
284 | struct mmc_data *data; | |
285 | ||
286 | /* Make sure we get a consistent snapshot */ | |
965ebf33 HS |
287 | spin_lock_bh(&slot->host->lock); |
288 | mrq = slot->mrq; | |
deec9ae3 HS |
289 | |
290 | if (mrq) { | |
291 | cmd = mrq->cmd; | |
292 | data = mrq->data; | |
293 | stop = mrq->stop; | |
294 | ||
295 | if (cmd) | |
296 | seq_printf(s, | |
297 | "CMD%u(0x%x) flg %x rsp %x %x %x %x err %d\n", | |
298 | cmd->opcode, cmd->arg, cmd->flags, | |
299 | cmd->resp[0], cmd->resp[1], cmd->resp[2], | |
d586ebbb | 300 | cmd->resp[3], cmd->error); |
deec9ae3 HS |
301 | if (data) |
302 | seq_printf(s, "DATA %u / %u * %u flg %x err %d\n", | |
303 | data->bytes_xfered, data->blocks, | |
304 | data->blksz, data->flags, data->error); | |
305 | if (stop) | |
306 | seq_printf(s, | |
307 | "CMD%u(0x%x) flg %x rsp %x %x %x %x err %d\n", | |
308 | stop->opcode, stop->arg, stop->flags, | |
309 | stop->resp[0], stop->resp[1], stop->resp[2], | |
d586ebbb | 310 | stop->resp[3], stop->error); |
deec9ae3 HS |
311 | } |
312 | ||
965ebf33 | 313 | spin_unlock_bh(&slot->host->lock); |
deec9ae3 HS |
314 | |
315 | return 0; | |
316 | } | |
317 | ||
318 | static int atmci_req_open(struct inode *inode, struct file *file) | |
319 | { | |
320 | return single_open(file, atmci_req_show, inode->i_private); | |
321 | } | |
322 | ||
323 | static const struct file_operations atmci_req_fops = { | |
324 | .owner = THIS_MODULE, | |
325 | .open = atmci_req_open, | |
326 | .read = seq_read, | |
327 | .llseek = seq_lseek, | |
328 | .release = single_release, | |
329 | }; | |
330 | ||
331 | static void atmci_show_status_reg(struct seq_file *s, | |
332 | const char *regname, u32 value) | |
333 | { | |
334 | static const char *sr_bit[] = { | |
335 | [0] = "CMDRDY", | |
336 | [1] = "RXRDY", | |
337 | [2] = "TXRDY", | |
338 | [3] = "BLKE", | |
339 | [4] = "DTIP", | |
340 | [5] = "NOTBUSY", | |
04d699c3 RE |
341 | [6] = "ENDRX", |
342 | [7] = "ENDTX", | |
deec9ae3 HS |
343 | [8] = "SDIOIRQA", |
344 | [9] = "SDIOIRQB", | |
04d699c3 RE |
345 | [12] = "SDIOWAIT", |
346 | [14] = "RXBUFF", | |
347 | [15] = "TXBUFE", | |
deec9ae3 HS |
348 | [16] = "RINDE", |
349 | [17] = "RDIRE", | |
350 | [18] = "RCRCE", | |
351 | [19] = "RENDE", | |
352 | [20] = "RTOE", | |
353 | [21] = "DCRCE", | |
354 | [22] = "DTOE", | |
04d699c3 RE |
355 | [23] = "CSTOE", |
356 | [24] = "BLKOVRE", | |
357 | [25] = "DMADONE", | |
358 | [26] = "FIFOEMPTY", | |
359 | [27] = "XFRDONE", | |
deec9ae3 HS |
360 | [30] = "OVRE", |
361 | [31] = "UNRE", | |
362 | }; | |
363 | unsigned int i; | |
364 | ||
365 | seq_printf(s, "%s:\t0x%08x", regname, value); | |
366 | for (i = 0; i < ARRAY_SIZE(sr_bit); i++) { | |
367 | if (value & (1 << i)) { | |
368 | if (sr_bit[i]) | |
369 | seq_printf(s, " %s", sr_bit[i]); | |
370 | else | |
371 | seq_puts(s, " UNKNOWN"); | |
372 | } | |
373 | } | |
374 | seq_putc(s, '\n'); | |
375 | } | |
376 | ||
377 | static int atmci_regs_show(struct seq_file *s, void *v) | |
378 | { | |
379 | struct atmel_mci *host = s->private; | |
380 | u32 *buf; | |
b3894f26 BB |
381 | int ret = 0; |
382 | ||
deec9ae3 | 383 | |
2c96a293 | 384 | buf = kmalloc(ATMCI_REGS_SIZE, GFP_KERNEL); |
deec9ae3 HS |
385 | if (!buf) |
386 | return -ENOMEM; | |
387 | ||
965ebf33 HS |
388 | /* |
389 | * Grab a more or less consistent snapshot. Note that we're | |
390 | * not disabling interrupts, so IMR and SR may not be | |
391 | * consistent. | |
392 | */ | |
b3894f26 BB |
393 | ret = clk_prepare_enable(host->mck); |
394 | if (ret) | |
395 | goto out; | |
396 | ||
965ebf33 | 397 | spin_lock_bh(&host->lock); |
2c96a293 | 398 | memcpy_fromio(buf, host->regs, ATMCI_REGS_SIZE); |
965ebf33 | 399 | spin_unlock_bh(&host->lock); |
deec9ae3 | 400 | |
b3894f26 BB |
401 | clk_disable_unprepare(host->mck); |
402 | ||
8a4de07e | 403 | seq_printf(s, "MR:\t0x%08x%s%s ", |
2c96a293 LD |
404 | buf[ATMCI_MR / 4], |
405 | buf[ATMCI_MR / 4] & ATMCI_MR_RDPROOF ? " RDPROOF" : "", | |
8a4de07e NF |
406 | buf[ATMCI_MR / 4] & ATMCI_MR_WRPROOF ? " WRPROOF" : ""); |
407 | if (host->caps.has_odd_clk_div) | |
408 | seq_printf(s, "{CLKDIV,CLKODD}=%u\n", | |
409 | ((buf[ATMCI_MR / 4] & 0xff) << 1) | |
410 | | ((buf[ATMCI_MR / 4] >> 16) & 1)); | |
411 | else | |
412 | seq_printf(s, "CLKDIV=%u\n", | |
413 | (buf[ATMCI_MR / 4] & 0xff)); | |
2c96a293 LD |
414 | seq_printf(s, "DTOR:\t0x%08x\n", buf[ATMCI_DTOR / 4]); |
415 | seq_printf(s, "SDCR:\t0x%08x\n", buf[ATMCI_SDCR / 4]); | |
416 | seq_printf(s, "ARGR:\t0x%08x\n", buf[ATMCI_ARGR / 4]); | |
deec9ae3 | 417 | seq_printf(s, "BLKR:\t0x%08x BCNT=%u BLKLEN=%u\n", |
2c96a293 LD |
418 | buf[ATMCI_BLKR / 4], |
419 | buf[ATMCI_BLKR / 4] & 0xffff, | |
420 | (buf[ATMCI_BLKR / 4] >> 16) & 0xffff); | |
796211b7 | 421 | if (host->caps.has_cstor_reg) |
2c96a293 | 422 | seq_printf(s, "CSTOR:\t0x%08x\n", buf[ATMCI_CSTOR / 4]); |
deec9ae3 HS |
423 | |
424 | /* Don't read RSPR and RDR; it will consume the data there */ | |
425 | ||
2c96a293 LD |
426 | atmci_show_status_reg(s, "SR", buf[ATMCI_SR / 4]); |
427 | atmci_show_status_reg(s, "IMR", buf[ATMCI_IMR / 4]); | |
deec9ae3 | 428 | |
ccdfe612 | 429 | if (host->caps.has_dma_conf_reg) { |
74791a2d NF |
430 | u32 val; |
431 | ||
2c96a293 | 432 | val = buf[ATMCI_DMA / 4]; |
74791a2d NF |
433 | seq_printf(s, "DMA:\t0x%08x OFFSET=%u CHKSIZE=%u%s\n", |
434 | val, val & 3, | |
435 | ((val >> 4) & 3) ? | |
436 | 1 << (((val >> 4) & 3) + 1) : 1, | |
2c96a293 | 437 | val & ATMCI_DMAEN ? " DMAEN" : ""); |
796211b7 LD |
438 | } |
439 | if (host->caps.has_cfg_reg) { | |
440 | u32 val; | |
74791a2d | 441 | |
2c96a293 | 442 | val = buf[ATMCI_CFG / 4]; |
74791a2d NF |
443 | seq_printf(s, "CFG:\t0x%08x%s%s%s%s\n", |
444 | val, | |
2c96a293 LD |
445 | val & ATMCI_CFG_FIFOMODE_1DATA ? " FIFOMODE_ONE_DATA" : "", |
446 | val & ATMCI_CFG_FERRCTRL_COR ? " FERRCTRL_CLEAR_ON_READ" : "", | |
447 | val & ATMCI_CFG_HSMODE ? " HSMODE" : "", | |
448 | val & ATMCI_CFG_LSYNC ? " LSYNC" : ""); | |
74791a2d NF |
449 | } |
450 | ||
b3894f26 | 451 | out: |
b17339a1 HS |
452 | kfree(buf); |
453 | ||
b3894f26 | 454 | return ret; |
deec9ae3 HS |
455 | } |
456 | ||
457 | static int atmci_regs_open(struct inode *inode, struct file *file) | |
458 | { | |
459 | return single_open(file, atmci_regs_show, inode->i_private); | |
460 | } | |
461 | ||
462 | static const struct file_operations atmci_regs_fops = { | |
463 | .owner = THIS_MODULE, | |
464 | .open = atmci_regs_open, | |
465 | .read = seq_read, | |
466 | .llseek = seq_lseek, | |
467 | .release = single_release, | |
468 | }; | |
469 | ||
965ebf33 | 470 | static void atmci_init_debugfs(struct atmel_mci_slot *slot) |
deec9ae3 | 471 | { |
965ebf33 HS |
472 | struct mmc_host *mmc = slot->mmc; |
473 | struct atmel_mci *host = slot->host; | |
474 | struct dentry *root; | |
475 | struct dentry *node; | |
deec9ae3 | 476 | |
deec9ae3 HS |
477 | root = mmc->debugfs_root; |
478 | if (!root) | |
479 | return; | |
480 | ||
481 | node = debugfs_create_file("regs", S_IRUSR, root, host, | |
482 | &atmci_regs_fops); | |
483 | if (IS_ERR(node)) | |
484 | return; | |
485 | if (!node) | |
486 | goto err; | |
487 | ||
965ebf33 | 488 | node = debugfs_create_file("req", S_IRUSR, root, slot, &atmci_req_fops); |
deec9ae3 HS |
489 | if (!node) |
490 | goto err; | |
491 | ||
c06ad258 HS |
492 | node = debugfs_create_u32("state", S_IRUSR, root, (u32 *)&host->state); |
493 | if (!node) | |
494 | goto err; | |
495 | ||
deec9ae3 HS |
496 | node = debugfs_create_x32("pending_events", S_IRUSR, root, |
497 | (u32 *)&host->pending_events); | |
498 | if (!node) | |
499 | goto err; | |
500 | ||
501 | node = debugfs_create_x32("completed_events", S_IRUSR, root, | |
502 | (u32 *)&host->completed_events); | |
503 | if (!node) | |
504 | goto err; | |
505 | ||
506 | return; | |
507 | ||
508 | err: | |
965ebf33 | 509 | dev_err(&mmc->class_dev, "failed to initialize debugfs for slot\n"); |
deec9ae3 | 510 | } |
7d2be074 | 511 | |
e919fd20 LD |
512 | #if defined(CONFIG_OF) |
513 | static const struct of_device_id atmci_dt_ids[] = { | |
514 | { .compatible = "atmel,hsmci" }, | |
515 | { /* sentinel */ } | |
516 | }; | |
517 | ||
518 | MODULE_DEVICE_TABLE(of, atmci_dt_ids); | |
519 | ||
c3be1efd | 520 | static struct mci_platform_data* |
e919fd20 LD |
521 | atmci_of_init(struct platform_device *pdev) |
522 | { | |
523 | struct device_node *np = pdev->dev.of_node; | |
524 | struct device_node *cnp; | |
525 | struct mci_platform_data *pdata; | |
526 | u32 slot_id; | |
527 | ||
528 | if (!np) { | |
529 | dev_err(&pdev->dev, "device node not found\n"); | |
530 | return ERR_PTR(-EINVAL); | |
531 | } | |
532 | ||
533 | pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL); | |
534 | if (!pdata) { | |
535 | dev_err(&pdev->dev, "could not allocate memory for pdata\n"); | |
536 | return ERR_PTR(-ENOMEM); | |
537 | } | |
538 | ||
539 | for_each_child_of_node(np, cnp) { | |
540 | if (of_property_read_u32(cnp, "reg", &slot_id)) { | |
541 | dev_warn(&pdev->dev, "reg property is missing for %s\n", | |
542 | cnp->full_name); | |
543 | continue; | |
544 | } | |
545 | ||
546 | if (slot_id >= ATMCI_MAX_NR_SLOTS) { | |
547 | dev_warn(&pdev->dev, "can't have more than %d slots\n", | |
548 | ATMCI_MAX_NR_SLOTS); | |
549 | break; | |
550 | } | |
551 | ||
552 | if (of_property_read_u32(cnp, "bus-width", | |
553 | &pdata->slot[slot_id].bus_width)) | |
554 | pdata->slot[slot_id].bus_width = 1; | |
555 | ||
556 | pdata->slot[slot_id].detect_pin = | |
557 | of_get_named_gpio(cnp, "cd-gpios", 0); | |
558 | ||
559 | pdata->slot[slot_id].detect_is_active_high = | |
560 | of_property_read_bool(cnp, "cd-inverted"); | |
561 | ||
562 | pdata->slot[slot_id].wp_pin = | |
563 | of_get_named_gpio(cnp, "wp-gpios", 0); | |
564 | } | |
565 | ||
566 | return pdata; | |
567 | } | |
568 | #else /* CONFIG_OF */ | |
569 | static inline struct mci_platform_data* | |
570 | atmci_of_init(struct platform_device *dev) | |
571 | { | |
572 | return ERR_PTR(-EINVAL); | |
573 | } | |
574 | #endif | |
575 | ||
7a90dcc2 LD |
576 | static inline unsigned int atmci_get_version(struct atmel_mci *host) |
577 | { | |
578 | return atmci_readl(host, ATMCI_VERSION) & 0x00000fff; | |
579 | } | |
580 | ||
24011f34 LD |
581 | static void atmci_timeout_timer(unsigned long data) |
582 | { | |
583 | struct atmel_mci *host; | |
584 | ||
585 | host = (struct atmel_mci *)data; | |
586 | ||
587 | dev_dbg(&host->pdev->dev, "software timeout\n"); | |
588 | ||
589 | if (host->mrq->cmd->data) { | |
590 | host->mrq->cmd->data->error = -ETIMEDOUT; | |
591 | host->data = NULL; | |
592 | } else { | |
593 | host->mrq->cmd->error = -ETIMEDOUT; | |
594 | host->cmd = NULL; | |
595 | } | |
596 | host->need_reset = 1; | |
597 | host->state = STATE_END_REQUEST; | |
598 | smp_wmb(); | |
599 | tasklet_schedule(&host->tasklet); | |
600 | } | |
601 | ||
2c96a293 | 602 | static inline unsigned int atmci_ns_to_clocks(struct atmel_mci *host, |
7d2be074 HS |
603 | unsigned int ns) |
604 | { | |
66292ad9 LD |
605 | /* |
606 | * It is easier here to use us instead of ns for the timeout, | |
607 | * it prevents from overflows during calculation. | |
608 | */ | |
609 | unsigned int us = DIV_ROUND_UP(ns, 1000); | |
610 | ||
611 | /* Maximum clock frequency is host->bus_hz/2 */ | |
612 | return us * (DIV_ROUND_UP(host->bus_hz, 2000000)); | |
7d2be074 HS |
613 | } |
614 | ||
615 | static void atmci_set_timeout(struct atmel_mci *host, | |
965ebf33 | 616 | struct atmel_mci_slot *slot, struct mmc_data *data) |
7d2be074 HS |
617 | { |
618 | static unsigned dtomul_to_shift[] = { | |
619 | 0, 4, 7, 8, 10, 12, 16, 20 | |
620 | }; | |
621 | unsigned timeout; | |
622 | unsigned dtocyc; | |
623 | unsigned dtomul; | |
624 | ||
2c96a293 LD |
625 | timeout = atmci_ns_to_clocks(host, data->timeout_ns) |
626 | + data->timeout_clks; | |
7d2be074 HS |
627 | |
628 | for (dtomul = 0; dtomul < 8; dtomul++) { | |
629 | unsigned shift = dtomul_to_shift[dtomul]; | |
630 | dtocyc = (timeout + (1 << shift) - 1) >> shift; | |
631 | if (dtocyc < 15) | |
632 | break; | |
633 | } | |
634 | ||
635 | if (dtomul >= 8) { | |
636 | dtomul = 7; | |
637 | dtocyc = 15; | |
638 | } | |
639 | ||
965ebf33 | 640 | dev_vdbg(&slot->mmc->class_dev, "setting timeout to %u cycles\n", |
7d2be074 | 641 | dtocyc << dtomul_to_shift[dtomul]); |
03fc9a7f | 642 | atmci_writel(host, ATMCI_DTOR, (ATMCI_DTOMUL(dtomul) | ATMCI_DTOCYC(dtocyc))); |
7d2be074 HS |
643 | } |
644 | ||
645 | /* | |
646 | * Return mask with command flags to be enabled for this command. | |
647 | */ | |
648 | static u32 atmci_prepare_command(struct mmc_host *mmc, | |
649 | struct mmc_command *cmd) | |
650 | { | |
651 | struct mmc_data *data; | |
652 | u32 cmdr; | |
653 | ||
654 | cmd->error = -EINPROGRESS; | |
655 | ||
2c96a293 | 656 | cmdr = ATMCI_CMDR_CMDNB(cmd->opcode); |
7d2be074 HS |
657 | |
658 | if (cmd->flags & MMC_RSP_PRESENT) { | |
659 | if (cmd->flags & MMC_RSP_136) | |
2c96a293 | 660 | cmdr |= ATMCI_CMDR_RSPTYP_136BIT; |
7d2be074 | 661 | else |
2c96a293 | 662 | cmdr |= ATMCI_CMDR_RSPTYP_48BIT; |
7d2be074 HS |
663 | } |
664 | ||
665 | /* | |
666 | * This should really be MAXLAT_5 for CMD2 and ACMD41, but | |
667 | * it's too difficult to determine whether this is an ACMD or | |
668 | * not. Better make it 64. | |
669 | */ | |
2c96a293 | 670 | cmdr |= ATMCI_CMDR_MAXLAT_64CYC; |
7d2be074 HS |
671 | |
672 | if (mmc->ios.bus_mode == MMC_BUSMODE_OPENDRAIN) | |
2c96a293 | 673 | cmdr |= ATMCI_CMDR_OPDCMD; |
7d2be074 HS |
674 | |
675 | data = cmd->data; | |
676 | if (data) { | |
2c96a293 | 677 | cmdr |= ATMCI_CMDR_START_XFER; |
2f1d7918 NF |
678 | |
679 | if (cmd->opcode == SD_IO_RW_EXTENDED) { | |
2c96a293 | 680 | cmdr |= ATMCI_CMDR_SDIO_BLOCK; |
2f1d7918 NF |
681 | } else { |
682 | if (data->flags & MMC_DATA_STREAM) | |
2c96a293 | 683 | cmdr |= ATMCI_CMDR_STREAM; |
2f1d7918 | 684 | else if (data->blocks > 1) |
2c96a293 | 685 | cmdr |= ATMCI_CMDR_MULTI_BLOCK; |
2f1d7918 | 686 | else |
2c96a293 | 687 | cmdr |= ATMCI_CMDR_BLOCK; |
2f1d7918 | 688 | } |
7d2be074 HS |
689 | |
690 | if (data->flags & MMC_DATA_READ) | |
2c96a293 | 691 | cmdr |= ATMCI_CMDR_TRDIR_READ; |
7d2be074 HS |
692 | } |
693 | ||
694 | return cmdr; | |
695 | } | |
696 | ||
11d1488b | 697 | static void atmci_send_command(struct atmel_mci *host, |
965ebf33 | 698 | struct mmc_command *cmd, u32 cmd_flags) |
7d2be074 | 699 | { |
7d2be074 HS |
700 | WARN_ON(host->cmd); |
701 | host->cmd = cmd; | |
702 | ||
965ebf33 | 703 | dev_vdbg(&host->pdev->dev, |
7d2be074 HS |
704 | "start command: ARGR=0x%08x CMDR=0x%08x\n", |
705 | cmd->arg, cmd_flags); | |
706 | ||
03fc9a7f LD |
707 | atmci_writel(host, ATMCI_ARGR, cmd->arg); |
708 | atmci_writel(host, ATMCI_CMDR, cmd_flags); | |
7d2be074 HS |
709 | } |
710 | ||
2c96a293 | 711 | static void atmci_send_stop_cmd(struct atmel_mci *host, struct mmc_data *data) |
7d2be074 | 712 | { |
6801c41a | 713 | dev_dbg(&host->pdev->dev, "send stop command\n"); |
11d1488b | 714 | atmci_send_command(host, data->stop, host->stop_cmdr); |
03fc9a7f | 715 | atmci_writel(host, ATMCI_IER, ATMCI_CMDRDY); |
7d2be074 HS |
716 | } |
717 | ||
796211b7 LD |
718 | /* |
719 | * Configure given PDC buffer taking care of alignement issues. | |
720 | * Update host->data_size and host->sg. | |
721 | */ | |
722 | static void atmci_pdc_set_single_buf(struct atmel_mci *host, | |
723 | enum atmci_xfer_dir dir, enum atmci_pdc_buf buf_nb) | |
724 | { | |
725 | u32 pointer_reg, counter_reg; | |
7a90dcc2 | 726 | unsigned int buf_size; |
796211b7 LD |
727 | |
728 | if (dir == XFER_RECEIVE) { | |
729 | pointer_reg = ATMEL_PDC_RPR; | |
730 | counter_reg = ATMEL_PDC_RCR; | |
731 | } else { | |
732 | pointer_reg = ATMEL_PDC_TPR; | |
733 | counter_reg = ATMEL_PDC_TCR; | |
734 | } | |
735 | ||
736 | if (buf_nb == PDC_SECOND_BUF) { | |
1ebbe3d3 LD |
737 | pointer_reg += ATMEL_PDC_SCND_BUF_OFF; |
738 | counter_reg += ATMEL_PDC_SCND_BUF_OFF; | |
796211b7 LD |
739 | } |
740 | ||
7a90dcc2 LD |
741 | if (!host->caps.has_rwproof) { |
742 | buf_size = host->buf_size; | |
743 | atmci_writel(host, pointer_reg, host->buf_phys_addr); | |
744 | } else { | |
745 | buf_size = sg_dma_len(host->sg); | |
746 | atmci_writel(host, pointer_reg, sg_dma_address(host->sg)); | |
747 | } | |
748 | ||
749 | if (host->data_size <= buf_size) { | |
796211b7 LD |
750 | if (host->data_size & 0x3) { |
751 | /* If size is different from modulo 4, transfer bytes */ | |
752 | atmci_writel(host, counter_reg, host->data_size); | |
753 | atmci_writel(host, ATMCI_MR, host->mode_reg | ATMCI_MR_PDCFBYTE); | |
754 | } else { | |
755 | /* Else transfer 32-bits words */ | |
756 | atmci_writel(host, counter_reg, host->data_size / 4); | |
757 | } | |
758 | host->data_size = 0; | |
759 | } else { | |
760 | /* We assume the size of a page is 32-bits aligned */ | |
341fa4c3 LD |
761 | atmci_writel(host, counter_reg, sg_dma_len(host->sg) / 4); |
762 | host->data_size -= sg_dma_len(host->sg); | |
796211b7 LD |
763 | if (host->data_size) |
764 | host->sg = sg_next(host->sg); | |
765 | } | |
766 | } | |
767 | ||
768 | /* | |
769 | * Configure PDC buffer according to the data size ie configuring one or two | |
770 | * buffers. Don't use this function if you want to configure only the second | |
771 | * buffer. In this case, use atmci_pdc_set_single_buf. | |
772 | */ | |
773 | static void atmci_pdc_set_both_buf(struct atmel_mci *host, int dir) | |
65e8b083 | 774 | { |
796211b7 LD |
775 | atmci_pdc_set_single_buf(host, dir, PDC_FIRST_BUF); |
776 | if (host->data_size) | |
777 | atmci_pdc_set_single_buf(host, dir, PDC_SECOND_BUF); | |
778 | } | |
779 | ||
780 | /* | |
781 | * Unmap sg lists, called when transfer is finished. | |
782 | */ | |
783 | static void atmci_pdc_cleanup(struct atmel_mci *host) | |
784 | { | |
785 | struct mmc_data *data = host->data; | |
65e8b083 | 786 | |
009a891b | 787 | if (data) |
796211b7 LD |
788 | dma_unmap_sg(&host->pdev->dev, |
789 | data->sg, data->sg_len, | |
790 | ((data->flags & MMC_DATA_WRITE) | |
791 | ? DMA_TO_DEVICE : DMA_FROM_DEVICE)); | |
65e8b083 HS |
792 | } |
793 | ||
796211b7 LD |
794 | /* |
795 | * Disable PDC transfers. Update pending flags to EVENT_XFER_COMPLETE after | |
796 | * having received ATMCI_TXBUFE or ATMCI_RXBUFF interrupt. Enable ATMCI_NOTBUSY | |
797 | * interrupt needed for both transfer directions. | |
798 | */ | |
799 | static void atmci_pdc_complete(struct atmel_mci *host) | |
65e8b083 | 800 | { |
7a90dcc2 | 801 | int transfer_size = host->data->blocks * host->data->blksz; |
24011f34 | 802 | int i; |
7a90dcc2 | 803 | |
796211b7 | 804 | atmci_writel(host, ATMEL_PDC_PTCR, ATMEL_PDC_RXTDIS | ATMEL_PDC_TXTDIS); |
7a90dcc2 LD |
805 | |
806 | if ((!host->caps.has_rwproof) | |
24011f34 LD |
807 | && (host->data->flags & MMC_DATA_READ)) { |
808 | if (host->caps.has_bad_data_ordering) | |
809 | for (i = 0; i < transfer_size; i++) | |
810 | host->buffer[i] = swab32(host->buffer[i]); | |
7a90dcc2 LD |
811 | sg_copy_from_buffer(host->data->sg, host->data->sg_len, |
812 | host->buffer, transfer_size); | |
24011f34 | 813 | } |
7a90dcc2 | 814 | |
796211b7 | 815 | atmci_pdc_cleanup(host); |
65e8b083 | 816 | |
796211b7 LD |
817 | /* |
818 | * If the card was removed, data will be NULL. No point trying | |
819 | * to send the stop command or waiting for NBUSY in this case. | |
820 | */ | |
821 | if (host->data) { | |
6801c41a LD |
822 | dev_dbg(&host->pdev->dev, |
823 | "(%s) set pending xfer complete\n", __func__); | |
65e8b083 | 824 | atmci_set_pending(host, EVENT_XFER_COMPLETE); |
796211b7 | 825 | tasklet_schedule(&host->tasklet); |
65e8b083 HS |
826 | } |
827 | } | |
828 | ||
796211b7 LD |
829 | static void atmci_dma_cleanup(struct atmel_mci *host) |
830 | { | |
831 | struct mmc_data *data = host->data; | |
832 | ||
833 | if (data) | |
834 | dma_unmap_sg(host->dma.chan->device->dev, | |
835 | data->sg, data->sg_len, | |
836 | ((data->flags & MMC_DATA_WRITE) | |
837 | ? DMA_TO_DEVICE : DMA_FROM_DEVICE)); | |
838 | } | |
839 | ||
840 | /* | |
841 | * This function is called by the DMA driver from tasklet context. | |
842 | */ | |
65e8b083 HS |
843 | static void atmci_dma_complete(void *arg) |
844 | { | |
845 | struct atmel_mci *host = arg; | |
846 | struct mmc_data *data = host->data; | |
847 | ||
848 | dev_vdbg(&host->pdev->dev, "DMA complete\n"); | |
849 | ||
ccdfe612 | 850 | if (host->caps.has_dma_conf_reg) |
74791a2d | 851 | /* Disable DMA hardware handshaking on MCI */ |
03fc9a7f | 852 | atmci_writel(host, ATMCI_DMA, atmci_readl(host, ATMCI_DMA) & ~ATMCI_DMAEN); |
74791a2d | 853 | |
65e8b083 HS |
854 | atmci_dma_cleanup(host); |
855 | ||
856 | /* | |
857 | * If the card was removed, data will be NULL. No point trying | |
858 | * to send the stop command or waiting for NBUSY in this case. | |
859 | */ | |
860 | if (data) { | |
6801c41a LD |
861 | dev_dbg(&host->pdev->dev, |
862 | "(%s) set pending xfer complete\n", __func__); | |
65e8b083 HS |
863 | atmci_set_pending(host, EVENT_XFER_COMPLETE); |
864 | tasklet_schedule(&host->tasklet); | |
865 | ||
866 | /* | |
867 | * Regardless of what the documentation says, we have | |
868 | * to wait for NOTBUSY even after block read | |
869 | * operations. | |
870 | * | |
871 | * When the DMA transfer is complete, the controller | |
872 | * may still be reading the CRC from the card, i.e. | |
873 | * the data transfer is still in progress and we | |
874 | * haven't seen all the potential error bits yet. | |
875 | * | |
876 | * The interrupt handler will schedule a different | |
877 | * tasklet to finish things up when the data transfer | |
878 | * is completely done. | |
879 | * | |
880 | * We may not complete the mmc request here anyway | |
881 | * because the mmc layer may call back and cause us to | |
882 | * violate the "don't submit new operations from the | |
883 | * completion callback" rule of the dma engine | |
884 | * framework. | |
885 | */ | |
03fc9a7f | 886 | atmci_writel(host, ATMCI_IER, ATMCI_NOTBUSY); |
65e8b083 HS |
887 | } |
888 | } | |
889 | ||
796211b7 LD |
890 | /* |
891 | * Returns a mask of interrupt flags to be enabled after the whole | |
892 | * request has been prepared. | |
893 | */ | |
894 | static u32 atmci_prepare_data(struct atmel_mci *host, struct mmc_data *data) | |
895 | { | |
896 | u32 iflags; | |
897 | ||
898 | data->error = -EINPROGRESS; | |
899 | ||
900 | host->sg = data->sg; | |
bdbc5d0c | 901 | host->sg_len = data->sg_len; |
796211b7 LD |
902 | host->data = data; |
903 | host->data_chan = NULL; | |
904 | ||
905 | iflags = ATMCI_DATA_ERROR_FLAGS; | |
906 | ||
907 | /* | |
908 | * Errata: MMC data write operation with less than 12 | |
909 | * bytes is impossible. | |
910 | * | |
911 | * Errata: MCI Transmit Data Register (TDR) FIFO | |
912 | * corruption when length is not multiple of 4. | |
913 | */ | |
914 | if (data->blocks * data->blksz < 12 | |
915 | || (data->blocks * data->blksz) & 3) | |
916 | host->need_reset = true; | |
917 | ||
918 | host->pio_offset = 0; | |
919 | if (data->flags & MMC_DATA_READ) | |
920 | iflags |= ATMCI_RXRDY; | |
921 | else | |
922 | iflags |= ATMCI_TXRDY; | |
923 | ||
924 | return iflags; | |
925 | } | |
926 | ||
927 | /* | |
928 | * Set interrupt flags and set block length into the MCI mode register even | |
929 | * if this value is also accessible in the MCI block register. It seems to be | |
930 | * necessary before the High Speed MCI version. It also map sg and configure | |
931 | * PDC registers. | |
932 | */ | |
933 | static u32 | |
934 | atmci_prepare_data_pdc(struct atmel_mci *host, struct mmc_data *data) | |
935 | { | |
936 | u32 iflags, tmp; | |
937 | unsigned int sg_len; | |
938 | enum dma_data_direction dir; | |
24011f34 | 939 | int i; |
796211b7 LD |
940 | |
941 | data->error = -EINPROGRESS; | |
942 | ||
943 | host->data = data; | |
944 | host->sg = data->sg; | |
945 | iflags = ATMCI_DATA_ERROR_FLAGS; | |
946 | ||
947 | /* Enable pdc mode */ | |
948 | atmci_writel(host, ATMCI_MR, host->mode_reg | ATMCI_MR_PDCMODE); | |
949 | ||
950 | if (data->flags & MMC_DATA_READ) { | |
951 | dir = DMA_FROM_DEVICE; | |
952 | iflags |= ATMCI_ENDRX | ATMCI_RXBUFF; | |
953 | } else { | |
954 | dir = DMA_TO_DEVICE; | |
f5177547 | 955 | iflags |= ATMCI_ENDTX | ATMCI_TXBUFE | ATMCI_BLKE; |
796211b7 LD |
956 | } |
957 | ||
958 | /* Set BLKLEN */ | |
959 | tmp = atmci_readl(host, ATMCI_MR); | |
960 | tmp &= 0x0000ffff; | |
961 | tmp |= ATMCI_BLKLEN(data->blksz); | |
962 | atmci_writel(host, ATMCI_MR, tmp); | |
963 | ||
964 | /* Configure PDC */ | |
965 | host->data_size = data->blocks * data->blksz; | |
966 | sg_len = dma_map_sg(&host->pdev->dev, data->sg, data->sg_len, dir); | |
7a90dcc2 LD |
967 | |
968 | if ((!host->caps.has_rwproof) | |
24011f34 | 969 | && (host->data->flags & MMC_DATA_WRITE)) { |
7a90dcc2 LD |
970 | sg_copy_to_buffer(host->data->sg, host->data->sg_len, |
971 | host->buffer, host->data_size); | |
24011f34 LD |
972 | if (host->caps.has_bad_data_ordering) |
973 | for (i = 0; i < host->data_size; i++) | |
974 | host->buffer[i] = swab32(host->buffer[i]); | |
975 | } | |
7a90dcc2 | 976 | |
796211b7 LD |
977 | if (host->data_size) |
978 | atmci_pdc_set_both_buf(host, | |
979 | ((dir == DMA_FROM_DEVICE) ? XFER_RECEIVE : XFER_TRANSMIT)); | |
980 | ||
981 | return iflags; | |
982 | } | |
983 | ||
984 | static u32 | |
74791a2d | 985 | atmci_prepare_data_dma(struct atmel_mci *host, struct mmc_data *data) |
65e8b083 HS |
986 | { |
987 | struct dma_chan *chan; | |
988 | struct dma_async_tx_descriptor *desc; | |
989 | struct scatterlist *sg; | |
990 | unsigned int i; | |
991 | enum dma_data_direction direction; | |
05f5799c | 992 | enum dma_transfer_direction slave_dirn; |
657a77fa | 993 | unsigned int sglen; |
693e5e20 | 994 | u32 maxburst; |
796211b7 LD |
995 | u32 iflags; |
996 | ||
997 | data->error = -EINPROGRESS; | |
998 | ||
999 | WARN_ON(host->data); | |
1000 | host->sg = NULL; | |
1001 | host->data = data; | |
1002 | ||
1003 | iflags = ATMCI_DATA_ERROR_FLAGS; | |
65e8b083 HS |
1004 | |
1005 | /* | |
1006 | * We don't do DMA on "complex" transfers, i.e. with | |
1007 | * non-word-aligned buffers or lengths. Also, we don't bother | |
1008 | * with all the DMA setup overhead for short transfers. | |
1009 | */ | |
796211b7 LD |
1010 | if (data->blocks * data->blksz < ATMCI_DMA_THRESHOLD) |
1011 | return atmci_prepare_data(host, data); | |
65e8b083 | 1012 | if (data->blksz & 3) |
796211b7 | 1013 | return atmci_prepare_data(host, data); |
65e8b083 HS |
1014 | |
1015 | for_each_sg(data->sg, sg, data->sg_len, i) { | |
1016 | if (sg->offset & 3 || sg->length & 3) | |
796211b7 | 1017 | return atmci_prepare_data(host, data); |
65e8b083 HS |
1018 | } |
1019 | ||
1020 | /* If we don't have a channel, we can't do DMA */ | |
1021 | chan = host->dma.chan; | |
6f49a57a | 1022 | if (chan) |
65e8b083 | 1023 | host->data_chan = chan; |
65e8b083 HS |
1024 | |
1025 | if (!chan) | |
1026 | return -ENODEV; | |
1027 | ||
05f5799c | 1028 | if (data->flags & MMC_DATA_READ) { |
65e8b083 | 1029 | direction = DMA_FROM_DEVICE; |
e2b35f3d | 1030 | host->dma_conf.direction = slave_dirn = DMA_DEV_TO_MEM; |
693e5e20 | 1031 | maxburst = atmci_convert_chksize(host->dma_conf.src_maxburst); |
05f5799c | 1032 | } else { |
65e8b083 | 1033 | direction = DMA_TO_DEVICE; |
e2b35f3d | 1034 | host->dma_conf.direction = slave_dirn = DMA_MEM_TO_DEV; |
693e5e20 | 1035 | maxburst = atmci_convert_chksize(host->dma_conf.dst_maxburst); |
05f5799c | 1036 | } |
65e8b083 | 1037 | |
ccdfe612 H |
1038 | if (host->caps.has_dma_conf_reg) |
1039 | atmci_writel(host, ATMCI_DMA, ATMCI_DMA_CHKSIZE(maxburst) | | |
1040 | ATMCI_DMAEN); | |
693e5e20 | 1041 | |
266ac3f2 | 1042 | sglen = dma_map_sg(chan->device->dev, data->sg, |
796211b7 | 1043 | data->sg_len, direction); |
88ce4db3 | 1044 | |
e2b35f3d | 1045 | dmaengine_slave_config(chan, &host->dma_conf); |
16052827 | 1046 | desc = dmaengine_prep_slave_sg(chan, |
05f5799c | 1047 | data->sg, sglen, slave_dirn, |
65e8b083 HS |
1048 | DMA_PREP_INTERRUPT | DMA_CTRL_ACK); |
1049 | if (!desc) | |
657a77fa | 1050 | goto unmap_exit; |
65e8b083 HS |
1051 | |
1052 | host->dma.data_desc = desc; | |
1053 | desc->callback = atmci_dma_complete; | |
1054 | desc->callback_param = host; | |
65e8b083 | 1055 | |
796211b7 | 1056 | return iflags; |
657a77fa | 1057 | unmap_exit: |
88ce4db3 | 1058 | dma_unmap_sg(chan->device->dev, data->sg, data->sg_len, direction); |
657a77fa | 1059 | return -ENOMEM; |
65e8b083 HS |
1060 | } |
1061 | ||
796211b7 LD |
1062 | static void |
1063 | atmci_submit_data(struct atmel_mci *host, struct mmc_data *data) | |
1064 | { | |
1065 | return; | |
1066 | } | |
1067 | ||
1068 | /* | |
1069 | * Start PDC according to transfer direction. | |
1070 | */ | |
1071 | static void | |
1072 | atmci_submit_data_pdc(struct atmel_mci *host, struct mmc_data *data) | |
1073 | { | |
1074 | if (data->flags & MMC_DATA_READ) | |
1075 | atmci_writel(host, ATMEL_PDC_PTCR, ATMEL_PDC_RXTEN); | |
1076 | else | |
1077 | atmci_writel(host, ATMEL_PDC_PTCR, ATMEL_PDC_TXTEN); | |
1078 | } | |
1079 | ||
1080 | static void | |
1081 | atmci_submit_data_dma(struct atmel_mci *host, struct mmc_data *data) | |
74791a2d NF |
1082 | { |
1083 | struct dma_chan *chan = host->data_chan; | |
1084 | struct dma_async_tx_descriptor *desc = host->dma.data_desc; | |
1085 | ||
1086 | if (chan) { | |
5328906a LW |
1087 | dmaengine_submit(desc); |
1088 | dma_async_issue_pending(chan); | |
74791a2d NF |
1089 | } |
1090 | } | |
1091 | ||
796211b7 | 1092 | static void atmci_stop_transfer(struct atmel_mci *host) |
65e8b083 | 1093 | { |
6801c41a LD |
1094 | dev_dbg(&host->pdev->dev, |
1095 | "(%s) set pending xfer complete\n", __func__); | |
65e8b083 | 1096 | atmci_set_pending(host, EVENT_XFER_COMPLETE); |
03fc9a7f | 1097 | atmci_writel(host, ATMCI_IER, ATMCI_NOTBUSY); |
65e8b083 HS |
1098 | } |
1099 | ||
7d2be074 | 1100 | /* |
7122bbb0 | 1101 | * Stop data transfer because error(s) occurred. |
7d2be074 | 1102 | */ |
796211b7 | 1103 | static void atmci_stop_transfer_pdc(struct atmel_mci *host) |
7d2be074 | 1104 | { |
f5177547 | 1105 | atmci_writel(host, ATMEL_PDC_PTCR, ATMEL_PDC_RXTDIS | ATMEL_PDC_TXTDIS); |
796211b7 | 1106 | } |
965ebf33 | 1107 | |
796211b7 LD |
1108 | static void atmci_stop_transfer_dma(struct atmel_mci *host) |
1109 | { | |
1110 | struct dma_chan *chan = host->data_chan; | |
965ebf33 | 1111 | |
796211b7 LD |
1112 | if (chan) { |
1113 | dmaengine_terminate_all(chan); | |
1114 | atmci_dma_cleanup(host); | |
1115 | } else { | |
1116 | /* Data transfer was stopped by the interrupt handler */ | |
6801c41a LD |
1117 | dev_dbg(&host->pdev->dev, |
1118 | "(%s) set pending xfer complete\n", __func__); | |
796211b7 LD |
1119 | atmci_set_pending(host, EVENT_XFER_COMPLETE); |
1120 | atmci_writel(host, ATMCI_IER, ATMCI_NOTBUSY); | |
65e8b083 | 1121 | } |
7d2be074 HS |
1122 | } |
1123 | ||
796211b7 LD |
1124 | /* |
1125 | * Start a request: prepare data if needed, prepare the command and activate | |
1126 | * interrupts. | |
1127 | */ | |
965ebf33 HS |
1128 | static void atmci_start_request(struct atmel_mci *host, |
1129 | struct atmel_mci_slot *slot) | |
7d2be074 | 1130 | { |
965ebf33 | 1131 | struct mmc_request *mrq; |
7d2be074 | 1132 | struct mmc_command *cmd; |
965ebf33 | 1133 | struct mmc_data *data; |
7d2be074 | 1134 | u32 iflags; |
965ebf33 | 1135 | u32 cmdflags; |
7d2be074 | 1136 | |
965ebf33 HS |
1137 | mrq = slot->mrq; |
1138 | host->cur_slot = slot; | |
7d2be074 | 1139 | host->mrq = mrq; |
965ebf33 | 1140 | |
7d2be074 HS |
1141 | host->pending_events = 0; |
1142 | host->completed_events = 0; | |
f5177547 | 1143 | host->cmd_status = 0; |
ca55f46e | 1144 | host->data_status = 0; |
7d2be074 | 1145 | |
6801c41a LD |
1146 | dev_dbg(&host->pdev->dev, "start request: cmd %u\n", mrq->cmd->opcode); |
1147 | ||
24011f34 | 1148 | if (host->need_reset || host->caps.need_reset_after_xfer) { |
18ee684b LD |
1149 | iflags = atmci_readl(host, ATMCI_IMR); |
1150 | iflags &= (ATMCI_SDIOIRQA | ATMCI_SDIOIRQB); | |
03fc9a7f LD |
1151 | atmci_writel(host, ATMCI_CR, ATMCI_CR_SWRST); |
1152 | atmci_writel(host, ATMCI_CR, ATMCI_CR_MCIEN); | |
1153 | atmci_writel(host, ATMCI_MR, host->mode_reg); | |
796211b7 | 1154 | if (host->caps.has_cfg_reg) |
03fc9a7f | 1155 | atmci_writel(host, ATMCI_CFG, host->cfg_reg); |
18ee684b | 1156 | atmci_writel(host, ATMCI_IER, iflags); |
965ebf33 HS |
1157 | host->need_reset = false; |
1158 | } | |
03fc9a7f | 1159 | atmci_writel(host, ATMCI_SDCR, slot->sdc_reg); |
965ebf33 | 1160 | |
03fc9a7f | 1161 | iflags = atmci_readl(host, ATMCI_IMR); |
2c96a293 | 1162 | if (iflags & ~(ATMCI_SDIOIRQA | ATMCI_SDIOIRQB)) |
f5177547 | 1163 | dev_dbg(&slot->mmc->class_dev, "WARNING: IMR=0x%08x\n", |
965ebf33 HS |
1164 | iflags); |
1165 | ||
1166 | if (unlikely(test_and_clear_bit(ATMCI_CARD_NEED_INIT, &slot->flags))) { | |
1167 | /* Send init sequence (74 clock cycles) */ | |
03fc9a7f LD |
1168 | atmci_writel(host, ATMCI_CMDR, ATMCI_CMDR_SPCMD_INIT); |
1169 | while (!(atmci_readl(host, ATMCI_SR) & ATMCI_CMDRDY)) | |
965ebf33 HS |
1170 | cpu_relax(); |
1171 | } | |
74791a2d | 1172 | iflags = 0; |
7d2be074 HS |
1173 | data = mrq->data; |
1174 | if (data) { | |
965ebf33 | 1175 | atmci_set_timeout(host, slot, data); |
a252e3e3 HS |
1176 | |
1177 | /* Must set block count/size before sending command */ | |
03fc9a7f | 1178 | atmci_writel(host, ATMCI_BLKR, ATMCI_BCNT(data->blocks) |
2c96a293 | 1179 | | ATMCI_BLKLEN(data->blksz)); |
965ebf33 | 1180 | dev_vdbg(&slot->mmc->class_dev, "BLKR=0x%08x\n", |
2c96a293 | 1181 | ATMCI_BCNT(data->blocks) | ATMCI_BLKLEN(data->blksz)); |
74791a2d | 1182 | |
796211b7 | 1183 | iflags |= host->prepare_data(host, data); |
7d2be074 HS |
1184 | } |
1185 | ||
2c96a293 | 1186 | iflags |= ATMCI_CMDRDY; |
7d2be074 | 1187 | cmd = mrq->cmd; |
965ebf33 | 1188 | cmdflags = atmci_prepare_command(slot->mmc, cmd); |
11d1488b | 1189 | atmci_send_command(host, cmd, cmdflags); |
7d2be074 HS |
1190 | |
1191 | if (data) | |
796211b7 | 1192 | host->submit_data(host, data); |
7d2be074 HS |
1193 | |
1194 | if (mrq->stop) { | |
965ebf33 | 1195 | host->stop_cmdr = atmci_prepare_command(slot->mmc, mrq->stop); |
2c96a293 | 1196 | host->stop_cmdr |= ATMCI_CMDR_STOP_XFER; |
7d2be074 | 1197 | if (!(data->flags & MMC_DATA_WRITE)) |
2c96a293 | 1198 | host->stop_cmdr |= ATMCI_CMDR_TRDIR_READ; |
7d2be074 | 1199 | if (data->flags & MMC_DATA_STREAM) |
2c96a293 | 1200 | host->stop_cmdr |= ATMCI_CMDR_STREAM; |
7d2be074 | 1201 | else |
2c96a293 | 1202 | host->stop_cmdr |= ATMCI_CMDR_MULTI_BLOCK; |
7d2be074 HS |
1203 | } |
1204 | ||
1205 | /* | |
1206 | * We could have enabled interrupts earlier, but I suspect | |
1207 | * that would open up a nice can of interesting race | |
1208 | * conditions (e.g. command and data complete, but stop not | |
1209 | * prepared yet.) | |
1210 | */ | |
03fc9a7f | 1211 | atmci_writel(host, ATMCI_IER, iflags); |
24011f34 LD |
1212 | |
1213 | mod_timer(&host->timer, jiffies + msecs_to_jiffies(2000)); | |
965ebf33 | 1214 | } |
7d2be074 | 1215 | |
965ebf33 HS |
1216 | static void atmci_queue_request(struct atmel_mci *host, |
1217 | struct atmel_mci_slot *slot, struct mmc_request *mrq) | |
1218 | { | |
1219 | dev_vdbg(&slot->mmc->class_dev, "queue request: state=%d\n", | |
1220 | host->state); | |
1221 | ||
1222 | spin_lock_bh(&host->lock); | |
1223 | slot->mrq = mrq; | |
1224 | if (host->state == STATE_IDLE) { | |
1225 | host->state = STATE_SENDING_CMD; | |
1226 | atmci_start_request(host, slot); | |
1227 | } else { | |
6801c41a | 1228 | dev_dbg(&host->pdev->dev, "queue request\n"); |
965ebf33 HS |
1229 | list_add_tail(&slot->queue_node, &host->queue); |
1230 | } | |
1231 | spin_unlock_bh(&host->lock); | |
1232 | } | |
7d2be074 | 1233 | |
965ebf33 HS |
1234 | static void atmci_request(struct mmc_host *mmc, struct mmc_request *mrq) |
1235 | { | |
1236 | struct atmel_mci_slot *slot = mmc_priv(mmc); | |
1237 | struct atmel_mci *host = slot->host; | |
1238 | struct mmc_data *data; | |
1239 | ||
1240 | WARN_ON(slot->mrq); | |
6801c41a | 1241 | dev_dbg(&host->pdev->dev, "MRQ: cmd %u\n", mrq->cmd->opcode); |
965ebf33 HS |
1242 | |
1243 | /* | |
1244 | * We may "know" the card is gone even though there's still an | |
1245 | * electrical connection. If so, we really need to communicate | |
1246 | * this to the MMC core since there won't be any more | |
1247 | * interrupts as the card is completely removed. Otherwise, | |
1248 | * the MMC core might believe the card is still there even | |
1249 | * though the card was just removed very slowly. | |
1250 | */ | |
1251 | if (!test_bit(ATMCI_CARD_PRESENT, &slot->flags)) { | |
1252 | mrq->cmd->error = -ENOMEDIUM; | |
1253 | mmc_request_done(mmc, mrq); | |
1254 | return; | |
1255 | } | |
1256 | ||
1257 | /* We don't support multiple blocks of weird lengths. */ | |
1258 | data = mrq->data; | |
1259 | if (data && data->blocks > 1 && data->blksz & 3) { | |
1260 | mrq->cmd->error = -EINVAL; | |
1261 | mmc_request_done(mmc, mrq); | |
1262 | } | |
1263 | ||
1264 | atmci_queue_request(host, slot, mrq); | |
7d2be074 HS |
1265 | } |
1266 | ||
1267 | static void atmci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) | |
1268 | { | |
965ebf33 HS |
1269 | struct atmel_mci_slot *slot = mmc_priv(mmc); |
1270 | struct atmel_mci *host = slot->host; | |
1271 | unsigned int i; | |
b3894f26 | 1272 | bool unprepare_clk; |
7d2be074 | 1273 | |
2c96a293 | 1274 | slot->sdc_reg &= ~ATMCI_SDCBUS_MASK; |
945533b5 HS |
1275 | switch (ios->bus_width) { |
1276 | case MMC_BUS_WIDTH_1: | |
2c96a293 | 1277 | slot->sdc_reg |= ATMCI_SDCBUS_1BIT; |
945533b5 HS |
1278 | break; |
1279 | case MMC_BUS_WIDTH_4: | |
2c96a293 | 1280 | slot->sdc_reg |= ATMCI_SDCBUS_4BIT; |
945533b5 HS |
1281 | break; |
1282 | } | |
1283 | ||
7d2be074 | 1284 | if (ios->clock) { |
965ebf33 | 1285 | unsigned int clock_min = ~0U; |
7d2be074 HS |
1286 | u32 clkdiv; |
1287 | ||
b3894f26 BB |
1288 | clk_prepare(host->mck); |
1289 | unprepare_clk = true; | |
1290 | ||
965ebf33 HS |
1291 | spin_lock_bh(&host->lock); |
1292 | if (!host->mode_reg) { | |
945533b5 | 1293 | clk_enable(host->mck); |
b3894f26 | 1294 | unprepare_clk = false; |
03fc9a7f LD |
1295 | atmci_writel(host, ATMCI_CR, ATMCI_CR_SWRST); |
1296 | atmci_writel(host, ATMCI_CR, ATMCI_CR_MCIEN); | |
796211b7 | 1297 | if (host->caps.has_cfg_reg) |
03fc9a7f | 1298 | atmci_writel(host, ATMCI_CFG, host->cfg_reg); |
965ebf33 | 1299 | } |
945533b5 | 1300 | |
965ebf33 HS |
1301 | /* |
1302 | * Use mirror of ios->clock to prevent race with mmc | |
1303 | * core ios update when finding the minimum. | |
1304 | */ | |
1305 | slot->clock = ios->clock; | |
2c96a293 | 1306 | for (i = 0; i < ATMCI_MAX_NR_SLOTS; i++) { |
965ebf33 HS |
1307 | if (host->slot[i] && host->slot[i]->clock |
1308 | && host->slot[i]->clock < clock_min) | |
1309 | clock_min = host->slot[i]->clock; | |
1310 | } | |
1311 | ||
1312 | /* Calculate clock divider */ | |
faf8180b LD |
1313 | if (host->caps.has_odd_clk_div) { |
1314 | clkdiv = DIV_ROUND_UP(host->bus_hz, clock_min) - 2; | |
1315 | if (clkdiv > 511) { | |
1316 | dev_warn(&mmc->class_dev, | |
1317 | "clock %u too slow; using %lu\n", | |
1318 | clock_min, host->bus_hz / (511 + 2)); | |
1319 | clkdiv = 511; | |
1320 | } | |
1321 | host->mode_reg = ATMCI_MR_CLKDIV(clkdiv >> 1) | |
1322 | | ATMCI_MR_CLKODD(clkdiv & 1); | |
1323 | } else { | |
1324 | clkdiv = DIV_ROUND_UP(host->bus_hz, 2 * clock_min) - 1; | |
1325 | if (clkdiv > 255) { | |
1326 | dev_warn(&mmc->class_dev, | |
1327 | "clock %u too slow; using %lu\n", | |
1328 | clock_min, host->bus_hz / (2 * 256)); | |
1329 | clkdiv = 255; | |
1330 | } | |
1331 | host->mode_reg = ATMCI_MR_CLKDIV(clkdiv); | |
7d2be074 HS |
1332 | } |
1333 | ||
965ebf33 HS |
1334 | /* |
1335 | * WRPROOF and RDPROOF prevent overruns/underruns by | |
1336 | * stopping the clock when the FIFO is full/empty. | |
1337 | * This state is not expected to last for long. | |
1338 | */ | |
796211b7 | 1339 | if (host->caps.has_rwproof) |
2c96a293 | 1340 | host->mode_reg |= (ATMCI_MR_WRPROOF | ATMCI_MR_RDPROOF); |
7d2be074 | 1341 | |
796211b7 | 1342 | if (host->caps.has_cfg_reg) { |
99ddffd8 NF |
1343 | /* setup High Speed mode in relation with card capacity */ |
1344 | if (ios->timing == MMC_TIMING_SD_HS) | |
2c96a293 | 1345 | host->cfg_reg |= ATMCI_CFG_HSMODE; |
99ddffd8 | 1346 | else |
2c96a293 | 1347 | host->cfg_reg &= ~ATMCI_CFG_HSMODE; |
99ddffd8 NF |
1348 | } |
1349 | ||
1350 | if (list_empty(&host->queue)) { | |
03fc9a7f | 1351 | atmci_writel(host, ATMCI_MR, host->mode_reg); |
796211b7 | 1352 | if (host->caps.has_cfg_reg) |
03fc9a7f | 1353 | atmci_writel(host, ATMCI_CFG, host->cfg_reg); |
99ddffd8 | 1354 | } else { |
965ebf33 | 1355 | host->need_clock_update = true; |
99ddffd8 | 1356 | } |
965ebf33 HS |
1357 | |
1358 | spin_unlock_bh(&host->lock); | |
945533b5 | 1359 | } else { |
965ebf33 HS |
1360 | bool any_slot_active = false; |
1361 | ||
b3894f26 BB |
1362 | unprepare_clk = false; |
1363 | ||
965ebf33 HS |
1364 | spin_lock_bh(&host->lock); |
1365 | slot->clock = 0; | |
2c96a293 | 1366 | for (i = 0; i < ATMCI_MAX_NR_SLOTS; i++) { |
965ebf33 HS |
1367 | if (host->slot[i] && host->slot[i]->clock) { |
1368 | any_slot_active = true; | |
1369 | break; | |
1370 | } | |
945533b5 | 1371 | } |
965ebf33 | 1372 | if (!any_slot_active) { |
03fc9a7f | 1373 | atmci_writel(host, ATMCI_CR, ATMCI_CR_MCIDIS); |
965ebf33 | 1374 | if (host->mode_reg) { |
03fc9a7f | 1375 | atmci_readl(host, ATMCI_MR); |
965ebf33 | 1376 | clk_disable(host->mck); |
b3894f26 | 1377 | unprepare_clk = true; |
965ebf33 HS |
1378 | } |
1379 | host->mode_reg = 0; | |
1380 | } | |
1381 | spin_unlock_bh(&host->lock); | |
7d2be074 HS |
1382 | } |
1383 | ||
b3894f26 BB |
1384 | if (unprepare_clk) |
1385 | clk_unprepare(host->mck); | |
1386 | ||
7d2be074 | 1387 | switch (ios->power_mode) { |
965ebf33 HS |
1388 | case MMC_POWER_UP: |
1389 | set_bit(ATMCI_CARD_NEED_INIT, &slot->flags); | |
1390 | break; | |
7d2be074 HS |
1391 | default: |
1392 | /* | |
1393 | * TODO: None of the currently available AVR32-based | |
1394 | * boards allow MMC power to be turned off. Implement | |
1395 | * power control when this can be tested properly. | |
965ebf33 HS |
1396 | * |
1397 | * We also need to hook this into the clock management | |
1398 | * somehow so that newly inserted cards aren't | |
1399 | * subjected to a fast clock before we have a chance | |
1400 | * to figure out what the maximum rate is. Currently, | |
1401 | * there's no way to avoid this, and there never will | |
1402 | * be for boards that don't support power control. | |
7d2be074 HS |
1403 | */ |
1404 | break; | |
1405 | } | |
1406 | } | |
1407 | ||
1408 | static int atmci_get_ro(struct mmc_host *mmc) | |
1409 | { | |
965ebf33 HS |
1410 | int read_only = -ENOSYS; |
1411 | struct atmel_mci_slot *slot = mmc_priv(mmc); | |
7d2be074 | 1412 | |
965ebf33 HS |
1413 | if (gpio_is_valid(slot->wp_pin)) { |
1414 | read_only = gpio_get_value(slot->wp_pin); | |
7d2be074 HS |
1415 | dev_dbg(&mmc->class_dev, "card is %s\n", |
1416 | read_only ? "read-only" : "read-write"); | |
7d2be074 HS |
1417 | } |
1418 | ||
1419 | return read_only; | |
1420 | } | |
1421 | ||
965ebf33 HS |
1422 | static int atmci_get_cd(struct mmc_host *mmc) |
1423 | { | |
1424 | int present = -ENOSYS; | |
1425 | struct atmel_mci_slot *slot = mmc_priv(mmc); | |
1426 | ||
1427 | if (gpio_is_valid(slot->detect_pin)) { | |
1c1452be JL |
1428 | present = !(gpio_get_value(slot->detect_pin) ^ |
1429 | slot->detect_is_active_high); | |
965ebf33 HS |
1430 | dev_dbg(&mmc->class_dev, "card is %spresent\n", |
1431 | present ? "" : "not "); | |
1432 | } | |
1433 | ||
1434 | return present; | |
1435 | } | |
1436 | ||
88ff82ed AG |
1437 | static void atmci_enable_sdio_irq(struct mmc_host *mmc, int enable) |
1438 | { | |
1439 | struct atmel_mci_slot *slot = mmc_priv(mmc); | |
1440 | struct atmel_mci *host = slot->host; | |
1441 | ||
1442 | if (enable) | |
03fc9a7f | 1443 | atmci_writel(host, ATMCI_IER, slot->sdio_irq); |
88ff82ed | 1444 | else |
03fc9a7f | 1445 | atmci_writel(host, ATMCI_IDR, slot->sdio_irq); |
88ff82ed AG |
1446 | } |
1447 | ||
965ebf33 | 1448 | static const struct mmc_host_ops atmci_ops = { |
7d2be074 HS |
1449 | .request = atmci_request, |
1450 | .set_ios = atmci_set_ios, | |
1451 | .get_ro = atmci_get_ro, | |
965ebf33 | 1452 | .get_cd = atmci_get_cd, |
88ff82ed | 1453 | .enable_sdio_irq = atmci_enable_sdio_irq, |
7d2be074 HS |
1454 | }; |
1455 | ||
965ebf33 HS |
1456 | /* Called with host->lock held */ |
1457 | static void atmci_request_end(struct atmel_mci *host, struct mmc_request *mrq) | |
1458 | __releases(&host->lock) | |
1459 | __acquires(&host->lock) | |
1460 | { | |
1461 | struct atmel_mci_slot *slot = NULL; | |
1462 | struct mmc_host *prev_mmc = host->cur_slot->mmc; | |
1463 | ||
1464 | WARN_ON(host->cmd || host->data); | |
1465 | ||
1466 | /* | |
1467 | * Update the MMC clock rate if necessary. This may be | |
1468 | * necessary if set_ios() is called when a different slot is | |
25985edc | 1469 | * busy transferring data. |
965ebf33 | 1470 | */ |
99ddffd8 | 1471 | if (host->need_clock_update) { |
03fc9a7f | 1472 | atmci_writel(host, ATMCI_MR, host->mode_reg); |
796211b7 | 1473 | if (host->caps.has_cfg_reg) |
03fc9a7f | 1474 | atmci_writel(host, ATMCI_CFG, host->cfg_reg); |
99ddffd8 | 1475 | } |
965ebf33 HS |
1476 | |
1477 | host->cur_slot->mrq = NULL; | |
1478 | host->mrq = NULL; | |
1479 | if (!list_empty(&host->queue)) { | |
1480 | slot = list_entry(host->queue.next, | |
1481 | struct atmel_mci_slot, queue_node); | |
1482 | list_del(&slot->queue_node); | |
1483 | dev_vdbg(&host->pdev->dev, "list not empty: %s is next\n", | |
1484 | mmc_hostname(slot->mmc)); | |
1485 | host->state = STATE_SENDING_CMD; | |
1486 | atmci_start_request(host, slot); | |
1487 | } else { | |
1488 | dev_vdbg(&host->pdev->dev, "list empty\n"); | |
1489 | host->state = STATE_IDLE; | |
1490 | } | |
1491 | ||
24011f34 LD |
1492 | del_timer(&host->timer); |
1493 | ||
965ebf33 HS |
1494 | spin_unlock(&host->lock); |
1495 | mmc_request_done(prev_mmc, mrq); | |
1496 | spin_lock(&host->lock); | |
1497 | } | |
1498 | ||
7d2be074 | 1499 | static void atmci_command_complete(struct atmel_mci *host, |
c06ad258 | 1500 | struct mmc_command *cmd) |
7d2be074 | 1501 | { |
c06ad258 HS |
1502 | u32 status = host->cmd_status; |
1503 | ||
7d2be074 | 1504 | /* Read the response from the card (up to 16 bytes) */ |
03fc9a7f LD |
1505 | cmd->resp[0] = atmci_readl(host, ATMCI_RSPR); |
1506 | cmd->resp[1] = atmci_readl(host, ATMCI_RSPR); | |
1507 | cmd->resp[2] = atmci_readl(host, ATMCI_RSPR); | |
1508 | cmd->resp[3] = atmci_readl(host, ATMCI_RSPR); | |
7d2be074 | 1509 | |
2c96a293 | 1510 | if (status & ATMCI_RTOE) |
7d2be074 | 1511 | cmd->error = -ETIMEDOUT; |
2c96a293 | 1512 | else if ((cmd->flags & MMC_RSP_CRC) && (status & ATMCI_RCRCE)) |
7d2be074 | 1513 | cmd->error = -EILSEQ; |
2c96a293 | 1514 | else if (status & (ATMCI_RINDE | ATMCI_RDIRE | ATMCI_RENDE)) |
7d2be074 | 1515 | cmd->error = -EIO; |
24011f34 LD |
1516 | else if (host->mrq->data && (host->mrq->data->blksz & 3)) { |
1517 | if (host->caps.need_blksz_mul_4) { | |
1518 | cmd->error = -EINVAL; | |
1519 | host->need_reset = 1; | |
1520 | } | |
1521 | } else | |
7d2be074 | 1522 | cmd->error = 0; |
7d2be074 HS |
1523 | } |
1524 | ||
1525 | static void atmci_detect_change(unsigned long data) | |
1526 | { | |
965ebf33 HS |
1527 | struct atmel_mci_slot *slot = (struct atmel_mci_slot *)data; |
1528 | bool present; | |
1529 | bool present_old; | |
7d2be074 HS |
1530 | |
1531 | /* | |
965ebf33 HS |
1532 | * atmci_cleanup_slot() sets the ATMCI_SHUTDOWN flag before |
1533 | * freeing the interrupt. We must not re-enable the interrupt | |
1534 | * if it has been freed, and if we're shutting down, it | |
1535 | * doesn't really matter whether the card is present or not. | |
7d2be074 HS |
1536 | */ |
1537 | smp_rmb(); | |
965ebf33 | 1538 | if (test_bit(ATMCI_SHUTDOWN, &slot->flags)) |
7d2be074 HS |
1539 | return; |
1540 | ||
965ebf33 | 1541 | enable_irq(gpio_to_irq(slot->detect_pin)); |
1c1452be JL |
1542 | present = !(gpio_get_value(slot->detect_pin) ^ |
1543 | slot->detect_is_active_high); | |
965ebf33 | 1544 | present_old = test_bit(ATMCI_CARD_PRESENT, &slot->flags); |
7d2be074 | 1545 | |
965ebf33 HS |
1546 | dev_vdbg(&slot->mmc->class_dev, "detect change: %d (was %d)\n", |
1547 | present, present_old); | |
7d2be074 | 1548 | |
965ebf33 HS |
1549 | if (present != present_old) { |
1550 | struct atmel_mci *host = slot->host; | |
1551 | struct mmc_request *mrq; | |
1552 | ||
1553 | dev_dbg(&slot->mmc->class_dev, "card %s\n", | |
7d2be074 | 1554 | present ? "inserted" : "removed"); |
7d2be074 | 1555 | |
965ebf33 HS |
1556 | spin_lock(&host->lock); |
1557 | ||
1558 | if (!present) | |
1559 | clear_bit(ATMCI_CARD_PRESENT, &slot->flags); | |
1560 | else | |
1561 | set_bit(ATMCI_CARD_PRESENT, &slot->flags); | |
7d2be074 HS |
1562 | |
1563 | /* Clean up queue if present */ | |
965ebf33 | 1564 | mrq = slot->mrq; |
7d2be074 | 1565 | if (mrq) { |
965ebf33 HS |
1566 | if (mrq == host->mrq) { |
1567 | /* | |
1568 | * Reset controller to terminate any ongoing | |
1569 | * commands or data transfers. | |
1570 | */ | |
03fc9a7f LD |
1571 | atmci_writel(host, ATMCI_CR, ATMCI_CR_SWRST); |
1572 | atmci_writel(host, ATMCI_CR, ATMCI_CR_MCIEN); | |
1573 | atmci_writel(host, ATMCI_MR, host->mode_reg); | |
796211b7 | 1574 | if (host->caps.has_cfg_reg) |
03fc9a7f | 1575 | atmci_writel(host, ATMCI_CFG, host->cfg_reg); |
965ebf33 HS |
1576 | |
1577 | host->data = NULL; | |
1578 | host->cmd = NULL; | |
1579 | ||
1580 | switch (host->state) { | |
1581 | case STATE_IDLE: | |
c06ad258 | 1582 | break; |
965ebf33 HS |
1583 | case STATE_SENDING_CMD: |
1584 | mrq->cmd->error = -ENOMEDIUM; | |
f5177547 LD |
1585 | if (mrq->data) |
1586 | host->stop_transfer(host); | |
1587 | break; | |
1588 | case STATE_DATA_XFER: | |
c06ad258 | 1589 | mrq->data->error = -ENOMEDIUM; |
796211b7 | 1590 | host->stop_transfer(host); |
c06ad258 | 1591 | break; |
f5177547 LD |
1592 | case STATE_WAITING_NOTBUSY: |
1593 | mrq->data->error = -ENOMEDIUM; | |
1594 | break; | |
965ebf33 HS |
1595 | case STATE_SENDING_STOP: |
1596 | mrq->stop->error = -ENOMEDIUM; | |
1597 | break; | |
f5177547 LD |
1598 | case STATE_END_REQUEST: |
1599 | break; | |
965ebf33 | 1600 | } |
7d2be074 | 1601 | |
965ebf33 HS |
1602 | atmci_request_end(host, mrq); |
1603 | } else { | |
1604 | list_del(&slot->queue_node); | |
1605 | mrq->cmd->error = -ENOMEDIUM; | |
1606 | if (mrq->data) | |
1607 | mrq->data->error = -ENOMEDIUM; | |
1608 | if (mrq->stop) | |
1609 | mrq->stop->error = -ENOMEDIUM; | |
1610 | ||
1611 | spin_unlock(&host->lock); | |
1612 | mmc_request_done(slot->mmc, mrq); | |
1613 | spin_lock(&host->lock); | |
1614 | } | |
7d2be074 | 1615 | } |
965ebf33 | 1616 | spin_unlock(&host->lock); |
7d2be074 | 1617 | |
965ebf33 | 1618 | mmc_detect_change(slot->mmc, 0); |
7d2be074 HS |
1619 | } |
1620 | } | |
1621 | ||
1622 | static void atmci_tasklet_func(unsigned long priv) | |
1623 | { | |
965ebf33 | 1624 | struct atmel_mci *host = (struct atmel_mci *)priv; |
7d2be074 HS |
1625 | struct mmc_request *mrq = host->mrq; |
1626 | struct mmc_data *data = host->data; | |
c06ad258 HS |
1627 | enum atmel_mci_state state = host->state; |
1628 | enum atmel_mci_state prev_state; | |
1629 | u32 status; | |
1630 | ||
965ebf33 HS |
1631 | spin_lock(&host->lock); |
1632 | ||
c06ad258 | 1633 | state = host->state; |
7d2be074 | 1634 | |
965ebf33 | 1635 | dev_vdbg(&host->pdev->dev, |
c06ad258 HS |
1636 | "tasklet: state %u pending/completed/mask %lx/%lx/%x\n", |
1637 | state, host->pending_events, host->completed_events, | |
03fc9a7f | 1638 | atmci_readl(host, ATMCI_IMR)); |
7d2be074 | 1639 | |
c06ad258 HS |
1640 | do { |
1641 | prev_state = state; | |
6801c41a | 1642 | dev_dbg(&host->pdev->dev, "FSM: state=%d\n", state); |
7d2be074 | 1643 | |
c06ad258 | 1644 | switch (state) { |
965ebf33 HS |
1645 | case STATE_IDLE: |
1646 | break; | |
1647 | ||
c06ad258 | 1648 | case STATE_SENDING_CMD: |
f5177547 LD |
1649 | /* |
1650 | * Command has been sent, we are waiting for command | |
1651 | * ready. Then we have three next states possible: | |
1652 | * END_REQUEST by default, WAITING_NOTBUSY if it's a | |
1653 | * command needing it or DATA_XFER if there is data. | |
1654 | */ | |
6801c41a | 1655 | dev_dbg(&host->pdev->dev, "FSM: cmd ready?\n"); |
c06ad258 | 1656 | if (!atmci_test_and_clear_pending(host, |
f5177547 | 1657 | EVENT_CMD_RDY)) |
c06ad258 | 1658 | break; |
7d2be074 | 1659 | |
6801c41a | 1660 | dev_dbg(&host->pdev->dev, "set completed cmd ready\n"); |
c06ad258 | 1661 | host->cmd = NULL; |
f5177547 | 1662 | atmci_set_completed(host, EVENT_CMD_RDY); |
c06ad258 | 1663 | atmci_command_complete(host, mrq->cmd); |
f5177547 | 1664 | if (mrq->data) { |
6801c41a LD |
1665 | dev_dbg(&host->pdev->dev, |
1666 | "command with data transfer"); | |
f5177547 LD |
1667 | /* |
1668 | * If there is a command error don't start | |
1669 | * data transfer. | |
1670 | */ | |
1671 | if (mrq->cmd->error) { | |
1672 | host->stop_transfer(host); | |
1673 | host->data = NULL; | |
1674 | atmci_writel(host, ATMCI_IDR, | |
1675 | ATMCI_TXRDY | ATMCI_RXRDY | |
1676 | | ATMCI_DATA_ERROR_FLAGS); | |
1677 | state = STATE_END_REQUEST; | |
1678 | } else | |
1679 | state = STATE_DATA_XFER; | |
1680 | } else if ((!mrq->data) && (mrq->cmd->flags & MMC_RSP_BUSY)) { | |
6801c41a LD |
1681 | dev_dbg(&host->pdev->dev, |
1682 | "command response need waiting notbusy"); | |
f5177547 LD |
1683 | atmci_writel(host, ATMCI_IER, ATMCI_NOTBUSY); |
1684 | state = STATE_WAITING_NOTBUSY; | |
1685 | } else | |
1686 | state = STATE_END_REQUEST; | |
7d2be074 | 1687 | |
f5177547 | 1688 | break; |
7d2be074 | 1689 | |
f5177547 | 1690 | case STATE_DATA_XFER: |
c06ad258 HS |
1691 | if (atmci_test_and_clear_pending(host, |
1692 | EVENT_DATA_ERROR)) { | |
6801c41a | 1693 | dev_dbg(&host->pdev->dev, "set completed data error\n"); |
f5177547 LD |
1694 | atmci_set_completed(host, EVENT_DATA_ERROR); |
1695 | state = STATE_END_REQUEST; | |
c06ad258 HS |
1696 | break; |
1697 | } | |
7d2be074 | 1698 | |
f5177547 LD |
1699 | /* |
1700 | * A data transfer is in progress. The event expected | |
1701 | * to move to the next state depends of data transfer | |
1702 | * type (PDC or DMA). Once transfer done we can move | |
1703 | * to the next step which is WAITING_NOTBUSY in write | |
1704 | * case and directly SENDING_STOP in read case. | |
1705 | */ | |
6801c41a | 1706 | dev_dbg(&host->pdev->dev, "FSM: xfer complete?\n"); |
c06ad258 HS |
1707 | if (!atmci_test_and_clear_pending(host, |
1708 | EVENT_XFER_COMPLETE)) | |
1709 | break; | |
7d2be074 | 1710 | |
6801c41a LD |
1711 | dev_dbg(&host->pdev->dev, |
1712 | "(%s) set completed xfer complete\n", | |
1713 | __func__); | |
c06ad258 | 1714 | atmci_set_completed(host, EVENT_XFER_COMPLETE); |
7d2be074 | 1715 | |
077d4073 LD |
1716 | if (host->caps.need_notbusy_for_read_ops || |
1717 | (host->data->flags & MMC_DATA_WRITE)) { | |
f5177547 LD |
1718 | atmci_writel(host, ATMCI_IER, ATMCI_NOTBUSY); |
1719 | state = STATE_WAITING_NOTBUSY; | |
1720 | } else if (host->mrq->stop) { | |
1721 | atmci_writel(host, ATMCI_IER, ATMCI_CMDRDY); | |
1722 | atmci_send_stop_cmd(host, data); | |
1723 | state = STATE_SENDING_STOP; | |
c06ad258 | 1724 | } else { |
f5177547 | 1725 | host->data = NULL; |
c06ad258 HS |
1726 | data->bytes_xfered = data->blocks * data->blksz; |
1727 | data->error = 0; | |
f5177547 | 1728 | state = STATE_END_REQUEST; |
c06ad258 | 1729 | } |
f5177547 | 1730 | break; |
c06ad258 | 1731 | |
f5177547 LD |
1732 | case STATE_WAITING_NOTBUSY: |
1733 | /* | |
1734 | * We can be in the state for two reasons: a command | |
1735 | * requiring waiting not busy signal (stop command | |
1736 | * included) or a write operation. In the latest case, | |
1737 | * we need to send a stop command. | |
1738 | */ | |
6801c41a | 1739 | dev_dbg(&host->pdev->dev, "FSM: not busy?\n"); |
f5177547 LD |
1740 | if (!atmci_test_and_clear_pending(host, |
1741 | EVENT_NOTBUSY)) | |
1742 | break; | |
7d2be074 | 1743 | |
6801c41a | 1744 | dev_dbg(&host->pdev->dev, "set completed not busy\n"); |
f5177547 LD |
1745 | atmci_set_completed(host, EVENT_NOTBUSY); |
1746 | ||
1747 | if (host->data) { | |
1748 | /* | |
1749 | * For some commands such as CMD53, even if | |
1750 | * there is data transfer, there is no stop | |
1751 | * command to send. | |
1752 | */ | |
1753 | if (host->mrq->stop) { | |
1754 | atmci_writel(host, ATMCI_IER, | |
1755 | ATMCI_CMDRDY); | |
1756 | atmci_send_stop_cmd(host, data); | |
1757 | state = STATE_SENDING_STOP; | |
1758 | } else { | |
1759 | host->data = NULL; | |
1760 | data->bytes_xfered = data->blocks | |
1761 | * data->blksz; | |
1762 | data->error = 0; | |
1763 | state = STATE_END_REQUEST; | |
1764 | } | |
1765 | } else | |
1766 | state = STATE_END_REQUEST; | |
1767 | break; | |
c06ad258 HS |
1768 | |
1769 | case STATE_SENDING_STOP: | |
f5177547 LD |
1770 | /* |
1771 | * In this state, it is important to set host->data to | |
1772 | * NULL (which is tested in the waiting notbusy state) | |
1773 | * in order to go to the end request state instead of | |
1774 | * sending stop again. | |
1775 | */ | |
6801c41a | 1776 | dev_dbg(&host->pdev->dev, "FSM: cmd ready?\n"); |
c06ad258 | 1777 | if (!atmci_test_and_clear_pending(host, |
f5177547 | 1778 | EVENT_CMD_RDY)) |
c06ad258 HS |
1779 | break; |
1780 | ||
6801c41a | 1781 | dev_dbg(&host->pdev->dev, "FSM: cmd ready\n"); |
c06ad258 | 1782 | host->cmd = NULL; |
f5177547 LD |
1783 | data->bytes_xfered = data->blocks * data->blksz; |
1784 | data->error = 0; | |
c06ad258 | 1785 | atmci_command_complete(host, mrq->stop); |
f5177547 LD |
1786 | if (mrq->stop->error) { |
1787 | host->stop_transfer(host); | |
1788 | atmci_writel(host, ATMCI_IDR, | |
1789 | ATMCI_TXRDY | ATMCI_RXRDY | |
1790 | | ATMCI_DATA_ERROR_FLAGS); | |
1791 | state = STATE_END_REQUEST; | |
1792 | } else { | |
1793 | atmci_writel(host, ATMCI_IER, ATMCI_NOTBUSY); | |
1794 | state = STATE_WAITING_NOTBUSY; | |
1795 | } | |
41b4e9a1 | 1796 | host->data = NULL; |
f5177547 | 1797 | break; |
c06ad258 | 1798 | |
f5177547 LD |
1799 | case STATE_END_REQUEST: |
1800 | atmci_writel(host, ATMCI_IDR, ATMCI_TXRDY | ATMCI_RXRDY | |
1801 | | ATMCI_DATA_ERROR_FLAGS); | |
1802 | status = host->data_status; | |
1803 | if (unlikely(status)) { | |
1804 | host->stop_transfer(host); | |
1805 | host->data = NULL; | |
1806 | if (status & ATMCI_DTOE) { | |
1807 | data->error = -ETIMEDOUT; | |
1808 | } else if (status & ATMCI_DCRCE) { | |
1809 | data->error = -EILSEQ; | |
1810 | } else { | |
1811 | data->error = -EIO; | |
1812 | } | |
1813 | } | |
c06ad258 | 1814 | |
f5177547 LD |
1815 | atmci_request_end(host, host->mrq); |
1816 | state = STATE_IDLE; | |
c06ad258 HS |
1817 | break; |
1818 | } | |
1819 | } while (state != prev_state); | |
1820 | ||
1821 | host->state = state; | |
965ebf33 | 1822 | |
965ebf33 | 1823 | spin_unlock(&host->lock); |
7d2be074 HS |
1824 | } |
1825 | ||
1826 | static void atmci_read_data_pio(struct atmel_mci *host) | |
1827 | { | |
1828 | struct scatterlist *sg = host->sg; | |
1829 | void *buf = sg_virt(sg); | |
1830 | unsigned int offset = host->pio_offset; | |
1831 | struct mmc_data *data = host->data; | |
1832 | u32 value; | |
1833 | u32 status; | |
1834 | unsigned int nbytes = 0; | |
1835 | ||
1836 | do { | |
03fc9a7f | 1837 | value = atmci_readl(host, ATMCI_RDR); |
7d2be074 HS |
1838 | if (likely(offset + 4 <= sg->length)) { |
1839 | put_unaligned(value, (u32 *)(buf + offset)); | |
1840 | ||
1841 | offset += 4; | |
1842 | nbytes += 4; | |
1843 | ||
1844 | if (offset == sg->length) { | |
5e7184ae | 1845 | flush_dcache_page(sg_page(sg)); |
7d2be074 | 1846 | host->sg = sg = sg_next(sg); |
bdbc5d0c TB |
1847 | host->sg_len--; |
1848 | if (!sg || !host->sg_len) | |
7d2be074 HS |
1849 | goto done; |
1850 | ||
1851 | offset = 0; | |
1852 | buf = sg_virt(sg); | |
1853 | } | |
1854 | } else { | |
1855 | unsigned int remaining = sg->length - offset; | |
1856 | memcpy(buf + offset, &value, remaining); | |
1857 | nbytes += remaining; | |
1858 | ||
1859 | flush_dcache_page(sg_page(sg)); | |
1860 | host->sg = sg = sg_next(sg); | |
bdbc5d0c TB |
1861 | host->sg_len--; |
1862 | if (!sg || !host->sg_len) | |
7d2be074 HS |
1863 | goto done; |
1864 | ||
1865 | offset = 4 - remaining; | |
1866 | buf = sg_virt(sg); | |
1867 | memcpy(buf, (u8 *)&value + remaining, offset); | |
1868 | nbytes += offset; | |
1869 | } | |
1870 | ||
03fc9a7f | 1871 | status = atmci_readl(host, ATMCI_SR); |
7d2be074 | 1872 | if (status & ATMCI_DATA_ERROR_FLAGS) { |
03fc9a7f | 1873 | atmci_writel(host, ATMCI_IDR, (ATMCI_NOTBUSY | ATMCI_RXRDY |
7d2be074 HS |
1874 | | ATMCI_DATA_ERROR_FLAGS)); |
1875 | host->data_status = status; | |
965ebf33 | 1876 | data->bytes_xfered += nbytes; |
965ebf33 | 1877 | return; |
7d2be074 | 1878 | } |
2c96a293 | 1879 | } while (status & ATMCI_RXRDY); |
7d2be074 HS |
1880 | |
1881 | host->pio_offset = offset; | |
1882 | data->bytes_xfered += nbytes; | |
1883 | ||
1884 | return; | |
1885 | ||
1886 | done: | |
03fc9a7f LD |
1887 | atmci_writel(host, ATMCI_IDR, ATMCI_RXRDY); |
1888 | atmci_writel(host, ATMCI_IER, ATMCI_NOTBUSY); | |
7d2be074 | 1889 | data->bytes_xfered += nbytes; |
965ebf33 | 1890 | smp_wmb(); |
c06ad258 | 1891 | atmci_set_pending(host, EVENT_XFER_COMPLETE); |
7d2be074 HS |
1892 | } |
1893 | ||
1894 | static void atmci_write_data_pio(struct atmel_mci *host) | |
1895 | { | |
1896 | struct scatterlist *sg = host->sg; | |
1897 | void *buf = sg_virt(sg); | |
1898 | unsigned int offset = host->pio_offset; | |
1899 | struct mmc_data *data = host->data; | |
1900 | u32 value; | |
1901 | u32 status; | |
1902 | unsigned int nbytes = 0; | |
1903 | ||
1904 | do { | |
1905 | if (likely(offset + 4 <= sg->length)) { | |
1906 | value = get_unaligned((u32 *)(buf + offset)); | |
03fc9a7f | 1907 | atmci_writel(host, ATMCI_TDR, value); |
7d2be074 HS |
1908 | |
1909 | offset += 4; | |
1910 | nbytes += 4; | |
1911 | if (offset == sg->length) { | |
1912 | host->sg = sg = sg_next(sg); | |
bdbc5d0c TB |
1913 | host->sg_len--; |
1914 | if (!sg || !host->sg_len) | |
7d2be074 HS |
1915 | goto done; |
1916 | ||
1917 | offset = 0; | |
1918 | buf = sg_virt(sg); | |
1919 | } | |
1920 | } else { | |
1921 | unsigned int remaining = sg->length - offset; | |
1922 | ||
1923 | value = 0; | |
1924 | memcpy(&value, buf + offset, remaining); | |
1925 | nbytes += remaining; | |
1926 | ||
1927 | host->sg = sg = sg_next(sg); | |
bdbc5d0c TB |
1928 | host->sg_len--; |
1929 | if (!sg || !host->sg_len) { | |
03fc9a7f | 1930 | atmci_writel(host, ATMCI_TDR, value); |
7d2be074 HS |
1931 | goto done; |
1932 | } | |
1933 | ||
1934 | offset = 4 - remaining; | |
1935 | buf = sg_virt(sg); | |
1936 | memcpy((u8 *)&value + remaining, buf, offset); | |
03fc9a7f | 1937 | atmci_writel(host, ATMCI_TDR, value); |
7d2be074 HS |
1938 | nbytes += offset; |
1939 | } | |
1940 | ||
03fc9a7f | 1941 | status = atmci_readl(host, ATMCI_SR); |
7d2be074 | 1942 | if (status & ATMCI_DATA_ERROR_FLAGS) { |
03fc9a7f | 1943 | atmci_writel(host, ATMCI_IDR, (ATMCI_NOTBUSY | ATMCI_TXRDY |
7d2be074 HS |
1944 | | ATMCI_DATA_ERROR_FLAGS)); |
1945 | host->data_status = status; | |
965ebf33 | 1946 | data->bytes_xfered += nbytes; |
965ebf33 | 1947 | return; |
7d2be074 | 1948 | } |
2c96a293 | 1949 | } while (status & ATMCI_TXRDY); |
7d2be074 HS |
1950 | |
1951 | host->pio_offset = offset; | |
1952 | data->bytes_xfered += nbytes; | |
1953 | ||
1954 | return; | |
1955 | ||
1956 | done: | |
03fc9a7f LD |
1957 | atmci_writel(host, ATMCI_IDR, ATMCI_TXRDY); |
1958 | atmci_writel(host, ATMCI_IER, ATMCI_NOTBUSY); | |
7d2be074 | 1959 | data->bytes_xfered += nbytes; |
965ebf33 | 1960 | smp_wmb(); |
c06ad258 | 1961 | atmci_set_pending(host, EVENT_XFER_COMPLETE); |
7d2be074 HS |
1962 | } |
1963 | ||
88ff82ed AG |
1964 | static void atmci_sdio_interrupt(struct atmel_mci *host, u32 status) |
1965 | { | |
1966 | int i; | |
1967 | ||
2c96a293 | 1968 | for (i = 0; i < ATMCI_MAX_NR_SLOTS; i++) { |
88ff82ed AG |
1969 | struct atmel_mci_slot *slot = host->slot[i]; |
1970 | if (slot && (status & slot->sdio_irq)) { | |
1971 | mmc_signal_sdio_irq(slot->mmc); | |
1972 | } | |
1973 | } | |
1974 | } | |
1975 | ||
1976 | ||
7d2be074 HS |
1977 | static irqreturn_t atmci_interrupt(int irq, void *dev_id) |
1978 | { | |
965ebf33 | 1979 | struct atmel_mci *host = dev_id; |
7d2be074 HS |
1980 | u32 status, mask, pending; |
1981 | unsigned int pass_count = 0; | |
1982 | ||
7d2be074 | 1983 | do { |
03fc9a7f LD |
1984 | status = atmci_readl(host, ATMCI_SR); |
1985 | mask = atmci_readl(host, ATMCI_IMR); | |
7d2be074 HS |
1986 | pending = status & mask; |
1987 | if (!pending) | |
1988 | break; | |
1989 | ||
1990 | if (pending & ATMCI_DATA_ERROR_FLAGS) { | |
6801c41a | 1991 | dev_dbg(&host->pdev->dev, "IRQ: data error\n"); |
03fc9a7f | 1992 | atmci_writel(host, ATMCI_IDR, ATMCI_DATA_ERROR_FLAGS |
f5177547 LD |
1993 | | ATMCI_RXRDY | ATMCI_TXRDY |
1994 | | ATMCI_ENDRX | ATMCI_ENDTX | |
1995 | | ATMCI_RXBUFF | ATMCI_TXBUFE); | |
965ebf33 | 1996 | |
7d2be074 | 1997 | host->data_status = status; |
6801c41a | 1998 | dev_dbg(&host->pdev->dev, "set pending data error\n"); |
965ebf33 | 1999 | smp_wmb(); |
7d2be074 HS |
2000 | atmci_set_pending(host, EVENT_DATA_ERROR); |
2001 | tasklet_schedule(&host->tasklet); | |
2002 | } | |
796211b7 | 2003 | |
796211b7 | 2004 | if (pending & ATMCI_TXBUFE) { |
6801c41a | 2005 | dev_dbg(&host->pdev->dev, "IRQ: tx buffer empty\n"); |
796211b7 | 2006 | atmci_writel(host, ATMCI_IDR, ATMCI_TXBUFE); |
7e8ba228 | 2007 | atmci_writel(host, ATMCI_IDR, ATMCI_ENDTX); |
796211b7 LD |
2008 | /* |
2009 | * We can receive this interruption before having configured | |
2010 | * the second pdc buffer, so we need to reconfigure first and | |
2011 | * second buffers again | |
2012 | */ | |
2013 | if (host->data_size) { | |
2014 | atmci_pdc_set_both_buf(host, XFER_TRANSMIT); | |
7e8ba228 | 2015 | atmci_writel(host, ATMCI_IER, ATMCI_ENDTX); |
796211b7 LD |
2016 | atmci_writel(host, ATMCI_IER, ATMCI_TXBUFE); |
2017 | } else { | |
2018 | atmci_pdc_complete(host); | |
2019 | } | |
7e8ba228 | 2020 | } else if (pending & ATMCI_ENDTX) { |
6801c41a | 2021 | dev_dbg(&host->pdev->dev, "IRQ: end of tx buffer\n"); |
7e8ba228 | 2022 | atmci_writel(host, ATMCI_IDR, ATMCI_ENDTX); |
796211b7 LD |
2023 | |
2024 | if (host->data_size) { | |
2025 | atmci_pdc_set_single_buf(host, | |
7e8ba228 LD |
2026 | XFER_TRANSMIT, PDC_SECOND_BUF); |
2027 | atmci_writel(host, ATMCI_IER, ATMCI_ENDTX); | |
796211b7 LD |
2028 | } |
2029 | } | |
2030 | ||
2031 | if (pending & ATMCI_RXBUFF) { | |
6801c41a | 2032 | dev_dbg(&host->pdev->dev, "IRQ: rx buffer full\n"); |
796211b7 | 2033 | atmci_writel(host, ATMCI_IDR, ATMCI_RXBUFF); |
7e8ba228 | 2034 | atmci_writel(host, ATMCI_IDR, ATMCI_ENDRX); |
796211b7 LD |
2035 | /* |
2036 | * We can receive this interruption before having configured | |
2037 | * the second pdc buffer, so we need to reconfigure first and | |
2038 | * second buffers again | |
2039 | */ | |
2040 | if (host->data_size) { | |
2041 | atmci_pdc_set_both_buf(host, XFER_RECEIVE); | |
7e8ba228 | 2042 | atmci_writel(host, ATMCI_IER, ATMCI_ENDRX); |
796211b7 LD |
2043 | atmci_writel(host, ATMCI_IER, ATMCI_RXBUFF); |
2044 | } else { | |
2045 | atmci_pdc_complete(host); | |
2046 | } | |
7e8ba228 | 2047 | } else if (pending & ATMCI_ENDRX) { |
6801c41a | 2048 | dev_dbg(&host->pdev->dev, "IRQ: end of rx buffer\n"); |
7e8ba228 LD |
2049 | atmci_writel(host, ATMCI_IDR, ATMCI_ENDRX); |
2050 | ||
2051 | if (host->data_size) { | |
2052 | atmci_pdc_set_single_buf(host, | |
2053 | XFER_RECEIVE, PDC_SECOND_BUF); | |
2054 | atmci_writel(host, ATMCI_IER, ATMCI_ENDRX); | |
2055 | } | |
796211b7 LD |
2056 | } |
2057 | ||
f5177547 LD |
2058 | /* |
2059 | * First mci IPs, so mainly the ones having pdc, have some | |
2060 | * issues with the notbusy signal. You can't get it after | |
2061 | * data transmission if you have not sent a stop command. | |
2062 | * The appropriate workaround is to use the BLKE signal. | |
2063 | */ | |
2064 | if (pending & ATMCI_BLKE) { | |
6801c41a | 2065 | dev_dbg(&host->pdev->dev, "IRQ: blke\n"); |
f5177547 LD |
2066 | atmci_writel(host, ATMCI_IDR, ATMCI_BLKE); |
2067 | smp_wmb(); | |
6801c41a | 2068 | dev_dbg(&host->pdev->dev, "set pending notbusy\n"); |
f5177547 LD |
2069 | atmci_set_pending(host, EVENT_NOTBUSY); |
2070 | tasklet_schedule(&host->tasklet); | |
2071 | } | |
7e8ba228 | 2072 | |
2c96a293 | 2073 | if (pending & ATMCI_NOTBUSY) { |
6801c41a | 2074 | dev_dbg(&host->pdev->dev, "IRQ: not_busy\n"); |
f5177547 | 2075 | atmci_writel(host, ATMCI_IDR, ATMCI_NOTBUSY); |
965ebf33 | 2076 | smp_wmb(); |
6801c41a | 2077 | dev_dbg(&host->pdev->dev, "set pending notbusy\n"); |
f5177547 | 2078 | atmci_set_pending(host, EVENT_NOTBUSY); |
7d2be074 HS |
2079 | tasklet_schedule(&host->tasklet); |
2080 | } | |
f5177547 | 2081 | |
2c96a293 | 2082 | if (pending & ATMCI_RXRDY) |
7d2be074 | 2083 | atmci_read_data_pio(host); |
2c96a293 | 2084 | if (pending & ATMCI_TXRDY) |
7d2be074 HS |
2085 | atmci_write_data_pio(host); |
2086 | ||
f5177547 | 2087 | if (pending & ATMCI_CMDRDY) { |
6801c41a | 2088 | dev_dbg(&host->pdev->dev, "IRQ: cmd ready\n"); |
f5177547 LD |
2089 | atmci_writel(host, ATMCI_IDR, ATMCI_CMDRDY); |
2090 | host->cmd_status = status; | |
2091 | smp_wmb(); | |
6801c41a | 2092 | dev_dbg(&host->pdev->dev, "set pending cmd rdy\n"); |
f5177547 LD |
2093 | atmci_set_pending(host, EVENT_CMD_RDY); |
2094 | tasklet_schedule(&host->tasklet); | |
2095 | } | |
88ff82ed | 2096 | |
2c96a293 | 2097 | if (pending & (ATMCI_SDIOIRQA | ATMCI_SDIOIRQB)) |
88ff82ed AG |
2098 | atmci_sdio_interrupt(host, status); |
2099 | ||
7d2be074 HS |
2100 | } while (pass_count++ < 5); |
2101 | ||
7d2be074 HS |
2102 | return pass_count ? IRQ_HANDLED : IRQ_NONE; |
2103 | } | |
2104 | ||
2105 | static irqreturn_t atmci_detect_interrupt(int irq, void *dev_id) | |
2106 | { | |
965ebf33 | 2107 | struct atmel_mci_slot *slot = dev_id; |
7d2be074 HS |
2108 | |
2109 | /* | |
2110 | * Disable interrupts until the pin has stabilized and check | |
2111 | * the state then. Use mod_timer() since we may be in the | |
2112 | * middle of the timer routine when this interrupt triggers. | |
2113 | */ | |
2114 | disable_irq_nosync(irq); | |
965ebf33 | 2115 | mod_timer(&slot->detect_timer, jiffies + msecs_to_jiffies(20)); |
7d2be074 HS |
2116 | |
2117 | return IRQ_HANDLED; | |
2118 | } | |
2119 | ||
965ebf33 HS |
2120 | static int __init atmci_init_slot(struct atmel_mci *host, |
2121 | struct mci_slot_pdata *slot_data, unsigned int id, | |
88ff82ed | 2122 | u32 sdc_reg, u32 sdio_irq) |
965ebf33 HS |
2123 | { |
2124 | struct mmc_host *mmc; | |
2125 | struct atmel_mci_slot *slot; | |
2126 | ||
2127 | mmc = mmc_alloc_host(sizeof(struct atmel_mci_slot), &host->pdev->dev); | |
2128 | if (!mmc) | |
2129 | return -ENOMEM; | |
2130 | ||
2131 | slot = mmc_priv(mmc); | |
2132 | slot->mmc = mmc; | |
2133 | slot->host = host; | |
2134 | slot->detect_pin = slot_data->detect_pin; | |
2135 | slot->wp_pin = slot_data->wp_pin; | |
1c1452be | 2136 | slot->detect_is_active_high = slot_data->detect_is_active_high; |
965ebf33 | 2137 | slot->sdc_reg = sdc_reg; |
88ff82ed | 2138 | slot->sdio_irq = sdio_irq; |
965ebf33 | 2139 | |
e919fd20 LD |
2140 | dev_dbg(&mmc->class_dev, |
2141 | "slot[%u]: bus_width=%u, detect_pin=%d, " | |
2142 | "detect_is_active_high=%s, wp_pin=%d\n", | |
2143 | id, slot_data->bus_width, slot_data->detect_pin, | |
2144 | slot_data->detect_is_active_high ? "true" : "false", | |
2145 | slot_data->wp_pin); | |
2146 | ||
965ebf33 HS |
2147 | mmc->ops = &atmci_ops; |
2148 | mmc->f_min = DIV_ROUND_UP(host->bus_hz, 512); | |
2149 | mmc->f_max = host->bus_hz / 2; | |
2150 | mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34; | |
88ff82ed AG |
2151 | if (sdio_irq) |
2152 | mmc->caps |= MMC_CAP_SDIO_IRQ; | |
796211b7 | 2153 | if (host->caps.has_highspeed) |
99ddffd8 | 2154 | mmc->caps |= MMC_CAP_SD_HIGHSPEED; |
7a90dcc2 LD |
2155 | /* |
2156 | * Without the read/write proof capability, it is strongly suggested to | |
2157 | * use only one bit for data to prevent fifo underruns and overruns | |
2158 | * which will corrupt data. | |
2159 | */ | |
2160 | if ((slot_data->bus_width >= 4) && host->caps.has_rwproof) | |
965ebf33 HS |
2161 | mmc->caps |= MMC_CAP_4_BIT_DATA; |
2162 | ||
7a90dcc2 LD |
2163 | if (atmci_get_version(host) < 0x200) { |
2164 | mmc->max_segs = 256; | |
2165 | mmc->max_blk_size = 4095; | |
2166 | mmc->max_blk_count = 256; | |
2167 | mmc->max_req_size = mmc->max_blk_size * mmc->max_blk_count; | |
2168 | mmc->max_seg_size = mmc->max_blk_size * mmc->max_segs; | |
2169 | } else { | |
2170 | mmc->max_segs = 64; | |
2171 | mmc->max_req_size = 32768 * 512; | |
2172 | mmc->max_blk_size = 32768; | |
2173 | mmc->max_blk_count = 512; | |
2174 | } | |
965ebf33 HS |
2175 | |
2176 | /* Assume card is present initially */ | |
2177 | set_bit(ATMCI_CARD_PRESENT, &slot->flags); | |
2178 | if (gpio_is_valid(slot->detect_pin)) { | |
2179 | if (gpio_request(slot->detect_pin, "mmc_detect")) { | |
2180 | dev_dbg(&mmc->class_dev, "no detect pin available\n"); | |
2181 | slot->detect_pin = -EBUSY; | |
1c1452be JL |
2182 | } else if (gpio_get_value(slot->detect_pin) ^ |
2183 | slot->detect_is_active_high) { | |
965ebf33 HS |
2184 | clear_bit(ATMCI_CARD_PRESENT, &slot->flags); |
2185 | } | |
2186 | } | |
2187 | ||
2188 | if (!gpio_is_valid(slot->detect_pin)) | |
2189 | mmc->caps |= MMC_CAP_NEEDS_POLL; | |
2190 | ||
2191 | if (gpio_is_valid(slot->wp_pin)) { | |
2192 | if (gpio_request(slot->wp_pin, "mmc_wp")) { | |
2193 | dev_dbg(&mmc->class_dev, "no WP pin available\n"); | |
2194 | slot->wp_pin = -EBUSY; | |
2195 | } | |
2196 | } | |
2197 | ||
2198 | host->slot[id] = slot; | |
2199 | mmc_add_host(mmc); | |
2200 | ||
2201 | if (gpio_is_valid(slot->detect_pin)) { | |
2202 | int ret; | |
2203 | ||
2204 | setup_timer(&slot->detect_timer, atmci_detect_change, | |
2205 | (unsigned long)slot); | |
2206 | ||
2207 | ret = request_irq(gpio_to_irq(slot->detect_pin), | |
2208 | atmci_detect_interrupt, | |
2209 | IRQF_TRIGGER_FALLING | IRQF_TRIGGER_RISING, | |
2210 | "mmc-detect", slot); | |
2211 | if (ret) { | |
2212 | dev_dbg(&mmc->class_dev, | |
2213 | "could not request IRQ %d for detect pin\n", | |
2214 | gpio_to_irq(slot->detect_pin)); | |
2215 | gpio_free(slot->detect_pin); | |
2216 | slot->detect_pin = -EBUSY; | |
2217 | } | |
2218 | } | |
2219 | ||
2220 | atmci_init_debugfs(slot); | |
2221 | ||
2222 | return 0; | |
2223 | } | |
2224 | ||
2225 | static void __exit atmci_cleanup_slot(struct atmel_mci_slot *slot, | |
2226 | unsigned int id) | |
2227 | { | |
2228 | /* Debugfs stuff is cleaned up by mmc core */ | |
2229 | ||
2230 | set_bit(ATMCI_SHUTDOWN, &slot->flags); | |
2231 | smp_wmb(); | |
2232 | ||
2233 | mmc_remove_host(slot->mmc); | |
2234 | ||
2235 | if (gpio_is_valid(slot->detect_pin)) { | |
2236 | int pin = slot->detect_pin; | |
2237 | ||
2238 | free_irq(gpio_to_irq(pin), slot); | |
2239 | del_timer_sync(&slot->detect_timer); | |
2240 | gpio_free(pin); | |
2241 | } | |
2242 | if (gpio_is_valid(slot->wp_pin)) | |
2243 | gpio_free(slot->wp_pin); | |
2244 | ||
2245 | slot->host->slot[id] = NULL; | |
2246 | mmc_free_host(slot->mmc); | |
2247 | } | |
2248 | ||
8c964df0 | 2249 | static bool atmci_filter(struct dma_chan *chan, void *pdata) |
74465b4f | 2250 | { |
8c964df0 LD |
2251 | struct mci_platform_data *sl_pdata = pdata; |
2252 | struct mci_dma_data *sl; | |
74465b4f | 2253 | |
8c964df0 LD |
2254 | if (!sl_pdata) |
2255 | return false; | |
2256 | ||
2257 | sl = sl_pdata->dma_slave; | |
2635d1ba NF |
2258 | if (sl && find_slave_dev(sl) == chan->device->dev) { |
2259 | chan->private = slave_data_ptr(sl); | |
7dd60251 | 2260 | return true; |
2635d1ba | 2261 | } else { |
7dd60251 | 2262 | return false; |
2635d1ba | 2263 | } |
74465b4f | 2264 | } |
2635d1ba | 2265 | |
ef878198 | 2266 | static bool atmci_configure_dma(struct atmel_mci *host) |
2635d1ba NF |
2267 | { |
2268 | struct mci_platform_data *pdata; | |
8c964df0 | 2269 | dma_cap_mask_t mask; |
2635d1ba NF |
2270 | |
2271 | if (host == NULL) | |
ef878198 | 2272 | return false; |
2635d1ba NF |
2273 | |
2274 | pdata = host->pdev->dev.platform_data; | |
2275 | ||
8c964df0 LD |
2276 | dma_cap_zero(mask); |
2277 | dma_cap_set(DMA_SLAVE, mask); | |
ccdfe612 | 2278 | |
8c964df0 LD |
2279 | host->dma.chan = dma_request_slave_channel_compat(mask, atmci_filter, pdata, |
2280 | &host->pdev->dev, "rxtx"); | |
ef878198 LD |
2281 | if (!host->dma.chan) { |
2282 | dev_warn(&host->pdev->dev, "no DMA channel available\n"); | |
2283 | return false; | |
2284 | } else { | |
74791a2d | 2285 | dev_info(&host->pdev->dev, |
b81cfc41 | 2286 | "using %s for DMA transfers\n", |
74791a2d | 2287 | dma_chan_name(host->dma.chan)); |
e2b35f3d VK |
2288 | |
2289 | host->dma_conf.src_addr = host->mapbase + ATMCI_RDR; | |
2290 | host->dma_conf.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; | |
2291 | host->dma_conf.src_maxburst = 1; | |
2292 | host->dma_conf.dst_addr = host->mapbase + ATMCI_TDR; | |
2293 | host->dma_conf.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; | |
2294 | host->dma_conf.dst_maxburst = 1; | |
2295 | host->dma_conf.device_fc = false; | |
ef878198 LD |
2296 | return true; |
2297 | } | |
2635d1ba | 2298 | } |
796211b7 | 2299 | |
796211b7 LD |
2300 | /* |
2301 | * HSMCI (High Speed MCI) module is not fully compatible with MCI module. | |
2302 | * HSMCI provides DMA support and a new config register but no more supports | |
2303 | * PDC. | |
2304 | */ | |
2305 | static void __init atmci_get_cap(struct atmel_mci *host) | |
2306 | { | |
2307 | unsigned int version; | |
2308 | ||
2309 | version = atmci_get_version(host); | |
2310 | dev_info(&host->pdev->dev, | |
2311 | "version: 0x%x\n", version); | |
2312 | ||
ccdfe612 | 2313 | host->caps.has_dma_conf_reg = 0; |
6bf2af8c | 2314 | host->caps.has_pdc = ATMCI_PDC_CONNECTED; |
796211b7 LD |
2315 | host->caps.has_cfg_reg = 0; |
2316 | host->caps.has_cstor_reg = 0; | |
2317 | host->caps.has_highspeed = 0; | |
2318 | host->caps.has_rwproof = 0; | |
faf8180b | 2319 | host->caps.has_odd_clk_div = 0; |
24011f34 LD |
2320 | host->caps.has_bad_data_ordering = 1; |
2321 | host->caps.need_reset_after_xfer = 1; | |
2322 | host->caps.need_blksz_mul_4 = 1; | |
077d4073 | 2323 | host->caps.need_notbusy_for_read_ops = 0; |
796211b7 LD |
2324 | |
2325 | /* keep only major version number */ | |
2326 | switch (version & 0xf00) { | |
796211b7 | 2327 | case 0x500: |
faf8180b LD |
2328 | host->caps.has_odd_clk_div = 1; |
2329 | case 0x400: | |
2330 | case 0x300: | |
ccdfe612 | 2331 | host->caps.has_dma_conf_reg = 1; |
faf8180b | 2332 | host->caps.has_pdc = 0; |
796211b7 LD |
2333 | host->caps.has_cfg_reg = 1; |
2334 | host->caps.has_cstor_reg = 1; | |
2335 | host->caps.has_highspeed = 1; | |
faf8180b | 2336 | case 0x200: |
796211b7 | 2337 | host->caps.has_rwproof = 1; |
24011f34 | 2338 | host->caps.need_blksz_mul_4 = 0; |
077d4073 | 2339 | host->caps.need_notbusy_for_read_ops = 1; |
faf8180b | 2340 | case 0x100: |
24011f34 LD |
2341 | host->caps.has_bad_data_ordering = 0; |
2342 | host->caps.need_reset_after_xfer = 0; | |
2343 | case 0x0: | |
796211b7 LD |
2344 | break; |
2345 | default: | |
faf8180b | 2346 | host->caps.has_pdc = 0; |
796211b7 LD |
2347 | dev_warn(&host->pdev->dev, |
2348 | "Unmanaged mci version, set minimum capabilities\n"); | |
2349 | break; | |
2350 | } | |
2351 | } | |
74465b4f | 2352 | |
7d2be074 HS |
2353 | static int __init atmci_probe(struct platform_device *pdev) |
2354 | { | |
2355 | struct mci_platform_data *pdata; | |
965ebf33 HS |
2356 | struct atmel_mci *host; |
2357 | struct resource *regs; | |
2358 | unsigned int nr_slots; | |
2359 | int irq; | |
2360 | int ret; | |
7d2be074 HS |
2361 | |
2362 | regs = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
2363 | if (!regs) | |
2364 | return -ENXIO; | |
2365 | pdata = pdev->dev.platform_data; | |
e919fd20 LD |
2366 | if (!pdata) { |
2367 | pdata = atmci_of_init(pdev); | |
2368 | if (IS_ERR(pdata)) { | |
2369 | dev_err(&pdev->dev, "platform data not available\n"); | |
2370 | return PTR_ERR(pdata); | |
2371 | } | |
2372 | } | |
2373 | ||
7d2be074 HS |
2374 | irq = platform_get_irq(pdev, 0); |
2375 | if (irq < 0) | |
2376 | return irq; | |
2377 | ||
965ebf33 HS |
2378 | host = kzalloc(sizeof(struct atmel_mci), GFP_KERNEL); |
2379 | if (!host) | |
7d2be074 HS |
2380 | return -ENOMEM; |
2381 | ||
7d2be074 | 2382 | host->pdev = pdev; |
965ebf33 HS |
2383 | spin_lock_init(&host->lock); |
2384 | INIT_LIST_HEAD(&host->queue); | |
7d2be074 HS |
2385 | |
2386 | host->mck = clk_get(&pdev->dev, "mci_clk"); | |
2387 | if (IS_ERR(host->mck)) { | |
2388 | ret = PTR_ERR(host->mck); | |
2389 | goto err_clk_get; | |
2390 | } | |
2391 | ||
2392 | ret = -ENOMEM; | |
e8e3f6ca | 2393 | host->regs = ioremap(regs->start, resource_size(regs)); |
7d2be074 HS |
2394 | if (!host->regs) |
2395 | goto err_ioremap; | |
2396 | ||
b3894f26 BB |
2397 | ret = clk_prepare_enable(host->mck); |
2398 | if (ret) | |
2399 | goto err_request_irq; | |
03fc9a7f | 2400 | atmci_writel(host, ATMCI_CR, ATMCI_CR_SWRST); |
7d2be074 | 2401 | host->bus_hz = clk_get_rate(host->mck); |
b3894f26 | 2402 | clk_disable_unprepare(host->mck); |
7d2be074 HS |
2403 | |
2404 | host->mapbase = regs->start; | |
2405 | ||
965ebf33 | 2406 | tasklet_init(&host->tasklet, atmci_tasklet_func, (unsigned long)host); |
7d2be074 | 2407 | |
89c8aa20 | 2408 | ret = request_irq(irq, atmci_interrupt, 0, dev_name(&pdev->dev), host); |
7d2be074 HS |
2409 | if (ret) |
2410 | goto err_request_irq; | |
2411 | ||
796211b7 LD |
2412 | /* Get MCI capabilities and set operations according to it */ |
2413 | atmci_get_cap(host); | |
ccdfe612 | 2414 | if (atmci_configure_dma(host)) { |
796211b7 LD |
2415 | host->prepare_data = &atmci_prepare_data_dma; |
2416 | host->submit_data = &atmci_submit_data_dma; | |
2417 | host->stop_transfer = &atmci_stop_transfer_dma; | |
2418 | } else if (host->caps.has_pdc) { | |
2419 | dev_info(&pdev->dev, "using PDC\n"); | |
2420 | host->prepare_data = &atmci_prepare_data_pdc; | |
2421 | host->submit_data = &atmci_submit_data_pdc; | |
2422 | host->stop_transfer = &atmci_stop_transfer_pdc; | |
2423 | } else { | |
ef878198 | 2424 | dev_info(&pdev->dev, "using PIO\n"); |
796211b7 LD |
2425 | host->prepare_data = &atmci_prepare_data; |
2426 | host->submit_data = &atmci_submit_data; | |
2427 | host->stop_transfer = &atmci_stop_transfer; | |
2428 | } | |
2429 | ||
7d2be074 HS |
2430 | platform_set_drvdata(pdev, host); |
2431 | ||
b87cc1b5 LD |
2432 | setup_timer(&host->timer, atmci_timeout_timer, (unsigned long)host); |
2433 | ||
965ebf33 HS |
2434 | /* We need at least one slot to succeed */ |
2435 | nr_slots = 0; | |
2436 | ret = -ENODEV; | |
2437 | if (pdata->slot[0].bus_width) { | |
2438 | ret = atmci_init_slot(host, &pdata->slot[0], | |
2c96a293 | 2439 | 0, ATMCI_SDCSEL_SLOT_A, ATMCI_SDIOIRQA); |
7a90dcc2 | 2440 | if (!ret) { |
965ebf33 | 2441 | nr_slots++; |
7a90dcc2 LD |
2442 | host->buf_size = host->slot[0]->mmc->max_req_size; |
2443 | } | |
965ebf33 HS |
2444 | } |
2445 | if (pdata->slot[1].bus_width) { | |
2446 | ret = atmci_init_slot(host, &pdata->slot[1], | |
2c96a293 | 2447 | 1, ATMCI_SDCSEL_SLOT_B, ATMCI_SDIOIRQB); |
7a90dcc2 | 2448 | if (!ret) { |
965ebf33 | 2449 | nr_slots++; |
7a90dcc2 LD |
2450 | if (host->slot[1]->mmc->max_req_size > host->buf_size) |
2451 | host->buf_size = | |
2452 | host->slot[1]->mmc->max_req_size; | |
2453 | } | |
7d2be074 HS |
2454 | } |
2455 | ||
04d699c3 RE |
2456 | if (!nr_slots) { |
2457 | dev_err(&pdev->dev, "init failed: no slot defined\n"); | |
965ebf33 | 2458 | goto err_init_slot; |
04d699c3 | 2459 | } |
7d2be074 | 2460 | |
7a90dcc2 LD |
2461 | if (!host->caps.has_rwproof) { |
2462 | host->buffer = dma_alloc_coherent(&pdev->dev, host->buf_size, | |
2463 | &host->buf_phys_addr, | |
2464 | GFP_KERNEL); | |
2465 | if (!host->buffer) { | |
2466 | ret = -ENOMEM; | |
2467 | dev_err(&pdev->dev, "buffer allocation failed\n"); | |
2468 | goto err_init_slot; | |
2469 | } | |
2470 | } | |
2471 | ||
965ebf33 HS |
2472 | dev_info(&pdev->dev, |
2473 | "Atmel MCI controller at 0x%08lx irq %d, %u slots\n", | |
2474 | host->mapbase, irq, nr_slots); | |
deec9ae3 | 2475 | |
7d2be074 HS |
2476 | return 0; |
2477 | ||
965ebf33 | 2478 | err_init_slot: |
74465b4f DW |
2479 | if (host->dma.chan) |
2480 | dma_release_channel(host->dma.chan); | |
965ebf33 | 2481 | free_irq(irq, host); |
7d2be074 HS |
2482 | err_request_irq: |
2483 | iounmap(host->regs); | |
2484 | err_ioremap: | |
2485 | clk_put(host->mck); | |
2486 | err_clk_get: | |
965ebf33 | 2487 | kfree(host); |
7d2be074 HS |
2488 | return ret; |
2489 | } | |
2490 | ||
2491 | static int __exit atmci_remove(struct platform_device *pdev) | |
2492 | { | |
965ebf33 HS |
2493 | struct atmel_mci *host = platform_get_drvdata(pdev); |
2494 | unsigned int i; | |
7d2be074 | 2495 | |
7a90dcc2 LD |
2496 | if (host->buffer) |
2497 | dma_free_coherent(&pdev->dev, host->buf_size, | |
2498 | host->buffer, host->buf_phys_addr); | |
2499 | ||
2c96a293 | 2500 | for (i = 0; i < ATMCI_MAX_NR_SLOTS; i++) { |
965ebf33 HS |
2501 | if (host->slot[i]) |
2502 | atmci_cleanup_slot(host->slot[i], i); | |
2503 | } | |
7d2be074 | 2504 | |
b3894f26 | 2505 | clk_prepare_enable(host->mck); |
03fc9a7f LD |
2506 | atmci_writel(host, ATMCI_IDR, ~0UL); |
2507 | atmci_writel(host, ATMCI_CR, ATMCI_CR_MCIDIS); | |
2508 | atmci_readl(host, ATMCI_SR); | |
b3894f26 | 2509 | clk_disable_unprepare(host->mck); |
7d2be074 | 2510 | |
74465b4f DW |
2511 | if (host->dma.chan) |
2512 | dma_release_channel(host->dma.chan); | |
65e8b083 | 2513 | |
965ebf33 HS |
2514 | free_irq(platform_get_irq(pdev, 0), host); |
2515 | iounmap(host->regs); | |
7d2be074 | 2516 | |
965ebf33 HS |
2517 | clk_put(host->mck); |
2518 | kfree(host); | |
7d2be074 | 2519 | |
7d2be074 HS |
2520 | return 0; |
2521 | } | |
2522 | ||
5a942b6f | 2523 | #ifdef CONFIG_PM_SLEEP |
5c2f2b9b NF |
2524 | static int atmci_suspend(struct device *dev) |
2525 | { | |
2526 | struct atmel_mci *host = dev_get_drvdata(dev); | |
2527 | int i; | |
2528 | ||
2c96a293 | 2529 | for (i = 0; i < ATMCI_MAX_NR_SLOTS; i++) { |
5c2f2b9b NF |
2530 | struct atmel_mci_slot *slot = host->slot[i]; |
2531 | int ret; | |
2532 | ||
2533 | if (!slot) | |
2534 | continue; | |
2535 | ret = mmc_suspend_host(slot->mmc); | |
2536 | if (ret < 0) { | |
2537 | while (--i >= 0) { | |
2538 | slot = host->slot[i]; | |
2539 | if (slot | |
2540 | && test_bit(ATMCI_SUSPENDED, &slot->flags)) { | |
2541 | mmc_resume_host(host->slot[i]->mmc); | |
2542 | clear_bit(ATMCI_SUSPENDED, &slot->flags); | |
2543 | } | |
2544 | } | |
2545 | return ret; | |
2546 | } else { | |
2547 | set_bit(ATMCI_SUSPENDED, &slot->flags); | |
2548 | } | |
2549 | } | |
2550 | ||
2551 | return 0; | |
2552 | } | |
2553 | ||
2554 | static int atmci_resume(struct device *dev) | |
2555 | { | |
2556 | struct atmel_mci *host = dev_get_drvdata(dev); | |
2557 | int i; | |
2558 | int ret = 0; | |
2559 | ||
2c96a293 | 2560 | for (i = 0; i < ATMCI_MAX_NR_SLOTS; i++) { |
5c2f2b9b NF |
2561 | struct atmel_mci_slot *slot = host->slot[i]; |
2562 | int err; | |
2563 | ||
2564 | slot = host->slot[i]; | |
2565 | if (!slot) | |
2566 | continue; | |
2567 | if (!test_bit(ATMCI_SUSPENDED, &slot->flags)) | |
2568 | continue; | |
2569 | err = mmc_resume_host(slot->mmc); | |
2570 | if (err < 0) | |
2571 | ret = err; | |
2572 | else | |
2573 | clear_bit(ATMCI_SUSPENDED, &slot->flags); | |
2574 | } | |
2575 | ||
2576 | return ret; | |
2577 | } | |
5c2f2b9b NF |
2578 | #endif |
2579 | ||
5a942b6f JH |
2580 | static SIMPLE_DEV_PM_OPS(atmci_pm, atmci_suspend, atmci_resume); |
2581 | ||
7d2be074 HS |
2582 | static struct platform_driver atmci_driver = { |
2583 | .remove = __exit_p(atmci_remove), | |
2584 | .driver = { | |
2585 | .name = "atmel_mci", | |
5a942b6f | 2586 | .pm = &atmci_pm, |
e919fd20 | 2587 | .of_match_table = of_match_ptr(atmci_dt_ids), |
7d2be074 HS |
2588 | }, |
2589 | }; | |
2590 | ||
2591 | static int __init atmci_init(void) | |
2592 | { | |
2593 | return platform_driver_probe(&atmci_driver, atmci_probe); | |
2594 | } | |
2595 | ||
2596 | static void __exit atmci_exit(void) | |
2597 | { | |
2598 | platform_driver_unregister(&atmci_driver); | |
2599 | } | |
2600 | ||
74465b4f | 2601 | late_initcall(atmci_init); /* try to load after dma driver when built-in */ |
7d2be074 HS |
2602 | module_exit(atmci_exit); |
2603 | ||
2604 | MODULE_DESCRIPTION("Atmel Multimedia Card Interface driver"); | |
e05503ef | 2605 | MODULE_AUTHOR("Haavard Skinnemoen (Atmel)"); |
7d2be074 | 2606 | MODULE_LICENSE("GPL v2"); |