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15a0580c DB |
1 | /* |
2 | * mmc_spi.c - Access SD/MMC cards through SPI master controllers | |
3 | * | |
4 | * (C) Copyright 2005, Intec Automation, | |
5 | * Mike Lavender (mike@steroidmicros) | |
6 | * (C) Copyright 2006-2007, David Brownell | |
7 | * (C) Copyright 2007, Axis Communications, | |
8 | * Hans-Peter Nilsson (hp@axis.com) | |
9 | * (C) Copyright 2007, ATRON electronic GmbH, | |
10 | * Jan Nikitenko <jan.nikitenko@gmail.com> | |
11 | * | |
12 | * | |
13 | * This program is free software; you can redistribute it and/or modify | |
14 | * it under the terms of the GNU General Public License as published by | |
15 | * the Free Software Foundation; either version 2 of the License, or | |
16 | * (at your option) any later version. | |
17 | * | |
18 | * This program is distributed in the hope that it will be useful, | |
19 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
20 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
21 | * GNU General Public License for more details. | |
22 | * | |
23 | * You should have received a copy of the GNU General Public License | |
24 | * along with this program; if not, write to the Free Software | |
25 | * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. | |
26 | */ | |
56e303eb | 27 | #include <linux/sched.h> |
15a0580c | 28 | #include <linux/delay.h> |
23fd5045 | 29 | #include <linux/bio.h> |
15a0580c DB |
30 | #include <linux/dma-mapping.h> |
31 | #include <linux/crc7.h> | |
32 | #include <linux/crc-itu-t.h> | |
e5712a6a | 33 | #include <linux/scatterlist.h> |
15a0580c DB |
34 | |
35 | #include <linux/mmc/host.h> | |
36 | #include <linux/mmc/mmc.h> /* for R1_SPI_* bit values */ | |
37 | ||
38 | #include <linux/spi/spi.h> | |
39 | #include <linux/spi/mmc_spi.h> | |
40 | ||
41 | #include <asm/unaligned.h> | |
42 | ||
43 | ||
44 | /* NOTES: | |
45 | * | |
46 | * - For now, we won't try to interoperate with a real mmc/sd/sdio | |
47 | * controller, although some of them do have hardware support for | |
48 | * SPI protocol. The main reason for such configs would be mmc-ish | |
49 | * cards like DataFlash, which don't support that "native" protocol. | |
50 | * | |
51 | * We don't have a "DataFlash/MMC/SD/SDIO card slot" abstraction to | |
52 | * switch between driver stacks, and in any case if "native" mode | |
53 | * is available, it will be faster and hence preferable. | |
54 | * | |
55 | * - MMC depends on a different chipselect management policy than the | |
56 | * SPI interface currently supports for shared bus segments: it needs | |
57 | * to issue multiple spi_message requests with the chipselect active, | |
58 | * using the results of one message to decide the next one to issue. | |
59 | * | |
60 | * Pending updates to the programming interface, this driver expects | |
61 | * that it not share the bus with other drivers (precluding conflicts). | |
62 | * | |
63 | * - We tell the controller to keep the chipselect active from the | |
64 | * beginning of an mmc_host_ops.request until the end. So beware | |
65 | * of SPI controller drivers that mis-handle the cs_change flag! | |
66 | * | |
67 | * However, many cards seem OK with chipselect flapping up/down | |
68 | * during that time ... at least on unshared bus segments. | |
69 | */ | |
70 | ||
71 | ||
72 | /* | |
73 | * Local protocol constants, internal to data block protocols. | |
74 | */ | |
75 | ||
76 | /* Response tokens used to ack each block written: */ | |
77 | #define SPI_MMC_RESPONSE_CODE(x) ((x) & 0x1f) | |
78 | #define SPI_RESPONSE_ACCEPTED ((2 << 1)|1) | |
79 | #define SPI_RESPONSE_CRC_ERR ((5 << 1)|1) | |
80 | #define SPI_RESPONSE_WRITE_ERR ((6 << 1)|1) | |
81 | ||
82 | /* Read and write blocks start with these tokens and end with crc; | |
83 | * on error, read tokens act like a subset of R2_SPI_* values. | |
84 | */ | |
85 | #define SPI_TOKEN_SINGLE 0xfe /* single block r/w, multiblock read */ | |
86 | #define SPI_TOKEN_MULTI_WRITE 0xfc /* multiblock write */ | |
87 | #define SPI_TOKEN_STOP_TRAN 0xfd /* terminate multiblock write */ | |
88 | ||
89 | #define MMC_SPI_BLOCKSIZE 512 | |
90 | ||
91 | ||
92 | /* These fixed timeouts come from the latest SD specs, which say to ignore | |
93 | * the CSD values. The R1B value is for card erase (e.g. the "I forgot the | |
94 | * card's password" scenario); it's mostly applied to STOP_TRANSMISSION after | |
95 | * reads which takes nowhere near that long. Older cards may be able to use | |
96 | * shorter timeouts ... but why bother? | |
97 | */ | |
56e303eb | 98 | #define r1b_timeout (HZ * 3) |
15a0580c DB |
99 | |
100 | ||
101 | /****************************************************************************/ | |
102 | ||
103 | /* | |
104 | * Local Data Structures | |
105 | */ | |
106 | ||
107 | /* "scratch" is per-{command,block} data exchanged with the card */ | |
108 | struct scratch { | |
109 | u8 status[29]; | |
110 | u8 data_token; | |
111 | __be16 crc_val; | |
112 | }; | |
113 | ||
114 | struct mmc_spi_host { | |
115 | struct mmc_host *mmc; | |
116 | struct spi_device *spi; | |
117 | ||
118 | unsigned char power_mode; | |
119 | u16 powerup_msecs; | |
120 | ||
121 | struct mmc_spi_platform_data *pdata; | |
122 | ||
123 | /* for bulk data transfers */ | |
124 | struct spi_transfer token, t, crc, early_status; | |
125 | struct spi_message m; | |
126 | ||
127 | /* for status readback */ | |
128 | struct spi_transfer status; | |
129 | struct spi_message readback; | |
130 | ||
131 | /* underlying DMA-aware controller, or null */ | |
132 | struct device *dma_dev; | |
133 | ||
134 | /* buffer used for commands and for message "overhead" */ | |
135 | struct scratch *data; | |
136 | dma_addr_t data_dma; | |
137 | ||
138 | /* Specs say to write ones most of the time, even when the card | |
139 | * has no need to read its input data; and many cards won't care. | |
140 | * This is our source of those ones. | |
141 | */ | |
142 | void *ones; | |
143 | dma_addr_t ones_dma; | |
144 | }; | |
145 | ||
146 | ||
147 | /****************************************************************************/ | |
148 | ||
149 | /* | |
150 | * MMC-over-SPI protocol glue, used by the MMC stack interface | |
151 | */ | |
152 | ||
153 | static inline int mmc_cs_off(struct mmc_spi_host *host) | |
154 | { | |
155 | /* chipselect will always be inactive after setup() */ | |
156 | return spi_setup(host->spi); | |
157 | } | |
158 | ||
159 | static int | |
160 | mmc_spi_readbytes(struct mmc_spi_host *host, unsigned len) | |
161 | { | |
162 | int status; | |
163 | ||
164 | if (len > sizeof(*host->data)) { | |
165 | WARN_ON(1); | |
166 | return -EIO; | |
167 | } | |
168 | ||
169 | host->status.len = len; | |
170 | ||
171 | if (host->dma_dev) | |
172 | dma_sync_single_for_device(host->dma_dev, | |
173 | host->data_dma, sizeof(*host->data), | |
174 | DMA_FROM_DEVICE); | |
175 | ||
176 | status = spi_sync(host->spi, &host->readback); | |
15a0580c DB |
177 | |
178 | if (host->dma_dev) | |
179 | dma_sync_single_for_cpu(host->dma_dev, | |
180 | host->data_dma, sizeof(*host->data), | |
181 | DMA_FROM_DEVICE); | |
182 | ||
183 | return status; | |
184 | } | |
185 | ||
56e303eb WM |
186 | static int mmc_spi_skip(struct mmc_spi_host *host, unsigned long timeout, |
187 | unsigned n, u8 byte) | |
15a0580c DB |
188 | { |
189 | u8 *cp = host->data->status; | |
56e303eb | 190 | unsigned long start = jiffies; |
15a0580c DB |
191 | |
192 | while (1) { | |
193 | int status; | |
194 | unsigned i; | |
195 | ||
196 | status = mmc_spi_readbytes(host, n); | |
197 | if (status < 0) | |
198 | return status; | |
199 | ||
200 | for (i = 0; i < n; i++) { | |
201 | if (cp[i] != byte) | |
202 | return cp[i]; | |
203 | } | |
204 | ||
56e303eb | 205 | if (time_is_before_jiffies(start + timeout)) |
15a0580c | 206 | break; |
56e303eb WM |
207 | |
208 | /* If we need long timeouts, we may release the CPU. | |
209 | * We use jiffies here because we want to have a relation | |
210 | * between elapsed time and the blocking of the scheduler. | |
211 | */ | |
212 | if (time_is_before_jiffies(start+1)) | |
213 | schedule(); | |
15a0580c DB |
214 | } |
215 | return -ETIMEDOUT; | |
216 | } | |
217 | ||
218 | static inline int | |
56e303eb | 219 | mmc_spi_wait_unbusy(struct mmc_spi_host *host, unsigned long timeout) |
15a0580c DB |
220 | { |
221 | return mmc_spi_skip(host, timeout, sizeof(host->data->status), 0); | |
222 | } | |
223 | ||
56e303eb | 224 | static int mmc_spi_readtoken(struct mmc_spi_host *host, unsigned long timeout) |
15a0580c | 225 | { |
162350eb | 226 | return mmc_spi_skip(host, timeout, 1, 0xff); |
15a0580c DB |
227 | } |
228 | ||
229 | ||
230 | /* | |
231 | * Note that for SPI, cmd->resp[0] is not the same data as "native" protocol | |
232 | * hosts return! The low byte holds R1_SPI bits. The next byte may hold | |
233 | * R2_SPI bits ... for SEND_STATUS, or after data read errors. | |
234 | * | |
235 | * cmd->resp[1] holds any four-byte response, for R3 (READ_OCR) and on | |
236 | * newer cards R7 (IF_COND). | |
237 | */ | |
238 | ||
239 | static char *maptype(struct mmc_command *cmd) | |
240 | { | |
241 | switch (mmc_spi_resp_type(cmd)) { | |
242 | case MMC_RSP_SPI_R1: return "R1"; | |
243 | case MMC_RSP_SPI_R1B: return "R1B"; | |
244 | case MMC_RSP_SPI_R2: return "R2/R5"; | |
245 | case MMC_RSP_SPI_R3: return "R3/R4/R7"; | |
246 | default: return "?"; | |
247 | } | |
248 | } | |
249 | ||
250 | /* return zero, else negative errno after setting cmd->error */ | |
251 | static int mmc_spi_response_get(struct mmc_spi_host *host, | |
252 | struct mmc_command *cmd, int cs_on) | |
253 | { | |
254 | u8 *cp = host->data->status; | |
255 | u8 *end = cp + host->t.len; | |
256 | int value = 0; | |
ab5a643c WM |
257 | int bitshift; |
258 | u8 leftover = 0; | |
259 | unsigned short rotator; | |
260 | int i; | |
15a0580c DB |
261 | char tag[32]; |
262 | ||
263 | snprintf(tag, sizeof(tag), " ... CMD%d response SPI_%s", | |
264 | cmd->opcode, maptype(cmd)); | |
265 | ||
266 | /* Except for data block reads, the whole response will already | |
267 | * be stored in the scratch buffer. It's somewhere after the | |
268 | * command and the first byte we read after it. We ignore that | |
269 | * first byte. After STOP_TRANSMISSION command it may include | |
270 | * two data bits, but otherwise it's all ones. | |
271 | */ | |
272 | cp += 8; | |
273 | while (cp < end && *cp == 0xff) | |
274 | cp++; | |
275 | ||
276 | /* Data block reads (R1 response types) may need more data... */ | |
277 | if (cp == end) { | |
15a0580c | 278 | cp = host->data->status; |
ab5a643c | 279 | end = cp+1; |
15a0580c DB |
280 | |
281 | /* Card sends N(CR) (== 1..8) bytes of all-ones then one | |
282 | * status byte ... and we already scanned 2 bytes. | |
283 | * | |
284 | * REVISIT block read paths use nasty byte-at-a-time I/O | |
285 | * so it can always DMA directly into the target buffer. | |
286 | * It'd probably be better to memcpy() the first chunk and | |
287 | * avoid extra i/o calls... | |
ea15ba5c WM |
288 | * |
289 | * Note we check for more than 8 bytes, because in practice, | |
290 | * some SD cards are slow... | |
15a0580c | 291 | */ |
ea15ba5c | 292 | for (i = 2; i < 16; i++) { |
15a0580c DB |
293 | value = mmc_spi_readbytes(host, 1); |
294 | if (value < 0) | |
295 | goto done; | |
296 | if (*cp != 0xff) | |
297 | goto checkstatus; | |
298 | } | |
299 | value = -ETIMEDOUT; | |
300 | goto done; | |
301 | } | |
302 | ||
303 | checkstatus: | |
ab5a643c WM |
304 | bitshift = 0; |
305 | if (*cp & 0x80) { | |
306 | /* Houston, we have an ugly card with a bit-shifted response */ | |
307 | rotator = *cp++ << 8; | |
308 | /* read the next byte */ | |
309 | if (cp == end) { | |
310 | value = mmc_spi_readbytes(host, 1); | |
311 | if (value < 0) | |
312 | goto done; | |
313 | cp = host->data->status; | |
314 | end = cp+1; | |
315 | } | |
316 | rotator |= *cp++; | |
317 | while (rotator & 0x8000) { | |
318 | bitshift++; | |
319 | rotator <<= 1; | |
320 | } | |
321 | cmd->resp[0] = rotator >> 8; | |
322 | leftover = rotator; | |
323 | } else { | |
324 | cmd->resp[0] = *cp++; | |
15a0580c | 325 | } |
15a0580c DB |
326 | cmd->error = 0; |
327 | ||
328 | /* Status byte: the entire seven-bit R1 response. */ | |
329 | if (cmd->resp[0] != 0) { | |
330 | if ((R1_SPI_PARAMETER | R1_SPI_ADDRESS | |
ab5a643c | 331 | | R1_SPI_ILLEGAL_COMMAND) |
15a0580c DB |
332 | & cmd->resp[0]) |
333 | value = -EINVAL; | |
334 | else if (R1_SPI_COM_CRC & cmd->resp[0]) | |
335 | value = -EILSEQ; | |
336 | else if ((R1_SPI_ERASE_SEQ | R1_SPI_ERASE_RESET) | |
337 | & cmd->resp[0]) | |
338 | value = -EIO; | |
339 | /* else R1_SPI_IDLE, "it's resetting" */ | |
340 | } | |
341 | ||
342 | switch (mmc_spi_resp_type(cmd)) { | |
343 | ||
344 | /* SPI R1B == R1 + busy; STOP_TRANSMISSION (for multiblock reads) | |
345 | * and less-common stuff like various erase operations. | |
346 | */ | |
347 | case MMC_RSP_SPI_R1B: | |
348 | /* maybe we read all the busy tokens already */ | |
349 | while (cp < end && *cp == 0) | |
350 | cp++; | |
351 | if (cp == end) | |
352 | mmc_spi_wait_unbusy(host, r1b_timeout); | |
353 | break; | |
354 | ||
355 | /* SPI R2 == R1 + second status byte; SEND_STATUS | |
356 | * SPI R5 == R1 + data byte; IO_RW_DIRECT | |
357 | */ | |
358 | case MMC_RSP_SPI_R2: | |
ab5a643c WM |
359 | /* read the next byte */ |
360 | if (cp == end) { | |
361 | value = mmc_spi_readbytes(host, 1); | |
362 | if (value < 0) | |
363 | goto done; | |
364 | cp = host->data->status; | |
365 | end = cp+1; | |
366 | } | |
367 | if (bitshift) { | |
368 | rotator = leftover << 8; | |
369 | rotator |= *cp << bitshift; | |
370 | cmd->resp[0] |= (rotator & 0xFF00); | |
371 | } else { | |
372 | cmd->resp[0] |= *cp << 8; | |
373 | } | |
15a0580c DB |
374 | break; |
375 | ||
376 | /* SPI R3, R4, or R7 == R1 + 4 bytes */ | |
377 | case MMC_RSP_SPI_R3: | |
ab5a643c WM |
378 | rotator = leftover << 8; |
379 | cmd->resp[1] = 0; | |
380 | for (i = 0; i < 4; i++) { | |
381 | cmd->resp[1] <<= 8; | |
382 | /* read the next byte */ | |
383 | if (cp == end) { | |
384 | value = mmc_spi_readbytes(host, 1); | |
385 | if (value < 0) | |
386 | goto done; | |
387 | cp = host->data->status; | |
388 | end = cp+1; | |
389 | } | |
390 | if (bitshift) { | |
391 | rotator |= *cp++ << bitshift; | |
392 | cmd->resp[1] |= (rotator >> 8); | |
393 | rotator <<= 8; | |
394 | } else { | |
395 | cmd->resp[1] |= *cp++; | |
396 | } | |
397 | } | |
15a0580c DB |
398 | break; |
399 | ||
400 | /* SPI R1 == just one status byte */ | |
401 | case MMC_RSP_SPI_R1: | |
402 | break; | |
403 | ||
404 | default: | |
405 | dev_dbg(&host->spi->dev, "bad response type %04x\n", | |
406 | mmc_spi_resp_type(cmd)); | |
407 | if (value >= 0) | |
408 | value = -EINVAL; | |
409 | goto done; | |
410 | } | |
411 | ||
412 | if (value < 0) | |
413 | dev_dbg(&host->spi->dev, "%s: resp %04x %08x\n", | |
414 | tag, cmd->resp[0], cmd->resp[1]); | |
415 | ||
416 | /* disable chipselect on errors and some success cases */ | |
417 | if (value >= 0 && cs_on) | |
418 | return value; | |
419 | done: | |
420 | if (value < 0) | |
421 | cmd->error = value; | |
422 | mmc_cs_off(host); | |
423 | return value; | |
424 | } | |
425 | ||
426 | /* Issue command and read its response. | |
427 | * Returns zero on success, negative for error. | |
428 | * | |
429 | * On error, caller must cope with mmc core retry mechanism. That | |
430 | * means immediate low-level resubmit, which affects the bus lock... | |
431 | */ | |
432 | static int | |
433 | mmc_spi_command_send(struct mmc_spi_host *host, | |
434 | struct mmc_request *mrq, | |
435 | struct mmc_command *cmd, int cs_on) | |
436 | { | |
437 | struct scratch *data = host->data; | |
438 | u8 *cp = data->status; | |
439 | u32 arg = cmd->arg; | |
440 | int status; | |
441 | struct spi_transfer *t; | |
442 | ||
443 | /* We can handle most commands (except block reads) in one full | |
444 | * duplex I/O operation before either starting the next transfer | |
445 | * (data block or command) or else deselecting the card. | |
446 | * | |
447 | * First, write 7 bytes: | |
448 | * - an all-ones byte to ensure the card is ready | |
449 | * - opcode byte (plus start and transmission bits) | |
450 | * - four bytes of big-endian argument | |
451 | * - crc7 (plus end bit) ... always computed, it's cheap | |
452 | * | |
453 | * We init the whole buffer to all-ones, which is what we need | |
454 | * to write while we're reading (later) response data. | |
455 | */ | |
456 | memset(cp++, 0xff, sizeof(data->status)); | |
457 | ||
458 | *cp++ = 0x40 | cmd->opcode; | |
459 | *cp++ = (u8)(arg >> 24); | |
460 | *cp++ = (u8)(arg >> 16); | |
461 | *cp++ = (u8)(arg >> 8); | |
462 | *cp++ = (u8)arg; | |
463 | *cp++ = (crc7(0, &data->status[1], 5) << 1) | 0x01; | |
464 | ||
465 | /* Then, read up to 13 bytes (while writing all-ones): | |
466 | * - N(CR) (== 1..8) bytes of all-ones | |
467 | * - status byte (for all response types) | |
468 | * - the rest of the response, either: | |
469 | * + nothing, for R1 or R1B responses | |
470 | * + second status byte, for R2 responses | |
471 | * + four data bytes, for R3 and R7 responses | |
472 | * | |
473 | * Finally, read some more bytes ... in the nice cases we know in | |
474 | * advance how many, and reading 1 more is always OK: | |
475 | * - N(EC) (== 0..N) bytes of all-ones, before deselect/finish | |
476 | * - N(RC) (== 1..N) bytes of all-ones, before next command | |
477 | * - N(WR) (== 1..N) bytes of all-ones, before data write | |
478 | * | |
479 | * So in those cases one full duplex I/O of at most 21 bytes will | |
480 | * handle the whole command, leaving the card ready to receive a | |
481 | * data block or new command. We do that whenever we can, shaving | |
482 | * CPU and IRQ costs (especially when using DMA or FIFOs). | |
483 | * | |
484 | * There are two other cases, where it's not generally practical | |
485 | * to rely on a single I/O: | |
486 | * | |
487 | * - R1B responses need at least N(EC) bytes of all-zeroes. | |
488 | * | |
489 | * In this case we can *try* to fit it into one I/O, then | |
490 | * maybe read more data later. | |
491 | * | |
492 | * - Data block reads are more troublesome, since a variable | |
493 | * number of padding bytes precede the token and data. | |
494 | * + N(CX) (== 0..8) bytes of all-ones, before CSD or CID | |
495 | * + N(AC) (== 1..many) bytes of all-ones | |
496 | * | |
497 | * In this case we currently only have minimal speedups here: | |
498 | * when N(CR) == 1 we can avoid I/O in response_get(). | |
499 | */ | |
500 | if (cs_on && (mrq->data->flags & MMC_DATA_READ)) { | |
501 | cp += 2; /* min(N(CR)) + status */ | |
502 | /* R1 */ | |
503 | } else { | |
504 | cp += 10; /* max(N(CR)) + status + min(N(RC),N(WR)) */ | |
505 | if (cmd->flags & MMC_RSP_SPI_S2) /* R2/R5 */ | |
506 | cp++; | |
507 | else if (cmd->flags & MMC_RSP_SPI_B4) /* R3/R4/R7 */ | |
508 | cp += 4; | |
509 | else if (cmd->flags & MMC_RSP_BUSY) /* R1B */ | |
510 | cp = data->status + sizeof(data->status); | |
511 | /* else: R1 (most commands) */ | |
512 | } | |
513 | ||
514 | dev_dbg(&host->spi->dev, " mmc_spi: CMD%d, resp %s\n", | |
515 | cmd->opcode, maptype(cmd)); | |
516 | ||
517 | /* send command, leaving chipselect active */ | |
518 | spi_message_init(&host->m); | |
519 | ||
520 | t = &host->t; | |
521 | memset(t, 0, sizeof(*t)); | |
522 | t->tx_buf = t->rx_buf = data->status; | |
523 | t->tx_dma = t->rx_dma = host->data_dma; | |
524 | t->len = cp - data->status; | |
525 | t->cs_change = 1; | |
526 | spi_message_add_tail(t, &host->m); | |
527 | ||
528 | if (host->dma_dev) { | |
529 | host->m.is_dma_mapped = 1; | |
530 | dma_sync_single_for_device(host->dma_dev, | |
531 | host->data_dma, sizeof(*host->data), | |
532 | DMA_BIDIRECTIONAL); | |
533 | } | |
534 | status = spi_sync(host->spi, &host->m); | |
15a0580c DB |
535 | |
536 | if (host->dma_dev) | |
537 | dma_sync_single_for_cpu(host->dma_dev, | |
538 | host->data_dma, sizeof(*host->data), | |
539 | DMA_BIDIRECTIONAL); | |
540 | if (status < 0) { | |
541 | dev_dbg(&host->spi->dev, " ... write returned %d\n", status); | |
542 | cmd->error = status; | |
543 | return status; | |
544 | } | |
545 | ||
546 | /* after no-data commands and STOP_TRANSMISSION, chipselect off */ | |
547 | return mmc_spi_response_get(host, cmd, cs_on); | |
548 | } | |
549 | ||
550 | /* Build data message with up to four separate transfers. For TX, we | |
551 | * start by writing the data token. And in most cases, we finish with | |
552 | * a status transfer. | |
553 | * | |
554 | * We always provide TX data for data and CRC. The MMC/SD protocol | |
555 | * requires us to write ones; but Linux defaults to writing zeroes; | |
556 | * so we explicitly initialize it to all ones on RX paths. | |
557 | * | |
558 | * We also handle DMA mapping, so the underlying SPI controller does | |
559 | * not need to (re)do it for each message. | |
560 | */ | |
561 | static void | |
562 | mmc_spi_setup_data_message( | |
563 | struct mmc_spi_host *host, | |
564 | int multiple, | |
565 | enum dma_data_direction direction) | |
566 | { | |
567 | struct spi_transfer *t; | |
568 | struct scratch *scratch = host->data; | |
569 | dma_addr_t dma = host->data_dma; | |
570 | ||
571 | spi_message_init(&host->m); | |
572 | if (dma) | |
573 | host->m.is_dma_mapped = 1; | |
574 | ||
575 | /* for reads, readblock() skips 0xff bytes before finding | |
576 | * the token; for writes, this transfer issues that token. | |
577 | */ | |
578 | if (direction == DMA_TO_DEVICE) { | |
579 | t = &host->token; | |
580 | memset(t, 0, sizeof(*t)); | |
581 | t->len = 1; | |
582 | if (multiple) | |
583 | scratch->data_token = SPI_TOKEN_MULTI_WRITE; | |
584 | else | |
585 | scratch->data_token = SPI_TOKEN_SINGLE; | |
586 | t->tx_buf = &scratch->data_token; | |
587 | if (dma) | |
588 | t->tx_dma = dma + offsetof(struct scratch, data_token); | |
589 | spi_message_add_tail(t, &host->m); | |
590 | } | |
591 | ||
592 | /* Body of transfer is buffer, then CRC ... | |
593 | * either TX-only, or RX with TX-ones. | |
594 | */ | |
595 | t = &host->t; | |
596 | memset(t, 0, sizeof(*t)); | |
597 | t->tx_buf = host->ones; | |
598 | t->tx_dma = host->ones_dma; | |
599 | /* length and actual buffer info are written later */ | |
600 | spi_message_add_tail(t, &host->m); | |
601 | ||
602 | t = &host->crc; | |
603 | memset(t, 0, sizeof(*t)); | |
604 | t->len = 2; | |
605 | if (direction == DMA_TO_DEVICE) { | |
606 | /* the actual CRC may get written later */ | |
607 | t->tx_buf = &scratch->crc_val; | |
608 | if (dma) | |
609 | t->tx_dma = dma + offsetof(struct scratch, crc_val); | |
610 | } else { | |
611 | t->tx_buf = host->ones; | |
612 | t->tx_dma = host->ones_dma; | |
613 | t->rx_buf = &scratch->crc_val; | |
614 | if (dma) | |
615 | t->rx_dma = dma + offsetof(struct scratch, crc_val); | |
616 | } | |
617 | spi_message_add_tail(t, &host->m); | |
618 | ||
619 | /* | |
620 | * A single block read is followed by N(EC) [0+] all-ones bytes | |
621 | * before deselect ... don't bother. | |
622 | * | |
623 | * Multiblock reads are followed by N(AC) [1+] all-ones bytes before | |
624 | * the next block is read, or a STOP_TRANSMISSION is issued. We'll | |
625 | * collect that single byte, so readblock() doesn't need to. | |
626 | * | |
627 | * For a write, the one-byte data response follows immediately, then | |
628 | * come zero or more busy bytes, then N(WR) [1+] all-ones bytes. | |
629 | * Then single block reads may deselect, and multiblock ones issue | |
630 | * the next token (next data block, or STOP_TRAN). We can try to | |
631 | * minimize I/O ops by using a single read to collect end-of-busy. | |
632 | */ | |
633 | if (multiple || direction == DMA_TO_DEVICE) { | |
634 | t = &host->early_status; | |
635 | memset(t, 0, sizeof(*t)); | |
636 | t->len = (direction == DMA_TO_DEVICE) | |
637 | ? sizeof(scratch->status) | |
638 | : 1; | |
639 | t->tx_buf = host->ones; | |
640 | t->tx_dma = host->ones_dma; | |
641 | t->rx_buf = scratch->status; | |
642 | if (dma) | |
643 | t->rx_dma = dma + offsetof(struct scratch, status); | |
644 | t->cs_change = 1; | |
645 | spi_message_add_tail(t, &host->m); | |
646 | } | |
647 | } | |
648 | ||
649 | /* | |
650 | * Write one block: | |
651 | * - caller handled preceding N(WR) [1+] all-ones bytes | |
652 | * - data block | |
653 | * + token | |
654 | * + data bytes | |
655 | * + crc16 | |
656 | * - an all-ones byte ... card writes a data-response byte | |
657 | * - followed by N(EC) [0+] all-ones bytes, card writes zero/'busy' | |
658 | * | |
659 | * Return negative errno, else success. | |
660 | */ | |
661 | static int | |
162350eb | 662 | mmc_spi_writeblock(struct mmc_spi_host *host, struct spi_transfer *t, |
56e303eb | 663 | unsigned long timeout) |
15a0580c DB |
664 | { |
665 | struct spi_device *spi = host->spi; | |
666 | int status, i; | |
667 | struct scratch *scratch = host->data; | |
f079a8fc | 668 | u32 pattern; |
15a0580c DB |
669 | |
670 | if (host->mmc->use_spi_crc) | |
671 | scratch->crc_val = cpu_to_be16( | |
672 | crc_itu_t(0, t->tx_buf, t->len)); | |
673 | if (host->dma_dev) | |
674 | dma_sync_single_for_device(host->dma_dev, | |
675 | host->data_dma, sizeof(*scratch), | |
676 | DMA_BIDIRECTIONAL); | |
677 | ||
678 | status = spi_sync(spi, &host->m); | |
15a0580c DB |
679 | |
680 | if (status != 0) { | |
681 | dev_dbg(&spi->dev, "write error (%d)\n", status); | |
682 | return status; | |
683 | } | |
684 | ||
685 | if (host->dma_dev) | |
686 | dma_sync_single_for_cpu(host->dma_dev, | |
687 | host->data_dma, sizeof(*scratch), | |
688 | DMA_BIDIRECTIONAL); | |
689 | ||
690 | /* | |
691 | * Get the transmission data-response reply. It must follow | |
692 | * immediately after the data block we transferred. This reply | |
693 | * doesn't necessarily tell whether the write operation succeeded; | |
694 | * it just says if the transmission was ok and whether *earlier* | |
695 | * writes succeeded; see the standard. | |
f079a8fc WM |
696 | * |
697 | * In practice, there are (even modern SDHC-)cards which are late | |
698 | * in sending the response, and miss the time frame by a few bits, | |
699 | * so we have to cope with this situation and check the response | |
700 | * bit-by-bit. Arggh!!! | |
15a0580c | 701 | */ |
f079a8fc WM |
702 | pattern = scratch->status[0] << 24; |
703 | pattern |= scratch->status[1] << 16; | |
704 | pattern |= scratch->status[2] << 8; | |
705 | pattern |= scratch->status[3]; | |
706 | ||
707 | /* First 3 bit of pattern are undefined */ | |
708 | pattern |= 0xE0000000; | |
709 | ||
710 | /* left-adjust to leading 0 bit */ | |
711 | while (pattern & 0x80000000) | |
712 | pattern <<= 1; | |
713 | /* right-adjust for pattern matching. Code is in bit 4..0 now. */ | |
714 | pattern >>= 27; | |
715 | ||
716 | switch (pattern) { | |
15a0580c DB |
717 | case SPI_RESPONSE_ACCEPTED: |
718 | status = 0; | |
719 | break; | |
720 | case SPI_RESPONSE_CRC_ERR: | |
721 | /* host shall then issue MMC_STOP_TRANSMISSION */ | |
722 | status = -EILSEQ; | |
723 | break; | |
724 | case SPI_RESPONSE_WRITE_ERR: | |
725 | /* host shall then issue MMC_STOP_TRANSMISSION, | |
726 | * and should MMC_SEND_STATUS to sort it out | |
727 | */ | |
728 | status = -EIO; | |
729 | break; | |
730 | default: | |
731 | status = -EPROTO; | |
732 | break; | |
733 | } | |
734 | if (status != 0) { | |
735 | dev_dbg(&spi->dev, "write error %02x (%d)\n", | |
736 | scratch->status[0], status); | |
737 | return status; | |
738 | } | |
739 | ||
740 | t->tx_buf += t->len; | |
741 | if (host->dma_dev) | |
742 | t->tx_dma += t->len; | |
743 | ||
744 | /* Return when not busy. If we didn't collect that status yet, | |
745 | * we'll need some more I/O. | |
746 | */ | |
f079a8fc WM |
747 | for (i = 4; i < sizeof(scratch->status); i++) { |
748 | /* card is non-busy if the most recent bit is 1 */ | |
749 | if (scratch->status[i] & 0x01) | |
15a0580c DB |
750 | return 0; |
751 | } | |
162350eb | 752 | return mmc_spi_wait_unbusy(host, timeout); |
15a0580c DB |
753 | } |
754 | ||
755 | /* | |
756 | * Read one block: | |
757 | * - skip leading all-ones bytes ... either | |
758 | * + N(AC) [1..f(clock,CSD)] usually, else | |
759 | * + N(CX) [0..8] when reading CSD or CID | |
760 | * - data block | |
761 | * + token ... if error token, no data or crc | |
762 | * + data bytes | |
763 | * + crc16 | |
764 | * | |
765 | * After single block reads, we're done; N(EC) [0+] all-ones bytes follow | |
766 | * before dropping chipselect. | |
767 | * | |
768 | * For multiblock reads, caller either reads the next block or issues a | |
769 | * STOP_TRANSMISSION command. | |
770 | */ | |
771 | static int | |
162350eb | 772 | mmc_spi_readblock(struct mmc_spi_host *host, struct spi_transfer *t, |
56e303eb | 773 | unsigned long timeout) |
15a0580c DB |
774 | { |
775 | struct spi_device *spi = host->spi; | |
776 | int status; | |
777 | struct scratch *scratch = host->data; | |
ab5a643c WM |
778 | unsigned int bitshift; |
779 | u8 leftover; | |
15a0580c DB |
780 | |
781 | /* At least one SD card sends an all-zeroes byte when N(CX) | |
782 | * applies, before the all-ones bytes ... just cope with that. | |
783 | */ | |
784 | status = mmc_spi_readbytes(host, 1); | |
785 | if (status < 0) | |
786 | return status; | |
787 | status = scratch->status[0]; | |
788 | if (status == 0xff || status == 0) | |
162350eb | 789 | status = mmc_spi_readtoken(host, timeout); |
15a0580c | 790 | |
ab5a643c WM |
791 | if (status < 0) { |
792 | dev_dbg(&spi->dev, "read error %02x (%d)\n", status, status); | |
793 | return status; | |
794 | } | |
15a0580c | 795 | |
ab5a643c WM |
796 | /* The token may be bit-shifted... |
797 | * the first 0-bit precedes the data stream. | |
798 | */ | |
799 | bitshift = 7; | |
800 | while (status & 0x80) { | |
801 | status <<= 1; | |
802 | bitshift--; | |
803 | } | |
804 | leftover = status << 1; | |
15a0580c | 805 | |
ab5a643c WM |
806 | if (host->dma_dev) { |
807 | dma_sync_single_for_device(host->dma_dev, | |
808 | host->data_dma, sizeof(*scratch), | |
809 | DMA_BIDIRECTIONAL); | |
810 | dma_sync_single_for_device(host->dma_dev, | |
811 | t->rx_dma, t->len, | |
812 | DMA_FROM_DEVICE); | |
813 | } | |
15a0580c | 814 | |
ab5a643c | 815 | status = spi_sync(spi, &host->m); |
15a0580c | 816 | |
ab5a643c WM |
817 | if (host->dma_dev) { |
818 | dma_sync_single_for_cpu(host->dma_dev, | |
819 | host->data_dma, sizeof(*scratch), | |
820 | DMA_BIDIRECTIONAL); | |
821 | dma_sync_single_for_cpu(host->dma_dev, | |
822 | t->rx_dma, t->len, | |
823 | DMA_FROM_DEVICE); | |
824 | } | |
15a0580c | 825 | |
ab5a643c WM |
826 | if (bitshift) { |
827 | /* Walk through the data and the crc and do | |
828 | * all the magic to get byte-aligned data. | |
15a0580c | 829 | */ |
ab5a643c WM |
830 | u8 *cp = t->rx_buf; |
831 | unsigned int len; | |
832 | unsigned int bitright = 8 - bitshift; | |
833 | u8 temp; | |
834 | for (len = t->len; len; len--) { | |
835 | temp = *cp; | |
836 | *cp++ = leftover | (temp >> bitshift); | |
837 | leftover = temp << bitright; | |
838 | } | |
839 | cp = (u8 *) &scratch->crc_val; | |
840 | temp = *cp; | |
841 | *cp++ = leftover | (temp >> bitshift); | |
842 | leftover = temp << bitright; | |
843 | temp = *cp; | |
844 | *cp = leftover | (temp >> bitshift); | |
15a0580c DB |
845 | } |
846 | ||
847 | if (host->mmc->use_spi_crc) { | |
848 | u16 crc = crc_itu_t(0, t->rx_buf, t->len); | |
849 | ||
850 | be16_to_cpus(&scratch->crc_val); | |
851 | if (scratch->crc_val != crc) { | |
852 | dev_dbg(&spi->dev, "read - crc error: crc_val=0x%04x, " | |
853 | "computed=0x%04x len=%d\n", | |
854 | scratch->crc_val, crc, t->len); | |
855 | return -EILSEQ; | |
856 | } | |
857 | } | |
858 | ||
859 | t->rx_buf += t->len; | |
860 | if (host->dma_dev) | |
861 | t->rx_dma += t->len; | |
862 | ||
863 | return 0; | |
864 | } | |
865 | ||
866 | /* | |
867 | * An MMC/SD data stage includes one or more blocks, optional CRCs, | |
868 | * and inline handshaking. That handhaking makes it unlike most | |
869 | * other SPI protocol stacks. | |
870 | */ | |
871 | static void | |
872 | mmc_spi_data_do(struct mmc_spi_host *host, struct mmc_command *cmd, | |
873 | struct mmc_data *data, u32 blk_size) | |
874 | { | |
875 | struct spi_device *spi = host->spi; | |
876 | struct device *dma_dev = host->dma_dev; | |
877 | struct spi_transfer *t; | |
878 | enum dma_data_direction direction; | |
879 | struct scatterlist *sg; | |
880 | unsigned n_sg; | |
881 | int multiple = (data->blocks > 1); | |
162350eb | 882 | u32 clock_rate; |
56e303eb | 883 | unsigned long timeout; |
15a0580c DB |
884 | |
885 | if (data->flags & MMC_DATA_READ) | |
886 | direction = DMA_FROM_DEVICE; | |
887 | else | |
888 | direction = DMA_TO_DEVICE; | |
889 | mmc_spi_setup_data_message(host, multiple, direction); | |
890 | t = &host->t; | |
891 | ||
162350eb MF |
892 | if (t->speed_hz) |
893 | clock_rate = t->speed_hz; | |
894 | else | |
895 | clock_rate = spi->max_speed_hz; | |
896 | ||
56e303eb WM |
897 | timeout = data->timeout_ns + |
898 | data->timeout_clks * 1000000 / clock_rate; | |
899 | timeout = usecs_to_jiffies((unsigned int)(timeout / 1000)) + 1; | |
162350eb | 900 | |
15a0580c DB |
901 | /* Handle scatterlist segments one at a time, with synch for |
902 | * each 512-byte block | |
903 | */ | |
904 | for (sg = data->sg, n_sg = data->sg_len; n_sg; n_sg--, sg++) { | |
905 | int status = 0; | |
906 | dma_addr_t dma_addr = 0; | |
907 | void *kmap_addr; | |
908 | unsigned length = sg->length; | |
909 | enum dma_data_direction dir = direction; | |
910 | ||
911 | /* set up dma mapping for controller drivers that might | |
912 | * use DMA ... though they may fall back to PIO | |
913 | */ | |
914 | if (dma_dev) { | |
915 | /* never invalidate whole *shared* pages ... */ | |
916 | if ((sg->offset != 0 || length != PAGE_SIZE) | |
917 | && dir == DMA_FROM_DEVICE) | |
918 | dir = DMA_BIDIRECTIONAL; | |
919 | ||
45711f1a | 920 | dma_addr = dma_map_page(dma_dev, sg_page(sg), 0, |
15a0580c DB |
921 | PAGE_SIZE, dir); |
922 | if (direction == DMA_TO_DEVICE) | |
923 | t->tx_dma = dma_addr + sg->offset; | |
924 | else | |
925 | t->rx_dma = dma_addr + sg->offset; | |
926 | } | |
927 | ||
928 | /* allow pio too; we don't allow highmem */ | |
45711f1a | 929 | kmap_addr = kmap(sg_page(sg)); |
15a0580c DB |
930 | if (direction == DMA_TO_DEVICE) |
931 | t->tx_buf = kmap_addr + sg->offset; | |
932 | else | |
933 | t->rx_buf = kmap_addr + sg->offset; | |
934 | ||
935 | /* transfer each block, and update request status */ | |
936 | while (length) { | |
937 | t->len = min(length, blk_size); | |
938 | ||
939 | dev_dbg(&host->spi->dev, | |
940 | " mmc_spi: %s block, %d bytes\n", | |
941 | (direction == DMA_TO_DEVICE) | |
942 | ? "write" | |
943 | : "read", | |
944 | t->len); | |
945 | ||
946 | if (direction == DMA_TO_DEVICE) | |
162350eb | 947 | status = mmc_spi_writeblock(host, t, timeout); |
15a0580c | 948 | else |
162350eb | 949 | status = mmc_spi_readblock(host, t, timeout); |
15a0580c DB |
950 | if (status < 0) |
951 | break; | |
952 | ||
953 | data->bytes_xfered += t->len; | |
954 | length -= t->len; | |
955 | ||
956 | if (!multiple) | |
957 | break; | |
958 | } | |
959 | ||
960 | /* discard mappings */ | |
961 | if (direction == DMA_FROM_DEVICE) | |
45711f1a JA |
962 | flush_kernel_dcache_page(sg_page(sg)); |
963 | kunmap(sg_page(sg)); | |
15a0580c DB |
964 | if (dma_dev) |
965 | dma_unmap_page(dma_dev, dma_addr, PAGE_SIZE, dir); | |
966 | ||
967 | if (status < 0) { | |
968 | data->error = status; | |
969 | dev_dbg(&spi->dev, "%s status %d\n", | |
970 | (direction == DMA_TO_DEVICE) | |
971 | ? "write" : "read", | |
972 | status); | |
973 | break; | |
974 | } | |
975 | } | |
976 | ||
977 | /* NOTE some docs describe an MMC-only SET_BLOCK_COUNT (CMD23) that | |
978 | * can be issued before multiblock writes. Unlike its more widely | |
979 | * documented analogue for SD cards (SET_WR_BLK_ERASE_COUNT, ACMD23), | |
980 | * that can affect the STOP_TRAN logic. Complete (and current) | |
981 | * MMC specs should sort that out before Linux starts using CMD23. | |
982 | */ | |
983 | if (direction == DMA_TO_DEVICE && multiple) { | |
984 | struct scratch *scratch = host->data; | |
985 | int tmp; | |
986 | const unsigned statlen = sizeof(scratch->status); | |
987 | ||
988 | dev_dbg(&spi->dev, " mmc_spi: STOP_TRAN\n"); | |
989 | ||
990 | /* Tweak the per-block message we set up earlier by morphing | |
991 | * it to hold single buffer with the token followed by some | |
992 | * all-ones bytes ... skip N(BR) (0..1), scan the rest for | |
993 | * "not busy any longer" status, and leave chip selected. | |
994 | */ | |
995 | INIT_LIST_HEAD(&host->m.transfers); | |
996 | list_add(&host->early_status.transfer_list, | |
997 | &host->m.transfers); | |
998 | ||
999 | memset(scratch->status, 0xff, statlen); | |
1000 | scratch->status[0] = SPI_TOKEN_STOP_TRAN; | |
1001 | ||
1002 | host->early_status.tx_buf = host->early_status.rx_buf; | |
1003 | host->early_status.tx_dma = host->early_status.rx_dma; | |
1004 | host->early_status.len = statlen; | |
1005 | ||
1006 | if (host->dma_dev) | |
1007 | dma_sync_single_for_device(host->dma_dev, | |
1008 | host->data_dma, sizeof(*scratch), | |
1009 | DMA_BIDIRECTIONAL); | |
1010 | ||
1011 | tmp = spi_sync(spi, &host->m); | |
15a0580c DB |
1012 | |
1013 | if (host->dma_dev) | |
1014 | dma_sync_single_for_cpu(host->dma_dev, | |
1015 | host->data_dma, sizeof(*scratch), | |
1016 | DMA_BIDIRECTIONAL); | |
1017 | ||
1018 | if (tmp < 0) { | |
1019 | if (!data->error) | |
1020 | data->error = tmp; | |
1021 | return; | |
1022 | } | |
1023 | ||
1024 | /* Ideally we collected "not busy" status with one I/O, | |
1025 | * avoiding wasteful byte-at-a-time scanning... but more | |
1026 | * I/O is often needed. | |
1027 | */ | |
1028 | for (tmp = 2; tmp < statlen; tmp++) { | |
1029 | if (scratch->status[tmp] != 0) | |
1030 | return; | |
1031 | } | |
162350eb | 1032 | tmp = mmc_spi_wait_unbusy(host, timeout); |
15a0580c DB |
1033 | if (tmp < 0 && !data->error) |
1034 | data->error = tmp; | |
1035 | } | |
1036 | } | |
1037 | ||
1038 | /****************************************************************************/ | |
1039 | ||
1040 | /* | |
1041 | * MMC driver implementation -- the interface to the MMC stack | |
1042 | */ | |
1043 | ||
1044 | static void mmc_spi_request(struct mmc_host *mmc, struct mmc_request *mrq) | |
1045 | { | |
1046 | struct mmc_spi_host *host = mmc_priv(mmc); | |
1047 | int status = -EINVAL; | |
1048 | ||
1049 | #ifdef DEBUG | |
1050 | /* MMC core and layered drivers *MUST* issue SPI-aware commands */ | |
1051 | { | |
1052 | struct mmc_command *cmd; | |
1053 | int invalid = 0; | |
1054 | ||
1055 | cmd = mrq->cmd; | |
1056 | if (!mmc_spi_resp_type(cmd)) { | |
1057 | dev_dbg(&host->spi->dev, "bogus command\n"); | |
1058 | cmd->error = -EINVAL; | |
1059 | invalid = 1; | |
1060 | } | |
1061 | ||
1062 | cmd = mrq->stop; | |
1063 | if (cmd && !mmc_spi_resp_type(cmd)) { | |
1064 | dev_dbg(&host->spi->dev, "bogus STOP command\n"); | |
1065 | cmd->error = -EINVAL; | |
1066 | invalid = 1; | |
1067 | } | |
1068 | ||
1069 | if (invalid) { | |
1070 | dump_stack(); | |
1071 | mmc_request_done(host->mmc, mrq); | |
1072 | return; | |
1073 | } | |
1074 | } | |
1075 | #endif | |
1076 | ||
1077 | /* issue command; then optionally data and stop */ | |
1078 | status = mmc_spi_command_send(host, mrq, mrq->cmd, mrq->data != NULL); | |
1079 | if (status == 0 && mrq->data) { | |
1080 | mmc_spi_data_do(host, mrq->cmd, mrq->data, mrq->data->blksz); | |
1081 | if (mrq->stop) | |
1082 | status = mmc_spi_command_send(host, mrq, mrq->stop, 0); | |
1083 | else | |
1084 | mmc_cs_off(host); | |
1085 | } | |
1086 | ||
1087 | mmc_request_done(host->mmc, mrq); | |
1088 | } | |
1089 | ||
1090 | /* See Section 6.4.1, in SD "Simplified Physical Layer Specification 2.0" | |
1091 | * | |
1092 | * NOTE that here we can't know that the card has just been powered up; | |
1093 | * not all MMC/SD sockets support power switching. | |
1094 | * | |
1095 | * FIXME when the card is still in SPI mode, e.g. from a previous kernel, | |
1096 | * this doesn't seem to do the right thing at all... | |
1097 | */ | |
1098 | static void mmc_spi_initsequence(struct mmc_spi_host *host) | |
1099 | { | |
1100 | /* Try to be very sure any previous command has completed; | |
1101 | * wait till not-busy, skip debris from any old commands. | |
1102 | */ | |
1103 | mmc_spi_wait_unbusy(host, r1b_timeout); | |
1104 | mmc_spi_readbytes(host, 10); | |
1105 | ||
1106 | /* | |
1107 | * Do a burst with chipselect active-high. We need to do this to | |
1108 | * meet the requirement of 74 clock cycles with both chipselect | |
1109 | * and CMD (MOSI) high before CMD0 ... after the card has been | |
1110 | * powered up to Vdd(min), and so is ready to take commands. | |
1111 | * | |
1112 | * Some cards are particularly needy of this (e.g. Viking "SD256") | |
1113 | * while most others don't seem to care. | |
1114 | * | |
1115 | * Note that this is one of the places MMC/SD plays games with the | |
1116 | * SPI protocol. Another is that when chipselect is released while | |
1117 | * the card returns BUSY status, the clock must issue several cycles | |
1118 | * with chipselect high before the card will stop driving its output. | |
1119 | */ | |
1120 | host->spi->mode |= SPI_CS_HIGH; | |
1121 | if (spi_setup(host->spi) != 0) { | |
1122 | /* Just warn; most cards work without it. */ | |
1123 | dev_warn(&host->spi->dev, | |
1124 | "can't change chip-select polarity\n"); | |
1125 | host->spi->mode &= ~SPI_CS_HIGH; | |
1126 | } else { | |
1127 | mmc_spi_readbytes(host, 18); | |
1128 | ||
1129 | host->spi->mode &= ~SPI_CS_HIGH; | |
1130 | if (spi_setup(host->spi) != 0) { | |
1131 | /* Wot, we can't get the same setup we had before? */ | |
1132 | dev_err(&host->spi->dev, | |
1133 | "can't restore chip-select polarity\n"); | |
1134 | } | |
1135 | } | |
1136 | } | |
1137 | ||
1138 | static char *mmc_powerstring(u8 power_mode) | |
1139 | { | |
1140 | switch (power_mode) { | |
1141 | case MMC_POWER_OFF: return "off"; | |
1142 | case MMC_POWER_UP: return "up"; | |
1143 | case MMC_POWER_ON: return "on"; | |
1144 | } | |
1145 | return "?"; | |
1146 | } | |
1147 | ||
1148 | static void mmc_spi_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) | |
1149 | { | |
1150 | struct mmc_spi_host *host = mmc_priv(mmc); | |
1151 | ||
1152 | if (host->power_mode != ios->power_mode) { | |
1153 | int canpower; | |
1154 | ||
1155 | canpower = host->pdata && host->pdata->setpower; | |
1156 | ||
1157 | dev_dbg(&host->spi->dev, "mmc_spi: power %s (%d)%s\n", | |
1158 | mmc_powerstring(ios->power_mode), | |
1159 | ios->vdd, | |
1160 | canpower ? ", can switch" : ""); | |
1161 | ||
1162 | /* switch power on/off if possible, accounting for | |
1163 | * max 250msec powerup time if needed. | |
1164 | */ | |
1165 | if (canpower) { | |
1166 | switch (ios->power_mode) { | |
1167 | case MMC_POWER_OFF: | |
1168 | case MMC_POWER_UP: | |
1169 | host->pdata->setpower(&host->spi->dev, | |
1170 | ios->vdd); | |
1171 | if (ios->power_mode == MMC_POWER_UP) | |
1172 | msleep(host->powerup_msecs); | |
1173 | } | |
1174 | } | |
1175 | ||
1176 | /* See 6.4.1 in the simplified SD card physical spec 2.0 */ | |
1177 | if (ios->power_mode == MMC_POWER_ON) | |
1178 | mmc_spi_initsequence(host); | |
1179 | ||
1180 | /* If powering down, ground all card inputs to avoid power | |
1181 | * delivery from data lines! On a shared SPI bus, this | |
1182 | * will probably be temporary; 6.4.2 of the simplified SD | |
1183 | * spec says this must last at least 1msec. | |
1184 | * | |
1185 | * - Clock low means CPOL 0, e.g. mode 0 | |
1186 | * - MOSI low comes from writing zero | |
1187 | * - Chipselect is usually active low... | |
1188 | */ | |
1189 | if (canpower && ios->power_mode == MMC_POWER_OFF) { | |
1190 | int mres; | |
1685a03e | 1191 | u8 nullbyte = 0; |
15a0580c DB |
1192 | |
1193 | host->spi->mode &= ~(SPI_CPOL|SPI_CPHA); | |
1194 | mres = spi_setup(host->spi); | |
1195 | if (mres < 0) | |
1196 | dev_dbg(&host->spi->dev, | |
1197 | "switch to SPI mode 0 failed\n"); | |
1198 | ||
1685a03e | 1199 | if (spi_write(host->spi, &nullbyte, 1) < 0) |
15a0580c DB |
1200 | dev_dbg(&host->spi->dev, |
1201 | "put spi signals to low failed\n"); | |
1202 | ||
1203 | /* | |
1204 | * Now clock should be low due to spi mode 0; | |
1205 | * MOSI should be low because of written 0x00; | |
1206 | * chipselect should be low (it is active low) | |
1207 | * power supply is off, so now MMC is off too! | |
1208 | * | |
1209 | * FIXME no, chipselect can be high since the | |
1210 | * device is inactive and SPI_CS_HIGH is clear... | |
1211 | */ | |
1212 | msleep(10); | |
1213 | if (mres == 0) { | |
1214 | host->spi->mode |= (SPI_CPOL|SPI_CPHA); | |
1215 | mres = spi_setup(host->spi); | |
1216 | if (mres < 0) | |
1217 | dev_dbg(&host->spi->dev, | |
1218 | "switch back to SPI mode 3" | |
1219 | " failed\n"); | |
1220 | } | |
1221 | } | |
1222 | ||
1223 | host->power_mode = ios->power_mode; | |
1224 | } | |
1225 | ||
1226 | if (host->spi->max_speed_hz != ios->clock && ios->clock != 0) { | |
1227 | int status; | |
1228 | ||
1229 | host->spi->max_speed_hz = ios->clock; | |
1230 | status = spi_setup(host->spi); | |
1231 | dev_dbg(&host->spi->dev, | |
1232 | "mmc_spi: clock to %d Hz, %d\n", | |
1233 | host->spi->max_speed_hz, status); | |
1234 | } | |
1235 | } | |
1236 | ||
1237 | static int mmc_spi_get_ro(struct mmc_host *mmc) | |
1238 | { | |
1239 | struct mmc_spi_host *host = mmc_priv(mmc); | |
1240 | ||
1241 | if (host->pdata && host->pdata->get_ro) | |
08f80bb5 AV |
1242 | return !!host->pdata->get_ro(mmc->parent); |
1243 | /* | |
1244 | * Board doesn't support read only detection; let the mmc core | |
1245 | * decide what to do. | |
1246 | */ | |
1247 | return -ENOSYS; | |
15a0580c DB |
1248 | } |
1249 | ||
619ef4b4 AV |
1250 | static int mmc_spi_get_cd(struct mmc_host *mmc) |
1251 | { | |
1252 | struct mmc_spi_host *host = mmc_priv(mmc); | |
1253 | ||
1254 | if (host->pdata && host->pdata->get_cd) | |
1255 | return !!host->pdata->get_cd(mmc->parent); | |
1256 | return -ENOSYS; | |
1257 | } | |
15a0580c DB |
1258 | |
1259 | static const struct mmc_host_ops mmc_spi_ops = { | |
1260 | .request = mmc_spi_request, | |
1261 | .set_ios = mmc_spi_set_ios, | |
1262 | .get_ro = mmc_spi_get_ro, | |
619ef4b4 | 1263 | .get_cd = mmc_spi_get_cd, |
15a0580c DB |
1264 | }; |
1265 | ||
1266 | ||
1267 | /****************************************************************************/ | |
1268 | ||
1269 | /* | |
1270 | * SPI driver implementation | |
1271 | */ | |
1272 | ||
1273 | static irqreturn_t | |
1274 | mmc_spi_detect_irq(int irq, void *mmc) | |
1275 | { | |
1276 | struct mmc_spi_host *host = mmc_priv(mmc); | |
1277 | u16 delay_msec = max(host->pdata->detect_delay, (u16)100); | |
1278 | ||
1279 | mmc_detect_change(mmc, msecs_to_jiffies(delay_msec)); | |
1280 | return IRQ_HANDLED; | |
1281 | } | |
1282 | ||
460cd058 DB |
1283 | struct count_children { |
1284 | unsigned n; | |
1285 | struct bus_type *bus; | |
1286 | }; | |
1287 | ||
1288 | static int maybe_count_child(struct device *dev, void *c) | |
1289 | { | |
1290 | struct count_children *ccp = c; | |
1291 | ||
1292 | if (dev->bus == ccp->bus) { | |
1293 | if (ccp->n) | |
1294 | return -EBUSY; | |
1295 | ccp->n++; | |
1296 | } | |
1297 | return 0; | |
1298 | } | |
1299 | ||
15a0580c DB |
1300 | static int mmc_spi_probe(struct spi_device *spi) |
1301 | { | |
1302 | void *ones; | |
1303 | struct mmc_host *mmc; | |
1304 | struct mmc_spi_host *host; | |
1305 | int status; | |
1306 | ||
1307 | /* MMC and SD specs only seem to care that sampling is on the | |
1308 | * rising edge ... meaning SPI modes 0 or 3. So either SPI mode | |
48881cae WM |
1309 | * should be legit. We'll use mode 0 since the steady state is 0, |
1310 | * which is appropriate for hotplugging, unless the platform data | |
1311 | * specify mode 3 (if hardware is not compatible to mode 0). | |
15a0580c | 1312 | */ |
48881cae WM |
1313 | if (spi->mode != SPI_MODE_3) |
1314 | spi->mode = SPI_MODE_0; | |
15a0580c DB |
1315 | spi->bits_per_word = 8; |
1316 | ||
1317 | status = spi_setup(spi); | |
1318 | if (status < 0) { | |
1319 | dev_dbg(&spi->dev, "needs SPI mode %02x, %d KHz; %d\n", | |
1320 | spi->mode, spi->max_speed_hz / 1000, | |
1321 | status); | |
1322 | return status; | |
1323 | } | |
1324 | ||
460cd058 DB |
1325 | /* We can use the bus safely iff nobody else will interfere with us. |
1326 | * Most commands consist of one SPI message to issue a command, then | |
1327 | * several more to collect its response, then possibly more for data | |
1328 | * transfer. Clocking access to other devices during that period will | |
1329 | * corrupt the command execution. | |
1330 | * | |
1331 | * Until we have software primitives which guarantee non-interference, | |
1332 | * we'll aim for a hardware-level guarantee. | |
1333 | * | |
1334 | * REVISIT we can't guarantee another device won't be added later... | |
15a0580c DB |
1335 | */ |
1336 | if (spi->master->num_chipselect > 1) { | |
460cd058 | 1337 | struct count_children cc; |
15a0580c | 1338 | |
460cd058 DB |
1339 | cc.n = 0; |
1340 | cc.bus = spi->dev.bus; | |
1341 | status = device_for_each_child(spi->dev.parent, &cc, | |
1342 | maybe_count_child); | |
15a0580c DB |
1343 | if (status < 0) { |
1344 | dev_err(&spi->dev, "can't share SPI bus\n"); | |
1345 | return status; | |
1346 | } | |
1347 | ||
460cd058 | 1348 | dev_warn(&spi->dev, "ASSUMING SPI bus stays unshared!\n"); |
15a0580c DB |
1349 | } |
1350 | ||
1351 | /* We need a supply of ones to transmit. This is the only time | |
1352 | * the CPU touches these, so cache coherency isn't a concern. | |
1353 | * | |
1354 | * NOTE if many systems use more than one MMC-over-SPI connector | |
1355 | * it'd save some memory to share this. That's evidently rare. | |
1356 | */ | |
1357 | status = -ENOMEM; | |
1358 | ones = kmalloc(MMC_SPI_BLOCKSIZE, GFP_KERNEL); | |
1359 | if (!ones) | |
1360 | goto nomem; | |
1361 | memset(ones, 0xff, MMC_SPI_BLOCKSIZE); | |
1362 | ||
1363 | mmc = mmc_alloc_host(sizeof(*host), &spi->dev); | |
1364 | if (!mmc) | |
1365 | goto nomem; | |
1366 | ||
1367 | mmc->ops = &mmc_spi_ops; | |
1368 | mmc->max_blk_size = MMC_SPI_BLOCKSIZE; | |
1369 | ||
23af6039 | 1370 | mmc->caps = MMC_CAP_SPI; |
15a0580c DB |
1371 | |
1372 | /* SPI doesn't need the lowspeed device identification thing for | |
1373 | * MMC or SD cards, since it never comes up in open drain mode. | |
1374 | * That's good; some SPI masters can't handle very low speeds! | |
1375 | * | |
1376 | * However, low speed SDIO cards need not handle over 400 KHz; | |
1377 | * that's the only reason not to use a few MHz for f_min (until | |
1378 | * the upper layer reads the target frequency from the CSD). | |
1379 | */ | |
1380 | mmc->f_min = 400000; | |
1381 | mmc->f_max = spi->max_speed_hz; | |
1382 | ||
1383 | host = mmc_priv(mmc); | |
1384 | host->mmc = mmc; | |
1385 | host->spi = spi; | |
1386 | ||
1387 | host->ones = ones; | |
1388 | ||
1389 | /* Platform data is used to hook up things like card sensing | |
1390 | * and power switching gpios. | |
1391 | */ | |
9c43df57 | 1392 | host->pdata = mmc_spi_get_pdata(spi); |
15a0580c DB |
1393 | if (host->pdata) |
1394 | mmc->ocr_avail = host->pdata->ocr_mask; | |
1395 | if (!mmc->ocr_avail) { | |
1396 | dev_warn(&spi->dev, "ASSUMING 3.2-3.4 V slot power\n"); | |
1397 | mmc->ocr_avail = MMC_VDD_32_33|MMC_VDD_33_34; | |
1398 | } | |
1399 | if (host->pdata && host->pdata->setpower) { | |
1400 | host->powerup_msecs = host->pdata->powerup_msecs; | |
1401 | if (!host->powerup_msecs || host->powerup_msecs > 250) | |
1402 | host->powerup_msecs = 250; | |
1403 | } | |
1404 | ||
1405 | dev_set_drvdata(&spi->dev, mmc); | |
1406 | ||
1407 | /* preallocate dma buffers */ | |
1408 | host->data = kmalloc(sizeof(*host->data), GFP_KERNEL); | |
1409 | if (!host->data) | |
1410 | goto fail_nobuf1; | |
1411 | ||
49dce689 TJ |
1412 | if (spi->master->dev.parent->dma_mask) { |
1413 | struct device *dev = spi->master->dev.parent; | |
15a0580c DB |
1414 | |
1415 | host->dma_dev = dev; | |
1416 | host->ones_dma = dma_map_single(dev, ones, | |
1417 | MMC_SPI_BLOCKSIZE, DMA_TO_DEVICE); | |
1418 | host->data_dma = dma_map_single(dev, host->data, | |
1419 | sizeof(*host->data), DMA_BIDIRECTIONAL); | |
1420 | ||
1421 | /* REVISIT in theory those map operations can fail... */ | |
1422 | ||
1423 | dma_sync_single_for_cpu(host->dma_dev, | |
1424 | host->data_dma, sizeof(*host->data), | |
1425 | DMA_BIDIRECTIONAL); | |
1426 | } | |
1427 | ||
1428 | /* setup message for status/busy readback */ | |
1429 | spi_message_init(&host->readback); | |
1430 | host->readback.is_dma_mapped = (host->dma_dev != NULL); | |
1431 | ||
1432 | spi_message_add_tail(&host->status, &host->readback); | |
1433 | host->status.tx_buf = host->ones; | |
1434 | host->status.tx_dma = host->ones_dma; | |
1435 | host->status.rx_buf = &host->data->status; | |
1436 | host->status.rx_dma = host->data_dma + offsetof(struct scratch, status); | |
1437 | host->status.cs_change = 1; | |
1438 | ||
1439 | /* register card detect irq */ | |
1440 | if (host->pdata && host->pdata->init) { | |
1441 | status = host->pdata->init(&spi->dev, mmc_spi_detect_irq, mmc); | |
1442 | if (status != 0) | |
1443 | goto fail_glue_init; | |
1444 | } | |
1445 | ||
619ef4b4 AV |
1446 | /* pass platform capabilities, if any */ |
1447 | if (host->pdata) | |
1448 | mmc->caps |= host->pdata->caps; | |
1449 | ||
15a0580c DB |
1450 | status = mmc_add_host(mmc); |
1451 | if (status != 0) | |
1452 | goto fail_add_host; | |
1453 | ||
619ef4b4 | 1454 | dev_info(&spi->dev, "SD/MMC host %s%s%s%s%s\n", |
d1b26863 | 1455 | dev_name(&mmc->class_dev), |
15a0580c DB |
1456 | host->dma_dev ? "" : ", no DMA", |
1457 | (host->pdata && host->pdata->get_ro) | |
1458 | ? "" : ", no WP", | |
1459 | (host->pdata && host->pdata->setpower) | |
619ef4b4 AV |
1460 | ? "" : ", no poweroff", |
1461 | (mmc->caps & MMC_CAP_NEEDS_POLL) | |
1462 | ? ", cd polling" : ""); | |
15a0580c DB |
1463 | return 0; |
1464 | ||
1465 | fail_add_host: | |
1466 | mmc_remove_host (mmc); | |
1467 | fail_glue_init: | |
1468 | if (host->dma_dev) | |
1469 | dma_unmap_single(host->dma_dev, host->data_dma, | |
1470 | sizeof(*host->data), DMA_BIDIRECTIONAL); | |
1471 | kfree(host->data); | |
1472 | ||
1473 | fail_nobuf1: | |
1474 | mmc_free_host(mmc); | |
9c43df57 | 1475 | mmc_spi_put_pdata(spi); |
15a0580c DB |
1476 | dev_set_drvdata(&spi->dev, NULL); |
1477 | ||
1478 | nomem: | |
1479 | kfree(ones); | |
1480 | return status; | |
1481 | } | |
1482 | ||
1483 | ||
1484 | static int __devexit mmc_spi_remove(struct spi_device *spi) | |
1485 | { | |
1486 | struct mmc_host *mmc = dev_get_drvdata(&spi->dev); | |
1487 | struct mmc_spi_host *host; | |
1488 | ||
1489 | if (mmc) { | |
1490 | host = mmc_priv(mmc); | |
1491 | ||
1492 | /* prevent new mmc_detect_change() calls */ | |
1493 | if (host->pdata && host->pdata->exit) | |
1494 | host->pdata->exit(&spi->dev, mmc); | |
1495 | ||
1496 | mmc_remove_host(mmc); | |
1497 | ||
1498 | if (host->dma_dev) { | |
1499 | dma_unmap_single(host->dma_dev, host->ones_dma, | |
1500 | MMC_SPI_BLOCKSIZE, DMA_TO_DEVICE); | |
1501 | dma_unmap_single(host->dma_dev, host->data_dma, | |
1502 | sizeof(*host->data), DMA_BIDIRECTIONAL); | |
1503 | } | |
1504 | ||
1505 | kfree(host->data); | |
1506 | kfree(host->ones); | |
1507 | ||
1508 | spi->max_speed_hz = mmc->f_max; | |
1509 | mmc_free_host(mmc); | |
9c43df57 | 1510 | mmc_spi_put_pdata(spi); |
15a0580c DB |
1511 | dev_set_drvdata(&spi->dev, NULL); |
1512 | } | |
1513 | return 0; | |
1514 | } | |
1515 | ||
1516 | ||
1517 | static struct spi_driver mmc_spi_driver = { | |
1518 | .driver = { | |
1519 | .name = "mmc_spi", | |
1520 | .bus = &spi_bus_type, | |
1521 | .owner = THIS_MODULE, | |
1522 | }, | |
1523 | .probe = mmc_spi_probe, | |
1524 | .remove = __devexit_p(mmc_spi_remove), | |
1525 | }; | |
1526 | ||
1527 | ||
1528 | static int __init mmc_spi_init(void) | |
1529 | { | |
1530 | return spi_register_driver(&mmc_spi_driver); | |
1531 | } | |
1532 | module_init(mmc_spi_init); | |
1533 | ||
1534 | ||
1535 | static void __exit mmc_spi_exit(void) | |
1536 | { | |
1537 | spi_unregister_driver(&mmc_spi_driver); | |
1538 | } | |
1539 | module_exit(mmc_spi_exit); | |
1540 | ||
1541 | ||
1542 | MODULE_AUTHOR("Mike Lavender, David Brownell, " | |
1543 | "Hans-Peter Nilsson, Jan Nikitenko"); | |
1544 | MODULE_DESCRIPTION("SPI SD/MMC host driver"); | |
1545 | MODULE_LICENSE("GPL"); |